Q67007A9397A702 [INFINEON]
Buffer/Inverter Based Peripheral Driver, 4A, PDSO36, GREEN, PLASTIC, 36 PIN;
| 型号： | Q67007A9397A702 |
| 厂家： | 
Infineon |
| 描述： | Buffer/Inverter Based Peripheral Driver, 4A, PDSO36, GREEN, PLASTIC, 36 PIN 驱动 光电二极管 接口集成电路 |
| 文件： | 总21页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet TLE 6232 GP
Smart Six Channel Low-Side Switch
Features
Product Summary
Short Circuit Protection up to 24 V
Over-temperature Protection
Over-voltage Protection
16 bit Serial Data Input and Diagnostic
Output (2 bit/ch. acc. SPI protocol)
Direct Parallel Control of all six Chan-
nels for PWM Applications
·
·
·
·
Supply voltage
VS
4.5 – 5.5 V
Drain source clamping voltage
On resistance
VDS(AZ)typ.
RON1-4
RON 5,6
ID(NOM)
ID(NOM)
53
V
0.25
0.45
2
W
W
A
·
Output current (Channel 1-4)
(Channel 5,6)
General Fault Flag
Low Quiescent Current
·
·
·
·
·
·
·
1
A
Compatible with 3V Micro Controllers
Electrostatic Discharge (ESD) Protection
Parallel Inputs High or Low Active Programmable
Green Product (RoHS compliant)
AEC qualified
Application
µC Compatible Power Switch for 12 V and 24V Applications
Switch for Automotive and Industrial System
Solenoids, Relays and Resistive Loads
Robotic Controls
·
·
·
·
PG-DSO 36-26
General description
Six Channel Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI)
and six open drain DMOS output stages. The TLE 6232 GP is protected by embedded protection func-
tions and designed for automotive and industrial applications. The output stages are controlled via an
SPI Interface. Additionally all six channels can be controlled direct in parallel for PWM applications.
Therefore the TLE 6232 GP is particularly suitable for engine management and powertrain systems.
Block Diagram
RESET
VS
FAULT
PRG
GND
VS
VBB
IN1
IN6
Protection
Functions
as Ch. 1
as Ch. 1
as Ch. 1
as Ch. 1
as Ch. 1
LOGIC
OUT1
Output Stage
16
1
6
SCLK
SI
6
6
Output Control
Buffer
Serial Interface
SPI
OUT6
CS
SO
GND
V2.1
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1
Data Sheet TLE 6232 GP
Detailed Block Diagram
RESET FAULT
VS
Normal function
GND
VS
SCB/Overload/OT
Open load
PRG
IN1
IN2
short to ground
as Ch.1
as Ch.1
as Ch.1
as Ch.1
as Ch.1
IN3
IN4
IN5
IN6
Output Stage
OUT1
6
16
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
OUT2
OUT3
OUT4
SO
Output
Control
Buffer
6
SI
SPI
Interface
16 bit
SCLK
OUT5
OUT6
CS
GND
V2.1
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2
Data Sheet TLE 6232 GP
Pin Description
Pin Symbol
Pin Configuration (Top view)
Function
GND 1·
36 GND
35 NC
34 NC
1
GND
NC
Ground
NC
OUT5
NC
2
2
not connected
3
4
3
OUT5
NC
Power Output Channel 5
not connected
33
NC
4
OUT1
IN5
IN1
5
6
7
32 OUT4
31 NC
30 IN4
5
OUT1
IN5
Power Output Channel 1
Input Channel 5
Input Channel 1
Supply Voltage
Reset
6
VS
8
29
SI
7
IN1
9
10
28 SCLK
RESET
CS
8
Vs
27
26
SO
9
RESET
CS
PRG 11
IN2 12
IN6 13
OUT2 14
FAULT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Slave Select
25 IN3
24 NC
23 OUT3
PRG
IN2
Program (inputs high or low-active)
Input Channel 2
Input Channel 6
Power Output Channel 2
not connected
IN6
NC
OUT6 16
NC 17
15
22
NC
21 NC
20 NC
19 GND
OUT2
NC
GND 18
OUT6
NC
Power Output Channel 6
not connected
Power SO 36
GND
GND
NC
Ground
Ground
not connected
NC
not connected
NC
not connected
OUT3
NC
Power Output Channel 3
not connected
IN3
Input Channel 3
General Fault Flag
Serial Data Output
Serial Clock
FAULT
SO
SCLK
SI
Serial Data Input
Input Channel 4
not connected
IN4
NC
OUT4
NC
Power Output Channel 4
not connected
NC
not connected
NC
not connected
GND
Ground
Heat Slug internally connected to ground pins
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Data Sheet TLE 6232 GP
Maximum Ratings for Tj = – 40°C to 150°C
Parameter
Symbol
VS
Values
Unit
V
Supply Voltage
-0.3 ... +7
45
Continuous Drain Source Voltage (OUT1...OUT8)
Input Voltage, All Inputs and Data Lines
Operating Temperature Range
VDS
VIN
V
- 0.3 ... + 7
- 40 ... + 150
- 55 ... + 150
ID(lim) min
V
Tj
°C
Storage Temperature Range
Tstg
Output Current per Channel (see el. characteristics)
Single pulse inductive Energy (internal clamping)
ID(lim)
E
A
mJ
T=125°C,
j
Ch1-4: 3A linear decreasing
Ch5,6: 1,5A linear decreasing
40
20
Output Current per Channel @ TA = 25°C
ID 1-4
ID 5,6
Ptot
1.1
0.55
3.3
2000
A
1
)
(All 6 Channels ON; Mounted on PCB )
Power Dissipation (mounted on PCB) @ TA = 25°C
Electrostatic Discharge Voltage (Human Body Model)
W
V
VESD
according to MIL STD 883D, method 3015.7 and EOS/ESD
assn. standard S5.1 - 1993
DIN Humidity Category, DIN 40 040
IEC Climatic Category, DIN IEC 68-1
E
40/150/56
Thermal Resistance
junction – case (die soldered on the frame)
junction - ambient @ min. footprint
RthJC
RthJA
2
50
38
K/W
junction - ambient @ 6 cm2 cooling area with heat pipes
PCB with heat pipes,
backside 6 cm2 cooling area
Minimum footprint
1
)
Output current rating so long as maximum junction temperature is not exceeded. AtTA = 125 °C the output
current has to be calculated usingRthJA according mounting conditions.
V2.1
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Data Sheet TLE 6232 GP
Electrical Characteristics
Parameter and Conditions
Symbol
Values
Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
min
typ
max
1. Power Supply, Reset
Supply Voltage2
4.5
--
--
--
--
--
5.5
10
10
--
VS
V
Supply Current
IS
mA
µA
µs
Supply Current in Standby Mode (RESET = L)
Minimum Reset Duration
IS(stdy)
tReset,min
--
1
2. Power Outputs
ON Resistance VS = 5 V; ID = 1 A
Channel 1-4
TJ = 25°C
TJ = 150°C
TJ = 25°C
TJ = 150°C
RDS(ON)
RDS(ON)
--
--
--
--
0.25 0.28
-- 0.5
0.45 0.55
W
W
ON Resistance VS = 5 V; ID = 500 mA
Channel 5,6
--
1
45
53
60
V
A
Output Clamping Voltage
Current Limit Channel 1-4
Current Limit Channel 5,6
Output OFF
VDS(AZ)
ID(lim) 1-4
ID(lim) 5,6
ID(lkg)
3
4
2
6
3
1.5
Output Leakage Current
VReset = L
--
--
--
5
10
10
µA
µs
Turn-On Time Ch 1-4 ID = 2 A, resistive load
Ch 5,6 ID = 1 A, resistive load
tON
--
5
10
µs
Turn-Off Time
Ch 1-4 ID = 2 A, resistive load
Ch 5,6 ID = 1 A, resistive load
tOFF
1
1
4
4
20
20
V/µs
V/µs
Switch-On Slew Rate (resistive load)
Switch-Off Slew Rate (resistive load)
son
son
3. Digital Inputs
Input Low Voltage
VINL
- 0.3
2.0
100
10
--
1.0
--
V
V
Input High Voltage
VINH
--
Input Voltage Hysteresis
Input Pull Down/Up Current (IN1 ... IN6)
Input Pull Up Current (Reset)
Input Pull Down Current (PRG)
VINHys
IIN(1..6)
IIN(Res)
IIN(PRG)
IIN(SI,SCLK)
200
20
20
20
20
400
50
50
50
50
mV
µA
µA
µA
µA
10
10
Input Pull Up Current (
, SI, SCLK)
10
CS
4. Digital Outputs (SO,
)
FAULT
SO High State Output Voltage
ISOH = -2 mA
ISOL 2 mA
VSOH
VS - 1
--
--
V
SO Low State Output Voltage
=
VSOL
--
--
0
0.4
10
V
µA
V
Output Tri-state Leakage Current CS = H, 0
V
V
£
ISOlkg
-10
--
£
SO
S
FAULT Output Low Voltage
IFAULT = 2 mA
VFAULTL
--
0.4
2 For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely
switched off. This under-voltage reset gets active at VS = 3V (typ. value) and isspecified by design.
V2.1
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Data Sheet TLE 6232 GP
Electrical Characteristics cont.
Parameter and Conditions
Symbol
Values
Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
min
typ
max
(unless otherwise specified)
5. Diagnostic Functions
Open Load Detection Voltage
VDS(OL)
0.52*
Vs
0.6*
Vs
0.68*
Vs
V
V
Short to Ground Detection Voltage
VDS(SHG)
0.32*
Vs
0.4*
Vs
0.48*
Vs
Diagnostic Current (incl. Leakage)
UOUTi,j = 14V
UOUTi,j = 0V
IOUTi,j
325
50
580
130
4
980
250
6
µA
µA
A
-IOUTi,j
ID(lim) 1-4
ID(lim) 5,6
Tth(sd)
Thys
Current Limitation; Overload Threshold Current
3
1.5
170
5
2
3
A
Over-temperature Shutdown Threshold
Hysteresis
--
200
20
°C
K
10
120
Fault Delay Time
td(fault)
60
240
µs
6. SPI-Timing
Serial Clock Frequency (@ C
50pF)
fSCK
DC
200
50
--
--
--
--
--
5
MHz
£
SO
Serial Clock Period (1/fclk)
Serial Clock High Time
Serial Clock Low Time
tp(SCK)
tSCKH
tSCKL
--
--
--
--
ns
ns
ns
ns
100
100
Enable Lead Time (falling edge of CS to rising edge of CLK) tlead
Enable Lag Time (falling edge of CLK to rising edge ofCS )
Data Setup Time (required time SI to falling of CLK)
Data Hold Time (falling edge of CLK to SI)
Disable Time
tlag
tSU
tH
150
20
---
--
--
--
--
--
ns
ns
ns
ns
ns
--
20
--
tDIS
tdt
--
100
--
Transfer Delay Time3
150
(
high time between two accesses)
CS
Data Valid Time4
CL = 50 pF
CL = 100 pF
CL = 150 pF
tvalid
--
--
--
--
--
--
100
120
150
ns
ns
ns
3 This time is necessary between two write accesses. To get the correct diagnostic information, the transfer
delay time has to be extended to the maximum fault delay time td(fault)max = 200µs.
4 This parameter will not be tested but specified by design
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Data Sheet TLE 6232 GP
Description of the Power Stages
4 low side power switches for nominal currents up to 3A (power stages OUT1 to OUT4). Control
is possible by input pins or via SPI. For TJ = 150°C the on-resistance of the power switches is
W
below 500m .
2 low side power switches for nominal currents up to 1.5A (power stages OUT5 and OUT6).
Control is possible by input pins or via SPI. For TJ = 150°C the on-resistance of the power
W
switches is below 1 .
In order to increase the switching current or to reduce the power dissipation parallel connection
of power stages is possible.
Each of the 6 output stages is equipped with its own zener clamp, which limits the output volt-
age to a maximum of 60V. The outputs are provided with a current limitation set to a minimum of
1.5A resp. 3A. Each power stage is equipped with an own temperature sensor.
5)
Each output is protected by embedded protection functions . In case of overload or short-
circuit to UBatt the current is internally limited and the corresponding bit combination is set (early
warning). If this operation leads to an over-temperature condition, a second protection level
(about 170°C) will change the output into a low duty cycle PWM (selective thermal shut-down
with restart) to prevent critical chip temperatures.
The following faults can be detected (individually for each output):
- short to UBatt:
- short to ground: (SCG) can be detected when switches are
- open load: (OL) can be detected when switches are
- over-temperature: (OT) will only be detected when switches are
(SCB/overload) can be detected when switches are
On state
Off state
Off state
On state
The fault conditions SCB, SCG and OL will not be stored until an integrated filtering time is ex-
pired (please note for PWM application). If, at one output, several errors occur in a sequence,
always the last detected error will be stored (with filtering time). All fault conditions are encoded
in two bits per switch and are stored in the corresponding SPI registers. Additionally there are
two central diagnostic bits: one especially for over-temperature (latched result of an OR-
operation out of the 6 signals of the temperature sensor) and one for fault occurrence at any
output. A fault that has been detected and stored in the fault register must not be replaced by
o.k.-state (11) unless it is read out by the RD_DIAG command sent by the microcontroller or an
internal or external reset has been applied. I.e. the fault register will be cleared only by the
RD_DIAG command.
PRG - Program pin.
PRG = High (VS): Parallel inputs Channel 1 to 6 are high active
PRG = Low (GND): Parallel inputs Channel 1 to 6 are low active.
If the parallel input pins are not connected (independent of high or low activity), channels 1 to 6
are switched OFF.
PRG pin itself is internally pulled down when it is not connected.
5) The integrated protection functions prevent device destruction under fault conditions and may not be used in
normal operation or permanently.
V2.1
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Data Sheet TLE 6232 GP
The effect of the integrated under-voltage detection is similar to the effect of an external reset
at pin Reset (except low current consumption):
- locks all power switches regardless of their input signals
- clears the fault registers
- resets SPI control register
Parallel Connection of Power Stages
The power stages which are connected in parallel have to be switched on and off simultane-
ously.
In case of overload the ground current and the power dissipation are increasing. The applica-
tion has to take into account that all maximum ratings are observed (e.g. operating temperature
TJ and total ground current IGND, see Maximal Ratings).
The maximum current limitation value (or overload detection threshold) of the parallel con-
nected power stages is the summation of the corresponding maximum values of the power
stages (IOUT(lim)x + IOUT(lim)y + ....).
Max. Nominal Current
Max. Clamping Energy On Resistance
2 power stages of the
same type
0.8 x (Ex + Ey)
(Imax,OUTx+Imax,OUTy ) x 0.9
0.5xRON,OUTx , y
(see note 1)
3 power stages of the
same type
0.7 x (Ex + Ey + Ez)
(Imax,OUTx+Imax,OUTy
Imax,OUTz) x 0.8
+
0.34xRON,OUTx , y,z
(see note 1,2)
RON,OUTx xRON,OUTy
2 power stages with the
same clamping voltage,
but different nominal
current (see note 3)
Min (Eclpx , Eclpy)
(Imax,OUTx+Imax,OUTy ) x 0.8
+
RON,OUTx RON,OUTy
Note 1: Power stages of the same type have the same nominal current
Note 2: Only for 3A power stages
Note 3: Parallel connection of power stage type 3A/53V with type 1.5A/53V
SPI Interface
The serial SPI interface makes possible communication between TLE6232 and the microcon-
troller.
TLE 6232 GP always works in slave mode whereas the microcontroller provides the master
function. The maximum baud rate is 5MBaud.
Applying a chip select signal at CS and setting bit 7 and bit 6 of the instruction byte to „1“ and
„0“ TLE 6232 GP is selected by the SPI master. SI is the data input (Signal In), SO the data
output
(Signal Out). Via SCLK (Serial Clock Input) the SPI clock is given by the master.
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Data Sheet TLE 6232 GP
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6232 GP by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - diagnostic status information is transferred from the power
outputs into the shift register.
- serial input data can be clocked in from then on
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits
CS Low to High transition: - transfer of SI bits from shift register into output buffers
- reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during high
to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI pins
are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6232GP.
The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while
the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of
serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS
makes any transition. The number of clock pulses will be counted during a chip select cycle.
The received data will only be accepted, if exactly 16 clock pulses were counted during CS is
active.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI informa-
tion is read in on the falling edge of SCLK. Input data is latched in the shift register and then
transferred to the control buffer of the output stages.
The input data consists of two bytes - a "control byte” followed by a "data byte". The control
byte contains the information as to whether the data byte will be accepted or ignored (see di-
agnostics section). The data byte contains the input information for the six channels. A logic
high level at this pin (within the data byte) will switch on the power switch, provided that the cor-
responding parallel input is also switched on (AND-operation for channel 1 to 6).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET
- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
In case of inactive chip select signal (High) or bit 7 and bit 6 of the instruction byte differing
from1“ and „0“ the data output SO remains into tri-state.
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Data Sheet TLE 6232 GP
SPI Interface
Power Stages 1...6
SCON_REG
Power Stages 1...6
MUX_REG
CS
SPI Control:
SCK
State Machine
Clock Counter
Control Bits
SI
Parity Generator
Shift Register
SO
DIA_REG
Power Stages 1...6
SPI Communication
A SPI communication starts with a SPI instruction (SI control word) sent from the controller to
TLE 6232 GP. Simultaneously the device sends the first SO byte back to the µC.
During a writing cycle the controller sends the data after the SPI instruction, beginning with the
MSB. During a reading cycle, after having received the SPI instruction, TLE 6232 GP sends the
corresponding data to the controller, also starting with the MSB.
The SPI Interface consists of three register:
- MUX_REG: 8-bit (1 byte) length for parallel operation mode (IN1 ... IN6 enabled or not)
- SCON_REG: 8-bit (1 byte) length for serial control of the outputs (serial data bits)
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Data Sheet TLE 6232 GP
- DIAG_REG: 16-bit (2 byte) length. Contains the diagnostic information (2 bits per chan-
nel), a common over-temperature bit and a common fault bit.
Registers MUX_REG and SCON_REG are writeable as well as readable from the microcontrol-
ler. The DIAG_REG can only be read from the µC.
This leads to five different control bytes which are recognized by the IC. The following table
shows the different modes.
MSB
LSB MSB
LSB
WR_SCON SI:
H L L H H L X X
OT DIA6 DIA5
Z Z F
H L L H L H X X
D6 D5 D4 D3 D2 D1 X X
DIA4 DIA3 DIA2 DIA1
Write to SCON Register.
Read SCON Register
Write to MUX Register.
Read MUX Register
SO:
RD_SCON
WR_MUX
RD_MUX
RD_DIAG
SI:
SO:
X X X X X X X X
SCON6 .. . SCON1 H H
M6 M5 M4 M3 M2 M1 X X
DIA4 DIA3 DIA2 DIA1
OT DIA6 DIA5
Z Z F
SI:
SO:
H L H L H L X X
Z Z F OT DIA6 DIA5
H L H L L H X X
SI:
SO:
X
X
X
X
X
X
X
X
MUX6 . . MUX1
H H
OT DIA6 DIA5
Z Z F
SI:
X X X X X X X X DIA4
DIA3 DIA2 DIA1
H L L L L L X X
Read DIAG Register
SO
OT DIA6 DIA5
Z Z F
SI Control Byte
SI Data Byte
Note:
’X’ means ’don’t care’, because data will be ignored
’Dx’ represents the serial data bits, either being H (= OFF) or L (= ON)
’Mx’ enables parallel control of channel x H (=parallel) or L (=serial)
’Z’ means tri-state
’F’ is the common fault flag
’OT’ is the common over-temperature flag
’DIAx’ is the 2 bit diagnosis information per channel
All other possible control bytes will lead to an ignorance of the data bits, but the full diagnosis
information (like RD_DIAG command) is provided at the SO line. A reset of all fault registers
(and OT bit) the will only be done if the RD_DIAG command wasclocked in.
Characteristics of the SPI Interface
If the slave select signal at CS is High or bit 7 and bit 6 of the instruction byte differ from „1“
and „0“, the state machine is set on default condition, i.e. the state machine expects an instruc-
tion.
If the 5V-reset (RESET) is active, the SPI output SO is switched intotri-state.
In order to increase the possible number of SPI participants on one and the same CS signal,
bits 7 and 6 of the instruction byte are fixed as shown above. While receiving thefirst two bits of
the instruction byte the data output SO has to be in tri-state. After having received the first two
bits TLE6232 has to decide if it is addressed (bit 7 = high, bit 6 = low).In this case the remain-
ing 6 bits of the instruction byte and the data byte are accepted and the diagnostic feedback
respectively the data byte content (MUX, SCON) is sent to the microcontroller.Otherwise in-
struction and data bits are rejected and SO remains in tri-state.
On a reading access the bit pattern of the data byte at the SPI input SI will be ignored. The first
SO byte sent out simultaneously by the TLE 6232 GP always contains the common fault bit, the
over-temperature bit and the diagnostic information of channels 6 and 5 (2 bits each). Depend-
ing on the SI control byte, the second SO byte contains the requested information.
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Data Sheet TLE 6232 GP
- Read back of SCON_REG (SCON bits 6 to 1 and two high bits)
- Read back of MUX_REG (MUX information for channel 6 to 1 and two high bits)
- Diagnostic information of channel 4 to 1 (2 bits per channel)
On a writing access always the full diagnostic information of the 6 channels (2 bit per channel)
and the over-temperature and common fault bit is performed.
Invalid instruction/access:
An instruction is invalid, if the following condition is fulfilled:
- an unused instruction code is detected (see tables with SPI instructions).
If an invalid instruction is detected, a writing access on a register of TLE6232 GP is not allow-
wed. In addition an access is invalid if the number of SPI clock pulses counted during active CS
differs from exactly 16 clock pulses (falling edges are counted).
- On a writing access the received data is only taken over into the internal registers and
- the fault register is only cleared by the RD_DIAG command,
if exactly 16 SPI clock pulses were counted while CS active.
Writing access / 8 bit+ 8 bit resp.
SS
SPI Instruction
Data/8 Bit
SI
1
0
-
-
-
-
-
-
MSB
MSB
SO
DIA4 DIA3 DIA2 DIA1
Z
Z
F
OT DIA6 DIA5
MSB
Reading access / 8 bit + 8 bit
SS
SPI Instruction
SI
1
0
XXXX XXXX
-
-
-
-
-
-
MSB
SO
Data/8 Bit
Z
Z
F OT DIA6 DIA5
MSB
MSB
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Data Sheet TLE 6232 GP
Serial/Parallel Control of the Power Stages 1...6
(SPI-Instructions: WR_MUX, RD_MUX, WR_SCON, RD_SCON)
The following table shows the truth table for the control of the power stages 1...6. The register
MUX_REG prescribes parallel or serial control of the power stages.The register SCON_REG
prescribes the state of the power stage in case of serial control.
RST
0
1
1
1
1
1
1
PRG
X
X
X
0
0
1
1
INx
X
X
X
0
1
0
1
MUXx SCONx Output OUTx of Power Stage x, x = 1..6
X
0
0
1
1
1
1
X
0
1
X
X
X
X
OUTx off
Serial Control: OUTx on
Serial Control: OUTx off
Parallel Control: OUTx on
Parallel Control: OUTx off
Parallel Control: OUTx off
Parallel Control: OUTx on
Note: Serial Data bits are low active. Parallel Inputs are high or low active depending on the PRG pin.
Description of the SPI Registers
Register:
7
MUX6
State of
Reset:
MUX_REG
6
MUX5
FFH
5
4
3
2
1
1
0
1
MUX4
MUX3
MUX2
MUX1
Access by Read/Write
Controller:
Bit
7
6
5
4
3
2
1-0
Name
MUX6
MUX5
MUX4
MUX3
MUX2
MUX1
Description
Serial or parallel control of power stage 6
Serial or parallel control of power stage 5
Serial or parallel control of power stage 4
Serial or parallel control of power stage 3
Serial or parallel control of power stage 2
Serial or parallel control of power stage 1
No function: HIGH on reading
Register:
7
SCON6
State of
Reset:
SCON_REG
6
SCON5
FFH
5
4
3
2
1
1
0
1
SCON4
SCON3
SCON2
SCON1
Access by Read/Write
Controller:
Bit
7
6
5
4
3
2
1-0
Name
Description
SCON6
SCON5
SCON4
SCON3
SCON2
SCON1
State of serial control of power stage 6
State of serial control of power stage 5
State of serial control of power stage 4
State of serial control of power stage 3
State of serial control of power stage 2
State of serial control of power stage 1
No function: HIGH on reading
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Data Sheet TLE 6232 GP
Diagnostics/Encoding of Failures
Description of the SPI Registers
(SPI Instructions: RD_DIAG)
Register:
7
DIAG_REG1
6
ST6
5
ST5
4
ST4
3
ST3
2
ST2
1
ST1
0
ST0
ST7
State of
Reset:
FFH
Access by Read only
Controller:
Bit
Name
DIA4
DIA3
DIA2
DIA1
Description
7-6
5-4
3-2
1-0
Diagnostic Bits of power stage 4
Diagnostic Bits of power stage 3
Diagnostic Bits of power stage 2
Diagnostic Bits of power stage 1
Note:
This byte is always clocked out (second SO-byte), except the SI control words says:
RD_SCON or RD_MUX. But: The content of the fault register will only be deleted if the control command
’RD_DIAG’ was clocked in and 16 clock pulses were counted.
Register:
7
DIA_REG2
6
Z
5
F
4
OT
3
2
1
ST9
0
ST8
Z
ST11
ST10
State of
Reset:
FFH
Access by Read only
Controller:
Bit
7-6
5
Name
Z
F
Description
Bit 7 and 6 are always tri-state
Common error flag
4
3-2
1-0
OT
DIA6
DIA5
Common over-temperature flag
Diagnostic Bits of power stage 6
Diagnostic Bits of power stage 5
Encoding of the Diagnostic (Status) Bits of the Power Stages
ST(2*x-1)
ST(2*x-2)
1
0
1
0
State of power stage x
Power stage o.k.
Overload, short circuit to battery (SCB) or over-temperature (OT)
Open load (OL)
x = 1..6
1
1
0
0
Short circuit to ground (SCG)
Note: DIA_REG2 is always clocked out as first byte
F, OT Bit = 1: No Fault
F, OT Bit = 0: Fault, Over-temperature
The over-temperature bit is the latched result of an OR-operation out of the 6 signals of the
temperature sensor)
The general fault bit shows the fault occurrence at any of the outputs.
Reset of the Diagnostic Information
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Data Sheet TLE 6232 GP
The diagnostic information will only be reset after the RD_DIAG command on the rising edge of
slave select or a reset signal is applied (RESET = low).
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Data Sheet TLE 6232 GP
Timing Diagrams
CS
SCLK
C
MSB
15
O
N
T
R
O
L
Byte
8
7
6
5
5
4
3
2
1
0
SI
14
13
12
11
10
9
7
6
4
3
2
1
0
SO
Figure 2: Serial Interface
Figure 3: Input Timing Diagram
CS
0.7VS
tdt
0.2 VS
tlag
trSI
tSCKH
S
tlead
0.7V
SCLK
SI
S
0.2V
tSCKL
tH
tfSI
tSU
0.7VS
S
0.2V
Figure 4:
0.7 VS
CS
0.2 VS
SCLK
valid
t
Dis
t
0.7 VS
SO
SO
SO
S
0.2 V
S
0.7 V
0.2 VS
SO Valid Time Waveforms
Enable and Disable Time Waveforms
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Data Sheet TLE 6232 GP
VIN
t
tOFF
tON
VDS
80%
20%
t
Figure 5: Power Outputs
Timing is valid for resistive load with parallel and serial control.
Rising edge of chip select initiates the switching
Application Circuits
VBB
C
VS = 5V
10k
VS
PRG
OUT1
OUT2
FAULT
RESET
IN1
µC
e.g. C167
TLE
6232 GP
IN6
SI
MTSR
SO
OUT6
MRST
CLK
P xy
CLK
CS
GND
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Data Sheet TLE 6232 GP
Parallel SPI Configuration
Engine Management Application
TLE 6232 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose
loads and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the
numerous loads to be driven in a modern Engine Management/Powertrain system. From 26
channels in sum 18 can be controlled direct in parallel for PWM applications.
Injector 1
4
P x.1-4
4 PWM
Channels
Injector 2
MTSR
MRST
SI
Injector 3
Injector 4
TLE
6220 GP
Quad
SO
CLK
CLK
P x.y
CS
CS
4
6 PWM
Channels
P x.1-6
µC
SI
TLE
6232 GP
Hex
SO
C167
CLK
CS
P x.y
8
8 PWM
Channels
P x.1-8
SI
TLE
SO
6240 GP
16-fold
CLK
CS
P x.y
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Data Sheet TLE 6232 GP
Package and Ordering Code
(All dimensions in mm)
Ordering Code
PG-DSO 36-26
TLE 6232 GP
Q67007A9397A702
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-
Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-
020).
V2.1
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Data Sheet TLE 6232 GP
Revision History
Version
V2.0 ->
V2.1
Date
Changes
Ordering Code / Q-Nr. removed
V2.0 ->
V2.1
05.04.2007
Layout Changes, correct green package name implemented P-DSO-36-
12 à PG-DSO-36-26
V1.2 ->
V2.0
V2.0
05.03.2007
05.03.2007
Green Date sheet Version created
Changes to Green Product Version:
-
-
-
-
AEC, RoHS Logo and Feature List content added
Package Name P-DSO -> PG-DSO
Change History added
Disclaimer re-newed
V1.2
08. Oct. 2003
Initial Version of “grey” product
V2.1
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20
Data Sheet TLE 6232 GP
Edition 2007-04-17
Published by
Infineon Technologies AG
81726 Munich, Germany
© 5/4/07 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or charac-
teristics. With respect to any examples or hints given herein, any typical values stated herein and/or any infor-
mation regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property
rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types
in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express writ-
ten approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause
the failure of that life-support device or system or to affect the safety or effectiveness of that device or system.
Life support devices or systems are intended to be implanted in the human body or to support and/or maintain
and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
V2.1
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