Q67100-Q2004 [INFINEON]
1M x 72-Bit Dynamic RAM Module; 1M X 72位动态RAM模块型号: | Q67100-Q2004 |
厂家: | Infineon |
描述: | 1M x 72-Bit Dynamic RAM Module |
文件: | 总11页 (文件大小:86K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1M × 72-Bit Dynamic RAM Module
(ECC - Module)
HYM 721000GS-60/-70
HYM 721010GS-60/-70
Advanced Information
• 1 048 576 words by 72-bit ECC - mode organization
• Fast access and cycle time
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
• Fast page mode capability with
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
max. 10890 mW active (-60 version)
max. 9900 mW active (-70 version)
CMOS – 451 mW standby
TTL
– 550 mW standby
• CAS-before-RAS refresh, RAS-only-refresh
• 18 decoupling capacitors mounted on substrate
• All inputs, outputs and clock fully TTL compatible
• 4 Byte interleave enabled, Dual Address inputs (A0/B0)
• Buffered inputs excepts RAS and DQ
• 168 pin, dual read-out, Single in-Line Memory Module
• Utilizes eighteen 1M × 4 -DRAMs in TSOPII-packages
and four BiCMOS 8-bit buffers/line drivers 74ABT244
• Two versions: HYM 721000GS with TSOPII-components (4.06 mm module thickness)
HYM 721010GS with SOJ-components (8.89 mm module thickness)
• 1024 refresh cycles / 16 ms
• Gold contact pad
• double sided module with 25.35 mm (1000 mil) height
Semiconductor Group
1
12.95
HYM721000/10GS-60/-70
1M x 72 ECC- Module
The HYM 721000GS-60/-70 is a 8 MByte DRAM module organized as 1 048 576 words by 72-bit in
a 168-pin, dual read-out, single-in-line package comprising eighteen HYB 514400BT 1M × 4
DRAMs in 300 mil wide TSOPII - packages mounted together with eighteen 0.2 µF ceramic
decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using four
BiCMOS 8-bit buffers/line drivers.
Each HYB 514400BT is described in the data sheet and is fully electrically tested and processed
according to Siemens standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The density and speed of the module can be detected by the use of presence detect pins.
Ordering Information
Type
Ordering Code
Q67100-Q2004
on request
Package
Descriptions
HYM 721000GS-60
HYM 721000GS-70
HYM 721010GS-60
HYM 721010GS-70
L-DIM-168-2
L-DIM-168-2
L-DIM-168-2
L-DIM-168-2
60ns DRAM module
70ns DRAM module
60ns DRAM module
70ns DRAM module
on request
on request
Pin Names
A0-A9,B0
Address Input
DQ0 - DQ71
RAS0, RAS2
CAS0 , CAS2
WE0, WE2
OE0, OE2
Vcc
Data Input/Output
Row Address Strobe
Column Address Strobe
Read / Write Input
Output Enable
Power (+5 Volt)
Vss
Ground
PD1 - PD8
PDE
Presence Detect Pins
Presence Detect Enable
ID indentification bit
No Connection
ID0 , ID1
N.C.
Presence-Detect and ID-pin Truth Table:
Module
ID0
ID1
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
HYM 721000/10GS-60
HYM 721000/10GS-70
Vss Vss
Vss Vss
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
Note: 1 = High Level ( Driver Output) , 0 = Low Level (Driver Output) for PDE active ( ground) . For PDE at a high
level all PD terminal are in tri-state.
Semiconductor Group
2
HYM721000/10GS-60/-70
1M x 72 ECC- Module
Pin Configuration
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
1
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
DQ16
DQ17
VSS
NC
43
VSS
85
VSS
127
VSS
2
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
OE2
86
DQ36
DQ37
DQ38
DQ39
VCC
DQ40
DQ41
DQ42
DQ43
DQ44
VSS
DQ45
DQ46
DQ47
DQ48
DQ49
VCC
DQ50
DQ51
DQ52
DQ53
VSS
NC
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NC
3
RAS2
CAS4
NC
87
NC
4
88
NC
5
89
NC
6
WE2
VCC
NC
90
PDE
VCC
NC
7
91
8
92
9
NC
93
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ18
DQ19
VSS
94
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
NC
95
96
DQ20
DQ21
DQ22
DQ23
VCC
DQ24
NC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
NC
NC
NC
NC
NC
NC
DQ25
DQ26
DQ27
VSS
DQ61
DQ62
DQ63
VSS
DQ64
DQ65
DQ66
DQ67
VCC
DQ68
DQ69
DQ70
DQ71
VSS
PD2
NC
NC
VCC
WE0
CAS0
NC
VCC
NC
DQ28
DQ29
DQ30
DQ31
VCC
DQ32
DQ33
DQ34
DQ35
VSS
NC
NC
RAS0
OE0
VSS
A0
NC
NC
VSS
A1
A2
A3
A4
A5
A6
A7
A8
PD1
A9
NC
PD3
NC
PD4
NC
PD5
NC
PD6
VCC
NC
PD7
VCC
NC
PD8
ID0 (VSS)
VCC
ID1 (VSS)
VCC
NC
B0
Semiconductor Group
3
HYM721000/10GS-60/-70
1M x 72 ECC- Module
RAS0
CAS0
RAS2
CAS4
WE0
OE0
WE2
OE2
DQ0-DQ3
I/O1-I/O4
I/O1-I/O4
I/O1-I/O4
I/O1-I/O4
I/O1-I/O4
I/O1-I/O4
I/O1-I/O4
I/O1-I/O4
I/O1-I/O4
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ64-DQ67
DQ68-DQ71
I/O1-I/O4
D9
D0
D1
D2
D3
D4
D5
D6
D7
D8
DQ4-DQ7
I/O1-I/O4
D10
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ32-DQ35
I/O1-I/O4
D11
I/O1-I/O4
D12
I/O1-I/O4
D13
I/O1-I/O4
D14
I/O1-I/O4
D15
I/O1-I/O4
D16
I/O1-I/O4
D17
A0
Vcc
Vss
D0 - D8
D0-D17, buffers
B0
D9 - D17
D0 - D17
A1-A9
PDE
Vcc or Vss
PD1-PD8
Block Diagram
Semiconductor Group
4
HYM721000/10GS-60/-70
1M x 72 ECC- Module
Absolute Maximum Ratings
Operating temperature range .........................................................................................0 to + 70 °C
Storage temperature range......................................................................................– 55 to + 125 °C
Input/output voltage ........................................................................................................ – 1 to + 7 V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................ 13,86 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics 1)
TA = 0 to 70 °C; VCC = 5 V ± 10 %
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
5.5
0.8
–
Input high voltage
VIH
VIL
2.4
– 1.0
2.4
–
V
–
Input low voltage
V
–
–
–
–
Output high voltage (IOUT = – 5 mA)
Output low voltage (IOUT = 4.2 mA)
VOH
VOL
II(L)
V
0.4
10
V
Input leakage current
– 10
µA
(0 V < VIN < 6.5 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < 5.5 V)
IO(L)
ICC1
– 10
10
µA
–
Average VCC supply current:
HYM 721000/10GS-60
HYM 721000/10GS-70
2), 3)
–
–
1980
1800
mA
mA
(RAS, CAS, address cycling, tRC = tRC min.)
Standby VCC supply current
(RAS = CAS = VIH)
ICC2
ICC3
–
50
mA
–
Average VCC supply current during RAS
only refresh cycles:
2)
HYM 721000/10GS-60
HYM 721000/10GS-70
–
–
1980
1800
mA
mA
(RAS cycling, CAS = VIH , tRC = tRC min.)
Semiconductor Group
5
HYM721000/10GS-60/-70
1M x 72 ECC- Module
DC Characteristics (cont’d) 1)
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Average VCC supply current during fast
page mode:
ICC4
2), 3)
HYM 721000/10GS-60
HYM 721000/10GS-70
–
–
–
1260
1260
mA
mA
(RAS = VIL, CAS, address cycling
tPC = tPC min.)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
ICC6
–
30
mA
–
Average VCC supply current during
CAS-before-RAS refresh mode:
1)
HYM 721000/10GS-60
HYM 721000/10GS-70
–
–
1980
1800
mA
mA
(RAS, CAS cycling, tRC = tRC min.)
Capacitance
TA = 0 to 70 °C; VCC = 5 V ± 10 %; f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
10
Input capacitance (A0 to A9,B0)
Input capacitance (RAS0, RAS2)
Input capacitance (CAS0-CAS7)
Input capacitance (WE0,WE2,OE0,OE2)
I/O capacitance (DQ0-DQ71)
CI1
CI2
CI3
CI4
CIO1
–
–
–
–
–
pF
pF
pF
pF
pF
50
15
15
15
Semiconductor Group
6
HYM721000/10GS-60/-70
1M x 72 ECC- Module
AC Characteristics (note: 5,6,7,8)
TA = 0 to 70 °C,VCC = 5.0 ± 10 %
Parameter
Symbol
-60
max. min.
-70
max.
Unit Note
min.
common parameters
Random read or write cycle time
RAS precharge time
tRC
110
40
60
15
10
5
–
130
50
–
ns
ns
ns
ns
ns
tRP
–
–
RAS pulse width
tRAS
tCAS
tCP
100k 70
100k 20
100k
100k
–
CAS pulse width
CAS precharge time
–
10
5
9
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
–
–
ns
ns
ns
ns
10
11
9
8
–
8
–
2
–
2
–
15
18
13
20
58
10
3
–
20
18
13
25
68
10
3
–
12
40
25
–
45
30
–
ns
ns
ns
ns
ns
ms
12
9
10
9
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
7
30
16
30
16
tREF
–
–
Read Cycle
13,14
Access time from RAS
Access time from CAS
Access time from column address
OE access time
tRAC
tCAC
tAA
–
60
20
35
20
–
–
70
25
40
25
–
ns
ns
ns
ns
ns
ns
ns
ns
9,13,14
9,13, 15
–
–
–
–
9,13
9
tOEA
tRAL
tRCS
tRCH
–
–
Column address to RAS lead time
Read command setup time
Read command hold time
35
2
40
2
11
–
–
11,16
16
2
–
2
–
Read command hold time referenced tRRH
0
–
0
–
to RAS
11,13
9,17
9,17
CAS to output in low-Z
tCLZ
tOFF
tOEZ
2
–
–
–
2
–
–
–
ns
ns
ns
Output buffer turn-off delay
Output buffer turn-off delay from OE
20
20
25
25
Semiconductor Group
7
HYM721000/10GS-60/-70
1M x 72 ECC- Module
AC Characteristics (cont’d)(note: 5,6,7,8)
TA = 0 to 70 °C,VCC = 5.0 ± 10 %
Parameter
Symbol
-60
max. min.
-70
max.
Unit Note
min.
0
18
CAS delay time from Din
Data to OE low delay
CAS high to data delay
OE high to data delay
tDZC
tDZO
tCDD
tODD
–
0
–
–
–
–
ns
ns
ns
ns
18
0
–
–
–
0
9,19
9,19
20
20
25
25
Write Cycle
9
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
15
10
2
–
–
–
–
–
–
–
15
10
2
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
11,20
9
tWCS
tRWL
tCWL
tDS
20
15
-2
25
20
-2
10,21
9,21
Data hold time
tDH
15
20
Read-Modify-Write Cycle
Read-write cycle time
9
tRWC
tRWD
tCWD
tAWD
tOEH
155
82
–
–
–
–
–
185
97
–
–
–
–
–
ns
ns
ns
ns
ns
11,21
11,21
11,21
10
RAS to WE delay time
CAS to WE delay time
37
47
Column address to WE delay time
OE command hold time
52
62
13
18
Fast Page Mode Cycle
Fast page mode cycle time
Access time from CAS precharge
RAS pulse width
tPC
40
–
–
45
–
–
ns
ns
ns
ns
9,13
9
tCPA
tRAS
tRHCP
40
45
200k
–
60
40
200k 70
– 45
CAS precharge to RAS Delay
Semiconductor Group
8
HYM721000/10GS-60/-70
1M x 72 ECC- Module
AC Characteristics (cont’d)(note: 5,6,7,8)
TA = 0 to 70 °C,VCC = 5.0 ± 10 %
Parameter
Symbol
-60
max. min.
-70
max.
Unit Note
min.
Fast Page Mode Read-Modify-Write Cycle
11
Fast page mode read-write cycle time tPRWC
82
57
–
97
67
–
–
ns
ns
11,21
CAS precharge to WE
tCPWD
–
CAS-before-RAS Refresh Cycle
CAS setup time
11
tCSR
tCHR
tRPC
tWRP
tWRH
12
8
–
–
–
–
–
12
8
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
10
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
5
5
12
8
12
8
11
10
Presence Detect Read Cycle
PDE to valid presence detect data
tPD
–
0
10
10
ns
ns
PDE inactive to presence detects
inactive
tPDOFF
Semiconductor Group
9
HYM721000/10GS-60/-70
1M x 72 ECC- Module
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (CAS, WE, OE,
addresses) maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are
not buffered, which preserves the DRAMs access specification of 50ns and 60ns.
9) A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers.
10) A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
11) A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
12) A -2ns (min.) and a -5ns (max.) timing skew from the DRAM to the module resulted from the addition of line
drivers.
13) Measured with the specified current load and 100 pF at Voh = 2.4 V and Vol = 0.4 V.
14) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
15) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
16) Either tRCH or tRRH must be satisfied for a read cycle.
17) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
18) Either tDZC or tDZO must be satisfied.
19) Either tCDD or tODD must be satisfied.
20) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
21) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-
Modify-Write cycles.
Semiconductor Group
10
HYM721000/10GS-60/-70
1M x 72 ECC- Module
L-DIM-168-2
Module package
(dual read-out, single in-line memory module)
GLD05861
Semiconductor Group
11
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