S6E1C11B0AGN20000_技术文档

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Continuity of ordering part numbers

Infineon continues to support existing part numbers. Please continue to use the

ordering part numbers listed in the datasheet for ordering.

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The following document contains information on Cypress products. The document has the

ordering part numbering with the prefix “S”. Cypress will offer these products to new and existing

customers with the updated ordering part number (updated last digit).

How to Check the Ordering Part Number

1. Go to www.cypress.com/pcn.

2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click

Apply.

3. Click the corresponding title from the search results.

4. Download the Affected Parts List file, which has details of all changes

For More Information

Please contact your local sales office for additional information about Cypress products and

solutions.

About Cypress

Cypress is the leader in advanced embedded system solutions for the world's most innovative

automotive, industrial, smart home appliances, consumer electronics and medical products.

Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,

high-performance memories help engineers design differentiated products and get them to market

first. Cypress is committed to providing customers with the best support and development

resources on the planet enabling them to disrupt markets by creating new product categories in

record time. To learn more, go to www.cypress.com.

S6E1C Series

32-bit ARM^®Cortex^®-M0+

FM0+ Microcontroller

The FM0+ family of Flexible Microcontrollers is the industry’s most energy-efficient 32-bit ARM^®Cortex^®-M0+ based MCUs. This

family of MCUs is designed for ultra-low-power and cost-sensitive applications such as white goods, sensors, meters, HMI systems,

power tools and Internet of Things (IoT) battery-powered or wearable devices.

This family of ultra-low-power MCUs features an industry-leading 35 µA/CoreMark^®score and 40µA/MHz Active Power

consumption.

The S6E1C Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power

consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of

peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I²C, I²S, Smart Card, and USB).

The products which are described in this data sheet are placed into TYPE3-M0+ product categories in "FM0+ Family Peripheral

Manual".

Features

Ultra Low Power MCU Subsystem

Analog Subsystem

40 MHz ARM Cortex-M0+ CPU with 1.65 V to 3.6 V

1x 12-bit, 1-Msps ADCs with an 8-channel multiplexer input

1% high precision internal oscillator

operating voltage

Maximum operating frequency: 40.8 MHz

Package Options

32-/48-/64-pin LQFP

32-/48-/64-pin QFN

30-pin WLCSP

Nested Vectored Interrupt Controller (NVIC): 1 non-maskable

interrupt (NMI) and 24 peripheral interrupt with 4 selectable

interrupt priority levels

24-bit System timer (Sys Tick): System timer for OS task

management

Up to 128 KB Flash, 16 KB SRAM

Low-Power Consumption Modes

Descriptor System Transfer Controller (DSTC)

Industry's most efficient 35 µA/CoreMark Score

This series has six low-power consumption modes:

 Sleep

 Timer

 RTC

 Stop

 Ultra-low-power consumption: Active – 40 µA/MHz and

Standby – 0.6 µA

Fast wake-up from standby mode (execute from Flash):

20 µs (Typ)

 Deep standby RTC (selectable between keeping the value

of RAM and not)

 Deep standby Stop (selectable between keeping the value

of RAM and not)

Digital Subsystem

Up to 8x Base Timers

1x Dual Timer, 1x Watch Counter

Up to 6x Multi-Function Serial (MFS) interfaces configurable

as SPI, UART, I²C

Up to 1x USB, up to 2x I²S, up to 2x HDMI-CEC, up to 1x

Smart Card interfaces

Cypress Semiconductor Corporation

Document Number: 002-00233 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 13, 2017

S6E1C Series

Ecosystem for Cypress FM0+ MCUs

Cypress provides a wealth of data at www.cypress.com to help you to select the right MCU for your design, and to help you to

quickly and effectively integrate the device into your design. Following is an abbreviated list for FM0+ MCUs:

 Overview: Product Portfolio, Product Roadmap

 AN205411 – FM0+ IEC60730 Class B Self-Test Library :

This document covers how to use and implement the

 Product Selectors: FM0+ MCUs

 Application notes: Cypress offers a large number of FM0+

application notes covering a broad range of topics, from

basic to advanced level. Recommended application notes

for getting started with FM0+ family of MCUs are:

library functions provided. It will first show the requirement

of IEC60730 Class B, and then explain how it can be

implemented. At last an example is given to show how to

integrate test functions into a real system.

 AN210985 – FM0+ Getting Started with FM0+

 AN202487 - Differences Among FM0+, FM3, and FM4

32-Bit Microcontrollers: Highlights the peripheral

differences in Cypress’s FM family MCUs. It provides

dedicated sections for each peripheral and contains lists,

tables, and descriptions of peripheral feature and register

differences.

Development: AN210985 introduces you to the FM0+

family of 32-bit general-purpose microcontrollers. The

FM0+ family is based on the ARM® Cortex®-M0+

processor core, ideal for ultra-low-power designs. This

note provides an overview of hardware features and

capabilities, firmware development, and the multitude of

technical resources available to you. This application note

uses the FM0+ S6E1B8-Series Starter Kit as an example.

 AN204438 - How to Setup Flash Security for FM0+, FM3

and FM4 Families: This application note describes how to

setup the Flash Security for FM0+, FM3, and FM4 devices

 AN203277 - FM 32-Bit Microcontroller Family Hardware

Design Considerations: This application note reviews

several topics for designing a hardware system around

FM0+, FM3, and FM4 family MCUs. Subjects include

power system, reset, crystal, and other pin connections,

and programming and debugging interfaces.

 Development kits:

 FM0-V48-S6E1A1 ARM® Cortex®-M0+ FM0+ MCU

Evaluation Board

 FM0-64L-S6E1C3 - ARM® Cortex®-M0+ MCU Starter Kit

with USB and Digital Audio Interface

 Peripheral Manuals

Document Number: 002-00233 Rev. *D

Page 2 of 109

S6E1C Series

11.9.2 Return Factor: Reset ................................................94

12. Ordering Information...................................................96

13. Acronyms.....................................................................97

14. Package Dimensions...................................................99

15. Errata..........................................................................106

15.1 Part Numbers Affected ..........................................106

15.2 Qualification Status................................................106

15.3 Errata Summary.....................................................106

Document History...........................................................108

Sales, Solutions, and Legal Information.......................109

Table of Contents

Features...............................................................................1

1. Block Diagram...............................................................4

2. Product Lineup..............................................................5

2.1

2.2

Package Dependent Features...................................6

Packages...................................................................6

3. Product Features in Detail............................................7

4. Pin Assignment...........................................................10

5. List of Pin Functions...................................................17

6. I/O Circuit Type............................................................26

7. Handling Precautions .................................................31

7.1

7.2

7.3

Precautions for Product Design...............................31

Precautions for Package Mounting..........................32

Precautions for Use Environment............................34

8. Handling Devices ........................................................35

9. Memory Map ................................................................38

10. Pin Status in Each CPU State ....................................41

11. Electrical Characteristics ...........................................44

11.1 Absolute Maximum Ratings.....................................44

11.2 Recommended Operating Conditions......................45

11.3 DC Characteristics...................................................46

11.3.1 Current Rating..........................................................46

11.3.2 Pin Characteristics ...................................................51

11.4 AC Characteristics...................................................52

11.4.1 Main Clock Input Characteristics..............................52

11.4.2 Sub Clock Input Characteristics ...............................53

11.4.3 Built-in CR Oscillation Characteristics......................54

11.4.4 Operating Conditions of Main PLL (In the Case of

Using the Main Clock as the Input Clock of the PLL)55

11.4.5 Operating Conditions of Main PLL (In the Case of

Using the Built-in High-Speed CR Clock as the Input

Clock of the Main PLL).............................................55

11.4.6 Reset Input Characteristics ......................................56

11.4.7 Power-on Reset Timing............................................56

11.4.8 Base Timer Input Timing..........................................57

11.4.9 CSIO/SPI/UART Timing...........................................58

11.4.10 External Input Timing............................................75

11.4.11 I²C Timing.............................................................76

11.4.12 I²S Timing (MFS-I2S Timing)................................77

11.4.13 Smart Card Interface Characteristics....................79

11.4.14 SW-DP Timing......................................................80

11.5 12-bit A/D Converter................................................81

11.6 USB Characteristics ................................................84

11.7 Low-Voltage Detection Characteristics....................89

11.7.1 Low-Voltage Detection Reset...................................89

11.7.2 Low-Voltage Detection Interrupt...............................90

11.8 Flash Memory Write/Erase Characteristics .............91

11.9 Return Time from Low-Power Consumption Mode..92

11.9.1 Return Factor: Interrupt/WKUP ................................92

Document Number: 002-00233 Rev. *D

Page 3 of 109

S6E1C Series

1. Block Diagram

SWCLK

SWDIO

SW-DP

Fast

GPIO

On-Chip SRAM

12/16Kbyte

Cortex-M0+Core

NVIC

MTB

Bit Band

Wrapper

On-Chip FLASH

64/128Kbyte

Flash I/F

Security

System ROM table

Dual-Timer

WatchDog Timer

(Software)

INITX

Clock Reset

Generator

WatchDog Timer

(Hardware)

DSTC

64ch.

WatchDog Timer

(CVS)

Source Clock

X0

X1

Main

Osc

Sub

Osc

UDP0,

UDM0

PLL

PHY

USB2.0

(Host/Device)

CR

8MHz

CR

100KHz

X0A

X1A

UHCONX0

CROUT

Power-On

LVD Ctrl

LVD

AVRH

AVRL

12-bit A/D Converter

C

Regulator

IRQ-Monitor

Watch Counter

Real-Time Clock

ANxx

Unit 0

ADTG

Base Timer

16-bit 8 ch.

32-bit 4 ch.

TIOAx

TIOBx

RTCCO

External Interrupt

Controller

INTx

12 pin(Max) + NMI

NMIX

MD0,

MD1

CRC Accelarator

MODE-Ctrl

Low-Speed CR

Peripheral Clock

Gating

P0x,

P1x,

PIN-Function-Ctrl

GPIO

:

PEx

SCKx

SINx

SOTx

SCSx

Multi-function Serial

I/F

MI2SCKx

MI2SDIx

6 ch. (Max)

MI2SDOx

MI2SMCKx

MI2SWSx

IC1_CLKx

IC1_VCCx

IC1_VPENx

Smart Card I/F

WKUPx

Deep Standby Ctrl

IC1_CINx

IC1_DATAx

Document Number: 002-00233 Rev. *D

Page 4 of 109

S6E1C Series

2. Product Lineup

Memory Size

Product name

S6E1C11

S6E1C31

S6E1C12

S6E1C32

On-chip Flash memory

On-chip SRAM

64 Kbytes

12 Kbytes

128 Kbytes

16 Kbytes

Function

Function Name

S6E1C1

S6E1C3

Cortex-M0+

40.8 MHz

CPU

Frequency

Power supply voltage range

USB2.0 (Device/Host)

DSTC

1.65 V to 3.6 V

-

1 unit

64 ch.

Base Timer

(PWC/Reload timer/PWM/PPG)

8 ch. (Max)

Dual Timer

1 unit

Real-time Clock

1 unit

Watch Counter

1 unit

CRC Accelerator

Yes

1 ch. (SW) + 1 ch. (HW)

Yes

Watchdog timer

CSV (Clock Supervisor)

LVD (Low-voltage Detection)

2 ch.

High-speed

Built-in CR

8 MHz (Typ)

100 kHz (Typ)

SW-DP

Low-speed

Debug Function

Unique ID

Yes

Note:

−

Because of package pin limitations, not all functions within the device can be brought out to external pins. You must carefully

work out the pin allocation needed for your design.

You must use the port relocate function of the I/O port according to your function use.

−

See "11. Electrical Characteristics 11.4 AC Characteristics 11.4.3 Built-in CR Oscillation Characteristics" for accuracy of built-in

CR.

Document Number: 002-00233 Rev. *D

Page 5 of 109

S6E1C Series

2.1 Package Dependent Features

Feature

Package

32 LQFP

32 QFN

48 LQFP

48 QFN

64 LQFP

64 QFN

30 WLCSP

Pin count

30

32

48

64

4 ch. (Max)

6 ch. (Max)

Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO

Multi-function Serial Interface

(UART/CSIO/I²C/I²S)

Ch. 6 with FIFO

Ch.4/6/7 with FIFO

I²S: 1 ch (Max)

Ch. 6 with FIFO

I²S: 2 ch (Max)

Ch. 4/6 with FIFO

I²S: No

7 pins (Max),

NMI x 1

9 pins (Max),

NMI x 1

12 pins (Max),

NMI x 1

External Interrupt

I/O port

24 pins (Max)

6 ch. (1 unit)

38 pins (Max)

8 ch. (1 unit)

54 pins (Max)

8 ch. (1 unit)

12-bit A/D converter

Smart Card Interface

No

1 ch (Max)

HDMI-CEC/ Remote Control

Receiver

1 ch.(Max)

Ch.1

2 ch (Max)

Ch.0/1

2.2 Packages

Package Suffix

B0A

C0A

D0A

Package

LQFP: LQB032 (0.80 mm pitch)

QFN: WNU032 (0.50 mm pitch)

WLCSP: U4M030 (0.40 mm pitch)

LQFP: LQA048 (0.50 mm pitch)

QFN: WNY048 (0.50 mm pitch)

LQFP: LQD064 (0.50 mm pitch)



-



-



-



-

QFN: WNS064 (0.50 mm pitch)

: Available

Note:

−

See "14. Package Dimensions" for detailed information on each package.

Document Number: 002-00233 Rev. *D

Page 6 of 109

S6E1C Series

3. Product Features in Detail

Multi-Function Serial Interface (Max 6channels)

3 channels with 64Byte FIFO (Ch.4, 6 and 7), 3 channels

without FIFO (Ch.0, 1 and 3)

32-bit ARM Cortex-M0+ Core

Maximum operating frequency: 40.8 MHz

The operation mode of each channel can be selected from

one of the following.

Nested Vectored Interrupt Controller (NVIC): 1 NMI

(non-maskable interrupt) and 24 peripheral interrupt with 4

selectable interrupt priority levels

 UART

 CSIO (CSIO is known to many customers as SPI)

 I²C

24-bit System timer (Sys Tick): System timer for OS task

management

UART

 Full duplex double buffer

Bit Band Operation

Compatible with Cortex-M3 bit band operation.

 Parity can be enabled or disabled.

 Built-in dedicated baud rate generator

 External clock available as a serial clock

On-Chip Memory

 Hardware Flow control* : Automatically control the

transmission by CTS/RTS (only ch.4)

* : S6E1C32B0A/S6E1C31B0A and

S6E1C32C0A/S6E1C31C0A do not support Hardware

Flow control.

 Various error detection functions (parity errors, framing

errors, and overrun errors)

Flash memory

 Up to 128 Kbytes

 Read cycle: 0 wait-cycle

 Security function for code protection

SRAM

CSIO (also known as SPI)

 Full duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detection function

 Serial chip select function (ch1 and ch6 only)

 Data length: 5 to 16 bits

The on-chip SRAM of this series has one independent SRAM.

 Up to 16 Kbytes

 4Kbytes: can retain value in Deep standby Mode

USB Interface

USB interface is composed of Device and Host

With Main PLL, USB clock can be generated by multiplication

of Main clock.

I²C

 Standard-mode (Max: 100 kbps) supported / Fast-mode

(Max 400 kbps) supported.

USB Device

I²S (MFS-I2S)

 USB 2.0 Full-Speed supported

 Max 6 EndPoint supported

• EndPoint 0 is control transfer

• EndPoint 1, 2 can be selected Bulk-transfer,

Interrupt-transfer or Isochronous-transfer

 Using CSIO (Max 2 ch: ch.4, ch.6) and I²S clock generator

 Supports two transfer protocol

• I²S

• MSB-justified

 Master mode only

• EndPoint 3 to 5 can select Bulk-transfer or

Interrupt-transfer

• EndPoint 1 to 5 comprise Double Buffer

• The size of each EndPoint is according to the follows

• EndPoint 0, 2 to 5 : 64 bytes

Descriptor System Data Transfer Controller (DSTC)

(64 Channels)

The DSTC can transfer data at high-speed without going via

the CPU. The DSTC adopts the Descriptor system and,

following the specified contents of the Descriptor that has

already been constructed on the memory, can access directly

the memory / peripheral device and performs the data

transfer operation.

• EndPoint 1 : 256 bytes

USB host

 USB 2.0 Full/Low-Speed supported

 Bulk-transfer, Interrupt-transfer and Isochronous-transfer

support

 USB Device connected/disconnected automatically detect

 IN/OUT token handshake packet automatically

 Max 256-byte packet-length supported

It supports the software activation, the hardware activation,

and the chain activation functions

 Wake-up function supported

Document Number: 002-00233 Rev. *D

Page 7 of 109

S6E1C Series

It can count leap years automatically.

A/D Converter (Max: 8 Channels)

Watch Counter

12-bit A/D Converter

The Watch Counter wakes up the microcontroller from the low

power consumption mode. The clock source can be selected

from the main clock, the sub clock, the built-in high-speed CR

clock or the built-in low-speed CR clock.

 Successive approximation type

 Conversion time: 2.0 μs @ 2.7 V to 3.6 V

 Priority conversion available (2 levels of priority)

 Scan conversion mode

 Built-in FIFO for conversion data storage (for scan

conversion: 16 steps, for priority conversion: 4 steps)

Interval timer: up to 64 s (sub clock: 32.768 kHz)

External Interrupt Controller Unit

Up to 12 external interrupt input pins

Non-maskable interrupt (NMI) input pin: 1

Base Timer (Max: 8 Channels)

The operation mode of each channel can be selected from one

of the following.

16-bit PWM timer

16-bit PPG timer

Watchdog Timer (2 Channels)

The watchdog timer generates an interrupt or a reset when the

counter reaches a time-out value.

16/32-bit reload timer

16/32-bit PWC timer

This series consists of two different watchdogs, hardware

watchdog and software watchdog.

General-Purpose I/O Port

The hardware watchdog timer is clocked by the built-in

low-speed CR oscillator. Therefore, the hardware watchdog is

active in any low-power consumption modes except RTC, Stop,

Deep standby RTC and Deep standby Stop mode.

This series can use its pin as a general-purpose I/O port when

it is not used for an external bus or a peripheral function. All

ports can be set to fast general-purpose I/O ports or slow

general-purpose I/O ports. In addition, this series has a port

relocate function that can set to which I/O port a peripheral

function can be allocated.

CRC (Cyclic Redundancy Check) Accelerator

The CRC accelerator calculates the CRC which has a heavy

software processing load, and achieves a reduction of the

integrity check processing load for reception data and storage.

All ports are Fast GPIO which can be accessed by 1cycle

Capable of controlling the pull-up of each pin

Capable of reading pin level directly

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

 CCITT CRC16 Generator Polynomial: 0x1021

 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7

Port relocate function

HDMI-CEC/Remote Control Receiver (Up to 2

Channels)

Up to 54 fast general-purpose I/O ports @64-pin package

Certain ports are 5 V tolerant.

See 5.List of Pin Functions and 6.I/O Circuit Type for the

corresponding pins.

HDMI-CEC transmitter

 Header block automatic transmission by judging Signal

free

Dual Timer (32-/16-bit Down Counter)

 Generating status interrupt by detecting Arbitration lost

The Dual Timer consists of two programmable 32-/16-bit down

counters. The operation mode of each timer channel can be

selected from one of the following.

 Generating START, EOM, ACK automatically to output

CEC transmission by setting 1 byte data

 Generating transmission status interrupt when transmitting

1 block (1 byte data and EOM/ACK)

Free-running mode

HDMI-CEC receiver

 Automatic ACK reply function available

 Line error detection function available

Periodic mode (= Reload mode)

One-shot mode

Remote control receiver

 4 bytes reception buffer

Real-Time Clock

The Real-time Clock counts

 Repeat code detection function available

Smart Card Interface (Max 1 Channel)

Compliant with ISO7816-3 specification

year/month/day/hour/minute/second/day of the week from year

00 to year 99.

The RTC can generate an interrupt at a specific time

(year/month/day/hour/minute) and can also generate an

interrupt in a specific year, in a specific month, on a specific

day, at a specific hour or at a specific minute.

Card Reader only/B class card only

Available protocols

 Transmitter: 8E2, 8O2, 8N2

 Receiver: 8E1, 8O1, 8N2, 8N1, 9N1

 Inverse mode

It has a timer interrupt function generating an interrupt upon

a specific time or at specific intervals.

It can keep counting while rewriting the time.

TX/RX FIFO integrated (RX: 16-bytes, TX:16-bytes)

Document Number: 002-00233 Rev. *D

Page 8 of 109

S6E1C Series

Clock and Reset

Low Power Consumption Mode

This series has six low power consumption modes.

Clocks

A clock can be selected from five clock sources (two external

oscillators, two built-in CR oscillator, and main PLL).

Sleep

Timer

RTC

Stop

 Main clock:

 Sub clock:

 Built-in high-speed CR clock: 8 MHz

 Built-in low-speed CR clock: 100 kHz

8 MHz to 48 MHz

32.768 kHz

 Main PLL clock

8MHz to 16MHz (Input),

75MHz to 150MHz (Output)

Deep standby RTC (selectable between keeping the value of

RAM and not)

Resets

 Reset request from the INITX pin

 Power on reset

Deep standby Stop (selectable between keeping the value of

RAM and not)

 Software reset

Peripheral Clock Gating

 Watchdog timer reset

 Low-voltage detection reset

 Clock supervisor reset

The system can reduce the current consumption of the total

system with gating the operation clocks of peripheral functions

not used.

Debug

Clock Supervisor (CSV)

The Clock Supervisor monitors the failure of external clocks

with a clock generated by a built-in CR oscillator.

Serial Wire Debug Port (SW-DP)

Micro Trace Buffer (MTB)

If an external clock failure (clock stop) is detected, a reset is

asserted.

Unique ID

A 41-bit unique value of the device has been set.

If an external frequency anomaly is detected, an interrupt or

a reset is asserted.

Power Supply

Low-Voltage Detector (LVD)

Wide voltage range:

This series monitors the voltage on the VCC pin with a 2-stage

mechanism. When the voltage falls below a designated voltage,

the Low-voltage Detector generates an interrupt or a reset.

VCC = 1.65V to 3.6 V

VCC = 3.0V to 3.6V (when USB is used)

LVD1: monitor V_CCand error reporting via an interrupt

LVD2: auto-reset operation

Document Number: 002-00233 Rev. *D

Page 9 of 109

S6E1C Series

4. Pin Assignment

LQD064

(TOP VIEW)

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S6E1C Series

WNS064

(TOP VIEW)

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S6E1C Series

LQA048

(TOP VIEW)

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S6E1C Series

WNY048

(TOP VIEW)

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S6E1C Series

LQB032

(TOP VIEW)

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S6E1C Series

WNU032

(TOP VIEW)

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Page 15 of 109

S6E1C Series

U4M030

(BOTTOM VIEW)

1

2

3

4

5

P50

P01

AVRH

P81

P80

A

B

C

P22

P12

P51

P52

P23

P11

P05

P03

P21

P13

P60

VSS

C

P32

P33

X0A

X1A

P0F

P31

X0

P10

X1

D

E

F

MD0

INITX

VCC

Document Number: 002-00233 Rev. *D

Page 16 of 109

S6E1C Series

5. List of Pin Functions

List of Pin Numbers

The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel

on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select

the pin to be used.

Pin No.

Alternate Functions

1

2

1

2

3

4

-

A1

P50

P51

P52

P53

P30

P31

P32

P33

P34

P35

P3A

P3B

P3C

P3D

P3E

P3F

MD0

PE2

PE3

P40

P41

P42

P43

P4C

P4D

P4E

VCC

C

SIN3_1

SOT3_1

SCK3_1

TIOA1_2

SCS60_1

SCK6_1

SOT6_1

ADTG_6

SCS61_1

INT00_0

INT01_0

INT02_0

INT07_2

TIOB0_1

INT04_2

TIOB2_1

SIN6_1

D

H

D

I

K

F

A

B

K

-

B1

3

C1

4

-

5

-

INT03_2

MI2SWS6_1

6

-

MI2SCK6_1

-

5

-

E2

7

-

INT05_2

MI2SDO6_1

MI2SDI6_1

-

6

-

D1

8

-

INT04_0

-

7

-

E1

SIN6_1

INT04_0

9

-

TIOB4_1

MI2SMCK6_1

-

9

-

SCS61_1 MI2SMCK6_1

10

11

-

SCS62_1

TIOA0_1

TIOA1_1

TIOA2_1

TIOA3_1

TIOA4_1

TIOA5_1

TIOB5_1

INT03_0

INT08_1

RTCCO_2

-

SUBOUT_2

IC1_CIN_0

10

-

INT03_0

12

-

IC1_DATA_0

11

-

13

-

IC1_RST_0

12

-

14

15

16

17

18

19

20

21

22

23

24

-

IC1_VPEN_0

IC1_VCC_0

IC1_CLK_0

-

13

14

15

-

8

9

10

-

F1

F2

E3

-

X0

A

D

-

X1

TIOA0_0

TIOA1_0

TIOA2_0

ADTG_7

SCK7_1

SOT7_1

SIN7_1

INT12_1

INT13_1

-

TIOA3_0

TIOB3_0

-

16

17

18

19

20

21

22

-

25

26

27

28

29

30

-

INT06_2

11

12

13

14

F3

F4

E4

D5

-

VSS

P46

-

X0A

C

Document Number: 002-00233 Rev. *D

Page 17 of 109

S6E1C Series

Pin No.

Alternate Functions

31

32

33

34

35

36

37

-

23

15

16

17

-

E5

F5

D4

-

P47

INITX

P60

P1E

P1D

P1C

P1B

P1A

P1F

P10

P11

X1A

C

B

H

D

H

D

F

G

F

-

D

E

K

J

24

25

-

TIOA2_2

RTS4_1

CTS4_1

SCK4_1

SOT4_1

SIN4_1

ADTG_5

AN00

INT15_1

CEC1_0

MI2SMCK4_1

MI2SWS4_1

MI2SCK4_1

MI2SDO4_1

-

26

-

38

-

INT05_1

CEC0_0

MI2SDI4_1

WKUP1

27

-

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

-

28

29

30

31

32

33

34

35

36

37

38

39

-

18

19

20

21

-

D3

C5

C4

C3

-

AN01

SIN1_1

SOT1_1

SCK1_1

SIN0_1

INT02_1

J

P12

P13

P14

P15

P23

P22

VCC

AVRH¹

AVRL

P21

P00

P01

P02

P03

P05

VCC

P80

P81

VSS

P61

P0B

P0C

P0F

AN02

AN03

AN04

AN05

AN06

AN07

J

RTCCO_1

SCS10_1

SCS11_1

TIOA7_1

SUBOUT_1

INT03_1

J

-

SOT0_1

SCK0_0

TIOB7_1

J

22

23

24

-

B5

B4

A5

-

J

-

25

26

-

B3

-

INT06_1

WKUP4

SWCLK

WKUP5

SWDIO

MD1

WKUP2

SOT0_0

E

D

E

D

E

-

K

-

40

-

27

-

A4

-

41

42

43

44

45

46

47

-

28

29

-

C2

B2

-

SIN0_0

TIOB7_0

INT00_1

TIOA5_2

WKUP3

30

31

32

-

A3

A2

-

UDM0

UDP0

J

G

-

J

-

UHCONX0

TIOB6_1

TIOA6_1

NMIX

TIOB2_2

WKUP6

WKUP7

WKUP0

H

E

K

I

-

48

1

D2

RTCCO_0

SUBOUT_0

CROUT_1

E

1

In a 32-pin package, the AVRH pin is internally connected to the V_CCpin.

Document Number: 002-00233 Rev. *D

Page 18 of 109

S6E1C Series

List of Pin Functions

The number after the underscore ("_") in a function name such as XXX_1 and XXX_2 indicates one of the relocate options to route

that function to a different pin. Use the Extended Port Function Register (EPFR) to disable or select the desired relocate option.

Pin No.

Pin Function

Pin Name

Function Description

LQFP-64 LQFP-48 LQFP-32 WLCSP-

QFN-64

39

8

QFN-48

QFN-32

30

-

ADTG_5

ADTG_6

ADTG_7

AN00

-

8

-

7

ADC

A/D converter external trigger input pin

E1

-

23

40

41

42

43

44

45

46

47

20

11

5

-

28

29

30

31

32

33

34

35

-

18

19

20

21

-

D3

C5

C4

C3

-

AN01

AN02

AN03

A/D converter analog input pin.

ANxx describes ADC ch.xx.

ADC

AN04

AN05

-

AN06

22

23

-

B5

B4

-

AN07

TIOA0_0

TIOA0_1

TIOB0_1

TIOA1_0

TIOA1_1

TIOA1_2

TIOA2_0

TIOA2_1

TIOA2_2

TIOB2_1

TIOB2_2

TIOA3_0

TIOA3_1

TIOB3_0

TIOA4_1

TIOB4_1

TIOA5_1

TIOA5_2

TIOB5_1

TIOA6_1

TIOB6_1

TIOA7_1

TIOB7_0

TIOB7_1

SWCLK

Base timer ch.0 TIOA pin

Base timer ch.0 TIOB pin

Base Timer 0

Base Timer 1

10

5

-

21

12

4

-

Base timer ch.1 TIOA pin

Base timer ch.2 TIOA pin

11

4

-

22

13

33

7

-

12

25

7

-

Base Timer 2

17

6

D4

D1

-

Base timer ch.2 TIOB pin

Base timer ch.3 TIOA pin

61

23

14

24

15

9

47

-

Base Timer 3

Base Timer 4

Base Timer 5

Base Timer 6

Base Timer 7

-

Base timer ch.3 TIOB pin

Base timer ch.4 TIOA pin

Base timer ch.4 TIOB pin

-

16

56

10

63

62

46

55

47

53

-

Base timer ch.5 TIOA pin

42

-

29

-

B2

-

Base timer ch.5 TIOB pin

Base timer ch.6 TIOA pin

Base timer ch.6 TIOB pin

Base timer ch.7 TIOA pin

-

34

41

35

40

22

28

23

27

B5

C2

B4

A4

Base timer ch.7 TIOB pin

Serial wire debug interface clock input pin

Serial wire debug interface data input /

output pin

Debugger

SWDIO

55

41

28

C2

Document Number: 002-00233 Rev. *D

Page 19 of 109

S6E1C Series

Pin No.

LQFP-64 LQFP-48 LQFP-32 WLCSP-

Pin Function

Pin Name

Function Description

QFN-64

1

QFN-48

1

QFN-32

30

A1

B2

B1

C1

C5

-

INT00_0

INT00_1

INT01_0

INT02_0

INT02_1

INT03_0

INT03_1

INT03_2

INT04_0

INT04_2

INT05_1

INT05_2

INT06_1

INT06_2

INT07_2

INT08_1

INT12_1

INT13_1

INT15_1

NMIX

P00

2

29

3

External interrupt request 00 input pin

External interrupt request 01 input pin

External interrupt request 02 input pin

56

2

42

2

3

4

41

11

44

5

29

10

32

5

19

-

External interrupt request 03 input pin

-

8

7

E1

E2

-

External interrupt request 04 input pin

External interrupt request 05 input pin

External interrupt request 06 input pin

6

5

External

Interrupt

38

7

27

7

-

6

D1

B3

-

51

26

4

39

18

4

26

-

External interrupt request 07 input pin

External interrupt request 08 input pin

External interrupt request 12 input pin

External interrupt request 13 input pin

External interrupt request 15 input pin

Non-Maskable Interrupt input pin

-

10

20

21

33

64

52

53

54

55

56

62

63

64

40

41

42

43

44

45

38

37

36

35

34

39

51

47

46

-

25

48

-

17

1

D4

D2

-

P01

40

-

27

-

A4

-

P02

P03

41

42

-

28

29

-

C2

B2

-

GPIO

General-purpose I/O port 0

P05

P0B

P0C

-

P0F

48

28

29

30

31

32

33

27

26

-

1

D2

D3

C5

C4

C3

-

P10

18

19

20

21

-

P11

P12

P13

P14

P15

-

GPIO

General-purpose I/O port 1

P1A

-

P1B

-

P1C

-

P1D

-

P1E

-

P1F

-

P21

39

35

34

26

23

22

B3

B4

B5

GPIO

P22

General-purpose I/O port 2

P23

Document Number: 002-00233 Rev. *D

Page 20 of 109

S6E1C Series

Pin No.

LQFP-64 LQFP-48 LQFP-32 WLCSP-

Pin Function

Pin Name

Function Description

QFN-64

5

QFN-48

QFN-32

30

-

P30

P31

5

6

-

5

6

7

-

6

E2

D1

E1

-

P32

7

P33

8

P34

9

P35

10

11

12

13

14

15

16

20

21

22

23

30

31

24

25

26

1

-

GPIO

General-purpose I/O port 3

P3A

P3B

P3C

P3D

P3E

P3F

10

11

12

-

P40

-

P41

-

P42

-

P43

-

GPIO

P46

General-purpose I/O port 4

22

23

16

17

18

1

14

15

-

D5

E5

-

P47

P4C

P4D

P4E

P50

-

2

3

4

-

A1

B1

C1

-

P51

2

General-purpose I/O port 5

P52

3

P53

4

P60

33

61

58

59

18

19

55

44

25

47

44

45

14

15

41

32

17

-

D4

-

GPIO

General-purpose I/O port 6

General-purpose I/O port 8

General-purpose I/O port E

P61

P80

30

31

9

10

28

-

A3

A2

F2

E3

C2

-

P81

PE2

PE3

SIN0_0

SIN0_1

SOT0_0

(SDA0_0)

Multi-function serial interface ch.0 input

Multi-function serial interface ch.0 output

pin. This pin operates as SOT0 when

used as a UART/CSIO/LIN pin (operation

mode 0 to 3) and as SDA0 when used as

an I²C pin (operation mode 4).

53

40

27

A4

SOT0_1

Multi-function

Serial 0

45

33

-

(SDA0_1)

Multi-function serial interface ch.0 clock

I/O pin. This pin operates as SCK0 when

used as a CSIO pin (operation mode 2)

and as SCL0 when used as an I²C pin

(operation mode 4).

SCK0_0

46

34

22

B5

(SCL0_0)

Document Number: 002-00233 Rev. *D

Page 21 of 109

S6E1C Series

Pin No.

LQFP-64 LQFP-48 LQFP-32 WLCSP-

Pin Function

Pin Name

Function Description

QFN-64

QFN-48

QFN-32

30

Multi-function serial interface ch.1 input

SIN1_1

41

29

19

C5

Multi-function serial interface ch.1 output

pin. This pin operates as SOT1 when

used as a UART/CSIO/LIN pin (operation

mode 0 to 3) and as SDA1 when used as

an I²C pin (operation mode 4).

SOT1_1

42

30

20

C4

(SDA1_1)

Multi-function

Serial 1

Multi-function serial interface ch.1 clock

I/O pin. This pin operates as SCK1 when

used as a CSIO pin (operation mode 2)

and as SCL1 when used as an I²C pin

(operation mode 4).

SCK1_1

43

44

31

32

21

-

C3

(SCL1_1)

Multi-function serial interface ch.1 serial

chip select 0 input/output pin.

SCS10_1

-

Multi-function serial interface ch.1 serial

chip select 1 output pin.

SCS11_1

SIN3_1

45

1

33

1

-

Multi-function serial interface ch.3 input

2

A1

Multi-function serial interface ch.3 output

pin. This pin operates as SOT3 when

used as a UART/CSIO/LIN pin (operation

mode 0 to 3) and as SDA3 when used as

an I²C pin (operation mode 4).

SOT3_1

2

3

B1

(SDA3_1)

Multi-function

Serial 3

Multi-function serial interface ch.3 clock

I/O pin. This pin operates as SCK3 when

used as a CSIO (operation mode 2) and

as SCL3 when used as an I²C pin

(operation mode 4).

SCK3_1

3

4

-

C1

-

(SCL3_1)

Multi-function serial interface ch.4 input

SIN4_1

38

27

Multi-function serial interface ch.4 output

pin. This pin operates as SOT4 when

used as a UART/CSIO/LIN pin (operation

mode 0 to 3) and as SDA4 when used as

an I²C pin (operation mode 4).

SOT4_1

37

36

26

-

(SDA4_1)

Multi-function

Serial 4

Multi-function serial interface ch.4 clock

I/O pin. This pin operates as SCK4 when

used as a CSIO (operation mode 2) and

as SCL4 when used as an I²C pin

(operation mode 4).

SCK4_1

-

(SCL4_1)

Multi-function serial interface ch4 CTS

input pin

Multi-function serial interface ch4 RTS

output pin

CTS4_1

RTS4_1

35

34

-

Document Number: 002-00233 Rev. *D

Page 22 of 109

S6E1C Series

Pin No.

LQFP-64 LQFP-48 LQFP-32 WLCSP-

Pin Function

Pin Name

Function Description

QFN-64

QFN-48

QFN-32

30

Multi-function serial interface ch.6 input

SIN6_1

8

7

E1

Multi-function serial interface ch.6 output

pin. This pin operates as SOT6 when

used as a UART/CSIO/LIN pin (operation

mode 0 to 3) and as SDA6 when used as

an I²C pin (operation mode 4).

SOT6_1

7

6

7

6

5

D1

E2

(SDA6_1)

Multi-function serial interface ch.6 clock

I/O pin. This pin operates as SCK6 when

used as a CSIO (operation mode 2) and

as SCL6 when used as an I²C pin

(operation mode 4).

Multi-function

Serial 6

SCK6_1

(SCL6_1)

Multi-function serial interface ch.6 serial

chip select 0 input/output pin.

SCS60_1

SCS61_1

SCS62_1

SIN7_1

5

9

5

9

-

Multi-function serial interface ch.6 serial

chip select 1 output pin.

Multi-function serial interface ch.6 serial

chip select 2 output pin.

10

26

-

Multi-function serial interface ch.7 input

18

Multi-function serial interface ch.7 output

pin. This pin operates as SOT7 when

used as a UART/CSIO/LIN pin (operation

mode 0 to 3) and as SDA7 when used as

an I²C pin (operation mode 4).

SOT7_1

25

24

17

16

-

(SDA7_1)

Multi-function

Serial 7

Multi-function serial interface ch.7 clock

I/O pin. This pin operates as SCK7 when

used as a CSIO (operation mode 2) and

as SCL7 when used as an I²C pin

(operation mode 4).

SCK7_1

(SCL7_1)

Document Number: 002-00233 Rev. *D

Page 23 of 109

S6E1C Series

Pin No.

LQFP-64 LQFP-48 LQFP-32 WLCSP-

Pin Function

Pin Name

Function Description

QFN-64

QFN-48

QFN-32

30

I²S Serial Data Input pin (operation

mode 2).

I²S Serial Data Output pin (operation

MI2SDI4_1

MI2SDO4_1

MI2SCK4_1

MI2SWS4_1

MI2SMCK4_1

MI2SDI6_1

38

-

37

36

35

34

8

-

mode 2).

I²S Serial Clock Output pin (operation

mode 2).

I²S Word Select Output pin (operation

-

mode 2).

I²S Master Clock Input/output pin

(operation mode 2).

I²S Serial Data Input pin (operation

-

I2S(MFS)

8

7

6

5

mode 2).

I²S Serial Data Output pin (operation

mode 2).

I²S Serial Clock Output pin (operation

MI2SDO6_1

MI2SCK6_1

MI2SWS6_1

7

6

mode 2).

I²S Word Select Output pin (operation

mode 2).

5

I²S Master Clock Input/output pin

MI2SMCK6_1

IC1_CIN_0

9

-

(operation mode 2).

Smart Card insert detection output pin

Smart Card serial interface clock output

11

16

IC1_CLK_0

-

Smart Card

Interface

IC1_DATA_0

IC1_RST_0

IC1_VCC_0

IC1_VPEN_0

UDM0

Smart Card serial interface data input pin

Smart Card reset output pin

Smart Card power enable output pin

Smart Card programming output pin

USB function/host D – pin

USB function/host D + pin

USB external pull-up control pin

12

13

15

14

58

59

61

64

43

11

64

43

11

-

44

45

47

48

31

10

48

31

10

30

31

-

A3

A2

-

USB

UDP0

UHCONX0

RTCCO_0

RTCCO_1

RTCCO_2

SUBOUT_0

SUBOUT_1

SUBOUT_2

1

D2

C3

-

0.5 seconds pulse output pin of

real-time clock

21

-

Real-time

Clock

1

D2

C3

-

Sub clock output pin

21

-

HDMI-CEC/Remote Control Reception

ch.0 input/output pin

CEC0_0

CEC1_0

38

33

27

25

-

HDMI-CEC/Re

mote Control

Reception

HDMI-CEC/Remote Control Reception

ch.1 input/output pin

17

D4

Document Number: 002-00233 Rev. *D

Page 24 of 109

S6E1C Series

Pin No.

LQFP-64 LQFP-48 LQFP-32 WLCSP-

Pin Function

Pin Name

Function Description

QFN-64

QFN-48

QFN-32

30

Deep Standby mode return signal input

pin 0

Deep Standby mode return signal input

pin 1

Deep Standby mode return signal input

pin 2

Deep Standby mode return signal input

pin 3

Deep Standby mode return signal input

pin 4

Deep Standby mode return signal input

pin 5

Deep Standby mode return signal input

pin 6

Deep Standby mode return signal input

pin 7

WKUP0

WKUP1

WKUP2

WKUP3

WKUP4

WKUP5

WKUP6

WKUP7

64

48

1

D2

41

51

56

52

54

62

63

29

39

42

-

19

26

29

-

C5

B3

B2

-

Low Power

Consumption

Mode

-

External Reset Input pin.

A reset is valid when INITX="L".

RESET

MODE

INITX

32

24

16

F5

Mode 0 pin.

During normal operation, input MD0="L".

During serial programming to Flash

memory, input MD0="H".

MD0

17

13

8

F1

Mode 1 pin.

During normal operation, input is not

needed.

MD1

56

42

29

B2

During serial programming to Flash

memory, MD1 = "L" must be input.

X0

X0A

X1

Main clock (oscillation) input pin

Sub clock (oscillation) input pin

Main clock (oscillation) I/O pin

Sub clock (oscillation) I/O pin

18

30

19

31

14

22

15

23

9

F2

D5

E3

E5

14

10

15

CLOCK

X1A

Built-in high-speed CR oscillation clock

output port

CROUT_1

64

48

1

D2

VCC

VSS

27

48

57

29

60

19

36

43

21

46

11

24

-

F3

A5

-

POWER

GND

Power supply pin

13

32

E4

-

GND pin

A/D converter analog reference voltage

input pin

A/D converter analog reference voltage

input pin

AVRH²

49

50

37

38

-

Analog

Reference

AVRL

25

Power supply stabilization capacitance

C pin

C

28

20

12

F4

2

In case of 32-pin package, AVRH pin is internally connected to the V_CCpin.

Document Number: 002-00233 Rev. *D

Page 25 of 109

S6E1C Series

6. I/O Circuit Type

Type

Circuit

Remarks

P-ch

Digital output

X1

It is possible to select the main

oscillation / GPIO function

N-ch

Digital output

R

When the main oscillation is

selected.

Pull-up resistor control

Digital input

・Oscillation feedback resistor

Approximately 1 MΩ

・With standby mode control

Standby mode Control

Clock input

A

When the GPIO is selected.

・CMOS level output.

・CMOS level hysteresis input

・With pull-up resistor control

・With standby mode control

・Pull-up resistor

Standby mode Control

Digital input

Standby mode Control

R

P-ch

Approximately 33 kΩ

Digital output

X0

・I_OH= -4 mA, I_OL= 4 mA

N-ch

Digital output

Pull-up resistor control

CMOS level hysteresis input

Pull-up resistor

B

Approximately 33 kΩ

Digital input

Document Number: 002-00233 Rev. *D

Page 26 of 109

S6E1C Series

Type

Circuit

Remarks

P-ch

Digital output

X1A

It is possible to select the sub

oscillation / GPIO function

N-ch

Digital output

R

When the sub oscillation is

selected.

 Oscillation feedback resistor

Approximately 5 MΩ

Pull-up resistor control

Digital input

Standby mode Control

Clock input

 With Standby mode control

C

When the GPIO is selected.

 CMOS level output.

Standby mode Control

Digital input

 CMOS level hysteresis input

 With pull-up resistor control

 With standby mode control

 Pull-up resistor

Standby mode Control

Approximately 33 kΩ

R

I_OH= -4 mA, I_OL= 4 mA

P-ch

Digital output

X0A

N-ch

Digital output

Pull-up resistor control

Document Number: 002-00233 Rev. *D

Page 27 of 109

S6E1C Series

Type

Circuit

Remarks

・CMOS level output

・CMOS level hysteresis input

・With pull-up resistor control

・With standby mode control

・Pull-up resistor

P-ch

Digital output

N-ch

Digital output

D

Approximately 33 kΩ

R

・I_OH= -4mA, I_OL= 4 mA

・When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

Pull-up resistor control

Digital input

Standby mode Control

・CMOS level output

P-ch

Digital output

・CMOS level hysteresis input

・With pull-up resistor control

・With standby mode control

・Pull-up resistor

N-ch

R

E

Approximately 33 kΩ

・I_OH= -4 mA, I_OL= 4 mA

・When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

Pull-up resistor control

Digital input

Standby mode Control

Wake up request

Wake up control

Document Number: 002-00233 Rev. *D

Page 28 of 109

S6E1C Series

Type

Circuit

Remarks

・CMOS level output

P-ch

Digital output

・CMOS level hysteresis input

・With input control

・Analog input

N-ch

Digital output

・With pull-up resistor control

・With standby mode control

・Pull-up resistor

R

F

Pull-up resistor control

Digital input

Approximately 33 kΩ

・I_OH= -4 mA, I_OL= 4 mA

・When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

Standby mode Control

Analog input

Input control

P-ch

Digital output

・CMOS level output

・CMOS level hysteresis input

・With input control

N-ch

・Analog input

R

・With pull-up resistor control

・With standby mode control

・Pull-up resistor

G

Pull-up resistor control

Digital input

: Approximately 33 kΩ

・I_OH= -4 mA, I_OL= 4 mA

・When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

Standby mode Control

Wake up request

Wake up Control

Analog input

Input control

Document Number: 002-00233 Rev. *D

Page 29 of 109

S6E1C Series

Type

Circuit

Remarks

・CMOS level output

・CMOS level hysteresis input

・5V tolerant

・With pull-up resistor control

・With standby mode control

・Pull-up resistor

P-ch

Digital output

H

Approximately 33 kΩ

N-ch

Digital output

R

・I_OH= -4 mA, I_OL= 4 mA

・Available to control PZR

registers

・When this pin is used as an

I²C pin, the digital output

P-ch transistor is always off

Pull-up resistor control

Digital input

Standby mode Control

Mode input

I

・CMOS level hysteresis input

GPIO Digital output

GPIO Digital input/output direction

GPIO Digital input

GPIO Digital input circuit control

UDP output

It is possible to select the USB

I/O / GPIO function.

UDP0/P81

USB Full-speed/Low-speed control

UDP input

When the USB I/O is selected.

 Full-speed, Low-speed control

Differential

UDM0/P80

Differential input

USB/GPIO select

J

When the GPIO is selected.

 CMOS level output

UDM input

 CMOS level hysteresis input

 With standby mode control

UDM output

USB Digital input/output direction

GPIO Digital input

GPIO Digital input/output direction

GPIO Digital input

GPIO Digital input circuit control

Document Number: 002-00233 Rev. *D

Page 30 of 109

S6E1C Series

7. Handling Precautions

Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in

which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to

minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

7.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of

certain established limits, called absolute maximum ratings. Do not exceed these ratings.

Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical

characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely

affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users

considering application outside the listed conditions are advised to contact their sales representative beforehand.

Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output

functions.

(1) Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,

and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at

the design stage.

(2) Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.

Such conditions if present for extended periods of time can damage the device.

Therefore, avoid this type of connection.

(3) Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be

connected through an appropriate resistance to a power supply pin or ground pin.

Document Number: 002-00233 Rev. *D

Page 31 of 109

S6E1C Series

Latch-Up

Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally

high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of

several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or

damage from high heat, smoke or flame. To prevent this from happening, do the following:

(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal

noise, surge levels, etc.

(2) Be sure that abnormal current flows do not occur during the power-on sequence.

Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic

interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.

Fail-Safe Design

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating conditions.

Precautions Related to Usage of Devices

Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office

equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)

are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from

such use without prior approval.

7.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you

should mount only under Cypress’ recommended conditions. For detailed information about mount conditions, contact your sales

representative.

Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or

mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow

soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected

to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress

recommended mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact

deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be

verified before mounting.

Document Number: 002-00233 Rev. *D

Page 32 of 109

S6E1C Series

Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed

or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections

caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of

mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended

conditions.

Lead-Free Packaging

CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength

may be reduced under some conditions of use.

Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of

moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing

moisture resistance and causing packages to crack. To prevent, do the following:

(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.

Store products in locations where temperature changes are slight.

(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C

and 30 ˚C.

When you open Dry Package that recommends humidity 40% to 70% relative humidity.

(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica

gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.

(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

Baking

Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended

conditions for baking.

Condition: 125°C/24 h

Static Electricity

Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:

(1) Maintain relative humidity in the working environment between 40% and 70%.

Use of an apparatus for ion generation may be needed to remove electricity.

(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.

(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of

1 MΩ).

Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is

recommended.

(4) Ground all fixtures and instruments, or protect with anti-static measures.

(5) Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.

Document Number: 002-00233 Rev. *D

Page 33 of 109

S6E1C Series

7.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.

For reliable performance, do the following:

(1) Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are

anticipated, consider anti-humidity processing.

(2) Discharge of Static Electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,

use anti-static measures or processing to prevent discharges.

(3) Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If

you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.

(4) Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide

shielding as appropriate.

(5) Smoke, Flame

CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices

begin to smoke or burn, there is danger of the release of toxic gases.

Customers considering the use of Cypress products in other special environmental conditions should consult with sales

representatives.

Document Number: 002-00233 Rev. *D

Page 34 of 109

S6E1C Series

8. Handling Devices

Power Supply Pins

In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to

prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground

lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the

ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also

advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and

GND pin, between AVRH pin and AVRL pin near this device.

Stabilizing Supply Voltage

A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended

operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that

the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC

value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a

momentary fluctuation on switching the power supply.

Crystal Oscillator Circuit

Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,

X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.

It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by

ground plane as this is expected to produce stable operation.

Evaluate oscillation of your using crystal oscillator by your mount board.

Sub Crystal Oscillator

This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions

is recommended for sub crystal oscillator to stabilize the oscillation.

Surface mount type

Size: More than 3.2 mm × 1.5 mm

Load capacitance: Approximately 6 pF to 7 pF

Lead type

Load capacitance: Approximately 6 pF to 7 pF

Document Number: 002-00233 Rev. *D

Page 35 of 109

S6E1C Series

Using an External Clock

When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)

can be used as a general-purpose I/O port.

Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to

X0A. X1A (P47) can be used as a general-purpose I/O port.

However in the Deep Standby mode, an external clock as an input of the sub clock cannot be used.

Example of Using an External Clock

Device

X0(X0A)

Set as

Can be used as

general-purpose

I/O ports.

External clock

input

X1(PE3),

X1A (P47)

Handling when Using Multi-Function Serial Pin as I²C Pin

If it is using the multi-function serial pin as I²C pins, P-ch transistor of digital output is always disabled. However, I²C pins need to

keep the electrical characteristic like other pins and not to connect to the external I²C bus system with power OFF.

C Pin

This series contains the regulator. Be sure to connect a smoothing capacitor (C_S) for the regulator between the C pin and the GND

pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.

However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F

characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use

by evaluating the temperature characteristics of a capacitor.

A smoothing capacitor of about 4.7 μF would be recommended for this series.

Incidentally, the C pin becomes floating in Deep standby mode.

C

Device

C_S

VSS

GND

Mode Pins (MD0)

Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays

low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection

impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is

because of preventing the device erroneously switching to test mode due to noise.

Document Number: 002-00233 Rev. *D

Page 36 of 109

S6E1C Series

Notes on Power-on

Turn power on/off in the following order or at the same time.

Turning on : VCC →AVRH

Turning off : AVRH →VCC

Serial Communication

There is a possibility to receive wrong data due to the noise or other causes on the serial communication.

Therefore, design a printed circuit board so as to avoid noise.

Consider the case of receiving wrong data due to noise; perform error detection such as by applying a checksum of data at the end.

If an error is detected, retransmit the data.

Differences in Features Among the Products with Different Memory Sizes and Between Flash Memory

Products and MASK Products

The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among

the products with different memory sizes and between Flash memory products and MASK products are different because chip

layout and memory structures are different.

If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.

Pull-Up Function of 5 V Tolerant I/O

Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.

Handling when Using Debug Pins

When debug pins (SWDIO/SWCLK) are set to GPIO or other peripheral functions, set them as output only; do not set them as input.

Document Number: 002-00233 Rev. *D

Page 37 of 109

S6E1C Series

9. Memory Map

Memory Map (1)

0x41FF_FFFF

Reserved

0xFFFF_FFFF

0xF802_0000

Reserved

0x4006_2000

0x4006_1000

0x4005_0000

0x4004_0000

FAST GPIO

(Single-cycle I/O port)

VIR (Vector Indicate reg.)

(Single-cycle I/O port)

FAST GPIO

DSTC

Reserved

USB

0xF800_0180

0xF800_0100

Reserved

0x4003_CB00

0x4003_CA00

0x4003_C900

0x4003_C200

0x4003_C100

0x4003_C000

0x4003_B000

0x4003_A000

(Single-cycle I/O port)

0xF800_0000

0xF000_2000

0xF000_1000

MFS-I2S Clock Gen.

Smart Card I/F

Reserved

Peripheral Clock Gating

Low Speed CR Prescaler

RTC

Reserved

MTB_DWT

CM0+

Coresight-MTB(SFR)

Watch Counter

CRC Accelerator

MFS

0xF000_0000

0xE000_0000

0x4003_9000

0x4003_8000

CM0+

Private Peripherals

Reserved

0x4003_7000

0x4003_6000

0x4003_5000

USB Clock ctrl

LVD/DS mode

Reserved

0x4400_0000

HDMI-CEC/

Remote Control Receiver

0x4003_4000

0x4003_3000

32 Mbytes Bit band alias

0x40000000 ~ 0x40100000

GPIO

Reserved

Int-Req.Read

EXTI

0x4200_0000

0x4000_0000

0x4003_2000

0x4003_1000

Peripherals

Reserved

0x4003_0000

0x4002_F000

0x4002_E000

Reserved

HCR Trimming

0x2400_0000

Reserved

32 Mbytes Bit band alias

0x20000000 ~ 0x20100000

0x4002_8000

0x4002_7000

0x4002_6000

0x4002_5000

0x2200_0000

0x2000_4000

0x2000_0000

A/D Converter

Reserved

Base Timer

Reserved

SRAM

0x4001_6000

0x4001_5000

Dual timer

Reserved

0x0010_0008

0x0010_0004

CR Trim

Security

0x4001_3000

SW-Watchdog

HW-Watchdog

Clock/Reset

0x0010_0000

0x4001_2000

0x4001_1000

Reserved

0x0001_FFF0

0x4001_0000

FLASH

Reserved

Flash-IF

0x0000_0000

0x4000_1000

0x4000_0000

See "Memory map (2)" for the memory size details.

Document Number: 002-00233 Rev. *D

Page 38 of 109

S6E1C Series

Memory Map (2)

S6E1C11/S6E1C31

S6E1C12/S6E1C32

*: See "S6E1C1/C3 Series Flash Programming Manual" to check details of the flash memory.

Document Number: 002-00233 Rev. *D

Page 39 of 109

S6E1C Series

Peripheral Address Map

Start Address

End Address

Bus

Peripheral

Flash memory I/F register

0x4000_0000

0x4000_1000

0x4001_0000

0x4001_1000

0x4001_2000

0x4001_3000

0x4001_5000

0x4001_6000

0x4002_0000

0x4002_1000

0x4002_4000

0x4002_5000

0x4002_6000

0x4002_7000

0x4002_8000

0x4002_E000

0x4002_F000

0x4003_0000

0x4003_1000

0x4003_2000

0x4003_3000

0x4003_4000

0x4000_0FFF

AHB

0x4000_FFFF

0x4001_0FFF

0x4001_1FFF

0x4001_2FFF

0x4001_4FFF

0x4001_5FFF

0x4001_FFFF

0x4002_0FFF

0x4002_3FFF

0x4002_4FFF

0x4002_5FFF

0x4002_6FFF

0x4002_7FFF

0x4002_DFFF

0x4002_EFFF

0x4002_FFFF

0x4003_0FFF

0x4003_1FFF

0x4003_2FFF

0x4003_3FFF

0x4003_4FFF

Reserved

Clock/Reset Control

Hardware Watchdog Timer

Software Watchdog Timer

Reserved

APB0

Dual-Timer

Reserved

Base Timer

Reserved

A/D Converter

Reserved

Built-in CR trimming

Reserved

External Interrupt Controller

Interrupt Request Batch-Read Function

Reserved

GPIO

HDMI-CEC/Remote Control Receiver

APB1

0x4003_5000

0x4003_6000

0x4003_5FFF

0x4003_6FFF

Low-Voltage Detection / DS mode / Vref Calibration

USB Clock Generator

0x4003_7000

0x4003_7800

0x4003_7A00

0x4003_8000

0x4003_9000

0x4003_A000

0x4003_B000

0x4003_C000

0x4003_C100

0x4003_77FF

0x4003_79FF

0x4003_7FFF

0x4003_8FFF

0x4003_9FFF

0x4003_AFFF

0x4003_BFFF

0x4003_C0FF

0x4003_C7FF

Reserved

Multi-function Serial Interface

CRC

Watch Counter

Real-time clock

Low-speed CR Prescaler

Peripheral Clock Gating

0x4003_C800

0x4003_C900

0x4003_CA00

0x4003_CB00

0x4004_0000

0x4005_0000

0x4006_1000

0x4006_2000

0x4003_C8FF

0x4003_C9FF

0x4003_CAFF

0x4003_FFFF

0x4004_FFFF

0x4006_0FFF

0x4006_1FFF

0x41FF_FFFF

Reserved

Smart Card Interface

MFS-I2S Clock Generator

Reserved

USB ch.0

Reserved

AHB

DSTC

Reserved

Document Number: 002-00233 Rev. *D

Page 40 of 109

S6E1C Series

10.Pin Status in Each CPU State

The following table shows pin status in each CPU state.

CPU State

Type

Selected Pin Function

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

Main oscillation

circuit selected³

Main oscillation circuit selected

OS

OE

GS

IS

OS

A

Main clock external input selected

GPIO selected

-

IE/IS

PC

IE/IS

HC

IE/IS

IS

HS

IS

HS

Digital I/O

selected⁴

Main oscillation

circuit selected³

Digital I/O

Main oscillation circuit selected

GPIO selected

OS

-

OS

-

OE

PC

OE

HC

OE

IS

GS

IS

OS

GS

B

C

selected⁴

Sub oscillation

circuit selected³

Sub oscillation circuit selected

OS

OE

Sub clock external input selected

GPIO selected

-

IE/IS

PC

IE/IS

HC

IE/IS

IS

Digital I/O

selected⁴

HS

OE

HS

OE

Sub oscillation

Sub oscillation circuit selected

OS

OE

circuit selected ³

D

Digital I/O

selected⁴

GPIO selected

INITX input

-

PC

HC

IS

HS

IS

HS

Digital I/O

selected

This pin is digital input pin, pull up resistor is on, and digital input

is not shut off in all CPU states.

E

F

Digital I/O

selected

This pin is digital input pin, pull up resistor is none, digital input is

not shut off in all CPU states.

MD0 input

USB I/O selected⁵

USB port selected

GPIO selected

-

UE

CP

US

HC

US

IS

US

HS

US

IS

US

HS

G

H

Digital I/O

selected⁶

IS

IE

SW selected

IS

-

IP⁷

-

PC

IP

IS

IP

IS

IP

Digital I/O

selected

GPIO selected

HC

HS

NMI selected

-

IP

IS

-

IP

-

IP

-

IP

-

Digital I/O

selected

I

WKUP0 enable and input selected

GPIO selected

IS

IE

PC

HC

Analog input

selected⁸

Analog input selected

Analog input is enabled in all CPU state

WKUP enable and input selected

External interrupt enable and input selected

-

IP

GS

IP

IS

IP

GS

J

Digital I/O

selected⁹

GPIO selected

-

PC

HC

IS

HS

GS

IS

HS

GS

Resource other than above selected

CEC pin selected

-

CP

IP

PC

CP

IP

HC

CP

IP

CP

IP

GS

CP

IP

IS

CP

IP

GS

WKUP enable and input selected

External interrupt enable and input selected

Digital I/O

selected

K

GPIO selected

IS

-

IE

-

PC

HC

IS

HS

GS

IS

HS

GS

Resource other than above selected

Terms in the table above have the following meanings.

3

In this type, when internal oscillation function is selected, digital output is disabled. (Hi-Z) pull up resistor is off, digital input is shut off by fixed 0.

In this type, when Digital I/O function is selected, internal oscillation function is disabled.

In this type, when USB I/O function is selected, digital output is disabled. (Hi-Z), digital input is shut off by fixed 0.

In this type, when Digital I/O function is selected, USB I/O function is disabled.This pin does not have pull up resistor.

In this case, PCR register is initialized to “1”. Pull up resistor is on.

4

5

6

7

8

9

In this type, when analog input function is selected, digital output is disabled, (Hi-Z). pull up resistor is off, digital input is shut off by fixed 0.

In this type, when Digital I/O function is selected, analog input function is not available.

Document Number: 002-00233 Rev. *D

Page 41 of 109

S6E1C Series

Type

This indicates a pin status type that is shown in “pin list table” in “5. List of Pin Functions”

Selected Pin function

This indicates a pin function that is selected by user program.

CPU state

This indicates a state of the CPU that is shown below.

(1)

(2)

Reset state. CPU is initialized by Power-on reset or a reset due to low Power voltage supply.

Reset state. CPU is initialized by INITX input signal or system initialization after power on reset.

(3) Run mode or SLEEP mode state.

Timer mode, RTC mode or STOP mode state.

(4)

The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0".

Timer mode, RTC mode or STOP mode state.

(5)

(6)

The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1".

Deep standby STOP mode or Deep standby RTC mode state,

The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0"

Deep standby STOP mode or Deep standby RTC mode state,

(7)

(8)

The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1"

Run mode state after returning from Deep Standby mode.

(I/O state hold function(CONTX) is fixed at 1)

Document Number: 002-00233 Rev. *D

Page 42 of 109

S6E1C Series

Each pin status

The meaning of the symbols in the pin status table is as follows.

IS

IE

Digital output is disabled. (Hi-Z) Pull up resistor is off. Digital input is shut off by fixed 0.

Digital output is disabled. (Hi-Z) Pull up resistor is off. Digital input is not shut off.

Digital output is disabled. (Hi-Z) Pull up resistor is defined by the value of the PCR register. Digital

input is not shut off.

IP

Digital output is disabled. (Hi-Z) Pull up resistor is off. Digital input is shut off in case of the OSC

stop. Digital input is not shut off in case of the OSC operation.

IE/IS

OE

The OSC is in operation state. However, it may be stopped in some operation mode of the CPU.

For detail, see chapter “Low Power Consumption Mode” in peripheral manual.

The OSC is in stop state. (Hi-Z)

OS

UE

USB I/O function is controlled by USB controller.

US

PC

USB I/O function is disabled(Hi-Z)

Digital output and pull up resistor is controlled by the register in the GPIO or peripheral function.

Digital input is not shut off

Digital output is controlled by the register in the GPIO or peripheral function. Pull up resistor is off．

Digital input is not shut off.

CP

HC

HS

GS

Digital output and pull up resistor is maintained the status that is immediately prior to entering the

current CPU state. Digital input is not shut off

Digital output and pull up resistor is maintained the status that is immediately prior to entering the

current CPU state. Digital input is shut off

Digital output and pull up resistor is copied the GPIO status that is immediately prior to entering the

current CPU state and the status is maintained. Digital input is shut off.

Document Number: 002-00233 Rev. *D

Page 43 of 109

S6E1C Series

11.Electrical Characteristics

11.1 Absolute Maximum Ratings

Parameter

Power supply voltage^{10, 11}

Analog reference voltage^{10, 12}

Rating

Symbol

Unit

Remarks

Min

V_SS- 0.5

Max

V_CC

AVRH

V_SS+ 4.6

V_CC+ 0.5

(≤ 4.6 V)

V_SS+ 6.5

V_CC+ 0.5

(≤ 4.6 V)

Vcc + 0.5

(≤ 4.6 V)

V

V_SS- 0.5

V

Input voltage¹⁰

V_I

5 V tolerant

Analog pin input voltage¹⁰

Output voltage¹⁰

V_IA

V_O

V_SS- 0.5

V

L level maximum output current¹³

L level average output current¹⁴

L level total maximum output current

L level total average output current¹⁵

H level maximum output current¹³

H level average output current¹⁴

H level total maximum output current

H level total average output current¹⁵

Power consumption

I_OL

I_OLAV

∑I_OL

∑I_OLAV

I_OH

I_OHAV

∑I_OH

∑I_OHAV

P_D

-

10

4

100

50

- 10

- 4

- 100

- 50

200

+ 150

mA

mW

°C

4 mA type

Storage temperature

T_STG

- 55

−

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of

absolute maximum ratings. Do not exceed these ratings.

10

11

12

13

14

15

These parameters are based on the condition that V_SS= 0 V.

V_CCmust not drop below V_SS- 0.5 V.

Ensure that the voltage does not to exceed V_CC+ 0.5 V at power-on.

The maximum output current is the peak value for a single pin.

The average output is the average current for a single pin over a period of 100 ms.

The total average output current is the average current for all pins over a period of 100 ms.

Document Number: 002-00233 Rev. *D

Page 44 of 109

S6E1C Series

11.2 Recommended Operating Conditions

(V_SS= 0.0 V)

Remarks

Value

Parameter

Symbol

Conditions

Unit

Min

Max

1.65¹⁶

3.6

V

Power supply voltage

V_CC

-

17

3.0

2.7

3.6

V_CC

V

V_CC≥ 2.7 V

AVRH

-

Analog reference voltage

V_CC

V_SS

1

V_CC

V_SS

10

V

μF

°C

V_CC< 2.7 V

AVRL

C_S

Ta

-

Smoothing capacitor

Operating temperature

For regulator¹⁸

- 40

+ 105

1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of

the device's electrical characteristics are warranted when the device is operated within these ranges.

2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may

adversely affect reliability and could result in device failure.

3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

4. Users considering application outside the listed conditions are advised to contact their representatives beforehand.

16

In between less than the minimum power supply voltage reset / interrupt detection voltage or more, instruction execution and low voltage detection function by

built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only.

17

When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).

See "C Pin" in "8. Handling Devices" for the connection of the smoothing capacitor.

18

Document Number: 002-00233 Rev. *D

Page 45 of 109

S6E1C Series

11.3 DC Characteristics

11.3.1 Current Rating

Symbol

HCLK

Frequency¹⁹

8 MHz

Value

Max²¹

Conditions

Unit

Remarks

Typ²⁰

1.4

(Pin Name)

8 MHz external clock input, PLL ON²²

NOP code executed

2.7

4.1

23

20 MHz

40 MHz

2.6

mA

Built-in high speed CR stopped

All peripheral clock stopped by CKENx

8 MHz external clock input, PLL ON²²

Benchmark code executed

3.9

5.6

8 MHz

1.3

2.3

2.6

3.8

Run mode,

code executed

from Flash

23

20 MHz

mA

Built-in high speed CR stopped

PCLK1 stopped

8 MHz crystal oscillation, PLL ON²²

40 MHz

3.4

5.1

8 MHz

1.6

2.8

3.0

4.4

NOP code executed

23 24

20 MHz

,

Built-in high speed CR stopped

All peripheral clock stopped by CKENx

8 MHz external clock input, PLL ON²²

NOP code executed

Built-in high speed CR stopped

All peripheral clock stopped by CKENx

40 MHz

4.1

5.9

8 MHz

1.0

1.7

2.1

2.9

Run mode,

23

20 MHz

code executed

Icc

from RAM

40 MHz

2.7

4.0

(VCC)

8 MHz external clock input, PLL ON

NOP code executed

Run mode,

code executed

from Flash

23 25 26

40 MHz

1.6

3.1

mA

,

Built-in high speed CR stopped

PCLK1 stopped

Built-in high speed CR²⁷

NOP code executed

23

8 MHz

32 kHz

100 kHz

1.1

240

246

2.4

mA

μA

All peripheral clock stopped by CKENx

32 kHz crystal oscillation

Run mode,

code executed

from Flash

1264

1271

NOP code executed

All peripheral clock stopped by CKENx

Built-in low speed CR

NOP code executed

All peripheral clock stopped by CKENx

8 MHz

20 MHz

40 MHz

0.8

1.3

1.8

1.9

2.4

3.0

8 MHz external clock input, PLL ON²²

All peripheral clock stopped by CKENx

23

mA

Built-in high speed CR²⁷

23

8 MHz

32 kHz

100 kHz

0.6

237

238

1.7

mA

μA

Iccs

Sleep

All peripheral clock stopped by CKENx

(VCC)

operation

32 kHz crystal oscillation

1261

1262

All peripheral clock stopped by CKENx

Built-in low speed CR

All peripheral clock stopped by CKENx

19

20

21

22

23

24

25

26

27

PCLK0 is set to divided rate 8.

T_A=+25°C,V_CC=3.3 V

T_A=+105°C,V_CC=3.6 V

When HCLK=8, PLL is off.

All ports are fixed

When IMAINSEL bit (MOSC_CTL:IMAINSEL) is “10” (default).

Flash sync down is set to FRWTR.RWT=111 and FSYNDN.SD=1111

VCC=1.65 V

The frequency is set to 8 MHz by trimming

Document Number: 002-00233 Rev. *D

Page 46 of 109

S6E1C Series

Symbol

(Pin

Name)

Value

Parameter

Conditions

Unit

μA

Remarks

Typ

Max

Ta=25℃

Vcc=3.3 V

28 29

12.4

52.4

,

I_CCH

(VCC)

Ta=25℃

Vcc=1.65 V

28 29

Stop mode

12.0

-

52.0

597

μA

,

Ta=105℃

Vcc=3.6 V

28 29

μA

,

Ta=25℃

Vcc=3.3 V

32 kHz Crystal

oscillation

Ta=25℃

Vcc=1.65 V

32 kHz Crystal

oscillation

28 29

15.6

15.0

-

55.6

55.0

601

μA

,

I_CCT

(VCC)

28 29

Sub timer mode

,

Power

supply

current

Ta=105℃

Vcc=3.6 V

32 kHz Crystal

oscillation

28 29

,

Ta=25℃

Vcc=3.3 V

32 kHz Crystal

oscillation

28 29

13.2

12.7

-

53.2

52.7

598

,

Ta=25℃

I_CCR

(VCC)

Vcc=1.65 V

32 kHz Crystal

oscillation

28 29

RTC mode

,

Ta=105℃

Vcc=3.6 V

32 kHz Crystal

oscillation

28 29

,

28

29

All ports are fixed. LVD off. Flash off.

When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added.

Document Number: 002-00233 Rev. *D

Page 47 of 109

S6E1C Series

Symbol

(Pin

Value

Max

Parameter

Conditions

Unit

Remarks

Typ

0.58

0.56

-

Name)

Ta=25°C

Vcc=3.3 V

Ta=25°C

Vcc=1.65 V

Ta=105°C

Vcc=3.6 V

Ta=25°C

Vcc=3.3 V

Ta=25°C

Vcc=1.65 V

Ta=105°C

Vcc=3.6 V

Ta=25°C

Vcc=3.3 V

Ta=25°C

Vcc=1.65 V

Ta=105°C

Vcc=3.6 V

Ta=25°C

Vcc=3.3 V

Ta=25°C

30 31

1.85

1.83

46

μA

,

30, 31

RAM off

I_CCHD

(VCC)

Deep standby

Stop mode

0.78

0.76

-

6.6

88

RAM on

RAM off

RAM on

Power

supply

current

1.16

1.15

-

2.4

46

I_CCRD

(VCC)

Deep standby

RTC mode

1.37

1.35

-

7.2

88

Vcc=1.65 V

Ta=105°C

Vcc=3.6 V

30

31

All ports are fixed. LVD off.

When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added.

Document Number: 002-00233 Rev. *D

Page 48 of 109

S6E1C Series

LVD Current

Parameter

(V_CC=1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Name

Symbol

Conditions

Unit

Remarks

Typ

Max

Low-Voltage

0.15

0.3

μA

For occurrence of reset

detection circuit

(LVD) power

supply current

I_CCLVD

VCC

At operation

For occurrence of

interrupt

0.10

0.3

μA

Bipolar Vref Current

(V_CC=1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

I_CCBGR

Conditions

Unit

Remarks

Name

Typ

Max

Bipolar Vref

Current

VCC

At operation

100

200

μA

Flash Memory Current

(V_CC=1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Name

Parameter

Flash

Symbol

Conditions

Unit

Remarks

Typ

Max

memory

write/erase

current

I_CCFLASH

VCC

At Write/Erase

4.4

5.6

mA

A/D converter Current

(V_CC=1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Name

Parameter

Symbol

Conditions

Unit

Remarks

Typ

Max

Power supply

current

I_CCAD

VCC

At operation

0.5

0.75

mA

Reference

power supply

current

At operation

At stop

0.69

0.1

1.3

mA

AVRH=3.6 V

I_CCAVRH

AVRH

μA

(AVRH)

Document Number: 002-00233 Rev. *D

Page 49 of 109

S6E1C Series

Peripheral Current Dissipation

(V_CC=1.65 V to 3.6 V, V_SS=0 V, T_A=- 40°C to +105°C)

Frequency (MHz)

20

Clock

Peripheral

System

Conditions

Unit

mA

Remarks

8

40

At all ports

operation

At 2ch

GPIO

0.05

0.12

0.06

0.13

0.05

0.10

0.03

0.05

0.08

0.23

HCLK

DSTC

USB

0.02

0.13

0.02

0.04

0.01

0.02

0.04

0.10

0.13

0.10

0.21

0.06

0.08

0.18

operation

At 1ch

32

operation

At 4ch

Base timer

ADC

operation

At 1 unit

operation

At 1ch

PCLK1

Multi-function serial

MFS-I2S

mA

operation

At 1ch

operation

At 1ch

Smart Card I/F

operation

32

USB itself uses 48 MHz clock

Document Number: 002-00233 Rev. *D

Page 50 of 109

S6E1C Series

11.3.2 Pin Characteristics

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Pin Name

Conditions

V_CC≥ 2.7 V

V_CC< 2.7 V

Unit

Remarks

Min

Typ

Max

CMOS

hysteresis

input pin,

MD0

V_CC× 0.8

H level input

voltage

(hysteresis

input)

-

V_CC+0.3

V

V_IHS

V_CC× 0.7

V_CC≥ 2.7 V

V_CC× 0.8

V_CC× 0.7

5 V tolerant

input pin

-

V_SS+5.5

V

V_CC< 2.7 V

CMOS

hysteresis

input pin,

MD0

V_CC≥ 2.7 V

V_CC× 0.2

V_CC× 0.3

V_SS- 0.3

V

L level input

voltage

(hysteresis

input)

V_CC< 2.7 V

V_ILS

V_CC≥ 2.7 V

-

V_CC× 0.2

V_CC× 0.3

5 V tolerant

input pin

V

V_CC< 2.7 V

V_CC≥ 2.7 V,

I_OH= - 4 mA

V_CC- 0.5

H level

output voltage

V_OH

4 mA type

-

V_CC

0.4

V_CC< 2.7 V,

I_OH= - 2 mA

V_CC- 0.45

V_CC≥ 2.7 V,

I_OL4 mA

L level

output voltage

V_OL

V_SS

V

V_CC< 2.7 V,

I_OL=2 mA

Input leak

current

I_IL

-

- 5

21

-

33

-

+ 5

48

88

μA

kΩ

Pull-up

resistance

value

V_CC≥ 2.7 V

V_CC< 2.7 V

R_PU

Pull-up pin

Other than

VCC, VSS,

AVRH

Input

capacitance

C_IN

-

5

15

pF

Document Number: 002-00233 Rev. *D

Page 51 of 109

S6E1C Series

11.4 AC Characteristics

11.4.1 Main Clock Input Characteristics

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

V_CC≥ 2.7V

V_CC< 2.7V

8

48

20

When the crystal

oscillator is connected

MHz

ns

Input frequency

Input clock cycle

F_CH

When the external

clock is used

-

8

48

X0,

X1

When the external

clock is used

t_CYLH

-

20.83

125

Input clock pulse

width

PWH/tCYLH,

PWL/tCYLH

When the external

clock is used

When the external

clock is used

45

-

55

5

%

Input clock rising

time and falling time

t_CF,

t_CR

-

ns

F_CM

F_CC

-

40.8

-

MHz

ns

Master clock

-

Base clock (HCLK/FCLK)

APB0 bus clock³⁴

APB1 bus clock³⁴

Master clock

Internal operating

clock³³frequency

F_CP0

F_CP1

-

24.5

t_CYCCM

t_CYCC

t_CYCP0

t_CYCP1

-

24.5

-

ns

Base clock (HCLK/FCLK)

APB0 bus clock³⁴

APB1 bus clock³⁴

Internal operating

clock³³cycle time

X0

33

34

For details of each internal operating clock, refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".

For details of the APB bus to which a peripheral is connected, see the Peripheral Address Map.

Document Number: 002-00233 Rev. *D

Page 52 of 109

S6E1C Series

11.4.2 Sub Clock Input Characteristics³⁵

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Typ

Max

When the crystal

oscillator is

-

32.768

-

kHz

connected

When the external

clock is used

When the external

clock is used

When the external

clock is used

Input frequency

Input clock cycle

f_CL

-

32

10

45

-

100

31.25

55

kHz

μs

X0A,

X1A

t_CYLL

-

Input clock pulse

width

PWH/tCYLL,

PWL/tCYLL

%

X0A

35

See "Sub crystal oscillator" in "11. Handling Devices" for the crystal oscillator used.

Document Number: 002-00233 Rev. *D

Page 53 of 109

S6E1C Series

11.4.3 Built-in CR Oscillation Characteristics

Built-in High-Speed CR

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Typ

Max

Ta = - 10°C to + 105°C,

7.92

8

8.08

MHz

Clock frequency

F_CRH

After trimming³⁶

Ta = - 40°C to + 105°C,

-

7.84

-

8

-

8.16

300

MHz

Frequency

stabilization time

37

t_CRWT

μs

Built-in Low-Speed CR

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Typ

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Clock frequency

f_CRL

-

50

100

150

kHz

36

37

In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming.

This is time from the trim value setting to stable of the frequency of the High-speed CR clock.

After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.

Document Number: 002-00233 Rev. *D

Page 54 of 109

S6E1C Series

11.4.4 Operating Conditions of Main PLL

(In the Case of Using the Main Clock as the Input Clock of the PLL)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Typ

Parameter

Symbol

Unit

Remarks

Min

Max

PLL oscillation stabilization wait time³⁸

(LOCK UP time)

t_LOCK

50

-

μs

PLL input clock frequency

PLL multiple rate

F_PLLI

-

8

5

-

16

18

MHz

multiple

MHz

PLL macro oscillation clock frequency

Main PLL clock frequency³⁹

USB clock frequency⁴⁰

F_PLLO

F_CLKPLL

F_CLKSPLL

75

-

150

40

MHz

-

48

MHz

Main PLL connection

Main PLL

clock

PLL input

clock

PLL macro

Main clock (CLKMO)

oscillation clock

(CLKPLL)

K

M

Main

PLL

High-speed CR clock (CLKHC)

divider

N

divider

USB clock

USB

clock

divider

11.4.5 Operating Conditions of Main PLL

(In the Case of Using the Built-in High-Speed CR Clock as the Input Clock of the Main PLL)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Typ

Parameter

Symbol

Unit

Remarks

Min

Max

PLL oscillation stabilization wait time⁴¹

(LOCK UP time)

t_LOCK

50

-

μs

PLL input clock frequency

PLL multiple rate

F_PLLI

-

7.84

9

8

-

8.16

18

MHz

multiple

MHz

PLL macro oscillation clock frequency

Main PLL clock frequency⁴²

F_PLLO

F_CLKPLL

75

-

150

40.8

-

MHz

Note:

−

For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency and temperature have been trimmed.

When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the

master clock from exceeding the maximum frequency.

38

39

40

41

42

The wait time is the time it takes for PLL oscillation to stabilize.

For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".

For more information about USB clock, see "Chapter: USB Clock Generation" in "FM0+ Family Peripheral Manual Communication Macro Part”.

The wait time is the time it takes for PLL oscillation to stabilize.

For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".

Document Number: 002-00233 Rev. *D

Page 55 of 109

S6E1C Series

11.4.6 Reset Input Characteristics

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Reset input time

t_INITX

INITX

-

500

-

ns

11.4.7 Power-on Reset Timing

(V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Typ

Name

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

V_CCmust be held

below 0.2V for a

minimum period of

t_OFF. Improper

initialization may

occur if this

Power supply shut down time

t_OFF

-

2

-

ms

condition is not

met.

VCC

This dV/dt

characteristic is

1000 mV/μs applied at the

power-on of cold

Vcc: 0.2V to

1.65V

Power ramp rate

dV/dt

t_PRT

0.6

-

start (t_OFF>2ms).

Time until releasing

Power-on reset

-

0.43

3.4

ms

1.65V

V_DH

V_CC

0.2V

dV/dt

tPRT

tOFF

Internal RST

release

start

RST Active

CPU Operation

Glossary

 VDH: detection voltage of Low-Voltage detection reset. See "11.7 Low-Voltage Detection Characteristics".

Document Number: 002-00233 Rev. *D

Page 56 of 109

S6E1C Series

11.4.8 Base Timer Input Timing

Timer Input Timing

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Pin Name

Conditions

Unit

Remarks

Min

Max

TIOAn/TIOBn

(when using as

ECK, TIN)

Input pulse width

t_TIWH, t_TIWL

-

2 t_CYCP

-

ns

t_TIWH

t_TIWL

ECK

TIN

V_IHS

V_ILS

Trigger Input Timing

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Pin Name

Conditions

Unit

Remarks

Min

Max

TIOAn/TIOBn

(when using as

TGIN)

Input pulse width

t_TRGH, t_TRGL

-

2 t_CYCP

-

ns

t_TRGH

t_TRGL

V_IHS

TGIN

V_ILS

Note:

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map

−

".

Document Number: 002-00233 Rev. *D

Page 57 of 109

S6E1C Series

11.4.9 CSIO/SPI/UART Timing

CSIO (SPI=0, SCINV=0)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

V_CC≥ 2.7 V

name

-

Parameter

Symbol

Conditions

Unit

Min

Max

Min

Max

Baud rate

-

8

-

8

Mbps

ns

Serial clock cycle time

t_SCYC

SCKx

4 t_CYCP

-

4 t_CYCP

-

SCKx,

SOTx

SCKx,

SINx

SCKx,

SINx

SCK ↓ → SOT delay time

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK ↓ → SOT delay time

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

t_SLOVI

t_IVSHI

t_SHIXI

t_SLSH

t_SHSL

t_SLOVE

t_IVSHE

t_SHIXE

- 30

50

0

+ 30

- 20

36

0

+ 20

ns

Master mode

-

2 t_CYCP

10

-

2 t_CYCP

10

t_CYCP

10

-

SCKx

-

+

t_CYCP+ 10

-

SCKx,

SOTx

SCKx,

SINx

SCKx,

SINx

-

50

-

30

-

Slave mode

10

20

10

20

-

SCK falling time

SCK rising time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above AC characteristics are for clock synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

The characteristics are applicable only when the relocate port numbers are the same.

For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.

External load capacitance C_L=30 pF

Document Number: 002-00233 Rev. *D

Page 58 of 109

S6E1C Series

t_SCYC

V_OH

SCK

SOT

V_OL

t_SLOVI

V_OH

V_OL

t_IVSHI

V_IH

V_IL

t_SHIXI

V_IH

V_IL

SIN

Master mode

t_SLSH

t_SHSL

V_IH

t_R

V_IH

t_F

V_IH

SCK

V_IL

t_SLOVE

V_OH

V_OL

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

Document Number: 002-00233 Rev. *D

Page 59 of 109

S6E1C Series

CSIO (SPI=0, SCINV=1)

Parameter

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7V

V_CC≥ 2.7V

name

-

Symbol

Conditions

Unit

Min

Max

8

-

Min

Max

8

-

Baud rate

Serial clock cycle time

-

Mbps

ns

t_SCYC

SCKx

4 t_CYCP

SCKx,

SOTx

SCK ↑ → SOT delay time

t_SHOVI

- 30

+ 30

- 20

+ 20

ns

Master mode

SCKx,

SINx

SCKx,

SINx

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

t_IVSLI

t_SLIXI

50

0

-

36

0

-

ns

2 t_CYCP

10

t_CYCP+ 10

-

2 t_CYCP

10

t_CYCP+ 10

-

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK ↑ → SOT delay time

t_SLSH

t_SHSL

SCKx

-

ns

SCKx

SCKx,

SOTx

SCKx,

SINx

t_SHOVE

-

50

-

33

Slave mode

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

t_IVSLE

t_SLIXE

10

20

-

10

20

-

ns

SCKx,

SINx

SCK falling time

SCK rising time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above AC characteristics are for clock synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

The characteristics are applicable only when the relocate port numbers are the same.

For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.

External load capacitance C_L=30 pF

Document Number: 002-00233 Rev. *D

Page 60 of 109

S6E1C Series

t_SCYC

V_OH

SCK

V_OL

t_SHOVI

V_OH

V_OL

SOT

SIN

t_IVSLI

V_IH

V_IL

t_SLIXI

V_IH

V_IL

Master mode

t_SHSL

t_SLSH

V_IH

t_F

SCK

V_IL

t_R

V_IL

t_SHOVE

V_OH

V_OL

SOT

SIN

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

Document Number: 002-00233 Rev. *D

Page 61 of 109

S6E1C Series

SPI (SPI=1, SCINV=0)

Parameter

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

V_CC≥ 2.7 V

name

-

Symbol

Conditions

Unit

Min

Max

Min

Max

Baud rate

Serial clock cycle time

-

8

-

8

-

Mbps

ns

t_SCYC

SCKx

4 t_CYCP

SCKx,

SOTx

SCK ↑ → SOT delay time

t_SHOVI

- 30

+ 30

- 20

+ 20

ns

SCKx,

SINx

SCKx,

SINx

SCKx,

SOTx

SIN → SCK ↓ setup time

SCK ↓→ SIN hold time

SOT → SCK ↓ delay time

t_IVSLI

t_SLIXI

t_SOVLI

50

0

-

36

0

-

ns

Master mode

2 t_CYCP

30

-

2 t_CYCP

30

-

2 t_CYCP

10

t_CYCP+ 10

-

2 t_CYCP

10

t_CYCP+ 10

-

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK ↑ → SOT delay time

t_SLSH

t_SHSL

SCKx

-

ns

SCKx

SCKx,

SOTx

SCKx,

SINx

t_SHOVE

-

50

-

33

Slave mode

SIN → SCK ↓ setup time

SCK ↓→ SIN hold time

t_IVSLE

t_SLIXE

10

20

-

10

20

-

ns

SCKx,

SINx

SCK falling time

SCK rising time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above AC characteristics are for clock synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

The characteristics are applicable only when the relocate port numbers are the same.

For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.

External load capacitance C_L=30 pF

Document Number: 002-00233 Rev. *D

Page 62 of 109

S6E1C Series

t_SCYC

V_OH

SCK

V_OL

t_SHOVI

t_SOVLI

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSLI

t_SLIXI

V_IH

V_IL

V_IH

V_IL

Master mode

t_SLSH

t_SHSL

V_IH

t_F

V_IH

SCK

SOT

SIN

V_IL

t_R

t_SHOVE

*

V_OH

V_OL

V_OH

V_OL

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

*: Changes when writing to TDR register

Document Number: 002-00233 Rev. *D

Page 63 of 109

S6E1C Series

SPI (SPI=1, SCINV=1)

Parameter

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

V_CC≥ 2.7 V

name

-

Symbol

Conditions

Unit

Min

Max

Min

Max

Baud rate

Serial clock cycle time

-

8

-

8

-

Mbps

ns

t_SCYC

SCKx

4 t_CYCP

SCKx,

SOTx

SCK ↓ → SOT delay time

t_SLOVI

- 30

+ 30

- 20

+ 20

ns

SCKx,

SINx

SCKx,

SINx

SCKx,

SOTx

Master mode

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

SOT → SCK ↑ delay time

t_IVSHI

t_SHIXI

t_SOVHI

50

0

-

36

0

-

ns

2 t_CYCP

30

-

2 t_CYCP

30

-

2 t_CYCP

10

t_CYCP+ 10

-

2 t_CYCP

10

t_CYCP+ 10

-

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK ↓ → SOT delay time

t_SLSH

t_SHSL

SCKx

-

ns

SCKx

SCKx,

SOTx

SCKx,

SINx

t_SLOVE

-

50

-

33

Slave mode

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

t_IVSHE

t_SHIXE

10

20

-

10

20

-

ns

SCKx,

SINx

SCK falling time

SCK rising time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above AC characteristics are for clock synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

The characteristics are applicable only when the relocate port numbers are the same.

For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.

External load capacitance C_L=30 pF

Document Number: 002-00233 Rev. *D

Page 64 of 109

S6E1C Series

t_SCYC

V_OH

SCK

V_OL

t_SOVHI

t_SLOVI

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_SHIXI

t_IVSHI

V_IH

V_IL

V_IH

V_IL

Master mode

t_R

t_F

t_SHSL

t_SLSH

V_IH

SCK

V_IL

t_SLOVE

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

Document Number: 002-00233 Rev. *D

Page 65 of 109

S6E1C Series

When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=1)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

V_CC≥ 2.7 V

Parameter

Symbol

Conditions

Unit

Min

Max

Min

Max

SCS↓→SCK↓ setup time

SCK↑→SCS↑ hold time

SCS deselect time

t_CSSI

t_CSHI

t_CSDI

t_CSSE

t_CSHE

t_CSDE

t_DSE

-50⁴³

+0⁴⁴

-50⁴⁵

+0⁴³

+50⁴⁴

-50⁴³

+0⁴⁴

-50⁴⁴

+0⁴³

+50⁴⁴

ns

Master mode

SCS↓→SCK↓ setup time

SCK↑→SCS↑ hold time

SCS deselect time

3t_CYCP+30

-

3t_CYCP+30

-

0

Slave mode

3t_CYCP+30

-

3t_CYCP+30

-

SCS↓→SOT delay time

SCS↑→SOT delay time

-

55

-

40

-

t_DEE

0

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".

These characteristics guarantee only the same relocate port number.

For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.

−

When the external load capacitance C_L=30 pF.

43

44

45

CSSU bit value × serial chip select timing operating clock cycle.

CSHD bit value × serial chip select timing operating clock cycle.

CSDS bit value × serial chip select timing operating clock cycle.

Irrespective of CSDS bit setting, 5t_CYCPor more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip

select pin becomes active again.

Document Number: 002-00233 Rev. *D

Page 66 of 109

S6E1C Series

SCSO

SCK

tCSSI

tCSDI

tCSHI

SOT

(SPI=0)

SOT

(SPI=1)

Master mode

SCSI

SCK

tCSSE

tCSDE

tCSHE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

Slave mode

Document Number: 002-00233 Rev. *D

Page 67 of 109

S6E1C Series

When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=1)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

V_CC≥ 2.7 V

Parameter

Symbol

Conditions

Unit

Min

Max

Min

Max

SCS↓→SCK↑ setup time

SCK↓→SCS↑ hold time

SCS deselect time

t_CSSI

t_CSHI

t_CSDI

t_CSSE

t_CSHE

t_CSDE

t_DSE

-50⁴⁶

+0⁴⁷

-50⁴⁸

+0⁴⁶

+50⁴⁷

+50⁴⁸

-50⁴⁶

+0⁴⁷

-50⁴⁸

+0⁴⁶

+50⁴⁷

+50⁴⁸

ns

Master mode

SCS↓→SCK↑ setup time

SCK↓→SCS↑ hold time

SCS deselect time

3t_CYCP+30

-

3t_CYCP+30

-

0

Slave mode

3t_CYCP+30

-

3t_CYCP+30

-

SCS↓→SOT delay time

SCS↑→SOT delay time

-

55

-

40

-

t_DEE

0

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".

These characteristics guarantee only the same relocate port number.

For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.

−

When the external load capacitance C_L=30 pF.

46

47

48

CSSU bit value × serial chip select timing operating clock cycle.

CSHD bit value × serial chip select timing operating clock cycle.

CSDS bit value × serial chip select timing operating clock cycle.

Irrespective of CSDS bit setting, 5t_CYCPor more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip

select pin becomes active again.

Document Number: 002-00233 Rev. *D

Page 68 of 109

S6E1C Series

SCSO

SCK

tCSSI

tCSDI

tCSHI

SOT

(SPI=0)

SOT

(SPI=1)

Master mode

SCSI

SCK

tCSSE

tCSDE

tCSHE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

Slave mode

Document Number: 002-00233 Rev. *D

Page 69 of 109

S6E1C Series

When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=0)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

V_CC≥ 2.7 V

Parameter

Symbol

Conditions

Unit

Min

Max

Min

Max

SCS↑→SCK↓ setup time

SCK↑→SCS↓ hold time

SCS deselect time

t_CSSI

t_CSHI

t_CSDI

t_CSSE

t_CSHE

t_CSDE

t_DSE

-50⁴⁹

+0⁵⁰

-50⁵¹

+0⁴⁹

+50⁵⁰

+50⁵¹

-50⁴⁹

+0⁵⁰

-50⁵¹

+0⁴⁹

+50⁵⁰

+50⁵¹

ns

Master mode

SCS↑→SCK↓ setup time

SCK↑→SCS↓ hold time

SCS deselect time

3t_CYCP+30

-

3t_CYCP+30

-

0

Slave mode

3t_CYCP+30

-

3t_CYCP+30

-

SCS↑→SOT delay time

SCS↓→SOT delay time

-

55

-

40

-

t_DEE

0

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

For information About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".

These characteristics guarantee only the same relocate port number.

For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.

−

When the external load capacitance C_L=30 pF.

49

50

51

CSSU bit value × serial chip select timing operating clock cycle.

CSHD bit value × serial chip select timing operating clock cycle.

CSDS bit value × serial chip select timing operating clock cycle.

Irrespective of CSDS bit setting, 5t_CYCPor more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip

select pin becomes active again.

Document Number: 002-00233 Rev. *D

Page 70 of 109

S6E1C Series

tCSDI

SCSO

SCK

tCSSI

tCSHI

SOT

(SPI=0)

SOT

(SPI=1)

Master mode

tCSDE

SCSI

SCK

tCSSE

tCSHE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

Slave mode

Document Number: 002-00233 Rev. *D

Page 71 of 109

S6E1C Series

When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=0)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

V_CC≥ 2.7 V

Parameter

Symbol

Conditions

Unit

Min

Max

Min

Max

SCS↑→SCK↑ setup time

SCK↓→SCS↓ hold time

SCS deselect time

t_CSSI

t_CSHI

t_CSDI

t_CSSE

t_CSHE

t_CSDE

t_DSE

-50⁵²

+0⁵³

-50⁵⁴

+0⁵²

+50⁵³

+50⁵⁴

-50⁵²

+0⁵³

-50⁵⁴

+0⁵²

+50⁵³

+50⁵⁴

ns

Master mode

SCS↑→SCK↑ setup time

SCK↓→SCS↓ hold time

SCS deselect time

3t_CYCP+30

-

3t_CYCP+30

-

0

Slave mode

3t_CYCP+30

-

3t_CYCP+30

-

SCS↑→SOT delay time

SCS↓→SOT delay time

-

55

-

40

-

t_DEE

0

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

−

For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".

These characteristics guarantee only the same relocate port number.

For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.

−

When the external load capacitance C_L=30 pF.

52

53

54

CSSU bit value × serial chip select timing operating clock cycle.

CSHD bit value × serial chip select timing operating clock cycle.

CSDS bit value × serial chip select timing operating clock cycle.

Irrespective of CSDS bit setting, 5t_CYCPor more are required for the period the time when the serial chip select pin becomes inactive to the time when the serial chip

select pin becomes active again.

Document Number: 002-00233 Rev. *D

Page 72 of 109

S6E1C Series

tCSDI

SCSO

SCK

tCSSI

tCSHI

SOT

(SPI=0)

SOT

(SPI=1)

Master mode

tCSDE

SCSI

SCK

tCSSE

tCSHE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

Slave mode

Document Number: 002-00233 Rev. *D

Page 73 of 109

S6E1C Series

UART external clock input (EXT=1)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Serial clock L pulse width

Serial clock H pulse width

SCK falling time

t_SLSH

t_SHSL

t_F

t_CYCP+10

-

ns

t_CYCP+10

C_L=30 pF

-

5

SCK rising time

t_R

t_F

t_SHSL

t_SLSH

V_IH

SCK

V_IL

Document Number: 002-00233 Rev. *D

Page 74 of 109

S6E1C Series

11.4.10 External Input Timing

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Min

Parameter

Symbol

Pin Name

Conditions

Unit

Remarks

Max

A/D converter

trigger input

55

ADTGx

-

2 t_CYCP

-

ns

Input pulse width

t_INH,t_INL

56

57

INT00 to INT08,

INT12, INT13,

INT15, NMIX

2 t_CYCP+100⁵⁵

500

-

ns

External

interrupt, NMI

Deep standby

wake up

58

WKUPx

500

-

ns

55

56

57

58

t_CYCPindicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

In Run mode and Sleep mode

In Timer mode, RTC mode and Stop mode

In Deep Standby RTC mode and Deep Standby Stop mode

Document Number: 002-00233 Rev. *D

Page 75 of 109

S6E1C Series

11.4.11 I²C Timing

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Standard-Mode

Fast-Mode

Min Max

Parameter

Symbol

F_SCL

Conditions

Unit

kHz

μs

Remarks

Min

Max

SCL clock frequency

(Repeated) Start condition hold time

SDA ↓ → SCL ↓

0

100

0

400

t_HDSTA

4.0

-

0.6

-

SCL clock L width

t_LOW

t_HIGH

4.7

4.0

-

1.3

0.6

-

μs

SCL clock H width

(Repeated) Start setup time

SCL ↑ → SDA ↓

Data hold time

SCL ↓ → SDA ↓ ↑

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTO

4.7

0

-

0.6

0

-

μs

ns

μs

C_L=30 pF,

3.45⁶⁰

0.9⁶¹

59

R=(Vp/I_OL

)

Data setup time

250

4.0

-

100

0.6

-

SDA ↓ ↑ → SCL ↑

Stop condition setup time

SCL ↑ → SDA ↑

Bus free time between

Stop condition and

Start condition

t_BUF

t_SP

4.7

2

-

1.3

2

-

μs

Noise filter

-

ns

62

t_CYCP

".

To use Standard-mode, set the APB bus clock at 2 MHz or more.

To use Fast-mode, set the APB bus clock at 8 MHz or more.

SDA

SCL

59

R represents the pull-up resistance of the SCL and SDA lines, and C_Lthe load capacitance of the SCL and SDA lines. V_Prepresents the power supply voltage of the

pull-up resistance, and I_OLthe V_OLguaranteed current.

60

The maximum t_HDDATmust satisfy at least the condition that the period during which the device is holding the SCL signal at L (t_LOW) does not extend.

61

A Fast-mode I²C bus device can be used in a Standard-mode I²C bus system, provided that the condition of t_SUDAT≥ 250 ns is fulfilled.

62

t_CYCPrepresents the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see the Peripheral Address Map.

Document Number: 002-00233 Rev. *D

Page 76 of 109

S6E1C Series

11.4.12 I²S Timing (MFS-I2S Timing)

Master Mode Timing

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

V_CC< 2.7 V

Min Max

V_CC≥ 2.7 V

Min Max

Symbo

Condition

s

Parameter

Pin Name

Unit

l

F_MI2SCK

t_ICYC

∆

MI2SCK max frequency⁶³

I²S clock cycle time⁶³

I²S clock Duty cycle

MI2SCK↓ → MI2SWS delay

time

MI2SCK↓ → MI2SDO delay

time

MI2SDI → MI2SCK ↑ setup

time

MI2SCK ↑ → MI2SDI hold

time

MI2SCK falling time

MI2SCK rising time

MI2SCKx

MI2SCKx,

MI2SWSx

MI2SCKx,

MI2SDOx

MI2SCKx,

MI2SDIx

MI2SCKx,

MI2SDIx

MI2SCKx

-

6.144

-

55%

-

6.144

-

55%

MHz

ns

4 t_CYCP

45%

4 t_CYCP

45%

t_SWDT

t_SDDT

t_DSST

t_SDHT

-30

50

0

+30

-20

36

0

+20

ns

+30

+20

C_L=30 pF

-

tF

tR

-

5

-

5

ns

VIH

MI2SCK

VIL

tF

tR

t_SWDT,

t_SDDT

MI2SWS

and

MI2SDO

VOH

VOL

t_DSST

t_SDHT

VIH

MI2SDI

VIL

63

I²S clock should meet the multiple of PCLK(t_ICYC) and the frequency less than F_MI2SCKmeantime. The detail information please refer to Chapter I²S of Communication

Macro Part of the Peripheral Manual.

Document Number: 002-00233 Rev. *D

Page 77 of 109

S6E1C Series

MI2SMCK Input Characteristics

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Input frequency

Symbol

Pin Name Conditions

Unit

Remarks

Min

Max

f_CHS

MI2SMCK

-

12.288

MHz

Input clock cycle

t_CYLHS

-

t_CFS

-

81.3

45

-

ns

%

P_WHS/t_CYLHS

P_WLS/t_CYLHS

When using

external clock

When using

external clock

Input clock pulse width

55

Input clock rise time and

fall time

-

5

ns

t_CRS

MI2SMCK Output Characteristics

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Pin Name Conditions

Unit

Remarks

Min

Max

-

25

MHz

V_CC≥ 2.7 V

Output frequency

f_CHS

MI2SMCK

-

20

MHz

V_CC< 2.7 V

Document Number: 002-00233 Rev. *D

Page 78 of 109

S6E1C Series

11.4.13 Smart Card Interface Characteristics

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Pin Name

Conditions

Unit

Remarks

Min

Max

ICx_VCC,

ICx_RST,

ICx_CLK,

ICx_DATA

Output rising time

t_R

4

20

ns

Output falling time

t_F

C_L=30 pF

4

20

ns

Output clock frequency

Duty cycle

f_CLK

-

20

MHz

ICx_CLK

∆

45%

55%

External pull-up resistor (20 kΩ to 50 kΩ) must be applied to ICx_CIN pin when it’s used as smart card reader function.

Document Number: 002-00233 Rev. *D

Page 79 of 109

S6E1C Series

11.4.14 SW-DP Timing

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Parameter

Symbol

Pin Name

Conditions

Unit

Remarks

Min

Max

SWCLK,

SWDIO

SWDIO setup time

t_SWS

-

15

-

ns

SWCLK,

SWDIO

SWDIO hold time

t_SWH

t_SWD

-

15

-

ns

SWCLK,

SWDIO

SWDIO delay time

45

Note:

−

External load capacitance C_L=30 pF

SWCLK

SWDIO

(When input)

SWD

SWDIO

(When output)

Document Number: 002-00233 Rev. *D

Page 80 of 109

S6E1C Series

11.5 12-bit A/D Converter

Electrical Characteristics of A/D Converter (Preliminary Values)

(V_CC= 1.65 V to 3.6 V, V_SS= 0 V, T_A=- 40°C to +105°C)

Value

Typ

-

Parameter

Resolution

Integral Nonlinearity

Differential Nonlinearity

Zero transition voltage

Symbol

Pin Name

Unit

Remarks

Min

-

- 4.5

- 2.5

- 15

Max

12

4.5

+ 2.5

+ 15

-

bit

LSB

mV

V_ZT

ANxx

Full-scale transition voltage

V_FST

ANxx

AVRH - 15

-

AVRH + 15

mV

1.0

4.0

10

-

V_CC≥ 2.7 V

Conversion time⁶⁴

-

μs

1.8 ≤ V_CC< 2.7 V

1.65 ≤ V_CC< 1.8 V

V_CC≥ 2.7 V

0.3

1.2

3.0

50

Sampling time⁶⁵

Ts

-

10

μs

1.8 ≤ V_CC< 2.7 V

1.65 ≤ V_CC< 1.8 V

V_CC≥ 2.7 V

Compare clock cycle⁶⁶

Tcck

1000

1.0

ns

200

500

1.8 ≤ V_CC< 2.7 V

1.65 ≤ V_CC< 1.8 V

State transition time to

operation permission

Analog input capacity

Tstt

-

μs

C_AIN

7.5

2.2

pF

V_CC≥ 2.7 V

1.8 ≤ V_CC< 2.7 V

1.65 ≤ V_CC< 1.8 V

Analog input resistance

R_AIN

-

kΩ

5.5

10.5

4

Interchannel disparity

Analog port input leak

current

-

LSB

μA

V

ANxx

5

Analog input voltage

V_SS

2.7

V_CC

V_SS

AVRH

V_CC

VCC ≥ 2.7V

VCC < 2.7V

-

AVRH

AVRL

-

V

Reference voltage

V_SS

64

The conversion time is the value of sampling time (t_S) + compare time (t_C).

The minimum conversion time is computed according to the following conditions:

V_CC≥ 2.7 V

1.8 ≤ V_CC< 2.7 V

1.65 ≤ V_CC< 1.8 V

sampling time=0.3 μs, compare time=0.7 μs

sampling time=1.2 μs, compare time=2.8 μs

sampling time=3.0 μs, compare time=7.0 μs

Ensure that the conversion time satisfies the specifications of the sampling time (t_S) and compare clock cycle (t_CCK).

For details of the settings of the sampling time and compare clock cycle, refer to "Chapter: A/D Converter" in "FM0+ Family Peripheral Manual Analog Macro Part".

The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.

For the number of the APB bus to which the A/D Converter is connected, see the Peripheral Address Map.

The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.

65

The required sampling time varies according to the external impedance. Set a sampling time that satisfies (Equation 1).

The compare time (t_C) is the result of (Equation 2).

66

Document Number: 002-00233 Rev. *D

Page 81 of 109

S6E1C Series

ANxx

Analog input pins

Comparator

R_EXT

R_AIN

Analog signal

source

C_AIN

(Equation 1) t_S≥ (R_AIN+ R_EXT) × C_AIN× 9

t_S:

Sampling time

R_AIN

:

Input resistance of A/D Converter = 2.2 kΩ with 2.7 < VCC < 3.6

Input resistance of A/D Converter = 5.5 kΩ with 1.8 < VCC < 2.7

Input resistance of A/D Converter = 10.5 kΩ with 1.65 < VCC < 1.8

Input capacitance of A/D Converter = 7.5 pF with 1.65 < VCC < 3.6

Output impedance of external circuit

C_AIN

:

R_EXT

:

(Equation 2) t_C=t_CCK× 14

t_C:

t_CCK

Compare time

:

Compare clock cycle

Document Number: 002-00233 Rev. *D

Page 82 of 109

S6E1C Series

Definitions of 12-bit A/D Converter Terms

Resolution:

Analog variation that is recognized by an A/D converter.

Integral Nonlinearity:

Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the

full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion

characteristics.

Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.

Integral Nonlinearity

Differential Nonlinearity

0xFFF

Actual conversion

characteristics

0xFFE

0xFFD

0x(N+1)

0xN

characteristics

{1 LSB(N-1) + V_ZT}

V_FST

Ideal characteristics

(Actually-

measured

value)

V_NT

0x004

(Actually-measured

value)

V_(N+1)T

(Actually-measured

value)

0x(N-1)

0x(N-2)

0x003

0x002

Actual conversion

characteristics

V_NT

(Actually-measured

value)

Ideal characteristics

0x001

(Actually-measured value)

Analog input

V_ZT

Actual conversion characteristics

V_SS

AVRH

V_SS

AVRH

Analog input

V_NT- {1LSB × (N - 1) + V_ZT}

1LSB

Integral Nonlinearity of digital output N =

Differential Nonlinearity of digital output N =

[LSB]

V_{(N + 1) T}- V_NT

- 1 [LSB]

1LSB

V_FST– V_ZT

1LSB =

4094

N

V_ZT

V_FST

V_NT

: A/D converter digital output value.

: Voltage at which the digital output changes from 0x000 to 0x001.

: Voltage at which the digital output changes from 0xFFE to 0xFFF.

: Voltage at which the digital output changes from 0x(N − 1) to 0xN.

Document Number: 002-00233 Rev. *D

Page 83 of 109

S6E1C Series

11.6 USB Characteristics

(V_CC=3.0 V to 3.6 V, V_SS=0 V, T_A=- 40°C to +105°C)

Value

Schematic

Parameter

Symbol

VIH

Conditions

Unit

V

Name

Min

Max

Reference

V_CC

+

1

Input H level voltage

-

2.0

0.3

V_SS

0.3

0.2

0.8

–

1

Input

Input L level voltage

characteristics

VIL

-

0.8

V

Differential input sensitivity

VDI

-

V

2

3

Differential common mode range

VCM

-

2.5

External pull-down

resistance = 15 kΩ

External pull-up

resistance = 1.5 kΩ

-

Output H level voltage

VOH

VOL

2.8

0.0

3.6

0.3

V

3

UDP0,

UDM0

Output L level voltage

Crossover voltage

VCRS

tFR

1.3

4

2.0

20

V

4

5

6

7

Rising time

Full-speed

Low-speed

ns

%

Ω

Output

Falling time

tFF

4

20

characteristic

Rising/Falling time matching

Output impedance

Rising time

tFRFM

ZDRV

tLR

90

28

75

80

111.11

44

300

125

ns

%

Falling time

tLF

Rising/Falling time matching

tLRFM

1. The switching threshold voltage of single-end-receiver of USB I/O buffer is set as within VIL(Max)=0.8 V, VIH(Min)=2.0 V (TTL

input standard).

There is some hysteresis to lower noise sensitivity.

2. Use differential-receiver to receive USB differential data signal.

Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local

ground reference level.

Above voltage range is the common mode input voltage range.

1.0

0.2

0.8

2.5

Common mode input voltage [V]

Document Number: 002-00233 Rev. *D

Page 84 of 109

S6E1C Series

3. The output drive capability of the driver is below 0.3 V at Low-state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the

VSS and 1.5 kΩ load) at high-state (VOH)

4. The cross voltage of the external differential output signal (D+ / D-) of USB I/O buffer is within 1.3 V to 2.0 V.

D+

Max 2.0V

VCRS specified range

Min 1.3V

D-

5. They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.

They are defined by the time between 10% and 90% of the output signal voltage.

For full-speed buffer, Tr/Tf ratio is regulated as within ±10% to minimize RFI emission.

D+

90%

10%

D-

Trise

Tfall

Rising time

Falling time

Full-speed buffer

Rs=27 Ω

TxD+

CL=50 pF

Rs=27 Ω

TxD-

3-state enable

6. USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential

Mode).

USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs)

addition is defined to satisfy the above definition and keep balance.

When using this USB I/O, use it with 25 Ω to 33 Ω (recommendation value: 27 Ω) series resistor Rs.

Document Number: 002-00233 Rev. *D

Page 85 of 109

S6E1C Series

Full-speed buffer

Rs

TxD+

28 Ω to 44 Ω equivalent impedance

TxD-

28 Ω to 44 Ω equivalent impedance

Mount it as external resistance.

3-state enable

Rs series resistor 25 Ω to 30 Ω

Series resistor of 27 Ω (recommendation value) must be added.

And, use “resistance with an uncertainty of 5% by E24 sequence”.

7. They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.

They are defined by the time between 10% and 90% of the output signal voltage.

D+

90%

10%

D-

Tfall

Trise

Falling time

Rising time

See “Low-speed load (Compliance Load)” for conditions of external load.

Document Number: 002-00233 Rev. *D

Page 86 of 109

S6E1C Series

・Low-Speed Load (Upstream Port Load) – Reference 1

Low-speed buffer

Rs=27 Ω

TxD+

CL=50 pF to 150 pF

Rpd

Rs=27 Ω

TxD-

CL=50 pF to 150 pF

Rpd

3-state enable

Rpd=15 kΩ

・Low-Speed Load (Downstream Port Load) – Reference 2

Low-speed buffer

Rs=27 Ω

VTERM

TxD+

CL=200 pF to

600 pF

Rs=27 Ω

TxD-

CL=50 pF to 150 pF

Rpu=1.5 kΩ

VTERM=3.6 V

3-state enable

Document Number: 002-00233 Rev. *D

Page 87 of 109

S6E1C Series

・Low-Speed Load (Compliance Load)

Low-speed buffer

Rs=27 Ω

TxD+

CL=200 pF to 450 pF

TxD-

CL=200 pF to 450 pF

3-state enable

Document Number: 002-00233 Rev. *D

Page 88 of 109

S6E1C Series

11.7 Low-Voltage Detection Characteristics

11.7.1 Low-Voltage Detection Reset

(T_A=-40°C to +105°C)

Value

Typ

1.50

Parameter

Symbol

Conditions

Unit

Remarks

Min

1.38

1.43

Max

1.60

1.65

Detected voltage

Released voltage

VDL

VDH

V

When voltage drops

When voltage rises

Fixed⁶⁷

1.55

LVD stabilization wait

time

8160×

t_CYCP

T_LVDW

-

μs

68

LVD detection delay

time

T_LVDDL

-

200

67

68

The value of low voltage detection reset is always fixed.

t_CYCPindicates the APB1 bus clock cycle time.

Document Number: 002-00233 Rev. *D

Page 89 of 109

S6E1C Series

11.7.2 Low-Voltage Detection Interrupt

(T_A=-40°C to +105°C)

Value

Typ

Parameter

Symbol

Conditions

Unit

Remarks

Min

1.56

1.61

1.66

1.70

1.75

1.79

1.84

1.89

1.93

2.30

2.39

2.48

2.58

2.67

2.76

2.85

2.94

3.04

Max

1.84

1.89

1.94

2.00

2.05

SVHI=00100

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.50

2.60

2.70

2.80

2.90

3.00

3.10

3.20

3.30

V

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

SVHI=00101

SVHI=00110

SVHI=00111

SVHI=01000

SVHI=01001

SVHI=01010

SVHI=01011

SVHI=01100

SVHI=01101

SVHI=01110

SVHI=01111

SVHI=10000

SVHI=10001

SVHI=10010

SVHI=10011

2.11

2.16

2.21

2.27

2.70

2.81

2.92

3.02

3.13

3.24

3.35

3.46

3.56

8160

×

LVD stabilization wait

time

T_LVDW

T_LVDDL

-

μs

69

t_CYCP

LVD detection delay

time

200

69

t_CYCPrepresents the APB1 bus clock cycle time.

Document Number: 002-00233 Rev. *D

Page 90 of 109

S6E1C Series

11.8 Flash Memory Write/Erase Characteristics

(V_CC=1.65 V to 3.6 V, T_A=- 40°C to +105°C)

Value⁷⁰

Typ

Parameter

Unit

Remarks

Min

Max

Large

sector

Small

sector

-

1.1

2.7

The sector erase time includes the time of

writing prior to internal erase.

Sector erase time

s

-

0.3

30

0.9

528

11.7

The halfword (16-bit) write time excludes the

system-level overhead.

The chip erase time includes the time of

writing prior to internal erase.

Halfword (16-bit) write time

Chip erase time

μs

4.5

s

Write/Erase Cycle and Data Hold Time

Write/Erase Cycle

Data Hold Time (Year)

Remarks

These values come from the technology qualification

(using Arrhenius equation to translate high

temperature acceleration test result into average

temperature value at +85°C).

1,000

20

10

10,000

70

The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.

Document Number: 002-00233 Rev. *D

Page 91 of 109

S6E1C Series

11.9 Return Time from Low-Power Consumption Mode

11.9.1 Return Factor: Interrupt/WKUP

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the

program operation.

Return Count Time

(V_CC=1.65 V to 3.6 V, T_A=-40°C to +105°C)

Parameter

Value

Symbol

Unit

Remarks

When

High-speed CR

is enabled

Current Mode

Sleep mode

Mode to return

Typ

Max⁷¹

each Run Mode

4*HCLK

μs

High-speed CR Run mode

Main Run mode

When

High-speed CR

is enabled

12*HCLK

13*HCLK

μs

PLL Run mode

Timer mode

Stop Mode

RTC mode

Low-speed CR Run mode

Sub Run mode

High-speed CR Run mode

Low-speed CR Run mode

Main Run mode

Sub Run mode

PLL Run mode

High-speed CR Run mode

Low-speed CR Run mode

Sub Run mode

34+12*HCLK

72+13*HCLK

μs

t_ICNT

34+12*HCLK

72+13*HCLK

72

μs

+tOSCWT

34+12*HCLK

72+13*HCLK

Main Run mode

PLL Run mode

34+12*HCLK

72+13*HCLK

μs

+tOSCWT

Deep Standby RTC mode

Deep Standby Stop mode

High-speed CR Run mode

43

281

Operation Example of Return from Low-Power Consumption Mode (by External Interrupt⁷³)

External

interrupt

Interrupt factor

Active

accept

t_ICNT

Interrupt factor

clear by CPU

CPU

Operation

Start

71

72

73

The maximum value depends on the condition of environment.

t_OSCWT: Oscillator stabilization time.

External interrupt is set to detecting fall edge.

Document Number: 002-00233 Rev. *D

Page 92 of 109

S6E1C Series

Operation Example of Return from Low-Power Consumption Mode (by Internal Resource Interrupt⁷⁴)

Internal

resource

interrupt

Interrupt factor

accept

Active

t_ICNT

Interrupt factor

clear by CPU

CPU

Operation

Start

Notes:

−

The return factor is different in each Low-Power consumption modes.

See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual.

−

When interrupt recovers, the operation mode that CPU recovers depends on the state before the Low-Power consumption

mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual".

74

Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.

Document Number: 002-00233 Rev. *D

Page 93 of 109

S6E1C Series

11.9.2 Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program

operation.

Return Count Time

(V_CC=1.65 V to 3.6 V, T_A=-40°C to +105°C)

Parameter

Value

Symbol

Unit

Remarks

When

High-speed CR

is enabled

When

Current Mode

Mode to return

Typ

Max⁷⁵

High-speed CR Sleep mode

Main Sleep mode

20

22

μs

PLL Sleep mode

Low-speed CR Sleep mode

Sub Sleep mode

50

106

137

μs

High-speed CR

is enabled

When

High-speed CR

is enabled

112

When

High-speed CR

is enabled

High-speed CR Timer mode

Main Timer mode

PLL Timer mode

High-speed CR Run mode

t_RCNT

20

22

μs

Low-speed CR Timer mode

Sub Timer mode

87

159

209

μs

148

Stop mode

RTC mode

Deep Standby RTC mode

Deep Standby Stop mode

45

43

68

μs

281

Operation Example of Return from Low-Power Consumption Mode (by INITX)

INITX

Internal reset

Reset active

Release

t_RCNT

CPU

Operation

Start

75

The maximum value depends on the accuracy of built-in CR.

Document Number: 002-00233 Rev. *D

Page 94 of 109

S6E1C Series

Operation Example of Return from Low Power Consumption Mode (by Internal Resource Reset⁷⁶)

Internal

resource

reset

Internal reset

Reset active

Release

t_RCNT

CPU

Operation

Start

Notes:

−

The return factor is different in each Low-Power consumption modes.

See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual.

When interrupt recovers, the operation mode that CPU recovery depends on the state before the Low-Power consumption

mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual".

The time during the power-on reset/low-voltage detection reset is excluded. See "11.4.7 Power-on Reset Timing in 11.4 AC

Characteristics in 11. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection

reset.

−

When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is

necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.

The internal resource reset means the watchdog reset and the CSV reset.

76

Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.

Document Number: 002-00233 Rev. *D

Page 95 of 109

S6E1C Series

12.Ordering Information

Package-Specific

Features

(see next table)

Flash

Part number

SRAM

[Kbyte]

Package

(Tray)

USB2.0

I²S

[Kbyte]



S6E1C32D0AGV20000

S6E1C31D0AGV20000

128

64

16

12

16

12

16

12

16

12

16

12

16

12

Plastic  LQFP

(0.50 mm pitch),

64 pins

64-pin

48-pin

32-pin

64-pin

48-pin

32-pin



(LQD064)

S6E1C32C0AGV20000

S6E1C31C0AGV20000

128

64

Plastic  LQFP

(0.50 mm pitch),

48 pins

(LQA048)

S6E1C32B0AGP20000

S6E1C31B0AGP20000

128

64

Plastic  LQFP

(0.80 mm pitch),

32 pins

(LQB032)



S6E1C32D0AGN20000

S6E1C31D0AGN20000

128

64

Plastic  QFN64

(0.50 mm pitch),

64 pins

(WNS064)

S6E1C32C0AGN20000

S6E1C31C0AGN20000

128

64

Plastic  QFN48

(0.50 mm pitch),

48 pins

(WNY048)

S6E1C32B0AGN20000

S6E1C31B0AGN20000

128

64

Plastic  QFN32

(0.50 mm pitch),

32 pins

(WNU032)

S6E1C32B0AGU1H000

Plastic  WLCSP30

(0.40 mm pitch),

30 pins



128

16

30-pin

(U4M030)

* 7 inch reel only for

this MPN



S6E1C12D0AGV20000

S6E1C11D0AGV20000

128

64

16

12

16

12

16

12

16

12

16

12

16

12

Plastic  LQFP

(0.50 mm pitch),

64 pins

64-pin

48-pin

32-pin

64-pin

48-pin

32-pin

(LQD064)

S6E1C12C0AGV20000

S6E1C11C0AGV20000

128

64

Plastic  LQFP

(0.50 mm pitch),

48 pins

(LQA048)

S6E1C12B0AGP20000

S6E1C11B0AGP20000

128

64

Plastic  LQFP

(0.80 mm pitch),

32 pins

(LQB032)

S6E1C12D0AGN20000

S6E1C11D0AGN20000

128

64



Plastic  QFN64

(0.50 mm pitch),

64 pins

(WNS064)

S6E1C12C0AGN20000

S6E1C11C0AGN20000

128

64

Plastic  QFN48

(0.50 mm pitch),

48 pins

(WNY048)

S6E1C12B0AGN20000

S6E1C11B0AGN20000

128

64

Plastic  QFN32

(0.50 mm pitch),

32 pins

(WNU032)

Document Number: 002-00233 Rev. *D

Page 96 of 109

S6E1C Series

Package

Feature

32 LQFP

32 QFN

48 LQFP

48 QFN

64 LQFP

64 QFN

30 WLCSP

Pin count

30

32

48

64

4 ch. (Max)

6 ch. (Max)

Ch.0/1/3 without FIFO

Ch. 6 with FIFO

Ch.0/1/3 without FIFO Ch.0/1/3 without FIFO

Multi-function Serial Interface

(UART/CSIO/I²C/I²S)

Ch.4/6/7 with FIFO

I²S: 1 ch (Max)

Ch. 6 with FIFO

I²S: 2 ch (Max)

Ch. 4/6 with FIFO

I²S: No

7 pins (Max),

NMI x 1

9 pins (Max),

NMI x 1

12 pins (Max),

NMI x 1

External Interrupt

I/O port

24 pins (Max)

6 ch. (1 unit)

38 pins (Max)

8 ch. (1 unit)

54 pins (Max)

8 ch. (1 unit)

12-bit A/D converter

Smart Card Interface

No

1 ch (Max)

HDMI-CEC/ Remote Control

Receiver

1 ch.(Max)

Ch.1

2 ch (Max)

Ch.0/1

13.Acronyms

Acronym

Description

ADC

ACK

analog-to-digital converter

acknowledge

AHB

ARM^®

AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus

Advanced RISC Machine, a CPU architecture

Consumer Electronics Control, a command and control interface over HDMI (High Definition Multimedia

Interface)

CEC

CMOS

CPU

complementary metal oxide semiconductor

central processing unit

CR

clock and reset

CRC

CSIO

CSV

cyclic redundancy check, an error-checking protocol

clock synchronous serial interface

clock supervisor

CTS

clear to send, a flow control signal in some data communication interfaces

descriptor system data transfer controller

end of message

first in, first out

general-purpose input/output

High Definition Multimedia Interface

High Definition Multimedia Interface - Consumer Electronics Control, see CEC

interface

Inter-Integrated Circuit, a communications protocol

Inter-IC (integrated circuit) Sound, a communications protocol

input/output, see also GPIO

DTSC

EOM

FIFO

GPIO

HDMI

HDMI-CEC

I/F

I²C, or IIC

I²S, or IIS

I/O

IRQ

interrupt request

LIN

LVD

Local Interconnect Network, a communications protocol

low-voltage detect

MFS

multi-function serial

MSB

MTB

most significant byte

micro trace buffer

NMI

non-maskable interrupt

Document Number: 002-00233 Rev. *D

Page 97 of 109

S6E1C Series

Acronym

NVIC

OS

Description

nested vectored interrupt controller

operating system

OSC

PLL

oscillator

phase-locked loop

PPG

PWC

PWM

RAM

RX

programmable pulse generator

pulse-width counter

pulse-width modulator

random access memory

receive

RTS

SPI

SRAM

SW-DP

TX

request to send, a flow control signal in some data communication interfaces

Serial Peripheral Interface, a communications protocol

static random access memory

serial wire debug port

transmit

UART

USB

universal asynchronous receiver transmitter

Universal Serial Bus

Document Number: 002-00233 Rev. *D

Page 98 of 109

S6E1C Series

14.Package Dimensions

Package Type

Package Code

LQFP-32

LQB032

4

D

5

7

D1

24

17

24

25

16

E1

E

5

4

7

3

6

32

9

32

1

8

1

2

5

7

e

BOTTOM VIEW

0.10

C

A-B

D

3

0.20

C

A-B D

b

0.20

C

A-B

D

8

TOPVIEW

2

9

θ

c

b

SECTION A-A'

A

SEATING

PLANE

A'

0.25

0.10

C

10

SIDEVIEW

DIMENSIONS

SYMBOL

MIN. NOM. MAX.

1.60

A

A1

b

0.05

0.32

0.13

0.15

0.35 0.43

0.18

c

D

9.00 BSC

D1

e

7.00 BSC

0.80 BSC

9.00 BSC

7.00 BSC

E

E1

L

0.45 0.60 0.75

0.30 0.50 0.70

L1

θ

0°

8°

PACKAGE OUTLINE, 32 LEAD LQFP

7.0X7.0X1.6 MM LQB032 REV*.*

002-13879 **

Document Number: 002-00233 Rev. *D

Page 99 of 109

S6E1C Series

Package Type

Package Code

LQFP-48

LQA048

4

5

D

7

D1

36

25

37

24

37

E1

E

5

7

4

3

6

48

13

48

1

12

2

A-B

5

7

e

0.10

C

D

3

0.20

C A-B D

0.80

C

A-B

D

b

8

2

A

9

θ

A

SEATING

PLANE

c

A'

0.25

A1

10

b

0.80

C

L1

L

SECTION A-A'

DIMENSIONS

MIN. NOM. MAX.

1.70

SYMBOL

A

A1

b

0.00

0.20

0.27

0.20

0.15

0.09

c

D

9.00 BSC

7.00 BSC

0.50 BSC

9.00 BSC

7.00 BSC

0.60

D1

e

E

E1

L

0.45

0.30

0°

0.75

0.70

L1

θ

0.50

8°

PACKAGE OUTLINE, 48 LEAD LQFP

7.0X7.0X1.7 MM LQA048 REV**

002-13731 **

Page 100 of 109

Document Number: 002-00233 Rev. *D

S6E1C Series

Package Type

Package Code

LQFP-64

LQD064

4

5

D

7

D1

48

33

48

32

49

5

7

E1

E

4

3

6

17

64

1

16

1

2

5

7

e

A-B D

3

0.10

0.08

C A-B D

BOTTOM VIEW

0.20

C

A-B

D

b

8

TOPVIEW

2

A

9

c

A

SEATING

PLANE

b

0.25

A'

A1

SECTION A-A'

L1

0.08

C

L

10

SIDE VIEW

DIMENSIONS

SYMBOL

MIN. NOM. MAX.

1.70

A

A1

b

0.00

0.15

0.09

0.20

0.2

c

0.20

D

12.00 BSC.

10.00 BSC.

0.50 BSC

D1

e

E

12.00 BSC.

10.00 BSC.

E1

L

0.45 0.60 0.75

0.30 0.50 0.70

L1

PACKAGE OUTLINE, 64 LEAD LQFP

10.0X10.0X1.7 MM LQD064 Rev**

002-11499 **

Page 101 of 109

Document Number: 002-00233 Rev. *D

S6E1C Series

Package Type

Package Code

QFN-32

WNU032

D

0.10

C A B

D2

A

17

24

0.10

2X

C

0.10

C A B

16

25

(ND-1)× e

E

E2

5

9

32

c

8

1

9

INDEX MARK

8

L

0.10

0.05

C A B

e

b

B

C

0.10

2X

C

4

BOTTOM VIEW

TOP VIEW

0.10

C

A

SEATING PLANE

0.08

9

C

A1

C

SIDE VIEW

NOTE

1. ALL DIMENSIONSARE IN MILLIMETERS.

DIMENSIONS

NOM. MAX.

SYMBOL

A

2. DIMENSIONING AND TOLERANCIN C CONFORMSTO ASME Y14.5-1994.

3. N ISTHE TOTAL NU MBER OF TERMINALS.

MIN.

0.80

0.05

4. DIMENSION "b"APPLIESTO META

LLIZED TERMINAL AND ISMEASURED

A

D

E

0.00

1

BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS

THE OPTIONAL RADIUSON THE OTHER END OF THE TERMINAL. THE

DIMENSION "b"SHOULD NOTBE MEASURED IN THATRADIUSAREA.

5.00 BSC

0.25

5. ND REFERTO THE NUMBER OF

TERMINALSON D OR E SIDE.

0.20

0.30

b

6. MAX. PACKAGE WARPAGE IS0.05mm.

D

3.20 BSC

0.50 BSC

0.25 REF

0.40

2

7. MAXIMUM ALLOWABL E BURRSIS0.076mm IN ALL DIRECTIONS.

8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.

E

e

c

9. BILATERAL COPLAN ARITY ZONE APPLIESTO THE EXPOSED HEAT

SINK SLUG ASWELL ASTHE TERMINALS.

10. JEDEC SPEC IFICATION NO. REF : N/A

L

0.35

0.45

PACKAGEOUTLINE, 32 LEAD QFN

5.00X5.00X0.80MM WNU032 3.20X3.20MMEPAD(SAWN)REV**

002-15907 **

Page 102 of 109

Document Number: 002-00233 Rev. *D

S6E1C Series

Package Type

Package Code

QFN-48

WNY048

0.15

C

A B

D

D2

A

25

36

0.10

2X

C

24

37

0.15

C A B

(ND-1)× e

E2

E

5

13

48

9

c

12

1

INDEX MARK

8

L

b

e

0.10

0.05

C

A B

B

0.10

2X

C

TOP VIEW

4

BOTTOM VIEW

A

SEATING PLANE

0.05

C

A1

9

C

SIDE VIEW

NOTE

1. ALLDIMENSIONSAREIN MILLIMETERS.

DIMENSIONS

SYMBOL

A

2. DIMENSIONING AND TOLERANCING CONFORMSTO ASME Y14.5-1994.

3. N ISTHETOTALNUMBEROFTERMINALS.

MIN. NOM. MAX.

0.80

4. DIMENSION "b"APPLIESTO METALLIZED TERMINALAND ISMEASURED

BETWEEN 0.15 AND 0.30mm FROM TERMINALTIP.IFTHETERMINALHAS

THEOPTIONALRADIUSON THEOTHEREND OFTHETERMINAL. THE

DIMENSION "b"SHOULD NOTBEMEASURED IN THATRADIUSAREA.

A

D

E

0.00

0.05

1

7.00 BSC

0.25

5. ND REFERTO THENUMBEROFTERMINALSON D ORESIDE.

6. MAX. PACKAGEWARPAGEIS0.05mm.

0.18

0.30

b

D

4.65 BSC

0.50 BSC

0.30 REF

0.50

2

7. MAXIMUM ALLOWABLEBURRSIS0.076mm IN ALLDIRECTIONS.

8. PIN #1 ID ON TOPW ILLBE LOCATED WITHIN INDICATED ZONE.

E

e

c

9. BILATERALCOPLANARITY ZONEAPPLIESTO THEEXPOSEDHEAT

SINKSLUG ASWELLASTHETERMINALS.

10. JEDECSPECIFICATION NO. REF: N/A

L

0.45

0.55

PACKAGEOUTLINE, 48 LEAD QFN

7.00X7.00X0.80MM WNY0484.65X4.65MMEPAD(SAWN)REV**

002-16422 **

Page 103 of 109

Document Number: 002-00233 Rev. *D

S6E1C Series

Package Type

Package Code

QFN-64

WNS064

0.15

C A B

D2

D

A

33

48

0.10

2X

C

0.15

C A B

32

49

(ND-1)× e

E

E2

5

17

64

c

16

1

INDEX MARK

8

L

9

b

e

0.10

C

A B

B

0.05

0.10

2X

C

4

TOPVIEW

BOTTOM VIEW

A

SEATING PLANE

0.05

C

A1

9

C

SIDEVIEW

NOTE

1. ALLDIMENSIONSAREIN MILLIMETERS.

DIMENSIONS

SYMBOL

A

2. DIMENSIONING AND TOLERANCING CONFORMSTO ASME Y14.5-1994.

3. N ISTHETOTALNUMBEROFTERMINALS.

MIN. NOM. MAX.

0.80

4. DIMENSION "b"APPLIESTO METALLIZED TERMINALAND ISMEASURED

BETWEEN 0.15 AND 0.30mm FROM TERMINALTIP.IFTHETERMINALHAS

THEOPTIONALRADIUSON THEOTHEREND OFTHETERMINAL. THE

DIMENSION "b"SHOULD NOTBEMEASURED IN THATRADIUSAREA.

A

1

0.00

0.05

D

E

b

9.00 BSC

0.25

5. ND REFERTO THENUMBEROFTERMINALSON D ORESIDE.

6. MAX. PACKAGEWARPAGEIS0.05mm.

0.20

0.30

D

E

e

7.20 BSC

0.50 BSC

0.50 REF

0.40

2

7. MAXIMUM ALLOWABLEBURRSIS0.076mm IN ALLDIRECTIONS.

8. PIN #1 ID ON TOPW ILLBE LOCATED WITHIN INDICATED ZONE.

9. BILATERALCOPLANARITY ZONEAPPLIESTO THEEXPOSEDHEAT

SINKSLUG ASWELLASTHETERMINALS.

c

10. JEDECSPECIFICATION NO. REF: N/A

L

0.35

0.45

PACKAGEOUTLINE, 64 LEAD QFN

9.00X9.00X0.80MM WNS0647.20X7.20MMEPAD(SAWN)REV**

002-16424 **

Page 104 of 109

Document Number: 002-00233 Rev. *D

S6E1C Series

Package Type

Package Code

WLCSP 30

U4M030

A

D1

D

eD

INDEX MARK

8

7

1

2

3

4

5

SE

PIN A1

CORNER

eE

E

E1

0.03

2X

C

F

E

D

C

B

A

B

7

SD

0.03

2X

C

TOP VIEW

30×φ ｂ

0.05

C A B

6

BOTTOM VIEW

DETAIL A

A

A2

0.05

C

A1

DETAIL A

SIDE VIEW

DIMENSIONS

NOTES

1. ALL DIMENSIONSARE IN MILLIMETERS.

SYMBOL

MIN. NOM. MAX.

0.534

2. DIMENSIONSAND TOLERANCESMETHODSPERASME Y14.5-2009.

THISOUTLINE CONFORMSTO JEP95, SECTION 4.5.

A

0.164

0.224

A1

D

3. BALL POSITION DESIGNATION PERJEP95, SECTION 3, SPP-010.

4. "e" REPRESENTSTHE SOLDERBALL GRID PITCH.

2.690 BSC

2.310 BSC

2.000 BSC

1.600 BSC

6

E

5. SYMBOL "MD"ISTHE BALL MATRIX SIZE IN THE "D"DIRECTION.

SYMBOL "ME"ISTHE BALL MATRIX SIZE IN THE "E"DIRECTION.

n ISTHE NUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX

SIZE MD X ME.

D

E

1

6. DIMENSION "b"ISMEASURED ATTHE MAXIMUM BALL DIAMETER

IN A PLANE PARALLEL TO DATUM C.

MD

ME

n

5

7. "SD" AND "SE" ARE MEASURED WITH RESPECTTO DATUMSA AND BAND

DEFINE THE POSITION OF THE CENTERSOLDERBALL IN THE OUTERROW.

WHEN THERE ISAN ODD NUMBEROF SOLDERBALLSIN THE OUTERROW

"SD"OR "SE"= 0.

30

φb

0.24

0.27

0.30

WHEN THERE ISAN EVEN NUMBEROF SOLDERBALLSIN THE OUTERROW,

"SD"= eD/2 AND "SE" = eE/2.

eD

eE

0.400 BSC

0.40 BSC

8. A1 CORNERTO BE IDENTIFIED BY CHAMFER, LASERORINK MARK.

METALLIZED MARK IN DENTATION OROTHERMEANS.

SD /SE

0.20 /0 BSC

9. "+"INDICATESTHE THEORETICAL CENTEROF DEPOPULATED BALLS.

10. JEDEC SPECIFICATION NO. REF: N/A.

PACKAGE OUTLINE, 30 BALLWLCSP

2.31X2.69X0.534 MM U4M030

^Rev0^**02-18455 **

Document Number: 002-00233 Rev. *D

Page 105 of 109

S6E1C Series

15.Errata

This chapter describes the errata for S6E1C product family. Details include errata trigger conditions, scope of impact, available

workaround, and silicon revision applicability.

Contact your local Cypress Sales Representative if you have questions.

15.1 Part Numbers Affected

Part Number

S6E1C32D0AGV20000, S6E1C32C0AGV20000, S6E1C32B0AGP20000,

S6E1C32D0AGN20000, S6E1C32C0AGN20000, S6E1C32B0AGN20000

S6E1C32B0AGU1H000

S6E1C31D0AGV20000, S6E1C31C0AGV20000, S6E1C31B0AGP20000,

S6E1C31D0AGN20000, S6E1C31C0AGN20000, S6E1C31B0AGN20000

S6E1C12D0AGV20000, S6E1C12C0AGV20000, S6E1C12B0AGP20000,

S6E1C12D0AGN20000, S6E1C12C0AGN20000, S6E1C12B0AGN20000

S6E1C11D0AGV20000, S6E1C11C0AGV20000, S6E1C11B0AGP20000,

S6E1C11D0AGN20000, S6E1C11C0AGN20000, S6E1C11B0AGN20000

15.2 Qualification Status

Product Status: In Production − Qual.

15.3 Errata Summary

This table defines the errata applicability to available devices.

Items

Part Number

Silicon Revision

Fix Status

[1] AHB Bus Matrix issue

Refer to 15.1

Rev B

Fixed in Rev C

[2] Deep Standby Mode current

consumption issue

Refer to 15.1

Rev B, Rev C

Next silicon is not planned.

15.4 Errata Detail

15.4.1 AHB Bus Matrix issue

PROBLEM DEFINITION

The AHB Bus Matrix logic has two master interfaces (CPU and DSTC) and four slave interfaces (RAM, FLASH, AHB and APB).

When two master interfaces (CPU and DSTC) access the same slave interface at the same time, and when the CPU is in wait cycle,

an unnecessary access occurs during the wait cycle and the expected access occurs again after the unnecessary access.

PARAMETERS AFFECTED

N/A

TRIGGER CONDITION(S)

CPU and DSTC access the same slave interface at the same time.

SCOPE OF IMPACT

DSTC cannot be used.

WORKAROUND

DSTC must not use.

Document Number: 002-00233 Rev. *D

Page 106 of 109

S6E1C Series

FIX STATUS

This issue is fixed in Rev C.

15.4.2 Deep Standby Mode current consumption issue

PROBLEM DEFINITION

The current consumption does not decrease in Deep Standby Mode (Deep Standby RTC Mode and Deep Standby Stop Mode)

PARAMETERS AFFECTED

N/A

TRIGGER CONDITION(S)

MCU is in Deep Standby Mode and both MAINXC bits in SPSR and SUBXC bits in SUBOSC_CTL has not been cleared with 0b00

since power-on.

SCOPE OF IMPACT

The current consumption does not decrease.

WORKAROUND

Clear both MAINXC bits in SPSR and SUBXC bits in SUBOSC_CTL with 0b00.

Please note:

- Output pins become unstable state in a moment right after clearing these register bits with 0b00.

- You can set these register bits to any value after they are cleared with 0b00.

FIX STATUS

The user uses the workaround to prevent this issue. The next silicon fixing this issue is not planned.

Document Number: 002-00233 Rev. *D

Page 107 of 109

S6E1C Series

Document History

Document Title: S6E1C Series 32-bit ARM^®Cortex^®-M0+ FM0+ Microcontroller

Document Number: 002-00233

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

4896074

4955136

TEKA

08/31/2015 New Spec.

*A

TEKA

10/9/2015

AC/DC characteristics updated. Typo fixed in “List of Pin Functions”.

Added the frequency value of “Ta = - 10°C to + 105°C” on “11.4.3 Built-in

CR Oscillation Characteristics”.

Added the remark of “VCC < 0.2V” on “11.4.7 Power-on Reset Timing”.

Added the measure condition of ICC on “11.3.1 Current Rating”.

*B

5158709

YUKT

03/04/2016

Changed the package outlines to cypress format on “13. Package

Dimensions”.

Changed the package codes to cypress codes on “3. Pin Assignment” and

“12. Ordering Information”.

Consolidated the C Series of Cypress MCUs into one data sheet. Minor

updates to grammar. Made table footnotes consectutive. Corrected

navigational aids (cross reference link colors). Added front matter to data

sheet to match Cypress corporate style. Added tables to differentiate parts

in 2 Product Lineup and 2.1 Package Dependent Features. Removed full

multiplexed signal names from 4 Pin Assignment drawings. Added

hyperlinks to 5 List of Pin Functions.

10 Pin Status in Each CPU State: Changed several instances of pullup

register to pull up resistor.

*C

5220682

MBGR

09/07/2016

Expanded 12 Ordering Information.

Fixed typo in Memory Map. Updated logo. Removed WLCSP information.

Updated 11.4.7 Power-on Reset Timing.

Added 15 Erratta.

Added 13 Acronyms.

Updated “15 Errata”(Page 106)

Updated the schematic for “11.4.7 Power-on Reset Timing”(Page 56)

Updated “14. Package Dimensions” (Page 99-105)

Modify expressions of channel numbers for USB, I²S (Page 1)

Added the Baud rate spec in “11.4.9 CSIO/SPI/UART Timing”.(Page 58, 60,

62, 64)

*D

5453786

YSKA

04/13/2017

Modify typo about Main oscillation (Page 41)

Modified Real-Time Clock(RTC) in “3. Product Features in Detail”

Deleted “second, or day of the week” in the Interrupt function.(Page 8)

Added WLCSP package information(Page 1, 6, 6, 17, 19, 96, 97, 105)

Deleted I²C slave related description(Page 4, 6, 38, 41, 76, 97)

Document Number: 002-00233 Rev. *D

Page 108 of 109

S6E1C Series

Sales, Solutions, and Legal Information

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cypress.com/support

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cypress.com/memory

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cypress.com/psoc

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ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.

All other trademarks or registered trademarks referenced herein are the property of their respective owners.

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or

other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,

then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source

code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form

externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are

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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

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is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress

products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support

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failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform

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Document Number: 002-00233 Rev. *D

April 13, 2017

Page 109 of 109


型号：	S6E1C11B0AGN20000
厂家：	Infineon
描述：	FM0+ S6E1C-Series Arm® Cortex®-M0+ Microcontroller (MCU) Family 微控制器
文件：	总111页 (文件大小：3276K)
中文：	中文翻译
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