S80KS2563GABHV023 [INFINEON]
256MBit 1.8 V Industrial (105°C) xSPI (Octal) HYPERRAM Gen 2.0 in 24 FBGA;型号: | S80KS2563GABHV023 |
厂家: | Infineon |
描述: | 256MBit 1.8 V Industrial (105°C) xSPI (Octal) HYPERRAM Gen 2.0 in 24 FBGA |
文件: | 总53页 (文件大小:871K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
S80KS2563
256 Mb: HYPERRAM™ self-refresh dynamic
RAM (DRAM) with Octal xSPI interface
1.8 V
Features
• Interface
- xSPI (Octal) interface
- 1.8 V interface support
• Single ended clock (CK) - 11 bus signals
• Optional differential clock (CK, CK#) - 12 bus signals
- Chip select (CS#)
- 8-bit data bus (DQ[7:0])
- Hardware reset (RESET#)
- Bidirectional read-write data strobe (RWDS)
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read data strobe
• Input during write transactions as write data mask
• Performance, power, and packages
- 200 MHz maximum clock rate
- DDR - transfers data on both edges of the clock
- Data throughput up to 400 MBps (3,200 Mbps)
- Configurable burst characteristics
• Linear burst
• Wrapped burst lengths:
16 bytes (8 clocks)
32 bytes (16 clocks)
64 bytes (32 clocks)
128 bytes (64 clocks)
• Hybrid option - one wrapped burst followed by linear burst
- Configurable output drive strength
- Power modes
• Hybrid sleep mode
• Deep power down
- Array refresh
• Partial memory array (1/8, 1/4, 1/2, and so on)
• Full
- Package
• 24-ball FBGA
- Operating temperature range
• Industrial (I): –40 °C to +85 °C
• Industrial Plus (V): –40 °C to +105 °C
• Automotive, AEC-Q100 Grade 3: –40 °C to +85 °C
• Automotive, AEC-Q100 Grade 2: –40 °C to +105°C
• Automotive, AEC-Q100 Grade 1: –40 °C to +125 °C
• Technology
• 25-nm DRAM
Datasheet
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Please read the Important Notice and Warnings at the end of this document
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1.8 V
Performance summary
Performance summary
Read transaction timings
Unit
200 MHz
35 ns
Maximum clock rate at 1.8 V VCC/VCCQ
Maximum access time (tACC
)
Maximum current consumption
Burst read/write (linear burst at 200 MHz)
Unit
22 mA/25 mA
1.55 mA
Standby (105 °C)
Deep power down (105 °C)
15 µA
Logic block diagram
CS#
CK/CK#
RWDS
Memory
Control
Logic
Y Decoders
Data Latch
I/O
DQ[7:0]
RESET#
Data Path
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1.8 V
Table of contents
Table of contents
1 General description.........................................................................................................................5
1.1 xSPI (Octal) interface ..............................................................................................................................................5
2 Product overview ...........................................................................................................................8
2.1 xSPI (Octal) interface ..............................................................................................................................................8
3 Signal description...........................................................................................................................9
3.1 Input/output summary...........................................................................................................................................9
4 xSPI (Octal) transaction details......................................................................................................10
4.1 Command/address/data bit assignments...........................................................................................................11
4.2 RESET ENABLE transaction ..................................................................................................................................12
4.3 RESET transaction.................................................................................................................................................12
4.4 READ ID transaction..............................................................................................................................................13
4.5 DEEP POWER DOWN transaction .........................................................................................................................14
4.6 READ transaction ..................................................................................................................................................15
4.7 WRITE transaction.................................................................................................................................................16
4.8 WRITE ENABLE transaction ..................................................................................................................................17
4.9 WRITE DISABLE transaction .................................................................................................................................17
4.10 READ ANY REGISTER transaction .......................................................................................................................17
4.11 WRITE ANY REGISTER transaction......................................................................................................................18
4.12 Data placement during memory READ/WRITE transactions ............................................................................19
4.13 Data placement during register READ/WRITE transactions..............................................................................20
5 Memory space ..............................................................................................................................21
5.1 xSPI (Octal) interface ............................................................................................................................................21
5.2 Density and row boundaries ................................................................................................................................21
6 Register space access ....................................................................................................................22
6.1 xSPI (Octal) interface ............................................................................................................................................22
6.2 Device identification registers..............................................................................................................................22
6.3 Device configuration registers .............................................................................................................................23
6.3.1 Configuration register 0 (CR0)...........................................................................................................................23
6.3.2 Configuration register 1.....................................................................................................................................26
7 Interface states ............................................................................................................................28
8 Power conservation modes............................................................................................................29
8.1 Interface standby..................................................................................................................................................29
8.2 Active clock stop ...................................................................................................................................................29
8.3 Hybrid sleep ..........................................................................................................................................................29
8.4 Deep power down.................................................................................................................................................30
9 Electrical specifications.................................................................................................................31
9.1 Absolute maximum ratings ..................................................................................................................................31
9.2 Input signal overshoot..........................................................................................................................................31
9.3 Latch-up characteristics .......................................................................................................................................32
9.4 Operating ranges ..................................................................................................................................................32
9.4.1 Temperature ranges ..........................................................................................................................................32
9.4.2 Power supply voltages.......................................................................................................................................32
9.5 DC characteristics .................................................................................................................................................33
9.5.1 Capacitance characteristics ..............................................................................................................................36
9.6 Power-up initialization .........................................................................................................................................37
9.7 Power down ..........................................................................................................................................................38
9.8 Hardware reset......................................................................................................................................................39
10 Timing specifications ..................................................................................................................40
10.1 Key to switching waveforms...............................................................................................................................40
10.2 AC test conditions ...............................................................................................................................................40
10.3 CLK characteristics .............................................................................................................................................41
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Table of contents
10.4 AC characteristics................................................................................................................................................42
10.4.1 Read transactions ............................................................................................................................................42
10.4.2 Write transactions............................................................................................................................................43
10.5 Timing reference levels.......................................................................................................................................45
11 Physical interface .......................................................................................................................46
11.1 FBGA 24-ball 5 x 5 array footprint ......................................................................................................................46
11.2 Physical diagrams ...............................................................................................................................................47
12 Ordering information ..................................................................................................................48
12.1 Ordering part number.........................................................................................................................................48
12.2 Valid combinations .............................................................................................................................................49
12.3 Valid combinations - Automotive Grade / AEC-Q100 ........................................................................................49
13 Acronyms ...................................................................................................................................50
14 Document conventions................................................................................................................51
14.1 Units of measure .................................................................................................................................................51
Revision history ..............................................................................................................................52
Datasheet
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1.8 V
General description
1
General description
The 256 Mb HYPERRAM™ device is a high-speed CMOS, self-refresh DRAM, with xSPI (Octal) interface. The DRAM
array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh
operations on the DRAM array when the memory is not being actively read or written by the xSPI interface master
(host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as
though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately
described as pseudo static RAM (PSRAM).
Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host
limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The
host must confine the duration of transactions and allow additional initial access latency, at the beginning of a
new transaction, if the memory indicates a refresh operation is needed.
1.1
xSPI (Octal) interface
xSPI (Octal) is a SPI-compatible low signal count, DDR interface supporting eight I/Os. The DDR protocol in xSPI
(Octal) transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on
xSPI (Octal) consists of a series of 16-bit wide, one clock cycle data transfers at the internal RAM array with two
corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are
LV-CMOS compatible. Device are available as 1.8 V VCC/VCCQ (nominal) for array (VCC) and I/O buffer (VCCQ
supplies, through different ordering part number (OPN).
)
Each transaction on xSPI (Octal) must include a command whereas address and data are optional. The transac-
tions are structures as follows:
• Each transaction begins with CS# going LOW and ends with CS# returning HIGH.
• The serial clock (CK) marks the transfer of each bit or group of bits between the host and memory. All transfers
occur on every CK edge (DDR mode).
• Each transaction has a 16-bit command which selects the type of device operation to perform. The 16-bit
command is based on two 8-bit opcodes. The same 8-bit opcode is sent on both edges of the clock.
• A command may be stand-alone or may be followed by address bits to select a memory location in the device
to access data.
• Read transactions require a latency period after the address bits and can be zero to several CK cycles. CK must
continue to toggle during any read transaction latency period. During the command and address parts of a
transaction, the memory can indicate whether an additional latency period is needed for a required refresh time
(tRFH) which is added to the initial latency period; by driving the RWDS signal to the HIGH state.
• Write transactions to registers do not require a latency period.
• Write transactions to the memory array require a latency period after the address bits and can be zero to several
CK cycles. CK must continue to toggle during any write transaction latency period. During the command and
address parts of a transaction, the memory can indicate whether an additional latency period is needed for a
required refresh time (tRFH) which is added to the initial latency period by driving the RWDS signal to the HIGH
state.
• In all transactions, command and address bits are shifted in the device with the most significant bits (MSb) first.
The individual data bits within a data byte are shifted in and out of the device MSb first as well. All data bytes
are transferred with the lowest address byte sent out first.
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General description
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 1
xSPI (Octal) command only transaction (DDR)
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RW DS
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0], Memory drives RW DS)
W rite Data
Figure 2
xSPI (Octal) write with no latency transaction (DDR) (Register writes)[1]
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS acts as Data mask
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drivesDQ[7:0])
Figure 3
Notes
xSPI (Octal) write with 1X latency transaction (DDR) (Memory array writes)[2, 3]
1. Write with no latency transaction is used for register writes only.
2. RWDS driven by the host.
3. Data DinA and DinA+2 are masked.
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General description
CS#
CK#, CK
Latency Count (2X)
RWDS
High: 2X Latency Count
Low: 1X Latency Count
RWDS acts as Data Mask
DQ[7:0]
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 4
xSPI (Octal) write with 2X latency transaction (DDR) (Memory array writes)[4, 5]
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutA+3
[7:0]
Command - Address
(Host drives DQ[7:0] andMemory drivesRWDS)
Read Data
(Memorydrives RWDS)
Figure 5
xSPI (Octal) read with 1X latency transaction (DDR) (All reads)[6]
CS#
CK#, CK
Laten
cy Count (2
X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutB+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 6
xSPI (Octal) read with 2X latency transaction (DDR) (All reads)[7]
Notes
4. RWDS driven by HYPERRAM™ during command & address cycles for 2X latency and then driven by the host
for data masking.
5. Data DinA and DinA+2 are masked.
6. RWDS is driven by HYPERRAM™ phase aligned with data.
7. RWDS is driven by HYPERRAM™ during command & address cycles for 2X latency and then driven again phase
aligned with data.
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1.8 V
Product overview
2
Product overview
The 256 Mb HYPERRAM™ device is 1.8 V array and I/O, synchronous self-refresh dynamic RAM (DRAM). The
HYPERRAM™ device provides an xSPI (Octal) slave interface to the host system. The xSPI (Octal) interface has an
8-bit (1 byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read transactions
provide 16 bits of data during each clock cycle (8 bits on both clock edges). Write transactions take 16 bits of data
from each clock cycle (8 bits on each clock edge).
RESET#
V
CC
V
CCQ
CS#
CK
DQ[7:0]
RWDS
CK#
V
SS
V
SSQ
Figure 7
xSPI (Octal) HYPERRAM™ interface[8]
2.1
xSPI (Octal) interface
Read and write transactions require three clock cycles to define the target row/column address and then an initial
access latency of tACC. During the CA part of a transaction, the memory will indicate whether an additional latency
for a required refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the HIGH state.
During a read (or write) transaction, after the initial data value has been output (or input), additional data can be
read from (or written to) the row on subsequent clock cycles in either a wrapped or linear sequence. When
configured in linear burst mode, the device will automatically fetch the next sequential row from the memory
array to support a continuous linear burst. Simultaneously accessing the next row in the array while the read or
write data transfer is in progress, allows for a linear sequential burst operation that can provide a sustained data
rate of 400 MBps (1 byte (8 bit data bus) * 2 (data clock edges) * 200 MHz = 400 MBps).
Note
8. CK# is used in differential clock mode, but optional.
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Signal description
3
Signal description
3.1
Input/output summary
The xSPI (Octal) HYPERRAM™ signals are shown in Table 1. Active low signal names have a hash symbol (#) suffix.
Table 1
Symbol
I/O summary
Type
Description
Chip select. Bus transactions are initiated with a HIGH to LOW
transition. Bus transactions are terminated with a Low to High
transition. The master device has a separate CS# for each slave.
CS#
Input
Differential clock. Command, address, and data information is output
with respect to the crossing of the CK and CK# signals. Use of
differential clock is optional.
CK, CK#[9]
DQ[7:0]
Input
Single ended clock. CK# is not used, only a single ended CK is used.
The clock is not required to be free-running.
Data input/output. Command, address, and data information is
transferred on these signals during read and write transactions.
Input/output
Read-write data strobe. During the command/address portion of all
bus transactions RWDS is a slave output and indicates whether
additional initial latency is required. Slave output during read data
transfer, data is edge-aligned with RWDS. Slave input during data
transfer in write transactions to function as a data mask.
RWDS
Input/output
(HIGH = additional latency, LOW = no additional latency).
Hardware RESET. When LOW, the slave device will self initialize and
return to the standby state. RWDS and DQ[7:0] are placed into the
RESET#
Input, internal pull-up HIGH-Z state when RESET# is LOW. The slave RESET# input includes a
weak pull-up, if RESET# is left unconnected it will be pulled up to the
HIGH state.
VCC
VCCQ
VSS
Power supply
Power supply
Power supply
Power supply
Array power.
Input/output power.
Array ground.
VSSQ
Input/output ground.
Reserved for future use. May or may not be connected internally, the
signal/ball location should be left unconnected and unused by PCB
routing channel for future compatibility. The signal/ball may be used
by a signal in the future.
RFU
No connect
Note
9. CK# is used in differential clock mode, but optional connection. Tie the CK# input pin to either VCCQ or VSSQ
if not connected to the host controller, but do not leave it floating.
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xSPI (Octal) transaction details
4
xSPI (Octal) transaction details
The xSPI (Octal) master begins a transaction by driving CS# LOW while clock is idle. Then the clock begins toggling
while CA words are transferred.
For memory read and write transactions, the xSPI (Octal) master then continues clocking for a number of cycles
defined by the latency count setting in configuration register 0 (Register write transactions do not require any
latency count). The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is
LOW during the CA cycles, one latency count is inserted. If RWDS is HIGH during the CA cycles, an additional
latency count is inserted. Once these latency clocks have been completed the memory starts to simultaneously
transition the RWDS and output the target data.
During the read data transfers, read data is output edge-aligned with every transition of RWDS. Data will continue
to be output as long as the host continues to transition the clock while CS# is LOW. Note that burst transactions
should not be so long as to prevent the memory from doing distributed refreshes.
During the write data transfers, write data is center-aligned with the clock edges. The first byte of data in each
word is captured by the memory on the rising edge of CK and the second byte is captured on the falling edge of
CK. RWDS is driven by the host master interface as a data mask. When data is being written and RWDS is HIGH the
byte will be masked and the array will not be altered. When data is being written and RWDS is LOW the data will
be placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor
the HYPERRAM™ device are able to indicate a need for latency within the data transfer portion of a write trans-
action. The acceptable write data burst length setting is also shown in configuration register 0.
Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential
manner across row boundaries. When a linear burst read reaches the last address in the array, continuing the
burst beyond the last address will provide data from the beginning of the address range. Read transfers can be
ended at any time by bringing CS# HIGH when the clock is idle.
The clock is not required to be free-running. The clock may remain idle while CS# is HIGH.
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xSPI (Octal) transaction details
4.1
Table 2
Command/address/data bit assignments
Command set[10-14]
Address
Data
Command
Code
CA-Data
Latency cycles
Prerequisite
(bytes)
(bytes)
Software reset
REST ENABLE
RESET
0x66
0x99
8-0-0
8-0-0
0
0
0
0
0
0
RESET ENABLE
Identification
READ ID[10]
0x9F
8-8-8
8-0-0
8-8-8
8-8-8
4 (0x00)
3-7
0
4
Power modes
DEEP POWER DOWN 0xB9
0
4
4
0
Read memory array
READ (DDR)
0xEE
0xDE
3-7
3-7
1 to ∞
1 to ∞
Write memory array
WRITE (DDR)
WRITE ENABLE
WRITE ENABLE
Write enable / disable
WRITE ENABLE
0x06
0x04
8-0-0
8-0-0
0
0
0
0
0
0
WRITE DISABLE
Read registers
READ ANY REGISTER
Write registers
0x65
8-8-8
8-8-8
4
4
3-7
0
2
2
WRITE ANY REGISTER 0x71
Notes
10.The two identification registers contents are read together - identification 0 followed by identification 1.
11.Write enable provides protection against inadvertent changes to memory or register values. It sets the inter-
nal write enable latch (WEL) which allows write transactions to execute afterwards.
12.Write disable can be used to disable write transactions from execution. It resets the internal write enable
latch (WEL).
13.The WEL latch stays set to ‘1’ at the end of any successful memory write transaction. After a power down /
power up sequence, or a hardware/software reset, WEL latch is cleared to ‘0’.
14.The internal WEL latch is cleared to ‘0’ at the end of any successful register write transaction.
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xSPI (Octal) transaction details
4.2
RESET ENABLE transaction
The RESET ENABLE transaction is required immediately before a RESET transaction. Any transaction other than
RESET following RESET ENABLE will clear the reset enable condition and prevent a later RESET transaction from
being recognized.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 8
RESET ENABLE transaction (DDR)
4.3
RESET transaction
The RESET transaction immediately following a RESET ENABLE will initiate the software reset process. The
software reset provides a software method of returning the device to the standby state. During tSR (400 ns, max)
the device will draw ICC5 current. A software reset will:
• Cause the configuration registers to return to their default values
• Halt self-refresh operation during the software reset process - memory array data is considered invalid
After software reset finishes, the self-refresh operation will resume. Because self-refresh operation is stopped,
and the self-refresh row counter is reset to its default value, some rows may not be refreshed within the required
array refresh interval. This may result in the loss of DRAM array data. The host system should consider DRAM array
data is lost after software reset and reload any required data.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 9
RESET transaction (DDR)
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1.8 V
xSPI (Octal) transaction details
4.4
READ ID transaction
The READ ID transaction provides read access to device identification registers 0 and 1. The registers contain the
manufacturer’s identification along with device identification. The read data sequence is as follows.
Table 3
READ ID data sequence
Address space
Byte order
Byte position
Word data Bit
DQ
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
A
8
Register 0
Big-endian
7
6
5
4
B
A
B
3
2
1
0
15
14
13
12
11
10
9
8
Register 1
Big-endian
7
6
5
4
3
2
1
0
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xSPI (Octal) transaction details
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
IDRG0
[15:8]
IDRG 0
[7:0]
IDRG 1
[15:8]
IDRG1
[7:0]
0x00
0x00
0x00
0x00
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 10
READ ID with 1X latency transaction (DDR)[15]
CS#
CK#, CK
Latency Count (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
IDRG 0
[15:8]
IDRG 0
[7:0]
IDRG1
[15:8]
IDRG1
[7:0]
0x00
0x00
0x00
0x00
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 11
READ ID with 2X latency transaction (DDR)[16]
4.5
DEEP POWER DOWN transaction
DEEP POWER DOWN transaction brings the device into deep power down state which is the lowest power
consumption state. Writing a “0” to CR0[15] will also bring the device in deep power down state. All register
contents are lost in deep power down state and the device powers-up in its default state.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 12
Notes
DEEP POWER DOWN transaction (DDR)
15. RWDS is driven by HYPERRAM™ phase aligned with data.
16. RWDS is driven by HYPERRAM™ during command & address cycles for 2X latency and then is driven again
phase aligned with data.
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xSPI (Octal) transaction details
4.6
READ transaction
The READ transaction reads data from the memory array. It has a latency requirement (dummy cycles) which
allows the device’s internal circuitry enough time to access the addressed memory location. During these latency
cycles, the host can tristate the data bus DQ[7:0].
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
DQ[7:0]
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 13
READ with 1X latency transaction (DDR)[17]
CS#
CK#, CK
Latency C
ount (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutA+1
[7:0]
DoutA+2
[7:0]
DoutB+3
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 14
READ with 2X latency transaction (DDR)[18]
Notes
17. RWDS is driven by HYPERRAM™ phase aligned with data.
18. RWDS is driven by HYPERRAM™ during command & address cycles for 2X latency and then is driven again
phase aligned with data.
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xSPI (Octal) transaction details
4.7
WRITE transaction
The WRITE transaction writes data to the memory array. It has a latency requirement (dummy cycles) which
allows the device’s internal circuitry enough time to access the addressed memory location. During these latency
cycles, the host can tristate the data bus DQ[7:0].
WRITE ENABLE transaction which sets the WEL latch must be executed before the first WRITE. The WEL latch stays
set to ‘1’ at the end of any successful memory write transaction. It must be reset by WRITE DISABLE transaction
to prevent any inadvertent writes to the memory array.
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS acts as Data mask
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 15
WRITE with 1X latency transaction (DDR)[19, 20]
CS#
CK#, CK
Latency Count (2X)
RWDS
High: 2X Latency Count
Low: 1X Latency Count
RWDS acts as Data Mask
DQ[7:0]
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DinA
[7:0]
DinA+1
[7:0]
DinA+2
[7:0]
DinA+3
[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Write Data
(Host drives DQ[7:0])
Figure 16
WRITE with 2X latency transaction (DDR)[21, 22]
Notes
19. RWDS is driven by the host.
20. Data DinA and DinA+2 are masked.
21. RWDS is driven by HYPERRAM™ during command and address cycles for 2X latency and then is driven by the
host for data masking.
22. Data DinA and DinA+2 are masked.
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xSPI (Octal) transaction details
4.8
WRITE ENABLE transaction
The WRITE ENABLE transaction must be executed prior to any transaction that modifies data either in the
memory array or the registers.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 17
WRITE ENABLE transaction (DDR)
4.9
WRITE DISABLE transaction
The WRITE DISABLE transaction inhibits writing data either in the memory array or the registers.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
DQ[7:0]
Command
(Host drives DQ[7:0])
Figure 18
WRITE DISABLE transaction (DDR)
4.10
READ ANY REGISTER transaction
The READ ANY REGISTER transaction reads all the device registers. It has a latency requirement (dummy cycles)
which allows the device’s internal circuitry enough time to access the addressed register location. During these
latency cycles, the host can tristate the data bus DQ[7:0].
CS#
CK#, CK
Latency Count (1X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory Drives RWDS)
Figure 19
Note
READ ANY REGISTER with 1X latency transaction (DDR)[23]
23. RWDS is driven by HYPERRAM™ phase aligned with data.
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xSPI (Octal) transaction details
CS#
CK#, CK
Latency Count (2X)
High: 2X Latency Count
Low: 1X Latency Count
RWDS
RWDS & Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Read Data
(Memory drives RWDS)
Figure 20
READ ANY REGISTER with 2X latency transaction (DDR)[24]
4.11
WRITE ANY REGISTER transaction
The WRITE ANY REGISTER transaction writes to the device registers. It does not have a latency requirement
(dummy cycles).
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RWDS
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
Command - Address
(Host drives DQ[7:0], Memory drives RWDS)
Write Data
Figure 21
xSPI (Octal) write with no latency transaction (DDR) (Register writes)[25, 26]
Notes
24. RWDS is driven by HYPERRAM™ during command & address cycles for 2X latency and then driven again phase
aligned with data.
25. Write with no latency transaction is used for register writes only.
26. Data mask on RWDS is not supported.
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xSPI (Octal) transaction details
4.12
Data placement during memory READ/WRITE transactions
Data placement during memory read/write is dependent upon the host. The device will output data (read) as it
was written in (write). Hence both Big Endian and Little Endian are supported for the memory array.
Table 4
Data placement during memory READ and WRITE
Word
order
Address Byte
Byte position data DQ
bit
Bit order
space
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
B
A
B
8
Big-
endian
7
6
5
4
3
When data is being accessed in memory space:
The first byte of each word read or written is the “A” byte and the
second is the “B” byte.
2
1
The bits of the word within the A and B bytes depend on how the
data was written. If the word lower address bits 7-0 are written
in the A byte position and bits 15-8 are written into the B byte
position, or vice versa, they will be read back in the same order.
0
Memory
7
6
So, memory space can be stored and read in either little-endian
or big-endian order.
5
4
3
2
1
0
Little-
endian
15
14
13
12
11
10
9
8
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xSPI (Octal) transaction details
4.13
Data placement during register READ/WRITE transactions
Data placement during register read/write is Big Endian.
Table 5
Data placement during register READ/WRITE transactions
Address Byte
Worddata
bit
Byte position
DQ
Bit order
space
order
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
When data is being accessed in register space:
During a read transaction on the xSPI (Octal) two bytes are
transferred on each clock cycle. The upper order byte A
(Word[15:8]) is transferred between the rising and falling
edges of RWDS (edge-aligned). The lower order byte B
(Word[7:0]) is transferred between the falling and rising
edges of RWDS.
A
8
Big-
endian
Register
7
During a write, the upper order byte A (Word[15:8]) is trans-
ferred on the CK rising edge and the lower order byte B
(Word[7:0]) is transferred on the CK falling edge.
So, register space is always read and written in Big-endian
order because registers have device dependent fixed bit
location and meaning definitions.
6
5
4
B
3
2
1
0
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Memory space
5
Memory space
5.1
xSPI (Octal) interface
Table 6
Memory space address map (byte based - 8 bits with least significant bit A(0) always set to ‘0’)
System byte
Unit type
Count
Address bits
Notes
address bits
Rows within 256 Mb
device
A24 - A10
24 - 10
32,768 (rows)
-
Each row has 64 half-pages. Each
half-page has 16 bytes. Each column
has 1K bytes).
A9 - A4
A3 - A0
9 - 4
3 - 0
Row
64 (half-pages)
Half-page (HP) address is also refer-
enced as upper column address. A
word within a HP address is also
referenced as lower column address.
A0 always set to “0”
16 (byte
addresses)
Half-page
5.2
Density and row boundaries
The DRAM array size (density) of the device can be determined from the total number of system address bits used
for the row and column addresses as indicated by the row address bit count and column address bit count fields
in the ID0 register. For example: a 256 Mb HYPERRAM™ device has 10 column address bits and 15 row address bits
for a total of 25 address bits (byte address) = 225 = 32M bytes (16M words). The 10 column address bits indicate
that each row holds 210 = 1K bytes or 512 words. The row address bit count indicates there are 32768 rows to be
refreshed within each array refresh interval. The row count is used in calculating the refresh interval.
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Register space access
6
Register space access
6.1
xSPI (Octal) interface
Table 7
Register space address map (Address bit A0 always set to ‘0’)
Registers
Address (Byte addressable)
Identification registers 0 (ID0[15:0])
Identification registers 1 (ID1[15:0])
Configuration registers 0 (ID0[15:0])
Configuration registers 1 (ID1[15:0])
0x00000000
0x00000002
0x00000004
0x00000006
6.2
Device identification registers
There are two read-only, nonvolatile, word registers, that provide information on the device selected when CS#
is LOW. The device information fields identify:
• Manufacturer
• Type
• Density
- Row address bit count
- Column address bit count
• Refresh type
Table 8
Bits
Identification register 0 (ID0) bit assignments
Function
Settings (binary)
[15:14]
13
Reserved
Reserved
00b - Default
0b - Default
[12:8]
[7:4]
[3:0]
Row address bit count 01110b - Fifteen row address bits (256 Mb)
Column address bit count 1001b - Ten column address bits (default)
Manufacturer
0110b
ID0 value for S80KS2563 is 0x0E96.
Table 9
Identification register 1 (ID1) bit assignments
Function
Bits
[15:4]
[3:0]
Settings (binary)
Reserved
0000_0000_0000b (default)
Device type
0001b - HYPERRAM™ 2.0
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Register space access
6.3
Device configuration registers
Configuration register 0 (CR0)
6.3.1
Configuration register 0 (CR0) is used to define the power state and access protocol operating conditions for the
HYPERRAM™ device. Configurable characteristics include:
• Wrapped burst length (16, 32, 64, or 128 byte aligned and length data group)
• Wrapped burst type
- Legacy wrap (sequential access with wrap around within a selected length and aligned group)
- Hybrid wrap (Legacy wrap once then linear burst at start of the next sequential group)
• Initial latency
• Variable latency
- Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected the
memory will always indicate a refresh latency and delay the read data transfer accordingly. If variable latency
is selected, latency for a refresh is only added when a refresh is required at the same time a new transaction
is starting.
• Output drive strength
• Deep power down (DPD) mode
Table 10
CR0 bit
Configuration register 0 (CR0) bit assignments
Function
Settings (binary)
1 - Normal operation (default). HYPERRAM™ will automatically set this value to
‘1’ after DPD exit
Deep power
down enable
[15]
0 - Writing 0 causes the device to enter deep power down
000 - 34 ohms (default)
001 - 115 ohms
010 - 67 ohms
011 - 46 ohms
100 - 34 ohms
101 - 27 ohms
110 - 22 ohms
111 - 19 ohms
[14:12]
[11:8]
Drive strength
Reserved
1 - Reserved (default)
Reserved for future use. When writing this register, these bits should be set to
1 for future compatibility.
0000 - 5 clock latency @ 133 MHz Max frequency
0001 - 6 clock latency @ 166 MHz Max frequency
0010 - 7 clock latency @ 200 MHz Max frequency (default)
0011 - Reserved
[7:4]
Initial latency 0100 - Reserved
...
1101 - Reserved
1110 - 3 clock latency @ 85 MHz Max frequency
1111 - 4 clock latency @ 104 MHz Max frequency
0 - Variable latency - 1 or 2 times initial latency depending on RWDS during CA
Fixed latency
enable
[3]
[2]
cycles.
1 - Fixed 2 times initial latency (default)
Hybrid burst 0: Wrapped burst sequence to follow hybrid burst sequencing
enable 1: Wrapped burst sequence in legacy wrapped burst manner (default)
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Register space access
Table 10
CR0 bit
Configuration register 0 (CR0) bit assignments (continued)
Function
Settings (binary)
00 - 128 bytes
01 - 64 bytes
[1:0]
Burst length
10- 16 bytes
11 - 32 bytes (default)
Wrapped burst
A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching
the length of the configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes
alignment and length. During wrapped transactions, access starts at the CA selected location within the group,
continues to the end of the configured word group aligned boundary, then wraps around to the beginning
location in the group, then continues back to the starting location. Wrapped bursts are generally used for critical
word first instruction or data cache line fill read accesses.
Hybrid burst
The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing
to the next half-page of data beyond the end of the wrap group. Continued access is in linear burst order until the
transfer is ended by returning CS# HIGH. This hybrid of a wrapped burst followed by a linear burst starting at the
beginning of the next burst group, allows multiple sequential address cache lines to be filled in a single access.
The first cache line is filled starting at the critical word. Then the next sequential line in memory can be read in
to the cache while the first line is being processed.
Table 11
Bit
CR0[2] Control of wrapped burst sequence
Default value
Setting details
Hybrid burst enable
CR0[2] = 0: Wrapped burst sequence to follow hybrid burst sequencing
CR0[2] = 1: Wrapped burst sequence in legacy wrapped burst manner
CR0[2]
1b
Table 12
Example wrapped burst sequences (Addressing)
Wrap
Start address
Burst type boundary
(bytes)
Sequence of byte addresses (Hex) of data words
(Hex)
02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26, 28,
2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 00
64 wrap
Hybrid 64 once then
linear
XXXXXX02 (wrap complete, now linear beyond the end of the initial 64 byte wrap
group)
40, 42, 44, 46, 48, 4A, 4C, 4E, 50, 52, ...
2E, 30, 32, 34, 36, 38, 3A, 3C, 3E,
00, 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26,
XXXXXX2E 28, 2A, 2C, (wrap complete, now linear beyond the end of the initial 64
byte wrap group)
64 wrap
Hybrid 64 once then
linear
40, 42, 44, 46, 48, 4A, 4B, 4C, 4D, 4E, 4F, 50, 52, ...
02, 04, 06, 08, 0A, 0C, 0E, 00
16 wrap
Hybrid 16 once then
linear
(wrap complete, now linear beyond the end of the initial 16 byte wrap
XXXXXX02
group)
10, 12, 14, 16, 18, 1A, ..
0C, 0E, 00, 02, 04, 06, 08, 0A
16 wrap
Hybrid 16 once then
linear
(wrap complete, now linear beyond the end of the initial 16 byte wrap
XXXXXX0C
group)
10, 12, 14, 16, 18, 1A, ...
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Register space access
Table 12
Example wrapped burst sequences (Addressing) (continued)
Wrap
Start address
Burst type boundary
(bytes)
Sequence of byte addresses (Hex) of data words
(Hex)
0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 00, 02, 04, 06, 08
(wrap complete, now linear beyond the end of the initial 32 byte wrap
group)
32 wrap
Hybrid 32 once then
linear
XXXXXX0A
XXXXXX02
20, 22, 24, 26, 28, 2A, ...
02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26, 28,
2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 00, ...
Wrap 64
Wrap 64
64
64
2E, 30, 32, 34, 36, 38, 3A, 3C, 3E,
XXXXXX2E 00, 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26,
28, 2A, 2C, 2E, 30, ….
Wrap 16
Wrap 16
Wrap 32
16
16
32
XXXXXX02 02, 04, 06, 08, 0A, 0C, 0E, 00, ...
XXXXXX0C 0C, 0E, 00, 02, 04, 06, 08, 0A, ...
XXXXXX0A 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 00, 02, 04, 06, 08, ...
Linear
burst
Linear
XXXXXX02 02, 04, 06, 08, 0A, 0C, 0E, 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, ...
Initial latency
Memory space read and write transactions or register space read transactions require some initial latency to
open the row selected by the CA. This initial latency is tACC. The number of latency clocks needed to satisfy tACC
depends on the clock input frequency can vary from 3 to 7 clocks. The value in CR0[7:4] selects the number of
clocks for initial latency. The default value is 7 clocks, allowing for operation up to a maximum frequency of
200MHz prior to the host system setting a lower initial latency value that may be more optimal for the system.
In the event a distributed refresh is required at the time a memory space read or write transaction or register
space read transaction begins, the RWDS signal goes High during the CA to indicate that an additional initial
latency is being inserted to allow a refresh operation to complete before opening the selected row.
Register space write transactions always have zero initial latency. RWDS may be HIGH or LOW during the CA
period. The level of RWDS during the CA period does not affect the placement of register data immediately after
the CA, as there is no initial latency needed to capture the register data. A refresh operation may be performed
in the memory array in parallel with the capture of register data.
Fixed latency
A configuration register option bit CR0[3] is provided to make all memory space read and write transactions or
register space read transactions require the same initial latency by always driving RWDS HIGH during the CA to
indicate that two initial latency periods are required. This fixed initial latency is independent of any need for a
distributed refresh, it simply provides a fixed (deterministic) initial latency for all of these transaction types. Fixed
latency is the default POR or reset configuration. The system may clear this configuration bit to disable fixed
latency and allow variable initial latency with RWDS driven HIGH only when additional latency for a refresh is
required.
Drive strength
DQ and RWDS signal line loading, length, and impedance vary depending on each system design. Configuration
register bits CR0[14:12] provide a means to adjust the DQ[7:0] and RWDS signal output impedance to customize
the DQ and RWDS signal impedance to the system conditions to minimize high speed signal behaviors such as
overshoot, undershoot, and ringing. The default POR or reset configuration value is 000b to select the mid point
of the available output impedance options.
The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process condi-
tions, nominal operating voltage (1.8 V) and 50°C. The impedance values may vary from the typical values
depending on the process, voltage, and temperature (PVT) conditions. Impedance will increase with slower
process, lower voltage, or higher temperature. Impedance will decrease with faster process, higher voltage, or
lower temperature.
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Register space access
Each system design should evaluate the data signal integrity across the operating voltage and temperature
ranges to select the best drive strength settings for the operating conditions.
Deep power down
When the HYPERRAM™ device is not needed for system operation, it may be placed in a very low power consuming
state called deep power down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the
DPD state within tDPDIN time and all refresh operations stop. The data in RAM is lost, (becomes invalid without
refresh) during DPD state. Exiting DPD requires driving CS# LOW then HIGH, POR, or a reset. Only CS# and RESET#
signals are monitored during DPD mode. For additional details, see “Deep power down” on page 30.
6.3.2
Configuration register 1
Configuration register 1 (CR1) is used to define the refresh array size, refresh rate and hybrid sleep for the
HYPERRAM™ device. Configurable characteristics include:
• Partial array refresh
• Hybrid sleep state
• Refresh rate
Table 13
CR1 bit
Configuration register 1 (CR1) bit assignments
Function
Setting (binary)
11111111 - Reserved (default)
[15:8]
Reserved
When writing this register, these bits should keep 0xFFh for future compat-
ibility.
1 - Linear burst (default)
0 - Wrapped burst
[7]
[6]
[5]
Burst type
Master clock type
Hybrid sleep
1 - Single ended - CK (default)
0 - Differential - CK#, CK
1 - Causes the device to enter hybrid sleep state
0 - Normal operation (default)
000 - Full array (default)
001 - Bottom 1/2 array
010 - Bottom 1/4 array
011 - Bottom 1/8 array
100 - none
Partial array
refresh
[4:2]
101 - Top 1/2 array
110 - Top 1/4 array
111 - Top 1/8 array
10 - 1µs tCSM (Industrial plus temperature range devices)
Distributed refresh 11 - Reserved
[1:0]
interval
00 - Reserved
01 - 4µs tCSM (Industrial temperature range devices)
Burst type
Two burst types, namely linear and wrapped, are supported in xSPI (Octal) mode by HYPERRAM™. CR1[7] selects
which type to use.
Master clock type
Two clock types, namely single ended and differential, are supported. CR1[6] selects which type to use.
• In the single ended clock mode (by default), CK# input is not enabled; hence it may be left either floating or
biased to HIGH or LOW.
• In the differential clock mode (when enabled), the CK# input can't be left floating. It must be either driven by
the host, or biased to HIGH or LOW.
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Register space access
Partial array refresh
The partial array refresh configuration restricts the refresh operation in HYPERRAM™ to a portion of the memory
array specified by CR1[5:3]. This reduces the standby current. The default configuration refreshes the whole
array.
Hybrid sleep (HS)
When the HYPERRAM™ is not needed for system operation but data in the device needs to be retained, it may be
placed in hybrid sleep state to save more power. Enter hybrid sleep state by writing 1 to CR1[5]. Bringing CS# LOW
will cause the device to exit HS state and set CR1[5] to 0. Also, POR, or a hardware reset will cause the device to
exit hybrid sleep state. Note that a POR or a hardware reset disables refresh where the memory core data can
potentially get lost.
Distributed refresh interval
The HYPERRAM™ device is built with volatile DRAM array which requires periodic refresh of all bits in it. The refresh
operation can be done by an internal self-refresh logic that will evenly refresh the memory array automatically.
The automatic refresh operation can only be done when the memory array is not actively read or written by the
host system. The refresh logic waits for the end of any active read or write before doing a refresh, if a refresh is
needed at that time. If a new read or write begins before the refresh is completed, the memory will drive RWDS
high during the CA period to indicate that an additional initial latency time is required at the start of the new
access in order to allow the refresh operation to complete before starting the new access. The evenly distributed
refresh operations require a maximum refresh interval between two adjacent refresh operations. The maximum
distributed refresh interval varies with temperature as shown in Table 14.
Table 14
Array refresh interval per temperature
Refresh interval tCSM
Operating temperature
CR1[1:0]
01b
TA ≤ 85 °C
4 µs
1 µs
85 °C < TA ≤ 125 °C
10b
The distributed refresh operation requires that the host does not perform burst transactions longer than the
distributed refresh interval to prevent the memory from unable doing the distributed refreshes operation when
it is needed. This sets an upper limit on the length of read and write transactions so that the automatic distributed
refresh operation can be done between transactions. This limit is called the CS# low maximum time (tCSM) and
the tCSM will be equal to the maximum distributed refresh interval. The host system is required to respect the tCSM
value by terminating each transaction before violating tCSM. This can be done by host memory controller splitting
long transactions when reaching the tCSM limit, or by host system hardware or software not performing a single
burst read or write transaction that would be longer than tCSM
.
As noted in Table 14, the maximum refresh interval is longer at lower temperatures such that tCSM could be
increased to allow longer transactions. The host may determine the operating temperature from a temperature
sensor in the system and use the tCSM value from the table accordingly, or it may determine dynamically by
reading the read only CR1[1:0] bits in order to set the distributed refresh interval prior to the HYPERRAM™ access.
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Interface states
7
Interface states
Table 15 describes the required value of each signal for each interface state.
Table 15 Interface states
Interface state
VCC / VCCQ
CS# CK, CK# DQ7-DQ0
RWDS
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
RESET#
Power-off
< VLKO
X
X
X
X
X
X
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
X
X
L
Power-on (cold) reset
Hardware (warm) reset
Interface standby
≥ VCC / VCCQ min
≥ VCC / VCCQ min
≥ VCC / VCCQ min
X
H
H
Master
CA
≥ VCC / VCCQ min
≥ VCC / VCCQ min
≥ VCC / VCCQ min
≥ VCC / VCCQ min
L
L
L
L
T
T
T
T
Y
H
H
H
H
output valid
Read initial access latency
(data bus turn around
period)
HIGH-Z
HIGH-Z
L
Write initial access latency
(RWDS turn around period)
HIGH-Z
Slaveoutput
valid
Slaveoutput
valid
Read data transfer
Z or T
Master
output valid
X or T
Write data transfer with
initial latency
Master
≥ VCC / VCCQ min
≥ VCC / VCCQ min
L
L
T
T
H
H
output valid
Write data transfer without
initial latency [27]
Master
Slaveoutput
output valid L or HIGH-Z
Master or
slave output
Active clock stop [28]
≥ VCC / VCCQ min
L
Idle
Y
H
valid or
HIGH-Z
Deep power down
Hybrid sleep
Notes
≥ VCC / VCCQ min
≥ VCC / VCCQ min
H
H
X or T
X or T
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
H
H
27. Writes without initial latency (with zero initial latency), do not have a turn around period for RWDS. The
HYPERRAM™ device will always drive RWDS during the CA period to indicate whether extended latency is
required. Since master write data immediately follows the CA period the HYPERRAM™ device may continue
to drive RWDS LOW or may take RWDS to HIGH-Z. The master must not drive RWDS during writes with zero
latency. writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written
(full word writes).
28. Active clock stop is described in “Active clock stop” on page 29. DPD is described in “Deep power down”
on page 30
Legend
L = VIL; H = VIH; X = either VIL or VIH; Y= either VIL or VIH or VOL or VOH; Z = either VOL or VOH; L/H = rising edge;
H/L = falling edge; T = Toggling during information transfer; Idle = CK is LOW and CK# is HIGH;
Valid = all bus signals have stable L or H level
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Power conservation modes
8
Power conservation modes
8.1
Interface standby
Standby is the default, low power, state for the interface while the device is not selected by the host for data
transfer (CS# = HIGH). All inputs, and outputs other than CS# and RESET# are ignored in this state.
8.2
Active clock stop
Design Note: Active Clock Stop feature is pending device characterization to determine if it will be supported. The
active clock stop state reduces device interface energy consumption to the ICC6 level during the data transfer
portion of a read or write operation. The device automatically enables this state when clock remains stable for
tACC + 30 ns. While in active clock Stop state, read data is latched and always driven onto the data bus. ICC6 shown
in “DC characteristics” on page 33.
Active clock stop state helps reduce current consumption when the host system clock has stopped to pause the
data transfer. Even though CS# may be LOW throughout these extended data transfer cycles, the memory device
host interface will go into the active clock stop current level at tACC + 30 ns. This allows the device to transition
into a lower current state if the data transfer is stalled. Active read or write current will resume once the data
transfer is restarted with a toggling clock. The active clock stop state must not be used in violation of the tCSM
limit. CS# must go HIGH before tCSM is violated. Clock can be stopped during any portion of the active transaction
as long as it is in the LOW state. Note that it is recommended to avoid stopping the clock during register access.
CS#
Clock Stopped
CK#, CK
Latency Count (1X)
High: 2XLatencyCount
Low: 1XLatencyCount
RWDS
DQ[7:0]
RWDS&Data are edge aligned
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
DoutA
[7:0]
DoutB
[7:0]
DoutA+1
[7:0]
DoutB+1
[7:0]
Output Driven
Read Data
Command - Address
(Host drives DQ[7:0] and Memory drives RWDS)
Figure 22
Active clock stop during read transaction (DDR)[29]
8.3
Hybrid sleep
In the hybrid sleep (HS) state, the current consumption is reduced (IHS). HS state is entered by writing a 1 to
CR1[5]. The device reduces power within tHSIN time. The data in memory space and register space is retained
during HS state. Bringing CS# LOW will cause the device to exit HS state and set CR1[5] to 0. Also, POR, or a
hardware reset will cause the device to exit hybrid sleep state. Note that a POR or a hardware reset disables
refresh where the memory core data can potentially get lost. Returning to standby state requires tEXITHS time.
Following the exit from HS due to any of these events, the device is in the same state as entering hybrid sleep.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RW DS
tHSIN
CM D
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
W rite Data
CR0 Value
Enter Hybrid Sleep
tHSIN
Com mand - Address
(Host drives DQ[7:0], Memory drives RW DS)
HS
Figure 23
Note
Enter HS transaction
29. RWDS is LOW during the CA cycles. In this read transaction there is a single initial latency count for read data
access because, this read transaction does not begin at a time when additional latency is required by the
slave.
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Power conservation modes
CS#
tCSHS
tEXTHS
Figure 24
Table 16
Exit HS transaction
Hybrid sleep timing parameters
Parameter
Description
Min
-
60
Max
3
Unit
µs
tHSIN
tCSHS
tEXTHS
Hybrid sleep CR1[5] = 0 register write to DPD power level
CS# pulse width to exit HS
3000
100
ns
CS# exit hybrid sleep to standby wakeup time
-
µs
8.4
Deep power down
In the deep power down (DPD) state, current consumption is driven to the lowest possible level (IDPD). DPD state
is entered by writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop.
The data in memory space is lost, (becomes invalid without refresh) during DPD state. Driving CS# LOW then HIGH
will cause the device to exit DPD state. Also, POR, or a hardware reset will cause the device to exit DPD state.
Returning to standby state requires tEXTDPD time. Returning to standby state following a POR requires tVCS time,
as with any other POR. Following the exit from DPD due to any of these events, the device is in the same state as
following POR.
Note In xSPI (Octal), deep power down transaction or write any register transaction can be used to enter DPD.
CS#
CK#, CK
High: 2X Latency Count
Low: 1X Latency Count
RW DS
tDPDIN
CM D
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
RG
[15:8]
RG
[7:0]
DQ[7:0]
W rite Data
CR0 Value
Enter Deep Power Down
tDPDIN
Command - Address
(Host drives DQ[7:0], Memory drives RW DS)
DPD
Figure 25
Enter DPD transaction
CS#
tCSDPD
tEXTDPD
Figure 26
Table 17
Exit DPD transaction
Deep power down timing parameters
Description
Parameter
tDPDIN
Min
Max
Unit
µs
Deep power down CR0[15] = 0 register write to DPD power level
CS# pulse width to exit DPD
-
200
-
3
tCSDPD
3000
150
ns
tEXTDPD
CS# exit deep power down to standby wakeup time
µs
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Electrical specifications
9
Electrical specifications
9.1
Absolute maximum ratings
Storage temperature plastic packages
Ambient temperature with power applied
Voltage with respect to ground all signals[30]
Output short circuit current[31]
-65 °C to +150 °C
-65 °C to +135 °C
-0.5 V to + (VCC + 0.5 V)
100 mA
Voltage on VCC, VCCQ pins relative to VSS
-0.5 V to +2.5 V
Electrostatic discharge voltage:
Human body model (JEDEC Std JESD22-A114-B)
2000 V
Charged device model (JEDEC Std JESD22-C101-A) 500 V
9.2
Input signal overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage
transitions, inputs or I/Os may negative overshoot VSS to -1.0V or positive overshoot to VCC +1.0V, for periods up to
20 ns.
VSSQ to VCC
Q
- 1.0V
20 ns
≤
Figure 27
Maximum negative overshoot waveform
≤ 20 ns
VCCQ + 1.0V
VSSQ to VCC
Q
Figure 28
Notes
Maximum positive overshoot waveform
30. Minimum DC voltage on input or I/O signal is -1.0V. During voltage transitions, input or I/O signals may
undershoot VSS to -1.0V for periods of up to 20 ns. See Figure 27. Maximum DC voltage on input or I/O signals
is VCC +1.0V. During voltage transitions, input or I/O signals may overshoot to VCC +1.0V for periods up to 20
ns. See Figure 28.
31. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be
greater than one second.
32. Stresses above those listed under “Absolute maximum ratings” on page 31 may cause permanent dam-
age to the device. This is a stress rating only; functional operation of the device at these or any other con-
ditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the
device to absolute maximum rating conditions for extended periods may affect device reliability.
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Electrical specifications
9.3
Table 18
Latch-up characteristics
Latch-up specification[33]
Description
Min
Max
Unit
V
Input voltage with respect to VSSQ on all input only
connections
- 1.0
VCCQ + 1.0
Input voltage with respect to VSSQ on all I/O
connections
-1.0
VCCQ + 1.0
+100
VCCQ current
-100
mA
Note
33. Excludes power supplies VCC/VCCQ. Test conditions: VCC = VCCQ, one connection at a time tested, connec-
tions not being tested are at VSS
.
9.4
Operating ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
9.4.1
Temperature ranges
Table 19
Temperature ranges
Spec
Parameter
Symbol
Device
Unit
Min
–40
–40
–40
–40
–40
Max
85
Industrial (I)
Industrial plus (V)
105
85
Ambient temperature
TA
Automotive, AEC-Q100 Grade 3 (A)
Automotive, AEC-Q100 Grade 2 (B)
Automotive, AEC-Q100 Grade 1 (M)
°C
105
125
9.4.2
Table 20
Power supply voltages
Power supply voltages
Description
CC power supply
Min
Max
Unit
V
1.7
2.0
V
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Electrical specifications
9.5
DC characteristics
Table 21
DC characteristics (CMOS compatible)
Value
Parameter
Description
Test conditions
Unit
[34]
Min
Typ
Max
Input leakage current.
Device reset signal HIGH
ILI2
–
–
2
VIN = VSS to VCC, VCC = VCC
max
µA
Input leakage current
ILI4
–
–
–
–
15
20
22
Device reset signal LOW[35]
VCC Active read current
Operating temperature range
ICC1
14
CS# = VSS, CK@200 MHz,
VCC = VCC max
mA
VCC Active write current
Operating temperature range
ICC2
16
CS# = VCC, VCC = VCC max;
full array
–
–
–
–
–
–
–
–
–
–
–
–
–
–
470
–
1200
850
700
600
850
700
600
1550
1150
950
850
1150
950
850
CS# = VCC, VCC = VCC max;
bottom 1/2 array
CS# = VCC, VCC = VCC max;
bottom 1/4 array
–
VCC standby current
(-40 °C to +85 °C)
CS# = VCC, VCC = VCC max;
bottom 1/8 array
–
µA
CS# = VCC, VCC = VCC max;
top 1/2 array
–
CS# = VCC, VCC = VCC max;
top 1/4 array
–
CS# = VCC, VCC = VCC max;
top 1/8 array
–
ICC4
CS# = VCC, VCC = VCC max;
full array
470
–
CS# = VCC, VCC = VCC max;
bottom 1/2 array
CS# = VCC, VCC = VCC max;
bottom 1/4 array
–
VCC standby current
(-40 °C to +105 °C)
CS# = VCC, VCC = VCC max;
bottom 1/8 array
–
µA
CS# = VCC, VCC = VCC max;
top 1/2 array
–
CS# = VCC, VCC = VCC max;
top 1/4 array
–
CS# = VCC, VCC = VCC max;
top 1/8 array
–
Notes
34. Not 100% tested.
35. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during
RESET# LOW insignificant.
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Electrical specifications
Table 21
DC characteristics (CMOS compatible) (continued)
Value
Parameter
Description
Test conditions
Unit
[34]
Min
Typ
Max
CS# = VCC, VCC = VCC max;
full array
–
470
2000
CS# = VCC, VCC = VCC max;
bottom 1/2 array
–
–
–
–
–
–
–
–
–
–
–
–
1550
1250
1100
1550
1250
1100
CS# = VCC, VCC = VCC max;
bottom 1/4 array
VCC standby current
(-40 °C to +125 °C)
CS# = VCC, VCC = VCC max;
bottom 1/8 array
ICC4
µA
CS# = VCC, VCC = VCC max;
top 1/2 array
CS# = VCC, VCC = VCC max;
top 1/4 array
CS# = VCC, VCC = VCC max;
top 1/8 array
Reset current (-40°C to +85°C)
Reset current (-40°C to +105°C)
Reset current (-40°C to +125°C)
–
–
–
–
–
–
0.55
0.75
1
CS# = VCC, RESET# = VSS
VCC = VCC max
,
,
ICC5
Active clock stop current
(-40 °C to +85 °C)
–
–
–
17
17
17
25
30
40
mA
Active clock stop current
(-40 °C to +105 °C)
CS# = VSS, RESET# = VCC
VCC = VCC max
ICC6
Active clock stop current
(-40 °C to +125 °C)
VCC current during power
up[34]
CS# = VCC, VCC = VCC max,
VCCQ = VCC
ICC7
–
–
35
Deep power down current
(-40 °C to +85 °C)
–
–
–
–
–
–
–
–
–
12
15
Deep power down current
(-40 °C to +105 °C)
[34]
IDPD
CS# = VCC, VCC = VCC max
µA
µA
Deep power down current
(-40 °C to +125 °C)
–
20
CS# = VCC; VCC = VCC max;
full array
140
–
1100
800
600
500
CS# = VCC; VCC = VCC max;
bottom 1/2 array
Hybrid sleep current
(-40 °C to +85 °C)
[34]
IHS
CS# = VCC; VCC = VCC max;
bottom 1/4 array
–
CS# = VCC; VCC = VCC max;
bottom 1/8 array
–
Notes
34. Not 100% tested.
35. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during
RESET# LOW insignificant.
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Electrical specifications
Table 21
DC characteristics (CMOS compatible) (continued)
Value
Parameter
Description
Test conditions
Unit
[34]
Min
Typ
Max
CS# = VCC; VCC = VCC max;
top 1/2 array
–
–
800
Hybrid sleep current
(-40 °C to +85 °C)
CS# = VCC; VCC = VCC max;
top 1/4 array
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
600
500
1250
850
650
550
850
650
550
1500
1150
900
750
1150
900
750
µA
CS# = VCC; VCC = VCC max;
top 1/8 array
CS# = VCC; VCC = VCC max;
full array
140
CS# = VCC; VCC = VCC max;
bottom 1/2 array
–
–
CS# = VCC; VCC = VCC max;
bottom 1/4 array
Hybrid sleep current
(-40 °C to +105 °C)
CS# = VCC; VCC = VCC max;
bottom 1/8 array
–
µA
CS# = VCC; VCC = VCC max;
top 1/2 array
–
CS# = VC; VCC = VCC max;
top 1/4 array
[34]
IHS
–
CS# = VCC; VCC = VCC max;
top 1/8 array
–
CS# = VCC; VCC = VCC max;
full array
140
–
CS# = VCC; VCC = VCC max;
bottom 1/2 array
CS# = VCC; VCC = VCC max;
bottom 1/4 array
–
Hybrid sleep current
(-40 °C to +125 °C)
CS# = VCC; VCC = VCC max;
bottom 1/8 array
–
µA
CS# = VCC; VCC = VCC max;
top 1/2 array
–
CS# = VCC; VCC = VCC max;
top 1/4 array
–
CS# = VCC; VCC = VCC max;
top 1/8 array
–
VIL
Input low voltage
Input high voltage
Output low voltage
Output high voltage
–
–
-0.15 × VCCQ
0.70 × VCCQ
–
–
–
–
–
0.30 × VCCQ
VIH
1.15 × VCCQ
V
VOL
VOH
Notes
0.2
–
IOL = 100 µA for DQ[7:0]
VCCQ - 0.20
34. Not 100% tested.
35. RESET# LOW initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during
RESET# LOW insignificant.
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Electrical specifications
9.5.1
Table 22
Capacitance characteristics
Capacitive characteristics[36-38]
256 Mb
Max
3.0
Description
Parameter
Unit
Input capacitance (CK, CK#, CS#)
Delta input capacitance (CK, CK#)
Output capacitance (RWDS)
IO capacitance (DQx)
CI
CID
CO
0.25
3.0
pF
CIO
CIOD
3.0
IO capacitance delta (DQx)
Notes
0.25
36. These values are guaranteed by design and are tested on a sample basis only.
37. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector
network analyzer. VCC, VCCQ are applied and all other signals (except the signal under test) floating. DQs
should be in the high impedance state.
38. Note that the capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance
values to allow for signal propagation time matching in the system. The capacitance value for CS# is not as
critical because there are no critical timings between CS# going active (LOW) and data being presented on
the DQ’s bus.
Table 23
Thermal resistance
Description
24-ballFBGA
package
Parameter[39]
Test conditions
Unit
θJA
Thermal resistance Test conditions follow standard test methods
(junction to ambient) and procedures for measuring thermal
40.8
°C/W
impedance, per EIA/JESD51.
θJC
Thermal resistance
(junction to case)
8
Note
39. This parameter is guaranteed by characterization; not tested in production.
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Electrical specifications
9.6
Power-up initialization
HYPERRAM™ products include an on-chip voltage sensor used to launch the power-up initialization process. VCC
and VCCQ must be applied simultaneously. When the power supply reaches a stable level at or above VCC(min),
the device will require tVCS time to complete its self-initialization process.
The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min) is
reached during power-up, and then CS# must remain high for a further delay of tVCS. A simple pull-up resistor
from VCCQ to chip select (CS#) can be used to insure safe and proper power-up.
If RESET# is LOW during power up, the device delays start of the tVCS period until RESET# is HIGH. The tVCS period
is used primarily to perform refresh operations on the DRAM array to initialize it.
When initialization is complete, the device is ready for normal operation.
Vcc_VccQ
VCC Minimum
Device
Access Allowed
tVCS
CS#
RESET#
Figure 29
Power-up with RESET# HIGH
Vcc_VccQ
CS#
VCC Minimum
Device
Access Allowed
tVCS
RESET#
Figure 30
Table 24
Power-up with RESET# LOW
Power up and reset parameters[40-42]
Parameter
Description
Min
Max
Unit
VCC
VCC Power supply
1.7
2.0
V
VCC and VCCQ ≥ minimum and RESET# HIGH to
first access
tVCS
-
150
µs
Notes
40. Bus transactions (read and write) are not allowed during the power-up reset time (tVCS).
41. VCCQ must be the same voltage as VCC
42. VCC ramp rate may be non-linear.
.
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Electrical specifications
9.7
Power down
HYPERRAM™ devices are considered to be powered-off when the array power supply (VCC) drops below the VCC
lock-out voltage (VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or
equal to VCC. At the VLKO level, the HYPERRAM™ device will have lost configuration or array data.
VCC must always be greater than or equal to VCCQ (VCC ≥ VCCQ).
During power-down or voltage drops below VLKO, the array power supply voltages must also drop below VCC
Reset (VRST) for a power down period (tPD) for the part to initialize correctly when the power supply again rises to
VCC minimum. See Figure 31.
If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is
again above VCC minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no
assurance that the POR process will be performed. In this case, a hardware reset will be required ensure the
device is properly initialized.
V
(Max)
(Min)
CC
V
CC
No Device Access Allowed
V
CC
Device Access
Allowed
t
VCS
V
LKO
V
RST
t
PD
Time
Figure 31
Power down or voltage drop
The following section describes HYPERRAM™ device dependent aspects of power down specifications.
Table 25
Symbol
Power-down voltage and timing[42]
Parameter
VCC power supply
Min
1.7
1.5
0.7
50
Max
Unit
V
VCC
VLKO
VRST
tPD
2.0
VCC lock-out below which re-initialization is required
VCC low voltage needed to ensure initialization will occur
Duration of VCC ≤ VRST
-
-
-
V
V
µs
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Electrical specifications
9.8
Hardware reset
The RESET# input provides a hardware method of returning the device to the standby state.
During tRPH the device will draw ICC5 current. If RESET# continues to be held LOW beyond tRPH, the device draws
CMOS standby current (ICC4). While RESET# is LOW (during tRP), and during tRPH, bus transactions are not allowed.
A hardware reset will do the following:
• Cause the configuration registers to return to their default values
• Halt self-refresh operation while RESET# is LOW - memory array data is considered as invalid
• Force the device to exit the hybrid sleep state
• Force the device to exit the deep power down state
After RESET# returns HIGH, the self-refresh operation will resume. Because self-refresh operation is stopped
during RESET# LOW, and the self-refresh row counter is reset to its default value, some rows may not be refreshed
within the required array refresh interval per Table 14. This may result in the loss of DRAM array data during or
immediately following a hardware reset. The host system should assume DRAM array data is lost after a hardware
reset and reload any required data.
tRP
RESET#
tRH
tRPH
CS#
Figure 32
Table 26
Hardware reset timing diagram
Power-up and reset parameters
Parameter
Description
Min
200
200
Max
Unit
ns
tRP
tRH
RESET# Pulse Width
-
-
Time between RESET# (HIGH) and CS#
(LOW)
ns
tRPH
RESET# LOW to CS# LOW
400
-
ns
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Timing specifications
10
Timing specifications
The following section describes HYPERRAM™ device dependent aspects of timing specifications.
10.1
Key to switching waveforms
Valid_High_or_Low
High_to_Low_Transition
Low_to_High_Transition
Invalid
High_Impedance
Figure 33
Key to switching waveforms
10.2
AC test conditions
Device
Under
Test
CL
Figure 34
Table 27
Test setup
Test specification[44]
Parameter
All Speeds
15
Units
pF
V/ns
V
Output load capacitance, CL
Minimum input rise and fall slew rates (1.8 V)[43]
1.13
Input pulse levels
0.0-VCCQ
Input timing measurement reference levels
Output timing measurement reference levels
V
CCQ/2
CCQ/2
V
V
V
Notes
43. All AC timings assume this input slew rate.
44. Input and output timing is referenced to VCCQ/2 or to the crossing of CK/CK#.
VccQ
Input VccQ / 2
Measurement Level
VccQ / 2 Output
Vss
Figure 35
Note
Input waveforms and measurement levels[45]
45. Input timings for the differential CK/CK# pair are measured from clock crossings.
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Timing specifications
10.3
CLK characteristics
t
CK
t
t
CKHP
CKHP
CK#
V
IX (Max)
VCCQ / 2
V
IX (Min)
CK
Figure 36
Table 28
Clock characteristics
Clock timings[46-48]
Parameter
200 MHZ
Symbol
Unit
Min
5
Max
–
CK period
tCK
ns
CK half period - duty cycle
tCKHP
0.45
0.55
tCK
CK half period at frequency
Min = 0.45 tCK min
Max = 0.55 tCK min
tCKHP
2.25
2.75
ns
Notes
46. Clock jitter of ±5% is permitted
47. Minimum frequency (Maximum tCK) is dependent upon maximum CS# low time (tCSM), initial latency, and
burst length.
48. CK and CK# input slew rate must be ≥ 1 V/ns (2 V/ns if measured differentially).
Table 29
Clock AC/DC electrical characteristics[49, 50]
Parameter Symbol
Min
Max
Unit
DC input voltage
VIN
VID(DC)
VID(AC)
VIX
–0.3
VCCQ + 0.3
VCCQ + 0.6
VCCQ + 0.6
VCCQ x 0.6
V
V
V
V
DC input differential voltage
AC input differential voltage
AC differential crossing voltage
Notes
VCCQ x 0.4
VCCQ x 0.6
VCCQ x 0.4
49. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
50. The value of VIX is expected to equal VCCQ/2 of the transmitting device and must track variations in the DC
level of VCCQ
.
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Timing specifications
10.4
AC characteristics
10.4.1
Read transactions
Table 30
HYPERRAM™ specific read timing parameters
200 MHZ
Parameter
Symbol
Unit
Min
Max
–
Chip select high between transactions
HYPERRAM™ read-write recovery time
Chip select setup to next CK rising edge
Data strobe valid
t
6.0
35
4.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSHI
t
–
RWR
t
–
CSS
t
5.0
–
DSV
t
Input setup
0.5
0.5
35
0
IS
Input hold
t
–
IH
t
HYPERRAM™ read initial access time
Clock to DQs Low Z
–
ACC
t
–
DQLZ
CK transition to DQ valid
CK transition to DQ invalid
t
1.0
0
5.0
4.2
CKD
t
CKDI
Data valid (tDV min = the lesser of: tCKHP min - tCKD max + tCKDI max) or tCKHP
min - tCKD min + tCKDI min)
[51, 52]
tDV
1.45
–
ns
CK transition to RWDS valid
tCKDS
1.0
–0.4
–0.4
0
5.0
+0.4
+0.4
–
ns
ns
ns
ns
ns
ns
ns
ns
t
RWDS transition to DQ valid
DSS
RWDS transition to DQ invalid
Chip select hold after CK falling edge
Chip select inactive to RWDS High-Z
Chip select inactive to DQ High-Z
Refresh time
tDSH
t
CSH
tDSZ
tOZ
–
5.0
5.0
–
–
t
35
1.0
RFH
t
CK transition to RWDS low @CA phase @read
5.5
CKDSR
Notes
51. Refer to Figure 39 for data valid timing.
52. The tDV timing calculation is provided for reference only, not to determine the spec limit. The spec limit is
guaranteed by testing.
CS#
tCSH
tRWR=Read
tACC
Write Recovery
tCSS
CK#, CK
RWDS
tDSZ
4 cycle latency
tCKDS
tDSV
Low: 1X Latency Count
tIS
tOZ
tDSS
tIH
tDQLZ
tCKD
tDSH
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
Dn
A
Dn+1
A
Dn+2
A
Dn+3
A
DQ[7:0]
RWDS and Data
are edge aligned
Command - Address
Host drives DQ[7:0] and Memory drives RWDS
Memory drives DQ[7:0]
and RWDS
Figure 37
Read timing diagram — No additional latency required
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Timing specifications
tCSHI
CS#
tCSS
tRWR=Read
tCSH
Additional latency
4 cycle latency 1
tACC
Write Recovery
tCSS
CK#, CK
RWDS
tDSZ
4 cycle latency 2
tCKDS
tDSV
High: 2X Latency Count
tCKDSR
tOZ
tDSS
tDQLZ
tCKD
tIS
tIH
tDSH
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
Dn
A
Dn+1
A
Dn+2
A
Dn+3
A
DQ[7:0]
RWDS and Data
are edge aligned
Command - Address
Host drives DQ[7:0] and Memory drives RWDS
Memory drives DQ[7:0]
and RWDS
Figure 38
Read timing diagram — with additional latency required
CS#
tCKHP
tCSHS tCSS
CK
CK#
tDSZ
tOZ
tCKDS
RWDS
tDSS
tCKD
tCKDI
tDV
tDQLZ
tCKD
tDSH
Dn
A
Dn
B
Dn+1
A
Dn+1
B
DQ[7:0]
Figure 39
Data valid timing[53-55]
10.4.2
Write transactions
Table 31
Write timing parameters
200 MHz
Parameter
Symbol
Unit
Min
35
35
35
–
Max
Read-write recovery time
Access time
tRWR
tACC
tRFH
tCSM
tCSM
tDMV
–
–
–
4
1
–
ns
ns
ns
µs
µs
µs
Refresh time
Chip select maximum low time (85 °C)
Chip select maximum low time (105/125 °C)
RWDS data mask valid
–
0
Notes
53. tCKD and tCKDI parameters define the beginning and end position of data valid period.
54. tDSS and tDSH define how early or late DQ may transition relative to RWDS. This is a potential skew between
the CK to DQ delay tCKD and CK to RWDS delay tCKDS
.
55. Since DQ and RWDS are the same output types, the tCKD, and tCKDS values track together (vary by the same
ratio).
Datasheet
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Timing specifications
CS#
tCSH
tRWR=Read
Write Recovery
tCSS
CK#, CK
tIS
tIH
tDSV
tDSZ
tDMV
RWDS
Low: 1X Latency Count
tIS
tIS tIH
tIH
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
Dn
A
Dn+1
A
Dn+2
A
Dn+3
A
DQ[7:0]
CK and Data
are center aligned
Command - Address
Host drives DQ[7:0]
and RWDS
Host drives DQ[7:0] and Memory drives RWDS
Figure 40
Write timing diagram — no additional latency
CS#
tCSH
tRWR=Read
Additional Latency
4 cycle latency1
tACC
2tCK
Write Recovery
tCSS
CK#, CK
RWDS
tIS
tIH
tDSV
4 cycle latency2
tDSZ
tDMV
High: 2X Latency Count
tIS
tIS tIH
tIH
CMD
[7:0]
CMD
[7:0]
ADR
[31:24]
ADR
[23:16]
ADR
[15:8]
ADR
[7:0]
Dn
A
Dn+1
A
Dn+2
A
Dn+3
A
DQ[7:0]
CK and Data
Are center aligned
Command - Address
Host drives DQ[7:0] and Memory drives RWDS
Host drives DQ[7:0]
and RWDS
Figure 41
Write timing diagram — with additional latency required
Datasheet
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Timing specifications
10.5
Timing reference levels
tCK
VCCQ
CK, CK#
VT
VSSQ
tIS
tIH
tIS
tIH
VCCQ
VIH(min)
VIL(max)
VT
RWDS
VSSQ
tIS
tIH
tIS
tIH
VCCQ
VIH(min)
VIL(max)
VT
DQ[7:0]
VSSQ
Figure 42
DDR input timing reference levels
tSCK
VCCQ
RWDS
VT
VSSQ
VCCQ
tDSS
tDSH
VOH(min)
VOL(max)
VT
DQ[7:0]
VSSQ
Figure 43
DDR output timing reference levels
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Physical interface
11
Physical interface
11.1
FBGA 24-ball 5 x 5 array footprint
HYPERRAM™ devices are provided in fortified ball grid array (FBGA), 1 mm pitch, 24-ball, 5 x 5 ball array footprint,
with 6mm x 8mm body.
1
2
3
4
5
A
B
C
D
E
RFU
CK
CS#
Vss
RESET# RFU
CK#
VssQ
VccQ
DQ7
Vcc
DQ2
DQ3
RFU
RFU
DQ4
RFU
DQ1
DQ6
RWDS
DQ0
DQ5
VccQ VssQ
Figure 44
24-ball FBGA, 6 x 8 mm, 5 x 5 ball footprint, top view
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Physical interface
11.2
Physical diagrams
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
DIMENSIONS
SYMBOL
MIN.
-
NOM.
MAX.
1.00
-
A
-
-
2. ALL DIMENSIONS ARE IN MILLIMETERS.
A1
D
0.20
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
8.00 BSC
4.
5.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
E
6.00 BSC
4.00 BSC
4.00 BSC
5
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
D1
E1
MD
ME
N
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
5
24
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.40
b
0.35
0.45
eE
eD
SD
SE
1.00 BSC
1.00 BSC
0.00 BSC
0.00 BSC
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2.
8.
9.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION
OR OTHER MEANS.
002-15550 *A
JEDEC SPECIFICATION NO. REF: N/A
10.
Figure 45
Fortified ball grid array 24-ball 6 x 8 x 1.0 mm (VAA024)
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Ordering information
12
Ordering information
12.1
Ordering part number
The ordering part number is formed by a valid combination of the following:
S80KS 256
3
GA
B
H
I
02 0
Packing type
0 = Tray
3 = 13” Tape and reel
Model number (Additional ordering options)
02 = Standard 6 x 8 x 1.0 mm package (VAA024)
Temperature range / grade
I = Industrial (–40 °C to + 85 °C)
V = Industrial Plus (–40 °C to + 105 °C)
A = Automotive, AEC-Q100 Grade 3 (–40 °C to + 85 °C)
B = Automotive, AEC-Q100 Grade 2(–40 °C to + 105 °C)
M = Automotive, AEC-Q100 Grade 1(–40 °C to + 125 °C)
Package materials
H = Low-Halogen, Pb-free
Package type
B = 24-ball FBGA, 1.00 mm pitch (5x5 ball footprint)
Speed
GA = 200MHz
Device technology
2 = HYPERBUS™
3 = Octal xSPI
4 = HYPERBUS™ Extended-IO
Density
256 = 256 Mb
Device family
S80KS - Infineon Memory 1.8 V-only, HYPERRAM™ self-refresh
DRAM
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Ordering information
12.2
Valid combinations
The recommended combinations table lists configurations planned to be available in volume. Table 32 will be
updated as new combinations are released. Contact your local sales representative to confirm availability of
specific combinations and to check on newly released combinations.
Table 32
Valid combinations - standard
Package,
Density Technology Speed material, and
temperature
Device
family
Model Packing
Ordering part number Package marking
number
type
S80KS
S80KS
S80KS
S80KS
256
256
256
256
3
3
3
3
GA
GA
GA
GA
BHI
BHI
02
02
02
02
0
3
0
3
S80KS2563GABHI020
S80KS2563GABHI023
S80KS2563GABHV020
S80KS2563GABHV023
8KS2563GAHI02
8KS2563GAHI02
8KS2563GAHV02
8KS2563GAHV02
BHV
BHV
12.3
Valid combinations - Automotive Grade / AEC-Q100
Table 33 list configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in
volume. The table will be updated as new combinations are released. Contact your local sales representative to
confirm availability of specific combinations and to check on newly released combinations.
Production part approval process (PPAP) support is only provided for AEC-Q100 grade products.
Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade
products in combination with PPAP. Non-AEC-Q100 grade products are not manufactured or documented in full
compliance with ISO/TS-16949 requirements.
AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require
ISO/TS-16949 compliance.
Table 33
Valid combinations - Automotive Grade / AEC-Q100
Package,
Model Packing
Device
family
Density Technology Speed material, and
Ordering part number Package marking
number
type
temperature
BHA
S80KS
S80KS
S80KS
S80KS
S80KS
S80KS
256
256
256
256
256
256
3
3
3
3
3
3
GA
GA
GA
GA
GA
GA
02
02
02
02
02
02
0
3
0
3
0
3
S80KS2563GABHA020 8KS2563GAHA02
S80KS2563GABHA023 8KS2563GAHA02
S80KS2563GABHB020 8KS2563GAHB02
S80KS2563GABHB023 8KS2563GAHB02
S80KS2563GABHM020 8KS2563GAHM02
S80KS2563GABHM023 8KS2563GAHM02
BHA
BHB
BHB
BHM
BHM
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Acronyms
13
Acronyms
Table 34
Acronyms used in this document
Acronym
Description
CMOS
DCARS
DDR
complementary metal oxide semiconductor
DDR Center-Aligned Read Strobe
double data rate
DPD
deep power down
DRAM
HS
dynamic RAM
hybrid sleep
MSb
most significant bit
POR
power-on reset
PSRAM
PVT
pseudo static RAM
process, voltage, and temperature
read-write data strobe
serial peripheral interface
expanded serial peripheral interface
RWDS
SPI
xSPI
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Document conventions
14
Document conventions
14.1
Units of measure
Table 35
Units of measure
Symbol
Unit of measure
°C
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
MHz
µA
µs
mA
mm
ns
Ω
%
percent
pF
V
picofarad
volt
W
watt
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Revision history
Revision history
Document
Date of release
Description of changes
version
*C
2021-09-27
Publish to web.
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Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
The information given in this document shall in no
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Edition 2021-09-27
Published by
Infineon Technologies AG
81726 Munich, Germany
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Document reference
002-31339 Rev. *C
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