SAB-C161JI-LF_技术文档

Data Sheet, V3.0, Jan. 2001

C161CS-32R/-L

C161JC-32R/-L

C161JI-32R/-L

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2001-01

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

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characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

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Due to technical requirements components may contain dangerous substances. For information on the types in

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be endangered.

Data Sheet, V3.0, Jan. 2001

C161CS-32R/-L

C161JC-32R/-L

C161JI-32R/-L

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

C161CS/JC/JI

Revision History:

2001-01

V3.0

Previous Version:

2000-08 V2.0 (intermediate version)

1999-03

(Advance Information)

Page

All

Subjects (major changes since last revision)¹⁾

Converted to Infineon layout

2

Derivative Synopsis Table updated

4, 6, 10, 18 Programmable Interface Routing introduced

27, 28

29

GPT block diagrams updated

RTC description improved

35

OWD description improved

39ff

51

RSTCON and SDLM registers added

Description of input/output voltage and hysteresis improved

Separate table for power consumption

Clock generation mode table updated

External clock drive specification improved

Reset calibration time specified, definition of V_AREFimproved

Programmable sample time introduced

Timing tables updated to 25 MHz

53

57

60

62

63

65ff

1)

Changes refer to version 1999-03.

Controller Area Network (CAN): License of Robert Bosch GmbH

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16-Bit Single-Chip Microcontroller

C166 Family

C161CS/JC/JI

• High Performance 16-bit CPU with 4-Stage Pipeline

– 80 ns Instruction Cycle Time at 25 MHz CPU Clock

– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 MBytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 59 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),

via prescaler or via direct clock input

– Additional 32 kHz Oscillator

• On-Chip Memory Modules

– 2 KBytes On-Chip Internal RAM (IRAM)

– 8 KBytes On-Chip Extension RAM (XRAM)

– 256 KBytes On-Chip Mask ROM

• On-Chip Peripheral Modules

– 12-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 µs

– Two 16-Channel Capture/Compare Units (eight IO lines each)

– Two Multi-Functional General Purpose Timer Units with 5 Timers

– Two Asynchronous/Synchronous Serial Channels

– High-Speed Synchronous Serial Channel (SPI)

– On-Chip CAN Interface (Rev. 2.0B active, Full CAN / Basic CAN)

with 15 Message Objects (C161CS 2x, C161JC 1x)

– Serial Data Link Module (SDLM), compliant with J1850,

supporting Class 2 (C161JC/JI)

– IIC Bus Interface (10-bit Addressing, 400 kHz) with 2 Channels (multiplexed)

– On-Chip Real Time Clock

• Up to 16 MBytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Five Programmable Chip-Select Signals

– Hold- and Hold-Acknowledge Bus Arbitration Support

Data Sheet

1

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 93 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

• Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,

Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 128-Pin TQFP Package

This document describes several derivatives of the C161 group. Table 1 enumerates

these derivatives and summarizes the differences. As this document refers to all of these

derivatives, some descriptions may not apply to a specific product.

Table 1

C161CS/JC/JI Derivative Synopsis

Derivative

On-Chip

Program Memory Interface(s)

Serial Bus

Maximum CPU

Frequency

SAK-C161CS-32RF

SAB-C161CS-32RF

256 KByte ROM

CAN1, CAN2

CAN1, SDLM

SDLM

25 MHz

SAK-C161CS-LF

SAB-C161CS-LF

---

SAK-C161JC-32RF

SAB-C161JC-32RF

256 KByte ROM

SAK-C161JC-LF

SAB-C161JC-LF

---

SAK-C161JI-32RF

SAB-C161JI-32RF

256 KByte ROM

---

SAK-C161JI-LF

SAB-C161JI-LF

SDLM

For simplicity all versions are referred to by the term C161CS/JC/JI throughout this

document.

Data Sheet

2

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C161CS/JC/JI please refer to the “Product

Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Introduction

The C161CS/JC/JI derivatives are high performance derivatives of the Infineon

C166 Family of full featured single-chip CMOS microcontrollers. They combine high

CPU performance (up to 12.5 million instructions per second) with high peripheral

functionality and enhanced IO-capabilities. They also provide clock generation via PLL

and various on-chip memory modules such as program ROM, internal RAM, and

extension RAM.

V_DDV_SS

V_AREFV_AGND

Port 0

16 Bit

XTAL1

XTAL2

XTAL3

XTAL4

RSTIN

RSTOUT

NMI

Port 1

16 Bit

Port 2

8 Bit

Port 3

15 Bit

C161CS/JC/JI

Port 4

8 Bit

EA

READY

ALE

Port 6

8 Bit

RD

Port 7

4 Bit

WR/WRL

Port 5

12 Bit

Port 9

6 Bit

MCL04450

Figure 1

Logic Symbol

Data Sheet

3

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Pin Configuration

(top view)

RSTOUT

NMI

1

2

3

4

5

6

7

8

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

P0H.1/AD9

P0H.0/AD8

V_SS

V_DD

P6.0/CS0

P6.1/CS1

P6.2/CS2

V_DD

P0L.7/AD7

P0L.6/AD6

P0L.5/AD5

P0L.4/AD4

P0L.3/AD3

P0L.2/AD2

P0L.1/AD1

P0L.0/AD0

EA

P6.3/CS3

P6.4/CS4

9

P6.5/HOLD

P6.6/HLDA

P6.7/BREQ

P7.4/CC28IO/*

P7.5/CC29IO/*

P7.6/CC30IO/*

P7.7/CC31IO/*

V_SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

ALE

READY

WR/WRL

RD

V_SS

V_DD

P4.7/A23/*

P4.6/A22/*

P4.5/A21/*

P4.4/A20/*

P4.3/A19

P4.2/A18

P4.1/A17

P4.0/A16

V_SS

C161CS/JC/JI

V_DD

P9.0/SDA0

P9.1/SCL0

P9.2/SDA1

P9.3/SCL1

P9.4/SDA2

P9.5

V_SS

V_DD

P5.0/AN0

P5.1/AN1

P5.2/AN2

P5.3/AN3

P5.4/AN4

P5.5/AN5

V_DD

P3.15/CLKOUT/FOUT

P3.13/SCLK

P3.12/BHE/WRH

MCP04451

Figure 2

*) The marked pins of Port 4 and Port 7 can have interface lines assigned to them (CAN

interface in the C161CS and C161JC, SDLM interface in the C161JC and C161JI).

Table 2 on the pages below lists the possible assignments.

Data Sheet

4

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions

Symbol Pin

No.

Input Function

Outp.

RST

OUT

1

O

Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or

a watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI

2

I

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the C161CS/JC/JI to go into

power down mode. If NMI is high, when PWRDN is

executed, the part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

P6

IO

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 6 outputs can be configured as push/

pull or open drain drivers.

The Port 6 pins also serve for alternate functions:

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

5

6

7

8

9

10

11

O

I

CS0

CS1

CS2

CS3

CS4

HOLD

HLDA

Chip Select 0 Output

Chip Select 1 Output

Chip Select 2 Output

Chip Select 3 Output

Chip Select 4 Output

External Master Hold Request Input

Hold Acknowledge Output (master mode)

or Input (slave mode)

I/O

P6.7

12

O

BREQ

Bus Request Output

Data Sheet

5

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

P7

IO

Port 7 is a 4-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 7 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 7 is

selectable (TTL or special). Port 7 pins provide inputs/

outputs for CAPCOM2 and serial interface lines.¹⁾

P7.4

P7.5

P7.6

P7.7

13

14

15

16

I/O

I

O

I/O

O

I

I/O

I

O

I/O

O

I

CC28IO

CAPCOM2: CC28 Capture Inp./Compare Outp.,

CAN1_RxD CAN 1 Receive Data Input,

CAN2_RxD CAN 2 Receive Data Input,

SDL_TxD SDLM Transmit Data Output

(C161CS/JC)

(C161CS)

(C161JC/JI)

CC29IO

CAPCOM2: CC29 Capture Inp./Compare Outp.,

CAN1_TxD CAN 1 Transmit Data Output,

CAN2_TxD CAN 2 Transmit Data Output,

SDL_RxD SDLM Receive Data Input

(C161CS/JC)

(C161CS)

(C161JC/JI)

CC30IO

CAPCOM2: CC30 Capture Inp./Compare Outp.,

CAN1_RxD CAN 1 Receive Data Input,

CAN2_RxD CAN 2 Receive Data Input,

SDL_TxD SDLM Transmit Data Output

(C161CS/JC)

(C161CS)

(C161JC/JI)

CC31IO

CAPCOM2: CC31 Capture Inp./Compare Outp.,

CAN1_TxD CAN 1 Transmit Data Output,

CAN2_TxD CAN 2 Transmit Data Output,

SDL_RxD SDLM Receive Data Input

(C161CS/JC)

(C161CS)

(C161JC/JI)

P9

IO

Port 9 is a 6-bit bidirectional open drain I/O port (provide

external pullup resistors if required). It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

The following Port 9 pins also serve for alternate functions:

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

19

20

21

22

23

24

I/O

–

SDA0

SCL0

SDA1

SCL1

SDA2

–

IIC Bus Data Line 0

IIC Bus Clock Line 0

IIC Bus Data Line 1

IIC Bus Clock Line 1

IIC Bus Data Line 2

Note: Port 9 pins can only tolerate positive overload currents

(see Table 9).

Data Sheet

6

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

P5

I

Port 5 is a 12-bit input-only port with Schmitt-Trigger char.

The pins of Port 5 also serve as analog input channels for the

A/D converter, or they serve as timer inputs:

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

P5.12 37

P5.13 38

P5.14 39

P5.15 40

27

28

29

30

31

32

33

34

I

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN12,

AN13,

AN14,

AN15,

T6IN

T5IN

GPT2 Timer T6 Count Inp.

GPT2 Timer T5 Count Inp.

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.

T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.

Data Sheet

7

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

P2

IO

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 2 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 2 is

selectable (TTL or special).

The following Port 2 pins also serve for alternate functions:

P2.8

P2.9

43

44

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

CC8IO

EX0IN

CC9IO

EX1IN

CC10IO

EX2IN

CC11IO

EX3IN

CC12IO

EX4IN

CC13IO

EX5IN

CC14IO

EX6IN

CC15IO

EX7IN

T7IN

CAPCOM1: CC8 Capture Inp./Compare Output,

Fast External Interrupt 0 Input

CAPCOM1: CC9 Capture Inp./Compare Output,

Fast External Interrupt 1 Input

CAPCOM1: CC10 Capture Inp./Compare Outp.,

Fast External Interrupt 2 Input

CAPCOM1: CC11 Capture Inp./Compare Outp.,

Fast External Interrupt 3 Input

CAPCOM1: CC12 Capture Inp./Compare Outp.,

Fast External Interrupt 4 Input

CAPCOM1: CC13 Capture Inp./Compare Outp.,

Fast External Interrupt 5 Input

CAPCOM1: CC14 Capture Inp./Compare Outp.,

Fast External Interrupt 6 Input

CAPCOM1: CC15 Capture Inp./Compare Outp.,

Fast External Interrupt 7 Input,

P2.10 45

P2.11 46

P2.12 47

P2.13 48

P2.14 49

P2.15 50

CAPCOM2: Timer T7 Count Input

Note: During Sleep Mode a spike filter on the EXnIN

interrupt inputs suppresses input pulses < 10 ns.

Input pulses > 100 ns safely pass the filter.

Data Sheet

8

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

P3

IO

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 3 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or special).

The following Port 3 pins also serve for alternate functions:

P3.0

P3.1

53

54

I

T0IN

CAPCOM1 Timer T0 Count Input,

ASC1 Clock/Data Output (Async./Sync)

GPT2 Timer T6 Toggle Latch Output,

ASC1 Data Input (Async.) or Inp./Output (Sync.)

GPT2 Register CAPREL Capture Input

GPT1 Timer T3 Toggle Latch Output

GPT1 Timer T3 External Up/Down Control Input

GPT1 Timer T4 Count/Gate/Reload/Capture Inp

GPT1 Timer T3 Count/Gate Input

GPT1 Timer T2 Count/Gate/Reload/Capture Inp

SSC Master-Receive/Slave-Transmit Inp./Outp.

SSC Master-Transmit/Slave-Receive Outp./Inp.

ASC0 Clock/Data Output (Async./Sync.)

ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe

SSC Master Clock Output / Slave Clock Input.

O

I/O

I

O

I

I/O

O

I/O

O

I/O

O

TxD1

T6OUT

RxD1

CAPIN

T3OUT

T3EUD

T4IN

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

55

56

57

58

59

60

61

62

T3IN

T2IN

MRST

MTSR

TxD0

RxD0

BHE

P3.10 63

P3.11 64

P3.12 65

WRH

SCLK

P3.13 66

P3.15 67

CLKOUT System Clock Output (= CPU Clock)

FOUT Programmable Frequency Output

Data Sheet

9

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

P4

IO

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. The Port 4 outputs can be configured as

push/pull or open drain drivers. The input threshold of Port 4

is selectable (TTL or special).

Port 4 can be used to output the segment address lines and

for serial interface lines:¹⁾

P4.0

P4.1

P4.2

P4.3

P4.4

70

71

72

73

74

O

I

A16

A17

A18

A19

A20

Least Significant Segment Address Line

Segment Address Line

Segment Address Line,

CAN2_RxD CAN 2 Receive Data Input,

SDL_RxD SDLM Receive Data Input

(C161CS)

(C161JC/JI)

I

P4.5

P4.6

75

76

O

I

O

I

A21

CAN1_RxD CAN 1 Receive Data Input,

A22 Segment Address Line,

CAN1_TxD CAN 1 Transmit Data Output,

CAN2_TxD CAN 2 Transmit Data Output,

SDL_RxD SDLM Receive Data Input

Segment Address Line,

(C161CS/JC)

(C161CS)

(C161JC/JI)

P4.7

77

O

I

O

I

A23

Most Significant Segment Address Line,

CAN1_RxD CAN 1 Receive Data Input,

CAN2_TxD CAN 2 Transmit Data Output,

CAN2_RxD CAN 2 Receive Data Input,

SDL_TxD SDLM Transmit Data Output

(C161CS/JC)

(C161CS)

(C161JC/JI)

O

RD

80

81

O

External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR/

WRL

External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL-mode

this pin is activated for low byte data write accesses on a

16-bit bus, and for every data write access on an 8-bit bus.

See WRCFG in register SYSCON for mode selection.

Data Sheet

10

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

READY 82

I

Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force

the insertion of memory cycle time waitstates until the pin

returns to a low level.

An internal pullup device will hold this pin high when nothing

is driving it.

ALE

EA

83

84

O

I

Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the

multiplexed bus modes.

External Access Enable pin. A low level at this pin during and

after Reset forces the C161CS/JC/JI to begin instruction

execution out of external memory. A high level forces

execution out of the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

PORT0

P0L.0-7 85-

92

P0H.0-7 95-

102

IO

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state.

In case of an external bus configuration, PORT0 serves as

the address (A) and address/data (AD) bus in multiplexed

bus modes and as the data (D) bus in demultiplexed bus

modes.

Demultiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

D0 – D7

I/O

16-bit

D0 - D7

D8 - D15

Multiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

16-bit

AD0 – AD7 AD0 - AD7

A8 - A15 AD8 - AD15

Note: At the end of an external reset (EA = ‘0’) PORT0 also

inputs the configuration values.

Data Sheet

11

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

PORT1

P1L.0-7 103-

110

P1H.0-7 113-

120

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state. PORT1 is used as the

16-bit address bus (A) in demultiplexed bus modes and also

after switching from a demultiplexed bus mode to a

multiplexed bus mode.

The following PORT1 pins also serve for alternate functions:

P1H.4 117

P1H.5 118

P1H.6 119

P1H.7 120

I/O

CC24IO

CC25IO

CC26IO

CC27IO

CAPCOM2: CC24 Capture Inp./Compare Outp.

CAPCOM2: CC25 Capture Inp./Compare Outp.

CAPCOM2: CC26 Capture Inp./Compare Outp.

CAPCOM2: CC27 Capture Inp./Compare Outp.

XTAL2 123

XTAL1 124

O

I

XTAL2:

XTAL1:

Output of the oscillator amplifier circuit.

Input to the oscillator amplifier and input to

the internal clock generator

To clock the device from an external source, drive XTAL1,

while leaving XTAL2 unconnected. Minimum and maximum

high/low and rise/fall times specified in the AC

Characteristics must be observed.

XTAL3 126

XTAL4 127

I

XTAL3:

Input to the 32-kHz oscillator amplifier and

input to the internal clock generator

Output of the oscillator amplifier circuit.

O

XTAL4:

To clock the device from an external source, drive XTAL3,

while leaving XTAL4 unconnected. Minimum and maximum

high/low and rise/fall times specified in the AC

Characteristics must be observed.

Data Sheet

12

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

RSTIN 128

I/O

Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C161CS/

JC/JI. An internal pullup resistor permits power-on reset

using only a capacitor connected to V_SS.

A spike filter suppresses input pulses < 10 ns. Input pulses

> 100 ns safely pass the filter. The minimum duration for a

safe recognition should be 100 ns + 2 CPU clock cycles.

In bidirectional reset mode (enabled by setting bit BDRSTEN

in register SYSCON) the RSTIN line is internally pulled low

for the duration of the internal reset sequence upon any reset

(HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle and to

let the PLL lock a reset duration of ca. 1 ms is

recommended.

V_AREF35

V_AGND36

–

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

V_DD

4, 18,

Digital Supply Voltage:

26²⁾,

+5 V during normal operation and idle mode.

≥ 2.5 V during power down mode if RTC is off

≥ 2.7 V during power down mode if RTC is running

42, 52,

68, 78,

93, 111,

121

V_SS

3, 17,

25²⁾,

–

Digital Ground.

41, 51,

69, 79,

94, 112,

122,

125

1)

The CAN and/or SDLM interface lines are assigned to ports P4 and P7 under software control. Within the CAN

module or SDLM several assignments can be selected.

2)

Supply pins 25 and 26 feed the Analog/Digital Converter and should be decoupled separately.

Data Sheet

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C161CS/JC/JI-32R

C161CS/JC/JI-L

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared

automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the

bootstrap loader may be activated when P0L.4 is low.

• Pin RSTIN may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet

14

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Functional Description

The architecture of the C161CS/JC/JI combines advantages of both RISC and CISC

processors and of advanced peripheral subsystems in a very well-balanced way. In

addition the on-chip memory blocks allow the design of compact systems with maximum

performance.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the C161CS/JC/JI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

C166-Core

ProgMem

IRAM

Internal

RAM

16

Data

32

16

ROM

256 KByte

Instr. / Data

CPU

2 KByte

Osc / PLL

XTAL

XRAM

8 KByte

PEC

External Instr. / Data

16-Level

Priority

Interrupt Controller

ASC1

(USART)

RTC WDT

16

Interrupt Bus

IIC

400 KBd, 2 Ch.

Peripheral Data Bus

16

CAN/SDLM

2.0B act. / Cl.B

ADC ASC0 SSC

GPT

CCOM2CCOM1

10-Bit

(USART)

(SPI)

T2

T3

T4

T7

T8

T0

T1

12

Channels

EBC

8

XBUS Control

External Bus

Control

8

T5

T6

BRGen

Port 0

Port 1

Port 5

Port 3

Port 7

4

Port 9

6

16

12

15

MCB04323_1CSR

Figure 3

Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are

connected to the CPU via separate buses. A fourth bus, the XBUS, connects external

resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).

The XBUS resources (XRAM, CAN, SDLM, IIC, ASC1) of the C161CS/JC/JI can be

enabled during initialization by setting the general X-Peripheral enable bit XPEN

(SYSCON.2).

If the X-Peripherals remain disabled they consume neither address space nor port pins.

Data Sheet

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C161CS/JC/JI-32R

C161CS/JC/JI-L

Memory Organization

The memory space of the C161CS/JC/JI is configured in a Von Neumann architecture

which means that code memory, data memory, registers and I/O ports are organized

within the same linear address space which includes 16 MBytes. The entire memory

space can be accessed bytewise or wordwise. Particular portions of the on-chip memory

have additionally been made directly bitaddressable.

The C161CS/JC/JI incorporates 256 KBytes of on-chip mask-programmable ROM for

code or constant data. The lower 32 KBytes of the on-chip ROM can be mapped either

to segment 0 or segment 1.

2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined

variables, for the system stack, general purpose register banks and even for code. A

register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,

…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the C166 Family.

8 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user

stacks, or code. The XRAM is accessed like external memory and therefore cannot be

used for the system stack or for register banks and is not bitaddressable. The XRAM

permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the

microcontroller.

Data Sheet

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C161CS/JC/JI-32R

C161CS/JC/JI-L

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus

Controller (EBC). It can be programmed either to Single Chip Mode when no external

memory is required, or to one of four different external memory access modes, which

are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/

output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses

and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,

Memory Tri-State Time, Length of ALE and Read Write Delay) have been made

programmable to allow the user the adaption of a wide range of different types of

memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs

ADDRSELx / BUSCONx) which control the access to different resources with different

bus characteristics. These address windows are arranged hierarchically where

BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to

locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 5 external CS signals (4 windows plus default) can be generated in order to save

external glue logic. The C161CS/JC/JI offers the possibility to switch the CS outputs to

an unlatched mode. In this mode the internal filter logic is switched off and the CS signals

are directly generated from the address. The unlatched CS mode is enabled by setting

CSCFG (SYSCON.6).

Access to very slow memories or memories with varying access times is supported via

a particular ‘Ready’ function.

A HOLD/HLDA protocol is available for bus arbitration and allows to share external

resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN

in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)

are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA

pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA

is switched to input. This allows to directly connect the slave controller to another master

controller without glue logic.

For applications which require less than 16 MBytes of external memory space, this

address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case

Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an

address space of 16 MBytes is used.

Data Sheet

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C161CS/JC/JI-32R

C161CS/JC/JI-L

Note: When one or both of the on-chip CAN Modules or the SDLM are used with the

interface lines assigned to Port 4, the interface lines override the segment address

lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e.

address lines A21/A19 … A16. CS lines can be used to increase the total amount

of addressable external memory.

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic

and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a

separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161CS/JC/JI’s instructions can be

executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For

example, shift and rotate instructions are always processed during one machine cycle

independent of the number of bits to be shifted. All multiple-cycle instructions have been

optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16

bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline

optimization, the so-called ‘Jump Cache’, allows reducing the execution time of

repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

CPU

16

Internal

RAM

SP

STKOV

STKUN

MDH

MDL

R15

Exec. Unit

Instr. Ptr.

Instr. Reg.

Mul/Div-HW

Bit-Mask Gen

General

Purpose

Registers

R15

ALU

32

4-Stage

Pipeline

(16-bit)

ROM

Barrel - Shifter

Context Ptr.

R0

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

16

R0

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Data Page Ptr.

Code Seg. Ptr.

MCB02147

Figure 4

CPU Block Diagram

Data Sheet

18

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.

These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer

(CP) register determines the base address of the active register bank to be accessed by

the CPU at any time. The number of register banks is only restricted by the available

internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The

system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the

stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly

compared against the stack pointer value upon each stack access for the detection of a

stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently

be utilized by a programmer via the highly efficient C161CS/JC/JI instruction set which

includes the following instruction classes:

– Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes

and words. A variety of direct, indirect or immediate addressing modes are provided to

specify the required operands.

Data Sheet

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V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of

internal program execution), the C161CS/JC/JI is capable of reacting very fast to the

occurrence of non-deterministic events.

The architecture of the C161CS/JC/JI supports several mechanisms for fast and flexible

response to service requests that can be generated from various sources internal or

external to the microcontroller. Any of these interrupt requests can be programmed to

being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is

suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies

a single byte or word data transfer between any two memory locations with an additional

increment of either the PEC source or the destination pointer. An individual PEC transfer

counter is implicity decremented for each PEC service except when performing in the

continuous transfer mode. When this counter reaches zero, a standard interrupt is

performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data.

The C161CS/JC/JI has 8 PEC channels each of which offers such fast interrupt-driven

data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable

flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via

its related register, each source can be programmed to one of sixteen interrupt priority

levels. Once having been accepted by the CPU, an interrupt service can only be

interrupted by a higher prioritized service request. For the standard interrupt processing,

each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high

precision requirements. These fast interrupt inputs feature programmable edge

detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with

an individual trap (interrupt) number.

Table 3 shows all of the possible C161CS/JC/JI interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt

request bit (xIR).

Data Sheet

20

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 3

C161CS/JC/JI Interrupt Nodes

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Trap

Vector

Location Number

CAPCOM Register 0

CAPCOM Register 1

CAPCOM Register 2

CAPCOM Register 3

CAPCOM Register 4

CAPCOM Register 5

CAPCOM Register 6

CAPCOM Register 7

CAPCOM Register 8

CAPCOM Register 9

CC0IR

CC1IR

CC2IR

CC3IR

CC4IR

CC5IR

CC6IR

CC7IR

CC8IR

CC9IR

CC0IE

CC0INT

CC1INT

CC2INT

CC3INT

CC4INT

CC5INT

CC6INT

CC7INT

CC8INT

CC9INT

00’0040_H10_H

00’0044_H11_H

00’0048_H12_H

00’004C_H13_H

00’0050_H14_H

00’0054_H15_H

00’0058_H16_H

00’005C_H17_H

00’0060_H18_H

00’0064_H19_H

CC1IE

CC2IE

CC3IE

CC4IE

CC5IE

CC6IE

CC7IE

CC8IE

CC9IE

CAPCOM Register 10 CC10IR

CAPCOM Register 11 CC11IR

CAPCOM Register 12 CC12IR

CAPCOM Register 13 CC13IR

CAPCOM Register 14 CC14IR

CAPCOM Register 15 CC15IR

CAPCOM Register 16 CC16IR

CAPCOM Register 17 CC17IR

CAPCOM Register 18 CC18IR

CAPCOM Register 19 CC19IR

CAPCOM Register 20 CC20IR

CAPCOM Register 21 CC21IR

CAPCOM Register 22 CC22IR

CAPCOM Register 23 CC23IR

CAPCOM Register 24 CC24IR

CAPCOM Register 25 CC25IR

CAPCOM Register 26 CC26IR

CAPCOM Register 27 CC27IR

CAPCOM Register 28 CC28IR

CAPCOM Register 29 CC29IR

CC10IE

CC11IE

CC12IE

CC13IE

CC14IE

CC15IE

CC16IE

CC17IE

CC18IE

CC19IE

CC20IE

CC21IE

CC22IE

CC23IE

CC24IE

CC25IE

CC26IE

CC27IE

CC28IE

CC29IE

CC10INT 00’0068_H1A_H

CC11INT 00’006C_H1B_H

CC12INT 00’0070_H1C_H

CC13INT 00’0074_H1D_H

CC14INT 00’0078_H1E_H

CC15INT 00’007C_H1F_H

CC16INT 00’00C0_H30_H

CC17INT 00’00C4_H31_H

CC18INT 00’00C8_H32_H

CC19INT 00’00CC_H33_H

CC20INT 00’00D0_H34_H

CC21INT 00’00D4_H35_H

CC22INT 00’00D8_H36_H

CC23INT 00’00DC_H37_H

CC24INT 00’00E0_H38_H

CC25INT 00’00E4_H39_H

CC26INT 00’00E8_H3A_H

CC27INT 00’00EC_H3B_H

CC28INT 00’00E0_H3C_H

CC29INT 00’0110_H44_H

Data Sheet

21

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 3

C161CS/JC/JI Interrupt Nodes (cont’d)

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Trap

Vector

Location Number

CAPCOM Register 30 CC30IR

CC30IE

CC31IE

T0IE

CC30INT 00’0114_H45_H

CAPCOM Register 31 CC31IR

CC31INT 00’0118_H46_H

CAPCOM Timer 0

CAPCOM Timer 1

CAPCOM Timer 7

CAPCOM Timer 8

GPT1 Timer 2

T0IR

T1IR

T7IR

T8IR

T2IR

T3IR

T4IR

T5IR

T6IR

CRIR

T0INT

T1INT

T7INT

T8INT

T2INT

T3INT

T4INT

T5INT

T6INT

CRINT

ADCINT

ADEINT

S0TINT

00’0080_H20_H

00’0084_H21_H

00’00F4_H3D_H

00’00F8_H3E_H

00’0088_H22_H

00’008C_H23_H

00’0090_H24_H

00’0094_H25_H

00’0098_H26_H

00’009C_H27_H

00’00A0_H28_H

00’00A4_H29_H

00’00A8_H2A_H

T1IE

T7IE

T8IE

T2IE

GPT1 Timer 3

T3IE

GPT1 Timer 4

T4IE

GPT2 Timer 5

T5IE

GPT2 Timer 6

T6IE

GPT2 CAPREL Reg.

CRIE

A/D Conversion Compl. ADCIR

ADCIE

ADEIE

S0TIE

S0TBIE

S0RIE

S0EIE

SCTIE

SCRIE

SCEIE

XP0IE

XP1IE

XP2IE

XP3IE

XP4IE

XP5IE

XP6IE

XP7IE

A/D Overrun Error

ASC0 Transmit

ADEIR

S0TIR

ASC0 Transmit Buffer S0TBIR

S0TBINT 00’011C_H47_H

ASC0 Receive

ASC0 Error

S0RIR

S0EIR

SCTIR

SCRIR

SCEIR

S0RINT

S0EINT

SCTINT

SCRINT

SCEINT

XP0INT

XP1INT

XP2INT

XP3INT

XP4INT

XP5INT

XP6INT

XP7INT

00’00AC_H2B_H

00’00B0_H2C_H

00’00B4_H2D_H

00’00B8_H2E_H

00’00BC_H2F_H

00’0100_H40_H

00’0104_H41_H

00’0108_H42_H

00’010C_H43_H

00’0120_H48_H

00’0124_H49_H

00’0128_H4A_H

00’012C_H4B_H

SSC Transmit

SSC Receive

SSC Error

IIC Data Transfer Event XP0IR

IIC Protocol Event

CAN1 (C161CS/JC)

PLL/OWD and RTC

ASC1 Transmit

ASC1 Receive

XP1IR

XP2IR

XP3IR

XP4IR

XP5IR

XP6IR

XP7IR

ASC1 Error

CAN2 (C161CS) or

SDLM (C161JC/JI)

Data Sheet

22

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

The C161CS/JC/JI also provides an excellent mechanism to identify and to process

exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.

Hardware traps cause immediate non-maskable system reaction which is similar to a

standard interrupt service (branching to a dedicated vector table location). The

occurence of a hardware trap is additionally signified by an individual bit in the trap flag

register (TFR). Except when another higher prioritized trap service is in progress, a

hardware trap will interrupt any actual program execution. In turn, hardware trap services

can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

Hardware Reset

Software Reset

–

RESET

00’0000_H

00_H

III

W-dog Timer Overflow

Class A Hardware Traps:

Non-Maskable Interrupt NMI

NMITRAP 00’0008_H

STOTRAP 00’0010_H

STUTRAP 00’0018_H

02_H

04_H

06_H

II

Stack Overflow

Stack Underflow

STKOF

STKUF

Class B Hardware Traps:

Undefined Opcode

Protected Instruction

Fault

UNDOPC BTRAP

PRTFLT BTRAP

00’0028_H

0A_H

I

Illegal Word Operand

Access

ILLOPA

BTRAP

00’0028_H

0A_H

I

Illegal Instruction

Access

ILLINA

ILLBUS

BTRAP

00’0028_H

0A_H

I

Illegal External Bus

Access

Reserved

–

[2C_H–

3C_H]

[0B_H–

0F_H]

–

Software Traps

Any

Current

CPU

Priority

TRAP Instruction

[00’0000_H– [00_H–

00’01FC_H] 7F_H]

in steps

of 4_H

Data Sheet

23

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Capture/Compare (CAPCOM) Units

The CAPCOM units support generation and control of timing sequences on up to

32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically

used to handle high speed I/O tasks such as pulse and waveform generation, pulse

width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time

recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time

bases for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal

system clock, or may be derived from an overflow/underflow of timer T6 in module

GPT2. This provides a wide range of variation for the timer period and resolution and

allows precise adjustments to the application specific requirements. In addition, external

count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/

compare registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/

compare registers, each of which may be individually allocated to either CAPCOM timer

T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.

Eight registers of each module have one port pin associated with it which serves as an

input pin for triggering the capture function, or as an output pin to indicate the occurrence

of a compare event.

When a capture/compare register has been selected for capture mode, the current

contents of the allocated timer will be latched (‘captured’) into the capture/compare

register in response to an external event at the port pin which is associated with this

register. In addition, a specific interrupt request for this capture/compare register is

generated. Either a positive, a negative, or both a positive and a negative external signal

transition at the pin can be selected as the triggering event.

The contents of all registers which have been selected for one of the five compare

modes are continuously compared with the contents of the allocated timers.

Table 5

Compare Modes (CAPCOM)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1

Mode 2

Mode 3

Pin toggles on each compare match;

several compare events per timer period are possible

Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Data Sheet

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V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

When a match occurs between the timer value and the value in a capture/compare

register, specific actions will be taken based on the selected compare mode.

Reload Reg. TxREL

f_CPU

TxIN

2ⁿ: 1

Tx

Input

Control

Interrupt

Request

CAPCOM Timer Tx

GPT2 Timer T6

Over/Underflow

CCxIO

Mode

Control

(Capture

or

16-Bit

8 Capture Inputs

8 Compare Outputs

Capture/

Compare

Registers

16 Capture/Compare

Interrupt Request

Compare)

CCxIO

f_CPU

2ⁿ: 1

Ty

Interrupt

Request

Input

Control

CAPCOM Timer Ty

Reload Reg. TyREL

GPT2 Timer T6

Over/Underflow

x = 0, 7

y = 1, 8

n = 3 … 10

MCB02143c

Figure 5

CAPCOM Unit Block Diagram

Data Sheet

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V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which

may be used for many different time related tasks such as event timing and counting,

pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate

modules, GPT1 and GPT2. Each timer in each module may operate independently in a

number of different modes, or may be concatenated with another timer of the same

module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for

one of four basic modes of operation, which are Timer, Gated Timer, Counter, and

Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from

the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer

to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the

operation of a timer is controlled by the ‘gate’ level on an external input pin. For these

purposes, each timer has one associated port pin (TxIN) which serves as gate or clock

input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD) to

facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected

to the incremental position sensor signals A and B via their respective inputs TxIN and

TxEUD. Direction and count signals are internally derived from these two input signals,

so the contents of the respective timer Tx corresponds to the sensor position. The third

position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-

flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out

monitoring of external hardware components, or may be used internally to clock timers

T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload

or capture registers for timer T3. When used as capture or reload registers, timers T2

and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a

signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2

or T4 triggered either by an external signal or by a selectable state transition of its toggle

latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite

state transitions of T3OTL with the low and high times of a PWM signal, this signal can

be constantly generated without software intervention.

Data Sheet

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C161CS/JC/JI-L

T2EUD

f_CPU

T2IN

U/D

Interrupt

Request

(T2IR)

2ⁿ: 1

GPT1 Timer T2

T2

Mode

Control

Reload

Capture

Interrupt

Request

(T3IR)

f_CPU

2ⁿ: 1

Toggle FF

T3OTL

T3

Mode

Control

T3IN

GPT1 Timer T3

T3OUT

U/D

T3EUD

Capture

Reload

T4IN

T4

Mode

Control

Interrupt

Request

(T4IR)

2ⁿ: 1

GPT1 Timer T4

U/D

f_CPU

T4EUD

MCT04825

n = 3 … 10

Figure 6

Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control

and time measurement. It includes two timers (T5, T6) and a capture/reload register

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU

clock via a programmable prescaler or with external signals. The count direction (up/

down) for each timer is programmable by software or may additionally be altered

dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is

supported via the output toggle latch (T6OTL) of timer T6, which changes its state on

each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin

T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the

CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The

CAPREL register may capture the contents of timer T5 based on an external signal

transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared

Data Sheet

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C161CS/JC/JI-L

after the capture procedure. This allows the C161CS/JC/JI to measure absolute time

differences or to perform pulse multiplication without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of

GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3

operates in Incremental Interface Mode.

f_CPU

T5IN

2ⁿ: 1

T5

Mode

Control

U/D

Interrupt

Request

(T5IR)

GPT2 Timer T5

Clear

Capture

Interrupt

Request

(CRIR)

T3

MUX

CT3

CAPIN

GPT2 CAPREL

Interrupt

Request

(T6IR)

GPT2 Timer T6

U/D

T6OTL

T6OUT

T6IN

To auxiliary

Timers

T6

Mode

f_CPU

2ⁿ: 1

Control

To other

Modules

mcb03999b.vsd

n = 2 … 9

Figure 7

Block Diagram of GPT2

Data Sheet

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Real Time Clock

The Real Time Clock (RTC) module of the C161CS/JC/JI consists of a chain of 3 divider

blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer

(accessible via registers RTCH and RTCL). The RTC module is directly clocked via a

separate clock driver with the on-chip main oscillator frequency divided by 32

(f_RTC= f_OSCm/ 32) or with the on-chip auxiliary oscillator frequency (f_RTC= f_OSCa). It is

therefore independent from the selected clock generation mode of the C161CS/JC/JI.

All timers count up.

The RTC module can be used for different purposes:

• System clock to determine the current time and date

• Cyclic time based interrupt

• 48-bit timer for long term measurements

T14REL

Reload

f_RTC

T14

8:1

Interrupt

Request

RTCH

RTCL

MCD04432

Figure 8

RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

Data Sheet

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A/D Converter

For analog signal measurement, a 10-bit A/D converter with 12 multiplexed input

channels and a sample and hold circuit has been integrated on-chip. It uses the method

of successive approximation. The sample time (for loading the capacitors) and the

conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register

(ADDAT): either an interrupt request will be generated when the result of a previous

conversion has not been read from the result register at the time the next conversion is

complete, or the next conversion is suspended in such a case until the previous result

has been read.

For applications which require less than 12 analog input channels, the remaining

channel inputs can be used as digital input port pins.

The A/D converter of the C161CS/JC/JI supports four different conversion modes. In the

standard Single Channel conversion mode, the analog level on a specified channel is

sampled once and converted to a digital result. In the Single Channel Continuous mode,

the analog level on a specified channel is repeatedly sampled and converted without

software intervention. In the Auto Scan mode, the analog levels on a prespecified

number of channels (standard or extension) are sequentially sampled and converted. In

the Auto Scan Continuous mode, the number of prespecified channels is repeatedly

sampled and converted. In addition, the conversion of a specific channel can be inserted

(injected) into a running sequence without disturbing this sequence. This is called

Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the

conversion results into a table in memory for later evaluation, without requiring the

overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs

calibration cycles. This automatic self-calibration constantly adjusts the converter to

changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal

operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise

those pins used for analog input can be disconnected from the digital IO or input stages

under software control. This can be selected for each pin separately via register

P5DIDIS (Port 5 Digital Input Disable).

Data Sheet

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Serial Channels

Serial communication with other microcontrollers, processors, terminals or external

peripheral components is provided by three serial interfaces with different functionality,

two Asynchronous/Synchronous Serial Channels (ASC0/ASC1) and a High-Speed

Synchronous Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller

families and supports full-duplex asynchronous communication at up to 781 kBaud and

half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock).

A dedicated baud rate generator allows to set up all standard baud rates without

oscillator tuning. For transmission, reception and error handling 4 separate interrupt

vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or

received, preceded by a start bit and terminated by one or two stop bits. For

multiprocessor communication, a mechanism to distinguish address from data bytes has

been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a

shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop

back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated, if the last

character received has not been read out of the receive buffer register at the time the

reception of a new character is complete.

The ASC1 is function compatible with the ASC0, except that its registers are not bit-

addressable (XBUS peripheral) and it provides only three interrupt vectors.

The SSC supports full-duplex synchronous communication at up to 6.25 MBaud

(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked

peripheral components. A dedicated baud rate generator allows to set up all standard

baud rates without oscillator tuning. For transmission, reception and error handling three

separate interrupt vectors are provided.

The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift

clock which can be generated by the SSC (master mode) or by an external master (slave

mode). The SSC can start shifting with the LSB or with the MSB and allows the selection

of shifting and latching clock edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. Transmit and receive error supervise the correct handling

of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet

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Serial Data Link Module (SDLM)

The Serial Data Link Module (SDLM) provides serial communication via a J1850 type

multiplexed serial bus via an external J1850 bus transceiver. The module conforms to

the SAE Class B J1850 specification for variable pulse width modulation (VPW). The

SDLM is integrated as an on-chip peripheral and is connected to the CPU via the XBUS.

General SDLM Features:

• Compliant to the SAE Class B J1850 specification (VPW)

• Class 2 protocol fully supported

• Variable Pulse Width (VPW) operation at 10.4 kBaud

• High Speed 4X operation at 41.6 kBaud

• Programmable Normalization Bit

• Programmable Delay for transceiver interface

• Digital Noise Filter

• Power Down mode with automatic wakeup support upon bus activity

• Single Byte Header and Consolidated Header supported

• CRC generation and checking

• Receive and transmit Block Mode

Data Link Operation Features:

• 11 Byte Transmit Buffer

• Double buffered 11 Byte receive buffer (optional overwrite enable)

• Support for In Frame Response (IFR) types 1, 2 and 3

• Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode

• Advanced Interrupt Handling with 8 separately enabled sources:

Error, format or bus shorted

CRC error

Lost Arbitration

Break received

In-Frame-Response request

Header received

Complete message received

Transmit successful

• Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers

• User configurable clock divider

• Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress)

Note: When the SDLM is used with the interface lines assigned to Port 4, the interface

lines override the segment address lines and the segment address output on

Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines

can be used to increase the total amount of addressable external memory.

Data Sheet

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CAN-Modules

The integrated CAN-Modules handle the completely autonomous transmission and

reception of CAN frames in accordance with the CAN specification V2.0 part B (active),

i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit

identifiers as well as extended frames with 29-bit identifiers.

The modules provide Full CAN functionality on up to 15 message objects each.

Message object 15 may be configured for Basic CAN functionality. Both modes provide

separate masks for acceptance filtering which allows to accept a number of identifiers in

Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode.

All message objects can be updated independent from the other objects and are

equipped for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of

1 MBaud. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external

bus transceiver. The interface pins are assigned via software.

Module CAN2 (C161CS only) is identical with the first one, except that it uses a separate

address area and a separate interrupt node.

The two CAN modules can be internally coupled by assigning their interface pins to the

same two port pins, or they can interface to separate CAN buses.

Note: When one or both of the on-chip CAN Modules are used with the interface lines

assigned to Port 4, the interface lines override the segment address lines and the

segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines

A21/A19 … A16. CS lines can be used to increase the total amount of addressable

external memory.

IIC Module

The integrated IIC Bus Module handles the transmission and reception of frames over

the two-line IIC bus in accordance with the IIC Bus specification. The on-chip IIC Module

can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave

mode, in master mode or in multi-master mode.

Several physical interfaces (port pins) can be established under software control. Data

can be transferred at speeds up to 400 kbit/sec.

Two interrupt nodes dedicated to the IIC module allow efficient interrupt service and also

support operation via PEC transfers.

Note: The port pins associated with the IIC interfaces feature open drain drivers only, as

required by the IIC specification.

Data Sheet

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Parallel Ports

The C161CS/JC/JI provides up to 93 I/O lines which are organized into eight input/output

ports and one input port. All port lines are bit-addressable, and all input/output lines are

individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O

ports are true bidirectional ports which are switched to high impedance state when

configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)

for push/pull operation or open-drain operation via control registers, Port 9 provides

open-drain-only drivers. During the internal reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 4, Port 6, and Port 7 is selectable (TTL or

CMOS like), where the special CMOS like input threshold reduces noise sensitivity due

to the input hysteresis. The input threshold may be selected individually for each byte of

the respective ports.

All port lines have programmable alternate input or output functions associated with

them. All port lines that are not used for these alternate functions may be used as

general purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external

memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in

systems where segmentation is enabled to access more than 64 KBytes of memory.

Port 2, Port 7, and parts of PORT1 are associated with the capture inputs or compare

outputs of the CAPCOM units.

Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select

signals.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control

signal BHE, and the system clock output CLKOUT (or the programmable frequency

output FOUT).

Port 5 is used for the analog input channels to the A/D converter or timer control signals.

The edge characteristics (transition time) and driver characteristics (output current) of

the C161CS/JC/JI’s port drivers can be selected via the Port Output Control registers

(POCONx).

Data Sheet

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Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be

disabled in the time interval until the EINIT (end of initialization) instruction has been

executed. Thus, the chip’s start-up procedure is always monitored. The software has to

be designed to service the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/

256. The high byte of the Watchdog Timer register can be set to a prespecified reload

value (stored in WDTREL) in order to allow further variation of the monitored time

interval. Each time it is serviced by the application software, the high byte of the

Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 671 ms can be

monitored (@ 25 MHz).

The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).

Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip

oscillator (either with a crystal or via external clock drive). For this operation the PLL

provides a clock signal which is used to supervise transitions on the oscillator clock. This

PLL clock is independent from the XTAL1 clock. When the expected oscillator clock

transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and

supplies the CPU with the PLL clock signal. Under these circumstances the PLL will

oscillate with its basic frequency.

In direct drive mode the PLL base frequency is used directly (f_CPU= 2 … 5 MHz).

In prescaler mode the PLL base frequency is divided by 2 (f_CPU= 1 … 2.5 MHz).

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.

In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the

CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also

no interrupt request will be generated in case of a missing oscillator clock.

Note: At the end of an external reset (EA = ‘0’) bit OWDDIS reflects the inverted level of

pin RD at that time. Thus the oscillator watchdog may also be disabled via

hardware by (externally) pulling the RD line low upon a reset, similar to the

standard reset configuration via PORT0. At the end of an internal reset (EA = ‘1’)

bit OWDDIS is cleared.

Data Sheet

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Power Management

The C161CS/JC/JI provides several means to control the power it consumes either at a

given time or averaged over a certain timespan. Three mechanisms can be used (partly

in parallel):

• Power Saving Modes switch the C161CS/JC/JI into a special operating mode

(control via instructions).

Idle Mode stops the CPU while the peripherals can continue to operate.

Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may

optionally continue running). Sleep Mode can be terminated by external interrupt

signals.

• Clock Generation Management controls the distribution and the frequency of

internal and external clock signals (control via register SYSCON2).

Slow Down Mode lets the C161CS/JC/JI run at a CPU clock frequency of f_OSC

/

1 … 32 (half for prescaler operation) which drastically reduces the consumed power.

The PLL can be optionally disabled while operating in Slow Down Mode.

External circuitry can be controlled via the programmable frequency output FOUT.

• Peripheral Management permits temporary disabling of peripheral modules (control

via register SYSCON3).

Each peripheral can separately be disabled/enabled. A group control option disables

a major part of the peripheral set by setting one single bit.

The on-chip RTC supports intermittend operation of the C161CS/JC/JI by generating

cyclic wakeup signals. This offers full performance to quickly react on action requests

while the intermittend sleep phases greatly reduce the average power consumption of

the system.

Data Sheet

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Instruction Set Summary

Table 6 lists the instructions of the C161CS/JC/JI in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation

of the instructions, parameters for conditional execution of instructions, and the opcodes

for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailled description of each instruction.

Table 6

Mnemonic

ADD(B)

ADDC(B)

SUB(B)

SUBC(B)

MUL(U)

DIV(U)

Instruction Set Summary

Description

Bytes

2 / 4

Add word (byte) operands

Add word (byte) operands with Carry

Subtract word (byte) operands

Subtract word (byte) operands with Carry

(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

DIVL(U)

CPL(B)

NEG(B)

AND(B)

OR(B)

Complement direct word (byte) GPR

Negate direct word (byte) GPR

Bitwise AND, (word/byte operands)

Bitwise OR, (word/byte operands)

Bitwise XOR, (word/byte operands)

Clear direct bit

2

2 / 4

2

XOR(B)

BCLR

BSET

Set direct bit

2

BMOV(N)

Move (negated) direct bit to direct bit

AND/OR/XOR direct bit with direct bit

4

BAND, BOR,

BXOR

4

BCMP

Compare direct bit to direct bit

4

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

Compare word (byte) operands

2 / 4

Compare word data to GPR and decrement GPR by 1/2 2 / 4

Compare word data to GPR and increment GPR by 1/2

2 / 4

2

Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR

SHL / SHR

ROL / ROR

ASHR

Shift left/right direct word GPR

2

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

Data Sheet

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Table 6

Instruction Set Summary (cont’d)

Description

Mnemonic

MOV(B)

MOVBS

MOVBZ

Bytes

Move word (byte) data

2 / 4

Move byte operand to word operand with sign extension 2 / 4

Move byte operand to word operand. with zero extension 2 / 4

JMPA, JMPI,

JMPR

Jump absolute/indirect/relative if condition is met

4

JMPS

J(N)B

JBC

Jump absolute to a code segment

4

Jump relative if direct bit is (not) set

Jump relative and clear bit if direct bit is set

Jump relative and set bit if direct bit is not set

JNBS

CALLA, CALLI,

CALLR

Call absolute/indirect/relative subroutine if condition is met 4

CALLS

PCALL

Call absolute subroutine in any code segment

4

Push direct word register onto system stack and call

absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

Push/pop direct word register onto/from system stack

2

4

PUSH, POP

SCXT

Push direct word register onto system stack and update

register with word operand

RET

Return from intra-segment subroutine

Return from inter-segment subroutine

2

RETS

RETP

Return from intra-segment subroutine and pop direct

word register from system stack

RETI

Return from interrupt service subroutine

Software Reset

2

SRST

4

IDLE

Enter Idle Mode

4

PWRDN

SRVWDT

DISWDT

EINIT

Enter Power Down Mode (supposes NMI-pin being low)

Service Watchdog Timer

4

Disable Watchdog Timer

4

Signify End-of-Initialization on RSTOUT-pin

Begin ATOMIC sequence

4

ATOMIC

EXTR

2

Begin EXTended Register sequence

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

Null operation

2

EXTP(R)

EXTS(R)

NOP

2 / 4

2

Data Sheet

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Special Function Registers Overview

Table 7 lists all SFRs which are implemented in the C161CS/JC/JI in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the

Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column

“Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected

addressing mode, an SFR can be accessed via its physical address (using the Data

Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Note: Registers within device specific interface modules (CAN, SDLM) are only present

in the corresponding device, of course.

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

ADCIC

b FF98_H

CC_HA/D Converter End of Conversion

Interrupt Control Register

0000_H

ADCON

b FFA0_H

D0_H

50_H

A/D Converter Control Register

A/D Converter Result Register

A/D Converter 2 Result Register

Address Select Register 1

Address Select Register 2

Address Select Register 3

Address Select Register 4

0000_H

ADDAT

FEA0_H

ADDAT2

F0A0_HE 50_H

ADDRSEL1

ADDRSEL2

ADDRSEL3

ADDRSEL4

ADEIC

FE18_H

FE1A_H

0C_H

0D_H

0E_H

0F_H

FE1C_H

FE1E_H

b FF9A_H

CD_HA/D Converter Overrun Error Interrupt

Control Register

BUFFCON

BUFFSTAT

EB24_HX ---

EB1C_HX ---

SDLM Buffer Control Register

SDLM Buffer Status Register

Bus Configuration Register 0

Bus Configuration Register 1

Bus Configuration Register 2

Bus Configuration Register 3

Bus Configuration Register 4

SDLM Bus Status Register

CAN1 Bit Timing Register

0000_H

UUUU_H

XX01_H

UFUU_H

BUSCON0 b FF0C_H

BUSCON1 b FF14_H

BUSCON2 b FF16_H

BUSCON3 b FF18_H

BUSCON4 b FF1A_H

86_H

8A_H

8B_H

8C_H

8D_H

BUSSTAT

C1BTR

EB20_HX ---

EF04_HX ---

C1CSR

EF00_HX ---

EF06_HX ---

CAN1 Control / Status Register

CAN1 Global Mask Short

C1GMS

Data Sheet

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Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Address Addr.

Reset

Value

C1PCIR

C1LARn

C1LGML

C1LMLM

C1MCFGn

C1MCRn

C1UARn

C1UGML

C1UMLM

C2BTR

C2CSR

C2GMS

C2PCIR

C2LARn

C2LGML

C2LMLM

C2MCFGn

C2MCRn

C2UARn

C2UGML

C2UMLM

CAPREL

CC0

EF02_HX ---

EFn4_HX ---

EF0A_HX ---

EF0E_HX ---

EFn6_HX ---

EFn0_HX ---

EFn2_HX ---

EF08_HX ---

EF0C_HX ---

EE04_HX ---

EE00_HX ---

EE06_HX ---

EE02_HX ---

EEn4_HX ---

EE0A_HX ---

EE0E_HX ---

EEn6_HX ---

EEn0_HX ---

EEn2_HX ---

EE08_HX ---

EE0C_HX ---

CAN1 Port Control / Interrupt Register

CAN1 Lower Arbitration Reg. (msg. n)

CAN1 Lower Global Mask Long

CAN1 Lower Mask of Last Message

CAN1 Message Config. Reg. (msg. n)

CAN1 Message Control Reg. (msg. n)

CAN1 Upper Arbitration Reg. (msg. n)

CAN1 Upper Global Mask Long

CAN1 Upper Mask of Last Message

CAN2 Bit Timing Register

XXXX_H

UUUU_H

UU_H

UUUU_H

XX01_H

UFUU_H

XXXX_H

UUUU_H

UU_H

CAN2 Control / Status Register

CAN2 Global Mask Short

CAN2 Port Control / Interrupt Register

CAN2 Lower Arbitration Reg. (msg. n)

CAN2 Lower Global Mask Long

CAN2 Lower Mask of Last Message

CAN2 Message Config. Reg. (msg. n)

CAN2 Message Control Reg. (msg. n)

CAN2 Upper Arbitration Reg. (msg. n)

CAN2 Upper Global Mask Long

CAN2 Upper Mask of Last Message

GPT2 Capture/Reload Register

CAPCOM Register 0

UUUU_H

0000_H

FE4A_H

FE80_H

25_H

40_H

0000_H

CC0IC

b FF78_H

FE82_H

BC_HCAPCOM Register 0 Interrupt Ctrl. Reg.

0000_H

CC1

41_H

4A_H

C6_H

4B_H

C7_H

4C_H

C8_H

4D_H

CAPCOM Register 1

0000_H

CC10

FE94_H

CAPCOM Register 10

0000_H

CC10IC

CC11

b FF8C_H

FE96_H

CAPCOM Reg. 10 Interrupt Ctrl. Reg.

CAPCOM Register 11

0000_H

CC11IC

CC12

b FF8E_H

FE98_H

CAPCOM Reg. 11 Interrupt Ctrl. Reg.

CAPCOM Register 12

0000_H

CC12IC

CC13

b FF90_H

FE9A_H

CAPCOM Reg. 12 Interrupt Ctrl. Reg.

CAPCOM Register 13

0000_H

Data Sheet

40

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

CC13IC

CC14

b FF92_H

C9_H

CAPCOM Reg. 13 Interrupt Ctrl. Reg.

CAPCOM Register 14

0000_H

FE9C_H

b FF94_H

FE9E_H

4E_H

CC14IC

CC15

CA_HCAPCOM Reg. 14 Interrupt Ctrl. Reg.

4F_HCAPCOM Register 15

CB_HCAPCOM Reg. 15 Interrupt Ctrl. Reg.

CC15IC

CC16

b FF96_H

FE60_H

30_H

CAPCOM Register 16

CC16IC

CC17

b F160_HE B0_H

FE62_H31_H

b F162_HE B1_H

FE64_H32_H

b F164_HE B2_H

FE66_H33_H

b F166_HE B3_H

CAPCOM Reg.16 Interrupt Ctrl. Reg.

CAPCOM Register 17

CC17IC

CC18

CAPCOM Reg. 17 Interrupt Ctrl. Reg.

CAPCOM Register 18

CC18IC

CC19

CAPCOM Reg. 18 Interrupt Ctrl. Reg.

CAPCOM Register 19

CC19IC

CC1IC

CC2

CAPCOM Reg. 19 Interrupt Ctrl. Reg.

b FF7A_H

FE84_H

BD_HCAPCOM Reg. 1 Interrupt Ctrl. Reg.

42_H

34_H

CAPCOM Register 2

CC20

FE68_H

CAPCOM Register 20

CC20IC

CC21

b F168_HE B4_H

FE6A_H35_H

b F16A_HE B5_H

FE6C_H36_H

b F16C_HE B6_H

FE6E_H37_H

b F16E_HE B7_H

FE70_H38_H

b F170_HE B8_H

FE72_H39_H

b F172_HE B9_H

FE74_H3A_H

b F174_HE BA_H

FE76_H3B_H

b F176_HE BB_H

FE78_H3C_H

CAPCOM Reg. 20 Interrupt Ctrl. Reg.

CAPCOM Register 21

CC21IC

CC22

CAPCOM Reg. 21 Interrupt Ctrl. Reg.

CAPCOM Register 22

CC22IC

CC23

CAPCOM Reg. 22 Interrupt Ctrl. Reg.

CAPCOM Register 23

CC23IC

CC24

CAPCOM Reg. 23 Interrupt Ctrl. Reg.

CAPCOM Register 24

CC24IC

CC25

CAPCOM Reg. 24 Interrupt Ctrl. Reg.

CAPCOM Register 25

CC25IC

CC26

CAPCOM Reg. 25 Interrupt Ctrl. Reg.

CAPCOM Register 26

CC26IC

CC27

CAPCOM Reg. 26 Interrupt Ctrl. Reg.

CAPCOM Register 27

CC27IC

CC28

CAPCOM Reg. 27 Interrupt Ctrl. Reg.

CAPCOM Register 28

Data Sheet

41

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Address Addr.

b F178_HE BC_HCAPCOM Reg. 28 Interrupt Ctrl. Reg.

Reset

Value

CC28IC

CC29

CC29IC

CC2IC

CC3

0000_H

FC00_H

FE7A_H

3D_H

CAPCOM Register 29

b F184_HE C2_H

CAPCOM Reg. 29 Interrupt Ctrl. Reg.

CAPCOM Reg. 2 Interrupt Ctrl. Reg.

CAPCOM Register 3

b FF7C_H

FE86_H

BE_H

43_H

3E_H

CC30

CC30IC

CC31

CC31IC

CC3IC

CC4

FE7C_H

CAPCOM Register 30

b F18C_HE C6_H

FE7E_H3F_H

CAPCOM Reg. 30 Interrupt Ctrl. Reg.

CAPCOM Register 31

b F194_HE CA_HCAPCOM Reg. 31 Interrupt Ctrl. Reg.

b FF7E_H

FE88_H

BF_H

44_H

C0_H

45_H

C1_H

46_H

C2_H

47_H

C3_H

48_H

C4_H

49_H

C5_H

A9_H

AA_H

AB_H

CAPCOM Reg. 3 Interrupt Ctrl. Reg.

CAPCOM Register 4

CC4IC

CC5

b FF80_H

FE8A_H

CAPCOM Reg. 4 Interrupt Ctrl. Reg.

CAPCOM Register 5

CC5IC

CC6

b FF82_H

FE8C_H

CAPCOM Reg. 5 Interrupt Ctrl. Reg.

CAPCOM Register 6

CC6IC

CC7

b FF84_H

FE8E_H

CAPCOM Reg. 6 Interrupt Ctrl. Reg.

CAPCOM Register 7

CC7IC

CC8

b FF86_H

FE90_H

CAPCOM Reg. 7 Interrupt Ctrl. Reg.

CAPCOM Register 8

CC8IC

CC9

b FF88_H

FE92_H

CAPCOM Reg. 8 Interrupt Ctrl. Reg.

CAPCOM Register 9

CC9IC

CCM0

CCM1

CCM2

CCM3

CCM4

CCM5

CCM6

CCM7

CLKDIV

CP

b FF8A_H

b FF52_H

b FF54_H

b FF56_H

b FF58_H

b FF22_H

b FF24_H

b FF26_H

b FF28_H

CAPCOM Reg. 9 Interrupt Ctrl. Reg.

CAPCOM Mode Control Register 0

CAPCOM Mode Control Register 1

CAPCOM Mode Control Register 2

AC_HCAPCOM Mode Control Register 3

91_H

92_H

93_H

94_H

CAPCOM Mode Control Register 4

CAPCOM Mode Control Register 5

CAPCOM Mode Control Register 6

CAPCOM Mode Control Register 7

SDLM Clock Divider Register

EB14_HX ---

FE10_H

08_H

CPU Context Pointer Register

Data Sheet

42

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

b FF6A_H

FE08_H

Addr.

CRIC

CSP

B5_H

GPT2 CAPREL Interrupt Ctrl. Reg.

0000_H

04_H

CPU Code Segment Pointer Register

(8 bits, not directly writeable)

DP0H

DP0L

DP1H

DP1L

DP2

b F102_HE 81_H

b F100_HE 80_H

b F106_HE 83_H

b F104_HE 82_H

P0H Direction Control Register

P0L Direction Control Register

P1H Direction Control Register

P1L Direction Control Register

Port 2 Direction Control Register

Port 3 Direction Control Register

Port 4 Direction Control Register

Port 6 Direction Control Register

Port 7 Direction Control Register

00_H

b FFC2_H

b FFC6_H

b FFCA_H

b FFCE_H

b FFD2_H

b FFDA_H

FE00_H

E1_H

E3_H

E5_H

E7_H

E9_H

0000_H

00_H

DP3

DP4

DP6

00_H

DP7

00_H

DP9

ED_HPort 9 Direction Control Register

00_H

DPP0

DPP1

DPP2

DPP3

ERRSTAT

EXICON

EXISEL

00_H

01_H

02_H

03_H

CPU Data Page Pointer 0 Reg. (10 bits)

CPU Data Page Pointer 1 Reg. (10 bits)

CPU Data Page Pointer 2 Reg. (10 bits)

CPU Data Page Pointer 3 Reg. (10 bits)

SDLM Error Status Register

0000_H

0001_H

0002_H

0003_H

0000_H

FE02_H

FE04_H

FE06_H

EB22_HX ---

b F1C0_HE E0_H

External Interrupt Control Register

b F1DA_HE ED_HExternal Interrupt Source Select

Register

FLAGRST

FOCON

GLOBCON

ICADR

EB28_HX ---

b FFAA_HD5_H

SDLM Flag Reset Register

Frequency Output Control Register

SDLM Global Control Register

IIC Address Register

IIC Configuration Register

IIC Control Register

IIC Receive/Transmit Buffer

IIC Status Register

0000_H

0XXX_H

XX00_H

0000_H

XX_H

EB10_HX ---

ED06_HX ---

ED00_HX ---

ED02_HX ---

ED08_HX ---

ED04_HX ---

F07C_HE 3E_H

F07E_HE 3F_H

F07A_HE 3D_H

ICCFG

ICCON

ICRTB

ICST

0000_H

1XXX_H

1820_H

X040_H

IDCHIP

IDMANUF

IDMEM

Identifier

Data Sheet

43

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Address Addr.

Reset

Value

IDPROG

IFR

F078_HE 3C_H

EB18_HX ---

EB2C_HX ---

EB04_HX ---

F1DE_HE EF_H

Identifier

XXXX_H

0000_H

0007_H

0000_H

00_H

SDLM In-Frame Response Register

SDLM Interrupt Control Register

SDLM Interface Port Connect Register

Interrupt Subnode Control Register

CPU Multiply Divide Control Register

CPU Multiply Divide Reg. – High Word

CPU Multiply Divide Reg. – Low Word

Port 2 Open Drain Control Register

Port 3 Open Drain Control Register

Port 4 Open Drain Control Register

Port 6 Open Drain Control Register

Port 7 Open Drain Control Register

Constant Value 1’s Register (read only)

Port 0 High Reg. (Upper half of PORT0)

Port 0 Low Reg. (Lower half of PORT0)

Port 1 High Reg. (Upper half of PORT1)

Port 1 Low Reg. (Lower half of PORT1)

Port 2 Register

INTCON

IPCR

ISNC

MDC

MDH

MDL

b FF0E_H

87_H

06_H

07_H

FE0C_H

FE0E_H

ODP2

ODP3

ODP4

ODP6

ODP7

ONES

P0H

b F1C2_HE E1_H

b F1C6_HE E3_H

b F1CA_HE E5_H

b F1CE_HE E7_H

b F1D2_HE E9_H

00_H

b FF1E_H

b FF02_H

b FF00_H

b FF06_H

b FF04_H

b FFC0_H

b FFC4_H

b FFC8_H

b FFA2_H

b FFCC_H

b FFD0_H

b FFD8_H

FEC0_H

8F_H

81_H

80_H

83_H

82_H

E0_H

E2_H

E4_H

D1_H

E6_H

E8_H

FFFF_H

00_H

P0L

00_H

P1H

00_H

P1L

00_H

P2

0000_H

00_H

P3

Port 3 Register

P4

Port 4 Register (7 bits)

P5

Port 5 Register (read only)

XXXX_H

00_H

P6

Port 6 Register (8 bits)

P7

Port 7 Register (8 bits)

00_H

P9

EC_HPort 9 Register (8 bits)

00_H

PECC0

PECC1

PECC2

PECC3

PECC4

PECC5

PECC6

60_H

61_H

62_H

63_H

64_H

65_H

66_H

PEC Channel 0 Control Register

0000_H

FEC2_H

PEC Channel 1 Control Register

PEC Channel 2 Control Register

PEC Channel 3 Control Register

PEC Channel 4 Control Register

PEC Channel 5 Control Register

PEC Channel 6 Control Register

FEC4_H

FEC6_H

FEC8_H

FECA_H

FECC_H

Data Sheet

44

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

PECC7

FECE_H

67_H

PEC Channel 7 Control Register

Port Input Threshold Control Register

P0L Output Control Register

P0H Output Control Register

P1L Output Control Register

P1H Output Control Register

Port 2 Output Control Register

Dedicated Pins Output Control Register

Port 3 Output Control Register

Port 4 Output Control Register

Port 6 Output Control Register

Port 7 Output Control Register

CPU Program Status Word

0000_H

XX_H

PICON

b F1C4_HE E2_H

F082_HE 41_H

F080_HE 40_H

F086_HE 43_H

F084_HE 42_H

F088_HE 44_H

F0AA_HE 55_H

F08A_HE 45_H

F08C_HE 46_H

F08E_HE 47_H

F090_HE 48_H

POCON0H

POCON0L

POCON1H

POCON1L

POCON2

POCON20

POCON3

POCON4

POCON6

POCON7

PSW

b FF10_H

88_H

RP0H

b F108_HE 84_H

System Startup Configuration Register

(Rd. only)

RSTCON b F1E0_Hm ---

Reset Control Register

00XX_H

no

RTCH

F0D6_HE 6B_H

F0D4_HE 6A_H

EB4C_HX ---

EB4A_HX ---

EB4E_HX ---

EB40_HX ---

EB4A_HX ---

EB42_HX ---

EB44_HX ---

EB46_HX ---

EB48_HX ---

EB50_HX ---

EB5A_HX ---

EB52_HX ---

EB54_HX ---

EB56_HX ---

RTC High Register

RTCL

RTC Low Register

no

RXCNT

RXCNTB

RXCPU

RXD00

RXD010

RXD02

RXD04

RXD06

RXD08

RXD10

RXD110

RXD12

RXD14

RXD16

SDLM Bus Receive Byte Counter (CPU)

SDLM Bus Receive Byte Counter (bus)

SDLM CPU Receive Byte Counter Reg.

SDLM Receive Data Register 00 (CPU)

SDLM Receive Data Register 010 (CPU)

SDLM Receive Data Register 02 (CPU)

SDLM Receive Data Register 04 (CPU)

SDLM Receive Data Register 06 (CPU)

SDLM Receive Data Register 08 (CPU)

SDLM Receive Data Register 10 (bus)

SDLM Receive Data Register 110 (bus)

SDLM Receive Data Register 12 (bus)

SDLM Receive Data Register 14 (bus)

SDLM Receive Data Register 16 (bus)

0000_H

Data Sheet

45

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Address Addr.

EB58_HX ---

Reset

Value

RXD18

S0BG

SDLM Receive Data Register 18 (bus)

0000_H

FEB4_H

5A_H

Serial Channel 0 Baud Rate Generator

Reload Register

S0CON

S0EIC

b FFB0_H

b FF70_H

D8_H

B8_H

Serial Channel 0 Control Register

0000_H

Serial Channel 0 Error Interrupt Ctrl.

Reg.

S0RBUF

S0RIC

FEB2_H

59_H

B7_H

Serial Channel 0 Receive Buffer

Register (read only)

XXXX_H

0000_H

b FF6E_H

Serial Channel 0 Receive Interrupt

Control Register

S0TBIC

S0TBUF

S0TIC

b F19C_HE CE_HSerial Channel 0 Transmit Buffer

Interrupt Control Register

FEB0_H

58_H

B6_H

Serial Channel 0 Transmit Buffer

Register

b FF6C_H

Serial Channel 0 Transmit Interrupt

Control Register

S1BG

EDA4_HX ---

Serial Channel 1 Baud Rate Generator

Reload Register

S1CON

EDA6_HX ---

EDA2_HX ---

Serial Channel 1 Control Register

0000_H

S1RBUF

Serial Channel 1 Receive Buffer

Register (read only)

XXXX_H

S1TBUF

EDA0_HX ---

Serial Channel 1 Transmit Buffer

Register

0000_H

SOFPTR

SP

EB60_HX ---

SDLM Start-of-Frame Pointer Register

CPU System Stack Pointer Register

SSC Baudrate Register

0000_H

FC00_H

0000_H

XXXX_H

0000_H

FA00_H

FC00_H

FE12_H

09_H

SSCBR

F0B4_HE 5A_H

SSCCON b FFB2_H

D9_H

BB_H

SSC Control Register

SSCEIC

SSCRB

SSCRIC

SSCTB

SSCTIC

STKOV

STKUN

b FF76_H

SSC Error Interrupt Control Register

SSC Receive Buffer (read only)

SSC Receive Interrupt Control Register

SSC Transmit Buffer (write only)

SSC Transmit Interrupt Control Register

CPU Stack Overflow Pointer Register

CPU Stack Underflow Pointer Register

F0B2_HE 59_H

b FF74_H

BA_H

F0B0_HE 58_H

b FF72_H

B9_H

0A_H

0B_H

FE14_H

FE16_H

Data Sheet

46

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

SYSCON b FF12_H

89_H

CPU System Configuration Register

CPU System Configuration Register 1

CPU System Configuration Register 2

CPU System Configuration Register 3

CAPCOM Timer 0 Register

¹⁾0XX0_H

0000_H

0X00_H

0000_H

no

SYSCON1 b F1DC_HE EE_H

SYSCON2 b F1D0_HE E8_H

SYSCON3 b F1D4_HE EA_H

T0

FE50_H

b FF50_H

b FF9C_H

FE54_H

28_H

A8_H

T01CON

T0IC

T0REL

T1

CAPCOM Timer 0 and Timer 1 Ctrl. Reg.

CE_HCAPCOM Timer 0 Interrupt Ctrl. Reg.

2A_H

29_H

CAPCOM Timer 0 Reload Register

CAPCOM Timer 1 Register

FE52_H

T14

F0D2_HE 69_H

F0D0_HE 68_H

RTC Timer 14 Register

T14REL

T1IC

T1REL

T2

RTC Timer 14 Reload Register

CAPCOM Timer 1 Interrupt Ctrl. Reg.

CAPCOM Timer 1 Reload Register

GPT1 Timer 2 Register

no

b FF9E_H

CF_H

2B_H

20_H

A0_H

B0_H

21_H

A1_H

B1_H

22_H

A2_H

B2_H

23_H

A3_H

B3_H

24_H

A4_H

B4_H

0000_H

FE56_H

FE40_H

T2CON

T2IC

T3

b FF40_H

b FF60_H

FE42_H

GPT1 Timer 2 Control Register

GPT1 Timer 2 Interrupt Control Register

GPT1 Timer 3 Register

T3CON

T3IC

T4

b FF42_H

b FF62_H

FE44_H

GPT1 Timer 3 Control Register

GPT1 Timer 3 Interrupt Control Register

GPT1 Timer 4 Register

T4CON

T4IC

T5

b FF44_H

b FF64_H

FE46_H

GPT1 Timer 4 Control Register

GPT1 Timer 4 Interrupt Control Register

GPT2 Timer 5 Register

T5CON

T5IC

T6

b FF46_H

b FF66_H

FE48_H

GPT2 Timer 5 Control Register

GPT2 Timer 5 Interrupt Control Register

GPT2 Timer 6 Register

T6CON

T6IC

T7

b FF48_H

b FF68_H

GPT2 Timer 6 Control Register

GPT2 Timer 6 Interrupt Control Register

CAPCOM Timer 7 Register

F050_HE 28_H

b FF20_H90_H

T78CON

T7IC

T7REL

CAPCOM Timer 7 and 8 Ctrl. Reg.

b F17A_HE BD_HCAPCOM Timer 7 Interrupt Ctrl. Reg.

F054_HE 2A_H

CAPCOM Timer 7 Reload Register

47

Data Sheet

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Table 7

Name

C161CS/JC/JI Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Address Addr.

Reset

Value

T8

F052_HE 29_H

b F17C_HE BE_H

F056_HE 2B_H

CAPCOM Timer 8 Register

0000_H

0014_H

0000_H

²⁾00XX_H

0000_H

T8IC

T8REL

TFR

CAPCOM Timer 8 Interrupt Ctrl. Reg.

CAPCOM Timer 8 Reload Register

Trap Flag Register

b FFAC_H

D6_H

TRANSSTAT EB1E_HX ---

SDLM Transmission Status Register

SDLM Bus Transmit Byte Counter Reg.

SDLM CPU Transmit Byte Counter Reg.

SDLM Transmit Data Register 0

SDLM Transmit Data Register 10

SDLM Transmit Data Register 2

SDLM Transmit Data Register 4

SDLM Transmit Data Register 6

SDLM Transmit Data Register 8

SDLM Transceiver Delay Register

Watchdog Timer Register (read only)

Watchdog Timer Control Register

IIC Data Interrupt Control Register

IIC Protocol Interrupt Control Register

TXCNT

TXCPU

TXD0

EB3C_HX ---

EB3E_HX ---

EB30_HX ---

EB3A_HX ---

EB32_HX ---

EB34_HX ---

EB36_HX ---

EB38_HX ---

EB16_HX ---

TXD10

TXD2

TXD4

TXD6

TXD8

TxDELAY

WDT

FEAE_H

57_H

D7_H

WDTCON b FFAE_H

XP0IC

XP1IC

XP2IC

XP3IC

XP4IC

XP5IC

XP6IC

XP7IC

ZEROS

1)

b F186_HE C3_H

b F18E_HE C7_H

b F196_HE CB_HCAN1 Interrupt Control Register

b F19E_HE CF_H

b F182_HE C1_H

b F18A_HE C5_H

b F192_HE C9_H

PLL/RTC Interrupt Control Register

ASC1 Transmit Interrupt Ctrl. Reg.

ASC1 Receive Interrupt Control Register

ASC1 Error Interrupt Control Register

b F19A_HE CD_HCAN2/SDLM Interrupt Control Register

b FF1C_H8E_HConstant Value 0’s Register (read only)

The system configuration is selected during reset.

2)

The reset value depends on the indicated reset source.

Data Sheet

48

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Absolute Maximum Ratings

Table 8

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

150

6.5

Storage temperature

T_ST

T_J

-65

-40

-0.5

°C

V

–

Junction temperature

under bias

–

Voltage on V_DDpins with

respect to ground (V_SS)

V_DD

Voltage on any pin with

respect to ground (V_SS)

V_IN

–

-0.5

-10

–

V

_DD+ 0.5 V

–

Input current on any pin

during overload condition

10

mA

Absolute sum of all input

currents during overload

condition

–

|100|

Power dissipation

P_DISS

–

1.5

W

–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN> V_DDor V_IN< V_SS) the

voltage on V_DDpins with respect to ground (V_SS) must not exceed the values

defined by the absolute maximum ratings.

Data Sheet

49

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the C161CS/JC/JI. All parameters specified in the following sections refer

to these operating conditions, unless otherwise noticed.

Table 9

Operating Condition Parameters

Parameter

Symbol

Limit Values

min. max.

4.5 5.5

Unit Notes

Digital supply voltage

V_DD

V

Active mode,

_CPUmax= 25 MHz

f

2.5¹⁾

5.5

V

PowerDown mode

Digital ground voltage

Overload current

V_SS

I_OV

0

Reference voltage

–

±5

mA Per pin²⁾³⁾⁴⁾

3)

Absolute sum of overload Σ|I_OV|

50

mA

currents

External Load

Capacitance

C_L

T_A

–

100

pF

Pin drivers in

fast edge mode⁵⁾

Ambient temperature

0

70

°C

SAB-C161CS/JC/JI …

SAF-C161CS/JC/JI …

SAK-C161CS/JC/JI …

-40

85

125

1)

Output voltages and output currents will be reduced when V_DDleaves the range defined for active mode.

2)

Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input overload

currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.

Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD, WR, etc.

3)

4)

Not 100% tested, guaranteed by design and characterization.

Due to the different port structure of Port 9 (required by the IIC bus specification) the pins of Port 9 can only

tolerate positive overload current, i.e. V_OV> V_SS- 0.5 V.

5)

The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current

in dynamic current mode must be respected when designing the system.

Data Sheet

50

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161CS/

JC/JI and partly its demands on the system. To aid in interpreting the parameters right,

when evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C161CS/JC/JI will provide signals with the respective timing

characteristics.

SR (System Requirement):

The external system must provide signals with the respective timing characteristics to

the C161CS/JC/JI.

DC Characteristics

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

max.

Input low voltage (TTL,

all except XTAL1, XTAL3, Port 9)

V_ILSR -0.5

V_IL2SR -0.5

V_ILSSR -0.5

0.2 V_DD

- 0.1

V

–

Input low voltage

XTAL1, XTAL3, Port 9

0.3 V_DD

Input low voltage

(Special Threshold)

2.0

Input high voltage (TTL, all

except RSTIN, XTAL1, XTAL3,

Port 9)

V_IHSR 0.2 V_DDV_DD

+ 0.9 0.5

+

Input high voltage RSTIN

(when operated as input)

V_IH1SR 0.6 V_DDV_DD

+

V

–

0.5

Input high voltage

XTAL1, XTAL3, Port 9

V_IH2SR 0.7 V_DDV_DD

0.5

Input high voltage

(Special Threshold)

V_IHSSR 0.8 V_DDV_DD

- 0.2

0.5

Input Hysteresis

HYS

400

–

mV Series resistance

(Special Threshold)

= 0 Ω

Output low voltage

V_OLCC –

0.45

0.4

V

I

_OL= 2.4 mA³⁾

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT, RSTIN²⁾)

_OL= 0.5 mA⁴⁾

Output low voltage

(Port 9)

V_OL9CC –

V

I_OL= 3.0 mA

Data Sheet

51

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

DC Characteristics (cont’d)

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

max.

Output low voltage

(all other outputs)

Output high voltage⁵⁾

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT)

V_OL1CC –

0.45

V

I

_OL= 1.6 mA³⁾

_OL= 1.6 mA⁴⁾

V_OHCC 2.4

–

I

_OH= -2.4 mA³⁾

_OH= -0.5 mA⁴⁾

0.9 V_DD

_OH1CC 2.4

–

V

I

_OH= -0.5 mA³⁾

Output high voltage⁵⁾

(all other outputs)

V

I

_OH= -1.6 mA³⁾

_OH= -0.5 mA⁴⁾

0.9 V_DD

I_OZ1CC –

–

V

I

_OH= -0.5 mA³⁾

Input leakage current (Port 5)

±200

±500

nA 0 V < V_IN< V_DD

Input leakage current (all other) I_OZ2CC –

nA 0.45 V < V_IN<

V_DD

7)

RSTIN inactive current⁶⁾

RSTIN active current⁶⁾

READY/RD/WR inact. current⁹⁾I_RWH

I_RSTH

–

-10

–

µA V_IN= V_IH1

µA V_IN= V_IL

8)

I_RSTL

-100

–

7)

-40

–

µA

V

_OUT= 2.4 V

8)

READY/RD/WR active current⁹⁾I_RWL

-500

–

_OUT= V_OLmax

_OUT= 2.4 V

7)

ALE inactive current⁹⁾

ALE active current⁹⁾

Port 6 inactive current⁹⁾

Port 6 active current⁹⁾

I_ALEL

40

–

8)

I_ALEH

500

–

7)

I_P6H

-40

–

_OUT= 2.4 V

8)

7)

I_P6L

-500

–

_OUT= V_OL1max

PORT0 configuration current¹⁰⁾I_P0H

-10

–

µA V_IN= V_IHmin

µA V_IN= V_ILmax

µA 0 V < V_IN< V_DD

8)

I_P0L

-100

XTAL1 input current

Pin capacitance¹¹⁾

I_ILCC –

C_IOCC –

±20

10

pF

f = 1 MHz

(digital inputs/outputs)

T_A= 25 °C

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current I_OV

.

2)

3)

4)

5)

Valid in bidirectional reset mode only.

This output current may be drawn from (output) pins operating in High Current mode.

This output current may be drawn from (output) pins operating in Low Current mode.

This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

Data Sheet

52

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

6)

7)

8)

9)

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins

are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The

READY-pullup is always active, except for Powerdown mode.

10)

11)

This specification is valid during Reset and during Adapt-mode.

Not 100% tested, guaranteed by design and characterization.

Power Consumption C161CS/JC/JI

(Operating Conditions apply)

Parameter

Symbol

Limit Values

min. max.

Unit Test Condition

Power supply current (active)

with all peripherals active

I_DD

–

15 +

2.5 × f_CPU

mA RSTIN = V_IL

f

_CPUin [MHz]¹⁾

Idle mode supply current

with all peripherals active

I_IDX

5 +

1.5 × f_CPU

mA RSTIN = V_IH1

_CPUin [MHz]¹⁾

µA RSTIN = V_IH1

_OSCin [MHz]¹⁾

f

2)

Idle mode supply curr., Main osc, I_IDOM

with all peripherals deactivated,

PLL off, SDD factor = 32

500 +

50 × f_OSC

f

2)

Idle mode supply curr., Aux. osc, I_IDOA

with all peripherals deactivated,

PLL off, SDD factor = 32

–

100

µA

V

f

_DD= V_DDmax

_OSC= 32 kHz³⁾

2)

Sleep and Power-down mode

supply current with RTC running

on main oscillator

I_PDRM

200 +

25 × f_OSC

V

_DD= V_DDmax

f

_OSCin [MHz]³⁾

3)

Sleep and Power-down mode

I_PDO

50

V_DD= V_DDmax

supply current with RTC disabled

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10.

These parameters are tested at V_DDmaxand maximum CPU clock with all outputs disconnected and all inputs

at V_ILor V_IH.

2)

3)

This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current,

however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical

circuitry and may change in case of a not optimized external oscillator circuitry.

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V_DD- 0.1 V to V_DD, all outputs (including pins configured as outputs) disconnected.

Data Sheet

53

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

I

µA

1500

1250

1000

750

500

250

0

I_IDOMmax

I_IDOMtyp

I_PDRMmax

I_PDOmax

I_IDOAmax

f_OSC

0

4

8

12

16 MHz

MCD04453

Figure 9

Idle and Power Down Supply Current as a Function of Oscillator

Frequency

Data Sheet

54

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

I [mA]

100

I_DD5max

80

60

40

20

I_DD5typ

I_IDX5max

I_IDX5typ

10

15

20

25

f

_CPU[MHz]

Figure 10

Supply/Idle Current as a Function of Operating Frequency

Data Sheet

55

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

AC Characteristics

Definition of Internal Timing

The internal operation of the C161CS/JC/JI is controlled by the internal CPU clock f_CPU

.

Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus

cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).

Phase Locked Loop Operation

f_OSC

TCL

f_CPU

TCL

Direct Clock Drive

f_OSC

TCL

f_CPU

TCL

Prescaler Operation

f_OSC

TCL

f_CPU

MCT04338

TCL

Figure 11

Generation Mechanisms for the CPU Clock

The CPU clock signal f_CPUcan be generated from the oscillator clock signal f_OSCvia

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate f_CPU. This influence must

be regarded when calculating the timings for the C161CS/JC/JI.

Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5.

Upon a long hardware reset register RP0H is loaded with the logic levels present on the

upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

Data Sheet

56

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register

RSTCON under software control.

Table 10 associates the combinations of these three bits with the respective clock

generation mode.

Table 10

C161CS/JC/JI Clock Generation Modes

CPU Frequency External Clock Notes

_CPU= f_OSC× F Input Range¹⁾

CLKCFG

(P0H.7-5)

f

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

f

_OSC× 4

2.5 to 6.25 MHz

3.33 to 8.33 MHz

5 to 12.5 MHz

2 to 5 MHz

Default configuration

_OSC× 3

_OSC× 2

_OSC× 5

_OSC× 1

_OSC× 1.5

_OSC/ 2

–

1 to 25 MHz

Direct drive²⁾

6.66 to 16.6 MHz

2 to 50 MHz

–

CPU clock via prescaler

–

0 0 0

_OSC× 2.5

4 to 10 MHz

1)

The external clock input range refers to a CPU clock range of 10 … 25 MHz.

2)

The maximum frequency depends on the duty cycle of the external clock signal.

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001_B) the CPU clock is derived from

the internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of f_CPUis half the frequency of f_OSCand the high and low time of f_CPU

(i.e. the duration of an individual TCL) is defined by the period of the input clock f_OSC

.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

calculated using the period of f_OSCfor any TCL.

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is

enabled and provides the CPU clock (see table above). The PLL multiplies the input

frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.

f

_CPU= f_OSC× F). With every F’th transition of f_OSCthe PLL circuit synchronizes the CPU

clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock

frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of f_CPUis constantly adjusted so

it is locked to f_OSC. The slight variation causes a jitter of f_CPUwhich also effects the

duration of individual TCLs.

Data Sheet

57

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

The timings listed in the AC Characteristics that refer to TCLs therefore must be

calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is

constantly adjusting its output frequency so it corresponds to the applied input frequency

(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than

for one single TCL (see formula and Figure 12).

For a period of N × TCL the minimum value is computed using the corresponding

deviation D :

N

(N × TCL)_min= N × TCL_NOM- D

D [ns] = ±(13.3 + N × 6.3) / f_CPU[MHz],

N

where N = number of consecutive TCLs and 1 ≤ N ≤ 40.

So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D = (13.3 + 3 × 6.3) / 25 = 1.288 ns,

3

and (3TCL)_min= 3TCL_NOM- 1.288 ns = 58.7 ns (@ f_CPU= 25 MHz).

This is especially important for bus cycles using waitstates and e.g. for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse

train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL

jitter is neglectible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12).

Max. jitter D_N

ns

This approximated formula is valid for

±30

<

25 MHz.

CPU

1

N

40 and 10 MHz

f

–

10 MHz

16 MHz

±26.5

±20

20 MHz

25 MHz

±10

±1

N

1

10

20

30

40

MCD04455

Figure 12

Approximated Maximum Accumulated PLL Jitter

Data Sheet

58

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Direct Drive

When direct drive is configured (CLKCFG = 011_B) the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input

clock signal.

The frequency of f_CPUdirectly follows the frequency of f_OSCso the high and low time of

f

_CPU(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

f_OSC

.

The timings listed below that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective circumstances. This minimum value

can be calculated via the following formula:

TCL_min= 1/f_OSC× DC_min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of f_OSCis

compensated so the duration of 2TCL is always 1/f_OSC. The minimum value TCL_min

therefore has to be used only once for timings that require an odd number of TCLs (1, 3,

…). Timings that require an even number of TCLs (2, 4, …) may use the formula

2TCL = 1/f_OSC

Note: The address float timings in Multiplexed bus mode (t₁₁and t₄₅) use the maximum

duration of TCL (TCL_max= 1/f_OSC× DC_max) instead of TCL_min

.

Data Sheet

59

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

AC Characteristics

External Clock Drive XTAL1 (Main Oscillator)

(Operating Conditions apply)

Table 11

External Clock Drive Characteristics

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

Oscillator period t_OSCMSR 40

max. min.

max.

500¹⁾ns

–

20

6

–

6

60¹⁾

10

–

High time²⁾

Low time²⁾

Rise time²⁾

t₁

t₂

t₃

t₄

SR 20³⁾

SR –

–

ns

–

6

–

10

–

10

Fall time²⁾

SR –

–

1)

The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation

mode. Please see respective table above.

2)

3)

The clock input signal must reach the defined levels V_IL2and V_IH2

.

The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f_CPU) in

direct drive mode depends on the duty cycle of the clock input signal.

t₁

t₃

t₄

V_IH2

V_IL

0.5 V_DD

t₂

t_OSC

MCT02534

Figure 13

External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 16 MHz.

It is strongly recommended to measure the oscillation allowance (or margin) in the

final target system (layout) to determine the optimum parameters for the oscillator

operation. Please refer to the limits specified by the crystal supplier.

When driven by an external clock signal it will accept the specified frequency

range. Operation at lower input frequencies is possible but is guaranteed by

design only (not 100% tested).

Data Sheet

60

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

AC Characteristics

External Clock Drive XTAL3 (Auxiliary Oscillator)

(Operating Conditions apply)

Table 12

AC Characteristics

Symbol

Parameter

Optimum Input Clock Variable Input Clock

Unit

= 32 kHz

min.

Oscillator period t_OSCASR 31

1 / t_OSCA= 10 to 50 kHz

max.

31

–

min.

max.

100

–

20

µs

1)

High time

Low time

Rise time

t₁

t₂

t₃

t₄

SR 6¹⁾

SR –

0.2 × t_OSCA

–

0.2 × t_OSCA

–

12

–

0.4 × t_OSCAµs

Fall time

SR –

1)

The clock input signal must reach the defined levels V_ILand V_IH2

.

Note: The auxiliary oscillator is optimized for oscillation with a crystal at a frequency of

32 kHz. When driven by an external clock signal it will accept the specified

frequency range.

Operation at lower input frequencies is possible but is guaranteed by design only

(not 100% tested).

Data Sheet

61

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

A/D Converter Characteristics

(Operating Conditions apply)

Table 13

A/D Converter Characteristics

Symbol Limit Values

min. max.

_AREFSR 4.0 _DD+ 0.1 V

_AGNDSR V_SS- 0.1 V_SS+ 0.2 V

Parameter

Unit Test

Condition

1)

Analog reference supply

Analog reference ground

V

2)

3)

4)

Analog input voltage range V_AINSR V_AGND

V_AREF

6.25

V

Basic clock frequency

Conversion time

f_BC

t_C

0.5

CC –

MHz

–

40 t_BC

+

t_S+ 2t_CPU

3328 t_BC

±2

t

5)

_CPU= 1 / f_CPU

Calibration time after reset t_CALCC –

–

1)

Total unadjusted error

TUE CC –

_AREFSR –

LSB

kΩ

Internal resistance of

R

t

_BC/ 60

t

_BCin [ns]⁶⁾⁷⁾

reference voltage source

- 0.25

Internal resistance of analog R_ASRCSR –

t_S/ 450

kΩ t_Sin [ns]⁷⁾⁸⁾

source

- 0.25

7)

ADC input capacitance

C_AINCC –

33

pF

1)

TUE is tested at V_AREF= 5.0 V, V_AGND= 0 V, V_DD= 4.9 V. It is guaranteed by design for all other voltages

within the defined voltage range.

If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V

(i.e. V_AREF= V_DD= +0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see I_OV

specification) does not exceed 10 mA.

During the reset calibration sequence the maximum TUE may be ±4 LSB.

2)

V_AINmay exceed V_AGNDor V_AREFup to the absolute maximum ratings. However, the conversion result in

these cases will be X000 or X3FF , respectively.

H

3)

4)

The limit values for f_BCmust not be exceeded when selecting the CPU frequency and the ADCTC setting.

This parameter includes the sample time t_S, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the basic clock t_BCdepend on programming and can be taken from Table 14.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

5)

6)

During the reset calibration conversions can be executed (with the current accuracy). The time required for

these conversions is added to the total reset calibration time.

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within each conversion step. The maximum internal resistance results from the programmed conversion

timing.

7)

Not 100% tested, guaranteed by design and characterization.

Data Sheet

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V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

8)

During the sample time the input capacitance C_AINcan be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within t_S.

After the end of the sample time t_S, changes of the analog input voltage have no effect on the conversion

result.

Values for the sample time t_Sdepend on programming and can be taken from Table 14.

Sample time and conversion time of the C161CS/JC/JI’s A/D Converter are

programmable. Table 14 should be used to calculate the above timings.

The limit values for f_BCmust not be exceeded when selecting ADCTC.

Table 14

A/D Converter Computation Table

ADCON.13|12 Sample time

ADCON.15|14 A/D Converter

(ADCTC)

Basic Clock f_BC

(ADSTC)

t_S

00

01

10

11

f

_CPU/ 4

_CPU/ 2

_CPU/ 16

_CPU/ 8

00

01

10

11

t

_BC× 8

_BC× 16

_BC× 32

_BC× 64

Converter Timing Example:

Assumptions:

f_CPU= 25 MHz (i.e. t_CPU= 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.

Basic clock

Sample time

f_BC

t_S

= f_CPU/ 4 = 6.25 MHz, i.e. t_BC= 160 ns.

= t_BC× 8 = 1280 ns.

Conversion time t_C

= t_S+ 40 t_BC+ 2 t_CPU= (1280 + 6400 + 80) ns = 7.8 µs.

Data Sheet

63

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Testing Waveforms

2.4 V

1.8 V

0.8 V

1.8 V

0.8 V

Test Points

0.45 V

’

AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.

Timing measurements are made at _IHmin for a logic 1’ and _ILmax for a logic 0’.

V

MCA04414

Figure 14

Input Output Waveforms

V_Load+ 0.1 V

V_OH- 0.1 V

Timing

Reference

Points

V_Load- 0.1 V

V_OL+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

but begins to float when a 100 mV change from the loaded V_OH

/

V_OLlevel occurs (I_OH

/

I

_OL= 20 mA).

MCA00763

Figure 15

Float Waveforms

Data Sheet

64

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx

registers and represent the special characteristics of the programmed memory cycle.

The following table describes, how these variables are to be computed.

Table 15

Memory Cycle Variables

Symbol Values

Description

ALE Extension

t_A

TCL × <ALECTL>

Memory Cycle Time Waitstates t_C

Memory Tristate Time

2TCL × (15 - <MCTC>)

2TCL × (1 - <MTTC>)

t_F

Note: Please respect the maximum operating frequency of the respective derivative.

AC Characteristics

Multiplexed Bus

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

ALE high time

t₅CC 10 + t_A

t₆CC 4 + t_A

t₇CC 10 + t_A

t₈CC 10 + t_A

t₉CC -10 + t_A

t₁₀CC –

–

TCL - 10

+ t_A

–

ns

Address setup to ALE

Address hold after ALE

–

TCL - 16

+ t_A

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (no RW-delay)

–

-10 + t_A

–

Address float after RD,

WR (with RW-delay)

6

–

6

Address float after RD,

WR (no RW-delay)

t₁₁CC –

26

–

TCL + 6

RD, WR low time

(with RW-delay)

t₁₂CC 30 + t_C

2TCL - 10 –

+ t_C

Data Sheet

65

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Multiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max.

min.

max.

RD, WR low time

(no RW-delay)

t₁₃CC 50 + t_C

–

3TCL - 10 –

+ t_C

ns

RD to valid data in

(with RW-delay)

t₁₄SR –

20 + t_C

40 + t_C

–

0

–

2TCL - 20 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 20 ns

+ t_C

ALE low to valid data in

t₁₆SR –

40 + t_A

+ t_C

3TCL - 20 ns

+ t_A+ t_C

Address to valid data in

t₁₇SR –

50 + 2t_A

+ t_C

4TCL - 30 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data float after RD

Data valid to WR

Data hold after WR

t₁₉SR –

26 + t_F

2TCL - 14 ns

+ t_F

t₂₂CC 20 + t_C

t₂₃CC 26 + t_F

–

2TCL - 20 –

+ t_C

ns

–

2TCL - 14 –

+ t_F

ALE rising edge after RD, t₂₅CC 26 + t_F

WR

–

2TCL - 14 –

+ t_F

Address hold after RD,

WR

ALE falling edge to CS¹⁾t₃₈CC -4 - t_A

CS low to Valid Data In¹⁾t₃₉SR –

t₂₇CC 26 + t_F

–

2TCL - 14 –

+ t_F

10 - t_A

-4 - t_A

10 - t_A

40

–

3TCL - 20 ns

+ t_C

+ 2t_A

+ t_C+ 2t_A

CS hold after RD, WR¹⁾t₄₀CC 46 + t_F

–

3TCL - 14 –

ns

+ t_F

ALE fall. edge to RdCS, t₄₂CC 16 + t_A

–

TCL - 4

–

WrCS (with RW delay)

+ t_A

Data Sheet

66

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Multiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

ALE fall. edge to RdCS, t₄₃CC -4 + t_A

WrCS (no RW delay)

–

-4

+ t_A

–

ns

Address float after RdCS, t₄₄CC –

WrCS (with RW delay)

0

–

0

Address float after RdCS, t₄₅CC –

WrCS (no RW delay)

20

TCL

RdCS to Valid Data In

(with RW delay)

t₄₆SR –

t₄₇SR –

16 + t_C

2TCL - 24 ns

+ t_C

RdCS to Valid Data In

(no RW delay)

36 + t_C

3TCL - 24 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 30 + t_C

(with RW delay)

–

2TCL - 10 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 50 + t_C

(no RW delay)

3TCL - 10 –

+ t_C

Data valid to WrCS

t₅₀CC 26 + t_C

2TCL - 14 –

+ t_C

Data hold after RdCS

Data float after RdCS

t₅₁SR 0

t₅₂SR –

–

0

–

20 + t_F

2TCL - 20 ns

+ t_F

Address hold after

RdCS, WrCS

t₅₄CC 20 + t_F

t₅₆CC 20 + t_F

–

2TCL - 20 –

+ t_F

ns

Data hold after WrCS

2TCL - 20 –

+ t_F

1)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

67

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A23-A16

Address

(A15-A8)

BHE, CSxE

t₅₄

t₁₉

t₆

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₈

t₁₀

t₁₄

t₁₂

`

RD

t₄₂

t₄₄

t₅₁

t₅₂

t₄₆

t₄₈

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₈

t₁₀

t₂₂

t₅₆

t₁₂

WR, WRL,

WRH

t₄₂

t₄₄

t₅₀

t₄₈

WrCSx

MCT04439

Figure 16

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

68

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A23-A16

Address

(A15-A8)

BHE, CSxE

t₆

t₅₄

t₁₉

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₈

t₁₀

t₁₄

t₁₂

RD

t₄₂

t₄₄

t₅₁

t₅₂

t₄₆

t₄₈

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₈

t₁₀

t₂₂

t₅₆

t₁₂

WR, WRL,

WRH

t₄₂

t₄₄

t₅₀

t₄₈

WrCSx

MCT04440

Figure 17

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

69

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A23-A16

Address

(A15-A8)

BHE, CSxE

t₅₄

t₁₉

t₆

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₉

t₁₁

t₁₅

t₁₃

RD

t₄₃

t₄₅

t₅₁

t₅₂

t₄₇

t₄₉

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₉

t₁₁

t₂₂

t₅₆

t₁₃

WR, WRL,

WRH

t₄₃

t₄₅

t₅₀

t₄₉

WrCSx

MCT04441

Figure 18

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

70

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A23-A16

Address

(A15-A8)

BHE, CSxE

t₆

t₅₄

t₁₉

t₇

t₁₈

Read Cycle

Address

Data IN

BUS

t₉

t₁₁

t₁₅

t₁₃

RD

t₄₃

t₄₅

t₅₁

t₄₇

t₄₉

t₅₂

RdCSx

t₂₃

Write Cycle

Address

Data OUT

BUS

t₉

t₁₁

t₂₂

t₅₆

t₁₃

WR, WRL,

WRH

t₄₃

t₄₅

t₅₀

t₄₉

WrCSx

MCT04442

Figure 19

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

71

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

AC Characteristics

Demultiplexed Bus

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz

1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

ALE high time

t₅CC 10 + t_A

t₆CC 4 + t_A

t₈CC 10 + t_A

t₉CC -10 + t_A

t₁₂CC 30 + t_C

t₁₃CC 50 + t_C

t₁₄SR –

–

TCL - 10

+ t_A

–

ns

Address setup to ALE

–

TCL - 16

+ t_A

–

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ t_A

ALE falling edge to RD,

WR (no RW-delay)

–

-10

+ t_A

RD, WR low time

(with RW-delay)

–

2TCL - 10 –

+ t_C

RD, WR low time

(no RW-delay)

–

3TCL - 10 –

+ t_C

RD to valid data in

(with RW-delay)

20 + t_C

40 + t_C

–

0

–

2TCL - 20 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 20 ns

+ t_C

ALE low to valid data in

t₁₆SR –

40 +

t_A+ t_C

3TCL - 20 ns

+ t_A+ t_C

Address to valid data in

t₁₇SR –

50 +

2t_A+ t_C

4TCL - 30 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data float after RD rising t₂₀SR –

26 +

2t_A+ t_F

2TCL - 14 ns

+ 22t_A

+ t_F

1)

edge (with RW-delay¹⁾)

1)

Data float after RD rising t₂₁SR –

10 +

2t_A+ t_F

–

TCL - 10

ns

1)

edge (no RW-delay¹⁾)

+ 22t_A

1)

+ t_F

Data Sheet

72

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Demultiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz

1 / 2TCL = 1 to 25 MHz

min.

max.

min. max.

Data valid to WR

t₂₂CC 20 + t_C

–

2TCL - 20 –

+ t_C

ns

Data hold after WR

t₂₄CC 10 + t_F

TCL - 10

+ t_F

–

ALE rising edge after RD, t₂₆CC -10 + t_F

-10 + t_F

WR

Address hold after WR²⁾t₂₈CC 0 + t_F

ALE falling edge to CS³⁾t₃₈CC -4 - t_A

CS low to Valid Data In³⁾t₃₉SR –

–

0 + t_F

-4 - t_A

–

ns

10 - t_A

40 +

3TCL - 20 ns

t_C+ 2t_A

+ t_C+ 2t_A

CS hold after RD, WR³⁾t₄₁CC 6 + t_F

–

TCL - 14

+ t_F

–

ns

ALE falling edge to RdCS, t₄₂CC 16 + t_A

WrCS (with RW-delay)

–

TCL - 4

+ t_A

ALE falling edge to RdCS, t₄₃CC -4 + t_A

–

-4

WrCS (no RW-delay)

+ t_A

RdCS to Valid Data In

(with RW-delay)

t₄₆SR –

t₄₇SR –

16 + t_C

–

2TCL - 24 ns

+ t_C

RdCS to Valid Data In

(no RW-delay)

36 + t_C

3TCL - 24 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 30 + t_C

(with RW-delay)

–

2TCL - 10 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 50 + t_C

(no RW-delay)

3TCL - 10 –

+ t_C

Data valid to WrCS

t₅₀CC 26 + t_C

2TCL - 14 –

+ t_C

Data hold after RdCS

t₅₁SR 0

t₅₃SR –

–

0

–

Data float after RdCS

(with RW-delay)¹⁾

20 + t_F

2TCL - 20 ns

1)

+ 2t_A+ t_F

Data Sheet

73

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Demultiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz

1 / 2TCL = 1 to 25 MHz

min.

t₆₈SR –

max.

min.

max.

Data float after RdCS

(no RW-delay)¹⁾

0 + t_F

–

TCL - 20

+ 2t_A+ t_F

ns

1)

Address hold after

RdCS, WrCS

t₅₅CC -6 + t_F

t₅₇CC 6 + t_F

–

-6 + t_F

–

Data hold after WrCS

TCL - 14 + –

t_F

1)

RW-delay and t_Arefer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2)

Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

74

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₂₈

t₁₇

A23-A16

A15-A0

Address

BHE, CSxE

t₅₅

t₆

t₂₀

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₈

t₁₄

t₁₂

RD

t₄₂

t₅₁

t₄₆

t₄₈

t₅₃

RdCSx

Write Cycle

t₂₄

BUS

(D15-D8)

D7-D0

Data OUT

t₈

t₂₂

t₅₇

t₁₂

WR, WRL,

WRH

t₄₂

t₅₀

t₄₈

WrCSx

MCT04443

Figure 20

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

75

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₁₇

t₂₈

A23-A16

A15-A0

Address

BHE, CSxE

t₆

t₅₅

t₂₀

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₈

t₁₄

t₁₂

RD

t₄₂

t₅₁

t₄₆

t₄₈

t₅₃

RdCSx

Write Cycle

t₂₄

BUS

Data OUT

(D15-D8)

D7-D0

t₈

t₂₂

t₅₇

t₁₂

WR, WRL,

WRH

t₄₂

t₅₀

t₄₈

WrCSx

MCT04444

Figure 21

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

76

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₂₈

t₁₇

A23-A16

A15-A0

Address

BHE, CSxE

t₅₅

t₆

t₂₁

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₉

t₁₅

t₁₃

RD

t₄₃

t₅₁

t₄₇

t₄₉

t₆₈

RdCSx

Write Cycle

t₂₄

BUS

(D15-D8)

D7-D0

Data OUT

t₂₂

t₅₇

t₉

t₁₃

WR, WRL,

WRH

t₄₃

t₅₀

t₄₉

WrCSx

MCT04445

Figure 22

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

77

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₁₇

t₂₈

A23-A16

A15-A0

Address

BHE, CSxE

t₆

t₅₅

t₂₁

Read Cycle

t₁₈

BUS

Data IN

(D15-D8)

D7-D0

t₉

t₁₅

t₁₃

RD

t₄₃

t₅₁

t₄₇

t₄₉

t₆₈

RdCSx

Write Cycle

t₂₄

BUS

Data OUT

(D15-D8)

D7-D0

t₉

t₂₂

t₅₇

t₁₃

WR, WRL,

WRH

t₄₃

t₅₀

t₄₉

WrCSx

MCT04446

Figure 23

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

78

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

AC Characteristics

CLKOUT and READY

(Operating Conditions apply)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min.

max.

min.

2TCL

TCL - 6

TCL - 10

–

max.

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

t₂₉CC 40

t₃₀CC 14

t₃₁CC 10

t₃₂CC –

40

–

2TCL

ns

–

4

t₃₃CC –

4

–

4

CLKOUT rising edge to

ALE falling edge

t₃₄CC 0 + t_A

10 + t_A0 + t_A

10 + t_A

Synchronous READY

setup time to CLKOUT

t₃₅SR 14

t₃₆SR 4

t₃₇SR 54

t₅₈SR 14

t₅₉SR 4

–

14

–

ns

Synchronous READY

hold time after CLKOUT

4

Asynchronous READY

low time

2TCL + t₅₈

Asynchronous READY

setup time¹⁾

14

4

Asynchronous READY

hold time¹⁾

Async. READY hold time t₆₀SR 0

after RD, WR high

0

TCL - 20

+ 2t_A+ t_C

+ t_F

+ 2t_A+

t_C

+ t_F

2)

(Demultiplexed Bus)²⁾

2)

1)

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2)

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This

adds even more time for deactivating READY.

The 2t_Aand t_Crefer to the next following bus cycle, t_Frefers to the current bus cycle.

The maximum limit for t₆₀must be fulfilled if the next following bus cycle is READY controlled.

Data Sheet

79

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

READY

Waitstate

MUX/Tristate ⁶⁾

Running Cycle ¹⁾

t₃₂

t₃₃

t₃₀

t₂₉

CLKOUT

ALE

t₃₁

t₃₄

7)

Command

RD, WR

2)

t₃₆

t₃₅

Sync

3)

READY

4)

t₅₉

t₆₀

t₅₈

Async

3)

READY

5)

see ⁶⁾

t₃₇

MCT04447

Figure 24

CLKOUT and READY

Notes

1)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

2)

READY sampled HIGH at this sampling point generates a READY controlled waitstate,

READY sampled LOW at this sampling point terminates the currently running bus cycle.

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or

WR).

3)

4)

5)

6)

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT

(e.g. because CLKOUT is not enabled), it must fulfill t₃₇in order to be safely synchronized. This is guaranteed,

4)

if READY is removed in reponse to the command (see Note ).

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted here.

For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without

MTTC waitstate this delay is zero.

The next external bus cycle may start here.

7)

Data Sheet

80

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

AC Characteristics

External Bus Arbitration

(Operating Conditions apply)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min.

max.

min.

max.

HOLD input setup time

to CLKOUT

t₆₁SR 20

t₆₂CC –

t₆₃CC –

–

20

–

ns

CLKOUT to HLDA high

or BREQ low delay

20

–

20

CLKOUT to HLDA low

or BREQ high delay

CSx release

t₆₄CC –

t₆₅CC -4

t₆₆CC –

t₆₇CC – 4

20

24

20

24

–

20

24

20

24

ns

CSx drive

-4

–

Other signals release

Other signals drive

– 4

Data Sheet

81

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

CLKOUT

HOLD

t₆₁

t₆₃

HLDA

see¹⁾

t₆₂

2)

BREQ

t₆₄

3)

CSx

(On P6.x)

t₆₆

Other

Signals

1)

MCT04448

Figure 25

External Bus Arbitration, Releasing the Bus

Notes

1)

The C161CS/JC/JI will complete the currently running bus cycle before granting bus access.

This is the first possibility for BREQ to get active.

The CS outputs will be resistive high (pullup) after t₆₄.

2)

3)

Data Sheet

82

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

2)

CLKOUT

HOLD

t₆₁

t₆₂

HLDA

t₆₂

t₆₃

1)

BREQ

t₆₅

CSx

(On P6.x)

t₆₇

Other

Signals

MCT04449

Figure 26

External Bus Arbitration, (Regaining the Bus)

Notes

1)

This is the last chance for BREQ to trigger the indicated regain-sequence.

Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.

Please note that HOLD may also be deactivated without the C161CS/JC/JI requesting the bus.

The next C161CS/JC/JI driven bus cycle may start here.

2)

Data Sheet

83

V3.0, 2001-01

C161CS/JC/JI-32R

C161CS/JC/JI-L

Package Outline

P-TQFP-128-2

(Plastic Thin Metric Quad Flat Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device

Data Sheet

84

V3.0, 2001-01

Infineon goes for Business Excellence

“Business excellence means intelligent approaches and clearly

defined processes, which are both constantly under review and

ultimately lead to good operating results.

Better operating results and business excellence mean less

idleness and wastefulness for all of us, more professional

success, more accurate information, a better overview and,

thereby, less frustration and more satisfaction.”

Dr. Ulrich Schumacher

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	SAB-C161JI-LF
厂家：	Infineon
描述：	16-Bit Single-Chip Microcontroller 16位单芯片微控制器微控制器和处理器外围集成电路时钟
文件：	总89页 (文件大小：1266K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAB-C161JI-LF [INFINEON]

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