SAB-C505A-4R20M_技术文档

Data Sheet, Dec. 2000

C505

C505C

C505A

C505CA

8-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2000-12

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address

list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Data Sheet, Dec. 2000

C505

C505C

C505A

C505CA

8-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

C505/C505C/C505A/C505CA Data Sheet

Revision History :

Current Version : 2000-12

Previous Releases :

08.00, 06.00, 07.99, 12.97

Page

Subjects (major changes since last revision)

(in previous (in current

version

24

version)

24

Version register VR2 for C505A-4R/C505CA-4R BB step is updated.

Controller Area Network (CAN): License of Robert Bosch GmbH

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Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

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8-Bit Single-Chip Microcontroller

C500 Family

C505/C505C/C505A/

C505CA

Advance Information

• Fully compatible to standard 8051 microcontroller

• Superset of the 8051 architecture with 8 datapointers

• Up to 20 MHz operating frequency

– 375 ns instruction cycle time @16 MHz

– 300 ns instruction cycle time @20 MHz (50 % duty cycle)

• On-chip program memory (with optional memory protection)

– C505(C)(A)-2R :

16K byte on-chip ROM

– C505A-4R/C505CA-4R: 32K byte on-chip ROM

– C505A-4E/C505CA-4E: 32K byte on-chip OTP

– alternatively up to 64k byte external program memory

• 256 byte on-chip RAM

• On-chip XRAM

– C505/C505C :

256 byte

– C505A/C505CA : 1K byte

(more features on next page)

XRAM

Oscillator

Watchdog

RAM

I/O

Port 0

Port 1

C505/C505C: 256 byte

C505A/C505CA: 1K byte

256 byte

A/D Converter

8 analog inputs /

8 digit. I/O

Timer

C500

C505/C505C : 8-bit

C505A/C505CA : 10-bit

8-bit

USART

0

Core

Port 2

I/O

Timer

1

Timer 2

8 Datapointers

Full-CAN Controller

C505C/C505CA only

Port 3

Port 4

I/O

Program Memory

C505(C)(A)-2R : 16K ROM

C505A-4R/C505CA-4R : 32K ROM

C505A-4E/C505CA-4E : 32K OTP

I/O (2-bit I/O port)

Watchdog Timer

Figure 1

C505 Functional Units

Data Sheet

1

12.00

C505/C505C/C505A/C505CA

Features (continued) :

• 32 + 2 digital I/O lines

– Four 8-bit digital I/O ports

– One 2-bit digital I/O port (port 4)

– Port 1 with mixed analog/digital I/O capability

• Three 16-bit timers/counters

– Timer 0 / 1 (C501 compatible)

– Timer 2 with 4 channels for 16-bit capture/compare operation

• Full duplex serial interface with programmable baudrate generator (USART)

• Full CAN Module, version 2.0 B compliant (C505C and C505CA only)

– 256 register/data bytes located in external data memory area

– 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz

– internal CAN clock prescaler when input frequency is over 10 MHz

• On-chip A/D Converter

– up to 8 analog inputs

– C505/C505C : 8-bit resolution

– C505A/C505CA: 10-bit resolution

• Twelve interrupt sources with four priority levels

• On-chip emulation support logic (Enhanced Hooks Technology ^TM

• Programmable 15-bit watchdog timer

• Oscillator watchdog

)

• Fast power on reset

• Power Saving Modes

– Slow-down mode

– Idle mode (can be combined with slow-down mode)

– Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin

• P-MQFP-44 package

• Pin configuration is compatible to C501, C504, C511/C513-family

• Temperature ranges:

SAB-C505 versions

SAF-C505 versions

SAH-C505 versions

SAK-C505 versions

T_A= 0 to 70 °C

T_A= -40 to 85°C

T_A= -40 to 110°C

T_A= -40 to 125°C

Data Sheet

2

12.00

C505/C505C/C505A/C505CA

Table 1

Differences in Functionality of the C505 MCUs

Device

Internal Program Memory XRAM Size A/D Converter CAN

Resolution

Controller

ROM

OTP

C505-2R

16K byte

–

256 byte

1K byte

8 Bit

–

√

–

√

–

√

C505-L

–

8 Bit

C505C-2R

C505C-L

16K byte

–

8 Bit

–

8 Bit

C505A-4R

C505A-2R

C505A-L

32K byte

–

10 Bit

16K byte

–

C505CA-4R

C505CA-2R

C505CA-L

C505A-4E

C505CA-4E

32K byte

–

16K byte

–

32K byte

Note: The term C505 refers to all versions described within this document unless otherwise noted.

However the term C505 may also be restricted by the context to refer to only CAN-less

derivatives with 8-Bit ADC which are C505-2R and C505-L in this document.

Note: The term C505(C)(A)-2R, for simplicity, is used to stand for C505 16K byte ROM versions

within this document which are C505-2R, C505C-2R, C505A-2R and C505CA-2R.

Ordering Information

The ordering code for Infineon Technologies’ microcontrollers provides an exact reference to the

required product. This ordering code identifies:

• the derivative itself, i.e. its function set

• the specificed temperature rage

• the package and the type of delivery

For the available ordering codes for the C505 please refer to the “Product information

Microcontrollers”, which summarizes all available microcontroller variants.

Data Sheet

3

12.00

C505/C505C/C505A/C505CA

V_DDV_SS

Port 0

8-bit Digital I/O

V_AREF

V_AGND

Port 1

8-bit Digital I/O /

8-bit Analog Inputs

XTAL1

XTAL2

C505

C505C

C505A

C505CA

Port 2

8-bit Digital I/O

RESET

EA

Port 3

8-bit Digital I/O

ALE

PSEN

Port 4

2-bit Digital I/O

Figure 2

Logic Symbol

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet

4

12.00

C505/C505C/C505A/C505CA

33 32 31 30 29 28 27 26 25 24 23

34

35

36

37

38

39

40

41

42

43

44

22

21

20

19

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P2.0 / A8

P0.3 / AD3

P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

C505

C505C

C505A

C505CA

V _AREF

18

17

16

15

14

13

12

V _AGND

V

DD

P1.0 / AN0 / INT3 / CC0

P1.1 / AN1 / INT4 / CC1

P1.2 / AN2 / INT5 / CC2

P1.3 / AN3 / INT6 / CC3

P1.4 / AN4

SS

XTAL1

XTAL2

P3.7 / RD

P3.6 / WR

1

2

3

4

5

6

7

8

9 10 11

This pin functionality is not available in the C505/C505A.

Figure 3

C505 Pin Configuration P-MQFP-44 Package (Top View)

Data Sheet

5

12.00

C505/C505C/C505A/C505CA

Table 2

Pin Definitions and Functions

Symbol

Pin Number I/O

*)

Function

Port 1

P1.0-P1.7

40-44,1-3

I/O

is an 8-bit quasi-bidirectional port with internal pull-up

arrangement. Port 1 pins can be used for digital input/output

or as analog inputs of the A/D converter. Port 1 pins that

have 1’s written to them are pulled high by internal pull-up

transistors and in that state can be used as inputs. As

inputs, port 1 pins being externally pulled low will source

current (I_IL, in the DC characteristics) because of the

internal pullup transistors. Port 1 pins are assigned to be

used as analog inputs via the register P1ANA.

As secondary digital functions, port 1 contains the interrupt,

timer, clock, capture and compare pins. The output latch

corresponding to a secondary function must be

programmed to a one (1) for that function to operate (except

for compare functions). The secondary functions are

assigned to the pins of port 1 as follows:

40

41

42

43

P1.0 / AN0 / INT3 / CC0 Analog input channel 0

interrupt 3 input /

capture/compare channel 0 I/O

P1.1 / AN1 / INT4 / CC1 Analog input channel 1/

interrupt 4 input /

capture/compare channel 1 I/O

P1.2 / AN2 / INT5 / CC2 Analog input channel 2 /

interrupt 5 input /

capture/compare channel 2 I/O

P1.3 / AN3 / INT6 / CC3 Analog input channel 3

interrupt 6 input /

capture/compare channel 3 I/O

44

1

P1.4 / AN4

P1.5 / AN5 / T2EX

Analog input channel 4

Analog input channel 5 / Timer 2

external reload / trigger input

Analog input channel 6 /

system clock output

2

3

P1.6 / AN6 / CLKOUT

P1.7 / AN7 / T2

Analog input channel 7 /

counter 2 input

Port 1 is used for the low-order address byte during program

verification of the C505 ROM versions (i.e. C505(C)(A)-2R/

C505A-4R/C505CA-4R).

*) I = Input

O= Output

Data Sheet

6

12.00

C505/C505C/C505A/C505CA

Table 2

Pin Definitions and Functions (cont’d)

Symbol

Pin Number I/O

*)

Function

RESET

4

I

RESET

A high level on this pin for two machine cycle while the

oscillator is running resets the device. An internal diffused

resistor to V_SSpermits power-on reset using only an

external capacitor to V_DD

.

P3.0-P3.7

5, 7-13

I/O

Port 3

is an 8-bit quasi-bidirectional port with internal pull-up

arrangement. Port 3 pins that have 1’s written to them are

pulled high by the internal pull-up transistors and in that

state can be used as inputs. As inputs, port 3 pins being

externally pulled low will source current (I_IL, in the DC

characteristics) because of the internal pullup transistors.

The output latch corresponding to a secondary function

must be programmed to a one (1) for that function to operate

(except for TxD and WR). The secondary functions are

assigned to the pins of port 3 as follows:

5

7

8

9

P3.0 / RxD

P3.1 / TxD

P3.2 / INT0

P3.3 / INT1

Receiver data input (asynch.) or data

input/output (synch.) of serial interface

Transmitter data output (asynch.) or

clock output (synch.) of serial interface

External interrupt 0 input / timer 0 gate

control input

External interrupt 1 input / timer 1 gate

control input

10

11

12

P3.4 / T0

P3.5 / T1

P3.6 / WR

Timer 0 counter input

Timer 1 counter input

WR control output; latches the data

byte from port 0 into the external data

memory

13

P3.7 / RD

RD control output; enables the external

data memory

*) I = Input

O= Output

Data Sheet

7

12.00

C505/C505C/C505A/C505CA

Table 2

Pin Definitions and Functions (cont’d)

Symbol

Pin Number I/O

*)

Function

P4.0

P4.1

6

28

I/O

Port 4

is a 2-bit quasi-bidirectional port with internal pull-up

arrangement. Port 4 pins that have 1’s written to them are

pulled high by the internal pull-up transistors and in that

state can be used as inputs. As inputs, port 4 pins being

externally pulled low will source current (I_IL, in the DC

characteristics) because of the internal pullup transistors.

The output latch corresponding to the secondary function

RXDC must be programmed to a one (1) for that function to

operate. The secondary functions are assigned to the two

pins of port 4 as follows (C505C and C505CA only) :

P4.0 / TXDC

P4.1 / RXDC

Transmitter output of CAN controller

Receiver input of CAN controller

XTAL2

XTAL1

14

15

O

I

XTAL2

Output of the inverting oscillator amplifier.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock generator circuits.

To drive the device from an external clock source, XTAL1

should be driven, while XTAL2 is left unconnected. To

operate above a frequency of 16 MHz, a duty cycle of the

etxernal clock signal of 50 % should be maintained.

Minimum and maximum high and low times as well as rise/

fall times specified in the AC characteristics must be

observed.

*) I = Input

O= Output

Data Sheet

8

12.00

C505/C505C/C505A/C505CA

Table 2

Pin Definitions and Functions (cont’d)

Symbol

Pin Number I/O

*)

Function

P2.0-P2.7

18-25

I/O

Port 2

is a an 8-bit quasi-bidirectional I/O port with internal pullup

resistors. Port 2 pins that have 1’s written to them are pulled

high by the internal pullup resistors, and in that state can be

used as inputs. As inputs, port 2 pins being externally pulled

low will source current (I_IL, in the DC characteristics)

because of the internal pullup resistors. Port 2 emits the

high-order address byte during fetches from external

program memory and during accesses to external data

memory that use 16-bit addresses (MOVX @DPTR). In this

application it uses strong internal pullup transistors when

issuing 1s. During accesses to external data memory that

use 8-bit addresses (MOVX @Ri), port 2 issues the

contents of the P2 special function register and uses only

the internal pullup resistors.

PSEN

26

27

O

The Program Store Enable

output is a control signal that enables the external program

memory to the bus during external fetch operations. It is

activated every three oscillator periods except during

external data memory accesses. Remains high during

internal program execution. This pin should not be driven

during reset operation.

ALE

The Address Latch Enable

output is used for latching the low-byte of the address into

external memory during normal operation. It is activated

every three oscillator periods except during an external data

memory access. When instructions are executed from

internal ROM or OTP (EA=1) the ALE generation can be

disabled by bit EALE in SFR SYSCON.

ALE should not be driven during reset operation.

*) I = Input

O= Output

Data Sheet

9

12.00

C505/C505C/C505A/C505CA

Table 2

Pin Definitions and Functions (cont’d)

Symbol

Pin Number I/O

*)

Function

EA

29

I

External Access Enable

When held at high level, instructions are fetched from the

internal program memory when the PC is less than 4000

H

(C505(C)(A)-2R) or 8000_H(C505A-4R/C505CA-4R/C505A-

4E/C505CA-4E). When held at low level, the C505 fetches

all instructions from external program memory.

For the C505 romless versions (i.e. C505-L, C505C-L,

C505A-L and C505CA-L) this pin must be tied low.

For the ROM protection version EA pin is latched during

reset.

P0.0-P0.7

37-30

I/O

Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

have 1’s written to them float, and in that state can be used

as high-impendance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external

program or data memory. In this application it uses strong

internal pullup transistors when issuing 1’s.

Port 0 also outputs the code bytes during program

verification in the C505 ROM versions. External pullup

resistors are required during program verification.

V_AREF

V_AGND

V_SS

38

39

16

17

–

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

Ground (0V)

V_DD

Power Supply (+5V)

*) I = Input

O= Output

Data Sheet

10

12.00

C505/C505C/C505A/C505CA

V

DD

ROM/

OTP

1)

Oscillator Watchdog

OSC & Timing

Vss

XRAM

1)

RAM

16K or 32K

256 Byte

or 1K Byte

XTAL1

XTAL2

256 Byte

Byte

CPU

8 datapointers

RESET

ALE

PSEN

EA

Programmable

Watchdog Timer

Port 0

Port 1

Port 2

Port 3

Port 4

8-bit digit. I/O

Timer 0

Timer 1

Port 1

8-bit digit. I/O /

8-bit analog In

Port 2

8-bit digit. I/O

Timer 2

USART

Baudrate generator

Port 3

8-bit digit. I/O

Full-CAN

Controller

Port 4

2-bit digit. I/O

Interrupt Unit

A/D Converter

V_AREF

V_AGND

1)

8-/10-Bit

Emulation

Support

Logic

S&H

MUX

C505C/C505CA only. 1) Please refer to Table 1 for device specific configuration.

Figure 4

Block Diagram of the C505/C505C/C505A/C505CA

Data Sheet

11

12.00

C505/C505C/C505A/C505CA

CPU

The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities

for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program

memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-

byte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns (20MHz:

300 ns).

Special Function Register PSW (Address D0 )

H

Reset Value : 00

H

Bit No. MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

P

H

D0

CY

AC

F0

RS1

RS0

OV

F1

PSW

H

Bit

Function

CY

Carry Flag

Used by arithmetic instruction.

AC

Auxiliary Carry Flag

Used by instructions which execute BCD operations.

F0

General Purpose Flag

RS1

RS0

Register Bank Select Control Bits

These bits are used to select one of the four register banks.

RS1

RS0

Function

Bank 0 selected, data address 00 -07

0

1

0

1

0

1

H

Bank 1 selected, data address 08 -0F

H

Bank 2 selected, data address 10 -17

H

Bank 3 selected, data address 18 -1F

H

OV

Overflow Flag

Used by arithmetic instruction.

General Purpose Flag

Parity Flag

F1

P

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Data Sheet

12

12.00

C505/C505C/C505A/C505CA

Memory Organization

The C505 CPU manipulates operands in the following four address spaces:

– On-chip program memory :16K byte ROM (C505(C)(A)-2R) or

32K byte ROM (C505A-4R/C505CA-4R) or

32K byte OTP (C505A-4E/C505CA-4E)

– Totally up to 64K byte internal/external program memory

– up to 64 Kbyte of external data memory

– 256 bytes of internal data memory

– Internal XRAM data memory :256 byte (C505/C505C)

1K byte (C505A/C505CA)

– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C505 versions.

Alternatively

FFFF

H

Internal

XRAM

See table below

for detailed

Data Memory

partitioning

Ext.

Data

Memory

Unused

Area

Int. CAN

Contr.

(256 Byte)

Ext.

F700

H

F6FF

H

Indirect

Addr.

Direct

Addr.

4000

8000

/

H

FF

80

H

Special

Function

Regs.

3FFF

7FFF

/

H

Internal

RAM

Ext.

Data

Memory

80

Int.

(EA = 1)

Ext.

(EA = 0)

7F

H

Internal

RAM

0000

00

H

"Code Space"

"Data Space" F700_Hto FFFF_H:

"Data Space"

"Internal Data Space"

MCB03632

Device

C505

CAN Area

Unused Area

F700_HFEFF_H

F800_HFEFF_H

F700_HFBFF_H

F800_HFBFF_H

XRAM Area

FF00_HFFFF_H

FC00_HFFFF_H

F700_HF7FF_H

C505C

C505A

C505CA

Figure 5

C505 Memory Map Memory Map

Data Sheet

13

12.00

C505/C505C/C505A/C505CA

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the

RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the

oscillator is running. A pulldown resistor is internally connected to V_SSto allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when V_DDis applied by connecting

the RESET pin to V_DDvia a capacitor. Figure 6 shows the possible reset circuitries.

a)

b)

C505

C505C

C505A

C505CA

C505

C505C

C505A

C505CA

V_DD

+

RESET

&

c)

C505

C505C

C505A

C505CA

V_DD

+

RESET

Figure 6

Reset Circuitries

Data Sheet

14

12.00

C505/C505C/C505A/C505CA

Figure 7 shows the recommended oscillator circuits for crystal and external clock operation.

C

XTAL2

C505

C505C

C505A

C505CA

2-20

MHz

C

XTAL1

C = 20pF ± 10pF for crystal operation

C = 20 pF ± 10pF for crystal operation

XTAL2

C505

N.C.

V_DD

C505C

C505A

C505CA

External

Clock

XTAL1

Signal

Figure 7

Recommended Oscillator Circuitries

Data Sheet

15

12.00

C505/C505C/C505A/C505CA

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit

datapointers instead of only one datapointer. The instruction set uses just one of these datapointers

at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL.

Figure 8 illustrates the datapointer addressing mechanism.

- - - - - .2 .1 .0

DPSEL(92

)

H

DPTR7

DPTR0

DPSEL

Selected

Data-

pointer

.2

.1

.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DPTR 0

DPTR 1

DPTR 2

DPTR 3

DPTR 4

DPTR 5

DPTR 6

DPTR 7

DPH(83

)

DPL(82 )

H

External Data Memory

MCD00779

Figure 8

External Data Memory Addressing using Multiple Datapointers

Data Sheet

16

12.00

C505/C505C/C505A/C505CA

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative

way to control the execution of C500 MCUs and to gain extensive information on the internal

operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.

Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation

and production chips are identical.

The Enhanced Hooks Technology^TM¹⁾, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces

costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate

all operating modes of the different versions of the C500 microcontrollers. This includes emulation

of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in

single step mode and to read the SFRs after a break.

ICE-System Interface

to Emulation Hardware

RESET

SYSCON

PCON

RSYSCON

RPCON

EA

ALE

EH-IC

TCON

RTCON

PSEN

C500

MCU

Enhanced Hooks

Interface Circuit

Port 0

Port 2

Optional

I/O Ports

Port 3 Port 1

RPort 2 RPort 0

TEA TALE TPSEN

MCS02647

Target System Interface

Figure 9

Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks

Emulation Concept to control the operation of the device during emulation and to transfer

informations about the programm execution and data transfer between the external emulation

hardware (ICE-system) and the C500 MCU.

1)

“Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Infineon

Technologies.

Data Sheet

17

12.00

C505/C505C/C505A/C505CA

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in

the special function register area. The special function register area consists of two portions : the

standard special function register area and the mapped special function register area. Five special

function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special

function register area. For accessing the mapped special function register area, bit RMAP in special

function register SYSCON must be set. All other special function registers are located in the

standard special function register area which is accessed when RMAP is cleared (“0“).

The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data

memory area at addresses F700 to F7FF ..

H

Special Function Register SYSCON (Address B1 )

H

(C505CA only)

Reset Value : XX100X01

Reset Value : XX100001

B

Bit No. MSB

LSB

0

7

6

–

5

4

3

2

1

CSWO

XMAP1 XMAP0

1)

–

B1

EALE RMAP CMOD

SYSCON

H

The functions of the shaded bits are not described here.

1) This bit is only available in the C505CA.

Bit

Function

RMAP

Special function register map bit

RMAP = 0 : The access to the non-mapped (standard) special function register

area is enabled.

RMAP = 1 : The access to the mapped special function register area is enabled.

CSWO

CAN Controller switch-off bit

CSWO = 0 : CAN Controller is enabled (default after reset).

CSWO = 1 : CAN Controller is switched off.

As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not

cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,

the bit RMAP must be cleared/set respectively by software.

All SFRs with addresses where address bits 0-2 are 0 (e.g. 80 , 88 , 90 , 98 , ..., F8 , FF ) are

H

bitaddressable.

The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers

and registers that provide an interface between the CPU and the other on-chip peripherals. The

SFRs of the C505 are listed in Table 3 and Table 4. In Table 3 they are organized in groups which

refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA

only) are also included in Table 3. Table 4 illustrates the contents of the SFRs in numeric order of

their addresses. Table 5 list the CAN-SFRs in numeric order of their addresses.

Data Sheet

18

12.00

C505/C505C/C505A/C505CA

Table 3

Special Function Registers - Functional Blocks

Block

Symbol

Name

Address Contents after

Reset

1)

CPU

ACC

B

Accumulator

B-Register

E0

F0

83

82

92

00

H

1)

H

DPH

DPL

DPSEL

PSW

SP

Data Pointer, High Byte

Data Pointer, Low Byte

Data Pointer Select Register

Program Status Word Register

Stack Pointer

3)

XXXXX000

00

07

H

XX100X01

XX100001

C5

B

1)

D0

H

81

B1

H

SYSCON²⁾System Control Register

3) 6)

3) 7)

H

B

4)

VR0

VR1

VR2 ⁴⁾

Version Register 0

Version Register 1

Version Register 2

FC

FD

FE

H

4)

05

H

5)

1)

3)

A/D-

ADCON0²⁾A/D Converter Control Register 0

D8

DC

D9

DA

D9

00X00000

01XXX000

00

XX

00

H

B

Converter ADCON1 A/D Converter Control Register 1

H

ADDAT

ADST

ADDATH

A/D Converter Data Reg. (C505/C505C)

A/D Converter Start Reg. (C505/C505C)

A/D Converter High Byte Data Register

(C505A/C505CA)

A/D Converter Low Byte Data Register

(C505A/C505CA)

H

3)

ADDATL

DA

00XXXXXX

H

B

P1ANA ^{2) 4)}Port 1 Analog Input Selection Register

90

FF

H

00

H

1)

Interrupt

System

IEN0 ²⁾

IEN1 ²⁾

IP0 ²⁾

IP1

TCON

T2CON

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

Interrupt Priority Register 1

Timer Control Register

Timer 2 Control Register

Serial Channel Control Register

Interrupt Request Control Register

A8

B8

A9

H

00

H

00

H

3)

B9

XX000000

B

2)

1)

88

00

H

2)

1)

C8

00X00000

00

H

B

2)

1)

SCON

IRCON

98

C0

H

XRAM

XPAGE

Page Address Register for Extended on-chip 91

XRAM and CAN Controller

00

H

SYSCON²⁾System Control Register

B1

XX100X01

XX100001

3) 6)

3) 7)

H

B

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

5) The content of this SFR varies with the actual step of the C505 (eg. 01 for the first step)

H

6) C505 / C505A/C505C only

7) C505CA only

Data Sheet

19

12.00

C505/C505C/C505A/C505CA

Table 3

Special Function Registers - Functional Blocks (cont’d)

Block

Symbol

Name

Address Contents after

Reset

1)

Ports

P0

P1

Port 0

Port 1

80

90

A0

B0

FF

H

1)

P1ANA ^{2) 4)}Port 1 Analog Input Selection Register

1)

P2

P3

P4

Port 2

Port 3

Port 4

1)

E8H ¹⁾

XXXXXX11

B

1)

3)

Serial

Channel

ADCON0²⁾A/D Converter Control Register 0

D8

00X00000

H

B

PCON ²⁾

SBUF

Power Control Register

Serial Channel Buffer Register

87

H

00

XX

00

H

3)

99

H

1)

98

SCON

SRELL

SRELH

Serial Channel Control Register

Serial Channel Reload Register, low byte

Serial Channel Reload Register, high byte

H

AA

H

D9

3)

BA

H

XXXXXX11

B

1)

Timer 0/

Timer 1

TCON

TH0

TH1

Timer 0/1 Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

88

00

H

8C

H

00

H

8D

H

00

H

TL0

8A

H

00

H

TL1

Timer 1, Low Byte

8B

H

00

H

TMOD

Timer Mode Register

89

00

H

3)

Compare/ CCEN

Capture

Unit /

Comp./Capture Enable Reg.

Comp./Capture Reg. 1, High Byte

Comp./Capture Reg. 2, High Byte

Comp./Capture Reg. 3, High Byte

Comp./Capture Reg. 1, Low Byte

Comp./Capture Reg. 2, Low Byte

Comp./Capture Reg. 3, Low Byte

Reload Register High Byte

Reload Register Low Byte

Timer 2, High Byte

C1

H

00

H

CCH1

CCH2

CCH3

CCL1

CCL2

CCL3

CRCH

CRCL

TH2

C3

H

00

H

C5

H

00

H

Timer 2

C7

H

00

H

C2

H

00

H

C4

H

00

H

C6

H

00

H

CB

H

00

H

CA

H

00

H

CD

H

00

H

TL2

Timer 2, Low Byte

CC

00

H

1)

C8

3)

T2CON

IEN0 ²⁾

IEN1 ²⁾

Timer 2 Control Register

Interrupt Enable Register 0

Interrupt Enable Register 1

00X00000

B

1)

A8

00

H

1)

B8

00

H

Watchdog WDTREL Watchdog Timer Reload Register

86

00

H

IEN0 ²⁾

IEN1 ²⁾

IP0 ²⁾

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

00

H

1)

A8

1)

B8

A9

00

H

00

H

Pow.Save PCON ²⁾

Modes

Power Control Register

87

H

00

H

0XX0XXXX

PCON1 ⁴⁾Power Control Register 1

1)

88

3)

H

B

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Data Sheet

20

12.00

C505/C505C/C505A/C505CA

Table 3

Special Function Registers - Functional Blocks (cont’d)

Block

Symbol

Name

Address Contents after

Reset

CAN

Controller SR

IR

(C505C/

C505CA BTR1

CR

Control Register

Status Register

Interrupt Register

Bit Timing Register Low

F700

F701

F702

F704

F705

F706

F707

F708

F709

01

XX

UU

0UUUUUUU

H

3)

BTR0

H

3)

Bit Timing Register High

B

3)

only)

GMS0

GMS1

Global Mask Short Register Low

Global Mask Short Register High

Upper Global Mask Long Register Low

Upper Global Mask Long Register High

Lower Global Mask Long Register Low

Lower Global Mask Long Register High

Upper Mask of Last Message Register Low F70C

Upper Mask of Last Message Register High F70D

Lower Mask of Last Message Register Low F70E

UU

H

3)

UUU11111_B

3)

UU

UGML0

UGML1

LGML0

LGML1

UMLM0

UMLM1

LMLM0

LMLM1

H

3)

UU

3)

F70A

F70B

UU

3)

UUUUU000_B

3)

UU

H

3)

UU

3)

UU

H

Lower Mask of Last Message Register High F70F

Message Object Registers :

UUUUU000_B

5)

3)

UU

MCR0

MCR1

UAR0

UAR1

LAR0

LAR1

MCFG

DB0

DB1

DB2

DB3

DB4

Message Control Register Low

Message Control Register High

Upper Arbitration Register Low

Upper Arbitration Register High

Lower Arbitration Register Low

Lower Arbitration Register High

Message Configuration Register

Message Data Byte 0

Message Data Byte 1

Message Data Byte 2

Message Data Byte 3

Message Data Byte 4

F7n0

F7n1

F7n2

F7n3

F7n4

F7n5

F7n6

F7n7

F7n8

F7n9

H

3)

UU

3)

UU

3)

UU

3)

UU

H

3)

UUUUU000_B

UUUUUU00_B

3)

XX

H

3)

XX

3)

XX

3)

XX

F7nA

F7nB

H

3)

XX

3)

XX

DB5

DB6

DB7

Message Data Byte 5

Message Data Byte 6

Message Data Byte 7

F7nC

F7nD

F7nE

3)

XX

3)

XX

H

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by

a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

5) The notation “n“ (n= 1 to F) in the message object address definition defines the number of the related

message object.

Data Sheet

21

12.00

C505/C505C/C505A/C505CA

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses

Addr Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

after

Reset¹⁾

2)

80

81

82

83

86

P0

FF

07

.7

.6

.5

.4

.3

.2

.1

.0

H

SP

H

DPL

DPH

00

WDTREL 00

WDT

PSEL

87

88

PCON

TCON

00

SMOD PDS

TF1 TR1

IDLS

TF0

–

SD

GF1

IE1

–

GF0

IT1

–

PDE

IE0

–

IDLE

IT0

–

H

2)

3)

TR0

WS

PCON1 0XX0-

XXXX

EWPD –

B

89

TMOD

TL0

00

GATE C/T

M1

.5

M0

.4

GATE C/T

M1

.1

M0

.0

H

8A

8B

.7

T2

.6

.3

.2

H

TL1

.5

.4

.3

.2

.1

.0

8C

8D

90

TH0

TH1

P1

.5

.4

.3

.2

.1

.0

H

.5

.4

.3

.2

.1

.0

2)

FF

CLK-

OUT

T2EX .4

INT6

INT5

INT4

.INT3

H

3)

90

91

92

P1ANA FF

XPAGE 00

EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0

H

.7

–

.6

–

.5

–

.4

–

.3

–

.2

.1

.0

H

DPSEL XXXX-

X000

B

2)

98

99

SCON

SBUF

P2

00

SM0

.7

SM1

.6

SM2

.5

REN

.4

TB8

.3

RB8

.2

TI

RI

.0

H

XX

FF

.1

H

2)

A0

A8

A9

.7

.6

.5

.4

.3

.2

.1

.0

H

IEN0

IP0

00

EA

WDT

ET2

ES

.4

ET1

.3

EX1

.2

ET0

.1

EX0

.0

OWDS WDTS .5

.7 .6 .5

AA

SRELL

D9

.4

.3

.2

.1

.0

H

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Data Sheet

22

12.00

C505/C505C/C505A/C505CA

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

after

Reset¹⁾

2)

H

B0

B1

P3

FF

RD

–

WR

–

T1

T0

INT1

INT0

TxD

RxD

H

SYSCON XX10-

3)

EALE RMAP CMOD –

XMAP1 XMAP0

H

0X01

B

B1

SYSCON XX10-

–

EALE RMAP CMOD CSWO XMAP1 XMAP0

H

4)

0001

B

2)

B8

B9

IEN1

IP1

00

EXEN2 SWDT EX6

EX5

.4

EX4

.3

EX3

.2

ECAN EADC

H

XX00-

–

.5

.1

.0

0000

B

BA

SRELH XXXX-

–

.1

.0

H

XX11

B

2)

C0

IRCON

CCEN

00

EXF2 TF2

IEX6

IEX5

IEX4

IEX3

SWI

IADC

H

C1

COCA COCAL COCA COCAL COCA COCAL COCA COCAL

H

H3

.7

3

H2

.5

–

2

H1

.3

1

H0

.1

0

C2

C3

C4

C5

C6

C7

C8

CCL1

CCH1

CCL2

CCH2

CCL3

CCH3

00

.6

.4

.2

.0

H

.0

2)

T2CON 00X0-

0000

T2PS I3FR

T2R1 T2R0 T2CM T2I1

T2I0

B

CA

CB

CRCL

CRCH

TL2

00

.7

.6

.5

F0

–

.4

.3

.2

.1

.0

H

.7

.6

.4

.3

.2

.1

.0

H

CC

CD

D0

.7

.6

.4

.3

.2

.1

.0

H

TH2

.7

.6

.4

.3

.2

.1

.0

2)

PSW

CY

BD

AC

CLK

RS1

BSY

RS0

ADM

OV

MX2

F1

MX1

P

H

2)

D8

ADCON0 00X0-

0000

MX0

B

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) C505 /C505C/C505A only

4) C505CA only

Data Sheet

23

12.00

C505/C505C/C505A/C505CA

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

Addr Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

after

Reset¹⁾

D9

ADDAT ⁶⁾00

.7

.9

.6

.8

.5

.7

.4

.6

.3

.5

.2

.4

.1

.3

.0

.2

H

ADDATH 00

7)

6)

DA

ADST

XXXX-

XXXX

–

H

B

ADDATL 00XX-

.1

.0

–

7)

XXXX

B

DC

ADCON1 01XX-

X000

ADCL1 ADCL0 –

MX2

MX1

MX0

H

B

2)

E0

ACC

P4

00

.7

–

.6

–

.5

–

.4

–

.3

–

.2

–

.1

.0

H

2)

H

E8

F0

XXXX-

XX11

RXDC TXDC

B

2)

B

00

H

.7

1

.6

1

.5

0

.4

0

.3

0

.2

1

.1

0

.0

1

H

3)4)

FC

FD

FE

VR0

VR1

VR2 ⁵⁾

C5

H

3)4)

H

05

H

0

1

0

1

8)

3)4)

H

01

.7

.6

.5

.4

.3

.2

.1

.0

H₉₎

12

H₁₀₎

33

H

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

4) These are read-only registers

5) The content of this SFR varies with the actual of the step C505 (eg. 01 or 11 or 21 for the first step)

H

6) C505 / C505C only

7) C505A / C505CA only

8) C505 / C505C AB step only

9) C505A-4E / C505CA-4E BA step only (11 for the AA step)

H

10) C505A-4R / C505CA-4R BB step only (32 for the BA step)

H

Data Sheet

24

12.00

C505/C505C/C505A/C505CA

Table 5

Contents of the CAN Registers in numeric order of their addresses

(C505C/C505CA only)

Addr.

Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

n=1-F

1)

after

H

Reset ²⁾

F700

CR

01

TEST CCE

0

EIE

SIE

IE

INIT

H

F701

F702

F704

F705

SR

XX

BOFF EWRN –

RXOK TXOK LEC2 LEC1 LEC0

H

IR

XX

INTID

BRP

H

BTR0

BTR1

UU

SJW

H

0UUU.

UUUU

0

TSEG2

TSEG1

B

F706

F707

GMS0

GMS1

UU

ID28-21

H

UUU1.

1111

ID20-18

1

0

1

0

1

0

B

F708

F709

UGML0 UU

UGML1 UU

LGML0 UU

ID28-21

ID20-13

ID12-5

H

F70A

F70B

H

LGML1 UUUU.

ID4-0

U000

B

F70C

F70D

F70E

UMLM0 UU

H

ID28-21

ID12-5

H

UMLM1 UU

H

ID20-18

ID17-13

0

LMLM0 UU

H

F70F

LMLM1 UUUU.

U000

B

F7n0

MCR0

MCR1

UU

MSGVAL

RMTPND

TXIE

RXIE

INTPND

H

F7n1

TXRQ

MSGLST

CPUUPD

NEWDAT

F7n2

F7n3

F7n4

F7n5

UAR0

UAR1

LAR0

LAR1

UU

ID28-21

H

ID20-18

ID17-13

ID12-5

UUUU.

U000

ID4-0

0

B

1) The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object.

2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged

by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation

Data Sheet

25

12.00

C505/C505C/C505A/C505CA

Table 5

Contents of the CAN Registers in numeric order of their addresses (cont’d)

(C505C/C505CA only)

Addr.

Register Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

n=1-F

1)

after

H

Reset ²⁾

F7n6

MCFG

UUUU.

DLC

DIR

XTD

0

H

UU00

B

F7n7

F7n8

F7n9

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

XX

H

.7

.6

.5

.4

.3

.2

.1

.0

H

XX

H

XX

H

F7nA

F7nB

XX

H

XX

H

F7nC

F7nD

F7nE

XX

H

XX

H

XX

H

1) The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object.

2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged

by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation

Data Sheet

26

12.00

C505/C505C/C505A/C505CA

I/O Ports

The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O

port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means,

when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally

pulled low. Port 0 will float when configured as input.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external

memory. In this application, port 0 outputs the low byte of the external memory address, time

multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory

address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR

contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET .

Port 4 is 2-bit I/O port with CAN controller specific alternate functions. The eight analog input lines

are realized as mixed digital/analog inputs. The 8 analog inputs, AN0-AN7, are located at the port

1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are

configured as digital inputs. The analog function of a specific port 1 pin is enabled by bits in the SFR

P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog

input.

Note : P1ANA is a mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set.

Data Sheet

27

12.00

C505/C505C/C505A/C505CA

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 6 :

Table 6

Timer/Counter 0 and 1 Operating Modes

Mode Description

TMOD

Input Clock

external (max)

_OSC/12x32

M1

M0

internal

_OSC/6x32

0

8-bit timer/counter with a

0

f

divide-by-32 prescaler

1

2

16-bit timer/counter

0

1

0

8-bit timer/counter with

8-bit autoreload

f_OSC/6

f_OSC/12

3

Timer/counter 0 used as one

8-bit timer/counter and one

8-bit timer

1

Timer 1 stops

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the

count rate is f_OSC/6.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a

falling edge the max. count rate is f_OSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the

input clock logic.

÷

6

f _OSC/6

OSC

C/T = 0

C/T = 1

Timer 0/1

Input Clock

P3.4/T0

P3.5/T1

Control

TR0

TR1

&

=1

Gate

(TMOD)

_

<

1

P3.2/INT0

P3.3/INT1

MCS03117

Figure 10

Timer/Counter 0 and 1 Input Clock Logic

Data Sheet

28

12.00

C505/C505C/C505A/C505CA

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C505 provides additional compare/capture/reload features. which allow the

selection of the following operating modes:

– Compare : up to 4 PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock)

– Capture

– Reload

: up to 4 high speed capture inputs with 300 ns resolution

: modulation of timer 2 cycle time

The block diagram in Figure 11 shows the general configuration of timer 2 with the additional

compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as

multifunctional port functions at port 1.

P1.5/

T2EX

_

<

1

Sync.

÷6

EXF2

Interrupt

Request

T2I0

T2I1

EXEN2

Reload

P1.7/

T2

&

Reload

f _OSC

OSC

÷12

Timer 2

TL2 TH2

T2PS

TF2

Compare

P1.0/

INT3/

CC0

P1.1/

INT4/

CC1

16 Bit

Comparator

16 Bit

Comparator

16 Bit

Comparator

16 Bit

Comparator

Input/

Output

Control

P1.2/

INT5/

CC2

Capture

P1.2/

INT6/

CC3

CCL3/CCH3

CCL2/CCH2

CCL1/CCH1

CRCL/CRCH

MCB02730

Figure 11

Timer 2 Block Diagram

Data Sheet

29

12.00

C505/C505C/C505A/C505CA

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A

roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR

IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer

2 operation.

Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler

offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency.

Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to

the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the

counting procedure. This facilitates pulse width measurements. The external gate signal is sampled

once every machine cycle.

Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1-

to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is

sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize

a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no

restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled

at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2 : Two reload modes are selectable:

In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer

2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.

In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-

ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been

set.

Data Sheet

30

12.00

C505/C505C/C505A/C505CA

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored

in a compare or compare/capture register is compared with the contents of the timer register; if the

count value in the timer register matches the stored value, an appropriate output signal is generated

at a corresponding port pin and an interrupt can be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal

changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode

0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port

will have no effect. Figure 12 shows a functional diagram of a port circuit when used in compare

mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The

input line from the internal bus and the write-to-latch line of the port latch are disconnected when

compare mode 0 is enabled.

Port Circuit

Read Latch

V_DD

Compare Register

Circuit

Compare Reg.

S

Q

Port

Internal

Bus

16 Bit

Comparator

D

Port

Latch

Write to

Latch

Compare

Match

CLK

16 Bit

Timer Register

Timer Circuit

R

Timer

Overflow

Read Pin

MCS02661

Figure 12

Port Latch in Compare Mode 0

Data Sheet

31

12.00

C505/C505C/C505A/C505CA

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be

choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the

actual pin-level) or should keep its old value at the time when the timer value matches the stored

compare value.

In compare mode 1 (see Figure 13) the port circuit consists of two separate latches. One latch

(which acts as a "shadow latch") can be written under software control, but its value will only be

transferred to the port latch (and thus to the port pin) when a compare match occurs.

Port Circuit

Read Latch

V_DD

Compare Register

Circuit

Compare Reg.

Internal

Bus

D

Q

D

Q

Port

16 Bit

Comparator

Shadow

Latch

Port

Latch

Compare

Match

Write to

Latch

CLK

16 Bit

Timer Register

Timer Circuit

Read Pin

MCS02662

Figure 13

Compare Function in Compare Mode 1

Timer 2 Capture Modes

Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the

current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this

function.

In mode 0, the external event causing a capture is :

– for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1

– for the CRC register:

a positive or negative transition at the corresponding pin, depending

on the status of the bit I3FR in SFR T2CON.

In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture

register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2

contents will be latched into the appropriate capture register in the cycle following the write

instruction. In this mode no interrupt request will be generated.

Data Sheet

32

12.00

C505/C505C/C505A/C505CA

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three

asynchronous modes) as illustrated in Table 7.

Table 7

USART Operating Modes

SCON

Description

Mode

SM0

SM1

0

Shift register mode, fixed baud rate

Serial data enters and exits through R×D; T×D outputs the shift

clock; 8-bit are transmitted/received (LSB first)

1

2

3

0

1

0

1

8-bit UART, variable baud rate

10 bits are transmitted (through T×D) or received (at R×D)

9-bit UART, fixed baud rate

11 bits are transmitted (through T×D) or received (at R×D)

9-bit UART, variable baud rate

Like mode 2

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"

should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is

16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have

to provide a "baud rate clock" (output signal in Figure 14 to the serial interface which - there divided

by 16 - results in the actual "baud rate". Further, the abbrevation f_OSCrefers to the oscillator

frequency (crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1

or from a decdicated baud rate generator (see Figure 14).

Data Sheet

33

12.00

C505/C505C/C505A/C505CA

Timer 1

Overflow

SCON.7

SCON.6

(SM0/

ADCON0.7

(BD)

PCON.7

Baud

Rate

Generator

Mode 1

Mode 3

(SMOD)

SM1)

0

1

÷2

0

f _OSC

Baud

Rate

1

(SRELH

SRELL)

Clock

Mode 2

Mode 0

Only one mode

can be selected

÷6

Note: The switch configuration shows the reset state.

MCS02733

Figure 14

Block Diagram of Baud Rate Generation for the Serial Interface

Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its

dependencies of the control bits BD and SMOD.

Table 8

Serial Interface - Baud Rate Dependencies

Serial Interface

Active Control Bits Baud Rate Calculation

Operating Modes

BD

–

SMOD

Mode 0 (Shift Register)

–

f_OSC/ 6

Mode 1 (8-bit UART)

Mode 3 (9-bit UART)

0

X

Controlled by timer 1 overflow :

(2^SMOD× timer 1 overflow rate) / 32

1

–

X

Controlled by baud rate generator

(2^SMOD× f_OSC) /

(32 × baud rate generator overflow rate)

Mode 2 (9-bit UART)

0

1

f

_OSC/ 32

_OSC/ 16

Data Sheet

34

12.00

C505/C505C/C505A/C505CA

CAN Controller (C505C and C505CA only)

The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all

resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the

extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the

CPU of as much overhead as possible when controlling many different message objects (up to 15).

This includes bus arbitration, resending of garbled messages, error handling, interrupt generation,

etc. In order to implement the physical layer, external components have to be connected to the

C505C/C505CA.

The internal bus interface connects the on-chip CAN controller to the internal bus of the

microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256

byte wide address range of the external data memory area (F700 to F7FF ) and can be accessed

H

using MOVX instructions. Figure 15 shows a block diagram of the on-chip CAN controller.

The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel

access to the whole data or remote frame for the acceptance match test and the parallel transfer of

the frame to and from the Intelligent Memory.

The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between

the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and

the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the

processes of reception, arbitration, transmission, and error signalling are performed according to

the CAN protocol. Note that the automatic retransmission of messages which have been corrupted

by noise or other external error conditions on the bus line is handled by the BSP.

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to

be transmitted after the data bytes and checks the CRC code of incoming messages. This is done

by dividing the data stream by the code generator polynomial.

The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its

counters, the Receive Error Counter and the Transmit Error Counter, are incremented and

decremented by commands from the Bit Stream Processor. According to the values of the error

counters, the CAN controller is set into the states error active, error passive and busoff.

The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit

timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant busline

transition at Start of Frame (hard synchronization) and on any further recessive to dominant busline

transition, if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL

also provides programmable time segments to compensate for the propagation delay time and for

phase shifts and to define the position of the Sample Point in the bit time. The programming of the

BTL depends on the baudrate and on external physical delay times.

The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of

maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of

control and status bits. After the initial configuration, the Intelligent Memory can handle the

reception and transmission of data without further microcontroller actions.

Data Sheet

35

12.00

C505/C505C/C505A/C505CA

TXDC

RXDC

Bit

Timing

Logic

BTL-Configuration

CRC

Gen./Check

Timing

Generator

TX/RX Shift Register

Messages

Clocks

(to all)

Control

Messages

Handlers

Intelligent

Memory

Interrupt

Register

Status +

Control

Bit

Stream

Processor

Error

Management

Logic

Status

Register

to internal Bus

MCB02736

Figure 15

CAN Controller Block Diagram

Data Sheet

36

12.00

C505/C505C/C505A/C505CA

CAN Controller Software Initialization

The very first step of the initialization is the CAN controller input clock selection. A divide-by-2

prescaler is enabled by default after reset (Figure 16). Setting bit CMOD (SYSCON.3) disables the

prescaler. The purpose of the prescaler selection is:

– to ensure that the CAN controller is operable when f

– to achieve the maximum CAN baudrate of 1 Mbaud when f

is over 10 MHz (bit CMOD =0)

osc

is 8 MHz (bit CMOD=1)

osc

SYSCON.3

(CMOD)

f

OSC

1

0

f

CAN

Full-CAN

Module

2

MCS03296

Condition: CMOD = 0, when f

> 10 MHz

OSC

Frequency (MHz)

CMOD

BRP

CAN

(SYSCON.3) (BTR0.0-5)

baudrate

(Mbaud/sec)

f

CAN

OSC

8

4

8

1

0

000000

1

0.5

1

B

16

Note : The switch configuration shows the reset state of bit CMOD.

Figure 16

CAN controller Input Clock Selection

Data Sheet

37

12.00

C505/C505C/C505A/C505CA

8-Bit A/D Converter (C505 and C505C only)

The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog

input channels. It operates with a successive approximation technique and provides the following

features:

– 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs

– 8-bit resolution

– Internal start-of-conversion trigger

– Interrupt request generation after each conversion

– Single or continuous conversion mode

The 8-bit ADC uses two clock signals for operation : the conversion clock f

(=1/t

) and the

ADC

input clock f (1/t ). f

is derived from the C505 system clock f

which is applied at the XTAL

IN

IN ADC

OSC

pins via the ADC clock prescaler as shown in Figure 17. The input clock is equal to f

. The

OSC

conversion clock f

is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock

ADC

prescaler must be programmed to a value which assures that the conversion clock does not exceed

1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.

ADCL1

ADCL0

f

OSC

32

16

8

f

Conversion Clock

ADC

MUX

A / D

Converter

4

Input Clock

1

f

Clock Prescaler

IN

Condition: f

< 1.25 MHz

f

= f

=

OSC

ADC max

IN

CLP

MCS03299

MCUSystemClock f

Prescaler

Ratio

f

ADCL1

ADCL0

IN

ADC

Rate (f

)

[MHz]

OSC

2 MHz

2

÷ 4

0.5

0

1

0

1

0

5 MHz

5

÷ 4

1.25

0.75

1.25

0.75

1

6 MHz

6

÷ 8

10 MHz

12 MHz

16 MHz

20 MHz

10

12

16

20

÷ 8

÷ 16

1.25

Figure 17

8-Bit A/D Converter Clock Selection

Data Sheet

38

12.00

C505/C505C/C505A/C505CA

Internal

Bus

IEN1 (B8

EXEN2

)

H

SWDT

EX6

IEX6

EAN5

EX5

IEX5

EAN4

EX4

IEX4

EAN3

EX3

IEX3

EAN2

MX2

ECAN

SWI

EADC

IADC

EAN0

MX0

IRCON (C0

EXF2

)

H

TF2

P1ANA (90

)

H

EAN7

EAN6

EAN1

MX1

ADCON1 (DC

ADCL1

)

H

ADCL0

ADCON0 (D8

BD

)

H

CLK

BSY

ADM

MX2

MX1

MX0

ADDAT ADST

Single /

Continuous Mode

(D9

)

(DA )

H

Port 1

LSB

.1

MUX

S&H

.2

.3

Conversion

Clock

Prescaler

f

Conversion Clock f

Input Clock f

OSC

ADC

.4

A / D

Converter

.5

.6

IN

MSB

V

AREF

AGND

Start of

conversion

Internal

Bus

Write to ADST

Shaded Bit locations are not used in ADC-functions.

MCB03298

Figure 18

Block Diagram of the 8-Bit A/D Converter

Data Sheet

39

12.00

C505/C505C/C505A/C505CA

10-Bit A/D Converter (C505A and C505CA only)

The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8

analog input channels. It operates with a successive approximation technique and uses self

calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D

converter provides the following features:

– 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs

– 10-bit resolution

– Single or continuous conversion mode

– Internal start-of-conversion trigger capability

– Interrupt request generation after each conversion

– Using successive approximation conversion technique via a capacitor array

– Built-in hidden calibration of offset and linearity errors

The 10-bit ADC uses two clock signals for operation : the conversion clock f

(=1/t

) and the

ADC

input clock f (=1/t ). f

is derived from the C505 system clock f

which is applied at the

IN

IN ADC

OSC

XTAL pins. The input clock f is equal to f

The conversion f

clock is limited to a maximum

IN

OSC

ADC

frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which

assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the

bits ADCL1 and ADCL0 of SFR ADCON1.

ADCL1

ADCL0

f

OSC

32

16

8

f

Conversion Clock

ADC

MUX

A / D

Converter

4

Input Clock

1

f

Clock Prescaler

IN

Condition: f

< 2 MHz

f

= f

=

OSC

ADC max

IN

CLP

MCS03635

MCUSystemClock f

Prescaler

Ratio

f

ADCL1

ADCL0

IN

ADC

Rate (f

)

[MHz]

0.5

1.5

2

OSC

2 MHz

2

÷ 4

÷ 8

÷ 16

0

1

0

1

0

6 MHz

6

8 MHz

8

12 MHz

16 MHz

20 MHz

12

16

20

1.5

2

1.25

Figure 19

10-Bit A/D Converter Clock Selection

Data Sheet

40

12.00

C505/C505C/C505A/C505CA

Internal

Bus

IEN1 (B8

EXEN2

)

H

EADC

IADC

EAN0

MX0

SWDT

EX6

EX5

EX4

EX3

ECAN

IRCON (C0

)

H

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

SWI

P1ANA (90

)

H

EAN7

EAN6

EAN5

EAN4

EAN3

EAN2

EAN1

ADCON1 (DC

ADCL1

)

H

ADCL0

MX2

MX1

ADCON0 (D8

BD

)

H

BSY

ADM

MX0

CLK

ADDAT ADST

ADDATH ADDATL

Single /

Continuous Mode

(D9

)

(DA )

H

(D9 )

(DA )

H

Port 1

.2

.3

MUX

S&H

.4

.5

Conversion

Clock

Prescaler

f

Conversion Clock f

Input Clock f

OSC

ADC

.6

A / D

Converter

.7

.8

LSB

.1

IN

MSB

V

AREF

AGND

Start of

conversion

Internal

Bus

Write to ADDATL

Shaded Bit locations are not used in ADC-functions.

MCB03636

Figure 20

Block Diagram of the 10-Bit A/D Converter

Data Sheet

41

12.00

C505/C505C/C505A/C505CA

Interrupt System

The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be

generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One

interrupt can be generated by the CAN controller (C505C and C505CA only) or by a software setting

and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/

INT0, P3.3/INT1, P1.0/AN0/INT3/CC0, P1.1/AN1/INT4/CC1, P1.2/AN2/INT5/CC2, P1.3/AN3/INT6/

CC3). Additionally, the P1.5/AN5/T2EX can trigger an interrupt. The wake-up from power-down

mode interrupt has a special functionality which allows to exit from the software power-down mode

by a short low pulse at either pin P3.2/INT0 or the pin P4.1/RXDC.

Figure 21 to Figure 23 give a general overview of the interrupt sources and illustrate the request

and the control flags which are described in the next sections. Table 9 lists all interrupt sources with

their request flags and interrupt vector addresses.

Table 9

Interrupt Source and Vectors

Interrupt Source

External Interrupt 0

Timer 0 Overflow

External Interrupt 1

Timer 1 Overflow

Serial Channel

Interrupt Vector Address

Interrupt Request Flags

0003

H

IE0

000B

H

TF0

0013

H

IE1

001B

H

TF1

0023

H

RI / TI

TF2 / EXF2

IADC

– / SWI

IEX3

IEX4

IEX5

IEX6

–

Timer 2 Overflow / Ext. Reload

A/D Converter

002B

H

0043

H

CAN Controller / Software Interrupt 004B

H

External interrupt 3

0053

External Interrupt 4

005B

H

External Interrupt 5

0063

H

External interrupt 6

006B

H

Wake-up from power-down mode 007B

Data Sheet

42

12.00

C505/C505C/C505A/C505CA

Highest

Priority Level

P3.2 /

INT0

IE0

0003

0043

H

TCON.1

EX0

Lowest

Priority Level

IT0

IEN0.0

TCON.0

A / D Converter

IADC

IRCON.0

EADC

IEN1.0

IP1.0

IP0.0

P

o

l

i

n

g

Timer 0

Overflow

TF0

000B

004B

H

TCON.5

ET0

IEN0.1

SWI

>1

IRCON.1

S

e

q

u

e

n

c

e

ECAN

Status

Error

IEN1.1

SIE

CR.2

>1

EIE

IE

CR.3

CR.1

Message

Transmit

TXIE

INTPND

MCR0.0 / 1

MCR0.5 / 4

Message

Receive

RXIE

EA

IP1.1

IP0.1

MCR0.3 / 2

IEN0.7

Bit addressable

Request flag is cleared by hardware

C505C and C505CA Only

MCB03303

Figure 21

Interrupt Structure, Overview Part 1

Note: Each of the 15 CAN controller message objects (C505C and C505CA only), shown in the

shaded area of Figure 21 provides the bits/flags.

Data Sheet

43

12.00

C505/C505C/C505A/C505CA

Highest

Priority Level

P3.3 /

INT1

IE1

0013

0053

H

TCON.3

EX1

Lowest

Priority Level

IT1

IEN0.2

TCON.2

P

o

P1.0 /

AN0 /

IEX3

IRCON.2

EX3

l

i

INT3 /

CC0

IEN1.2

IP1.2

IP0.2

I3FR

n

g

T2CON.6

Timer 1

Overflow

S

e

q

u

e

n

c

e

TF1

001B

H

TCON.7

ET1

IEN0.3

P1.1 /

AN1 /

INT4 /

CC1

IEX4

005B

EA

IRCON.3

EX4

IEN1.3

IP1.3

IP0.3

IEN0.7

Bit addressable

Request flag is cleared by hardware

MCB03304

Figure 22

Interrupt Structure, Overview Part 2

Data Sheet

44

12.00

C505/C505C/C505A/C505CA

Highest

Priority Level

RI

>1

SCON.0

USART

0023

0063

H

ES

TI

Lowest

Priority Level

IEN0.4

SCON.1

P1.2 /

AN2 /

INT5 /

CC2

P

o

l

i

n

g

IEX5

IRCON.4

EX5

IEN1.4

IP1.4

IP0.4

Timer 2

Overflow

TF2

IRCON.6

>1

S

e

q

u

e

n

c

e

P1.5 /

AN5 /

T2EX

002B

H

EXF2

ET2

EXEN2

IEN1.7

IRCON.7

IEN0.5

P1.3 /

INT6 /

CC3

IEX6

IRCON.5

006B

EA

EX6

IEN1.5

IP1.5

IP0.5

IEN0.7

Bit addressable

Request flag is cleared by hardware

MCB03305

Figure 23

Interrupt Structure, Overview Part 3

Data Sheet

45

12.00

C505/C505C/C505A/C505CA

Fail Save Mechanisms

The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software

upset or hardware failure :

– a programmable watchdog timer (WDT), with variable time-out period from 192 µs up to

approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).

– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for

a fast internal reset after power-on.

The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of f_OSC/12

upto f_OSC/192. The system clock of the C505 is divided by two prescalers, a divide-by-two and a

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the

watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.

0

7

8

f

/ 6

OSC

2

16

WDTL

14

WDT Reset - Request

WDTH

IP0 (A9

)

H

WDTPSEL

OWDS WDTS

External HW Reset

7

6

0

WDTREL (86

)

H

Control Logic

IEN0 (A8

IEN1 (B8

)

WDT

H

SWDT

MCB03306

Figure 24

Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped

during active mode of the device. If the software fails to refresh the running watchdog timer an

internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the

content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh

sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The

reset cause (external reset or reset caused by the watchdog) can be examined by software (flag

WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and

power down mode of the processor.

Data Sheet

46

12.00

C505/C505C/C505A/C505CA

Oscillator Watchdog

The oscillator watchdog unit serves for three functions:

– Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency

of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC

oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-

chip oscillator has a higher frequency than the RC oscillator), the part, in order to allow the

oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog

reset is released and the part starts program execution from address 0000 again.

H

– Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator

has started. The oscillator watchdog unit also works identically to the monitoring function.

– Control of external wake-up from software power-down mode

When the power-down mode is left by a low level at the P3.2/INT0 pin or the P4.1/RXDC pin,

the oscillator watchdog unit assures that the microcontroller resumes operation (execution of

the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the

RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when

power-down mode is released. When the on-chip oscillator has a higher frequency than the

RC oscillator, the microcontroller starts program execution by processing a power down

interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.

Data Sheet

47

12.00

C505/C505C/C505A/C505CA

EWPD

(PCON1.7)

WS

(PCON1.4)

Power - Down

Mode Activated

Power-Down Mode

Wake - Up Interrupt

P4.1 / RXDC

Control

Logic

Control

Logic

P3.2 / INT0

Internal Reset

Start /

Stop

RC

Oscillator

f

RC

1

10

3 MHz

<

f

1

2

Frequency

Comparator

>1

Delay

Start /

Stop

f

2

XTAL1

XTAL2

On-Chip

Oscillator

IP0 (A9

)

H

OWDS

Int. Clock

MCB03308

Figure 25

Functional Block Diagram of the Oscillator Watchdog

Data Sheet

48

12.00

C505/C505C/C505A/C505CA

Power Saving Modes

The C505 provides two basic power saving modes, the idle mode and the power down mode.

Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate

in normal operating mode and it can be also used for further power reduction in idle mode.

– Idle mode

In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from

the clock signal. All peripheral units are further provided with the clock. The CPU status is

preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a

peripheral unit or by a hardware reset.

– Power down mode

The operation of the C505 is completely stopped and the oscillator is turned off. This mode is

used to save the contents of the internal RAM with a very low standby current. Power down

mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/

INT0.or P4.1/RXDC.

– Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is

internally divided by 32. This slows down all parts of the controller, the CPU and all

peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency

significantly reduces power consumption.

In the power down mode of operation, V_DDcan be reduced to minimize power consumption. It must

be ensured, however, that V_DDis not reduced before the power down mode is invoked, and that V_DD

is restored to its normal operating level, before the power down mode is terminated. Table 10 gives

a general overview of the entry and exit procedures of the power saving modes.

Table 10

Power Saving Modes Overview

Mode

Entering

Leaving by

Remarks

(Instruction

Example)

Idle Mode

ORL PCON, #01H Ocurrence of an

ORL PCON, #20H interrupt from a

peripheral unit

CPU clock is stopped;

CPU maintains their data;

peripheral units are active (if

enabled) and provided with

clock

Hardware Reset

Power Down Mode ORL PCON, #02H Hardware Reset

Oscillator is stopped;

ORL PCON, #40H

contents of on-chip RAM and

SFR’s are maintained;

Short low pulse at

pin P3.2/INT0 or

P4.1/RXDC

Slow Down Mode

ORL PCON,#10H

ANL PCON,#0EFH

or

Hardware Reset

Oscillator frequency is

reduced to 1/32 of its nominal

frequency

Data Sheet

49

12.00

C505/C505C/C505A/C505CA

OTP Memory Operation (C505A-4E and C505CA-4E only)

The C505A-4E/C505CA-4E contains a 32K byte one-time programmable (OTP) program memory.

With the C505A-4E/C505CA-4E fast programming cycles are achieved (1 byte in 100 µsec). Also

several levels of OTP memory protection can be selected.

For programming of the device, the C505A-4E/C505CA-4E must be put into the programming

mode. This typically is done not in-system but in a special programming hardware. In the

programming mode the C505A-4E/C505CA-4E operates as a slave device similar as an EPROM

standalone memory device and must be controlled with address/data information, control lines, and

an external 11.5V programming voltage. Figure 26 shows the pins of the C505A-4E/C505CA-4E

which are required for controlling of the OTP programming mode.

V_DDV_SS

A0-A7 /

A8-A14

PALE

Port 2

Port 0

D0-D7

EA/V_PP

PROG

PRD

PMSEL0

PMSEL1

C505A-4E

C505CA-4E

RESET

XTAL1

XTAL2

PSEN

PSEL

Figure 26

Programming Mode Configuration

Data Sheet

50

12.00

C505/C505C/C505A/C505CA

Pin Configuration in Programming Mode

33 32 31 30 29 28 27 26 25 24 23

34

35

36

37

38

39

40

41

42

43

44

22

A4 / A12

D3

D2

D1

D0

N.C.

21

20

19

A3 / A11

A2 / A10

A1 / A9

A0 / A8

V_DD

18

17

16

15

14

13

12

C505A-4E

C505CA-4E

V

SS

N.C.

XTAL1

XTAL2

N.C.

1

2

3

4

5

6

7

8

9 10 11

Figure 27

P-MQFP-44 Pin Configuration of the C505A-4E/C505CA-4E in Programming Mode (Top View)

Data Sheet

51

12.00

C505/C505C/C505A/C505CA

The following Table 11 contains the functional description of all C505A-4E/C505CA-4E pins which

are required for OTP memory programming.

Table 11

Pin Definitions and Functions in Programming Mode

Symbol

I/O

*)

Function

Pin Number

4

RESET

I

Reset

This input must be at static “1“ (active) level during the whole

programming mode.

PMSEL0

PMSEL1

5

7

I

Programming mode selection pins

These pins are used to select the different access modes in

programming mode. PMSEL1,0 must satisfy a setup time to the

rising edge of PALE. When the logic level of PMSEL1,0 is

changed, PALE must be at low level.

PMSEL1

PMSEL0

Access Mode

0

1

0

1

0

1

Reserved

Read version bytes

Program/read lock bits

Program/read OTP memory byte

PSEL

PRD

8

I

Basic programming mode select

This input is used for the basic programming mode selection

and must be switched according Figure 28.

9

Programming mode read strobe

This input is used for read access control for OTP memory read,

Version Register read, and lock bit read operations.

PALE

10

Programming address latch enable

PALE is used to latch the high address lines. The high address

lines must satisfy a setup and hold time to/from the falling edge

of PALE. PALE must be at low level when the logic level of

PMSEL1,0 is changed.

XTAL2

XTAL1

V_SS

14

15

16

17

O

I

XTAL2

Output of the inverting oscillator amplifier.

XTAL1

Input to the oscillator amplifier.

–

Circuit ground potential

must be applied in programming mode.

V_DD

Power supply terminal

must be applied in programming mode.

*) I = Input

O= Output

Data Sheet

52

12.00

C505/C505C/C505A/C505CA

Table 11

Pin Definitions and Functions in Programming Mode (cont’d)

Symbol

I/O

*)

Function

Pin Number

18-25

P2.0-7

I

Address lines

P2.0-7 are used as multiplexed address input lines A0-A7 and

A8-A14. A8-A14 must be latched with PALE.

PSEN

PROG

26

27

Program store enable

This input must be at static “0“ level during the whole

programming mode.

Programming mode write strobe

This input is used in programming mode as a write strobe for

OTP memory program, and lock bit write operations During

basic programming mode selection a low level must be applied

to PROG.

EA/V_PP

29

–

External Access / Programming voltage

This pin must be at 11.5V (V_PP) voltage level during

programming of an OTP memory byte or lock bit. During an

OTP memory read operation this pin must be at V_IHhigh level.

This pin is also used for basic programming mode selection. At

basic programming mode selection a low level must be applied

to EA/V_PP.

D7-0

30-37

I/O

Data lines 0-7

During programming mode, data bytes are transferred via the

bidirectional port 0 data lines.

N.C.

1-3, 6, 11-13, –

28, 38-44

Not Connected

These pins should not be connected in programming mode.

*) I = Input

O= Output

Data Sheet

53

12.00

C505/C505C/C505A/C505CA

Basic Programming Mode Selection

The basic programming mode selection scheme is shown in Figure 28.

5V

V_DD

Clock

(XTAL1/XTAL2)

stable

RESET

PSEN

“1“

“0“

0,1

PMSEL1,0

“0“

PROG

PRD

“1“

PSEL

“0“

PALE

V_PP

V_IH

EA/V_PP

0V

Ready for access

mode selection

During this period signals

are not actively driven

Figure 28

Basic Programming Mode Selection

Data Sheet

54

12.00

C505/C505C/C505A/C505CA

Table 12

Access Modes Selection

EA/

V_PP

PMSEL

Address

(Port 2)

Data

(Port 0)

Access Mode

PROG

PRD

1

0

Program OTP memory byte

Read OTP memory byte

Program OTP lock bits

Read OTP lock bits

V_PP

V_IH

V_PP

V_IH

H

A0-7

A8-14

D0-7

H

L

–

D1,D0 see

Table 13

H

Read OTP version byte

H

Byte addr.

D0-7

of sign. byte

Lock Bits Programming / Read

The C505A-4E/C505CA-4E has two programmable lock bits which, when programmed according

to Table 13, provide four levels of protection for the on-chip OTP code memory. The state of the

lock bits can also be read.

Table 13

Lock Bit Protection Types

Lock Bits at D1,D0 Protection Protection Type

Level

D1

D0

1

Level 0

The OTP lock feature is disabled. During normal operation of

the C505A-4E/C505CA-4E, the state of the EA pin is not

latched on reset.

1

0

Level 1

During normal operation of the C505A-4E/C505CA-4E, MOVC

instructions executed from external program memory are

disabled from fetching code bytes from internal memory. EA is

sampled and latched on reset. An OTP memory read operation

is only possible using the ROM/OTP verification mode 2 for

protection level 1. Further programming of the OTP memory is

disabled (reprogramming security).

0

1

0

Level 2

Level 3

Same as level 1, but also OTP memory read operation using

OTP verification mode is disabled.

Same as level 2; but additionally external code execution by

setting EA=low during normal operation of the C505A-4E/

C505CA-4E is no more possible.

External code execution, which is initiated by an internal

program (e.g. by an internal jump instruction above the ROM

boundary), is still possible.

Data Sheet

55

12.00

C505/C505C/C505A/C505CA

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

Unit Notes

min.

– 65

– 0.5

max.

150

6.5

Storage temperature

°C

V

–

T_ST

Voltage on V_DDpins with respect

to ground (V_SS)

V_DD

Voltage on any pin with respect

to ground (V_SS)

– 0.5

– 10

V

_DD+ 0.5

V

–

V_IN

Input current on any pin during

overload condition

10

mA

W

Absolute sum of all input currents

during overload condition

| 100 mA |

1

Power dissipation

P_DISS

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for longer

periods may affect device reliability. During absolute maximum rating overload conditions

(V_IN> V_DDor V_IN< V_SS) the voltage on V_DDpins with respect to ground (V_SS) must not

exceed the values defined by the absolute maximum ratings.

Data Sheet

56

12.00

C505/C505C/C505A/C505CA

Operating Conditions

Parameter

Symbol

Limit Values

max.

Unit Notes

min.

Supply voltage

V_DD

4.25

5.5

V

Active mode,

f_{osc max}= 20 MHz

2

0

5.5

V

PowerDown mode

Reference voltage

–

Ground voltage

V_SS

V

Ambient temperature

°C

SAB-C505 T_A

0

70

SAF-C505 T_A

SAH-C505 T_A

SAK-C505 T_A

-40

4

85

110

125

Analog reference

voltage

V_AREF

V_DD+ 0.1

V

–

Analog ground voltage V_AGND

V_SS– 0.1

V_SS+ 0.2

V

Analog input voltage

V_AIN

V

_AGND-0.2

V_AREF+0.2

V

–

1)

XTAL clock

f_osc

2

20

MHz

(with 50% duty

cycle)

1) For the extended temperature range -40 °C to 110 °C (SAH) and -40 °C to 125 °C (SAK), the

devices C505-2R, C505-L, C505C-2R and C505C-L have the max. operating frequency of

16MHz with 50% clock duty cycle.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C505 and partly its

demands on the system. To aid in interpreting the parameters right, when evaluating them for a

design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C505 will provide signals with the respective characteristics.

SR (System Requirement):

The external system must provide signals with the respective characteristics to the C505.

Data Sheet

57

12.00

C505/C505C/C505A/C505CA

DC Characteristics

(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Input low voltages

all except EA, RESET

EA pin

V_IL

V_IL1

V_IL2

– 0.5

0.2 V_DD- 0.1

0.2 V_DD- 0.3

0.2 V_DD+ 0.1 V

V

–

RESET pin

Input high voltages

all except XTAL1, RESET

XTAL1 pin

V_IH

V_IH1

V_IH2

0.2 V_DD+ 0.9 V_DD+ 0.5

V

–

0.7 V_DD

0.6 V_DD

V

_DD+ 0.5

RESET pin

Output low voltages

Ports 1, 2, 3, 4

Port 0, ALE, PSEN

V_OL

V_OL1

–

0.45

V

I_OL= 1.6 mA ¹⁾

I_OL= 3.2 mA ¹⁾

Output high voltages

Ports 1, 2, 3, 4

V_OH

2.4

0.9 V_DD

2.4

–

V

I

_OH= – 80 µA

_OH= – 10 µA

_OH= – 800 µA

_OH= – 80 µA ²⁾

Port 0 in external bus mode,

ALE, PSEN

V_OH2

0.9 V_DD

Logic 0 input current

Ports 1, 2, 3, 4

I_IL

– 10

– 65

– 70

µA

V_IN= 0.45 V

V_IN= 2 V

Logical 1-to-0 transition current I_TL

– 650

Ports 1, 2, 3, 4

Input leakage current

Port 0, AN0-7 (Port 1), EA

I_LI

–

± 1

µA

0.45 < V_IN< V_DD

14)

Input high current to RESET

I_IH

5

–

100

10

µA

0.6 V_DD<V_IN<V_DD

Pin capacitance

C_IO

pF

f_c= 1 MHz,

T_A= 25 °C

3) 4)

Overload current

I_OV

–

± 5

12.1

30

mA

V

Programming voltage

Supply current at EA/V_PP

V_PP

10.9

11.5 V ± 5% ⁵⁾

6)

mA

Notes see Page 60

Data Sheet

58

12.00

C505/C505C/C505A/C505CA

Power Supply Currents

Parameter

Symbol Limit Values Unit Test Condition

typ.¹²⁾max.¹³⁾

7)

C505 /

C505C

Active Mode

12 MHz I_DD

20 MHz I_DD

19.3

31.3

27.0 mA

39

8)

Idle Mode

12 MHz I_DD

20 MHz I_DD

10.3

16.2

13.0 mA

21.0

9)

Active Mode with

12 MHz I_DD

3.9

4.8

5.5

7.5

mA

µA

slow-down enabled 20 MHz I_DD

Idle Mode with 12 MHz I_DD

slow-down enabled 20 MHz I_DD

10)

3.2

4.0

5.0

7.0

Power down mode

Active Mode

I_PD

10

50

V

7)

_DD= 2..5.5 V ¹¹⁾

C505A-4E

/C505CA-4E

16 MHz I_DD

20 MHz I_DD

28.7

35.2

30.7 mA

37.6

8)

Idle Mode

16 MHz I_DD

20 MHz I_DD

14.9

17.7

15.9 mA

18.9

9)

Active Mode with

16 MHz I_DD

9.9

12.3

12.8 mA

15.6

slow-down enabled 20 MHz I_DD

Idle Mode with 16 MHz I_DD

slow-down enabled 20 MHz I_DD

10)

5.1

6.3

5.6

6.8

mA

Power down mode

I_PD

5.6

20

µA

V

_DD= 2..5.5 V ¹¹⁾

7)

C505A-4R / Active Mode

C505CA-4R

16 MHz I_DD

20 MHz I_DD

22.8

27.6

29.2 mA

35.3

8)

/C505A-2R /

C505CA-2R

/C505A-L /

Idle Mode

16 MHz I_DD

20 MHz I_DD

12.7

15.0

16.3 mA

19.3

9)

Active Mode with

slow-down enabled 20 MHz I_DD

16 MHz I_DD

6.6

7.3

8.2

9.3

mA

µA

C505CA-L

10)

Idle Mode with

slow-down enabled 20 MHz I_DD

16 MHz I_DD

5.0

5.3

5.9

6.5

Power down mode

I_PD

5.3

30

V

_DD= 2..5.5 V ¹¹⁾

Notes see Page 60

Data Sheet

59

12.00

C505/C505C/C505A/C505CA

Note:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLof ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these

pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise

pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,

or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the V_OHon ALE and PSEN to momentarily fall below the

0.9 V_DDspecification when the address lines are stabilizing.

3) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operating range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input currents on all port

pins may not exceed 50 mA. The supply voltage V_DDand V_SSmust remain within the specified limits.

4) Not 100% tested, guaranteed by design characterization.

5) Only valid for C505A-4E and C505CA-4E.

6) Only valid for C505A-4E and C505CA-4E in programming mode.

7) I_DD(active mode) is measured with:

XTAL1 driven with t_R, t_F= 5 ns, 50% duty cycle , V_IL= V_SS+ 0.5 V, V_IH= V_DD– 0.5 V; XTAL2 = N.C.;

EA = Port 0 = RESET =V_DD; all other pins are disconnected.

8) I_DD(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with t_R, t_F= 5 ns, 50% duty cycle, V_IL= V_SS+ 0.5 V, V_IH= V_DD– 0.5 V; XTAL2 = N.C.;

RESET = EA = V_SS; Port0 = V_DD; all other pins are disconnected; the microcontroller is put into idle mode by

software;

9) I_DD(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;

XTAL1 driven with t_R, t_F= 5 ns, 50% duty cycle, V_IL= V_SS+ 0.5 V, V_IH= V_DD– 0.5 V; XTAL2 = N.C.;

RESET = EA = V_SS; all other pins are disconnected; the microcontroller is put into slow-down mode by

software;

10) I_DD(idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;

XTAL1 driven with t_R, t_F= 5 ns, 50% duty cycle, V_IL= V_SS+ 0.5 V, V_IH= V_DD– 0.5 V; XTAL2 = N.C.;

RESET = EA = V_SS; Port0 = V_DD; all other pins are disconnected; the microcontroller is put into idle mode

with slow-down enabled by software;

11) I_PD(power-down mode) is measured under following conditions:

Port 0 = EA = V_DD; RESET =V_SS; XTAL2 = N.C.; XTAL1 = V_SS; V_AGND= V_SS; V_AREF= V_DD

all other pins are disconnected.

;

12) The typical I_DDvalues are periodically measured at T_A= +25 °C but not 100% tested.

13) The maximum I_DDvalues are measured under worst case conditions (T_A= 0 °C or -40 °C and V_DD= 5.5 V)

14) The values are valid for C505CA-4R, C505CA-2R, C505CA-L, C505A-4R, C505A-2R and C505A-L only.

Data Sheet

60

12.00

C505/C505C/C505A/C505CA

I_DD

[mA]

40

C505

C505C

35

30

25

20

15

10

5

I_DD

max

typ

f_OSC

4

8

12

16

20

[MHz]

Figure 29

I

_DDDiagram of C505 and C505C

C505/C505C : Power Supply Current Calculation Formulas

Parameter

Symbol

Formula

1.5 f_OSC+ 1.3

Active mode

I_{DD typ}

*

I_{DD max}

1.5 f_OSC+ 9.0

*

Idle mode

I_{DD typ}

0.74 f_OSC+ 1.4

*

I_{DD max}

1.0 f_OSC+ 1.0

*

Active mode with

I_{DD typ}

0.11 f_OSC+ 2.6

*

slow-down enabled

I_{DD max}

0.25 f_OSC+ 2.5

*

Idle mode with

I_{DD typ}

0.1 f_OSC+ 2.0

*

slow-down enabled

I_{DD max}

0.25 f_OSC+ 2.0

*

Note:

f

is the oscillator frequency in MHz. I values are given in mA.

osc

DD

Data Sheet

61

12.00

C505/C505C/C505A/C505CA

C505A-4E

C505CA-4E

I_DD

[mA]

40

35

30

25

20

15

10

5

I_DD

max

typ

f_OSC

4

8

12

16

20

[MHz]

Figure 30

I_DDDiagram of C505A-4E and C505CA-4E

C505A-4E/C505CA-4E : Power Supply Current Calculation Formulas

Parameter

Symbol

Formula

1.63 f_OSC+ 2.6

Active mode

I_{DD typ}

*

I_{DD max}

1.74 f_OSC+ 2.8

*

Idle mode

I_{DD typ}

0.69 f_OSC+ 3.9

*

I_{DD max}

0.74 f_OSC+ 4.1

*

Active mode with

I_{DD typ}

0.6 f_OSC+ 0.3

*

slow-down enabled

I_{DD max}

0.7 f_OSC+ 1.6

*

Idle mode with

I_{DD typ}

0.3 f_OSC+ 0.3

*

slow-down enabled

I_{DD max}

0.3 f_OSC+ 0.8

*

Note:

f

is the oscillator frequency in MHz. I values are given in mA.

osc

DD

Data Sheet

62

12.00

C505/C505C/C505A/C505CA

C505A-4R

C505A-2R

C505A-L

I_DD

[mA]

40

C505CA-4R

C505CA-2R

C505CA-L

35

30

25

20

15

10

5

I_DD

max

I_DD

typ

f_OSC

4

8

12

16

20

[MHz]

Figure 31

I_DDDiagram of C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L

C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L :

Power Supply Current Calculation Formulas

Parameter

Symbol

Formula

1.19 f_OSC+ 3.77

Active mode

I_{DD typ}

*

I_{DD max}

1.54 f_OSC+ 4.47

*

Idle mode

I_{DD typ}

0.57 f_OSC+ 3.55

*

I_{DD max}

0.75 f_OSC+ 4.26

*

Active mode with

I_{DD typ}

0.18 f_OSC+ 3.74

*

slow-down enabled

I_{DD max}

0.28 f_OSC+ 3.67

*

Idle mode with

I_{DD typ}

0.07 f_OSC+ 3.91

*

slow-down enabled

I_{DD max}

0.14 f_OSC+ 3.64

*

Note:

f

is the oscillator frequency in MHz. I values are given in mA.

osc

DD

Data Sheet

63

12.00

C505/C505C/C505A/C505CA

A/D Converter Characteristics of C505 and C505C

(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

1)

Analog input voltage

Sample time

V_AIN

t_S

V_AGND

0.2

-

V_AREF

0.2

+

V

–

64 x t_IN

32 x t_IN

16 x t_IN

8 x t_IN

ns

Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4

2)

3)

Conversion cycle time

t_ADCC

–

320 x t_INns

160 x t_IN

80 x t_IN

Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4

40 x t_IN

Total unadjusted error

T_UE

–

± 2

LSB V_SS+0.5V ≤ V_AIN≤ V_DD-0.5V ⁴⁾

5) 6)

t_ADCin [ns]

Internal resistance of

R_AREF

t_ADC/ 500 kΩ

reference voltage source

- 1

2) 6)

t_Sin [ns]

Internal resistance of

analog source

R_ASRC

C_AIN

–

t_S/ 500

- 1

kΩ

6)

ADC input capacitance

Notes see next page.

50

pF

Clock calculation table :

ClockPrescaler ADCL1, 0

Ratio

t

ADC

S

ADCC

÷ 32

÷ 16

÷ 8

1

0

1

0

1

0

32 x t

16 x t

8 x t

64 x t

32 x t

16 x t

8 x t

320 x t

160 x t

80 x t

IN

÷ 4

4 x t

40 x t

Further timing conditions : t

t

min = 800 ns

ADC

IN

= 1 / f

= t

OSC

CLP

Data Sheet

64

12.00

C505/C505C/C505A/C505CA

Note:

1) V

may exeed V

or V

AGND AREF

up to the absolute maximum ratings. However, the conversion result in

AIN

these cases will be 00 or FF , respectively.

H

2) During the sample time the input capacitance C

must be charged/discharged by the external source. The

AIN

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t .

After the end of the sample time t , changes of the analog input voltage have no effect on the conversion result.

S

3) This parameter includes the sample time t , the time for determining the digital result. Values for the

S

conversion clock t

ADC

depend on programming and can be taken from the table on the previous page.

4) T

(max.) is tested at –40 ≤ T ≤=125 °C ; V_DD≤ 5.5 V; V

≤ V_DD+ 0.1 V and V =≤ V

. It is

A

AREF

SS

AGND

UE

guaranteed by design characterization for all other voltages within the defined voltage range.

If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload

currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is

permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Data Sheet

65

12.00

C505/C505C/C505A/C505CA

A/D Converter Characteristics of C505A and C505CA

(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

1)

Analog input voltage

Sample time

V_AIN

t_S

V_AGND

V_AREF

V

–

64 x t_IN

32 x t_IN

16 x t_IN

8 x t_IN

ns

Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4

2)

3)

Conversion cycle time

Total unadjusted error

t_ADCC

–

384 x t_INns

192 x t_IN

96 x t_IN

Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 4

48 x t_IN

T_UE

–

± 2

± 4

LSB V_SS+0.5V ≤ V_AIN≤ V_DD-0.5V ⁴⁾

LSB V_SS< V_AIN< V_DD+0.5V

4)

V

_DD- 0.5 V < V_AIN< V_DD

5) 6)

t

_ADCin [ns]

Internal resistance of

reference voltage source

R_AREF

R_ASRC

C_AIN

–

t_ADC/ 250 kΩ

- 0.25

2) 6)

t_Sin [ns]

Internal resistance of

analog source

t_S/ 500

kΩ

- 0.25

6)

ADC input capacitance

Notes see next page.

50

pF

Clock calculation table :

ClockPrescaler ADCL1, 0

Ratio

t

ADC

S

ADCC

÷ 32

÷ 16

÷ 8

1

0

1

0

1

0

32 x t

16 x t

8 x t

64 x t

384 x t

192 x t

96 x t

IN

32 x t

16 x t

8 x t

÷ 4

4 x t

48 x t

Further timing conditions : t

t

min = 500 ns

ADC

IN

= 1 / f

= t

OSC

CLP

Data Sheet

66

12.00

C505/C505C/C505A/C505CA

Note:

1) V

may exeed V

or V

AGND AREF

up to the absolute maximum ratings. However, the conversion result in

AIN

these cases will be X000 or X3FF , respectively.

H

2) During the sample time the input capacitance C

must be charged/discharged by the external source. The

AIN

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t .

After the end of the sample time t , changes of the analog input voltage have no effect on the conversion result.

S

3) This parameter includes the sample time t , the time for determining the digital result and the time for the

S

calibration. Values for the conversion clock t

the previous page.

depend on programming and can be taken from the table on

ADC

4) T

is tested at V

= 5.0 V, V = 0 V, V_DD= 4.9 V. It is guaranteed by design characterization for all

AGND

UE

AREF

other voltages within the defined voltage range.

If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload

currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is

permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Data Sheet

67

12.00

C505/C505C/C505A/C505CA

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle)

(Operating Conditions apply)

(C_Lfor port 0, ALE and PSEN outputs = 100 pF; C_Lfor all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

Unit

16-MHz clock

Duty Cycle 1/CLP= 2 MHz to 16 MHz

0.4 to 0.6

min.

48

10

–

max. min.

max.

ALE pulse width

t_LHLL

t_AVLL

t_LLAX

t_LLIV

–

CLP - 15

–

ns

Address setup to ALE

Address hold after ALE

ALE to valid instruction in

ALE to PSEN

–

TCL_Hmin-15 –

–

75

–

2 CLP - 50 ns

t_LLPL

t_PLPH

10

73

TCL_Lmin-15

–

ns

PSEN pulse width

–

CLP+

TCL_Hmin-15

PSEN to valid instruction in

t_PLIV

t_PXIX

–

38

–

CLP+

TCL_Hmin- 50

ns

Input instruction hold after PSEN

Input instruction float after PSEN

Address valid after PSEN

0

–

0

–

*)

t_PXIZ

–

15

–

TCL_Lmin-10 ns

*)

t_PXAV

20

–

TCL_Lmin- 5

–

ns

Address to valid instruction in

t_AVIV

95

2 CLP +

TCL_Hmin-55

Address float to PSEN

t_AZPL

-5

–

-5

–

ns

*)

Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not

cause any damage to port 0 drivers.

Data Sheet

68

12.00

C505/C505C/C505A/C505CA

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

Unit

16-MHz clock

Duty Cycle

0.4 to 0.6

1/CLP= 2 MHz to 16 MHz

min.

158

48

max. min. max.

t_RLRH

t_WLWH

t_LLAX2

t_RLDV

RD pulse width

–

3 CLP - 30

CLP - 15

–

ns

WR pulse width

–

Address hold after ALE

RD to valid data in

–

100

2 CLP+

TCL_Hmin- 50

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

Data hold after RD

Data float after RD

ALE to valid data in

Address to valid data in

0

–

0

–

ns

51

CLP - 12

4 CLP - 50

200

4 CLP +

TCL_Hmin-75

t_LLWL

ALE to WR or RD

73

103

CLP +

CLP+

ns

TCL_Lmin- 15 TCL_Lmin+ 15

t_AVWL

t_WHLH

t_QVWX

t_QVWH

Address valid to WR

95

10

5

–

2 CLP - 30

–

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

40

–

TCL_Hmin- 15 TCL_Hmin+ 15 ns

TCL_Lmin- 20

–

ns

163

–

3 CLP +

TCL_Lmin- 50

t_WHQX

t_RLAZ

Data hold after WR

5

–

0

TCL_Hmin- 20

–

0

ns

Address float after RD

Data Sheet

69

12.00

C505/C505C/C505A/C505CA

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d)

External Clock Drive Characteristics

Parameter

Symbol CPU Clock = 16 MHz

Duty Cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 2 to 16 MHz

Unit

min.

62.5

25

max.

62.5

–

min.

max.

Oscillator period

High time

CLP

TCL_H

TCL_L

t_R

62.5

500

ns

25

CLP - TCL_L

Low time

25

–

25

CLP - TCL_Hns

Rise time

–

10

–

10

ns

–

Fall time

t_F

–

10

–

10

Oscillator duty cycle

Clock cycle

DC

0.4

25

0.6

37.5

25 / CLP

1 - 25 / CLP

TCL

CLP * DC_minCLP * DC_maxns

Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of

the oscillator clock from 0.4 to 0.6.

Data Sheet

70

12.00

C505/C505C/C505A/C505CA

AC Characteristics (20 MHz, 0.5 Duty Cycle)

(Operating Conditions apply)

(C_Lfor port 0, ALE and PSEN outputs = 100 pF; C_Lfor all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

0.5 Duty Cycle 1/CLP = 2 MHz to 20 MHz

Unit

20 MHz clock

min.

35

10

–

max.

min.

max.

ALE pulse width

t_LHLL

t_AVLL

t_LLAX

t_LLIV

–

CLP - 15

CLP/2 - 15

–

ns

Address setup to ALE

Address hold after ALE

ALE to valid instruction in

ALE to PSEN

–

55

–

2 CLP - 45

t_LLPL

t_PLPH

10

60

CLP/2 - 15

–

PSEN pulse width

–

3/2 CLP

- 15

PSEN to valid instruction in

t_PLIV

t_PXIX

–

25

–

3/2 CLP

- 50

ns

Input instruction hold after PSEN

Input instruction float after PSEN

Address valid after PSEN

0

–

0

–

ns

*)

t_PXIZ

–

20

–

CLP/2 - 5

–

*)

t_PXAV

20

–

CLP/2 - 5

–

Address to valid instruction in

t_AVIV

65

5/2 CLP

- 60

Address float to PSEN

t_AZPL

- 5

–

- 5

–

ns

*)

Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not

cause any damage to port 0 drivers.

Data Sheet

71

12.00

C505/C505C/C505A/C505CA

AC Characteristics (20 MHz, 0.5 Duty Cycle, cont’d)

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

1/CLP = 2 MHz to 20 MHz

Unit

20 MHz clock

0.5 Duty Cycle

min.

120

35

–

max.

–

min.

max.

t_RLRH

t_WLWH

t_LLAX2

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

RD pulse width

3 CLP - 30

–

ns

WR pulse width

–

3 CLP - 30

Address hold after ALE

RD to valid data in

–

CLP - 15

75

–

0

–

5/2 CLP- 50 ns

Data hold after RD

0

–

ns

Data float after RD

–

38

150

90

–

CLP - 12

4 CLP - 50

ALE to valid data in

Address to valid data in

ALE to WR or RD

–

t_AVDV

t_LLWL

t_AVWL

t_WHLH

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

–

9/2 CLP - 75 ns

60

70

10

5

3/2 CLP - 15 3/2 CLP + 15 ns

Address valid to WR

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

Address float after RD

2 CLP - 30

CLP/2 - 15

CLP/2 - 20

7/2 CLP - 50

CLP/2 - 20

–

ns

40

–

CLP/2 + 15

–

0

125

5

–

0

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 2 MHz to 20 MHz

min.

50

15

–

max.

500

Oscillator period

High time

CLP

ns

–

TCL_H

CLP-TCL_L

CLP-TCL_H

10

Low time

TCL_L

t_R

Rise time

Fall time

t_F

–

10

Oscillator duty cycle

DC

0.5

Data Sheet

72

12.00

C505/C505C/C505A/C505CA

t _LHLL

ALE

t_AVLL

t _PLPH

t _LLPL

t _LLIV

t _PLIV

PSEN

Port 0

Port 2

t _AZPL

t _LLAX

t _PXAV

t _PXIZ

t _PXIX

A0 - A7

Instr.IN

A0 - A7

t _AVIV

A8 - A15

MCT00096

Figure 32

Program Memory Read Cycle

Data Sheet

73

12.00

C505/C505C/C505A/C505CA

t_WHLH

ALE

PSEN

RD

t _LLDV

t _LLWL

t _RLRH

t _RLDV

t _AVLL

t_RHDZ

t _LLAX2

t _RLAZ

t_RHDX

A0 - A7 from

Ri or DPL

A0 - A7

from PCL

Instr.

IN

Port 0

Data IN

t_AVWL

t _AVDV

Port 2

P2.0 - P2.7 or A8 - A15 from DPH

A8 - A15 from PCH

MCT00097

Figure 33

Data Memory Read Cycle

Data Sheet

74

12.00

C505/C505C/C505A/C505CA

t_WHLH

ALE

PSEN

WR

t _LLWL

t _WLWH

t_QVWX

t _AVLL

t_WHQX

t _LLAX2

t_QVWH

A0 - A7 from

Ri or DPL

A0 - A7

Instr.IN

Port 0

Port 2

Data OUT

from PCL

t_AVWL

P2.0 - P2.7 or A8 - A15 from DPH

A8 - A15 from PCH

MCT00098

Figure 34

Data Memory Write Cycle

TCL

t

F

R

H

0.7V

0.7

V

DD

XTAL1

0.2V_DD- 0.1

0.2

- 0.1

V

DD

TCL

L

CLP

MCT03310

Figure 35

External Clock Drive on XTAL1

Data Sheet

75

12.00

C505/C505C/C505A/C505CA

AC Characteristics of Programming Mode (C505A-4E and C505CA-4E only)

_DD= 5 V ± 10 %; V_PP= 11.5 V ± 5 %; T_A= 25 °C ± 10 °C

V

Parameter

Symbol

Limit Values

Unit

min.

35

max.

PALE pulse width

t_PAW

t_PMS

t_PAS

–

ns

PMSEL setup to PALE rising edge

10

Address setup to PALE, PROG, or PRD

falling edge

10

ns

Address hold after PALE, PROG, or PRD

falling edge

t_PAH

10

–

Address, data setup to PROG or PRD

Address, data hold after PROG or PRD

PMSEL setup to PROG or PRD

PMSEL hold after PROG or PRD

PROG pulse width

t_PCS

t_PCH

t_PMS

t_PMH

t_PWW

t_PRW

t_PAD

t_PRD

t_PDH

t_PDF

100

0

–

ns

µs

ns

µs

–

10

100

–

PRD pulse width

–

Address to valid data out

PRD to valid data out

75

20

–

Data hold after PRD

0

Data float after PRD

–

20

–

PROG high between two consecutive PROG t_PWH1

1

low pulses

PRD high between two consecutive PRD low t_PWH2

pulses

100

ns

XTAL clock period

t_CLKP

83.3

500

Data Sheet

76

12.00

C505/C505C/C505A/C505CA

t

PAW

PMS

PALE

t

H, H

PMSEL1,0

t

PAH

PAS

A8-A14

A0-A7

Port 2

Port 0

PROG

D0-D7

t

PWH

t

PCH

PCS

PWW

MCT03642

Notes: PRD must be high during a programming write cycle.

Figure 36

Programming Code Byte - Write Cycle Timing

Data Sheet

77

12.00

C505/C505C/C505A/C505CA

t

PAW

PMS

PALE

t

H, H

PMSEL1,0

t

PAH

PAS

A8-A14

A0-A7

Port 2

Port 0

PRD

t

PDH

PAD

D0-D7

t

PRD

PDF

PCH

t

PWH

t

PCS

PRW

Notes: PROG must be high during a programming read cycle.

MCT03643

Figure 37

Verify Code Byte - Read Cycle Timing

Data Sheet

78

12.00

C505/C505C/C505A/C505CA

H, L

PMSEL1,0

Port 0

D0, D1

t

PCH

PCS

t

PMS

PMH

PROG

t

PDH

t

PMS

PRD

PWW

PDF

t

PMH

t

PRW

PRD

MCT03644

Note: PALE should be low during a lock bit read / write cycle.

Figure 38

Lock Bit Access Timing

L, H

PMSEL1,0

e. g. FD

Port 2

Port 0

H

t

PCH

D0-7

t

PCS

PDH

t

PRD

PDF

t

PMS

PMH

t

PRD

PRW

MCT03645

Note: PROG must be high during a programming read cycle.

Figure 39

Version Byte Read Timing

Data Sheet

79

12.00

C505/C505C/C505A/C505CA

ROM/OTP Verification Characteristics for C505

ROM Verification Mode 1 (C505(C)(A)-2R and C505(C)A-4R only)

Parameter

Symbol

Limit Values

max.

Unit

min.

t_AVQV

Address to valid data

–

5 CLP

ns

P1.0 - P1.7

P2.0 - P2.6

Address

t

AVQV

Port 0

Data OUT

Inputs:

P2.7, PSEN = V

Address: P1.0 - P1.7 = A0 - A7

Inputs: P2.6, P2.7, PSEN = V

SS

ALE, EA = V

P2.6

P2.0 - P2.5 = A8 - A14

ALE, EA = V

IH

RESET = V

IH2

RESET = V

IH2

Data:

P0.0 - P0.7 = D0 - D7

MCT03693

Note: P2.6 should be connected to V for C505(C)(A)-2R

SS

Figure 40

ROM Verification Mode 1

Data Sheet

80

12.00

C505/C505C/C505A/C505CA

ROM/OTP Verification Characteristics for C505 (cont’d)

ROM/OTP Verification Mode 2

Parameter

Symbol

Limit Values

Unit

min.

typ

CLP

6 CLP

–

max.

t_AWD

t_ACY

t_DVA

t_DSA

t_AS

ALE pulse width

–

ns

ALE period

–

ns

Data valid after ALE

Data stable after ALE

P3.5 setup to ALE low

Oscillator frequency

–

2 CLP

ns

4 CLP

–

6

ns

–

4

t_CL

ns

1/ CLP

–

MHz

t _ACY

t _AWD

ALE

t _DSA

t _DVA

Port 0

P3.5

Data Valid

t _AS

MCT02613

Figure 41

ROM/OTP Verification Mode 2

Data Sheet

81

12.00

C505/C505C/C505A/C505CA

V_DD-0.5 V

0.2 V_DD+0.9

0.2 V_DD-0.1

Test Points

0.45 V

MCT00039

AC Inputs during testing are driven at V_DD- 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.

Timing measurements are made at V_IHminfor a logic ’1’ and V_ILmaxfor a logic ’0’.

Figure 42

AC Testing: Input, Output Waveforms

-0.1 V

V_OH

V_Load+0.1 V

Timing Reference

Points

V_Load

-0.1 V

V_Load

V

_OL+0.1 V

MCT00038

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel occurs.

I_OL/I_OH≥ ± 20 mA

Figure 43

AC Testing : Float Waveforms

Crystal Oscillator Mode

Driving from External Source

C

XTAL2

XTAL1

N.C.

XTAL2

2 - 20

MHz

External Oscillator

Signal

C

XTAL1

Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance)

MCS03311

Figure 44

Recommended Oscillator Circuits for Crystal Oscillator

Data Sheet

82

12.00

C505/C505C/C505A/C505CA

P-MQFP-44-2 (SMD)

(Plastic Metric Quad Flat Package)

Figure 45

P-MQFP-44 Package Outline

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”

SMD = Surface Mounted Device

Dimensions in mm

12.00

Data Sheet

83

Infineon goes for Business Excellence

“Business excellence means intelligent approaches and clearly

defined processes, which are both constantly under review and

ultimately lead to good operating results.

Better operating results and business excellence mean less

idleness and wastefulness for all of us, more professional

success, more accurate information, a better overview and,

thereby, less frustration and more satisfaction.”

Dr. Ulrich Schumacher

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	SAB-C505A-4R20M
厂家：	Infineon
描述：	Microcontroller, 8-Bit, MROM, 20MHz, CMOS, PQFP44, PLASTIC, MQFP-44 时钟微控制器外围集成电路
文件：	总88页 (文件大小：1013K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAB-C505A-4R20M [INFINEON]

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