SAF-C161PI-LF_技术文档

C161PI

Microcontrollers

C166 Family

16-Bit Single-Chip Microcontroller

C161PI

Data Sheet 1999-07

Preliminary

C161PI

Revision History:

1999-07 Preliminary

Previous Versions:

1998-05

1998-01

1997-12

(C161RI / Preliminary)

(C161RI / Advance Information)

Page

---

Subjects

3 V specification introduced

4, 5, 7

14

Signal FOUT added

XRAM description added

15

Unlatched CS description added

Block Diagram corrected

23

24

Description of divider chain improved

ADC description updated to 10-bit

Revised description of Absolute Max. Ratings and Operating Conditions

Power supply values improved

25, 51, 52

36, 37

39, 44

45 - 50

54 ff.

Revised description for clock generation including PLL

Standard 25-MHz timing

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

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The C161PI is the successor of the C161RI. Therefore this data sheet also replaces the C161RI

data sheet (see also revision history).

Edition 1999-07

Published by Infineon Technologies AG i. Gr.,

St.-Martin-Strasse 53

D-81541 München

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and

charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

in Germany or our Infineon Technologies Representatives worldwide (see address list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Tech-

nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect

the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to

support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other

persons may be endangered.

C166 Family of

C161PI

High-Performance CMOS 16-Bit Microcontrollers

Preliminary

C161PI 16-Bit Microcontroller

• High Performance 16-bit CPU with 4-Stage Pipeline

– 80 ns Instruction Cycle Time at 25 MHz CPU Clock

– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 MBytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 27 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

• Clk. Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clk. inp.

• On-Chip Memory Modules

– 1 KByte On-Chip Internal RAM (IRAM)

– 2 KBytes On-Chip Extension RAM (XRAM)

• On-Chip Peripheral Modules

– 4-Channel 10-bit A/D Converter with Programm. Conversion Time down to 7.8 µs

– Two Multi-Functional General Purpose Timer Units with 5 Timers

– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

– I²C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed)

• Up to 8 MBytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Five Programmable Chip-Select Signals

• Idle and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• On-Chip Real Time Clock

• Up to 76 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

• Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,

Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 100-Pin MQFP / TQFP Package

Data Sheet

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This document describes the SAB-C161PI-LM, the SAB-C161PI-LF, the SAF-C161PI-

LM and the SAF-C161PI-LF.

For simplicity all versions are referred to by the term C161PI throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

• the derivative itself, i.e. its function set

• the specified temperature range

• the package

• the type of delivery.

For the available ordering codes for the C161PI please refer to the

„Product Catalog Microcontrollers“, which summarizes all available microcontroller

variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet

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Introduction

The C161PI is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS

microcontrollers. It combines high CPU performance (up to 8 million instructions per

second) with high peripheral functionality and enhanced IO-capabilities. The C161PI

derivative is especially suited for cost sensitive applications.

V_DDV_SSV_AREFV_AGND

PORT0

XTAL1

XTAL2

16 bit

PORT1

16 bit

RSTIN

RSTOUT

Port 2

8 bit

NMI

EA

C161PI

Port 3

15 bit

Port 4

7 bit

ALE

RD

WR/WRL

Port 6

8 bit

Port 5

6 bit

Figure 1

Logic Symbol

Data Sheet

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Pin Configuration MQFP Package

(top view)

P5.2/AN2

P5.3/AN3

P5.14/T4EUD

P5.15/T2EUD

V_SS

1

2

3

4

5

6

7

8

NMI

RSTOUT

RSTIN

V_DD

V_SS

P1H.7/A15

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

V_DD

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

XTAL1

XTAL2

V_DD

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

C161PI

P3.6/T3IN

P3.7/T2IN

V_SS

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P0H.1/AD9

P3.8/MRST

P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT/

FOUT

V_SS

V_DD

P4.0/A16

P4.1/A17

P4.2/A18

P4.3/A19

P4.4/A20

Figure 2

Data Sheet

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Pin Configuration TQFP Package

(top view)

P5.14/T4EUD

P5.15/T2EUD

V_SS

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V_DD

V_SS

1

2

3

4

5

6

7

8

P1H.7/A15

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

V_DD

XTAL1

XTAL2

V_DD

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

P3.6/T3IN

P3.7/T2IN

P3.8/MRST

P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT/

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

V_SS

C161PI

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

FOUT

V_SS

V_DD

P4.0/A16

P4.1/A17

Figure 3

Data Sheet

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Table 1

Symbol Pin

Pin Definitions and Functions

Pin Input Function

Num. Num. Outp.

TQFP MQFP

P5

I

Port 5 is a 6-bit input-only port with Schmitt-Trigger

characteristics. The pins of Port 5 also serve as (up to

4) analog input channels for the A/D converter, or they

serve as timer inputs:

P5.0

P5.1

P5.2

P5.3

P5.14

P5.15

97

98

99

100

1

99

100

1

2

3

I

AN0

AN1

AN2

AN3

T4EUD

T2EUD

GPT1 Timer T4 Ext. Up/Down Ctrl. Input

GPT1 Timer T5 Ext. Up/Down Ctrl. Input

2

4

XTAL1 4

6

I

XTAL1:

Input to the oscillator amplifier and input to

the internal clock generator

XTAL2 5

7

O

XTAL2:

Output of the oscillator amplifier circuit.

To clock the device from an external source, drive

XTAL1, while leaving XTAL2 unconnected. Minimum

and maximum high/low and rise/fall times specified in

the AC Characteristics must be observed.

Data Sheet

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Table 1

Symbol Pin

Pin Definitions and Functions (continued)

Pin Input Function

Num. Num. Outp.

TQFP MQFP

P3

IO

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into

high-impedance state. Port 3 outputs can be

configured as push/pull or open drain drivers. The input

threshold of Port 3 is selectable (TTL or special). The

following Port 3 pins also serve for alternate functions:

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

7

8

9

10

11

12

9

I/O

I

O

I

SCL0

I2C Bus Clock Line 0

I2C Bus Data Line 0

10

11

12

13

14

SDA0

CAPIN

T3OUT

T3EUD

T4IN

GPT2 Register CAPREL Capture Input

GPT1 Timer T3 Toggle Latch Output

GPT1 Timer T3 External Up/Down Ctrl.Inp

GPT1 Timer T4 Count/Gate/Reload/

Capture Input

I

P3.6

P3.7

13

14

15

16

I

T3IN

T2IN

GPT1 Timer T3 Count/Gate Input

GPT1 Timer T2 Count/Gate/Reload/

Capture Input

P3.8

P3.9

P3.10

P3.11

P3.12

15

16

17

18

19

17

18

19

20

21

I/O

O

I/O

O

I/O

O

MRST

MTSR

T×D0

R×D0

BHE

SSC Master-Rec. / Slave-Trans. Inp/Outp.

SSC Master-Trans. / Slave-Rec. Outp/Inp.

ASC0 Clock/Data Output (Async./Sync.)

ASC0 Data Input (Async.) or I/O (Sync.)

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe

SSC Master Clock Outp. / Slave Clock Inp.

WRH

SCLK

P3.13

P3.15

20

21

22

23

CLKOUT System Clock Output (=CPU Clock)

FOUT Programmable Frequency Output

Note: Pins P3.0 and P3.1 are open drain outputs only.

O

Data Sheet

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Table 1

Symbol Pin

Pin Definitions and Functions (continued)

Pin Input Function

Num. Num. Outp.

TQFP MQFP

P4

IO

Port 4 is a 7-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into

high-impedance state. Port 4 outputs can be

configured as push/pull or open drain drivers. The input

threshold of Port 4 is selectable (TTL or special). Port 4

can be used to output the segment address lines:

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

24

25

26

27

28

29

30

26

27

28

29

30

31

32

O

A16

A17

A18

A19

A20

A21

A22

Least Significant Segment Address Line

Segment Address Line

Most Significant Segment Address Line

RD

31

33

O

External Memory Read Strobe. RD is activated for

every external instruction or data read access.

WR/

WRL

32

34

O

External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL-

mode this pin is activated for low byte data write

accesses on a 16-bit bus, and for every data write

access on an 8-bit bus. See WRCFG in register

SYSCON for mode selection.

READY 33

35

36

I

Ready Input. When the Ready function is enabled, a

high level at this pin during an external memory access

will force the insertion of memory cycle time waitstates

until the pin returns to a low level.

An internal pullup device will hold this pin high when

nothing is driving it.

ALE

34

O

Address Latch Enable Output. Can be used for latching

the address into external memory or an address latch

in the multiplexed bus modes.

Data Sheet

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Table 1

Symbol Pin

Pin Definitions and Functions (continued)

Pin Input Function

Num. Num. Outp.

TQFP MQFP

EA

35

37

I

External Access Enable pin. A low level at this pin

during and after Reset forces the C161PI to begin

instruction execution out of external memory. A high

level forces execution out of the internal program

memory.

"ROMless" versions must have this pin tied to ‘0’.

PORT0

P0L.0-7 38-

45

P0H.0-7 48-

55

IO

PORT0 consists of the two 8-bit bidirectional I/O ports

P0L and P0H. It is bit-wise programmable for input or

output via direction bits. For a pin configured as input,

the output driver is put into high-impedance state.

In case of external bus configurations, PORT0 serves

as the address (A) and address/data (AD) bus in

multiplexed bus modes and as the data (D) bus in

demultiplexed bus modes.

40-

47

50-

57

Demultiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

D0 – D7

I/O

16-bit

D0 - D7

D8 - D15

Multiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

16-bit

AD0 – AD7 AD0 - AD7

A8 - A15 AD8 - AD15

PORT1

P1L.0-7 56-

63

P1H.0-7 66-

73

IO

PORT1 consists of the two 8-bit bidirectional I/O ports

P1L and P1H. It is bit-wise programmable for input or

output via direction bits. For a pin configured as input,

the output driver is put into high-impedance state.

PORT1 is used as the 16-bit address bus (A) in

demultiplexed bus modes and also after switching from

a demultiplexed bus mode to a multiplexed bus mode.

58-

65

68-

75

Data Sheet

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Table 1

Symbol Pin

Pin Definitions and Functions (continued)

Pin Input Function

Num. Num. Outp.

TQFP MQFP

RSTIN 76

78

I/O

Reset Input with Schmitt-Trigger characteristics. A low

level at this pin while the oscillator is running resets the

C161PI. An internal pullup resistor permits power-on

reset using only a capacitor connected to 9_SS.

A spike filter suppresses input pulses <10 ns. Input

pulses >100 ns safely pass the filter.

The minimum duration for a safe recognition should be

100 ns + 2 CPU clock cycles.

In bidirectional reset mode (enabled by setting bit

BDRSTEN in register SYSCON) the RSTIN line is

internally pulled low for the duration of the internal

reset sequence upon any reset (HW, SW, WDT).

See note below this table.

Note: To let the reset configuration of PORT0 settle

and to let the PLL lock a reset duration of ca.

1 ms is recommended.

RST

OUT

77

78

79

80

O

Internal Reset Indication Output. This pin is set to a low

level when the part is executing either a hardware-, a

software- or a watchdog timer reset. RSTOUT remains

low until the EINIT (end of initialization) instruction is

executed.

NMI

I

Non-Maskable Interrupt Input. A high to low transition

at this pin causes the CPU to vector to the NMI trap

routine. When the PWRDN (power down) instruction is

executed, the NMI pin must be low in order to force the

C161PI to go into power down mode. If NMI is high,

when PWRDN is executed, the part will continue to run

in normal mode.

If not used, pin NMI should be pulled high externally.

Data Sheet

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Table 1

Symbol Pin

Pin Definitions and Functions (continued)

Pin Input Function

Num. Num. Outp.

TQFP MQFP

P6

IO

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into

high-impedance state. Port 6 outputs can be

configured as push/pull or open drain drivers.

The Port 6 pins also serve for alternate functions:

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

79

80

81

82

83

84

85

86

81

82

83

84

85

86

87

88

O

CS0

CS1

CS2

CS3

Chip Select 0 Output

Chip Select 1 Output

Chip Select 2 Output

Chip Select 3 Output

Chip Select 4 Output

I²C Bus Data Line 1

I²C Bus Clock Line 1

I²C Bus Data Line 2

O

CS4

I/O

SDA1

SCL1

SDA2

Note: Pins P6.7-5 are open drain outputs only.

P2

IO

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For

a pin configured as input, the output driver is put into

high-impedance state. Port 2 outputs can be

configured as push/pull or open drain drivers. The input

threshold of Port 2 is selectable (TTL or special).

The Port 2 pins also serve for alternate functions:

P2.8

P2.9

87

88

89

90

91

92

93

94

89

90

91

92

93

94

95

96

I

EX0IN

EX1IN

EX2IN

EX3IN

EX4IN

EX5IN

EX6IN

EX7IN

Fast External Interrupt 0 Input

Fast External Interrupt 1 Input

Fast External Interrupt 2 Input

Fast External Interrupt 3 Input

Fast External Interrupt 4 Input

Fast External Interrupt 5 Input

Fast External Interrupt 6 Input

Fast External Interrupt 7 Input

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

9_AREF

95

97

98

-

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

9_AGND96

Data Sheet

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Table 1

Symbol Pin

Pin Definitions and Functions (continued)

Pin Input Function

Num. Num. Outp.

TQFP MQFP

9_DD

6, 23, 8, 25, -

Digital Supply Voltage:

+ 5 V or + 3 V during normal operation and idle mode.

≥ 2.5 V during power down mode

37,

47,

39,

49,

65, 75 67, 77

9_SS

3, 22, 5, 24, -

Digital Ground.

36,

46,

38,

48,

64, 74 66, 76

Note: The following behaviour differences must be observed when the bidirectional reset

is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared

automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap

loader may be activated when P0L.4 is low.

• Pin RSTIN may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet

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Functional Description

The architecture of the C161PI combines advantages of both RISC and CISC

processors and of advanced peripheral subsystems in a very well-balanced way. The

following block diagram gives an overview of the different on-chip components and of the

advanced, high bandwidth internal bus structure of the C161PI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

16

&ꢀꢁꢁꢃ&RUH

(no

internal

ROM)

Data

Internal

RAM

32

16

&38ꢂ&RUH

Instr./Data

&38

16

OSC

Oscillator

⁽(ⁱⁿ1^p6^uM^{t: 1}H^6Mz)^Hz;

or dPireLcLt drive)

XTAL

prescaler

3(&

External Instr./Data

Watchdog

16

Interrupt Controller 11 ext. IR

I²C-Bus

Interface

Interrupt Bus

Peripheral Data

XRAM

2 KByte

8

External

Bus

(MUX

only) &

XBUS

Control,

CS Logic

(4 CS)

USART

Sync.

Channel

(SPI)

4-

GPT 1

GPT 2

RTC

Channel

10-bit

8-bit

T 2

T 3

T 4

T 5

T 6

ADC

16

SSC

BRG

ASC

BRG

7

Port 4

Port 1

Port 5

Port 3

15

Port 2

C161RI V0.1

8

16

6

Figure 4

Block Diagram

Data Sheet

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Memory Organization

The memory space of the C161PI is configured in a Von Neumann architecture which

means that code memory, data memory, registers and I/O ports are organized within the

same linear address space which includes 16 MBytes. The entire memory space can be

accessed bytewise or wordwise. Particular portions of the on-chip memory have

additionally been made directly bitaddressable.

1 KByte of on-chip Internal RAM (IRAM) is provided as a storage for user defined

variables, for the system stack, general purpose register banks and even for code. A

register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,

…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user

stacks, or code. The XRAM is accessed like external memory and therefore cannot be

used for the system stack or for register banks and is not bitaddressable. The XRAM

permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 8 MBytes of external RAM and/or ROM can be connected to the

microcontroller.

Data Sheet

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External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus

Controller (EBC). It can be programmed either to Single Chip Mode when no external

memory is required, or to one of four different external memory access modes, which are

as follows:

– 16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/

output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses

and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,

Memory Tri-State Time, Length of ALE and Read Write Delay) have been made

programmable to allow the user the adaption of a wide range of different types of

memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs

ADDRSELx / BUSCONx) which allow to access different resources with different bus

characteristics. These address windows are arranged hierarchically where BUSCON4

overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not

covered by these 4 address windows are controlled by BUSCON0.

Up to 5 external CS signals (4 windows plus default) can be generated in order to save

external glue logic. The C161PI offers the possibility to switch the CS outputs to an

unlatched mode. In this mode the internal filter logic is switched off and the CS signals

are directly generated from the address. The unlatched CS mode is enabled by setting

CSCFG (SYSCON.6).

Access to very slow memories is supported via a particular ‘Ready’ function.

For applications which require less than 8 MBytes of external memory space, this

address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4

outputs four, two or no address lines at all. It outputs all 7 address lines, if an address

space of 8 MBytes is used.

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Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic

and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a

separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161PI’s instructions can be executed

in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and

rotate instructions are always processed during one machine cycle independent of the

number of bits to be shifted. All multiple-cycle instructions have been optimized so that

they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication

in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-

called ‘Jump Cache’, reduces the execution time of repeatedly performed jumps in a loop

from 2 cycles to 1 cycle.

Figure 5

CPU Block Diagram

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The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.

These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer

(CP) register determines the base address of the active register bank to be accessed by

the CPU at any time. The number of register banks is only restricted by the available

internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The

system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the

stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly

compared against the stack pointer value upon each stack access for the detection of a

stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently

be utilized by a programmer via the highly efficient C161PI instruction set which includes

the following instruction classes:

– Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes

and words. A variety of direct, indirect or immediate addressing modes are provided to

specify the required operands.

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Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of

internal program execution), the C161PI is capable of reacting very fast to the

occurrence of non-deterministic events.

The architecture of the C161PI supports several mechanisms for fast and flexible

response to service requests that can be generated from various sources internal or

external to the microcontroller. Any of these interrupt requests can be programmed to

being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is

suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a

single byte or word data transfer between any two memory locations with an additional

increment of either the PEC source or the destination pointer. An individual PEC transfer

counter is implicity decremented for each PEC service except when performing in the

continuous transfer mode. When this counter reaches zero, a standard interrupt is

performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data.

The C161PI has 8 PEC channels each of which offers such fast interrupt-driven data

transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable

flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via

its related register, each source can be programmed to one of sixteen interrupt priority

levels. Once having been accepted by the CPU, an interrupt service can only be

interrupted by a higher prioritized service request. For the standard interrupt processing,

each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high

precision requirements. These fast interrupt inputs feature programmable edge

detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with

an individual trap (interrupt) number.

The following table shows all of the possible C161PI interrupt sources and the

corresponding hardware-related interrupt flags, vectors, vector locations and trap

(interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt

request bit (xIR).

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Table 2

C161PI Interrupt Nodes

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Trap

Vector

Location Number

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

External Interrupt 7

GPT1 Timer 2

CC8IR

CC9IR

CC10IR

CC11IR

CC12IR

CC13IR

CC14IR

CC15IR

T2IR

CC8IE

CC9IE

CC10IE

CC11IE

CC12IE

CC13IE

CC14IE

CC15IE

T2IE

CC8INT

CC9INT

00’0060_H

00’0064_H

18_H

19_H

1A_H

CC10INT 00’0068_H

CC11INT 00’006C_H1B_H

CC12INT 00’0070_H

CC13INT 00’0074_H

CC14INT 00’0078_H

1C_H

1D_H

1E_H

CC15INT 00’007C_H1F_H

T2INT

T3INT

T4INT

T5INT

T6INT

CRINT

00’0088_H

22_H

GPT1 Timer 3

T3IR

T3IE

00’008C_H23_H

GPT1 Timer 4

T4IR

T4IE

00’0090_H

00’0094_H

00’0098_H

24_H

25_H

26_H

GPT2 Timer 5

T5IR

T5IE

GPT2 Timer 6

T6IR

T6IE

GPT2 CAPREL

Register

CRIR

CRIE

00’009C_H27_H

A/D Conversion

Complete

ADCIR

ADCIE

ADCINT

00’00A0_H28_H

A/D Overrun Error

ASC0 Transmit

ADEIR

S0TIR

ADEIE

S0TIE

S0TBIE

S0RIE

S0EIE

SCTIE

SCRIE

SCEIE

XP0IE

ADEINT

S0TINT

00’00A4_H29_H

00’00A8_H2A_H

ASC0 Transmit Buffer S0TBIR

S0TBINT 00’011C_H47_H

ASC0 Receive

ASC0 Error

S0RIR

S0EIR

SCTIR

SCRIR

SCEIR

XP0IR

S0RINT

S0EINT

SCTINT

SCRINT

SCEINT

XP0INT

00’00AC_H2B_H

00’00B0_H2C_H

00’00B4_H2D_H

00’00B8_H2E_H

00’00BC_H2F_H

SSC Transmit

SSC Receive

SSC Error

I²C Data Transfer

Event

00’0100_H

40_H

I²C Protocol Event

X-Peripheral Node 2

PLL Unlock / RTC

XP1IR

XP2IR

XP3IR

XP1IE

XP2IE

XP3IE

XP1INT

XP2INT

XP3INT

00’0104_H

00’0108_H

41_H

42_H

00’010C_H43_H

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The C161PI also provides an excellent mechanism to identify and to process exceptions

or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware

traps cause immediate non-maskable system reaction which is similar to a standard

interrupt service (branching to a dedicated vector table location). The occurence of a

hardware trap is additionally signified by an individual bit in the trap flag register (TFR).

Except when another higher prioritized trap service is in progress, a hardware trap will

interrupt any actual program execution. In turn, hardware trap services can normally not

be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise

during run-time:

Table 3

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number Prio

Trap

Reset Functions:

Hardware Reset

Software Reset

RESET

00’0000_H

00_H

III

Watchdog Timer Overflow

Class A Hardware Traps:

Non-Maskable Interrupt

Stack Overflow

NMI

STKOF

STKUF

NMITRAP 00’0008_H

STOTRAP 00’0010_H

STUTRAP 00’0018_H

02_H

04_H

06_H

II

Stack Underflow

Class B Hardware Traps:

Undefined Opcode

Protected Instruction Fault

Illegal Word Operand Access ILLOPA

Illegal Instruction Access

UNDOPC BTRAP

00’0028_H

0A_H

I

PRTFLT

BTRAP

ILLINA

Illegal External Bus Access

ILLBUS

Reserved

[2C_H– 3C_H] [0B_H–

0F_H]

Software Traps:

TRAP Instruction

Any

Current

CPU

Priority

[00’0000_H– [00_H–

00’01FC_H] 7F_H]

in steps

of 4_H

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General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which

may be used for many different time related tasks such as event timing and counting,

pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate

modules, GPT1 and GPT2. Each timer in each module may operate independently in a

number of different modes, or may be concatenated with another timer of the same

module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for

one of four basic modes of operation, which are Timer, Gated Timer, Counter, and

Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from

the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer

to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the

operation of a timer is controlled by the ‘gate’ level on an external input pin. For these

purposes, each timer has one associated port pin (TxIN) which serves as gate or clock

input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD) to

facilitate eg. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected

to the incremental position sensor signals A and B via their respective inputs TxIN and

TxEUD. Direction and count signals are internally derived from these two input signals,

so the contents of the respective timer Tx corresponds to the sensor position. The third

position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-

flow/underflow. The state of this latch may be output on a port pin (T3OUT) eg. for time

out monitoring of external hardware components, or may be used internally to clock

timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload

or capture registers for timer T3. When used as capture or reload registers, timers T2

and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to

a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of

T2 or T4 triggered either by an external signal or by a selectable state transition of its

toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on

opposite state transitions of T3OTL with the low and high times of a PWM signal, this

signal can be constantly generated without software intervention.

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T2EUD

f_CPU

T2IN

U/D

Interrupt

Request

2ⁿ: 1

GPT1 Timer T2

T2

Mode

Control

Reload

Capture

Interrupt

Request

f_CPU

2ⁿ: 1

Toggle FF

T3OTL

T3

Mode

Control

T3IN

GPT1 Timer T3

T3OUT

U/D

T3EUD

Other

Timers

Capture

Reload

T4IN

T4

Mode

Control

Interrupt

Request

2ⁿ: 1

GPT1 Timer T4

U/D

f_CPU

T4EUD

MCT02141

Figure 6

Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control

and time measurement. It includes two timers (T5, T6) and a capture/reload register

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU

clock via a programmable prescaler. The count direction (up/down) for each timer is

programmable by software. Concatenation of the timers is supported via the output

toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/

underflow.

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The state of this latch may be used to clock timer T5. The overflows/underflows of timer

T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL

register may capture the contents of timer T5 based on an external signal transition on

the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the

capture procedure. This allows absolute time differences to be measured or pulse

multiplication to be performed without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of

GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3

operates in Incremental Interface Mode.

f_CPU

2ⁿ: 1

T5

Mode

Control

U/D

Interrupt

Request

GPT2 Timer T5

Clear

Capture

Interrupt

Request

T3

MUX

CT3

CAPIN

GPT2 CAPREL

Interrupt

Request

GPT2 Timer T6

U/D

T6OTL

T6OUT

T6

Mode

Control

Other

Timers

f_CPU

2ⁿ: 1

Mcb03999C.vsd

Figure 7

Block Diagram of GPT2

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Real Time Clock

The Real Time Clock (RTC) module of the C161PI consists of a chain of 3 divider blocks,

a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible

via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip

oscillator frequency divided by 32 via a separate clock driver (I_RTC= I_OSC/ 32) and is

therefore independent from the selected clock generation mode of the C161PI. All timers

count up.

The RTC module can be used for different purposes:

• System clock to determine the current time and date

• Cyclic time based interrupt

• 48-bit timer for long term measurements

T14REL

Reload

f_RTC

T14

8:1

Interrupt

Request

RTCL

Figure 8

RTC Block Diagram

Note: The registers associated with the RTC are not effected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

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A/D Converter

For analog signal measurement, a 10-bit A/D converter with 4 multiplexed input channels

and a sample and hold circuit has been integrated on-chip. It uses the method of

successive approximation. The sample time (for loading the capacitors) and the

conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register

(ADDAT): either an interrupt request will be generated when the result of a previous

conversion has not been read from the result register at the time the next conversion is

complete, or the next conversion is suspended in such a case until the previous result

has been read.

For applications which require less than 4 analog input channels, the remaining channel

inputs can be used as digital input port pins.

The A/D converter of the C161PI supports four different conversion modes. In the

standard Single Channel conversion mode, the analog level on a specified channel is

sampled once and converted to a digital result. In the Single Channel Continuous mode,

the analog level on a specified channel is repeatedly sampled and converted without

software intervention. In the Auto Scan mode, the analog levels on a prespecified

number of channels are sequentially sampled and converted. In the Auto Scan

Continuous mode, the number of prespecified channels is repeatedly sampled and

converted. In addition, the conversion of a specific channel can be inserted (injected) into

a running sequence without disturbing this sequence. This is called Channel Injection

Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the

conversion results into a table in memory for later evaluation, without requiring the

overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs

calibration cycles. This automatic self-calibration constantly adjusts the converter to

changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal

operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise

those pins used for analog input can be disconnected from the digital IO or input stages

under software control. This can be selected for each pin separately via registers

P5DIDIS (Port 5 Digital Input Disable).

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Serial Channels

Serial communication with other microcontrollers, processors, terminals or external

peripheral components is provided by two serial interfaces with different functionality, an

Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous

Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller

families and supports full-duplex asynchronous communication at up to 780 KBaud and

half-duplex synchronous communication at up to 3.1 MBaud @ 25 MHz CPU clock.

A dedicated baud rate generator allows to set up all standard baud rates without

oscillator tuning. For transmission, reception and error handling 4 separate interrupt

vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or

received, preceded by a start bit and terminated by one or two stop bits. For

multiprocessor communication, a mechanism to distinguish address from data bytes has

been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a

shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop

back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated, if the last

character received has not been read out of the receive buffer register at the time the

reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25 Mbaud @

25 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral

components. A dedicated baud rate generator allows to set up all standard baud rates

without oscillator tuning. For transmission, reception and error handling 3 separate

interrupt vectors are provided.

The SSC transmits or receives characters of 2...16 bits length synchronously to a shift

clock which can be generated by the SSC (master mode) or by an external master (slave

mode). The SSC can start shifting with the LSB or with the MSB and allows the selection

of shifting and latching clock edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. Transmit and receive error supervise the correct handling

of the data buffer. Phase and baudrate error detect incorrect serial data.

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I²C Module

The integrated I²C Bus Module handles the transmission and reception of frames over

the two-line I²C bus in accordance with the I²C Bus specification. The on-chip I²C Module

can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave

mode, in master mode or in multi-master mode.

Several physical interfaces (port pins) can be established under software control. Data

can be transferred at speeds up to 400 Kbit/sec.

Two interrupt nodes dedicated to the I²C module allow efficient interrupt service and also

support operation via PEC transfers.

Note: The port pins associated with the I²C interfaces feature open drain drivers only, as

required by the I²C specification.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be

disabled in the time interval until the EINIT (end of initialization) instruction has been

executed. Thus, the chip’s start-up procedure is always monitored. The software has to

be designed to service the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2

or by 128. The high byte of the Watchdog Timer register can be set to a prespecified

reload value (stored in WDTREL) in order to allow further variation of the monitored time

interval. Each time it is serviced by the application software, the high byte of the

Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 336 ms can be

monitored (@ 25 MHz).

The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).

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Parallel Ports

The C161PI provides up to 76 IO lines which are organized into six input/output ports

and one input port. All port lines are bit-addressable, and all input/output lines are

individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O

ports are true bidirectional ports which are switched to high impedance state when

configured as inputs. The output drivers of three IO ports can be configured (pin by pin)

for push/pull operation or open-drain operation via control registers. The other IO ports

operate in push/pull mode, except for the I²C interface pins which are open drain pins

only. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with

them. All port lines that are not used for these alternate functions may be used as general

purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external

memory, while Port 4 outputs the additional segment address bits A22/19/17...A16 in

systems where segmentation is enabled to access more than 64 KBytes of memory.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control

signal BHE and the system clock output CLKOUT (or the programmable frequency

output FOUT).

Port 5 is used for the analog input channels to the A/D converter or timer control signals.

Port 6 provides the optional chip select signals and interface lines for the I²C module.

The edge characteristics (transition time) of the C161PI’s port drivers can be selected

via the Port Driver Control Register (PDCR).

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Instruction Set Summary

The table below lists the instructions of the C161PI in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation

of the instructions, parameters for conditional execution of instructions, and the opcodes

for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailled description of each instruction.

Table 4

Mnemonic

ADD(B)

ADDC(B)

SUB(B)

SUBC(B)

MUL(U)

DIV(U)

Instruction Set Summary

Description

Bytes

2 / 4

Add word (byte) operands

Add word (byte) operands with Carry

Subtract word (byte) operands

Subtract word (byte) operands with Carry

(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

DIVL(U)

CPL(B)

NEG(B)

AND(B)

OR(B)

Complement direct word (byte) GPR

Negate direct word (byte) GPR

Bitwise AND, (word/byte operands)

Bitwise OR, (word/byte operands)

Bitwise XOR, (word/byte operands)

Clear direct bit

2

2 / 4

2

XOR(B)

BCLR

BSET

Set direct bit

2

BMOV(N)

Move (negated) direct bit to direct bit

AND/OR/XOR direct bit with direct bit

4

BAND, BOR,

BXOR

4

BCMP

Compare direct bit to direct bit

4

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

Compare word (byte) operands

2 / 4

Compare word data to GPR and decrement GPR by 1/2 2 / 4

Compare word data to GPR and increment GPR by 1/2

2 / 4

2

Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR

SHL / SHR

ROL / ROR

ASHR

Shift left/right direct word GPR

2

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

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Table 4

Instruction Set Summary (continued)

Description

Mnemonic

MOV(B)

MOVBS

MOVBZ

Bytes

Move word (byte) data

2 / 4

Move byte operand to word operand with sign extension 2 / 4

Move byte operand to word operand. with zero extension 2 / 4

JMPA, JMPI,

JMPR

Jump absolute/indirect/relative if condition is met

4

JMPS

J(N)B

JBC

Jump absolute to a code segment

4

Jump relative if direct bit is (not) set

Jump relative and clear bit if direct bit is set

Jump relative and set bit if direct bit is not set

JNBS

CALLA, CALLI,

CALLR

Call absolute/indirect/relative subroutine if condition is met 4

CALLS

PCALL

Call absolute subroutine in any code segment

4

Push direct word register onto system stack and call

absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

Push/pop direct word register onto/from system stack

2

4

PUSH, POP

SCXT

Push direct word register onto system stack und update

register with word operand

RET

Return from intra-segment subroutine

Return from inter-segment subroutine

2

RETS

RETP

Return from intra-segment subroutine and pop direct

word register from system stack

RETI

Return from interrupt service subroutine

Software Reset

2

SRST

4

IDLE

Enter Idle Mode

4

PWRDN

SRVWDT

DISWDT

EINIT

Enter Power Down Mode (supposes NMI-pin being low)

Service Watchdog Timer

4

Disable Watchdog Timer

4

Signify End-of-Initialization on RSTOUT-pin

Begin ATOMIC sequence

4

ATOMIC

EXTR

2

Begin EXTended Register sequence

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

Null operation

2

EXTP(R)

EXTS(R)

NOP

2 / 4

2

Data Sheet

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Special Function Registers Overview

The following table lists all SFRs which are implemented in the C161PI in alphabetical

order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the

Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-Peripherals (I²C) are marked with the letter “X” in

column “Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected

addressing mode, an SFR can be accessed via its physical address (using the Data

Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Table 5

Name

C161PI Registers, Ordered by Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

ADCIC

b FF98_H

CC_H

A/D Converter End of Conversion

Interrupt Control Register

0000_H

ADCON

b FFA0_H

D0_H

50_H

A/D Converter Control Register

A/D Converter Result Register

A/D Converter 2 Result Register

Address Select Register 1

Address Select Register 2

Address Select Register 3

Address Select Register 4

0000_H

ADDAT

FEA0_H

ADDAT2

F0A0_HE 50_H

ADDRSEL1

ADDRSEL2

ADDRSEL3

ADDRSEL4

ADEIC

FE18_H

FE1A_H

0C_H

0D_H

0E_H

0F_H

CD_H

FE1C_H

FE1E_H

b FF9A_H

A/D Converter Overrun Error Interrupt

Control Register

BUSCON0 b FF0C_H

BUSCON1 b FF14_H

BUSCON2 b FF16_H

BUSCON3 b FF18_H

BUSCON4 b FF1A_H

86_H

8A_H

8B_H

8C_H

8D_H

25_H

C4_H

C5_H

C6_H

C7_H

Bus Configuration Register 0

0000_H

Bus Configuration Register 1

Bus Configuration Register 2

Bus Configuration Register 3

Bus Configuration Register 4

CAPREL

CC8IC

FE4A_H

b FF88_H

b FF8A_H

b FF8C_H

b FF8E_H

GPT2 Capture/Reload Register

External Interrupt 0 Control Register

External Interrupt 1 Control Register

External Interrupt 2 Control Register

External Interrupt 3 Control Register

CC9IC

CC10IC

CC11IC

Data Sheet

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&ꢀꢁꢀ3,

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Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

C8_H

C9_H

CA_H

CB_H

08_H

CC12IC

CC13IC

CC14IC

CC15IC

CP

b FF90_H

External Interrupt 4 Control Register

External Interrupt 5 Control Register

External Interrupt 6 Control Register

External Interrupt 7 Control Register

CPU Context Pointer Register

0000_H

FC00_H

0000_H

b FF92_H

b FF94_H

b FF96_H

FE10_H

CRIC

b FF6A_H

FE08_H

B5_H

04_H

GPT2 CAPREL Interrupt Ctrl. Register

CSP

CPU Code Segment Pointer Register

(8 bits, not directly writeable)

DP0L

DP0H

DP1L

DP1H

DP2

b F100_HE 80_H

b F102_HE 81_H

b F104_HE 82_H

b F106_HE 83_H

P0L Direction Control Register

P0H Direction Control Register

P1L Direction Control Register

P1H Direction Control Register

Port 2 Direction Control Register

Port 3 Direction Control Register

Port 4 Direction Control Register

Port 6 Direction Control Register

00_H

b FFC2_H

b FFC6_H

b FFCA_H

b FFCE_H

FE00_H

E1_H

E3_H

E5_H

E7_H

00_H

0000_H

00_H

DP3

DP4

DP6

00_H

DPP0

CPU Data Page Pointer 0 Register (10

bits)

0000_H

DPP1

FE02_H

FE04_H

FE06_H

01_H

02_H

03_H

CPU Data Page Pointer 1 Reg. (10 bits)

CPU Data Page Pointer 2 Reg. (10 bits)

CPU Data Page Pointer 3 Reg. (10 bits)

External Interrupt Control Register

I²C Address Register

0001_H

0002_H

0003_H

0000_H

0XXX_H

XX00_H

0000_H

XX_H

DPP2

DPP3

EXICON

ICADR

ICCFG

ICCON

ICRTB

ICST

b F1C0_HE E0_H

ED06_HX ---

ED00_HX ---

ED02_HX ---

ED08_HX ---

ED04_HX ---

F07C_HE 3E_H

F07E_HE 3F_H

F07A_HE 3D_H

I²C Configuration Register

I²C Control Register

I²C Receive/Transmit Buffer

I²C Status Register

0000_H

09XX_H

1820_H

0000_H

IDCHIP

IDMANUF

IDMEM

Identifier

Data Sheet

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&ꢀꢁꢀ3,

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Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

IDPROG

ISNC

MDC

F078_HE 3C_H

Identifier

0000_H

00_H

b F1DE_HE EF_H

Interrupt Subnode Control Register

CPU Multiply Divide Control Register

CPU Multiply Divide Reg. – High Word

CPU Multiply Divide Reg. – Low Word

Port 2 Open Drain Control Register

Port 3 Open Drain Control Register

Port 6 Open Drain Control Register

Constant Value 1’s Register (read only)

Port 0 Low Reg. (Lower half of PORT0)

Port 0 High Reg. (Upper half of PORT0)

Port 1 Low Reg. (Lower half of PORT1)

Port 1 High Reg. (Upper half of PORT1)

Port 2 Register

b FF0E_H

FE0C_H

87_H

06_H

07_H

MDH

MDL

FE0E_H

ODP2

ODP3

ODP6

ONES

P0L

b F1C2_HE E1_H

b F1C6_HE E3_H

b F1CE_HE E7_H

b FF1E_H

b FF00_H

b FF02_H

b FF04_H

b FF06_H

b FFC0_H

b FFC4_H

b FFC8_H

b FFA2_H

b FFA4_H

b FFCC_H

FEC0_H

8F_H

80_H

81_H

82_H

83_H

E0_H

E2_H

E4_H

D1_H

D2_H

E6_H

60_H

61_H

62_H

63_H

64_H

65_H

66_H

67_H

88_H

FFFF_H

00_H

P0H

00_H

P1L

00_H

P1H

00_H

P2

0000_H

00_H

P3

Port 3 Register

P4

Port 4 Register (7 bits)

P5

Port 5 Register (read only)

XXXX_H

0000_H

00_H

P5DIDIS

P6

Port 5 Digital Input Disable Register

Port 6 Register (8 bits)

PECC0

PECC1

PECC2

PECC3

PECC4

PECC5

PECC6

PECC7

PSW

PEC Channel 0 Control Register

PEC Channel 1 Control Register

PEC Channel 2 Control Register

PEC Channel 3 Control Register

PEC Channel 4 Control Register

PEC Channel 5 Control Register

PEC Channel 6 Control Register

PEC Channel 7 Control Register

CPU Program Status Word

0000_H

XX_H

FEC2_H

FEC4_H

FEC6_H

FEC8_H

FECA_H

FECC_H

FECE_H

b FF10_H

PDCR

RP0H

F0AA_HE 55_H

Pin Driver Control Register

b F108_HE 84_H

System Startup Config. Reg. (Rd. only)

Data Sheet

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Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

RTCH

RTCL

S0BG

F0D6_HE 6B_H

F0D4_HE 6A_H

RTC High Register

RTC Low Register

no

FEB4_H

5A_H

Serial Channel 0 Baud Rate Generator

Reload Register

0000_H

S0CON

S0EIC

b FFB0_H

b FF70_H

D8_H

B8_H

Serial Channel 0 Control Register

0000_H

Serial Channel 0 Error Interrupt Control

Register

S0RBUF

S0RIC

FEB2_H

59_H

B7_H

Serial Channel 0 Receive Buffer Reg.

(read only)

XXXX_H

0000_H

b FF6E_H

Serial Channel 0 Receive Interrupt

Control Register

S0TBIC

S0TBUF

S0TIC

b F19C_HE CE_H

Serial Channel 0 Transmit Buffer

Interrupt Control Register

FEB0_H

b FF6C_H

FE12_H

58_H

B6_H

09_H

Serial Channel 0 Transmit Buffer Reg.

(write only)

Serial Channel 0 Transmit Interrupt

Control Register

SP

CPU System Stack Pointer Register

SSC Baudrate Register

FC00_H

0000_H

XXXX_H

0000_H

FA00_H

FC00_H

¹⁾0xx0_H

0000_H

no

SSCBR

F0B4_HE 5A_H

SSCCON b FFB2_H

D9_H

BB_H

SSC Control Register

SSCEIC

SSCRB

SSCRIC

SSCTB

SSCTIC

STKOV

STKUN

b FF76_H

SSC Error Interrupt Control Register

SSC Receive Buffer

F0B2_HE 59_H

b FF74_H

BA_H

SSC Receive Interrupt Control Register

SSC Transmit Buffer

F0B0_HE 58_H

b FF72_H

B9_H

0A_H

0B_H

89_H

SSC Transmit Interrupt Control Register

CPU Stack Overflow Pointer Register

CPU Stack Underflow Pointer Register

CPU System Configuration Register

CPU System Configuration Register 2

CPU System Configuration Register 3

RTC Timer 14 Register

FE14_H

FE16_H

SYSCON b FF12_H

SYSCON2 b F1D0_HE E8_H

SYSCON3 b F1D4_HE EA_H

T14

F0D2_HE 69_H

Data Sheet

34

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&ꢀꢁꢀ3,

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Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

T14REL

T2

F0D0_HE 68_H

RTC Timer 14 Reload Register

GPT1 Timer 2 Register

no

0000_H

²⁾00xx_H

0000_H

FE40_H

b FF40_H

b FF60_H

FE42_H

20_H

A0_H

B0_H

21_H

A1_H

B1_H

22_H

A2_H

B2_H

23_H

A3_H

B3_H

24_H

A4_H

B4_H

D6_H

57_H

D7_H

T2CON

T2IC

GPT1 Timer 2 Control Register

GPT1 Timer 2 Interrupt Control Register

GPT1 Timer 3 Register

T3

T3CON

T3IC

b FF42_H

b FF62_H

FE44_H

GPT1 Timer 3 Control Register

GPT1 Timer 3 Interrupt Control Register

GPT1 Timer 4 Register

T4

T4CON

T4IC

b FF44_H

b FF64_H

FE46_H

GPT1 Timer 4 Control Register

GPT1 Timer 4 Interrupt Control Register

GPT2 Timer 5 Register

T5

T5CON

T5IC

b FF46_H

b FF66_H

FE48_H

GPT2 Timer 5 Control Register

GPT2 Timer 5 Interrupt Control Register

GPT2 Timer 6 Register

T6

T6CON

T6IC

b FF48_H

b FF68_H

b FFAC_H

FEAE_H

GPT2 Timer 6 Control Register

GPT2 Timer 6 Interrupt Control Register

Trap Flag Register

TFR

WDT

Watchdog Timer Register (read only)

Watchdog Timer Control Register

I²C Data Interrupt Control Register

I²C Protocol Interrupt Control Register

X-Peripheral 2 Interrupt Control Register

RTC Interrupt Control Register

Constant Value 0’s Register (read only)

WDTCON

XP0IC

XP1IC

XP2IC

XP3IC

ZEROS

FFAE_H

b F186_HE C3_H

b F18E_HE C7_H

b F196_HE CB_H

b F19E_HE CF_H

b FF1C_H

8E_H

1) The system configuration is selected during reset.

2) The reset value depends on the indicated reset source.

Data Sheet

35

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Absolute Maximum Ratings

Table 6

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

min. max.

Unit Notes

Storage temperature

7_ST

-65

150

°C

V

Voltage on 9_DDpins with 9_DD

respect to ground (9_SS)

-0.5

6.5

Voltage on any pin with

respect to ground (9_SS)

9_IN

-0.5

-10

-

9_DD+0.5

10

V

Input current on any pin

during overload condition

mA

Absolute sum of all input

currents during overload

condition

|100|

Power dissipation

3_DISS

ꢀ

1.5

W

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (9_IN>9_DDor 9_IN<9_SS) the

voltage on 9_DDpins with respect to ground (9_SS) must not exceed the values

defined by the absolute maximum ratings.

Data Sheet

36

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Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the C161PI. All parameters specified in the following sections refer to these

operating conditions, unless otherwise noticed.

Table 7

Operating Condition Parameters

Parameter

Symbol

Limit Values

min. max.

4.5 5.5

Unit Notes

Standard

digital supply voltage

9_DD

V

Active mode,

_CPUmax= 25 MHz

I

2.5 ¹⁾

3.0

5.5

3.6

V

PowerDown mode

Reduced

9_DD

Active mode,

digital supply voltage

I_CPUmax= 20 MHz

2.5 ¹⁾

3.6

V

PowerDown mode

Digital ground voltage

Overload current

9_SS

0

Reference voltage

3)

,

-

±5

mA Per pin ²⁾

OV

3)

Absolute sum of overload Σ|,_OV|

50

mA

currents

External Load

Capacitance

&

L

-

100

pF

Pin drivers in

fast edge mode

(PDCR.BIPEC =

’0’)

-

50

pF

Pin drivers in

reduced edge

mode

(PDCR.BIPEC =

’1’) ³⁾

Ambient temperature

7_A

0

70

°C

SAB-C161PI...

SAF-C161PI...

SAK-C161PI...

-40

85

125

1) Output voltages and output currents will be reduced when 9_DDleaves the range defined for active mode.

2) Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e. 9_OV! 9_DD+0.5V or 9_OVꢁ 9_SS-0.5V). The absolute sum of input overload

currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits.

3) Not 100% tested, guaranteed by design characterization.

Data Sheet

37

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Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161PI

and partly its demands on the system. To aid in interpreting the parameters right, when

evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C161PI will provide signals with the respective timing characteristics.

SR (System Requirement):

The external system must provide signals with the respective timing characteristics to

the C161PI.

DC Characteristics (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Limit Values Unit Test Condition

min.

max.

Input low voltage XTAL1,

P3.0, P3.1, P6.5, P6.6, P6.7

9_IL1SR – 0.5

9_ILSR – 0.5

9_ILSSR – 0.5

0.3 V_DD

V

–

Input low voltage

(TTL)

0.2 9_DD

– 0.1

V

–

Input low voltage

2.0

V

–

(Special Threshold)

Input high voltage RSTIN

9_IH1SR 0.6 9_DD9_DD

+

V

–

0.5

Input high voltage XTAL1,

P3.0, P3.1, P6.5, P6.6, P6.7

9_IH2SR 0.7 9_DD9_DD

V

–

0.5

Input high voltage

(TTL)

9_IHSR 0.2 9_DD9_DD

V

–

+ 0.9

0.5

Input high voltage

(Special Threshold)

9_IHSSR 0.8 9_DD9_DD

V

–

- 0.2

400

0.5

–

Input Hysteresis

(Special Threshold)

HYS

mV

V

–

Output low voltage

9_OLCC –

0.45

,_OL= 2.4 mA

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT)

Output low voltage

9_OL2CC –

0.4

V

,_OL2= 3 mA

(P3.0, P3.1, P6.5, P6.6, P6.7)

Data Sheet

38

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DC Characteristics (Standard Supply Voltage Range) (continued)

(Operating Conditions apply)

Parameter

Symbol

Limit Values

min. max.

0.45

Unit Test Condition

Output low voltage

(all other outputs)

Output high voltage ¹⁾

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT)

9

_OL1CC –

9_OHCC 2.4

0.9 9_DD

V

,_OL= 1.6 mA

–

,

_OH= -2.4 mA

_OH= -0.5 mA

Output high voltage ¹⁾

(all other outputs)

9

_OH1CC 2.4

0.9 9_DD

CC –

–

V

,

_OH= -1.6 mA

_OH= -0.5 mA

–

Input leakage current (Port 5)

Input leakage current (all other)

,

±200

±500

-10

–

nA 0.45V < 9_IN< 9_DD

µA 9_IN= 9_IH1

OZ1

,

CC –

OZ2

2)

3)

RSTIN inactive current

RSTIN active current ²⁾

–

RSTH

RSTL

RWH

RWL

ALEL

ALEH

P6H

4)

-100

µA 9_IN= 9_IL

5)

3)

4)

Read/Write inactive current

Read/Write active current ⁵⁾

–

-40

–

µA

9

_OUT= 2.4 V

_OUT= 9_OLmax

_OUT= 2.4 V

_OUT= 9_OL1max

-500

–

5)

3)

4)

3)

ALE inactive current

40

–

ALE active current ⁵⁾

500

–

5)

Port 6 inactive current

-40

–

5)

4)

3)

4)

Port 6 active current

-500

–

P6L

P0H

P0L

IL

5)

PORT0 configuration current

-10

–

µA 9_IN= 9_IHmin

µA 9_IN= 9_ILmax

µA 0 V < 9_IN< 9_DD

-100

XTAL1 input current

CC –

±20

10

6)

Pin capacitance

&

pF

I = 1 MHz

7_A= 25 °C

IO

(digital inputs/outputs)

Power supply current (5V active) ,_DD5

with all peripherals active

–

1 +

2*I_CPU

mA RSTIN = 9_IL2

_CPUin [MHz] ⁷⁾

mA RSTIN = 9_IH1

_CPUin [MHz] ⁷⁾

µA RSTIN = 9_IH1

_OSCin [MHz] ⁷⁾

I

Idle mode supply current (5V)

with all peripherals active

,

1 +

0.8*I_CPU

IDX5

I

8)

Idle mode supply current (5V)

with all peripherals deactivated,

PLL off, SDD factor = 32

–

500 +

50*I_OSC

IDO5

I

Data Sheet

39

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&ꢀꢁꢀ3,

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DC Characteristics (Standard Supply Voltage Range) (continued)

(Operating Conditions apply)

Parameter

Symbol

Limit Values Unit Test Condition

min.

max.

8)

Power-down mode supply

current (5V) with RTC running

,

–

200 +

25*I_OSC

µA

9

_DD= 9_DDmax

PDR5

9)

I_OSCin [MHz]

Power-down mode supply

,

50

9_DD= 9_DDmax

PDO5

current (5V) with RTC disabled

1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 KΩ.

3) The maximum current may be drawn while the respective signal line remains inactive.

4) The minimum current must be drawn in order to drive the respective signal line active.

5) This specification is only valid during Reset, or during Hold- or Adapt-mode. During Hold mode Port 6 pins are

only affected, if they are used (configured) for CS output and the open drain function is not enabled.

6) Not 100% tested, guaranteed by design characterization.

7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.

These parameters are tested at 9_DDmaxand maximum CPU clock with all outputs disconnected and all inputs

at 9_ILor 9_IH.

The oscillator also contributes to the total supply current. The given values refer to the worst case, ie. I_PDRmax

.

For lower oscillator frequencies the respective supply current can be reduced accordingly.

8) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is

influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry

and may change in case of a not optimized external oscillator circuitry.

9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at 9_DD– 0.1 V to 9_DD, 9_REF= 0 V, all outputs (including pins configured as outputs) disconnected.

Data Sheet

40

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DC Characteristics (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Input low voltage XTAL1,

P3.0, P3.1, P6.5, P6.6, P6.7

9_IL1SR – 0.5

9_ILSR – 0.5

9_ILSSR – 0.5

0.3 V_DD

V

–

Input low voltage

(TTL)

0.8

1.3

V

–

Input low voltage

V

–

(Special Threshold)

Input high voltage RSTIN

9_IH1SR 0.6 9_DD9_DD

+

V

–

0.5

Input high voltage XTAL1,

P3.0, P3.1, P6.5, P6.6, P6.7

9_IH2SR 0.7 9_DD9_DD

V

–

0.5

Input high voltage

(TTL)

9_IHSR 1.8

9_DD

0.5

V

–

Input high voltage

(Special Threshold)

9_IHSSR 0.8 9_DD9_DD

V

–

- 0.2

0.5

Input Hysteresis

(Special Threshold)

HYS

250

–

mV

V

–

Output low voltage

9_OLCC –

0.45

,_OL= 1.6 mA

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT)

Output low voltage

P3.0, P3.1, P6.5, P6.6, P6.7

9

_OL2CC –

_OL1CC –

0.4

0.45

–

V

,

_OL2= 1.6 mA

Output low voltage

(all other outputs)

Output high voltage ¹⁾

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT)

9

,_OL= 1.0 mA

9_OHCC 0.9 9_DD

,

_OH= -0.5 mA

_OH= -0.25 mA

Output high voltage ¹⁾

(all other outputs)

9_OH1CC 0.9 9_DD

–

V

Input leakage current (Port 5)

,

CC –

±200

±500

-10

nA 0.45V < 9_IN< 9_DD

µA 9_IN= 9_IH1

OZ1

Input leakage current (all other)

,

CC –

OZ2

2)

3)

RSTIN inactive current

–

RSTH

Data Sheet

41

1999-07

&ꢀꢁꢀ3,

ꢂ

DC Characteristics (continued) (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Limit Values Unit Test Condition

min.

-100

max.

4)

RSTIN active current ²⁾

,

–

µA 9_IN= 9_IL

RSTL

5)

3)

Read/Write inactive current

Read/Write active current ⁵⁾

,

–

-10

–

µA

9_OUT= 2.4 V

9_OUT= 9_OLmax

9_OUT= 2.4 V

9_OUT= 9_OL1max

RWH

4)

,

-500

–

RWL

5)

3)

ALE inactive current

,

20

–

ALEL

4)

ALE active current ⁵⁾

,

500

–

ALEH

5)

3)

Port 6 inactive current

,

-10

–

P6H

5)

4)

Port 6 active current

,

-500

–

P6L

5)

3)

PORT0 configuration current

,

-5

µA 9_IN= 9_IHmin

µA 9_IN= 9_ILmax

µA 0 V < 9_IN< 9_DD

P0H

4)

,

-100

–

P0L

XTAL1 input current

,

CC –

±20

10

IL

6)

Pin capacitance

&

pF

I = 1 MHz

7_A= 25 °C

IO

(digital inputs/outputs)

Power supply current (3V active) ,_DD3

with all peripherals active

–

1 +

1.1*I_CPU

mA RSTIN = 9_IL2

_CPUin [MHz] ⁷⁾

mA RSTIN = 9_IH1

_CPUin [MHz] ⁷⁾

µA RSTIN = 9_IH1

_OSCin [MHz] ⁷⁾

I

Idle mode supply current (3V)

with all peripherals active

,

1 +

0.5*I_CPU

IDX3

IDO3

I

8)

Idle mode supply current (3V)

with all peripherals deactivated,

PLL off, SDD factor = 32

300 +

30*I_OSC

I

8)

Power-down

current (3V) with RTC running

Power-down mode supply ,_PDO3

current (3V) with RTC disabled

mode

supply ,_PDR3

–

100 +

10*I_OSC

µA

9_DD= 9_DDmax

9)

I_OSCin [MHz]

30

9_DD= 9_DDmax

1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 KΩ.

3) The maximum current may be drawn while the respective signal line remains inactive.

4) The minimum current must be drawn in order to drive the respective signal line active.

5) This specification is only valid during Reset, or during Hold- or Adapt-mode. During Hold mode Port 6 pins are

only affected, if they are used (configured) for CS output and the open drain function is not enabled.

6) Not 100% tested, guaranteed by design characterization.

Data Sheet

42

1999-07

&ꢀꢁꢀ3,

ꢂ

7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.

These parameters are tested at 9_DDmaxand maximum CPU clock with all outputs disconnected and all inputs

at 9_ILor 9_IH.

The oscillator also contributes to the total supply current. The given values refer to the worst case, ie. I_PDRmax

.

For lower oscillator frequencies the respective supply current can be reduced accordingly.

8) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is

influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry

and may change in case of a not optimized external oscillator circuitry.

9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at 9_DD– 0.1 V to 9_DD, 9_REF= 0 V, all outputs (including pins configured as outputs) disconnected.

1500

,

1250

1000

,

750

,

500

,

250

,

I

_OSC[MHz]

4

8

12

16

Figure 9

Idle and Power Down Supply Current as a Function of Oscillator

Frequency

Data Sheet

43

1999-07

&ꢀꢁꢀ3,

ꢂ

I_DD5max

50

I_DD5typ

25

I_DD3max

I_DD3typ

I_ID5max

I_ID5typ

I_ID3max

I_ID3typ

5

10

15

20

25

I

_CPU[MHz]

Figure 10

Supply/Idle Current as a Function of Operating Frequency

Data Sheet

44

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristics

Definition of Internal Timing

The internal operation of the C161PI is controlled by the internal CPU clock f_CPU. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)

operations.

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see figure below).

3KDVHꢂ/RFNHGꢂ/RRSꢂ2SHUDWLRQ

I

TCLTCL

'LUHFWꢂ&ORFNꢂ'ULYH

I

TCLTCL

3UHVFDOHUꢂ2SHUDWLRQ

I

TCL

Figure 11

Generation Mechanisms for the CPU Clock

The CPU clock signal I_CPUcan be generated from the oscillator clock signal I_OSCvia

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate I_CPU. This influence must

be regarded when calculating the timings for the C161PI.

Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.

The used mechanism to generate the CPU clock is selected during reset via the logic

levels on pins P0.15-13 (P0H.7-5).

The table below associates the combinations of these three bits with the respective clock

generation mode.ꢂ

Data Sheet

45

1999-07

&ꢀꢁꢀ3,

ꢂ

Table 8

C161PI Clock Generation Modes

CPU Frequency External Clock

P0.15-13

(P0H.7-5)

Notes

I

_CPU= I_OSC* F

Input Range ¹⁾

2.5 to 6.25 MHz

3.33 to 8.33 MHz

5 to 12.5 MHz

2 to 5 MHz

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

I

_OSC* 4

_OSC* 3

_OSC* 2

_OSC* 5

_OSC* 1

Default configuration

1 to 25 MHz

Direct drive ²⁾

I

_OSC* 1.5

_OSC/ 2

_OSC* 2.5

6.66 to 16.6 MHz

2 to 50 MHz

I

CPU clock via prescaler

I

4 to 10 MHz

1) The external clock input range refers to a CPU clock range of 10...25 MHz.

2) The maximum frequency depends on the duty cycle of the external clock signal.

Prescaler Operation

When pins P0.15-13 (P0H.7-5) equal 001_Bduring reset the CPU clock is derived from

the internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of I_CPUis half the frequency of I_OSCand the high and low time of I_CPU(i.e.

the duration of an individual TCL) is defined by the period of the input clock I_OSC

.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

calculated using the period of I_OSCfor any TCL.

Phase Locked Loop

For all combinations of pins P0.15-13 (P0H.7-5) except for 001_Band 011_Bthe on-chip

phase locked loop is enabled and provides the CPU clock (see table above). The PLL

multiplies the input frequency by the factor F which is selected via the combination of

pins P0.15-13 (i.e. I_CPU= I_OSC* F). With every F’th transition of I_OSCthe PLL circuit

synchronizes the CPU clock to the input clock. This synchronization is done smoothly,

i.e. the CPU clock frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of I_CPUis constantly adjusted so

it is locked to I_OSC. The slight variation causes a jitter of I_CPUwhich also effects the

duration of individual TCLs.

Data Sheet

46

1999-07

&ꢀꢁꢀ3,

ꢂ

The timings listed in the AC Characteristics that refer to TCLs therefore must be

calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is

constantly adjusting its output frequency so it corresponds to the applied input frequency

(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than

for one single TCL (see formula and figure below).

For a period of N * TCL the minimum value is computed using the corresponding

deviation D_N:

(N * TCL)_min= N * TCL_NOM- D_N

D_N[ns] = ±(13.3 + N*6.3) / I_CPU[MHz],

where N = number of consecutive TCLs and 1 ≤ N ≤ 40.

So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D₃= (13.3 + 3 * 6.3) / 25 = 1.288 ns,

and (3TCL)_min= 3TCL_NOM- 1.288 ns = 58.7 ns (@ I_CPU= 25 MHz).

This is especially important for bus cycles using waitstates and e.g. for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter

is neglectible.

Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below).

Max.jitter D [ns]

10 MHz

±26.5

This approximated formula is valid for

1 ≤ 1 ≤ 40 and 10MHz ≤ f_CPU≤ 25MHz.

±20

16 MHz

20 MHz

±10

±1

25 MHz

1

5

10

20

40

N

Figure 12

Approximated Maximum Accumulated PLL Jitter

Data Sheet

47

1999-07

&ꢀꢁꢀ3,

ꢂ

Direct Drive

When pins P0.15-13 (P0H.7-5) equal 011_Bduring reset the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input

clock signal.

The frequency of I_CPUdirectly follows the frequency of I_OSCso the high and low time of

I

_CPU(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

I_OSC

.

The timings listed below that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective circumstances. This minimum value

can be calculated via the following formula:

TCL_min= 1/I_OSC* DC_min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of I_OSCis compensated

so the duration of 2TCL is always 1/I_OSC. The minimum value TCL_mintherefore has to be

used only once for timings that require an odd number of TCLs (1,3,...). Timings that

require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/I_OSC

.

Note: The address float timings in Multiplexed bus mode (W₁₁and W₄₅) use the maximum

duration of TCL (TCL_max= 1/I_OSC* DC_max) instead of TCL_min.

Data Sheet

48

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristicsꢂꢂ

External Clock Drive XTAL1 (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

Oscillator period W_OSCSR 40

max.

min.

max.

min.

60 ¹⁾

max.

500 ¹⁾ns

–

20

6

–

6

High time ²⁾

Low time ²⁾

Rise time ²⁾

Fall time ²⁾

W₁SR 20 ³⁾

W₂SR 20 ³⁾

–

10

–

ns

–

6

–

W₃SR

W₄SR

–

10

–

10

–

1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation

mode. Please see respective table above.

2) The clock input signal must reach the defined levels 9_ILand 9_IH2

.

3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (I_CPU) in

direct drive mode depends on the duty cycle of the clock input signal.

AC Characteristicsꢂꢂ

External Clock Drive XTAL1 (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

max.

min.

max.

min.

60 ¹⁾

max.

500 ¹⁾ns

Oscillator period W_OSCSR 50

–

25

8

–

6

High time ²⁾

Low time ²⁾

Rise time ²⁾

Fall time ²⁾

W₁SR 25 ³⁾

W₂SR 25 ³⁾

–

10

–

ns

–

8

–

W₃SR

W₄SR

–

10

–

10

–

1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation

mode. Please see respective table above.

2) The clock input signal must reach the defined levels 9_ILand 9_IH2

.

3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (I_CPU) in

direct drive mode depends on the duty cycle of the clock input signal.

Data Sheet

49

1999-07

&ꢀꢁꢀ3,

ꢂ

Figure 13

External Clock Drive XTAL1

Note: The main oscillator is optimized for oscillation with a crystal within a frequency

range of 4...16 MHz. When driven by an external clock signal it will accept the

specified frequency range. Operation at lower input frequencies is possible but is

guaranteed by design only (not 100% tested).

It is strongly recommended to measure the oscillation allowance (or margin) in the

final target system (layout) to determine the optimum parameters for the oscillator

operation.

Data Sheet

50

1999-07

&ꢀꢁꢀ3,

ꢂ

A/D Converter Characteristics

(Operating Conditions apply)

4.0V (2.6V)ꢂ≤ꢂ9_AREF≤ 9_DD+ 0.1V (Note the influence on TUE.)

9_SS- 0.1V ≤ 9_AGND≤ 9_SS+ 0.2V

Parameter

Symbol

Limit Values

min. max.

9_AINSR 9_AGND

Unit Test Condition

1)

Analog input voltage range

Basic clock frequency

Conversion time

9_AREF

V

2)

I_BC

W_C

0.5

CC –

6.25

MHz

3)

40 W_BC

+

W_S+2W_CPU

W_CPU= 1 / I_CPU

LSB 9_AREF≥ 4.0 V ⁵⁾

Total unadjusted error

TUE CC –

± 2

4)

–

± 4

LSB 9_AREF≥ 2.6 V

Internal resistance of

5_AREFSR –

W_BC/ 60

kΩ

W

_BCin [ns] ^{6) 7)}

reference voltage source

- 0.25

Internal resistance of analog 5_ASRCSR –

source

W_S/ 450 kΩ W_Sin [ns] ^{7) 8)}

- 0.25

7)

ADC input capacitance

&

CC –

33

pF

AIN

1) 9_AINmay exceed 9_AGNDor 9_AREFup to the absolute maximum ratings. However, the conversion result in these

cases will be X000_Hor X3FF_H, respectively.

2) The limit values for I_BCmust not be exceeded when selecting the CPU frequency and the ADCTC setting.

3) This parameter includes the sample time W_S, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the basic clock W_BCdepend on the conversion time programming.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

4) TUE is tested at 9_AREF=5.0V (3.3V),ꢂ9_AGND=0V, 9_DD=4.9V (3.2V). It is guaranteed by design for all other

voltages within the defined voltage range.

The specified TUE is guaranteed only if an overload condition (see ,_OVspecification) occurs on maximum 2 not

selected analog input pins and the absolute sum of input overload currents on all analog input pins does not

exceed 10 mA.

During the reset calibration sequence the maximum TUE may be ±4 LSB (±8 LSB @ 3V).

5) This case is not applicable for the reduced supply voltage range.

6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within each conversion step. The maximum internal resistance results from the programmed conversion timing.

7) Not 100% tested, guaranteed by design.

8) During the sample time the input capacitance &_Ican be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within W_S.

After the end of the sample time W_S, changes of the analog input voltage have no effect on the conversion result.

Values for the sample time W_Sdepend on programming and can be taken from the table below.

Data Sheet

51

1999-07

&ꢀꢁꢀ3,

ꢂ

Sample time and conversion time of the C161PI’s A/D Converter are programmable. The

table below should be used to calculate the above timings.

The limit values for I_BCmust not be exceeded when selecting ADCTC.

Table 9

A/D Converter Computation Table

ADCON.15|14 A/D Converter

ADCON.13|12 Sample time

(ADCTC)

Basic clock I_BC

(ADSTC)

W_S

00

01

10

11

I_CPU/ 4

I_CPU/ 2

I_CPU/ 16

I_CPU/ 8

00

01

10

11

W

_BC* 8

_BC* 16

_BC* 32

_BC* 64

Converter Timing Example:

Assumptions:

I_CPU= 25 MHz (i.e. W_CPU= 40 ns), ADCTC = ’00’, ADSTC = ’00’.

Basic clock

Sample time

I_BC

W_S

= I_CPU/ 4 = 6.25 MHz, i.e. W_BC= 160 ns.

= W_BC* 8 = 1280 ns.

Conversion time W_C

= W_S+ 40 W_BC+ 2 W_CPU= (1280 + 6400 + 80) ns = 7.8 µs.

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx

registers and represent the special characteristics of the programmed memory cycle.

The following table describes, how these variables are to be computed.

Table 10

Memory Cycle Variables

Symbol Values

Description

ALE Extension

W_A

TCL * <ALECTL>

Memory Cycle Time Waitstates W_C

2TCL * (15 - <MCTC>)

2TCL * (1 - <MTTC>)

Memory Tristate Time

W_F

Data Sheet

52

1999-07

&ꢀꢁꢀ3,

ꢂ

Testing Waveforms

2.4 V

1.8 V

0.8 V

1.8 V

0.8 V

Test Points

0.45 V

AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.45 V for a logic ‘0’.

Timing measurements are made at 9_IHmin for a logic ’1’ and 9_ILmax for a logic ’0’.

Figure 14

Input Output Waveforms

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

but begins to float when a 100 mV change from the loaded 9_OH/9_OLlevel occurs (,_OH/,_OL= 20 mA).

Figure 15

Float Waveforms

Data Sheet

53

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristics

Multiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2W_A+ W_C+ W_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max.

min.

max.

ALE high time

W₅CC 10 + W_A

W₆CC 4 +ꢂW_A

W₇CC 10 +ꢂW_A

W₈CC 10 +ꢂW_A

W₉CC -10 +ꢂW_A

W₁₀CC –

–

TCL - 10

+ꢂW_A

–

6

ns

Address setup to ALE

Address hold after ALE

–

TCL - 16

+ꢂW_A

–

TCL - 10

+ꢂW_A

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ꢂW_A

ALE falling edge to RD,

WR (no RW-delay)

–

-10 +ꢂW_A

Address float after RD,

WR (with RW-delay)

6

–

Address float after RD,

WR (no RW-delay)

W₁₁CC –

26

TCL + 6

RD, WR low time

(with RW-delay)

W₁₂CC 30 +ꢂW_C

W₁₃CC 50 +ꢂW_C

W₁₄SR –

–

2TCL - 10 –

+ꢂW_C

RD, WR low time

(no RW-delay)

–

3TCL-

10+W_C

–

RD to valid data in

(with RW-delay)

20 +ꢂW_C

40 +ꢂW_C

–

0

–

2TCL - 20 ns

+ꢂW_C

RD to valid data in

(no RW-delay)

W₁₅SR –

3TCL - 20 ns

+ꢂW_C

ALE low to valid data in

W₁₆SR –

40 + W_A

+ W_C

3TCL - 20 ns

+ꢂW_A+ꢂW_C

Address to valid data in

W₁₇SR –

50 + 2W_A

+ W_C

4TCL - 30 ns

+ꢂ2W_A+ꢂW_C

Data hold after RD

rising edge

W₁₈SR 0

–

ns

Data float after RD

W₁₉SR –

26 +ꢂW_F

2TCL - 14 ns

+ꢂW_F

Data Sheet

54

1999-07

&ꢀꢁꢀ3,

ꢂ

Multiplexed Bus (Standard Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2W_A+ W_C+ W_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max.

min.

max.

Data valid to WR

W₂₂CC 20 +ꢂW_C

–

2TCL - 20 –

+ꢂW_C

ns

Data hold after WR

W₂₃CC 26 +ꢂW_F

–

2TCL - 14 –

+ꢂW_F

ALE rising edge after RD, W₂₅CC 26 +ꢂW_F

WR

–

2TCL - 14 –

+ꢂW_F

Address hold after RD,

WR

ALE falling edge to CS ¹⁾W₃₈CC -4 -ꢂW_A

CS low to Valid Data In ¹⁾W₃₉SR –

W₂₇CC 26 +ꢂW_F

–

2TCL - 14 –

+ꢂW_F

10 - W_A

-4 -ꢂW_A

10 -ꢂW_A

40

–

3TCL - 20 ns

+ꢂW_Cꢂ

+ꢂ2W_A

+ꢂW_C+ 2W_A

CS hold after RD, WR ¹⁾W₄₀CC 46 +ꢂW_F

–

3TCL - 14 –

ns

+W_F

ALE fall. edge to RdCS, W₄₂CC 16 +ꢂW_A

WrCS (with RW delay)

–

TCL - 4

+ꢂW_A

–

ALE fall. edge to RdCS, W₄₃CC -4 +ꢂW_A

WrCS (no RW delay)

–

-4

+ꢂW_A

–

Address float after RdCS, W₄₄CC –

WrCS (with RW delay)

0

–

0

Address float after RdCS, W₄₅CC –

WrCS (no RW delay)

20

TCL

RdCS to Valid Data In

(with RW delay)

W₄₆SR –

W₄₇SR –

16 +ꢂW_C

2TCL - 24 ns

+ꢂW_C

RdCS to Valid Data In

(no RW delay)

36 +ꢂW_C

3TCL - 24 ns

+ꢂW_C

RdCS, WrCS Low Time W₄₈CC 30 +ꢂW_C

(with RW delay)

–

2TCL - 10 –

+ꢂW_C

ns

RdCS, WrCS Low Time W₄₉CC 50 +ꢂW_C

3TCL - 10 –

(no RW delay)

+ꢂW_C

Data Sheet

55

1999-07

&ꢀꢁꢀ3,

ꢂ

Multiplexed Bus (Standard Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2W_A+ W_C+ W_F(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max.

min.

max.

Data valid to WrCS

W₅₀CC 26 +ꢂW_C

–

2TCL - 14 –

ns

+ꢂW_C

Data hold after RdCS

Data float after RdCS

W₅₁SR 0

W₅₂SR –

–

0

–

ns

20 +ꢂW_F

2TCL - 20 ns

+ꢂW_F

Address hold after

RdCS, WrCS

W₅₄CC 20 +ꢂW_F

W₅₆CC 20 +ꢂW_F

–

2TCL - 20 –

+ꢂW_F

ns

Data hold after WrCS

2TCL - 20 –

+ꢂW_F

1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

56

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristics

Multiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2W_A+ W_C+ W_F(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max.

min.

max.

ALE high time

W₅CC 11 + W_A

W₆CC 5 +ꢂW_A

W₇CC 15 +ꢂW_A

W₈CC 15 +ꢂW_A

W₉CC -10 +ꢂW_A

W₁₀CC –

–

TCL - 14

+ꢂW_A

–

6

ns

Address setup to ALE

Address hold after ALE

–

TCL - 20

+ꢂW_A

–

TCL - 10

+ꢂW_A

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ꢂW_A

ALE falling edge to RD,

WR (no RW-delay)

–

-10 +ꢂW_A

Address float after RD,

WR (with RW-delay)

6

–

Address float after RD,

WR (no RW-delay)

W₁₁CC –

31

TCL + 6

RD, WR low time

(with RW-delay)

W₁₂CC 34 +ꢂW_C

W₁₃CC 59 +ꢂW_C

W₁₄SR –

–

2TCL - 16 –

+ꢂW_C

RD, WR low time

(no RW-delay)

–

3TCL - 16 –

+ W_C

RD to valid data in

(with RW-delay)

22 +ꢂW_C

47 +ꢂW_C

–

0

–

2TCL - 28 ns

+ꢂW_C

RD to valid data in

(no RW-delay)

W₁₅SR –

3TCL - 28 ns

+ꢂW_C

ALE low to valid data in

W₁₆SR –

49 + W_A

+ W_C

3TCL - 30 ns

+ꢂW_A+ꢂW_C

Address to valid data in

W₁₇SR –

57 + 2W_A

+ W_C

4TCL - 43 ns

+ꢂ2W_A+ꢂW_C

Data hold after RD

rising edge

W₁₈SR 0

–

ns

Data float after RD

W₁₉SR –

36 +ꢂW_F

2TCL - 14 ns

+ꢂW_F

Data Sheet

57

1999-07

&ꢀꢁꢀ3,

ꢂ

Multiplexed Bus (Reduced Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2W_A+ W_C+ W_F(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max.

min.

max.

Data valid to WR

W₂₂CC 24 +ꢂW_C

–

2TCL - 26 –

+ꢂW_C

ns

Data hold after WR

W₂₃CC 36 +ꢂW_F

–

2TCL - 14 –

+ꢂW_F

ALE rising edge after RD, W₂₅CC 36 +ꢂW_F

WR

–

2TCL - 14 –

+ꢂW_F

Address hold after RD,

WR

ALE falling edge to CS ¹⁾W₃₈CC -8 -ꢂW_A

CS low to Valid Data In ¹⁾W₃₉SR –

W₂₇CC 36 +ꢂW_F

–

2TCL - 14 –

+ꢂW_F

10 - W_A

-8 -ꢂW_A

10 -ꢂW_A

47

–

3TCL - 28 ns

+ꢂW_C+ꢂ2W_A

+ꢂW_C+ 2W_A

CS hold after RD, WR ¹⁾W₄₀CC 57 +ꢂW_F

–

3TCL - 18 –

ns

+ W_F

ALE fall. edge to RdCS, W₄₂CC 19 +ꢂW_A

WrCS (with RW delay)

–

TCL - 6

+ꢂW_A

–

ALE fall. edge to RdCS, W₄₃CC -6 +ꢂW_A

WrCS (no RW delay)

–

-6

+ꢂW_A

–

Address float after RdCS, W₄₄CC –

WrCS (with RW delay)

0

–

0

Address float after RdCS, W₄₅CC –

WrCS (no RW delay)

25

TCL

RdCS to Valid Data In

(with RW delay)

W₄₆SR –

W₄₇SR –

20 +ꢂW_C

2TCL - 30 ns

+ꢂW_C

RdCS to Valid Data In

(no RW delay)

45 +ꢂW_C

3TCL - 30 ns

+ꢂW_C

RdCS, WrCS Low Time W₄₈CC 38 +ꢂW_C

(with RW delay)

–

2TCL - 12 –

+ꢂW_C

ns

RdCS, WrCS Low Time W₄₉CC 63 +ꢂW_C

(no RW delay)

3TCL - 12 –

+ꢂW_C

Data valid to WrCS

W₅₀CC 28 +ꢂW_C

2TCL - 22 –

+ꢂW_C

Data Sheet

58

1999-07

&ꢀꢁꢀ3,

ꢂ

Multiplexed Bus (Reduced Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2W_A+ W_C+ W_F(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max. min. max.

Data hold after RdCS

W₅₁SR 0

W₅₂SR –

–

0

–

ns

Data float after RdCS

30 +ꢂW_F

2TCL - 20 ns

+ꢂW_F

Address hold after

RdCS, WrCS

W₅₄CC 30 +ꢂW_F

W₅₆CC 30 +ꢂW_F

–

2TCL - 20 –

+ꢂW_F

ns

Data hold after WrCS

2TCL - 20 –

+ꢂW_F

1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

59

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₁₆

W₂₅

ALE

W₃₈

W₃₉

W₄₀

CSxL

W₁₇

W₂₇

A22-A16

(A15-A8)

BHE, CSxE

Address

W₆

W₇

W₅₄

W₁₉

W₁₈

5HDGꢂ&\FOH

BUS

Address

Data In

W₁₀

W₈

W₁₄

W₁₂

W₄₆

W₄₈

RD

W₅₁

W₄₄

W₄₂

W₅

2

RdCSx

:ULWHꢂ&\FOH

W₂₃

BUS

Address

Data Out

W₅₆

W₁₀

W₈

W₂₂

WR,

WRL,

WRH

W₁₂

W₄₄

W₄₂

W₅₀

WrCSx

W₄₈

Figure 16

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

60

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₃₈

W₁₆

W₂₅

ALE

W₃₉

W₄₀

CSxL

W₁₇

W₂₇

A22-A16

(A15-A8)

Address

BHE, CSxE

W₆

W₇

W₅₄

W₁₉

W₁₈

5HDGꢂ&\FOH

BUS

Address

Data In

W₁₀

W₈

W₁₄

W₁₂

W₄₆

W₄₈

RD

W₅₁

W₄₄

W₄₂

W₅₂

RdCSx

:ULWHꢂ&\FOH

W₂₃

BUS

Address

Data Out

W₅₆

W₁₀

W₈

W₂₂

WR,

WRL,

WRH

W₁₂

W₄₄

W₄₂

W₅₀

WrCSx

W₄₈

Figure 17

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

61

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₁₆

W₂₅

ALE

W₃₈

W₃₉

W₄₀

CSxL

W₁₇

W₂₇

A22-A16

(A15-A8)

Address

BHE, CSxE

W₆

W₇

W₅₄

W₁₉

W₁₈

5HDGꢂ&\FOH

BUS

Address

Data In

W₉

W₁₁

W₁₅

W₁₃

W₄₇

W₄₉

RD

W₅₁

W₄₃

W₄₅

W₅₂

RdCSx

:ULWHꢂ&\FOH

W₂₃

BUS

Address

Data Out

W₅₆

W₉

W₁₁

W₂₂

WR,

WRL,

WRH

W₁₃

W₅₀

W₄₃

W₄₅

WrCSx

W₄₉

Figure 18

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

62

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₁₆

W₂₅

ALE

W₃₈

W₃₉

W₄₀

CSxL

W₁₇

W₂₇

A22-A16

(A15-A8)

Address

BHE, CSxE

W₆

W₇

W₅₄

W₁₉

W₁₈

5HDGꢂ&\FOH

BUS

Address

Data In

W₉

W₁₁

W₁₅

W₁₃

W₄₇

W₄₉

RD

W₅₁

W₄₃

W₄₅

W₅₂

RdCSx

:ULWHꢂ&\FOH

W₂₃

BUS

Address

Data Out

W₅₆

W₉

W₁₁

W₂₂

WR,

WRL,

WRH

W₁₃

W₄₃

W₄₅

W₅₀

WrCSx

W₄₉

Figure 19

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

63

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristics

Demultiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2W_A+ W_C+ W_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max.

min.

max.

ALE high time

W₅CC 10 +ꢂW_A

W₆CC 4 +ꢂW_A

W₈CC 10 +ꢂW_A

W₉CC -10 +ꢂW_A

W₁₂CC 30 +ꢂW_C

W₁₃CC 50 +ꢂW_C

W₁₄SR –

–

TCL - 10

+ꢂW_A

–

ns

Address setup to ALE

–

TCL - 16

+ꢂW_A

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ꢂW_A

ALE falling edge to RD,

WR (no RW-delay)

–

-10

+ꢂW_A

RD, WR low time

(with RW-delay)

–

2TCL - 10 –

+ꢂW_C

RD, WR low time

(no RW-delay)

–

3TCL - 10 –

+ꢂW_C

RD to valid data in

(with RW-delay)

20 +ꢂW_C

40 +ꢂW_C

–

0

–

2TCL - 20 ns

+ꢂW_C

RD to valid data in

(no RW-delay)

W₁₅SR –

3TCL - 20 ns

+ꢂW_C

ALE low to valid data in

W₁₆SR –

40 +

W_A+ꢂW_C

3TCL - 20 ns

+ꢂW_A+ꢂW_C

Address to valid data in

W₁₇SR –

50 +

2W_A+ꢂW_C

4TCL - 30 ns

+ꢂ2W_A+ꢂW_C

Data hold after RD

rising edge

W₁₈SR 0

–

ns

Data float after RD rising W₂₀SR –

26 +

2TCL - 14 ns

+ꢂ22W_A

+ꢂW_F

edge (with RW-delay ¹⁾)

2W_A+ꢂW_F

1)

Data float after RD rising W₂₁SR –

10 +

2W_A+ꢂW_F

–

TCL - 10

ns

edge (no RW-delay ¹⁾)

+ꢂ22W_A

1)

+ꢂW_F

Data valid to WR

W₂₂CC 20 +ꢂW_C

–

2TCL - 20 –

+ꢂW_C

Data Sheet

64

1999-07

&ꢀꢁꢀ3,

ꢂ

Demultiplexed Bus (Standard Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2W_A+ W_C+ W_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max.

W₂₄CC 10 +ꢂW_F

min.

max.

Data hold after WR

–

TCL - 10

–

ns

+ꢂW_F

ALE rising edge after RD, W₂₆CC -10 +ꢂW_F

WR

Address hold after WR ²⁾W₂₈CC 0 +ꢂW_F

ALE falling edge to CS ³⁾W₃₈CC -4 -ꢂW_A

CS low to Valid Data In ³⁾W₃₉SR –

-10 +ꢂW_F

–

0 +ꢂW_F

-4 -ꢂW_A

–

ns

10 -ꢂW_A

40 +

3TCL - 20 ns

W_Cꢂ+ꢂ2W_A

+ꢂW_C+ 2W_A

CS hold after RD, WR ³⁾W₄₁CC 6 +ꢂW_F

–

TCL - 14

–

ns

+ꢂW_F

ALE falling edge to

RdCS, WrCS (with RW-

delay)

W₄₂CC 16 +ꢂW_A

W₄₃CC -4 +ꢂW_A

–

TCL - 4

+ꢂW_A

–

ALE falling edge to

RdCS, WrCS (no RW-

delay)

–

-4

+ꢂW_A

–

ns

RdCS to Valid Data In

(with RW-delay)

W₄₆SR –

W₄₇SR –

16 +ꢂW_C

–

2TCL - 24 ns

+ꢂW_C

RdCS to Valid Data In

(no RW-delay)

36 +ꢂW_C

3TCL - 24 ns

+ꢂW_C

RdCS, WrCS Low Time W₄₈CC 30 +ꢂW_C

(with RW-delay)

–

2TCL - 10 –

+ꢂW_C

ns

RdCS, WrCS Low Time W₄₉CC 50 +ꢂW_C

(no RW-delay)

3TCL - 10 –

+ꢂW_C

Data valid to WrCS

W₅₀CC 26 +ꢂW_C

2TCL - 14 –

+ꢂW_C

Data hold after RdCS

W₅₁SR 0

W₅₃SR –

–

0

–

Data float after RdCS

(with RW-delay) ¹⁾

20 +ꢂW_F

2TCL - 20 ns

1)

+ꢂ2W_A+ꢂW_F

Data float after RdCS

(no RW-delay) ¹⁾

W₆₈SR –

0 +ꢂW_F

–

TCL - 20

+ꢂ2W_A+ꢂW_F

ns

1)

Data Sheet

65

1999-07

&ꢀꢁꢀ3,

ꢂ

Demultiplexed Bus (Standard Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2W_A+ W_C+ W_F(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max. min. max.

-6 +ꢂW_F

Address hold after

RdCS, WrCS

W₅₅CC -6 +ꢂW_F

W₅₇CC 6 +ꢂW_F

–

ns

Data hold after WrCS

TCL - 14 +ꢂ –

W_F

1) RW-delay and W_Arefer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

66

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristics

Demultiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2W_A+ W_C+ W_F(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max.

min.

max.

ALE high time

W₅CC 11 +ꢂW_A

W₆CC 5 +ꢂW_A

W₈CC 15 +ꢂW_A

W₉CC -10 +ꢂW_A

W₁₂CC 34 +ꢂW_C

W₁₃CC 59 +ꢂW_C

W₁₄SR –

–

TCL - 14

+ꢂW_A

–

ns

Address setup to ALE

–

TCL - 20

+ꢂW_A

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ꢂW_A

ALE falling edge to RD,

WR (no RW-delay)

–

-10

+ꢂW_A

RD, WR low time

(with RW-delay)

–

2TCL - 16 –

+ꢂW_C

RD, WR low time

(no RW-delay)

–

3TCL - 16 –

+ꢂW_C

RD to valid data in

(with RW-delay)

22 +ꢂW_C

47 +ꢂW_C

–

0

–

2TCL - 28 ns

+ꢂW_C

RD to valid data in

(no RW-delay)

W₁₅SR –

3TCL - 28 ns

+ꢂW_C

ALE low to valid data in

W₁₆SR –

49 +

W_A+ꢂW_C

3TCL - 30 ns

+ꢂW_A+ꢂW_C

Address to valid data in

W₁₇SR –

57 +

2W_A+ꢂW_C

4TCL - 43 ns

+ꢂ2W_A+ꢂW_C

Data hold after RD

rising edge

W₁₈SR 0

–

ns

Data float after RD rising W₂₀SR –

36 +

2TCL - 14 ns

edge (with RW-delay ¹⁾)

2W_A+ꢂW_F

+ꢂ2W_A+ꢂW_F

1)

Data float after RD rising W₂₁SR –

15 +

2W_A+ꢂW_F

–

TCL - 10

ns

edge (no RW-delay ¹⁾)

+ꢂ2W_A

1)

+ꢂW_F

Data valid to WR

W₂₂CC 24 +ꢂW_C

–

2TCL - 26 –

+ꢂW_C

Data Sheet

67

1999-07

&ꢀꢁꢀ3,

ꢂ

Demultiplexed Bus (Reduced Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2W_A+ W_C+ W_F(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max.

W₂₄CC 15 +ꢂW_F

min.

max.

Data hold after WR

–

TCL - 10

–

ns

+ꢂW_F

ALE rising edge after RD, W₂₆CC -12 +ꢂW_F

WR

Address hold after WR ²⁾W₂₈CC 0 +ꢂW_F

ALE falling edge to CS ³⁾W₃₈CC -8 -ꢂW_A

CS low to Valid Data In ³⁾W₃₉SR –

-12 +ꢂW_F

–

0 +ꢂW_F

-8 -ꢂW_A

–

ns

10 -ꢂW_A

47 +

3TCL - 28 ns

W_Cꢂ+ꢂ2W_A

+ꢂW_C+ 2W_A

CS hold after RD, WR ³⁾W₄₁CC 9 +ꢂW_F

–

TCL - 16

–

ns

+ꢂW_F

ALE falling edge to

RdCS, WrCS (with RW-

delay)

W₄₂CC 19 +ꢂW_A

W₄₃CC -6 +ꢂW_A

–

TCL - 6

+ꢂW_A

–

ALE falling edge to

RdCS, WrCS (no RW-

delay)

–

-6

+ꢂW_A

–

ns

RdCS to Valid Data In

(with RW-delay)

W₄₆SR –

W₄₇SR –

20 +ꢂW_C

–

2TCL - 30 ns

+ꢂW_C

RdCS to Valid Data In

(no RW-delay)

45 +ꢂW_C

3TCL - 30 ns

+ꢂW_C

RdCS, WrCS Low Time W₄₈CC 38 +ꢂW_C

(with RW-delay)

–

2TCL - 12 –

+ꢂW_C

ns

RdCS, WrCS Low Time W₄₉CC 63 +ꢂW_C

(no RW-delay)

3TCL - 12 –

+ꢂW_C

Data valid to WrCS

W₅₀CC 28 +ꢂW_C

2TCL - 22 –

+ꢂW_C

Data hold after RdCS

W₅₁SR 0

W₅₃SR –

–

0

–

Data float after RdCS

(with RW-delay) ¹⁾

30 +ꢂW_F

2TCL - 20 ns

1)

+ꢂ2W_A+ꢂW_F

Data float after RdCS

(no RW-delay) ¹⁾

W₆₈SR –

5 +ꢂW_F

–

TCL - 20

+ꢂ2W_A+ꢂW_F

ns

1)

Data Sheet

68

1999-07

&ꢀꢁꢀ3,

ꢂ

Demultiplexed Bus (Reduced Supply Voltage Range) (continued)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2W_A+ W_C+ W_F(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max.

min.

max.

Address hold after

RdCS, WrCS

W₅₅CC -16 +ꢂW_F

–

-16 +ꢂW_F

–

ns

Data hold after WrCS

W₅₇CC 9 +ꢂW_F

–

TCL - 16

–

ns

+ꢂW_F

1) RW-delay and W_Arefer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

69

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₁₆

W₂₆

ALE

W₃₈

W₃₉

W₄₁

CSxL

W₁₇

W₂₈

A22-A16

A15-A0

Address

BHE, CSxE

W₆

W₅₅

W₂₀

W₁₈

5HDGꢂ&\FOH

BUS

Data In

(D15-D8)

D7-D0

W₈

W₁₄

RD

W₁₂

W₄₆

W₄₈

W₅₁

W₄₂

W₅₃

RdCSx

:ULWHꢂ&\FOH

BUS

(D15-D8)

D7-D0

W₂₄

Data Out

W₅₇

W₈

W₂₂

WR,

WRL,

WRH

W₁₂

W₄₂

W₅₀

WrCSx

W₄₈

Figure 20

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

70

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₁₆

W₃₉

W₁₇

W₂₆

ALE

W₃₈

W₄₁

CSxL

W₂₈

A22-A16

A15-A0

BHE,

Address

W₆

W₅₅

CSxE

W₂₀

W₁₈

5HDGꢂ&\FOH

BUS

Data In

(D15-D8)

D7-D0

W₈

W₁₄

W₁₂

W₄₆

W₄₈

RD

W₅₁

W₄₂

W₅₃

RdCSx

:ULWHꢂ&\FOH

BUS

(D15-D8)

D7-D0

W₂₄

Data Out

W₅₇

W₈

W₂₂

WR,

WRL,

WRH

W₁₂

W₄₂

W₅₀

WrCSx

W₄₈

Figure 21

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

71

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₁₆

W₂₆

ALE

W₃₈

W₃₉

W₄₁

CSxL

W₁₇

W₂₈

A22-A16

A15-A0

Address

BHE, CSxE

W₆

W₅₅

W₂₁

W₁₈

5HDGꢂ&\FOH

BUS

Data In

(D15-D8)

D7-D0

W₉

W₁₅

W₁₃

W₄₇

W₄₉

RD

W₅₁

W₄₃

W₆₈

RdCSx

:ULWHꢂ&\FOH

BUS

(D15-D8)

D7-D0

W₂₄

Data Out

W₅₇

W₉

W₂₂

WR,

WRL,WRH

W₁₃

W₅₀

W₄₃

WrCSx

W₄₉

Figure 22

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

72

1999-07

&ꢀꢁꢀ3,

ꢂ

W₅

W₁₆

W₃₉

W₁₇

W₂₆

ALE

W₃₈

W₄₁

CSxL

W₂₈

A22-A16

A15-A0

Address

BHE,CSxE

W₆

W₅₅

W₂₁

W₁₈

5HDGꢂ&\FOH

BUS

Data In

(D15-D8)

D7-D0

W₉

W₁₅

W₁₃

W₄₇

W₄₉

RD

W₅₁

W₄₃

W₆₈

RdCSx

:ULWHꢂ&\FOH

BUS

(D15-D8)

D7-D0

W₂₄

Data Out

W₅₇

W₉

W₂₂

WR,

WRL, WRH

W₁₃

W₄₃

W₅₀

WrCSx

W₄₉

Figure 23

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

73

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristicsꢂ

CLKOUT and READY (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 25 MHz 1 / 2TCL = 1 to 25 MHz

min. max. min. max.

2TCL 2TCL

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

W₂₉CC 40

W₃₀CC 14

W₃₁CC 10

W₃₂CC –

40

–

ns

TCL – 6

–

TCL – 10

–

4

–

4

W₃₃CC –

4

CLKOUT rising edge to

ALE falling edge

W₃₄CC 0 +ꢂW_A

10 +ꢂW_A0 +ꢂW_A

10 +ꢂW_A

Synchronous READY

setup time to CLKOUT

W₃₅SR 14

W₃₆SR 4

W₃₇SR 54

W₅₈SR 14

W₅₉SR 4

–

14

–

ns

Synchronous READY

hold time after CLKOUT

4

Asynchronous READY

low time

2TCL + W₅₈

Asynchronous READY

setup time ¹⁾

14

4

Asynchronous READY

hold time ¹⁾

Async. READY hold time W₆₀SR 0

after RD, WR high

0

TCL - 20

+ 2W_A+ W_C

+ W_F

+ 2W_A+

W_C+ W_F

(Demultiplexed Bus) ²⁾

2)

1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This

adds even more time for deactivating READY.

The 2W_Aand W_Crefer to the next following bus cycle,ꢂW_Frefers to the current bus cycle.

The maximum limit for W₆₀must be fulfilled if the next following bus cycle is READY controlled.

Data Sheet

74

1999-07

&ꢀꢁꢀ3,

ꢂ

AC Characteristicsꢂ

CLKOUT and READY (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 20 MHz 1 / 2TCL = 1 to 20 MHz

min. max. min. max.

2TCL 2TCL

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

W₂₉CC 40

W₃₀CC 15

W₃₁CC 13

W₃₂CC –

40

–

ns

TCL – 10

–

TCL – 12

–

12

8

–

12

W₃₃CC –

–

8

CLKOUT rising edge to

ALE falling edge

W₃₄CC 0 +ꢂW_A

8 +ꢂW_A

0 +ꢂW_A

8 +ꢂW_A

Synchronous READY

setup time to CLKOUT

W₃₅SR 18

W₃₆SR 4

W₃₇SR 68

W₅₈SR 18

W₅₉SR 4

–

18

–

ns

Synchronous READY

hold time after CLKOUT

4

Asynchronous READY

low time

2TCL + W₅₈

Asynchronous READY

setup time ¹⁾

18

4

Asynchronous READY

hold time ¹⁾

Async. READY hold time W₆₀SR 0

after RD, WR high

0

TCL - 25

+ 2W_A+ W_C

+ W_F

+ 2W_A+

W_C+ W_F

(Demultiplexed Bus) ²⁾

2)

1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This

adds even more time for deactivating READY.

The 2W_Aand W_Crefer to the next following bus cycle,ꢂW_Frefers to the current bus cycle.

The maximum limit for W₆₀must be fulfilled if the next following bus cycle is READY controlled.

Data Sheet

75

1999-07

&ꢀꢁꢀ3,

ꢂ

READY

waitstate

MUX/Tristate ⁶⁾

Running cycle ¹⁾

W₃₂

W₃₃

W₃₁

CLKOUT

ALE

W₃₀

W₃₄

W₂₉

7)

2)

Command

RD, WR

W₃₅

W₃₆

W₃₅

W₃₆

Sync

3)

READY

4)

W₆₀

W₅₈

W₅₉

W₅₈

W₅₉

3)

Async

3)

READY

W₃₇

5)

see 6)

Figure 24

CLKOUT and READY

Notes

1)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

2)

READY sampled HIGH at this sampling point generates a READY controlled waitstate,

READY sampled LOW at this sampling point terminates the currently running bus cycle.

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or

WR).

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT

(e.g. because CLKOUT is not enabled), it must fulfill W₃₇in order to be safely synchronized. This is guaranteed,

if READY is removed in reponse to the command (see Note ⁴⁾).

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted here.

3)

4)

5)

6)

For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without

MTTC waitstate this delay is zero.

The next external bus cycle may start here.

7)

Data Sheet

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&ꢀꢁꢀ3,

ꢂ

Package Outlines

Plastic Package, P-MQFP-100-2 (SMD)

(Plastic Metric Quad Flat Package)

Figure 25

Data Sheet

77

1999-07

C161PI

Package Outlines (continued)

Plastic Package, P-TQFP-100-1 (SMD)

(Plastic Thin Metric Quad Flat Package)

Figure 26

Sorts of Packing

Package outlines for tubes, trays, etc. are contained in our

Data Book “Package Information”

SMD = Surface Mounted Device

Dimensions in mm

1999-07

Data Sheet

78

&ꢀꢁꢀ3,

ꢂ

Data Sheet

79

1999-07

&ꢀꢁꢀ3,

ꢂ

Published by Infineon Technologies AG

Data Sheet

80

1999-07


型号：	SAF-C161PI-LF
厂家：	Infineon
描述：	Microcontroller, 16-Bit, 80166 CPU, 25MHz, CMOS, PQFP100, METRIC, PLASTIC, TQFP-100 时钟局域网微控制器外围集成电路
文件：	总82页 (文件大小：834K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAF-C161PI-LF [INFINEON]

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