SAF-XC164CS-16R40F_技术文档

Data Sheet, V2.1, Jun. 2003

XC164CS

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2003-06

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address

list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Data Sheet, V2.1, Jun. 2003

XC164CS

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

XC164

Revision History:

2003-06

V2.1

Previous Version:

2003-01

2002-03

V2.0

V1.0

Page

1

Subjects (major changes since last revision)

AD conversion times updated

RSTIN note added

6, 45

45

Digital supply voltage range for IO pads improved

Note 2 added

48

49ff

53

Specification of Sleep and Power-down mode supply current improved

Conversion time formulas improved

Note 4 changed

54

55

Converter timing example improved

Note 1 added

58

63

Table 19 changed

Controller Area Network (CAN): License of Robert Bosch GmbH

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16-Bit Single-Chip Microcontroller

XC166 Family

XC164

1

Summary of Features

• High Performance 16-bit CPU with 5-Stage Pipeline

– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)

– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles

– 1-Cycle Multiply-and-Accumulate (MAC) Instructions

– Enhanced Boolean Bit Manipulation Facilities

– Zero-Cycle Jump Execution

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Fast Context Switching Support with Two Additional Local Register Banks

– 16 Mbytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)

• 16-Priority-Level Interrupt System with up to 75 Sources, Sample-Rate down to 50 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space

• Clock Generation via on-chip PLL (factors 1:0.15 …1:10), or

via Prescaler (factors 1:1 …60:1)

• On-Chip Memory Modules

– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)

– 2 Kbytes On-Chip Data SRAM (DSRAM)

– 2 Kbytes On-Chip Program/Data SRAM (PSRAM)

– 128 Kbytes On-Chip Program Memory (Flash Memory or Mask ROM)

• On-Chip Peripheral Modules

– 14-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and

Conversion Time (down to 2.55 µs or 2.15 µs)

– Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins)

– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)

– Multi-Functional General Purpose Timer Unit with 5 Timers

– Two Synchronous/Asynchronous Serial Channels (USARTs)

– Two High-Speed-Synchronous Serial Channels

– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects

(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality

– On-Chip Real Time Clock

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

Data Sheet

1

V2.1, 2003-06

XC164

Derivatives

Summary of Features

• Up to 12 Mbytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses

– Selectable Address Bus Width

– 16-Bit or 8-Bit Data Bus Width

– Four Programmable Chip-Select Signals

• Up to 79 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

• On-Chip Bootstrap Loader

• Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,

Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Debug Support via JTAG Interface

• 100-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the XC164 please refer to the “Product Catalog

Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

This document describes several derivatives of the XC164 group. Table 1 enumerates

these derivatives and summarizes the differences. As this document refers to all of these

derivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term XC164 throughout this document.

Data Sheet

2

V2.1, 2003-06

XC164

Derivatives

Summary of Features

Table 1

XC164 Derivative Synopsis

1)

Derivative

Program Memory On-Chip RAM Interfaces

SAK-XC164CS-16F40F, 128 Kbytes Flash

SAK-XC164CS-16F20F

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

SAK-XC164CS-16R40F, 128 Kbytes ROM

SAK-XC164CS-16R20F

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

SAF-XC164CS-16F40F, 128 Kbytes Flash

SAF-XC164CS-16F20F

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

SAF-XC164CS-16R40F, 128 Kbytes ROM

SAF-XC164CS-16R20F

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

SAK-XC164CS-8F40F,

SAK-XC164CS-8F20F

64 Kbytes Flash

64 Kbytes ROM

64 Kbytes Flash

64 Kbytes ROM

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

SAK-XC164CS-8R40F,

SAK-XC164CS-8R20F

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

SAF-XC164CS-8F40F,

SAF-XC164CS-8F20F

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

SAF-XC164CS-8R40F,

SAF-XC164CS-8R20F

2 Kbytes DPRAM, ASC0, ASC1,

2 Kbytes DSRAM, SSC0, SSC1,

2 Kbytes PSRAM CAN0, CAN1

1)

This Data Sheet is valid for devices starting with and including design step AD of the Flash version, and design

step AA of the ROM version.

Data Sheet

3

V2.1, 2003-06

XC164

Derivatives

General Device Information

2

General Device Information

2.1

Introduction

The XC164 derivatives are high-performance members of the Infineon XC166 Family of

full featured single-chip CMOS microcontrollers. These devices extend the functionality

and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and

speed. They combine high CPU performance (up to 40 million instructions per second)

with high peripheral functionality and enhanced IO-capabilities. They also provide clock

generation via PLL and various on-chip memory modules such as program ROM or

Flash, program RAM, and data RAM.

V_AREF

V_AGND

V_DDI/P

V_SSI/P

XTAL1

XTAL2

PORT0

16 bit

PORT1

16 bit

NMI

RSTIN

Port 3

14 bit

XC164

RSTOUT

EA

Port 4

8 bit

Port 20

5 bit

ALE

RD

WR/WRL

Port 9

6 bit

Port 5

14 bit

TRST JTAG Debug

Via Port 3

Figure 1

Logic Symbol

Data Sheet

4

V2.1, 2003-06

XC164

Derivatives

General Device Information

2.2

Pin Configuration and Definition

The pins of the XC164 are described in detail in Table 2, including all their alternate

functions. Figure 2 summarizes all pins in a condensed way, showing their location on

the 4 sides of the package. E*) and C*) mark pins to be used as alternate external

interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them.

C

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RSTIN

P20.12/RSTOUT

NMI

P0H.4/AD12

P0L.7/AD7

P0L.6/AD6

P0L.5/AD5

P0L.4/AD4

P0L.3/AD3

P0L.2/AD2

P0L.1/AD1

P0L.0/AD0

P20.5/EA

P20.4/ALE

P20.1/WR/WRL

P20.0/RD

V_SSP

1

2

3

4

5

6

7

8

P0H.0/AD8

P0H.1/AD9

P0H.2/AD10

P0H.3/AD11

V_SSP

V_DDP

9

P9.0/CC16IO/C*)

P9.1/CC17IO/C*)

P9.2/CC18IO/C*)

P9.3/CC19IO/C*)

P9.4/CC20IO

P9.5/CC21IO

V_SSP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

XC164

V_DDP

P4.7/A23/C*)

P4.6/A22/C*)

P4.5/A21/C*)

P4.4/A20/C*)

P4.3/A19/CS0

P4.2/A18/CS1

P4.1/A17/CS2

P4.0/A16/CS3

P3.15/CLKOUT/FO

P3.13/SCLK0/E*)

V_DDP

P5.0/AN0

P5.1/AN1

P5.2/AN2

P5.3/AN3

P5.4/AN4

P5.5/AN5

P5.10/AN10/T6EUD

P5.11/AN11/T5EUD

Figure 2

Pin Configuration (top view)

Data Sheet

5

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions

Input Function

Symbol Pin

Num. Outp.

RSTIN 1

I

Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the XC164.

A spike filter suppresses input pulses <10 ns. Input pulses

>100 ns safely pass the filter. The minimum duration for a

safe recognition should be 100 ns + 2 CPU clock cycles.

Note: The reset duration must be sufficient to let the

hardware configuration signals settle.

External circuitry must guarantee low level at the

RSTIN pin at least until both power supply voltages

have reached the operating range.

P20.12 2

NMI

IO

I

For details, please refer to the description of P20.

3

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the XC164 into power down

mode. If NMI is high, when PWRDN is executed, the part will

continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

P0H.0- 4…7

IO

For details, please refer to the description of PORT0.

P0H.3

Data Sheet

6

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

P9

IO

Port 9 is a 6-bit bidirectional I/O port. Each pin can be

programmed for input (output driver in high-impedance

state) or output (configurable as push/pull or open drain

driver). The input threshold of Port 9 is selectable (standard

or special).

The following Port 9 pins also serve for alternate functions:

CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.,

CAN2_RxD CAN Node 2 Receive Data Input,

1)

P9.0

P9.1

P9.2

P9.3

10

11

12

13

I/O

I

I/O

O

I

I/O

I

EX7IN

CC17IO

Fast External Interrupt 7 Input (alternate pin B)

CAPCOM2: CC17 Capture Inp./Compare Outp.,

CAN2_TxD CAN Node 2 Transmit Data Output,

EX6IN

CC18IO

Fast External Interrupt 6 Input (alternate pin B)

CAPCOM2: CC18 Capture Inp./Compare Outp.,

CAN1_RxD CAN Node 1 Receive Data Input,

I

EX7IN

CC19IO

Fast External Interrupt 7 Input (alternate pin A)

CAPCOM2: CC19 Capture Inp./Compare Outp.,

I/O

O

I

I/O

CAN1_TxD CAN Node 1 Transmit Data Output,

EX6IN

CC20IO

CC21IO

Fast External Interrupt 6 Input (alternate pin A)

CAPCOM2: CC20 Capture Inp./Compare Outp.

CAPCOM2: CC21 Capture Inp./Compare Outp.

P9.4

P9.5

14

15

P5

I

Port 5 is a 14-bit input-only port.

The pins of Port 5 also serve as analog input channels for the

A/D converter, or they serve as timer inputs:

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.10

P5.11

P5.6

18

19

20

21

22

23

24

25

26

27

30

31

32

33

I

AN0

AN1

AN2

AN3

AN4

AN5

AN10,

AN11,

AN6

T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.

T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.

P5.7

AN7

P5.12

P5.13

P5.14

P5.15

AN12,

AN13,

AN14,

AN15,

T6IN

T5IN

GPT2 Timer T6 Count/Gate Input

GPT2 Timer T5 Count/Gate Input

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.

T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

Data Sheet

7

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

TRST

36

I

Test-System Reset Input. A high level at this pin activates

the XC164’s debug system. For normal system operation,

pin TRST should be held low.

P3

IO

Port 3 is a 14-bit bidirectional I/O port. Each pin can be

programmed for input (output driver in high-impedance

state) or output (configurable as push/pull or open drain

driver). The input threshold of Port 3 is selectable (standard

or special).

The following Port 3 pins also serve for alternate functions:

P3.1

39

O

I/O

I

T6OUT

RxD1

EX1IN

TCK

GPT2 Timer T6 Toggle Latch Output,

ASC1 Data Input (Async.) or Inp./Outp. (Sync.),

Fast External Interrupt 1 Input (alternate pin A),

Debug System: JTAG Clock Input

I

P3.2

P3.3

P3.4

P3.5

40

41

42

43

I

O

I

O

I

CAPIN

TDI

T3OUT

TDO

T3EUD

TMS

T4IN

GPT2 Register CAPREL Capture Input,

Debug System: JTAG Data In

GPT1 Timer T3 Toggle Latch Output,

Debug System: JTAG Data Out

GPT1 Timer T3 External Up/Down Control Input,

Debug System: JTAG Test Mode Selection

GPT1 Timer T4 Count/Gate/Reload/Capture Inp

ASC0 Clock/Data Output (Async./Sync.),

TxD1

BRKOUT Debug System: Break Out

T3IN

T2IN

P3.6

P3.7

44

45

GPT1 Timer T3 Count/Gate Input

GPT1 Timer T2 Count/Gate/Reload/Capture Inp

Debug System: Break In

I

BRKIN

MRST0

MTSR0

TxD0

EX2IN

RxD0

EX2IN

BHE

P3.8

P3.9

P3.10

46

47

48

I/O

O

I

I/O

I

O

I

I/O

I

SSC0 Master-Receive/Slave-Transmit In/Out.

SSC0 Master-Transmit/Slave-Receive Out/In.

ASC0 Clock/Data Output (Async./Sync.),

Fast External Interrupt 2 Input (alternate pin B)

ASC0 Data Input (Async.) or Inp./Outp. (Sync.),

Fast External Interrupt 2 Input (alternate pin A)

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe,

Fast External Interrupt 3 Input (alternate pin B)

SSC0 Master Clock Output / Slave Clock Input.,

Fast External Interrupt 3 Input (alternate pin A)

P3.11

P3.12

49

50

WRH

EX3IN

SCLK0

EX3IN

P3.13

P3.15

51

52

O

CLKOUT System Clock Output (=CPU Clock),

FOUT

Programmable Frequency Output

Data Sheet

8

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

P4

IO

Port 4 is an 8-bit bidirectional I/O port. Each pin can be

programmed for input (output driver in high-impedance

state) or output (configurable as push/pull or open drain

driver). The input threshold of Port 4 is selectable (standard

or special).

Port 4 can be used to output the segment address lines, the

1)

optional chip select lines, and for serial interface lines:

P4.0

P4.1

P4.2

P4.3

P4.4

53

54

55

56

57

O

I

A16

CS3

A17

CS2

A18

CS1

A19

CS0

A20

Least Significant Segment Address Line,

Chip Select 3 Output

Segment Address Line,

Chip Select 2 Output

Segment Address Line,

Chip Select 1 Output

Segment Address Line,

Chip Select 0 Output

Segment Address Line,

CAN2_RxD CAN Node 2 Receive Data Input,

I

O

I

EX5IN

A21

Fast External Interrupt 5 Input (alternate pin B)

Segment Address Line,

P4.5

P4.6

P4.7

58

59

60

CAN1_RxD CAN Node 1 Receive Data Input,

I

EX4IN

A22

Fast External Interrupt 4 Input (alternate pin B)

Segment Address Line,

O

I

O

I

CAN1_TxD CAN Node 1 Transmit Data Output,

EX5IN

A23

CAN1_RxD CAN Node 1 Receive Data Input,

CAN2_TxD CAN Node 2 Transmit Data Output,

EX4IN

Fast External Interrupt 5 Input (alternate pin A)

Most Significant Segment Address Line,

O

I

Fast External Interrupt 4 Input (alternate pin A)

Data Sheet

9

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

P20

IO

Port 20 is a 6-bit bidirectional I/O port. Each pin can be

programmed for input (output driver in high-impedance

state) or output. The input threshold of Port 20 is selectable

(standard or special).

The following Port 20 pins also serve for alternate functions:

P20.0

P20.1

63

64

O

RD

External Memory Read Strobe, activated for

every external instruction or data read access.

WR/WRL External Memory Write Strobe.

In WR-mode this pin is activated for every

external data write access.

In WRL-mode this pin is activated for low byte

data write accesses on a 16-bit bus, and for

every data write access on an 8-bit bus.

Address Latch Enable Output.

Can be used for latching the address into

external memory or an address latch in the

multiplexed bus modes.

P20.4

P20.5

65

66

O

I

ALE

EA

External Access Enable pin.

A low level at this pin during and after Reset

forces the XC164 to latch the configuration from

PORT0 and pin RD, and to begin instruction

execution out of external memory.

A high level forces the XC164 to latch the

configuration from pins RD, ALE, and WR, and

to begin instruction execution out of the internal

program memory. "ROMless" versions must

have this pin tied to ‘0’.

P20.12 2

O

RSTOUT Internal Reset Indication Output.

Is activated asynchronously with an external

hardware reset. It may also be activated

(selectable) synchronously with an internal

software or watchdog reset.

Is deactivated upon the execution of the EINIT

instruction, optionally at the end of reset, or at

any time (before EINIT) via user software.

Note: Port 20 pins may input configuration values (see EA).

Data Sheet

10

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

PORT0

IO

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. Each pin can be programmed for input (output

driver in high-impedance state) or output.

P0L.0-7 67 - 74

In case of an external bus configuration, PORT0 serves as

the address (A) and address/data (AD) bus in multiplexed

bus modes and as the data (D) bus in demultiplexed bus

modes.

P0H.0-3 4 - 7

P0H.4-7 75 - 78

Demultiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

D0 – D7

I/O

16-bit

D0 - D7

D8 - D15

Multiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

16-bit

AD0 – AD7 AD0 - AD7

A8 - A15 AD8 - AD15

Note: At the end of an external reset (EA = 0) PORT0 also

may input configuration values

PORT1

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. Each pin can be programmed for input (output

driver in high-impedance state) or output.

PORT1 is used as the 16-bit address bus (A) in

demultiplexed bus modes (also after switching from a

demultiplexed to a multiplexed bus mode).

The following PORT1 pins also serve for alt. functions:

P1L.0

P1L.1

P1L.2

P1L.3

P1L.4

P1L.5

P1L.6

P1L.7

79

80

81

82

83

84

85

86

I/O

O

I/O

O

I/O

O

CC60

COUT60 CAPCOM6: Output of Channel 0

CC61 CAPCOM6: Input / Output of Channel 1

COUT61 CAPCOM6: Output of Channel 1

CC62 CAPCOM6: Input / Output of Channel 2

CAPCOM6: Input / Output of Channel 0

COUT62 CAPCOM6: Output of Channel 2

COUT63 Output of 10-bit Compare Channel

I

CTRAP

CAPCOM6: Trap Input

CTRAP is an input pin with an internal pullup resistor. A low

level on this pin switches the CAPCOM6 compare outputs to

the logic level defined by software (if enabled).

I/O

CC22IO

CAPCOM2: CC22 Capture Inp./Compare Outp.

P1H

…

…continued…

Data Sheet

11

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

PORT1

(cont’d)

P1H.0 89

IO

…continued…

CC6POS0 CAPCOM6: Position 0 Input,

I

EX0IN

CC23IO

Fast External Interrupt 0 Input (default pin),

CAPCOM2: CC23 Capture Inp./Compare Outp.

I/O

P1H.1 90

P1H.2 91

P1H.3 92

I

CC6POS1 CAPCOM6: Position 1 Input,

EX1IN

MRST1

Fast External Interrupt 1 Input (default pin),

SSC1 Master-Receive/Slave-Transmit In/Out.

I/O

I

I/O

I

CC6POS2 CAPCOM6: Position 2 Input,

EX2IN

MTSR1

T7IN

Fast External Interrupt 2 Input (default pin),

SSC1 Master-Transmit/Slave-Receive Out/Inp.

CAPCOM2: Timer T7 Count Input,

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

SCLK1

EX3IN

EX0IN

CC24IO

EX4IN

CC25IO

EX5IN

CC26IO

EX6IN

CC27IO

EX7IN

SSC1 Master Clock Output / Slave Clock Input,

Fast External Interrupt 3 Input (default pin),

Fast External Interrupt 0 Input (alternate pin A)

CAPCOM2: CC24 Capture Inp./Compare Outp.,

Fast External Interrupt 4 Input (default pin)

CAPCOM2: CC25 Capture Inp./Compare Outp.,

Fast External Interrupt 5 Input (default pin)

CAPCOM2: CC26 Capture Inp./Compare Outp.,

Fast External Interrupt 6 Input (default pin)

CAPCOM2: CC27 Capture Inp./Compare Outp.,

Fast External Interrupt 7 Input (default pin)

P1H.4 93

P1H.5 94

P1H.6 95

P1H.7 96

XTAL2 99

XTAL1 100

O

I

XTAL2:

XTAL1:

Output of the oscillator amplifier circuit

Input to the oscillator amplifier and input to

the internal clock generator

To clock the device from an external source, drive XTAL1,

while leaving XTAL2 unconnected. Minimum and maximum

high/low and rise/fall times specified in the AC

Characteristics must be observed.

V_AREF28

V_AGND29

-

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

V_DDI

35, 97 -

Digital Core Supply Voltage (On-Chip Modules):

+2.5 V during normal operation and idle mode.

Please refer to the Operating Conditions

Data Sheet

12

V2.1, 2003-06

XC164

Derivatives

General Device Information

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

V_DDP

9, 17,

38, 61,

87

-

Digital Pad Supply Voltage (Pin Output Drivers):

+5 V during normal operation and idle mode.

Please refer to the Operating Conditions

V_SSI

34, 98 -

Digital Ground.

Connect decoupling capacitors to adjacent V_DD/V_SSpin

pairs as close as possible to the pins.

All V_SSpins must be connected to the ground-line or ground-

plane.

V_SSP

8, 16,

37, 62,

88

-

1)

The CAN interface lines are assigned to ports P4 and P9 under software control.

Data Sheet

13

V2.1, 2003-06

XC164

Derivatives

Functional Description

3

Functional Description

The architecture of the XC164 combines advantages of RISC, CISC, and DSP

processors with an advanced peripheral subsystem in a very well-balanced way. In

addition, the on-chip memory blocks allow the design of compact systems-on-silicon with

maximum performance (computing, control, communication).

The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data

SRAM) and the set of generic peripherals are connected to the CPU via separate buses.

Another bus, the LXBus, connects additional on-chip resoures as well as external

resources (see Figure 3).

This bus structure enhances the overall system performance by enabling the concurrent

operation of several subsystems of the XC164.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the XC164.

PSRAM

DPRAM

DSRAM

EBC

ProgMem

XBUS Control

External Bus

Control

Flash / RO M

128 KBytes

CPU

C166SV2-Core

OCDS

Debug Support

Osc / PLL

RTC WDT

XTAL

Interrupt & PEC

Clock G eneration

Interrupt Bus

P eripheral D ata Bus

ADC GPT ASC0 ASC1 SSC0 SSC1 CC1 CC2

CC6

Twin

CAN

8/10-Bit

(USART) (USART)

(S PI)

(SPI)

T2

T3

T4

T0

T1

T7

T8

T12

T13

12/16

Channels

A

B

T5

T6

BRGen

BRG en

Port 5

BRGen

P 20 Port 9

Port 4

Port 3

14

PORT1

PORT0

16

8

16

5

6

14

M CB04323_x4.vsd

Figure 3

Block Diagram

Data Sheet

14

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.1

Memory Subsystem and Organization

The memory space of the XC164 is configured in a Von Neumann architecture, which

means that all internal and external resources, such as code memory, data memory,

registers and I/O ports, are organized within the same linear address space. This

common memory space includes 16 Mbytes and is arranged as 256 segments of

64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.

The entire memory space can be accessed bytewise or wordwise. Portions of the on-

chip DPRAM and the register spaces (E/SFR) have additionally been made directly

bitaddressable.

The internal data memory areas and the Special Function Register areas (SFR and

ESFR) are mapped into segment 0, the system segment.

The Program Management Unit (PMU) handles all code fetches and, therefore, controls

accesses to the program memories, such as Flash memory, ROM, and PSRAM.

The Data Management Unit (DMU) handles all data transfers and, therefore, controls

accesses to the DSRAM and the on-chip peripherals.

Both units (PMU and DMU) are connected via the high-speed system bus to exchange

data. This is required if operands are read from program memory, code or data is written

to the PSRAM, code is fetched from external memory, or data is read from or written to

external resources, including peripherals on the LXbus (such as TwinCAN). The system

bus allows concurrent two-way communication for maximum transfer performance.

128 Kbytes of on-chip Flash memory or mask-programmable ROM store code or

constant data. The on-chip Flash memory is organized as four 8-Kbyte sectors, one

32-Kbyte sector, and one 64-Kbyte sector. Each sector can be separately write

1)

protected , erased and programmed (in blocks of 128 Bytes). The complete Flash or

ROM area can be read-protected. A password sequence temporarily unlocks protected

areas. The Flash module combines very fast 64-bit one-cycle read accesses with

protected and efficient writing algorithms for programming and erasing. Thus, program

execution out of the internal Flash results in maximum performance. Dynamic error

correction provides extremely high read data security for all read accesses.

Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector

typically takes 200 ms (500 ms max.).

2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.

The PSRAM is accessed via the PMU and is therefore optimized for code fetches.

2 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user

data.The DSRAM is accessed via the DMU and is therefore optimized for data accesses.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user

defined variables, for the system stack, general purpose register banks. A register bank

can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7)

1)

Each two 8-Kbyte sectors are combined for write-protection purposes.

Data Sheet

15

V2.1, 2003-06

XC164

Derivatives

Functional Description

so-called General Purpose Registers (GPRs).

The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,

any location in the DPRAM is bitaddressable.

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the XC166 Family. Therefore, they should

either not be accessed, or written with zeros, to ensure upward compatibility.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can

be connected to the microcontroller. The External Bus Interface also provides access to

external peripherals.

1)

Table 3

XC164 Memory Map

2)

Address Area

Start Loc. End Loc. Area Size

Notes

3)

Flash register space

Reserved (Acc. trap)

Reserved for PSRAM

Program SRAM

FF’F000

FF’FFFF

H

4 Kbytes Flash only

H

F8’0000

FF’EFFF

<0.5 Mbytes Minus Flash regs

<1.5 Mbytes Minus PSRAM

2 Kbytes Maximum

< 2 Mbytes Minus Flash/ROM

128 Kbytes

H

E0’0800

E0’0000

F7’FFFF

H

E0’07FF

H

Reserved for pr. mem. C2’0000

DF’FFFF

H

Program Flash/ROM

Reserved

C0’0000

BF’0000

C1’FFFF

BF’FFFF

64 Kbytes

External memory area 40’0000

BE’FFFF

< 8 Mbytes Minus res. seg.

< 2 Mbytes Minus TwinCAN

2 Kbytes

H

4)

External IO area

20’0800

20’0000

3F’FFFF

H

TwinCAN registers

20’07FF

H

External memory area 01’0000

Data RAMs and SFRs 00’8000

1F’FFFF

< 2 Mbytes Minus segment 0

32 Kbytes Partly used

32 Kbytes

H

00’FFFF

External memory area 00’0000

00’7FFF

1)

Accesses to the shaded areas generate external bus accesses.

2)

3)

4)

The areas marked with “<“ are slightly smaller than indicated, see column “Notes”.

Not defined register locations return a trap code.

Several pipeline optimizations are not active within the external IO area. This is necessary to control external

peripherals properly.

Data Sheet

16

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.2

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus

Controller (EBC). It can be programmed either to Single Chip Mode when no external

1)

memory is required, or to one of four different external memory access modes , which

are as follows:

– 16 …24-bit Addresses, 16-bit Data, Demultiplexed

– 16 …24-bit Addresses, 16-bit Data, Multiplexed

– 16 …24-bit Addresses, 8-bit Data, Multiplexed

– 16 …24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/

output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses

and data use PORT0 for input/output. The high order address (segment) lines use

Port 4. The number of active segment address lines is selectable, restricting the external

address space to 8 Mbytes …64 Kbytes. This is required when interface lines are

assigned to Port 4.

Up to 4 external CS signals (3 windows plus default) can be generated in order to save

external glue logic. External modules can directly be connected to the common address/

data bus and their individual select lines.

Important timing characteristics of the external bus interface have been made

programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a

wide range of different types of memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via registers

ADDRSELx) which control the access to different resources with different bus

characteristics. These address windows are arranged hierarchically where window 4

overrides window 3, and window 2 overrides window 1. All accesses to locations not

covered by these 4 address windows are controlled by TCONCS0/FCONCS0. The

currently active window can generate a chip select signal.

The external bus timing is related to the rising edge of the reference clock output

CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.

The EBC also controls accesses to resources connected to the on-chip LXBus. The

LXBus is an internal representation of the external bus and allows accessing integrated

peripherals and modules in the same way as external components.

The TwinCAN module is connected and accessed via the LXBus.

1)

Bus modes are switched dynamically if several address windows with different mode settings are used.

Data Sheet

17

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.3

Central Processing Unit (CPU)

The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage

instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply

and accumulate unit (MAC), a register-file providing three register banks, and dedicated

SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel

shifter.

System-Bus

PMU

Internal Program Memory

CPU

DPRAM

2-Stage

Prefetch

Pipeline

CSP

IP

VECSEG

TFR

Prefetch Unit

CPUCON1

CPUCON2

CPUID

Branch Unit

FIFO

5-Stage

Pipeline

Injection/Exception

Handler

Return Stack

IFU

IPIP

IDX0

IDX1

QX0

QX1

QR0

QR1

DPP0

DPP1

DPP2

DPP3

SPSEG

SP

STKOV

STKUN

CP

R15

address

R15

R14

R15

R14

R15

R14

GPRs

+/-

ADU

GPRs

Division Unit Bit-Mask-Gen.

Multiply Unit Barrel-Shifter

MRW

R1

R0

Multiply Unit

R1

R0

R1

MCW

MSW

MDC

+/-

PSW

RF

Buffer

MAH

MAL

MDH

Zeros

MDL

Ones

data in

data out

MAC

ALU

WB

SRAM

DMU

Peripheral-Bus

System-Bus

Figure 4

CPU Block Diagram

Based on these hardware provisions, most of the XC164’s instructions can be executed

in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift

and rotate instructions are always processed during one machine cycle independent of

the number of bits to be shifted. Also multiplication and most MAC instructions execute

in one single cycle. All multiple-cycle instructions have been optimized so that they can

be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles,

while the remaining 15 cycles are executed in the background. Another pipeline

Data Sheet

18

V2.1, 2003-06

XC164

Derivatives

Functional Description

optimization, the branch target prediction, allows eliminating the execution time of

branch instructions if the prediction was correct.

The CPU has a register context consisting of up to three register banks with 16 wordwide

GPRs each at its disposal. One of these register banks is physically allocated within the

on-chip DPRAM area. A Context Pointer (CP) register determines the base address of

the active register bank to be accessed by the CPU at any time. The number of register

banks is only restricted by the available internal RAM space. For easy parameter

passing, a register bank may overlap others.

A system stack of up to 32 Kwords is provided as a storage for temporary data. The

system stack can be allocated to any location within the address space (preferably in the

on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.

Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack

pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently

be utilized by a programmer via the highly efficient XC164 instruction set which includes

the following instruction classes:

– Standard Arithmetic Instructions

– DSP-Oriented Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes

and words. A variety of direct, indirect or immediate addressing modes are provided to

specify the required operands.

Data Sheet

19

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.4

Interrupt System

With an interrupt response time of typically 8 CPU clocks (in case of internal program

execution), the XC164 is capable of reacting very fast to the occurrence of non-

deterministic events.

The architecture of the XC164 supports several mechanisms for fast and flexible

response to service requests that can be generated from various sources internal or

external to the microcontroller. Any of these interrupt requests can be programmed to

being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is

suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a

single byte or word data transfer between any two memory locations with an additional

increment of either the PEC source, or the destination pointer, or both. An individual PEC

transfer counter is implicitly decremented for each PEC service except when performing

in the continuous transfer mode. When this counter reaches zero, a standard interrupt is

performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data.

The XC164 has 8 PEC channels each of which offers such fast interrupt-driven data

transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable

flag and an interrupt priority bitfield exists for each of the possible interrupt nodes. Via its

related register, each node can be programmed to one of sixteen interrupt priority levels.

Once having been accepted by the CPU, an interrupt service can only be interrupted by

a higher prioritized service request. For the standard interrupt processing, each of the

possible interrupt nodes has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high

precision requirements. These fast interrupt inputs feature programmable edge

detection (rising edge, falling edge, or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with

an individual trap (interrupt) number.

Table 4 shows all of the possible XC164 interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may

be used to generate software controlled interrupt requests by setting the

respective interrupt request bit (xIR).

Data Sheet

20

V2.1, 2003-06

XC164

Derivatives

Functional Description

Table 4

XC164 Interrupt Nodes

Source of Interrupt or PEC

Service Request

Control

Register

Vector

Location

Trap

Number

1)

CAPCOM Register 0

CAPCOM Register 1

CAPCOM Register 2

CAPCOM Register 3

CAPCOM Register 4

CAPCOM Register 5

CAPCOM Register 6

CAPCOM Register 7

CAPCOM Register 8

CAPCOM Register 9

CAPCOM Register 10

CAPCOM Register 11

CAPCOM Register 12

CAPCOM Register 13

CAPCOM Register 14

CAPCOM Register 15

CAPCOM Register 16

CAPCOM Register 17

CAPCOM Register 18

CAPCOM Register 19

CAPCOM Register 20

CAPCOM Register 21

CAPCOM Register 22

CAPCOM Register 23

CAPCOM Register 24

CAPCOM Register 25

CAPCOM Register 26

CAPCOM Register 27

CAPCOM Register 28

CAPCOM Register 29

CC1_CC0IC

CC1_CC1IC

CC1_CC2IC

CC1_CC3IC

CC1_CC4IC

CC1_CC5IC

CC1_CC6IC

CC1_CC7IC

CC1_CC8IC

CC1_CC9IC

CC1_CC10IC

CC1_CC11IC

CC1_CC12IC

CC1_CC13IC

CC1_CC14IC

CC1_CC15IC

CC2_CC16IC

CC2_CC17IC

CC2_CC18IC

CC2_CC19IC

CC2_CC20IC

CC2_CC21IC

CC2_CC22IC

CC2_CC23IC

CC2_CC24IC

CC2_CC25IC

CC2_CC26IC

CC2_CC27IC

CC2_CC28IC

CC2_CC29IC

xx’0040

xx’0044

xx’0048

10 / 16

H

D

11 / 17

H

12 / 18

H

xx’004C

13 / 19

H

xx’0050

xx’0054

xx’0058

14 / 20

H

15 / 21

H

16 / 22

H

xx’005C

17 / 23

H

xx’0060

xx’0064

xx’0068

18 / 24

H

19 / 25

H

1A / 26

H

D

xx’006C

1B / 27

H

D

xx’0070

xx’0074

xx’0078

1C / 28

H

D

1D / 29

H

1E / 30

H

xx’007C

xx’00C0

xx’00C4

xx’00C8

1F / 31

H

30 / 48

H

31 / 49

H

32 / 50

H

xx’00CC

33 / 51

H

xx’00D0

xx’00D4

xx’00D8

34 / 52

H

35 / 53

H

36 / 54

H

xx’00DC

37 / 55

H

xx’00E0

xx’00E4

xx’00E8

38 / 56

H

39 / 57

H

3A / 58

H

D

xx’00EC

3B / 59

H

xx’00E0

3C / 60

H D

H

xx’0110

44 / 68

H D

H

Data Sheet

21

V2.1, 2003-06

XC164

Derivatives

Functional Description

Table 4

XC164 Interrupt Nodes (cont’d)

Source of Interrupt or PEC

Service Request

Control

Register

Vector

Location

Trap

Number

1)

CAPCOM Register 30

CAPCOM Register 31

CAPCOM Timer 0

CAPCOM Timer 1

CAPCOM Timer 7

CAPCOM Timer 8

GPT1 Timer 2

CC2_CC30IC

CC2_CC31IC

CC1_T0IC

CC1_T1IC

CC2_T7IC

CC2_T8IC

xx’0114

xx’0118

xx’0080

xx’0084

45 / 69

H

D

46 / 70

H

20 / 32

H

21 / 33

H

xx’00F4

xx’00F8

3D / 61

H

D

3E / 62

H

GPT12E_T2IC xx’0088

22 / 34

H

GPT1 Timer 3

GPT12E_T3IC xx’008C

23 / 35

H

GPT1 Timer 4

GPT12E_T4IC xx’0090

GPT12E_T5IC xx’0094

GPT12E_T6IC xx’0098

24 / 36

H

GPT2 Timer 5

25 / 37

H

GPT2 Timer 6

26 / 38

H

GPT2 CAPREL Reg.

A/D Conversion Compl.

A/D Overrun Error

ASC0 Transmit

ASC0 Transmit Buffer

ASC0 Receive

GPT12E_CRIC xx’009C

27 / 39

H

ADC_CIC

ADC_EIC

ASC0_TIC

ASC0_TBIC

ASC0_RIC

ASC0_EIC

ASC0_ABIC

SSC0_TIC

SSC0_RIC

SSC0_EIC

PLLIC

xx’00A0

xx’00A4

xx’00A8

28 / 40

H

29 / 41

H

2A / 42

H

D

xx’011C

47 / 71

H

D

xx’00AC

2B / 43

H D

H

ASC0 Error

xx’00B0

2C / 44

H

D

ASC0 Autobaud

SSC0 Transmit

SSC0 Receive

xx’017C

5F / 95

H

xx’00B4

xx’00B8

2D / 45

H

D

2E / 46

H

SSC0 Error

xx’00BC

2F / 47

H

PLL/OWD

xx’010C

43 / 67

H

2)

ASC1 Transmit

ASC1_TIC

ASC1_TBIC

ASC1_RIC

ASC1_EIC

ASC1_ABIC

EOPIC

xx’0120

xx’0178

xx’0124

xx’0128

xx’0108

xx’0130

xx’0134

48 / 72

H

ASC1 Transmit Buffer

ASC1 Receive

5E / 94

H

D

49 / 73

H

ASC1 Error

4A / 74

H

D

ASC1 Autobaud

End of PEC Subch.

CAPCOM6 Timer T12

42 / 66

H

4C / 76

H

D

CCU6_T12IC

4D / 77

H

Data Sheet

22

V2.1, 2003-06

XC164

Derivatives

Functional Description

Table 4

XC164 Interrupt Nodes (cont’d)

Source of Interrupt or PEC

Service Request

Control

Register

Vector

Location

xx’0138

Trap

Number

1)

CAPCOM6 Timer T13

CAPCOM6 Emergency

CAPCOM6

SSC1 Transmit

SSC1 Receive

SSC1 Error

CAN0

CCU6_T13IC

CCU6_EIC

CCU6_IC

SSC1_TIC

SSC1_RIC

SSC1_EIC

CAN_0IC

CAN_1IC

CAN_2IC

CAN_3IC

CAN_4IC

CAN_5IC

CAN_6IC

CAN_7IC

RTC_IC

---

4E / 78

H

D

xx’013C

4F / 79

H

xx’0140

xx’0144

xx’0148

50 / 80

H

51 / 81

H

52 / 82

H

xx’014C

53 / 83

H

xx’0150

xx’0154

xx’0158

54 / 84

H

CAN1

55 / 85

H

CAN2

56 / 86

H

CAN3

xx’015C

57 / 87

H

CAN4

xx’0164

xx’0168

59 / 89

H

CAN5

5A / 90

H

D

CAN6

xx’016C

5B / 91

H

D

CAN7

xx’0170

xx’0174

xx’0100

xx’0104

5C / 92

H

D

RTC

5D / 93

H

Unassigned node

40 / 64

H D

---

41 / 65

H D

---

xx’012C

4B / 75

H

D

---

xx’00FC

3F / 63

H

Unassigned node

---

xx’0160

58 / 88

H

1)

Register VECSEG defines the segment where the vector table is located to.

Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table

represents the default setting, with a distance of 4 (two words) between two vectors.

2)

The interrupt nodes assigned to ASC1 are only available in derivatives including the ASC1. Otherwise, they

are unassigned nodes.

Data Sheet

23

V2.1, 2003-06

XC164

Derivatives

Functional Description

The XC164 also provides an excellent mechanism to identify and to process exceptions

or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware

traps cause immediate non-maskable system reaction which is similar to a standard

interrupt service (branching to a dedicated vector table location). The occurence of a

hardware trap is additionally signified by an individual bit in the trap flag register (TFR).

Except when another higher prioritized trap service is in progress, a hardware trap will

interrupt any actual program execution. In turn, hardware trap services can normally not

be interrupted by standard or PEC interrupts.

Table 5 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 5

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number Priority

Trap

1)

Reset Functions:

–

– Hardware Reset

– Software Reset

– W-dog Timer Overflow

RESET

xx’0000

00

III

H

Class A Hardware Traps:

– Non-Maskable Interrupt NMI

NMITRAP

STOTRAP

STUTRAP

xx’0008

xx’0010

xx’0018

02

04

06

08

II

H

– Stack Overflow

– Stack Underflow

– Software Break

STKOF

STKUF

SOFTBRK SBRKTRAP xx’0020

Class B Hardware Traps:

– Undefined Opcode

– PMI Access Error

– Protected Instruction

Fault

UNDOPC BTRAP

xx’0028

0A

I

H

PACER

BTRAP

PRTFLT

– Illegal Word Operand

Access

ILLOPA

BTRAP

xx’0028

0A

I

H

Reserved

–

[2C –

[0B –

–

H

3C ]

0F ]

H

Software Traps

– TRAP Instruction

Any

Current

CPU

[xx’0000 – [00 –

H H

xx’01FC ] 7F ]

Priority

H

in steps

of 4

H

1)

Register VECSEG defines the segment where the vector table is located to.

Data Sheet

24

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.5

On-Chip Debug Support (OCDS)

The On-Chip Debug Support system provides a broad range of debug and emulation

features built into the XC164. The user software running on the XC164 can thus be

debugged within the target system environment.

The OCDS is controlled by an external debugging device via the debug interface,

consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger

controls the OCDS via a set of dedicated registers accessible via the JTAG interface.

Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.

An injection interface allows the execution of OCDS-generated instructions by the CPU.

Multiple breakpoints can be triggered by on-chip hardware, by software, or by an

external trigger input. Single stepping is supported as well as the injection of arbitrary

instructions and read/write access to the complete internal address space. A breakpoint

trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the

activation of an external signal.

Tracing data can be obtained via the JTAG interface or via the external bus interface for

increased performance.

The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to

communicate with external circuitry. These interface signals are realized as alternate

functions on Port 3 pins.

Complete system emulation is supported by the New Emulation Technology (NET)

interface. Via this full-featured emulation interface (including internal buses, control,

status, and pad signals) the XC164 chip can be connected to a NET carrier chip.

The use of the XC164 production chip together with the carrier chip provides superior

emulation behavior, because the emulation system shows exactly the same functionality

as the production chip (use of the identical silicon).

Data Sheet

25

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.6

Capture/Compare Units (CAPCOM1/2)

The CAPCOM units support generation and control of timing sequences on up to

32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered

mode). The CAPCOM units are typically used to handle high speed I/O tasks such as

pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)

conversion, software timing, or time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time

bases for each capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal

system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows

precise adjustments to the application specific requirements. In addition, external count

inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare

registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/

compare registers, each of which may be individually allocated to either CAPCOM timer

T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.

12 registers of the CAPCOM2 module have each one port pin associated with it which

serves as an input pin for triggering the capture function, or as an output pin to indicate

the occurrence of a compare event.

Table 6

Compare Modes (CAPCOM1/2)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1

Mode 2

Mode 3

Pin toggles on each compare match;

several compare events per timer period are possible

Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;

only one compare event per timer period is generated

Double Register

Mode

Two registers operate on one pin;

pin toggles on each compare match;

several compare events per timer period are possible

Single Event Mode

Generates single edges or pulses;

can be used with any compare mode

Data Sheet

26

V2.1, 2003-06

XC164

Derivatives

Functional Description

When a capture/compare register has been selected for capture mode, the current

contents of the allocated timer will be latched (‘captured’) into the capture/compare

register in response to an external event at the port pin which is associated with this

register. In addition, a specific interrupt request for this capture/compare register is

generated. Either a positive, a negative, or both a positive and a negative external signal

transition at the pin can be selected as the triggering event.

The contents of all registers which have been selected for one of the five compare modes

are continuously compared with the contents of the allocated timers.

When a match occurs between the timer value and the value in a capture/compare

register, specific actions will be taken based on the selected compare mode.

R eload R eg. TxREL

n

f_SYS

2

: 1

Tx

Input

C ontrol

Interrupt

Request

(TxIR )

TxIN

C AP CO M Tim er Tx

G PT1 Tim er T3

O ver/U nderflow

C CzIO

M ode

C ontrol

(C apture

or

16-Bit

Capture/Com pare

Interrupt R equests

(CC zIR)

C apture Inputs

Com pare O utputs

Capture/

Com pare

Registers

Com pare)

C CzIO

n

f_SYS

2

: 1

Ty

Input

C ontrol

Interrupt

Request

(TyIR )

C AP CO M Tim er Ty

G PT1 Tim er T3

O ver/U nderflow

x = 0, 7

y = 1, 8

n = 0/3 … 10

R eload R eg. TyREL

z = 0 … 31 (for interrupts),

= 16 … 27 (for pins)

M CB02143_X4.VSD

Figure 5

CAPCOM1/2 Unit Block Diagram

Data Sheet

27

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.7

The Capture/Compare Unit CAPCOM6

The CAPCOM6 unit supports generation and control of timing sequences on up to three

16-bit capture/compare channels plus one independent 10-bit compare channel.

In compare mode the CAPCOM6 unit provides two output signals per channel which

have inverted polarity and non-overlapping pulse transitions (deadtime control). The

compare channel can generate a single PWM output signal and is further used to

modulate the capture/compare output signals.

In capture mode the contents of compare timer T12 is stored in the capture registers

upon a signal transition at pins CCx.

Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked

by the prescaled system clock.

Mode

Select Register

CC6MSEL

Period Register

Trap Register

CTRAP

T12P

CC60

COUT60

Offset Register

T12OF

CC Channel 0

CC60

f_CPU

CC61

COUT61

CC Channel 1

CC61

Port

Control

Logic

Compare

Timer T12

16-Bit

CC62

COUT62

CC Channel 2

CC62

COUT63

Cntrol Register

CTCON

Compare

Timer T13

10-Bit

f_CPU

Compare Register

CMP13

Block

Commutation

Control

CC6POS0

CC6POS1

CC6POS2

Period Register

T13P

CC6MCON.H

MCB04109

The timer registers (T12, T13) are not directly accessible.

The period and offset registers are loading a value into the timer registers.

Figure 6

CAPCOM6 Block Diagram

For motor control applications both subunits may generate versatile multichannel PWM

signals which are basically either controlled by compare timer T12 or by a typical hall

sensor pattern at the interrupt inputs (block commutation).

Data Sheet

28

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.8

General Purpose Timer (GPT12E) Unit

The GPT12E unit represents a very flexible multifunctional timer/counter structure which

may be used for many different time related tasks such as event timing and counting,

pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT12E unit incorporates five 16-bit timers which are organized in two separate

modules, GPT1 and GPT2. Each timer in each module may operate independently in a

number of different modes, or may be concatenated with another timer of the same

module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for

one of four basic modes of operation, which are Timer, Gated Timer, Counter, and

Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from

the system clock, divided by a programmable prescaler, while Counter Mode allows a

timer to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the

operation of a timer is controlled by the ‘gate’ level on an external input pin. For these

purposes, each timer has one associated port pin (TxIN) which serves as gate or clock

input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.

The count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD) to

facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected

to the incremental position sensor signals A and B via their respective inputs TxIN and

TxEUD. Direction and count signals are internally derived from these two input signals,

so the contents of the respective timer Tx corresponds to the sensor position. The third

position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-

flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out

monitoring of external hardware components. It may also be used internally to clock

timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload

or capture registers for timer T3. When used as capture or reload registers, timers T2

and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a

signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2

or T4 triggered either by an external signal or by a selectable state transition of its toggle

latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite

state transitions of T3OTL with the low and high times of a PWM signal, this signal can

be constantly generated without software intervention.

Data Sheet

29

V2.1, 2003-06

XC164

Derivatives

Functional Description

n

f_{SY S}

2

: 1

Interrupt

Request

(T2IR )

G PT1 Tim er T2

U/D

T2IN

T2

M ode

Control

T2EUD

R eload

C apture

Interrupt

Request

(T3IR )

n

f_{SY S}

T3IN

2

: 1

Toggle FF

T3O TL

T3

M ode

G PT1 Tim er T3

T6O UT

Control

U/D

T3EUD

C apture

R eload

n

f_{SY S}

T4IN

2

: 1

T4

M ode

Control

Interrupt

Request

(T4IR )

G PT1 Tim er T4

U/D

T4EUD

M ct04825_xc.vsd

n = 2 … 12

Figure 7

Block Diagram of GPT1

With its maximum resolution of 2 system clock cycles, the GPT2 module provides

precise event control and time measurement. It includes two timers (T5, T6) and a

capture/reload register (CAPREL). Both timers can be clocked with an input clock which

is derived from the CPU clock via a programmable prescaler or with external signals. The

count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD).

Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,

which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin

T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the

CAPCOM1/2 timers, and to cause a reload from the CAPREL register.

The CAPREL register may capture the contents of timer T5 based on an external signal

transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared

Data Sheet

30

V2.1, 2003-06

XC164

Derivatives

Functional Description

after the capture procedure. This allows the XC164 to measure absolute time differences

or to perform pulse multiplication without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of

GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3

operates in Incremental Interface Mode.

Interrupt

Request

(T5IR )

n

f_{SY S}

T5IN

2

: 1

G PT2 Tim er T5

T5

M ode

C ontrol

U /D

Clear

T5EU D

C apture

G PT2 CAPR EL

T3IN/

T3EU D

Interrupt

Request

(C RIR)

M U X

CT3

CAPIN

Interrupt

Request

(T6IR )

C lear

G PT2 Tim er T6

Toggle FF

T6O TL

n

T6O UT

f_{SY S}

T6IN

2

: 1

T6

M ode

C ontrol

O ther

M odules

U /D

T6EU D

M cb03999_xc.vsd

n = 1 … 11

Figure 8

Block Diagram of GPT2

Data Sheet

31

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.9

Real Time Clock

The Real Time Clock (RTC) module of the XC164 is directly clocked via a separate clock

driver with the prescaled on-chip oscillator frequency (f_RTC= f_OSC/ 32). It is therefore

independent from the selected clock generation mode of the XC164.

The RTC basically consists of a chain of divider blocks:

• a selectable 8:1 divider (on - off)

• the reloadable 16-bit timer T14

• the 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:

– a reloadable 10-bit timer

– a reloadable 6-bit timer

– a reloadable 10-bit timer

All timers count up. Each timer can generate an interrupt request. All requests are

combined to a common node request.

PRE

RUN

f_RTC

1

8

RTCINT

M UX

0

Interrupt Sub Node

CNT

INT0

CNT

INT1

CNT

INT2

CNT

INT3

REL-Register

6 Bits 6 Bits

T14REL

10 Bits

10 B its

T14

10 Bits

6 Bits

10 B its

T14-Register

CNT-Register

m cb04805_xc.vsd

Figure 9

RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

Data Sheet

32

V2.1, 2003-06

XC164

Derivatives

Functional Description

The RTC module can be used for different purposes:

• System clock to determine the current time and date,

optionally during idle mode, sleep mode, and power down mode

• Cyclic time based interrupt, to provide a system time tick independent of CPU

frequency and other resources, e.g. to wake up regularly from idle mode.

• 48-bit timer for long term measurements (maximum timespan is >100 years).

• Alarm interrupt for wake-up on a defined time

Data Sheet

33

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.10

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 14 multiplexed input

channels and a sample and hold circuit has been integrated on-chip. It uses the method

of successive approximation. The sample time (for loading the capacitors) and the

conversion time is programmable (in two modes) and can thus be adjusted to the

external circuitry. The A/D converter can also operate in 8-bit conversion mode, where

the conversion time is further reduced.

Overrun error detection/protection is provided for the conversion result register

(ADDAT): either an interrupt request will be generated when the result of a previous

conversion has not been read from the result register at the time the next conversion is

complete, or the next conversion is suspended in such a case until the previous result

has been read.

For applications which require less analog input channels, the remaining channel inputs

can be used as digital input port pins.

The A/D converter of the XC164 supports four different conversion modes. In the

standard Single Channel conversion mode, the analog level on a specified channel is

sampled once and converted to a digital result. In the Single Channel Continuous mode,

the analog level on a specified channel is repeatedly sampled and converted without

software intervention. In the Auto Scan mode, the analog levels on a prespecified

number of channels are sequentially sampled and converted. In the Auto Scan

Continuous mode, the prespecified channels are repeatedly sampled and converted. In

addition, the conversion of a specific channel can be inserted (injected) into a running

sequence without disturbing this sequence. This is called Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the

conversion results into a table in memory for later evaluation, without requiring the

overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs

calibration cycles. This automatic self-calibration constantly adjusts the converter to

changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal

operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise

those pins used for analog input can be disconnected from the digital IO or input stages

under software control. This can be selected for each pin separately via register P5DIDIS

(Port 5 Digital Input Disable).

The Auto-Power-Down feature of the A/D converter minimizes the power consumption

when no conversion is in progress.

Data Sheet

34

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.11

Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)

The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial

communication with other microcontrollers, processors, terminals or external peripheral

components. They are upward compatible with the serial ports of the Infineon 8-bit

microcontroller families and support full-duplex asynchronous communication and half-

duplex synchronous communication. A dedicated baud rate generator with a fractional

divider precisely generates all standard baud rates without oscillator tuning. For

transmission, reception, error handling, and baudrate detection 5 separate interrupt

vectors are provided.

In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted

or received, preceded by a start bit and terminated by one or two stop bits. For

multiprocessor communication, a mechanism to distinguish address from data bytes has

been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to

115.2 kbit/s with fixed or programmable IrDA pulse width are supported.

In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift

clock which is generated by the ASC0/1. The LSB is always shifted first.

In both modes, transmission and reception of data is FIFO-buffered. An autobaud

detection unit allows to detect asynchronous data frames with its baudrate and mode

with automatic initialization of the baudrate generator and the mode control bits.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated, if the last

character received has not been read out of the receive buffer register at the time the

reception of a new character is complete.

Summary of Features

• Full-duplex asynchronous operating modes

– 8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking

– Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)

– Multiprocessor mode for automatic address/data byte detection

– Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)

– Loop-back capability

– Auto baudrate detection

• Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)

• Buffered transmitter/receiver with FIFO support (8 entries per direction)

• Loop-back option available for testing purposes

• Interrupt generation on transmitter buffer empty condition, last bit transmitted

condition, receive buffer full condition, error condition (frame, parity, overrun error),

start and end of an autobaud detection

Note: The serial interface ASC1 is not available in all derivatives of the XC164.

Data Sheet

35

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.12

High Speed Synchronous Serial Channels (SSC0/SSC1)

The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-

duplex synchronous communication. It may be configured so it interfaces with serially

linked peripheral components, full SPI functionality is supported.

A dedicated baud rate generator allows to set up all standard baud rates without

oscillator tuning. For transmission, reception and error handling three separate interrupt

vectors are provided.

The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift

clock which can be generated by the SSC (master mode) or by an external master (slave

mode). The SSC can start shifting with the LSB or with the MSB and allows the selection

of shifting and latching clock edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. Transmit error and receive error supervise the correct

handling of the data buffer. Phase error and baudrate error detect incorrect serial data.

Summary of Features

• Master or Slave mode operation

• Full-duplex or Half-duplex transfers

• Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)

• Flexible data format

– Programmable number of data bits: 2 to 16 bits

– Programmable shift direction: LSB-first or MSB-first

– Programmable clock polarity: idle low or idle high

– Programmable clock/data phase: data shift with leading or trailing clock edge

• Loop back option available for testing purposes

• Interrupt generation on transmitter buffer empty condition, receive buffer full condition,

error condition (receive, phase, baudrate, transmit error)

• Three pin interface with flexible SSC pin configuration

Data Sheet

36

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.13

TwinCAN Module

The integrated TwinCAN module handles the completely autonomous transmission and

reception of CAN frames in accordance with the CAN specification V2.0 part B (active),

i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit

identifiers as well as extended frames with 29-bit identifiers.

Two Full-CAN nodes share the TwinCAN module’s resources to optimize the CAN bus

traffic handling and to minimize the CPU load. The module provides up to 32 message

objects, which can be assigned to one of the CAN nodes and can be combined to FIFO-

structures. Each object provides separate masks for acceptance filtering.

The flexible combination of Full-CAN functionality and FIFO architecture reduces the

efforts to fulfill the real-time requirements of complex embedded control applications.

Improved CAN bus monitoring functionality as well as the number of message objects

permit precise and comfortable CAN bus traffic handling.

Gateway functionality allows automatic data exchange between two separate CAN bus

systems, which reduces CPU load and improves the real time behavior of the entire

system.

The bit timing for both CAN nodes is derived from the master clock and is programmable

up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 4, Port 7, or Port 9 to

interface to an external bus transceiver. The interface pins are assigned via software.

TwinC AN M odule Kernel

f_{C AN}

C AN

Node A

CAN

N ode B

C lock

C ontrol

TXDC A

R XD CA

Address

Decoder

Port

M essage

Control

O bject

Buffer

TXDC B

R XD CB

Interrupt

C ontrol

TwinC AN C ontrol

M CB04515

Figure 10

TwinCAN Module Block Diagram

Data Sheet

37

V2.1, 2003-06

XC164

Derivatives

Functional Description

Summary of Features

• CAN functionality according to CAN specification V2.0B active.

• Data transfer rate up to 1 Mbit/s

• Flexible and powerful message transfer control and error handling capabilities

• Full-CAN functionality and Basic CAN functionality for each message object

• 32 flexible message objects

– Assignment to one of the two CAN nodes

– Configuration as transmit object or receive object

– Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm

– Handling of frames with 11-bit or 29-bit identifiers

– Individual programmable acceptance mask register for filtering for each object

– Monitoring via a frame counter

– Configuration for Remote Monitoring Mode

• Up to eight individually programmable interrupt nodes can be used

• CAN Analyzer Mode for bus monitoring is implemented

Note: When a CAN node has the interface lines assigned to Port 4, the segment address

output on Port 4 must be limited. CS lines can be used to increase the total amount

of addressable external memory.

3.14

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can be disabled

until the EINIT instruction has been executed (compatible mode), or it can be disabled

and enabled at any time by executing instructions DISWDT and ENWDT (enhanced

mode). Thus, the chip’s start-up procedure is always monitored. The software has to be

designed to restart the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/

256. The high byte of the Watchdog Timer register can be set to a prespecified reload

value (stored in WDTREL) in order to allow further variation of the monitored time

interval. Each time it is serviced by the application software, the high byte of the

Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between

13 µs and 419 ms can be monitored (@ 40 MHz).

The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).

Data Sheet

38

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.15

Clock Generation

The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers

to generate the clock signals for the XC164 with high flexibility. The master clock f_MCis

the reference clock signal, and is used for TwinCAN and is output to the external system.

The CPU clock f_CPUand the system clock f_SYSare derived from the master clock either

directly (1:1) or via a 2:1 prescaler (f_SYS= f_CPU= f_MC/ 2). See also Section 5.1.

The on-chip oscillator can drive an external crystal or accepts an external clock signal.

The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable

factor) or can be divided by a programmable prescaler factor.

If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent

clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is

independent from the XTAL1 clock. When the expected oscillator clock transitions are

missing the Oscillator Watchdog (OWD) activates the PLL Unlock / OWD interrupt node

and supplies the CPU with an emergency clock, the PLL clock signal. Under these

circumstances the PLL will oscillate with its basic frequency.

The oscillator watchdog can be disabled by switching the PLL off. This reduces power

consumption, but also no interrupt request will be generated in case of a missing

oscillator clock.

Note: At the end of an external reset (EA = ‘0’) the oscillator watchdog may be disabled

via hardware by (externally) pulling the RD line low upon a reset, similar to the

standard reset configuration.

3.16

Parallel Ports

The XC164 provides up to 79 I/O lines which are organized into six input/output ports

and one input port. All port lines are bit-addressable, and all input/output lines are

individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O

ports are true bidirectional ports which are switched to high impedance state when

configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)

for push/pull operation or open-drain operation via control registers. During the internal

reset, all port pins are configured as inputs (except for pin RSTOUT).

The edge characteristics (shape) and driver characteristics (output current) of the port

drivers can be selected via registers POCONx.

The input threshold of some ports is selectable (TTL or CMOS like), where the special

CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The

input threshold may be selected individually for each byte of the respective ports.

All port lines have programmable alternate input or output functions associated with

them. All port lines that are not used for these alternate functions may be used as general

purpose IO lines.

Data Sheet

39

V2.1, 2003-06

XC164

Derivatives

Functional Description

Table 7

Port

Summary of the XC164’s Parallel Ports

Control

Alternate Functions

1)

PORT0

PORT1

Pad drivers

Address/Data lines or data lines

2)

Address lines

Capture inputs or compare outputs,

Serial interface lines,

Fast external interrupt inputs

Port 3

Port 4

Pad drivers,

Open drain,

Timer control signals, serial interface lines,

Optional bus control signal BHE/WRH,

Input threshold System clock output CLKOUT (or FOUT),

Debug interface lines

3)

Pad drivers,

Open drain,

Input threshold

Segment address lines

Optional chip select signals

4)

CAN interface lines

Port 5

Port 9

---

Analog input channels to the A/D converter,

Timer control signals

Pad drivers,

Open drain,

Input threshold

Capture inputs or compare outputs

4)

CAN interface lines

Port 20

Pad drivers,

Open drain

Bus control signals RD, WR/WRL, ALE,

External access enable pin EA,

Reset indication output RSTOUT

1)

For multiplexed bus cycles.

For demultiplexed bus cycles.

2)

3)

4)

For more than 64 Kbytes of external resources.

Can be assigned by software.

Data Sheet

40

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.17

Power Management

The XC164 provides several means to control the power it consumes either at a given

time or averaged over a certain timespan. Three mechanisms can be used (partly in

parallel):

• Power Saving Modes switch the XC164 into a special operating mode (control via

instructions).

Idle Mode stops the CPU while the peripherals can continue to operate.

Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may

optionally continue running). Sleep Mode can be terminated by external interrupt

signals.

• Clock Generation Management controls the distribution and the frequency of

internal and external clock signals. While the clock signals for currently inactive parts

of logic are disabled automatically, the user can reduce the XC164’s CPU clock

frequency which drastically reduces the consumed power.

External circuitry can be controlled via the programmable frequency output FOUT.

• Peripheral Management permits temporary disabling of peripheral modules (control

via register SYSCON3). Each peripheral can separately be disabled/enabled.

The on-chip RTC supports intermittend operation of the XC164 by generating cyclic

wake-up signals. This offers full performance to quickly react on action requests while

the intermittend sleep phases greatly reduce the average power consumption of the

system.

Data Sheet

41

V2.1, 2003-06

XC164

Derivatives

Functional Description

3.18

Instruction Set Summary

Table 8 lists the instructions of the XC164 in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation

of the instructions, parameters for conditional execution of instructions, and the opcodes

for each instruction can be found in the “Instruction Set Manual”.

This document also provides a detailled description of each instruction.

Table 8

Instruction Set Summary

Description

Mnemonic

ADD(B)

Bytes

2 / 4

Add word (byte) operands

ADDC(B)

SUB(B)

Add word (byte) operands with Carry

Subtract word (byte) operands

Subtract word (byte) operands with Carry

SUBC(B)

MUL(U)

(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

DIV(U)

DIVL(U)

CPL(B)

Complement direct word (byte) GPR

Negate direct word (byte) GPR

2

NEG(B)

2

AND(B)

Bitwise AND, (word/byte operands)

Bitwise (exclusive)OR, (word/byte operands)

Clear/Set direct bit

2 / 4

2

(X)OR(B)

BCLR / BSET

BMOV(N)

Move (negated) direct bit to direct bit

AND/OR/XOR direct bit with direct bit

4

BAND / BOR /

BXOR

4

BCMP

Compare direct bit to direct bit

4

BFLDH / BFLDL

Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

Compare word (byte) operands

2 / 4

Compare word data to GPR and decrement GPR by 1/2 2 / 4

Compare word data to GPR and increment GPR by 1/2

2 / 4

2

Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR

SHL / SHR

ROL / ROR

ASHR

Shift left/right direct word GPR

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

Move word (byte) data

2

MOV(B)

2 / 4

MOVBS/Z

Move byte operand to word op. with sign/zero extension 2 / 4

Data Sheet

42

V2.1, 2003-06

XC164

Derivatives

Functional Description

Table 8

Mnemonic

JMPA/I/R

JMPS

Instruction Set Summary (cont’d)

Description

Bytes

Jump absolute/indirect/relative if condition is met

Jump absolute to a code segment

4

JB(C)

Jump relative if direct bit is set (and clear bit)

Jump relative if direct bit is not set (and set bit)

JNB(S)

CALLA/I/R

CALLS

Call absolute/indirect/relative subroutine if condition is met 4

Call absolute subroutine in any code segment

4

PCALL

Push direct word register onto system stack and call

absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

Push/pop direct word register onto/from system stack

2

4

PUSH / POP

SCXT

Push direct word register onto system stack and update

register with word operand

RET(P)

Return from intra-segment subroutine

2

(and pop direct word register from system stack)

RETS

Return from inter-segment subroutine

Return from interrupt service subroutine

Software Break

2

RETI

2

SBRK

SRST

2

Software Reset

4

IDLE

Enter Idle Mode

4

PWRDN

SRVWDT

Enter Power Down Mode (supposes NMI-pin being low)

Service Watchdog Timer

4

DISWDT/ENWDT Disable/Enable Watchdog Timer

4

EINIT

Signify End-of-Initialization on RSTOUT-pin

4

ATOMIC

EXTR

Begin ATOMIC sequence

2

Begin EXTended Register sequence

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

Null operation

2

EXTP(R)

EXTS(R)

NOP

2 / 4

2

CoMUL / CoMAC Multiply (and accumulate)

4

CoADD / CoSUB Add / Subtract

4

Co(A)SHR/CoSHL (Arithmetic) Shift right / Shift left

CoLOAD/STORE Load accumulator / Store MAC register

CoCMP/MAX/MIN Compare (maximum/minimum)

CoABS / CoRND Absolute value / Round accumulator

CoMOV/NEG/NOP Data move / Negate accumulator / Null operation

4

Data Sheet

43

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

4

Electrical Parameters

4.1

Absolute Maximum Ratings

Table 9

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

min. max.

Unit

Notes

Storage temperature

Junction temperature

T_ST

T_J

-65

-40

-0.5

150

3.25

° C

V

–

under bias

–

Voltage on V_DDIpins with V_DDI

respect to ground (V_SS)

Voltage on V_DDPpins with V_DDP

respect to ground (V_SS)

-0.5

-10

–

6.2

V

–

Voltage on any pin with

V_IN

V_DDP

+ 0.5

V

respect to ground (V_SS)

Input current on any pin

during overload condition

–

10

mA

Absolute sum of all input

currents during overload

condition

–

|100|

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN> V_DDPor V_IN< V_SS)

the voltage on V_DDPpins with respect to ground (V_SS) must not exceed the values

defined by the absolute maximum ratings.

4.2

Package Properties

Table 10

Package Parameters (P-TQFP-100-16)

Parameter

Symbol

Limit Values

min. max.

Unit

Notes

Power dissipation

P_DISS

R_THA

–

0.8

29

W

–

Thermal Resistance

K/W

Chip-Ambient

Data Sheet

44

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

4.3

Operating Conditions

The following operating conditions must not be exceeded to ensure correct operation of

the XC164. All parameters specified in the following sections refer to these operating

conditions, unless otherwise noticed.

Table 11

Operating Condition Parameters

Symbol Limit Values

min. max.

2.35 2.7

Parameter

Unit Notes

Digital supply voltage for V_DDI

V

Active mode,

f_CPU= f_CPUmax

1)

the core

2)

Digital supply voltage for V_DDP

IO pads

4.4

5.5

–

Active mode

3)

Supply Voltage Difference ∆V_DD

-0.5

V

V_DDP- V_DDI

Digital ground voltage

Overload current

V_SS

I_OV

0

Reference voltage

4)5)

-5

-2

5

mA Per IO pin

mA Per analog input

4)5)

-4

-3

-2

Overload current coupling K_OVA

factor for analog inputs

–

1.0 × 10

1.5 × 10

5.0 × 10

1.0 × 10

50

–

I_OV> 0

I_OV< 0

I_OV> 0

6)

–

Overload current coupling K_OVD

–

6)

factor for digital I/O pins

–

I_OV< 0

5)

Absolute sum of overload Σ|I_OV|

mA

currents

External Load

Capacitance

C_L

T_A

–

50

pF

Pin drivers in

default mode

7)

Ambient temperature

0

70

° C

SAB-XC164 …

SAF-XC164 …

SAK-XC164 …

-40

85

125

1)

f_CPUmax= 40 MHz for devices marked …40F, f_CPUmax= 20 MHz for devices marked …20F.

2)

External circuitry must guarantee low level at the RSTIN pin at least until both power supply voltages have

reached the operating level.

3)

This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down, and

power-save modes.

Data Sheet

45

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

4)

Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range: V_OV> V_DDP+ 0.5 V (I_OV> 0) or V_OV< V_SS- 0.5 V (I_OV< 0). The absolute sum

of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the

specified limits.

Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,

etc.

5)

6)

Not 100% tested, guaranteed by design and characterization.

An overload current (I_OV) through a pin injects a certain error current (I_INJ) into the adjacent pins. This error

current adds to the respective pin’s leakage current (I_OZ). The amount of error current depends on the overload

current and is defined by the overload coupling factor K_OV. The polarity of the injected error current is inverse

compared to the polarity of the overload current that produces it.

The total current through a pin is |I_TOT| = |I_OZ| + (|I_OV| × K_OV). The additional error current may distort the input

voltage on analog inputs.

7)

The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output

current may lead to increased delays or reduced driving capability (C_L).

4.4

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the XC164

and partly its demands on the system. To aid in interpreting the parameters right, when

evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the XC164 will provide signals with the respective characteristics.

SR (System Requirement):

The external system must provide signals with the respective characteristics to the

XC164.

Data Sheet

46

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

4.5

DC Parameters

DC Characteristics

(Operating Conditions apply)

1)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Input low voltage TTL

(all except XTAL1)

V_ILSR -0.5

0.2× V_DDP

- 0.1

V

–

Input low voltage XTAL1

V_ILCSR -0.5

V_ILSSR -0.5

0.3 × V_DDI

V

–

2)

Input low voltage

0.45

(Special Threshold)

× V_DDP

Input high voltage TTL

(all except XTAL1)

V_IHSR 0.2× V_DDPV_DDP

V

–

+ 0.9

V_IHCSR 0.7

× V_DDI

+ 0.5

Input high voltage XTAL1

V_DDI

+ 0.5

Input high voltage

(Special Threshold)

V_IHSSR 0.8× V_DDPV_DDP

- 0.2

+ 0.5

Input Hysteresis

(Special Threshold)

HYS

0.04

–

V_DDPin [V],

Series

× V_DDP

resistance = 0 Ω

3)

Output low voltage

V_OLCC –

1.0

0.45

–

V

I_OL≤I_OLmax

3) 4)

–

I_OL≤I_OLnom

5)

3)

Output high voltage

V_OHCC V_DDP

I_OH≥ I_OHmax

- 1.0

3) 4)

V_DDP

–

V

I_OH≥ I_OHnom

- 0.45

6)

Input leakage current (Port 5) I_OZ1CC –

±300

±200

±500

nA 0 V < V_IN< V_DDP,

T_A≤125 °C

nA 0 V < V_IN< V_DDP,

12)

T_A≤85 °C

Input leakage current (all

I_OZ2CC –

nA 0.45 V < V_IN<

6)

other)

V_DDP

7)

8)

Configuration pull-up current I_CPUH

–

-10

–

µA V_IN= V_IHmin

µA V_IN= V_ILmax

9)

I_CPUL

-100

Data Sheet

47

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

DC Characteristics (cont’d)

(Operating Conditions apply)

1)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

10

8)

Configuration pull-down

current

I_CPDL

–

µA V_IN= V_ILmax

µA V_IN= V_IHmin

10)

9)

I_CPDH

120

–

11)

8)

Level inactive hold current

I_LHI

-10

µA V_OUT=

0.5 × V_DDP

µA V_OUT= 0.45 V

µA 0 V < V_IN< V_DDI

pF

11)

9)

Level active hold current

XTAL1 input current

I_LHA

-100

–

I_ILCC –

C_IOCC –

±20

10

12)

Pin capacitance

(digital inputs/outputs)

1)

Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications, also refer to the specification of the overload current I_OV

.

2)

3)

This parameter is tested for P2, P3, P4, P9.

The maximum deliverable output current of a port driver depends on the selected output driver mode, see

Table 12, Current Limits for Port Output Drivers. The limit for pin groups must be respected.

4)

5)

6)

As a rule, with decreasing output current the output levels approach the respective supply level (V_OL→V_SS

V_OH→V_DDP). However, only the levels for nominal output currents are guaranteed.

,

This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

An additional error current (I_INJ) will flow if an overload current flows through an adjacent pin. Please refer to

the definition of the overload coupling factor K_OV

.

7)

8)

9)

This specification is valid during Reset for configuration on RD, WR, EA, PORT0.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn to drive the respective signal line active.

¹⁰⁾This specification is valid during Reset for configuration on ALE.

¹¹⁾This specification is valid during Reset for pins P4.3-0, which can act as CS outputs.

¹²⁾Not 100% tested, guaranteed by design and characterization.

Data Sheet

48

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

Table 12

Current Limits for Port Output Drivers

Port Output Driver

Mode

Maximum Output Current

Nominal Output Current

1)

(I_OLmax, -I_OHmax

)

(I_OLnom, -I_OHnom

)

Strong driver

Medium driver

10 mA

2.5 mA

4.0 mA

1.0 mA

Weak driver

0.5 mA

0.1 mA

1)

An output current above |I_OXnom| may be drawn from up to three pins at the same time.

For any group of 16 neighboring port output pins the total output current in each direction (ΣI_OLand Σ-I_OH

)

must remain below 50 mA.

Power Consumption XC164

(Operating Conditions apply)

Parameter

Symbol

Limit Values

min. max.

Unit Test Condition

1)

Power supply current (active)

with all peripherals active

I_DDI

–

15 +

2.6 × f_CPU

mA

2)

f_CPUin [MHz]

3)

Pad supply current

I_DDP

I_IDX

–

5

mA

Idle mode supply current

with all peripherals active

15 +

1.2 × f_CPU

mA

2)

f_CPUin [MHz]

5)

6)

Sleep and Power-down mode

supply current caused by

leakage

I_PDL

–

128,000

× e

mA V_DDI=V_DDImax

-α

T_Jin [°C]

α =

4)

4670/(273+T_J)

7)

Sleep and Power-down mode

supply current caused by

I_PDM

–

0.6 +

0.02× f_OSC

+ I_PDL

mA V_DDI=V_DDImax

f_OSCin [MHz]

leakage and the RTC running,

4)

clocked by the main oscillator

1)

During Flash programming or erase operations the supply current is increased by max. 5 mA.

2)

3)

4)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 11.

These parameters are tested at V_DDImaxand maximum CPU clock frequency with all outputs disconnected and

all inputs at V_ILor V_IH.

The pad supply voltage pins (V_DDP) mainly provides the current consumed by the pin output drivers. A small

amount of current is consumed even though no outputs are driven, because the drivers’ input stages are

switched and also the Flash module draws some power from the V_DDPsupply.

The total supply current in Sleep and Power-down mode is the sum of the temperature dependent leakage

current and the frequency dependent current for RTC and main oscillator (if active).

Data Sheet

49

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

5)

This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the

junction temperature (see Figure 13). The junction temperature T_Jis the same as the ambient temperature T_A

if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be

taken into account.

6)

7)

All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V_DDP- 0.1 V to V_DDP, all outputs (including

pins configured as outputs) disconnected. This parameter is tested at 25 °C and is valid for T_J≥ 25 °C.

This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see

Figure 12). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The

given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.

Data Sheet

50

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

I [mA]

I_DDImax

140

120

100

I_DDItyp

80

60

40

20

I_IDXmax

I_IDXtyp

10

20

30

40

f_CPU[MHz]

Figure 11

Supply/Idle Current as a Function of Operating Frequency

Data Sheet

51

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

I [mA]

3.0

2.0

I_PDMmax

I_PDMtyp

1.0

0.1

I_PDAmax

32 kHz

4

8

12

16

f_OSC[MHz]

Figure 12

Sleep and Power Down Supply Current due to RTC and Oscillator

running, as a Function of Oscillator Frequency

I_PDO

[mA]

1.5

1.0

0.5

-50

0

50

100

150

T_J[°C]

Figure 13

Sleep and Power Down Leakage Supply Current as a Function of

Temperature

Data Sheet

52

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

4.6

A/D Converter Characteristics

Table 13

A/D Converter Characteristics

(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

max.

1)

Analog reference supply

Analog reference ground

V_AREF

4.5

V_DDP

+ 0.1

V

SR

V_AGND

V_SS- 0.1 V_SS+ 0.1 V

SR

2)

3)

Analog input voltage range V_AINSR V_AGND

V_AREF

V

Basic clock frequency

f_BC

0.5

20

MHz

–

Conversion time for 10-bit

result

t_C10PCC 52× t_BC+ t_S+ 6× t_SYS

t_C10CC 40× t_BC+ t_S+ 6× t_SYS

t_C8PCC 44× t_BC+ t_S+ 6× t_SYS

Post-calibr. on

Post-calibr. off

Post-calibr. on

4)

–

Conversion time for 8-bit

–

7)

result

t_C8

CC 32× t_BC+ t_S+ 6× t_SYS

–

Post-calibr. off

5)

Calibration time after reset t_CALCC 484

11,696

±2

t_BC

LSB

pF

1)

6)

Total unadjusted error

TUE CC –

Total capacitance

of an analog input

C_AINT

C_AINS

R_AIN

–

15

CC

6)

Switched capacitance

of an analog input

10

2

pF

kΩ

pF

kΩ

Resistance of

the analog input path

Total capacitance

of the reference input

C_AREFT

20

15

1

CC

Switched capacitance

of the reference input

C_AREFS

CC

Resistance of

R_AREF

the reference input path

CC

Data Sheet

53

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

1)

TUE is tested at V_AREF= V_DDP+ 0.1 V, V_AGND= 0 V. It is guaranteed by design for all other voltages within

the defined voltage range.

If the analog reference supply voltage drops below 4.5 V (i.e. V_AREF≥ 4.0 V) or exceeds the power supply

voltage by up to 0.2 V (i.e. V_AREF= V_DDP+ 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not

100% tested.

The specified TUE is guaranteed only, if the absolute sum of input overload currents on Port 5 pins (see I_OV

specification) does not exceed 10 mA, and if V_AREFand V_AGNDremain stable during the respective period of

time. During the reset calibration sequence the maximum TUE may be ±4 LSB.

2)

V_AINmay exceed V_AGNDor V_AREFup to the absolute maximum ratings. However, the conversion result in

these cases will be X000_Hor X3FF_H, respectively.

3)

4)

The limit values for f_BCmust not be exceeded when selecting the peripheral frequency and the ADCTC setting.

This parameter includes the sample time t_S, the time for determining the digital result and the time to load the

result register with the conversion result (t_SYS= 1 / f_SYS).

Values for the basic clock t_BCdepend on programming and can be taken from Table 14.

When the post-calibration is switched off, the conversion time is reduced by 12 x t_BC

5)

6)

The actual duration of the reset calibration depends on the noise on the reference signal. Conversions

executed during the reset calibration increase the calibration time. The TUE for those conversions may be

increased.

Not 100% tested, guaranteed by design and characterization.

The given parameter values cover the complete operating range. Under relaxed operating conditions

(temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominal

supply voltage the following typical values can be used:

C

_AINTtyp= 12 pF, C_AINStyp= 7 pF, R_AINtyp= 1.5 kΩ, C_AREFTtyp= 15 pF, C_AREFStyp= 13 pF, R_AREFtyp= 0.7 kΩ.

A/D Converter

R_Source

R _{AIN , O n}

V_{A IN}

C _Ext

C _{AIN T}

-

C _{AIN S}

=

m cs04879_p.vsd

Figure 14

Equivalent Circuitry for Analog Inputs

Data Sheet

54

V2.1, 2003-06

XC164

Derivatives

Electrical Parameters

Sample time and conversion time of the XC164’s A/D Converter are programmable. In

compatibility mode, the above timing can be calculated using Table 14.

The limit values for f_BCmust not be exceeded when selecting ADCTC.

1)

Table 14

A/D Converter Computation Table

ADCON.15|14 A/D Converter

ADCON.13|12 Sample time

(ADCTC)

Basic Clock f_BC

f_SYS/ 4

(ADSTC)

t_S

00

01

10

00

01

10

11

t_BC× 8

t_BC× 16

t_BC× 32

t_BC× 64

f_SYS/ 2

f_SYS/ 16

f_SYS/ 8

11

1)

These selections are available in compatibility mode. An improved mechanism to control the ADC input clock

can be selected.

Converter Timing Example:

Assumptions:

f_SYS= 40 MHz (i.e. t_SYS= 25 ns), ADCTC = ‘01’, ADSTC = ‘00’.

Basic clock

Sample time

f_BC

t_S

= f_SYS/ 2 = 20 MHz, i.e. t_BC= 50 ns.

= t_BC× 8 = 400 ns.

Conversion 10-bit:

With post-calibr. t_C10P= 52 × t_BC+ t_S+ 6 × t_SYS= (2600 + 400 + 150) ns = 3.15 µs.

Post-calibr. off

t_C10= 40 × t_BC+ t_S+ 6 × t_SYS= (2000 + 400 + 150) ns = 2.55 µs.

Conversion 8-bit:

With post-calibr. t_C8P= 44 × t_BC+ t_S+ 6 × t_SYS= (2200 + 400 + 150) ns = 2.75 µs.

Post-calibr. off = 32 × t_BC+ t_S+ 6 × t_SYS= (1600 + 400 + 150) ns = 2.15 µs.

t_C8

Data Sheet

55

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

5

Timing Parameters

5.1

Definition of Internal Timing

The internal operation of the XC164 is controlled by the internal master clock f_MC

.

The master clock signal f_MCcan be generated from the oscillator clock signal f_OSCvia

different mechanisms. The duration of master clock periods (TCMs) and their variation

(and also the derived external timing) depend on the used mechanism to generate f_MC

.

This influence must be regarded when calculating the timings for the XC164.

Phase Locked Loop Operation (1:N)

f_OSC

f_MC

TCM

Direct Clock Drive (1:1)

f_OSC

f_MC

TCM

Prescaler Operation (N:1)

f_OSC

f_MC

TCM

Figure 15

Generation Mechanisms for the Master Clock

Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,

the example for prescaler operation refers to a divider factor of 2:1.

The used mechanism to generate the master clock is selected by register PLLCON.

CPU and EBC are clocked with the CPU clock signal f_CPU. The CPU clock can have the

same frequency as the master clock (f_CPU= f_MC) or can be the master clock divided by

two: f_CPU= f_MC/ 2. This factor is selected by bit CPSYS in register SYSCON1.

The specification of the external timing (AC Characteristics) depends on the period of the

CPU clock, called “TCP”.

The other peripherals are supplied with the system clock signal f_SYSwhich has the same

frequency as the CPU clock signal f_CPU

.

Data Sheet

56

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

Bypass Operation

When bypass operation is configured (PLLCTRL = 0x ) the master clock is derived from

B

the internal oscillator (input clock signal XTAL1) through the input- and output-

prescalers:

f_MC= f_OSC/ ((PLLIDIV+1)× (PLLODIV+1)).

If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of f_MC

directly follows the frequency of f_OSCso the high and low time of f_MCis defined by the

duty cycle of the input clock f_OSC

.

The lowest master clock frequency is achieved by selecting the maximum values for both

divider factors:

f_MC= f_OSC/ ((3+1)× (14+1)) = f_OSC/ 60.

Phase Locked Loop (PLL)

When PLL operation is configured (PLLCTRL = 11 ) the on-chip phase locked loop is

B

enabled and provides the master clock. The PLL multiplies the input frequency by the

factor F (f_MC= f_OSC× F) which results from the input divider, the multiplication factor,

and the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit

synchronizes the master clock to the input clock. This synchronization is done smoothly,

i.e. the master clock frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of f_MCis constantly adjusted so it

is locked to f_OSC. The slight variation causes a jitter of f_MCwhich also affects the duration

of individual TCMs.

The timing listed in the AC Characteristics refers to TCPs. Because f_CPUis derived from

f_MC, the timing must be calculated using the minimum TCP possible under the respective

circumstances.

The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is

constantly adjusting its output frequency so it corresponds to the applied input frequency

(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than

for one single TCP (see formula and Figure 16).

This is especially important for bus cycles using waitstates and e.g. for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter

is negligible.

The value of the accumulated PLL jitter depends on the number of consecutive VCO

output cycles within the respective timeframe. The VCO output clock is divided by the

output prescaler (K = PLLODIV+1) to generate the master clock signal f_MC. Therefore,

the number of VCO cycles can be represented as K × N, where N is the number of

consecutive f_MCcycles (TCM).

Data Sheet

57

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

For a period of N × TCM the accumulated PLL jitter is defined by the deviation D :

N

D [ns] = ±(1.5 + 6.32 × N / f_MC); f_MCin [MHz], N = number of consecutive TCMs.

N

So, for a period of 3 TCMs @ 20 MHz and K = 12: D = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.

3

This formula is applicable for K × N < 95. For longer periods the K× N=95 value can be

used. This steady value can be approximated by: D

[ns] = ±(1.5 + 600 / (K × f_MC)).

Nmax

Acc. jitter D _N

K=15 K=12 K=10 K=8

K=6

K=5

ns

±8

±7

±6

±5

±4

±3

±2

±1

0

15

25

1

5

10

20

N

m cb04413_xc.vsd

Figure 16

Approximated Accumulated PLL Jitter

Note: The bold lines indicate the minimum accumulated jitter which can be achieved by

selecting the maximum possible output prescaler factor K.

Different frequency bands can be selected for the VCO, so the operation of the PLL can

be adjusted to a wide range of input and output frequencies:

1)

Table 15

VCO Bands for PLL Operation

PLLCON.PLLVB VCO Frequency Range

Base Frequency Range

20 …80 MHz

00

01

10

100 …150 MHz

150 …200 MHz

40 …130 MHz

200 …250 MHz

60 …180 MHz

11

Reserved

1)

Values guarnteed by design characterisation.

Data Sheet

58

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

5.2

External Clock Drive XTAL1

Table 16

External Clock Drive Characteristics

(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit

min.

t_OSCSR 20

max.

1)

Oscillator period

250

ns

2)

High time

t₁

t₂

t₃

t₄

SR 6

–

8

2)

Low time

SR 6

SR –

2)

Rise time

2)

Fall time

1)

The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.

2)

The clock input signal must reach the defined levels V_ILCand V_IHC

.

t₁

t₃

t₄

V_IHC

V_ILC

0.5 V_DDI

t₂

t_OSC

MCT05138

Figure 17

External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the

oscillator frequency is limited to a range of 4 MHz to 16 MHz.

It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimum

parameters for the oscillator operation. Please refer to the limits specified by the

crystal supplier.

When driven by an external clock signal it will accept the specified frequency

range. Operation at lower input frequencies is possible but is guaranteed by

design only (not 100% tested).

Data Sheet

59

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

5.3

Testing Waveforms

Input signal

(driven by tester)

Output signal

(measured)

2.0 V

0.8 V

0.45 V

Figure 18

Input Output Waveforms

V_Load+ 0.1 V

V_OH- 0.1 V

Timing

Reference

Points

V_Load- 0.1 V

V_OL+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

but begins to float when a 100 mV change from the loaded V_OH

/

V_OLlevel occurs (I_OH

/

I

_OL= 20 mA).

MCA00763

Figure 19

Float Waveforms

Data Sheet

60

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

5.4

AC Characteristics

Table 17

CLKOUT Reference Signal

Parameter

Symbol

Limits

max.

Unit

min.

1)

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

tc₅CC

40/30/25

ns

tc₆CC 8

tc₇CC 6

tc₈CC –

tc₉CC –

–

4

CLKOUT fall time

1)

The CLKOUT cycle time is influenced by the PLL jitter (given values apply to f_CPU= 25/33/40 MHz).

For longer periods the relative deviation decreases (see PLL deviation formula).

tc₉

tc₇

tc₈

tc₅

tc₆

CLKOUT

MCT04415

Figure 20

CLKOUT Signal Timing

Data Sheet

61

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

Variable Memory Cycles

External bus cycles of the XC164 are executed in five subsequent cycle phases (AB, C,

D, E, F). The duration of each cycle phase is programmable (via the TCONCSx

registers) to adapt the external bus cycles to the respective external module (memory,

peripheral, etc.).

This table provides a summary of the phases and the respective choices for their

duration.

Table 18

Programmable Bus Cycle Phases (see timing diagrams)

Parameter Valid Values Unit

Bus Cycle Phase

Address setup phase, the standard duration of this tp_AB

phase (1 …2 TCP) can be extended by 0 …3 TCP if

the address window is changed

1 …2 (5)

TCP

Command delay phase

tp_C

tp_D

tp_E

tp_F

0 …3

0 …1

1 …32

0 …3

TCP

Write Data setup / MUX Tristate phase

Access phase

Address / Write Data hold phase

Note: The bandwidth of a parameter (minimum and maximum value) covers the whole

operating range (temperature, voltage) as well as process variations. Within a

given device, however, this bandwidth is smaller than the specified range. This is

also due to interdependencies between certain parameters. Some of these

interdependencies are described in additional notes (see standard timing).

Data Sheet

62

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

Table 19

External Bus Cycle Timing (Operating Conditions apply)

Symbol Limits

min. max.

Parameter

Unit

Output valid delay for:

RD, WR(L/H)

tc₁₀CC 1

tc₁₁CC -1

tc₁₂CC 1

tc₁₃CC 3

tc₁₄CC 1

tc₁₅CC 3

tc₁₆CC 3

tc₂₀CC -3

tc₂₁CC 0

tc₂₃CC 1

tc₂₄CC -3

tc₂₅CC 1

tc₃₀SR 24

tc₃₁SR -5

13

ns

Output valid delay for:

A23…A16, BHE, ALE

7

Output valid delay for:

A15…A0 (on PORT1)

16

14

17

3

Output valid delay for:

A15…A0 (on PORT0)

Output valid delay for:

CS

Output valid delay for:

D15…D0 (write data, mux-mode)

Output valid delay for:

D15…D0 (write data, demux-mode)

Output hold time for:

RD, WR(L/H)

Output hold time for:

A23…A16, BHE, ALE

8

Output hold time for:

A15…A0 (on PORT0)

13

3

Output hold time for:

CS

Output hold time for:

D15…D0 (write data)

13

–

Input setup time for:

READY, D15…D0 (read data)

Input hold time

READY, D15…D0 (read data)

–

1)

Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read

data can be removed after the rising edge of RD.

Note: The shaded parameters have been verified by characterization.

They are not 100% tested.

Data Sheet

63

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

tp

AB

C

D

E

F

CLKOUT

tc

21

11

ALE

tc |tc

11 14

A23-A16,

BHE, CSx

High Address

tc

20

10

RD

WR(L/H)

tc

31

13

23

30

AD15-AD0

(read)

Low Address

Data In

tc

25

15

AD15-AD0

(write)

Data Out

Figure 21

Multiplexed Bus Cycle

Data Sheet

64

V2.1, 2003-06

XC164

Derivatives

Timing Parameters

tp

AB

C

D

E

F

CLKOUT

tc

21

11

ALE

tc |tc

11 14

A23-A0,

BHE, CSx

Address

tc

20

10

RD

WR(L/H)

tc

31

30

D15-D0

(read)

Data In

tc

25

16

D15-D0

(write)

Data Out

Figure 22

Demultiplexed Bus Cycle

Data Sheet

65

V2.1, 2003-06

XC164

Derivatives

Packaging

6

Packaging

P-TQFP-100-16

(Plastic Metric Quad Flat Package)

Figure 23

Package Outlines P-TQFP-100-16

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

V2.1, 2003-06

SMD = Surface Mounted Device

Data Sheet

66

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	SAF-XC164CS-16R40F
厂家：	Infineon
描述：	16-Bit Single-Chip Microcontroller 16位单芯片微控制器微控制器和处理器外围集成电路时钟
文件：	总71页 (文件大小：2628K)
中文：	中文翻译
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SAF-XC164CS-16R40F [INFINEON]

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