SAF-XC164N-16F20F [INFINEON]
16-Bit Single-Chip Microcontroller with C166SV2 Core; 16位单芯片微控制器，带有C166SV2核心
| 型号： | SAF-XC164N-16F20F |
| 厂家： | 
Infineon |
| 描述： | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| 文件： | 总68页 (文件大小：981K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V1.0, Jan. 2005
XC164N
16-Bit Single-Chip Microcontroller
with C166SV2 Core
Microcontrollers
N e v e r s t o p t h i n k i n g .
Edition 2005-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.0, Jan. 2005
XC164N
16-Bit Single-Chip Microcontroller
with C166SV2 Core
Microcontrollers
N e v e r s t o p t h i n k i n g .
XC164N
Revision History:
2005-01
V1.0
Previous Version:
None
Page
Subjects (major changes since last revision)
Controller Area Network (CAN): License of Robert Bosch GmbH
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Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15
XC164-32
Derivatives
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 35
High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 36
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1
4.2
4.3
4.4
4.5
5
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1
5.2
5.3
5.4
6
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Data Sheet
1
V1.0, 2005-01
XC164N
Derivatives
Summary of Features
1
Summary of Features
• High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with up to 65 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 2 Kbytes On-Chip Data SRAM (DSRAM)
– 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
– up to 128 Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
– Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)
(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip Real Time Clock
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Four Programmable Chip-Select Signals
• Up to 79 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
Data Sheet
1
V1.0, 2005-01
XC164N
Derivatives
Summary of Features
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 100-Pin TQFP Package, 0.5 mm (19.7 mil) pitch
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the XC164N please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes several derivatives of the XC164 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC164N throughout this document.
Data Sheet
2
V1.0, 2005-01
XC164N
Derivatives
Summary of Features
Table 1
Derivative1)
XC164N Derivative Synopsis
Program Memory On-Chip RAM
Inter-
faces
Clock
SAF-XC164N-16F40F
SAF-XC164N-16F20F
SAF-XC164N-8F40F
SAF-XC164N-8F20F
128 Kbytes Flash
128 Kbytes Flash
64 Kbytes Flash
64 Kbytes Flash
2Kbytes DPRAM, ASC0, 40
2Kbytes DSRAM, ASC1, MHz
2Kbytes PSRAM
SSC0,
SSC1
2Kbytes DPRAM, ASC0, 20
2Kbytes DSRAM, ASC1, MHz
2Kbytes PSRAM
SSC0,
SSC1
2Kbytes DPRAM, ASC0, 40
2Kbytes DSRAM, ASC1, MHz
2Kbytes PSRAM
SSC0,
SSC1
2Kbytes DPRAM, ASC0, 20
2Kbytes DSRAM, ASC1, MHz
2Kbytes PSRAM
SSC0,
SSC1
1) This Data Sheet is valid for devices starting with and including design step BA.
Data Sheet
3
V1.0, 2005-01
XC164N
Derivatives
General Device Information
2
General Device Information
2.1
Introduction
The XC164N derivatives are high-performance members of the Infineon XC166 Family
of full featured single-chip CMOS microcontrollers. These devices extend the
functionality and performance of the C166 Family in terms of instructions (MAC unit),
peripherals, and speed. They combine high CPU performance (up to 40 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities.
They also provide clock generation via PLL and various on-chip memory modules such
as program Flash, program RAM, and data RAM.
VDDP
VDDI/P
VSSI/P
VSSP
XTAL1
XTAL2
PORT0
16 bit
PORT1
16 bit
NMI
RSTIN
Port 3
14 bit
XC164N
RSTOUT
EA
Port 4
8 bit
Port 20
5 bit
ALE
RD
WR/WRL
Port 9
6 bit
Port 5
14 bit
TRST JTAG Debug
Via Port 3
Figure 1
Logic Symbol
Data Sheet
4
V1.0, 2005-01
XC164N
Derivatives
General Device Information
2.2
Pin Configuration and Definition
The pins of the XC164N are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) marks pins to be used as alternate external interrupt
inputs.
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RSTIN
P20.12/RSTOUT
NMI
P0H.4/AD12
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
P20.5/EA
P20.4/ALE
P20.1/WR/WRL
P20.0/RD
VSSP
1
2
3
4
5
6
7
8
P0H.0/AD8
P0H.1/AD9
P0H.2/AD10
P0H.3/AD11
VSSP
VDDP
9
P9.0/CC16IO
P9.1/CC17IO
P9.2/CC18IO
P9.3/CC19IO
P9.4/CC20IO
P9.5/CC21IO
VSSP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
XC164N
VDDP
P4.7/A23/C*)
P4.6/A22/C*)
P4.5/A21/C*)
P4.4/A20/C*)
P4.3/A19/CS0
P4.2/A18/CS1
P4.1/A17/CS2
P4.0/A16/CS3
P3.15/CLKOUT/FO
P3.13/SCLK0/E*)
VDDP
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10/T6EUD
P5.11/T5EUD
Figure 2
Pin Configuration (top view)
Data Sheet
5
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions
Input Function
Symbo Pin
l
Num. Outp.
RSTIN 1
I
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the XC164N.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the
hardware configuration signals settle.
External circuitry must guarantee low level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
P20.12 2
IO
I
For details, please refer to the description of P20.
NMI
3
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164N into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
P0H.0- 4…7
IO
For details, please refer to the description of PORT0.
P0H.3
Data Sheet
6
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
Input Function
l
Num. Outp.
P9
IO
Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 9 is selectable (standard
or special).
The following Port 9 pins also serve for alternate functions:
P9.0
P9.1
P9.2
P9.3
10
11
12
13
I/O
CC16IO
CAPCOM2: CC16 Capture Inp./Compare Outp.,
I
EX7IN
CC17IO
Fast External Interrupt 7 Input (alternate pin B)
CAPCOM2: CC17 Capture Inp./Compare Outp.,
I/O
I
EX6IN
CC18IO
Fast External Interrupt 6 Input (alternate pin B)
CAPCOM2: CC18 Capture Inp./Compare Outp.,
I/O
I
EX7IN
CC19IO
Fast External Interrupt 7 Input (alternate pin A)
CAPCOM2: CC19 Capture Inp./Compare Outp.,
I/O
I
EX6IN
CC20IO
CC21IO
Fast External Interrupt 6 Input (alternate pin A)
CAPCOM2: CC20 Capture Inp./Compare Outp.
CAPCOM2: CC21 Capture Inp./Compare Outp.
P9.4
P9.5
14
15
I/O
I/O
P5
I
Port 5 is a 14-bit input-only port.
Some pins of Port 5 serve as timer inputs:
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10
P5.11
P5.6
18
19
20
21
22
23
24
25
26
27
30
31
32
33
I
I
I
I
I
I
I
I
I
I
I
I
I
I
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
No Alternate Function beside General Purpose Input
T6EUD
T5EUD
GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
P5.7
T6IN
T5IN
T4EUD
T2EUD
GPT2 Timer T6 Count/Gate Input
GPT2 Timer T5 Count/Gate Input
GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
P5.12
P5.13
P5.14
P5.15
Data Sheet
7
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
Input Function
l
Num. Outp.
TRST
36
I
Test-System Reset Input. A high level at this pin activates
the XC164N’s debug system. For normal system operation,
pin TRST should be held low.
P3
IO
Port 3 is a 14-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 3 is selectable (standard
or special).
The following Port 3 pins also serve for alternate functions:
P3.1
39
O
I/O
I
T6OUT
RxD1
EX1IN
TCK
GPT2 Timer T6 Toggle Latch Output,
ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
Fast External Interrupt 1 Input (alternate pin A),
Debug System: JTAG Clock Input
I
P3.2
P3.3
P3.4
P3.5
40
41
42
43
I
I
O
O
I
I
I
O
O
I
CAPIN
TDI
T3OUT
TDO
T3EUD
TMS
T4IN
GPT2 Register CAPREL Capture Input,
Debug System: JTAG Data In
GPT1 Timer T3 Toggle Latch Output,
Debug System: JTAG Data Out
GPT1 Timer T3 External Up/Down Control Input,
Debug System: JTAG Test Mode Selection
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
ASC0 Clock/Data Output (Async./Sync.),
TxD1
BRKOUT Debug System: Break Out
T3IN
T2IN
P3.6
P3.7
44
45
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
Debug System: Break In
I
I
BRKIN
MRST0
MTSR0
TxD0
EX2IN
RxD0
EX2IN
BHE
P3.8
P3.9
P3.10
46
47
48
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
SSC0 Master-Receive/Slave-Transmit In/Out.
SSC0 Master-Transmit/Slave-Receive Out/In.
ASC0 Clock/Data Output (Async./Sync.),
Fast External Interrupt 2 Input (alternate pin B)
ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
Fast External Interrupt 2 Input (alternate pin A)
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe,
Fast External Interrupt 3 Input (alternate pin B)
SSC0 Master Clock Output / Slave Clock Input.,
Fast External Interrupt 3 Input (alternate pin A)
P3.11
P3.12
49
50
WRH
EX3IN
SCLK0
EX3IN
P3.13
P3.15
51
52
O
O
CLKOUT System Clock Output (=CPU Clock),
FOUT
Programmable Frequency Output
Data Sheet
8
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
Input Function
l
Num. Outp.
P4
IO
Port 4 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 4 is selectable (standard
or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:
P4.0
P4.1
P4.2
P4.3
P4.4
53
54
55
56
57
O
O
O
O
O
O
O
O
O
A16
CS3
A17
CS2
A18
CS1
A19
CS0
A20
Least Significant Segment Address Line,
Chip Select 3 Output
Segment Address Line,
Chip Select 2 Output
Segment Address Line,
Chip Select 1 Output
Segment Address Line,
Chip Select 0 Output
Segment Address Line,
I
O
EX5IN
A21
Fast External Interrupt 5 Input (alternate pin B)
Segment Address Line,
P4.5
P4.6
P4.7
58
59
60
I
O
EX4IN
A22
Fast External Interrupt 4 Input (alternate pin B)
Segment Address Line,
I
O
EX5IN
A23
Fast External Interrupt 5 Input (alternate pin A)
Most Significant Segment Address Line,
I
EX4IN
Fast External Interrupt 4 Input (alternate pin A)
Data Sheet
9
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
Input Function
l
Num. Outp.
P20
IO
Port 20 is a 5-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
P20.0
P20.1
63
64
O
O
RD
External Memory Read Strobe, activated for
every external instruction or data read access.
WR/WRL External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
P20.4
P20.5
65
66
O
I
ALE
EA
External Access Enable pin.
A low level at this pin during and after Reset
forces the XC164N to latch the configuration
from PORT0 and pin RD, and to begin
instruction execution out of external memory.
A high level forces the XC164N to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. "ROMless" versions must
have this pin tied to ‘0’.
P20.12 2
O
RSTOUT Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
Note: Port 20 pins may input configuration values (see EA).
Data Sheet
10
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
Input Function
l
Num. Outp.
PORT0
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
P0L.0 - 67 -
P0L.7
74
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
P0H.0 - 4 -
P0L.3
7
Demultiplexed bus modes:
P0H.4 - 75 -
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7:
8-bit
D0 – D7
I/O
16-bit
D0 - D7
D8 - D15
P0L.7
78
Multiplexed bus modes:
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7:
8-bit
16-bit
AD0 – AD7 AD0 - AD7
A8 - A15 AD8 - AD15
Note: At the end of an external reset (EA = 0) PORT0 also
may input configuration values
PORT1
IO
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes (also after switching from a
demultiplexed to a multiplexed bus mode).
The following PORT1 pins also serve for alt. functions:
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
79
80
81
82
83
84
85
86
I/O
O
I/O
O
I/O
O
O
CC60
COUT60 CAPCOM6: Output of Channel 0
CC61 CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62 CAPCOM6: Input / Output of Channel 2
CAPCOM6: Input / Output of Channel 0
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Channel
I
CTRAP
CAPCOM6: Trap Input
CTRAP is an input pin with an internal pullup resistor. A low
level on this pin switches the CAPCOM6 compare outputs to
the logic level defined by software (if enabled).
I/O
CC22IO
CAPCOM2: CC22 Capture Inp./Compare Outp.
P1H
…
…continued…
Data Sheet
11
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
Input Function
l
Num. Outp.
PORT1
(cont’d)
P1H.0 89
IO
…continued…
CC6POS0 CAPCOM6: Position 0 Input,
I
I
EX0IN
CC23IO
Fast External Interrupt 0 Input (default pin),
CAPCOM2: CC23 Capture Inp./Compare Outp.
I/O
P1H.1 90
P1H.2 91
P1H.3 92
I
I
CC6POS1 CAPCOM6: Position 1 Input,
EX1IN
MRST1
Fast External Interrupt 1 Input (default pin),
SSC1 Master-Receive/Slave-Transmit In/Out.
I/O
I
I
I/O
I
CC6POS2 CAPCOM6: Position 2 Input,
EX2IN
MTSR1
T7IN
Fast External Interrupt 2 Input (default pin),
SSC1 Master-Transmit/Slave-Receive Out/Inp.
CAPCOM2: Timer T7 Count Input,
I/O
I
I
I/O
I
I/O
I
I/O
I
I/O
I
SCLK1
EX3IN
EX0IN
CC24IO
EX4IN
CC25IO
EX5IN
CC26IO
EX6IN
CC27IO
EX7IN
SSC1 Master Clock Output / Slave Clock Input,
Fast External Interrupt 3 Input (default pin),
Fast External Interrupt 0 Input (alternate pin A)
CAPCOM2: CC24 Capture Inp./Compare Outp.,
Fast External Interrupt 4 Input (default pin)
CAPCOM2: CC25 Capture Inp./Compare Outp.,
Fast External Interrupt 5 Input (default pin)
CAPCOM2: CC26 Capture Inp./Compare Outp.,
Fast External Interrupt 6 Input (default pin)
CAPCOM2: CC27 Capture Inp./Compare Outp.,
Fast External Interrupt 7 Input (default pin)
P1H.4 93
P1H.5 94
P1H.6 95
P1H.7 96
XTAL2 99
XTAL1 100
O
I
XTAL2:
XTAL1:
Output of the oscillator amplifier circuit
Input to the oscillator amplifier and input to
the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
res
28
29
-
-
pin is reserved and connected to VDDP
pin is reserved and connected to VSSP
res
VDDI
35, 97 -
Digital Core Supply Voltage (On-Chip Modules):
+2.5 V during normal operation and idle mode.
Please refer to the Operating Conditions
Data Sheet
12
V1.0, 2005-01
XC164N
Derivatives
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbo Pin
Input Function
l
Num. Outp.
VDDP
9, 17,
38, 61,
87
-
Digital Pad Supply Voltage (Pin Output Drivers):
+5 V during normal operation and idle mode.
Please refer to the Operating Conditions
VSSI
34, 98 -
Digital Ground.
Connect decoupling capacitors to adjacent VDD/VSS pin pairs
as close as possible to the pins.
All VSS pins must be connected to the ground-line or ground-
plane.
VSSP
8, 16,
37, 62,
88
-
Data Sheet
13
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3
Functional Description
The architecture of the XC164N combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resoures as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164N.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164N.
PSRAM
DPRAM
DSRAM
EBC
ProgMem
XBUS Control
External Bus
Control
Flash
128 KBytes
CPU
C166SV2-Core
OCDS
Debug Support
Osc / PLL
Clock Generation
RTC WDT
XTAL
Interrupt & PEC
Interrupt Bus
Peripheral Data Bus
GPT ASC0 ASC1 SSC0 SSC1 CC1 CC2
CC6
(USART) (USART)
(SPI)
(SPI)
T2
T3
T4
T0
T7
T12
T1
T8
T13
T5
T6
BRGen
BRGen
Port 5
BRGen
BRGen
P 20 Port 9
Port 4
Port 3
PORT1
16
PORT0
16
8
14
5
6
14
SAF-XC164N-16FxxF AC
Figure 3
Block Diagram
Data Sheet
14
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC164N is configured in a Von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed bytewise or wordwise. Portions of the on-
chip DPRAM and the register spaces (E/SFR) have additionally been made directly
bitaddressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXbus. The system bus allows
concurrent two-way communication for maximum transfer performance.
128 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and one 64-Kbyte
sectors. Each sector can be separately write protected1), erased and programmed (in
blocks of 128 Bytes). The complete Flash area can be read-protected. A password
sequence temporarily unlocks protected areas. The Flash module combines very fast
64-bit one-cycle read accesses with protected and efficient writing algorithms for
programming and erasing. Thus, program execution out of the internal Flash results in
maximum performance. Dynamic error correction provides extremely high read data
security for all read accesses.
Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector
typically takes 200 ms (500 ms max.).
2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.
2 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data.The DSRAM is accessed via the DMU and is therefore optimized for data accesses.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, general purpose register banks. A register bank
can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7)
1) Each two 8-Kbyte sectors are combined for write-protection purposes.
Data Sheet
15
V1.0, 2005-01
XC164N
Derivatives
Functional Description
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC164N Memory Map1)
Start Loc. End Loc. Area Size2)
FF’F000H FF’FFFFH
4 Kbytes Flash only3)
Address Area
Notes
Flash register space
Reserved (Acc. trap)
Reserved for PSRAM
Program SRAM
F8’0000H
E0’0800H
E0’0000H
FF’EFFFH <0.5 Mbytes Minus Flash regs
F7’FFFFH <1.5 Mbytes Minus PSRAM
E0’07FFH
2 Kbytes Maximum
Reserved for pr. mem. C2’0000H DF’FFFFH < 2 Mbytes Minus Flash
Program Flash
C0’0000H C1’FFFFH 128 Kbytes up to 128 Kbytes
Reserved
BF’0000H BF’FFFFH
64 Kbytes
External memory area 40’0000H
BE’FFFFH < 8 Mbytes Minus res. seg.
3F’FFFFH < 2 Mbytes
External IO area4)
20’0800H
20’0000H
Reserved
20’07FFH
2 Kbytes
External memory area 01’0000H
Data RAMs and SFRs 00’8000H
External memory area 00’0000H
1F’FFFFH < 2 Mbytes Minus segment 0
00’FFFFH
00’7FFFH
32 Kbytes Partly used
32 Kbytes
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with “<“ are slightly smaller than indicated, see column “Notes”.
3) Not defined register locations return a trap code.
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
16
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.2
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes1), which
are as follows:
– 16 … 24-bit Addresses, 16-bit Data, Demultiplexed
– 16 … 24-bit Addresses, 16-bit Data, Multiplexed
– 16 … 24-bit Addresses, 8-bit Data, Multiplexed
– 16 … 24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output. The high order address (segment) lines
use Port 4. The number of active segment address lines is selectable, restricting the
external address space to 8 Mbytes … 64 Kbytes. This is required when interface lines
are assigned to Port 4.
Up to 4 external CS signals (3 windows plus default) can be generated in order to save
external glue logic. External modules can directly be connected to the common
address/data bus and their individual select lines.
Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control the access to different resources with different bus
characteristics. These address windows are arranged hierarchically where window 4
overrides window 3, and window 2 overrides window 1. All accesses to locations not
covered by these 4 address windows are controlled by TCONCS0/FCONCS0. The
currently active window can generate a chip select signal.
The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
1) Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet
17
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
System-Bus
PMU
Internal Program Memory
CPU
DPRAM
2-Stage
Prefetch
Pipeline
CSP
IP
VECSEG
TFR
Prefetch Unit
CPUCON1
CPUCON2
CPUID
Branch Unit
FIFO
5-Stage
Pipeline
Injection/Exception
Handler
Return Stack
IFU
DPP0
IPIP
IDX0
IDX1
QX0
QX1
QR0
QR1
SPSEG
SP
STKOV
STKUN
CP
R15
DPP1
DPP2
DPP3
address
R14
R15
R14
GPRs
+/-
+/-
ADU
GPRs
Division Unit Bit-Mask-Gen.
Multiply Unit Barrel-Shifter
MRW
R1
R0
R0
Multiply Unit
R1
MCW
MSW
MDC
+/-
+/-
PSW
RF
MAH
MAL
MDH
Zeros
MDL
Ones
data in
Buffer
data out
MAC
ALU
WB
SRAM
DMU
Peripheral-Bus
System-Bus
Figure 4
CPU Block Diagram
Based on these hardware provisions, most of the XC164N’s instructions can be
executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. Also multiplication and most MAC
instructions execute in one single cycle. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: for example, a 32-/16-bit
division is started within 4 cycles, while the remaining 15 cycles are executed in the
Data Sheet
18
V1.0, 2005-01
XC164N
Derivatives
Functional Description
background. Another pipeline optimization, the branch target prediction, allows
eliminating the execution time of branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 wordwide
GPRs each at its disposal. One of these register banks is physically allocated within the
on-chip DPRAM area. A Context Pointer (CP) register determines the base address of
the active register bank to be accessed by the CPU at any time. The number of register
banks is only restricted by the available internal RAM space. For easy parameter
passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC164N instruction set which
includes the following instruction classes:
– Standard Arithmetic Instructions
– DSP-Oriented Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
19
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.4
Interrupt System
With an interrupt response time of typically 8 CPU clocks (in case of internal program
execution), the XC164N is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the XC164N supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source, or the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The XC164N has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt nodes. Via its
related register, each node can be programmed to one of sixteen interrupt priority levels.
Once having been accepted by the CPU, an interrupt service can only be interrupted by
a higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 4 shows all of the possible XC164N interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may
be used to generate software controlled interrupt requests by setting the
respective interrupt request bit (xIR).
Data Sheet
20
V1.0, 2005-01
XC164N
Derivatives
Functional Description
Table 4
XC164N Interrupt Nodes
Source of Interrupt or PEC
Service Request
Control
Register
Vector Trap
Location1)
xx’0040H
xx’0044H
xx’0048H
xx’004CH
xx’0050H
xx’0054H
xx’0058H
xx’005CH
xx’0060H
xx’0064H
xx’0068H
xx’006CH
xx’0070H
xx’0074H
xx’0078H
xx’007CH
xx’00C0H
xx’00C4H
xx’00C8H
xx’00CCH
xx’00D0H
xx’00D4H
xx’00D8H
xx’00DCH
xx’00E0H
xx’00E4H
xx’00E8H
xx’00ECH
xx’00E0H
xx’0110H
Number
10H / 16D
11H / 17D
12H / 18D
13H / 19D
14H / 20D
15H / 21D
16H / 22D
17H / 23D
18H / 24D
19H / 25D
1AH / 26D
1BH / 27D
1CH / 28D
1DH / 29D
1EH / 30D
1FH / 31D
30H / 48D
31H / 49D
32H / 50D
33H / 51D
34H / 52D
35H / 53D
36H / 54D
37H / 55D
38H / 56D
39H / 57D
3AH / 58D
3BH / 59D
3CH / 60D
44H / 68D
CAPCOM Register 0
CAPCOM Register 1
CAPCOM Register 2
CAPCOM Register 3
CAPCOM Register 4
CAPCOM Register 5
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CAPCOM Register 10
CAPCOM Register 11
CAPCOM Register 12
CAPCOM Register 13
CAPCOM Register 14
CAPCOM Register 15
CAPCOM Register 16
CAPCOM Register 17
CAPCOM Register 18
CAPCOM Register 19
CAPCOM Register 20
CAPCOM Register 21
CAPCOM Register 22
CAPCOM Register 23
CAPCOM Register 24
CAPCOM Register 25
CAPCOM Register 26
CAPCOM Register 27
CAPCOM Register 28
CAPCOM Register 29
CC1_CC0IC
CC1_CC1IC
CC1_CC2IC
CC1_CC3IC
CC1_CC4IC
CC1_CC5IC
CC1_CC6IC
CC1_CC7IC
CC1_CC8IC
CC1_CC9IC
CC1_CC10IC
CC1_CC11IC
CC1_CC12IC
CC1_CC13IC
CC1_CC14IC
CC1_CC15IC
CC2_CC16IC
CC2_CC17IC
CC2_CC18IC
CC2_CC19IC
CC2_CC20IC
CC2_CC21IC
CC2_CC22IC
CC2_CC23IC
CC2_CC24IC
CC2_CC25IC
CC2_CC26IC
CC2_CC27IC
CC2_CC28IC
CC2_CC29IC
Data Sheet
21
V1.0, 2005-01
XC164N
Derivatives
Functional Description
Table 4
XC164N Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector Trap
Location1)
xx’0114H
xx’0118H
xx’0080H
xx’0084H
xx’00F4H
xx’00F8H
Number
45H / 69D
46H / 70D
20H / 32D
21H / 33D
3DH / 61D
3EH / 62D
22H / 34D
23H / 35D
24H / 36D
25H / 37D
26H / 38D
27H / 39D
28H / 40D
29H / 41D
2AH / 42D
47H / 71D
2BH / 43D
2CH / 44D
5FH / 95D
2DH / 45D
2EH / 46D
2FH / 47D
43H / 67D
48H / 72D
5EH / 94D
49H / 73D
4AH / 74D
42H / 66D
4CH / 76D
4DH / 77D
CAPCOM Register 30
CAPCOM Register 31
CAPCOM Timer 0
CAPCOM Timer 1
CAPCOM Timer 7
CAPCOM Timer 8
GPT1 Timer 2
CC2_CC30IC
CC2_CC31IC
CC1_T0IC
CC1_T1IC
CC2_T7IC
CC2_T8IC
GPT12E_T2IC xx’0088H
GPT12E_T3IC xx’008CH
GPT12E_T4IC xx’0090H
GPT12E_T5IC xx’0094H
GPT12E_T6IC xx’0098H
GPT12E_CRIC xx’009CH
GPT1 Timer 3
GPT1 Timer 4
GPT2 Timer 5
GPT2 Timer 6
GPT2 CAPREL Reg.
Unassigned node
Unassigned node
ASC0 Transmit
ASC0 Transmit Buffer
ASC0 Receive
---
xx’00A0H
xx’00A4H
xx’00A8H
xx’011CH
xx’00ACH
xx’00B0H
xx’017CH
xx’00B4H
xx’00B8H
xx’00BCH
xx’010CH
xx’0120H
xx’0178H
xx’0124H
xx’0128H
xx’0108H
xx’0130H
xx’0134H
---
ASC0_TIC
ASC0_TBIC
ASC0_RIC
ASC0_EIC
ASC0_ABIC
SSC0_TIC
SSC0_RIC
SSC0_EIC
PLLIC
ASC0 Error
ASC0 Autobaud
SSC0 Transmit
SSC0 Receive
SSC0 Error
PLL/OWD
ASC1 Transmit2)
ASC1 Transmit Buffer
ASC1 Receive
ASC1_TIC
ASC1_TBIC
ASC1_RIC
ASC1_EIC
ASC1_ABIC
EOPIC
ASC1 Error
ASC1 Autobaud
End of PEC Subch.
CAPCOM6 Timer T12
CCU6_T12IC
Data Sheet
22
V1.0, 2005-01
XC164N
Derivatives
Functional Description
Table 4
XC164N Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector Trap
Location1)
xx’0138H
xx’013CH
xx’0140H
xx’0144H
xx’0148H
xx’014CH
xx’0150H
xx’0154H
xx’0158H
xx’015CH
xx’0164H
xx’0168H
xx’016CH
xx’0170H
xx’0174H
xx’0100H
xx’0104H
xx’012CH
xx’00FCH
xx’0160H
Number
4EH / 78D
4FH / 79D
50H / 80D
51H / 81D
52H / 82D
53H / 83D
54H / 84D
55H / 85D
56H / 86D
57H / 87D
59H / 89D
5AH / 90D
5BH / 91D
5CH / 92D
5DH / 93D
40H / 64D
41H / 65D
4BH / 75D
3FH / 63D
58H / 88D
CAPCOM6 Timer T13
CAPCOM6 Emergency
CAPCOM6
CCU6_T13IC
CCU6_EIC
CCU6_IC
SSC1 Transmit
SSC1_TIC
SSC1 Receive
SSC1_RIC
SSC1 Error
SSC1_EIC
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
Unassigned node
---
---
---
---
---
---
---
---
---
---
---
---
---
---
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
2) The interrupt nodes assigned to ASC1 are only available in derivatives including the ASC1. Otherwise, they
are unassigned nodes.
Data Sheet
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V1.0, 2005-01
XC164N
Derivatives
Functional Description
The XC164N also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
Location1) Number Priority
Reset Functions:
–
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
RESET
RESET
RESET
xx’0000H
xx’0000H
xx’0000H
00H
00H
00H
III
III
III
Class A Hardware Traps:
– Non-Maskable Interrupt NMI
NMITRAP
STOTRAP
STUTRAP
xx’0008H
xx’0010H
xx’0018H
02H
04H
06H
08H
II
II
II
II
– Stack Overflow
– Stack Underflow
– Software Break
STKOF
STKUF
SOFTBRK SBRKTRAP xx’0020H
Class B Hardware Traps:
– Undefined Opcode
– PMI Access Error
– Protected Instruction
Fault
UNDOPC BTRAP
xx’0028H
xx’0028H
xx’0028H
0AH
0AH
0AH
I
I
I
PACER
PRTFLT
BTRAP
BTRAP
– Illegal Word Operand
Access
ILLOPA
BTRAP
xx’0028H
0AH
I
Reserved
–
–
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
– TRAP Instruction
Any
Any
Current
CPU
Priority
[xx’0000H – [00H –
xx’01FCH] 7FH]
in steps
of 4H
1) Register VECSEG defines the segment where the vector table is located to.
Data Sheet
24
V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.5
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC164N. The user software running on the XC164N can thus be
debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the JTAG interface or via the external bus interface for
increased performance.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to
communicate with external circuitry. These interface signals are realized as alternate
functions on Port 3 pins.
Complete system emulation is supported by the New Emulation Technology (NET)
interface. Via this full-featured emulation interface (including internal buses, control,
status, and pad signals) the XC164N chip can be connected to a NET carrier chip.
The use of the XC164N production chip together with the carrier chip provides superior
emulation behavior, because the emulation system shows exactly the same functionality
as the production chip (use of the identical silicon).
Data Sheet
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V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.6
Capture/Compare Units (CAPCOM1/2)
The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM units are typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for each capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose
capture/compare registers, each of which may be individually allocated to either
CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or
compare function.
12 registers of the CAPCOM2 module have each one port pin associated with it which
serves as an input pin for triggering the capture function, or as an output pin to indicate
the occurrence of a compare event.
Table 6
Compare Modes (CAPCOM1/2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Mode 2
Mode 3
Pin toggles on each compare match;
several compare events per timer period are possible
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
can be used with any compare mode
Data Sheet
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V1.0, 2005-01
XC164N
Derivatives
Functional Description
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Data Sheet
27
V1.0, 2005-01
XC164N
Derivatives
Functional Description
Reload Reg.
T0REL/T7REL
fCC
T0IN/T7IN
T6OUF
T0/T7
Input
Control
T0IRQ,
T7IRQ
Timer T0/T7
CCxIO
CCxIO
CCxIRQ
CCxIRQ
Mode
Control
(Capture
or
Sixteen
16-bit
Capture/
Compare
Registers
Compare)
CCxIO
CCxIRQ
T1/T8
Input
Control
fCC
T1IRQ,
T8IRQ
Timer T1/T8
T6OUF
Reload Reg.
T1REL/T8REL
CAPCOM1 provides channels x = 0 … 15,
CAPCOM2 provides channels x = 16 … 31.
(see signals CCxIO and CCxIRQ)
MCB05569
Figure 5
CAPCOM1/2 Unit Block Diagram
Data Sheet
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V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.7
The Capture/Compare Unit CAPCOM6
The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one independent 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions (deadtime control). The
compare channel can generate a single PWM output signal and is further used to
modulate the capture/compare output signals.
In capture mode the contents of compare timer T12 is stored in the capture registers
upon a signal transition at pins CCx.
Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled system clock.
Mode
Select Register
CC6MSEL
Period Register
Trap Register
CTRAP
T12P
CC60
COUT60
Offset Register
T12OF
CC Channel 0
CC60
fCPU
CC61
COUT61
CC Channel 1
CC61
Port
Control
Logic
Compare
Timer T12
16-Bit
CC62
COUT62
COUT63
CC Channel 2
CC62
Cntrol Register
CTCON
Compare
Timer T13
10-Bit
fCPU
Compare Register
CMP13
Block
Commutation
Control
CC6POS0
CC6POS1
CC6POS2
Period Register
T13P
CC6MCON.H
MCB04109
The timer registers (T12, T13) are not directly accessible.
The period and offset registers are loading a value into the timer registers.
Figure 6
CAPCOM6 Block Diagram
For motor control applications both subunits may generate versatile multichannel PWM
signals which are basically either controlled by compare timer T12 or by a typical hall
sensor pattern at the interrupt inputs (block commutation).
Data Sheet
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V1.0, 2005-01
XC164N
Derivatives
Functional Description
3.8
General Purpose Timer (GPT12E) Unit
The GPT12E unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
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XC164N
Derivatives
Functional Description
n
fSYS
2
: 1
Interrupt
Request
(T2IR)
G PT1 Tim er T2
U/D
T2IN
T2
M ode
Control
T2EUD
Reload
Capture
Interrupt
Request
(T3IR)
n
fSYS
T3IN
2
: 1
Toggle FF
T3O TL
T3
M ode
G PT1 Tim er T3
T6O UT
Control
U/D
T3EUD
Capture
Reload
n
fSYS
T4IN
2
: 1
T4
M ode
Control
Interrupt
Request
(T4IR)
G PT1 Tim er T4
U/D
T4EUD
M ct04825_xc.vsd
n = 2 … 12
Figure 7
Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
Data Sheet
31
V1.0, 2005-01
XC164N
Derivatives
Functional Description
after the capture procedure. This allows the XC164N to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
Interrupt
Request
(T5IR)
n
fSYS
T5IN
2
: 1
G PT2 Tim er T5
T5
M ode
Control
U/D
Clear
T5EUD
Capture
G PT2 CAPREL
T3IN/
T3EUD
Interrupt
Request
(CRIR)
M UX
CT3
CAPIN
Interrupt
Request
(T6IR)
Clear
G PT2 Tim er T6
Toggle FF
n
fSYS
T6IN
T6O TL
T6O UT
2
: 1
T6
M ode
Control
U/D
O ther
M odules
T6EUD
M cb03999_xc.vsd
n = 1 … 11
Figure 8
Block Diagram of GPT2
Data Sheet
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XC164N
Derivatives
Functional Description
3.9
Real Time Clock
The Real Time Clock (RTC) module of the XC164N is directly clocked via a separate
clock driver with the prescaled on-chip oscillator frequency (fRTC = fOSC / 32). It is
therefore independent from the selected clock generation mode of the XC164N.
The RTC basically consists of a chain of divider blocks:
• a selectable 8:1 divider (on - off)
• the reloadable 16-bit timer T14
• the 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
PRE
RUN
fRTC
1
8
RTCINT
M UX
0
Interrupt Sub Node
CNT
INT0
CNT
INT1
CNT
INT2
CNT
INT3
REL-Register
6 Bits 6 Bits
T14REL
10 Bits
10 Bits
T14
10 Bits
6 Bits
6 Bits
10 Bits
T14-Register
CNT-Register
m cb04805_xc.vsd
Figure 9
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
Data Sheet
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XC164N
Derivatives
Functional Description
The RTC module can be used for different purposes:
• System clock to determine the current time and date,
optionally during idle mode, sleep mode, and power down mode
• Cyclic time based interrupt, to provide a system time tick independent of CPU
frequency and other resources, e.g. to wake up regularly from idle mode.
• 48-bit timer for long term measurements (maximum timespan is >100 years).
• Alarm interrupt for wake-up on a defined time
Data Sheet
34
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XC164N
Derivatives
Functional Description
3.10
Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)
The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial
communication with other microcontrollers, processors, terminals or external peripheral
components. They are upward compatible with the serial ports of the Infineon 8-bit
microcontroller families and support full-duplex asynchronous communication and half-
duplex synchronous communication. A dedicated baud rate generator with a fractional
divider precisely generates all standard baud rates without oscillator tuning. For
transmission, reception, error handling, and baudrate detection 5 separate interrupt
vectors are provided.
In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted
or received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to
115.2 kbit/s with fixed or programmable IrDA pulse width are supported.
In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift
clock which is generated by the ASC0/1. The LSB is always shifted first.
In both modes, transmission and reception of data is FIFO-buffered. An autobaud
detection unit allows to detect asynchronous data frames with its baudrate and mode
with automatic initialization of the baudrate generator and the mode control bits.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
Summary of Features
• Full-duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking
– Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)
– Multiprocessor mode for automatic address/data byte detection
– Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)
– Loop-back capability
– Auto baudrate detection
• Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)
• Buffered transmitter/receiver with FIFO support (8 entries per direction)
• Loop-back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, last bit transmitted
condition, receive buffer full condition, error condition (frame, parity, overrun error),
start and end of an autobaud detection
Data Sheet
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Derivatives
Functional Description
3.11
High Speed Synchronous Serial Channels (SSC0/SSC1)
The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-
duplex synchronous communication. It may be configured so it interfaces with serially
linked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling three separate interrupt
vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit error and receive error supervise the correct
handling of the data buffer. Phase error and baudrate error detect incorrect serial data.
Summary of Features
• Master or Slave mode operation
• Full-duplex or Half-duplex transfers
• Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB-first or MSB-first
– Programmable clock polarity: idle low or idle high
– Programmable clock/data phase: data shift with leading or trailing clock edge
• Loop back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, receive buffer full
condition, error condition (receive, phase, baudrate, transmit error)
• Three pin interface with flexible SSC pin configuration
3.12
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
until the EINIT instruction has been executed (compatible mode), or it can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT (enhanced
mode). Thus, the chip’s start-up procedure is always monitored. The software has to be
designed to restart the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
Data Sheet
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V1.0, 2005-01
XC164N
Derivatives
Functional Description
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by
2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13 µs and 419 ms can be monitored (@ 40 MHz).
The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
3.13
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC164N with high flexibility. The master clock fMC is
the reference clock signal and is output to the external system. The CPU clock fCPU and
the system clock fSYS are derived from the master clock either directly (1:1) or via a 2:1
prescaler (fSYS = fCPU = fMC / 2). See also Section 5.1.
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock / OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Note: At the end of an external reset (EA = ‘0’) the oscillator watchdog may be disabled
via hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration.
3.14
Parallel Ports
The XC164N provides up to 79 I/O lines which are organized into six input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs (except for pin RSTOUT).
Data Sheet
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Derivatives
Functional Description
The edge characteristics (shape) and driver characteristics (output current) of the port
drivers can be selected via registers POCONx.
The input threshold of some ports is selectable (TTL or CMOS like), where the special
CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The
input threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
Data Sheet
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Derivatives
Functional Description
Table 7
Port
Summary of the XC164N’s Parallel Ports
Control
Alternate Functions
Address/Data lines or data lines1)
Address lines2)
PORT0
PORT1
Pad drivers
Pad drivers
Capture inputs or compare outputs,
Serial interface lines,
Fast external interrupt inputs
Port 3
Port 4
Pad drivers,
Open drain,
Timer control signals, serial interface lines,
Optional bus control signal BHE/WRH,
Input threshold System clock output CLKOUT (or FOUT),
Debug interface lines
Pad drivers,
Open drain,
Input threshold
Segment address lines3)
Optional chip select signals
Port 5
Port 9
---
Timer control signals
Pad drivers,
Open drain,
Input threshold
Capture inputs or compare outputs
Port 20
Pad drivers,
Open drain
Bus control signals RD, WR/WRL, ALE,
External access enable pin EA,
Reset indication output RSTOUT
1) For multiplexed bus cycles.
2) For demultiplexed bus cycles.
3) For more than 64 Kbytes of external resources.
Data Sheet
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Derivatives
Functional Description
3.15
Power Management
The XC164N provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
• Power Saving Modes switch the XC164N into a special operating mode (control via
instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals. While the clock signals for currently inactive parts
of logic are disabled automatically, the user can reduce the XC164N’s CPU clock
frequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output FOUT.
• Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3). Each peripheral can separately be disabled/enabled.
The on-chip RTC supports intermittend operation of the XC164N by generating cyclic
wake-up signals. This offers full performance to quickly react on action requests while
the intermittend sleep phases greatly reduce the average power consumption of the
system.
Data Sheet
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XC164N
Derivatives
Functional Description
3.16
Instruction Set Summary
Table 8 lists the instructions of the XC164N in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Table 8
Instruction Set Summary
Description
Mnemonic
ADD(B)
Bytes
2 / 4
2 / 4
2 / 4
2 / 4
Add word (byte) operands
ADDC(B)
SUB(B)
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
SUBC(B)
MUL(U)
(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
DIV(U)
DIVL(U)
CPL(B)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
2
NEG(B)
2
AND(B)
Bitwise AND, (word/byte operands)
Bitwise (exclusive)OR, (word/byte operands)
Clear/Set direct bit
2 / 4
2 / 4
2
(X)OR(B)
BCLR / BSET
BMOV(N)
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
4
BAND / BOR /
BXOR
4
BCMP
Compare direct bit to direct bit
4
4
BFLDH / BFLDL
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
Compare word (byte) operands
2 / 4
Compare word data to GPR and decrement GPR by 1/2 2 / 4
Compare word data to GPR and increment GPR by 1/2
2 / 4
2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
SHL / SHR
ROL / ROR
ASHR
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
Move word (byte) data
2
2
2
MOV(B)
2 / 4
MOVBS/Z
Move byte operand to word op. with sign/zero extension 2 / 4
Data Sheet
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XC164N
Derivatives
Functional Description
Table 8
Mnemonic
JMPA/I/R
JMPS
Instruction Set Summary (cont’d)
Description
Bytes
Jump absolute/indirect/relative if condition is met
Jump absolute to a code segment
4
4
4
4
JB(C)
Jump relative if direct bit is set (and clear bit)
Jump relative if direct bit is not set (and set bit)
JNB(S)
CALLA/I/R
CALLS
Call absolute/indirect/relative subroutine if condition is met 4
Call absolute subroutine in any code segment
4
4
PCALL
Push direct word register onto system stack and call
absolute subroutine
TRAP
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
2
2
4
PUSH / POP
SCXT
Push direct word register onto system stack and update
register with word operand
RET(P)
Return from intra-segment subroutine
2
(and pop direct word register from system stack)
RETS
Return from inter-segment subroutine
Return from interrupt service subroutine
Software Break
2
RETI
2
SBRK
SRST
2
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
SRVWDT
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
4
4
DISWDT/ENWDT Disable/Enable Watchdog Timer
4
EINIT
Signify End-of-Initialization on RSTOUT-pin
4
ATOMIC
EXTR
Begin ATOMIC sequence
2
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
2
EXTP(R)
EXTS(R)
NOP
2 / 4
2 / 4
2
CoMUL / CoMAC Multiply (and accumulate)
4
CoADD / CoSUB Add / Subtract
4
Co(A)SHR/CoSHL (Arithmetic) Shift right / Shift left
CoLOAD/STORE Load accumulator / Store MAC register
CoCMP/MAX/MIN Compare (maximum/minimum)
CoABS / CoRND Absolute value / Round accumulator
CoMOV/NEG/NOP Data move / Negate accumulator / Null operation
4
4
4
4
4
Data Sheet
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XC164N
Derivatives
Electrical Parameters
4
Electrical Parameters
4.1
Absolute Maximum Ratings
Table 9
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
min. max.
Unit
Notes
Storage temperature
Junction temperature
TST
TJ
-65
-40
-0.5
150
150
3.25
°C
°C
V
–
under bias
–
Voltage on VDDI pins with VDDI
respect to ground (VSS)
Voltage on VDDP pins with VDDP
respect to ground (VSS)
-0.5
-0.5
-10
–
6.2
V
–
–
–
–
Voltage on any pin with
VIN
VDDP
+ 0.5
V
respect to ground (VSS)
Input current on any pin
during overload condition
–
10
mA
mA
Absolute sum of all input
currents during overload
condition
–
|100|
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
4.2
Package Properties
Table 10
Package Parameters (P-TQFP-100-16)
Parameter
Symbol
Limit Values
min. max.
Unit
Notes
Power dissipation
PDISS
RTHA
–
–
0.8
29
W
–
Thermal Resistance
K/W
Chip-Ambient
Data Sheet
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XC164N
Derivatives
Electrical Parameters
4.3
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC164N. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Table 11
Operating Condition Parameters
Symbol Limit Values
min. max.
2.35 2.7
Parameter
Unit Notes
Digital supply voltage for VDDI
V
V
Active mode,
fCPU = fCPUmax
1)
the core
Digital supply voltage for VDDP
IO pads
4.4
5.5
–
Active mode
2) 3)
4)
Supply Voltage Difference ∆VDD
-0.5
V
V
VDDP - VDDI
Digital ground voltage
Overload current
VSS
IOV
0
Reference voltage
-5
-2
5
5
mA Per IO pin5)6)
mA Per analog input
pin5)6)
Overload current coupling KOVA
–
–
–
–
–
1.0 × 10-4
1.5 × 10-3
5.0 × 10-3
1.0 × 10-2
50
–
IOV > 0
IOV < 0
IOV > 0
factor for analog inputs7)
–
Overload current coupling KOVD
–
factor for digital I/O pins7)
–
IOV < 0
6)
Absolute sum of overload Σ|IOV|
mA
currents
External Load
Capacitance
CL
TA
–
50
pF
Pin drivers in
default mode8)
Ambient temperature
0
70
°C
°C
°C
SAB-XC164N …
SAF-XC164N …
SAK-XC164N …
-40
-40
85
125
1) fCPUmax = 40 MHz for devices marked …40F, fCPUmax = 20 MHz for devices marked …20F.
2) External circuitry must guarantee low level at the RSTIN pin at least until both power supply voltages have
reached the operating level.
3) The specified voltage range is allowed for operation. The range limits may be reached under extreme
operating conditions. However, specified parameters, such as leakage currents, refer to the standard
operating voltage range of VDDP = 4.75 V to 5.25 V.
4) This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down,
and power-save modes.
Data Sheet
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Derivatives
Electrical Parameters
5) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VDDP + 0.5 V (IOV > 0) or VOV < VSS - 0.5 V (IOV < 0). The absolute sum of
input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the
specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
6) Not subject to production test - verified by design/characterization.
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input
voltage on analog inputs.
8) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
4.4
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the XC164N
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the XC164N will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
XC164N.
Data Sheet
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XC164N
Derivatives
Electrical Parameters
4.5
DC Parameters
DC Characteristics
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Input low voltage TTL
(all except XTAL1)
VIL SR -0.5
0.2×VDDP
- 0.1
V
–
Input low voltage XTAL1
VILC SR -0.5
VILS SR -0.5
0.3 ×VDDI
V
V
–
2)
Input low voltage
0.45
(Special Threshold)
× VDDP
Input high voltage TTL
(all except XTAL1)
VIH SR 0.2×VDDP VDDP
V
V
V
V
–
+ 0.9
VIHC SR 0.7
× VDDI
+ 0.5
Input high voltage XTAL1
VDDI
+ 0.5
–
2)
Input high voltage
(Special Threshold)
VIHS SR 0.8×VDDP VDDP
- 0.2
+ 0.5
Input Hysteresis
HYS
0.04
–
V
DDP in [V],
(Special Threshold)
× VDDP
Series resis-
tance = 0 Ω2)
3)
Output low voltage
VOL CC –
1.0
0.45
–
V
V
V
IOL ≤ IOLmax
3) 4)
–
IOL ≤ IOLnom
Output high voltage5)
VOH CC VDDP
I
OH ≥ IOHmax
3)
- 1.0
3) 4)
VDDP
–
V
I
OH ≥ IOHnom
- 0.45
Input leakage current
(Port 5)6)
IOZ1 CC –
±300
±200
±500
nA 0 V < VIN < VDDP,
TA ≤ 125 °C
nA 0 V < VIN < VDDP,
TA ≤ 85 °C12)
Input leakage current
(all other)6)
IOZ2 CC –
nA 0.45 V < VIN <
VDDP
Configuration pull-up current7) ICPUH
–
-10
–
µA VIN = VIHmin
µA VIN = VILmax
8)
9)
ICPUL
-100
Data Sheet
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Derivatives
Electrical Parameters
DC Characteristics (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
10
8)
Configuration pull-down
current10)
ICPDL
–
µA VIN = VILmax
µA VIN = VIHmin
9)
ICPDH
120
–
–
8)
Level inactive hold current11) ILHI
-10
µA VOUT
0.5 × VDDP
OUT = 0.45 V
=
Level active hold current11)
XTAL1 input current
Pin capacitance12)
ILHA
-100
–
µA
V
9)
IIL
CC –
±20
10
µA 0 V < VIN < VDDI
CIO CC –
pF
(digital inputs/outputs)
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV
.
2) This parameter is tested for P2, P3, P4, P9.
3) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 12, Current Limits for Port Output Drivers. The limit for pin groups must be respected.
4) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDDP). However, only the levels for nominal output currents are guaranteed.
5) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
6) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV
.
7) This specification is valid during Reset for configuration on RD, WR, EA, PORT0.
8) The maximum current may be drawn while the respective signal line remains inactive.
9) The minimum current must be drawn to drive the respective signal line active.
10) This specification is valid during Reset for configuration on ALE.
11) This specification is valid during Reset for pins P4.3-0, which can act as CS outputs.
12) Not subject to production test - verified by design/characterization.
Data Sheet
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XC164N
Derivatives
Electrical Parameters
Table 12
Current Limits for Port Output Drivers
Port Output Driver
Mode
Maximum Output Current
Nominal Output Current
1)
(IOLmax, -IOHmax
)
(IOLnom, -IOHnom
)
Strong driver
Medium driver
Weak driver
10 mA
2.5 mA
4.0 mA
1.0 mA
0.5 mA
0.1 mA
1) An output current above |IOXnom| may be drawn from up to three pins at the same time.
For any group of 16 neighboring port output pins the total output current in each direction (ΣIOL and Σ-IOH) must
remain below 50 mA.
Power Consumption XC164N
(Operating Conditions apply)
Parameter
Symbol
Limit Values
min. max.
Unit Test Condition
1)
Power supply current (active)
with all peripherals active
IDDI
–
15 +
2.6 × fCPU
mA
f
CPU in [MHz]2)
3)
Pad supply current
IDDP
IIDX
–
–
5
mA
mA
Idle mode supply current
with all peripherals active
15 +
1.2 × fCPU
f
CPU in [MHz]2)
5)
6)
Sleep and Power-down mode
supply current caused by
leakage4)
IPDL
–
128,000
mA VDDI=VDDImax
TJ in [°C]
× e-α
α =
4670/(273+TJ)
7)
Sleep and Power-down mode
supply current caused by
IPDM
–
0.6 +
mA VDDI=VDDImax
0.02×fOSC
+ IPDL
fOSC in [MHz]
leakage and the RTC running,
clocked by the main oscillator4)
1) During Flash programming or erase operations the supply current is increased by max. 5 mA.
2) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10.
These parameters are tested at VDDImax and maximum CPU clock frequency with all outputs disconnected and
all inputs at VIL or VIH.
3) The pad supply voltage pins (VDDP) mainly provides the current consumed by the pin output drivers. A small
amount of current is consumed even though no outputs are driven, because the drivers’ input stages are
switched and also the Flash module draws some power from the VDDP supply.
4) The total supply current in Sleep and Power-down mode is the sum of the temperature dependent leakage
current and the frequency dependent current for RTC and main oscillator (if active).
Data Sheet
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Derivatives
Electrical Parameters
5) This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the
junction temperature (see Figure 12). The junction temperature TJ is the same as the ambient temperature TA
if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be
taken into account.
6) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP, all outputs (including
pins configured as outputs) disconnected. This parameter is tested at 25 °C and is valid for TJ ≥ 25 °C.
7) This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see
Figure 11). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The
given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
Data Sheet
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Derivatives
Electrical Parameters
I [mA]
IDDImax
140
120
100
IDDItyp
80
60
40
20
IIDXmax
IIDXtyp
10
20
30
40
f
CPU [MHz]
Figure 10
Supply/Idle Current as a Function of Operating Frequency
Data Sheet
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XC164N
Derivatives
Electrical Parameters
I [mA]
3.0
2.0
IPDMmax
IPDMtyp
1.0
0.1
IPDAmax
32 kHz
4
8
12
16
f
OSC [MHz]
Figure 11
Sleep and Power Down Supply Current due to RTC and Oscillator
running, as a Function of Oscillator Frequency
IPDO
[mA]
1.5
1.0
0.5
-50
0
50
100
150
TJ [°C]
Figure 12
Sleep and Power Down Leakage Supply Current as a Function of
Temperature
Data Sheet
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Derivatives
Timing Parameters
5
Timing Parameters
5.1
Definition of Internal Timing
The internal operation of the XC164N is controlled by the internal master clock fMC.
The master clock signal fMC can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate fMC.
This influence must be regarded when calculating the timings for the XC164N.
Phase Locked Loop Operation (1:N)
fOSC
fMC
TCM
Direct Clock Drive (1:1)
fOSC
fMC
TCM
Prescaler Operation (N:1)
fOSC
fMC
TCM
Figure 13
Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 13 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal fCPU. The CPU clock can have the
same frequency as the master clock (fCPU = fMC) or can be the master clock divided by
two: fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal fSYS which has the same
frequency as the CPU clock signal fCPU
.
Data Sheet
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Derivatives
Timing Parameters
Bypass Operation
When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f
MC = fOSC / ((PLLIDIV+1)×(PLLODIV+1)).
If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of fMC
directly follows the frequency of fOSC so the high and low time of fMC is defined by the duty
cycle of the input clock fOSC
.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f
MC = fOSC / ((3+1)×(14+1)) = fOSC / 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor, and
the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it
is locked to fOSC. The slight variation causes a jitter of fMC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 14).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal fMC. Therefore,
the number of VCO cycles can be represented as K × N, where N is the number of
consecutive fMC cycles (TCM).
Data Sheet
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Derivatives
Timing Parameters
For a period of N × TCM the accumulated PLL jitter is defined by the deviation DN:
DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods the K×N=95 value can be
used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).
Acc. jitter D N
K=15 K=12 K=10 K=8
K=6
K=5
ns
±8
±7
±6
±5
z
±4
±3
±2
H
M
0
1
±1
0
15
25
1
5
10
20
N
m cb04413_xc.vsd
Figure 14
Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Table 13
PLLCON.PLLVB VCO Frequency Range
VCO Bands for PLL Operation1)
Base Frequency Range
20 … 80 MHz
00
01
10
11
100 … 150 MHz
150 … 200 MHz
200 … 250 MHz
Reserved
40 … 130 MHz
60 … 180 MHz
1) Not subject to production test - verified by design/characterization.
Data Sheet
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Derivatives
Timing Parameters
5.2
External Clock Drive XTAL1
Table 14
External Clock Drive Characteristics
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit
min.
tOSC SR 20
max.
2501)
Oscillator period
High time2)
Low time2)
Rise time2)
Fall time2)
ns
ns
ns
ns
ns
t1
t2
t3
t4
SR 6
–
–
8
8
SR 6
SR –
SR –
1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.
2) The clock input signal must reach the defined levels VILC and VIHC
.
t 1
t 3
t 4
VIHC
VILC
0.5 VDDI
t 2
t OSC
MCT05138
Figure 15
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the
oscillator frequency is limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not subject to production test).
Data Sheet
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Derivatives
Timing Parameters
5.3
Testing Waveforms
Input signal
(driven by tester)
Output signal
(measured)
2.0 V
0.8 V
0.45 V
Figure 16
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH
/
VOL level occurs (IOH
/
I
OL = 20 mA).
MCA00763
Figure 17
Float Waveforms
Data Sheet
56
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
5.4
AC Characteristics
Table 15
CLKOUT Reference Signal
Parameter
Symbol
Limits
max.
Unit
min.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
tc5 CC
50/251)
ns
ns
ns
ns
ns
tc6 CC 8
tc7 CC 6
tc8 CC –
tc9 CC –
–
–
4
4
1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 20/40 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
tc9
tc7
tc8
tc5
tc6
CLKOUT
MCT04415
Figure 18
CLKOUT Signal Timing
Data Sheet
57
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
Variable Memory Cycles
External bus cycles of the XC164N are executed in five subsequent cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
This table provides a summary of the phases and the respective choices for their
duration. The specification of the external timing depends on the period of the CPU
clock, which is called “TCP” and is used in Table 16
Table 16
Programmable Bus Cycle Phases (see timing diagrams)
Parameter Valid Values Unit
Bus Cycle Phase
Address setup phase, the standard duration of this tpAB
phase (1 … 2 TCP) can be extended by 0 … 3 TCP
if the address window is changed
1 … 2 (5)
TCP
Command delay phase
tpC
tpD
tpE
tpF
0 … 3
0 … 1
1 … 32
0 … 3
TCP
TCP
TCP
TCP
Write Data setup / MUX Tristate phase
Access phase
Address / Write Data hold phase
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Data Sheet
58
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
Table 17
External Bus Cycle Timing (Operating Conditions apply)
Symbol Limits
min. max.
Parameter
Unit
Output valid delay for:
RD, WR(L/H)
tc10 CC 1
tc11 CC -1
tc12 CC 3
tc13 CC 3
tc14 CC 3
tc15 CC 3
tc16 CC 2
tc20 CC -3
tc21 CC 0
tc23 CC 1
tc24 CC -2
tc25 CC 1
tc30 SR 29
tc31 SR -5
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output valid delay for:
BHE, ALE
8
Output valid delay for:
A23…A16, A15…A0 (on PORT1)
18
18
16
19
16
4
Output valid delay for:
A15…A0 (on PORT0)
Output valid delay for:
CS
Output valid delay for:
D15…D0 (write data, mux-mode)
Output valid delay for:
D15…D0 (write data, demux-mode)
Output hold time for:
RD, WR(L/H)
Output hold time for:
BHE, ALE
11
13
4
Output hold time for:
A23…A16, A15…A0 (on PORT0)
Output hold time for:
CS
Output hold time for:
D15…D0 (write data)
13
–
Input setup time for:
D15…D0 (read data)
Input hold time
–
D15…D0 (read data)1)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD
Note: The shaded parameters have been verified by characterization.
They are not subject to production test.
Data Sheet
59
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
tpAB
tpC
tpD
tpE
tpF
CLKOUT
tc11
tc21
ALE
tc11|tc14
A23-A16,
BHE, CSx
High Address
tc10
tc20
RD
WR(L/H)
tc13
tc23
tc30
Data In
tc31
AD15-AD0
(read)
Low Address
Low Address
tc13
tc15
tc25
AD15-AD0
(write)
Data Out
Figure 19
Multiplexed Bus Cycle
Data Sheet
60
V1.0, 2005-01
XC164N
Derivatives
Timing Parameters
tpAB
tpC
tpD
tpE
tpF
CLKOUT
tc11
tc21
ALE
tc11|tc14
A23-A0,
BHE, CSx
Address
tc10
tc20
RD
WR(L/H)
tc30
Data In
tc31
D15-D0
(read)
tc16
tc25
D15-D0
(write)
Data Out
Figure 20
Demultiplexed Bus Cycle
Data Sheet
61
V1.0, 2005-01
XC164N
Derivatives
Packaging
6
Packaging
Figure 21
Package Outlines P-TQFP-100-16 (Plastic Thin Quad Flat Package)
Dimensions in mm.
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products
Data Sheet
62
V1.0, 2005-01
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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