SAF-XC858CA-9FFIAC [INFINEON]
Microcontroller, CMOS;
| 型号： | SAF-XC858CA-9FFIAC |
| 厂家： | 
Infineon |
| 描述： | Microcontroller, CMOS 微控制器 |
| 文件： | 总124页 (文件大小：2023K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit
XC858CA
8-Bit Single-Chip Microcontroller
Data Sheet
V1.0 2010-03
Microcontrollers
Edition 2010-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
8-Bit
XC858CA
8-Bit Single-Chip Microcontroller
Data Sheet
V1.0 2010-03
Microcontrollers
XC858 Data Sheet
Revision History:
Page
Subjects (major changes since last revision)
Trademarks
TriCore™ is a trademark of Infineon Technologies AG.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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XC858CA
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
XC858 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer 2 Compare/Capture Unit Registers . . . . . . . . . . . . . . . . . . . . . 41
Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Flash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Flash Bank Pagination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 62
Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.1
3.2
3.2.1
3.2.1.1
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.3.1
3.2.4
3.2.4.1
3.2.4.2
3.2.4.3
3.2.4.4
3.2.4.5
3.2.4.6
3.2.4.7
3.2.4.8
3.2.4.9
3.2.4.10
3.2.4.11
3.2.4.12
3.3
3.3.1
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
3.7
3.7.1
3.7.2
Data Sheet
I-1
V1.0, 2010-03
XC858CA
Table of Contents
3.8
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 67
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 78
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 79
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Timer 2 Capture/Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.8.1
3.8.2
3.9
3.10
3.11
3.11.1
3.11.2
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.18.1
3.18.2
3.19
3.19.1
3.20
4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
External Data Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 108
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.1
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.2.3
4.2.3.1
4.2.4
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
5
Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.1
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Data Sheet
I-2
V1.0, 2010-03
XC858CA
Table of Contents
5.2
5.3
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Data Sheet
I-3
V1.0, 2010-03
8-Bit Single-Chip Microcontroller
XC858CA
1
Summary of Features
The XC858 has the following features:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM
– 256 bytes of RAM
– 3 Kbytes of XRAM
– 64/52/36 Kbytes of Flash;
(includes memory protection strategy)
•
I/O port supply at 5.0 V and core logic supply at 2.5 V (generated by embedded
voltage regulator)
(more features on next page)
Flash
On-Chip Debug Support
MultiCAN
Port 0
Port 1
Port 3
Port 4
Port 5
8-bit Digital I/O
8-bit Digital I/O
8-bit Digital I/O
8-bit Digital I/O
8-bit Digital I/O
36K/52K/64K x 8
Boot ROM
8K x 8
XC800 Core
.
XRAM
3K x 8
Timer 2 Capture/
Compare Unit
16-bit
RAM
Timer 0
16-bit
Timer 1
16-bit
Timer 21
16-bit
256 x 8
ADC
10-bit
Watchdog
Timer
SSC
UART
UART1
8-channel
8-bit Analog Input
Figure 1
XC858 Functional Units
Data Sheet
1
V1.0, 2010-03
XC858CA
Summary of Features
Features: (continued)
•
•
•
Power-on reset generation
Brownout detection for core logic supply
On-chip OSC and PLL for clock generation
– Loss-of-Clock detection
Power saving modes
•
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
Programmable 16-bit Watchdog Timer (WDT)
Five ports
•
•
– Up to 40 pins as digital I/O
– 8 dedicated analog inputs used as A/D converter input
8-channel, 10-bit ADC
Four 16-bit timers
•
•
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 and Timer 21 (T2 and T21)
MultiCAN with 2 nodes, 32 message objects
Timer 2 Capture/compare unit for PWM signal generation (T2CCU)
Two full-duplex serial interfaces (UART and UART1)
Synchronous serial channel (SSC)
On-chip debug support
•
•
•
•
•
– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)
– 64 bytes of monitor RAM
•
•
PG-LQFP-64 pin package
Temperature range TA:
– SAF (-40 to 85 °C)
Data Sheet
2
V1.0, 2010-03
XC858CA
Summary of Features
XC858 Variant Devices
The XC858 product family features devices with different program memory sizes.
The list of XC858 devices and their difference are summarized in Table 1. The type of
package available is the LQFP-64.
Table 1
Sales Type
Device Summary
Device Program Power Temp-
Quality
Profile
Type
Memory Supply erature
(Kbytes) (V)
(°C)
SAF-XC858CA-9FFI 5V
SAF-XC858CA-13FFI 5V
SAF-XC858CA-16FFI 5V
Flash 36
Flash 52
Flash 64
5.0
5.0
5.0
-40 to 85
-40 to 85
-40 to 85
Industrial
Industrial
Industrial
As this document refers to all the derivatives, some description may not apply to a
specific product. For simplicity, all versions are referred to by the term XC858 throughout
this document.
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery
For the available ordering codes for the XC858, please refer to your responsible sales
representative or your local distributor.
Data Sheet
3
V1.0, 2010-03
XC858CA
General Device Information
2
General Device Information
Chapter 2 contains the block diagram, pin configurations, definitions and functions of the
XC858.
2.1
Block Diagram
The block diagram of the XC858 is shown in Figure 2.
XC858
Internal Bus
8-Kbyte
Boot ROM1)
XC800 Core
P0.0 - P0.7
P1.0 - P1.7
P3.0 - P3.7
P4.0 - P4.7
256-byte RAM
+
TMS
T0 & T1
UART
64-byte monitor
RAM
MBC
TM
RESET
VDDP
WDT
UART1
SSC
3-Kbyte XRAM
VSSP
VDDC
VSSC
OCDS
36/52/64-Kbyte
Flash
MultiCAN
Clock Generator
XTAL1
XTAL2
Timer 2 Capture/
Compare Unit
4 MHz
On-chip OSC
PLL
Timer 21
P5.0 - P5.7
AN0 – AN7
VAREF
VAGND
1) Includes 1-Kbyte monitor ROM
Figure 2
XC858 Block Diagram
Data Sheet
4
V1.0, 2010-03
XC858CA
General Device Information
2.2
Logic Symbol
The logic symbol of the XC858 is shown in Figure 3.
VDDP
VSSP
Port 0 8-Bit
Port 1 8-Bit
Port 3 8-Bit
Port 4 8-Bit
VAREF
VAGND
RESET
MBC
XC858
TMS
TM
Port 5 8-Bit
AN0 – AN7
XTAL1
XTAL2
VDDC
XC858 Logic Symbol
VSSC
Figure 3
Data Sheet
5
V1.0, 2010-03
XC858CA
General Device Information
2.3
Pin Configuration
The pin configuration of the XC858 in Figure 4.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P3.2
P3.3
P3.4
P3.5
RESET
VSSP
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VAREF
V
AGND
AN6
AN5
AN4
AN3
VSSP
V DDP
AN2
AN1
AN0
P0.1
P5.7
P5.6
P0.2
P0.0
VDDP
N.C.
XC858
TM
MBC
P4.0
P4.1
P4.2
P0.7
P0.3
P0.4
1
2
3
4 5
6
7
8
9 10 11 12 13 14 15 16
Figure 4
XC858 Pin Configuration, PG-LQFP-64 Package (top view)
Data Sheet
6
V1.0, 2010-03
XC858CA
General Device Information
2.4
Pin Definitions and Functions
The functions and default states of the XC858 external pins are provided in Table 2.
Table 2 Pin Definitions and Functions
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P0
I/O
Port 0
Port 0 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, UART, UART1, T2CCU,
Timer 21, MultiCAN, SSC and External
Interface.
P0.0
P0.1
17
21
Hi-Z
Hi-Z
TCK_0
JTAG Clock Input
CLKOUT_0 Clock Output
RXDO_1
UART Transmit Data Output
TDI_0
JTAG Serial Data Input
RXD_1
RXDC1_0
EXF2_1
UART Receive Data Input
MultiCAN Node 1 Receiver Input
Timer 2 External Flag Output
P0.2
18
PU
TDO_0
TXD_1
JTAG Serial Data Output
UART Transmit Data
Output/Clock Output
MultiCAN Node 1 Transmitter
Output
TXDC1_0
P0.3
P0.4
63
64
Hi-Z
Hi-Z
SCK_1
RXDO1_0
A17
SSC Clock Input/Output
UART1 Transmit Data Output
Address Line 17 Output
MTSR_1
SSC Master Transmit Output/
Slave Receive Input
TXD1_0
UART1 Transmit Data
Output/Clock Output
A18
Address Line 18 Output
P0.5
1
Hi-Z
MRST_1
SSC Master Receive Input/Slave
Transmit Output
EXINT0_0 External Interrupt Input 0
T2EX1_1
RXD1_0
A19
Timer 21 External Trigger Input
UART1 Receive Data Input
Address Line 19 Output
Data Sheet
7
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P0.6
P0.7
2
PU
T2CC4_1
WR
Compare Output Channel 4
External Data Write Control
Output
62
PU
CLKOUT_1 Clock Output
T2CC5_1
RD
Compare Output Channel 5
External Data Read Control
Output
Data Sheet
8
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P1
I/O
Port 1
Port 1 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, UART, Timer 0, Timer 1, T2CCU,
Timer 21, MultiCAN, SSC and External
Interface.
P1.0
P1.1
34
35
PU
PU
RXD_0
T2EX_0
RXDC0_0
A8
EXINT3_0 External Interrupt Input 3
T0_1
TXD_0
UART Receive Data Input
Timer 2 External Trigger Input
MultiCAN Node 0 Receiver Input
Address Line 8 Output
Timer 0 Input
UART Transmit Data
Output/Clock Output
MultiCAN Node 0 Transmitter
Output
TXDC0_0
A9
Address Line 9 Output
P1.2
P1.3
36
37
PU
PU
SCK_0
A10
MTSR_0
SSC Clock Input/Output
Address Line 10 Output
SSC Master Transmit
Output/Slave Receive Input
SSC Clock Input/Output
MultiCAN Node 1 Transmitter
Output
SCK_2
TXDC1_3
A11
Address Line 11 Output
P1.4
38
PU
MRST_0
SSC Master Receive Input/
Slave Transmit Output
EXINT0_1 External Interrupt Input 0
RXDC1_3
MTSR_2
MultiCAN Node 1 Receiver Input
SSC Master Transmit
Output/Slave Receive Input
Address Line 12 Output
A12
Data Sheet
9
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P1.5
39
PU
EXINT5_0 External Interrupt Input 5
T1_1
Timer 1 Input
MRST_2
SSC Master Receive Input/
Slave Transmit Output
Timer 2 External Flag Output
UART Transmit Data Output
EXF2_0
RXDO_0
P1.6
P1.7
10
11
PU
PU
EXINT6_0 External Interrupt Input 6
RXDC0_2
T21_1
MultiCAN Node 0 Receiver Input
Timer 21 Input
T2_1
Timer 2 Input
MultiCAN Node 0 Transmitter
Output
TXDC0_2
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
Data Sheet
10
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P3
I/O
Port 3
Port 3 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART1, T2CCU, Timer 21, MultiCAN and
External Interface.
P3.0
43
Hi-Z
RXDO1_1
T2CC0_1/
UART1 Transmit Data Output
ExternalInterruptInput3/T2CCU
EXINT3_2 Capture/Compare Channel 0
P3.1
P3.2
44
49
Hi-Z
Hi-Z
TXD1_1
UART1 Transmit Data
Output/Clock Output
MultiCAN Node 1 Receiver Input
UART1 Receive Data Input
ExternalInterruptInput4/T2CCU
RXDC1_1
RXD1_1
T2CC1_1/
EXINT4_2 Capture/Compare Channel 1
P3.3
P3.4
P3.5
50
51
52
Hi-Z
Hi-Z
Hi-Z
TXDC1_1
MultiCAN Node 1 Transmitter
Output
T2CC2_1/
ExternalInterruptInput5/T2CCU
EXINT5_2 Capture/Compare Channel 2
A13
Address Line 13 Output
RXDC0_1
T2EX1_0
T2CC3_1/
MultiCAN Node 0 Receiver Input
Timer 21 External Trigger Input
ExternalInterruptInput6/T2CCU
EXINT6_3 Capture/Compare Channel 3
A14
EXF21_0
TXDC0_1
Address Line 14 Output
Timer 21 External Flag Output
MultiCAN Node 0 Transmitter
Output
A15
-
Address Line 15 Output
P3.6
P3.7
41
42
PU
Hi-Z
EXINT4_0 External Interrupt Input 4
A16 Address Line 16 Output
Data Sheet
11
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P4
I/O
Port 4
Port 4 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for Timer 0, Timer 1, T2CCU, Timer 21,
MultiCAN and External Interface.
P4.0
P4.1
59
60
Hi-Z
Hi-Z
RXDC0_3
T2CC0_0/
MultiCAN Node 0 Receiver Input
ExternalInterruptInput3/T2CCU
EXINT3_1 Capture/Compare Channel 0
D0
TXDC0_3
Data Line 0 Input/Output
MultiCAN Node 0 Transmitter
Output
ExternalInterruptInput4/T2CCU
T2CC1_0/
EXINT4_1 Capture/Compare Channel 1
D1
Data Line 1 Input/Output
P4.2
P4.3
P4.4
61
40
45
PU
EXINT6_1 External Interrupt Input 6
T21_0
D2
Timer 21 Input
Data Line 2 Input/Output
Hi-Z
Hi-Z
T2EX_1
EXF21_1
D3
Timer 2 External Trigger Input
Timer 21 External Flag Output
Data Line 3 Input/Output
T0_0
Timer 0 Input
T2CC2_0/
ExternalInterruptInput5/T2CCU
EXINT5_1 Capture/Compare Channel 2
D4
Data Line 4 Input/Output
P4.5
46
Hi-Z
T1_0
Timer 1 Input
T2CC3_0/
ExternalInterruptInput6/T2CCU
EXINT6_2 Capture/Compare Channel 3
D5
Data Line 5 Input/Output
P4.6
P4.7
47
48
Hi-Z
Hi-Z
T2_0
Timer 2 Input
T2CC4_0
D6
Compare Output Channel 4
Data Line 6 Input/Output
T2CC5_0
D7
Compare Output Channel 5
Data Line 7 Input/Output
Data Sheet
12
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P5
I/O
Port 5
Port 5 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART, UART1, T2CCU, JTAG and External
Interface.
P5.0
P5.1
P5.2
8
PU
PU
PU
EXINT1_1 External Interrupt Input 1
A0
Address Line 0 Output
9
EXINT2_1 External Interrupt Input 2
A1
Address Line 1 Output
12
RXD_2
UART Receive Data Input
T2CC2_2/
ExternalInterruptInput5/T2CCU
EXINT5_3 Capture/Compare Channel 2
A2
Address Line 2 Output
P5.3
13
PU
EXINT1_0 External Interrupt Input 1
TXD_2
UART Transmit Data
Output/Clock Output
T2CC5_2
A3
Compare Output Channel 5
Address Line 3 Output
P5.4
P5.5
14
15
PU
PU
EXINT2_0 External Interrupt Input 2
RXDO_2
T2CC4_2
A4
UART Transmit Data Output
Compare Output Channel 4
Address Line 4 Output
TDO_1
JTAG Serial Data Output
UART1 Transmit Data Output/
Clock Output
TXD1_2
T2CC0_2/
ExternalInterruptInput3/T2CCU
EXINT3_3 Capture/Compare Channel 0
A5
Address Line 5 Output
P5.6
19
PU
TCK_1
JTAG Clock Input
RXDO1_2
T2CC1_2/
UART1 Transmit Data Output
ExternalInterruptInput4/T2CCU
EXINT4_3 Capture/Compare Channel 1
A6
Address Line 6 Output
Data Sheet
13
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
P5.7
20
PU
TDI_1
JTAG Serial Data Input
RXD1_2
T2CC3_2/
UART1 Receive Data Input
ExternalInterruptInput6/T2CCU
EXINT6_4 Capture/Compare Channel 3
A7
Address Line 7 Output
Data Sheet
14
V1.0, 2010-03
XC858CA
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(LQFP-64)
State
VDDP
7, 25, 55
–
–
–
I/O Port Supply ( 5.0 V)
Also used by EVR and analog modules. All
pins must be connected.
VSSP
26, 54
–
I/O Ground
All pins must be connected.
VDDC
VSSC
VAREF
VAGND
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
XTAL1
6
5
–
–
–
–
I
I
I
I
I
I
I
I
I
–
–
–
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Core Supply Monitor (2.5 V)
Core Supply Ground
ADC Reference Voltage
ADC Reference Ground
Analog Input 0
Analog Input 1
Analog Input 2
Analog Input 3
Analog Input 4
32
31
22
23
24
27
28
29
30
33
4
Analog Input 5
Analog Input 6
Analog Input 7
External Oscillator Input
(Feedback resistor required, normally NC)
XTAL2
TMS
RESET 53
MBC
TM
3
O
Hi-Z
External Oscillator Output
(Feedback resistor required, normally NC)
16
I
I
I
–
PD
PU
PU
–
JTAG Test Mode Select
Reset Input
Monitor & BootStrap Loader Control
58
57
Test Mode
(External pull down device required)
NC
56
–
–
No Connection
Data Sheet
15
V1.0, 2010-03
XC858CA
Functional Description
3
Functional Description
Chapter 3 provides an overview of the XC858 functional description.
3.1
Processor Architecture
The XC858 is based on a high-performance 8-bit Central Processing Unit (CPU) that is
compatible with the standard 8051 processor. While the standard 8051 processor is
designed around a 12-clock machine cycle, the XC858 CPU uses a 2-clock machine
cycle. This allows fast access to ROM or RAM memories without wait state. The
instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.
The XC858 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and Special Function Registers (SFRs).
Figure 5 shows the CPU functional blocks.
Internal Data
Memory
Core SFRs
Register Interface
External Data
Memory
External SFRs
16-bit Registers &
Memory Interface
ALU
Program Memory
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
UART
fCCLK
Memory Wait
Reset
State Machine &
Power Saving
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Interrupt
Controller
Non-Maskable Interrupt
Figure 5
CPU Block Diagram
Data Sheet
16
V1.0, 2010-03
XC858CA
Functional Description
3.2
Memory Organization
The XC858 CPU operates in the following address spaces:
•
•
•
8 Kbytes of Boot ROM program memory
256 bytes of internal RAM data memory
3 Kbytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
A 128-byte Special Function Register area
•
•
64/52/36 Kbytes of Flash program memory (Flash devices)
Figure 6, Figure 7 and Figure 8 illustrates the memory address spaces of the XC858
with 64Kbytes, 52Kbytes and 36Kbytes embedded Flash respectively.
F' FFFFH
F' FFFFH
F' FC00H
External
XRAM
3 KByte
F' F000H
F' 0000H
E' FFFFH
E' 0000H
D' FFFFH
F' 0000H
E' FFFFH
E' 0000H
D' FFFFH
Bank E
Bank D
Bank C
Bank B
Bank A
Bank 9
Bank 8
D' 0000
D' 0000
H
H
C' FFFFH
C' FFFFH
C' 0000
C' 0000
H
H
B' FFFFH
B' 0000H
A' FFFFH
A' 0000H
9' FFFFH
B' FFFFH
B' 0000H
A' FFFFH
A' 0000H
9' FFFFH
Reserved
External
9' 0000
9' 0000
H
H
8' FFFFH
8' FFFFH
8' 0000
8' 0000
H
H
7' FFFFH
7' FFFFH
Bank 7
Bank 6
7' 0000
7' 0000
H
H
6' FFFFH
6' FFFFH
6' 0000
6' 0000
H
H
5' FFFFH
5' FFFFH
Bank 5
5' 0000
5' 0000
H
H
4' FFFFH
4' FFFFH
Bank 4
Bank 3
4' 0000
4' 0000
H
H
3' FFFFH
3' FFFFH
3' 0000
3' 0000
H
H
2' FFFFH
2' FFFFH
2' FEC0H
2' FEC0H
Reserved
Reserved
External
2' FE00H
2' FC00H
2' FE00H
2' FC00H
XRAM
Reserved
3 KByte
2' F000H
2' E000H
2' F000H
2' E000H
Reserved
External
Reserved
Boot ROM
Memory Extension
Stack Pointer
(MEXSP)
8 KByte
Indirect
Direct
2' C000H
2' C000H
Address
Address
2' 0000
H
2' 0000
H
Reserved
External
1' FFFFH
FFH
80H
1' FFFFH
Bank 1
1' 0000
H
Special Function
Registers
1' 0000
H
Internal RAM
Extension Stack RAM
0' FFFFH
0' FFFFH
D-Flash
4 KByte
0' F000H
Reserved
7FH
P-Flash
60 KByte
Internal RAM
0' 0000
0' 0000
H
H
00H
Code Space
Data Space
Internal Data Space
Memory Map User Mode
Figure 6
Memory Map of XC858 with 64K Flash Memory in user mode
Data Sheet
17
V1.0, 2010-03
XC858CA
Functional Description
F’FFFFH
F’FFFFH
Reserved
External
1'0000H
FFFF H
FEC0H
1'0000H
FFFF H
FEC0H
External
Reserved
External
Reserved
FE00H
FC00H
FE00H
FC00H
XRAM
XRAM
2 KByte
2 KByte
F000H
E000H
F000H
D-Flash
4 KByte
Reserved
Boot ROM
8 KByte
C000H
C000H
P-Flash
48 KByte
Reserved
Memory Extension
Stack Pointer
(MEXSP)
Indirect
Direct
Address
Address
FFH
80H
Special Function
Registers
Extension Stack RAM
Internal RAM
7FH
Internal RAM
0000H
0000H
00H
Code Space
Data Space
Internal Data Space
Memory Map User Mode
Figure 7
Memory Map of XC858 with 52K Flash Memory in user mode
Data Sheet
18
V1.0, 2010-03
XC858CA
Functional Description
F’FFFFH
F’FFFFH
Reserved
External
1'0000H
FFFFH
FEC0H
1'0000H
FFFF H
FEC0H
External
Reserved
External
Reserved
FE00H
FC00H
FE00H
FC00H
XRAM
XRAM
2 KByte
2 KByte
F000H
E000H
F000H
D-Flash
4 KByte
Reserved
External
Boot ROM
8 KByte
C000H
8000H
C000H
8000H
Reserved
Memory Extension
Stack Pointer
(MEXSP)
Indirect
Direct
Address
Address
P-Flash
FFH
80H
Reserved
32 KByte
Special Function
Registers
Extension Stack RAM
Internal RAM
7FH
Internal RAM
0000H
0000H
00H
Code Space
Data Space
Internal Data Space
Memory Map User Mode
Figure 8
Memory Map of XC858 with 36K Flash Memory in user mode
Data Sheet
19
V1.0, 2010-03
XC858CA
Functional Description
3.2.1
Memory Protection Strategy
The XC858 memory protection strategy includes:
•
Basic protection: The user is able to block any external access via the boot option to
any memory
•
•
Read-out protection: The user is able to protect the contents in the Flash
Flash program and erase protection
These protection strategies are enabled by programming a valid password (16-bit non-
one value) via Bootstrap Loader (BSL) mode 6.
3.2.1.1 Flash Memory Protection
As long as a valid password is available, all external access to the device, including the
Flash, will be blocked.
For additional security, the Flash hardware protection can be enabled to implement a
second layer of read-out protection, as well as to enable program and erase protection.
Flash hardware protection is available only for Flash devices and comes in two modes:
•
•
Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 3.
Table 3
Flash Protection Modes
Flash
Without hardware
With hardware protection
Protection
protection
Hardware
Protection
Mode
-
0
1
Activation
Selection
Program a valid password via BSL mode 6
Bit 13 of password = 0 Bit 13 of password = 1 Bit 13 of password = 1
MSB of password = 0 MSB of password = 1
P-Flash
contents
can be read
by
Read instructions in
any program memory
Read instructions in
the P-Flash
Read instructions in
the P-Flash or D-
Flash
External
access to P-
Flash
Not possible
Not possible
Not possible
Data Sheet
20
V1.0, 2010-03
XC858CA
Functional Description
Table 3
Flash Protection Modes (cont’d)
Flash
Without hardware
With hardware protection
Protection
protection
P-Flash
Possible
Possible only on the
Possible only on the
program
and erase
condition that MSB - 1 conditionthatMSB - 1
of password is set to 1 of password is set to 1
D-Flash
contents
can be read
by
Read instructions in
any program memory
Read instructions in
Read instructions in
any program memory the P-Flash or D-
Flash
External
access to D-
Flash
Not possible
Possible
Not possible
Possible
Not possible
D-Flash
Possible, on the
conditionthatMSB - 1
of password is set to 1
program
D-Flash
erase
Possible
Possible, on these
conditions:
Possible, on the
conditionthatMSB - 1
•
MISC_CON.DFLASH of password is set to 1
EN bit is set to 1
prior to each erase
operation; or
•
the MSB - 1 of
password is set to 1
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. To
disable the flash protection, a password match is required. A password match triggers
an automatic erase of the protected P-Flash and D-Flash contents, including the
programmed password. With a valid password, the Flash hardware protection is then
enabled or disabled upon next reset. For the other protection strategies, no reset is
necessary.
Although no protection scheme can be considered infallible, the XC858 memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Data Sheet
21
V1.0, 2010-03
XC858CA
Functional Description
3.2.2
Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
•
•
Mapping
Paging
3.2.2.1 Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number of
addressable SFRs to 256. The extended address range is not directly controlled by the
CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 9.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
Data Sheet
22
V1.0, 2010-03
XC858CA
Functional Description
Standard Area (RMAP = 0)
FFH
Module 1 SFRs
SYSCON0.RMAP
Module 2 SFRs
rw
Module n SFRs
80H
FFH
SFR Data
(to/from CPU)
Mapped Area (RMAP = 1)
Module (n+1) SFRs
Module (n+2) SFRs
Module m SFRs
80H
Direct
Internal Data
Memory Address
Figure 9
Address Extension by Mapping
Data Sheet
23
V1.0, 2010-03
XC858CA
Functional Description
SYSCON0
System Control Register 0
Reset Value: 04H
7
6
5
4
3
2
1
0
0
IMODE
0
1
0
RMAP
r
rw
r
r
r
rw
Field
Bits
Type Description
RMAP
0
rw
Interrupt Node XINTR0 Enable
0
The access to the standard SFR area is
enabled
1
The access to the mapped SFR area is
enabled
1
0
2
r
r
Reserved
Returns 1 if read; should be written with 1.
[7:5],
3,1
Reserved
Returns 0 if read; should be written with 0.
Note: The RMAP bit should be cleared/set by ANL or ORL instructions.The rest bits of
SYSCON0 should not be modified.
3.2.2.2 Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC858 has a 256-SFR address range. However, this is still
less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 10.
Data Sheet
24
V1.0, 2010-03
XC858CA
Functional Description
SFR Address
(from CPU)
PAGE 0
MOD_PAGE.PAGE
SFR0
SFR1
rw
SFRx
PAGE 1
SFR0
SFR1
SFR Data
(to/from CPU)
SFRy
PAGE q
SFR0
SFR1
SFRz
Module
Figure 10
Address Extension by Paging
In order to access a register located in a page different from the actual one, the current
page must be exited. This is done by reprogramming the bit field PAGE in the page
register. Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and the old page setting
restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore
action of the current page setting. By indicating which storage bit field should be used in
parallel with the new page value, a single write operation can:
•
Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
Data Sheet
25
V1.0, 2010-03
XC858CA
Functional Description
•
Overwrite the contents of PAGE with the contents of STx, ignoring the value written
to the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
PAGE
value update
from CPU
Figure 11
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC858 supports local address extension for:
•
•
•
Parallel Ports
Analog-to-Digital Converter (ADC)
System Control Registers
Data Sheet
26
V1.0, 2010-03
XC858CA
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
Reset Value: 00H
7
6
5
4
3
2
1
0
OP
STNR
0
PAGE
w
w
r
rw
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
Data Sheet
27
V1.0, 2010-03
XC858CA
Functional Description
Field
OP
Bits
[7:6]
Type Description
w Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
3.2.3
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the
bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit
field PASS closes access to writing of all protected bits. In both cases, the value of the
bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can
only be changed when bit field PASS is written with 11000B, for example, writing D0H to
PASSWD register disables the bit protection scheme.
Note that access is opened for maximum 32 CCLKs if the “close access” password is not
written. If “open access” password is written again before the end of 32 CCLK cycles,
there will be a recount of 32 CCLK cycles. The protected bits include the N- and K-
Divider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the power-
down and slow-down enable bits, PD and SD.
Data Sheet
28
V1.0, 2010-03
XC858CA
Functional Description
3.2.3.1 Password Register
PASSWD
Password Register
Reset Value: 07H
7
6
5
4
3
2
1
0
PROTECT
_S
PASS
MODE
w
rh
rw
Field
Bits
Type Description
MODE
[1:0]
rw
Bit Protection Scheme Control Bits
00
Scheme disabled - direct access to the
protected bits is allowed.
11
Scheme enabled - the bit field PASS has to be
written with the passwords to open and close
the access to protected bits. (default)
Others:Scheme Enabled.
These two bits cannot be written directly. To change
the value between 11B and 00B, the bit field PASS
must be written with 11000B; only then, will the
MODE[1:0] be registered.
PROTECT_S
PASS
2
rh
w
Bit Protection Signal Status Bit
This bit shows the status of the protection.
0
1
Software is able to write to all protected bits.
Software is unable to write to any protected
bits.
[7:3]
Password Bits
The Bit Protection Scheme only recognizes three
patterns.
11000B Enables writing of the bit field MODE.
10011B Opens access to writing of all protected bits.
10101B Closes access to writing of all protected bits
Data Sheet
29
V1.0, 2010-03
XC858CA
Functional Description
3.2.4
XC858 Register Overview
The SFRs of the XC858 are organized into groups according to their functional units. The
contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.12.
Note: The addresses of the bitaddressable SFRs appear in bold typeface.
3.2.4.1 CPU Registers
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 4
CPU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
81
82
83
87
88
89
SP
Reset: 07
Bit Field
Type
SP
rw
H
H
H
H
H
H
H
H
H
H
H
H
Stack Pointer Register
DPL
Reset: 00
Bit Field
Type
DPL7
rw
DPL6
rw
DPL5
rw
DPL4
rw
DPL3
rw
DPL2
rw
DPL1
rw
DPL0
rw
Data Pointer Register Low
DPH
Reset: 00
Bit Field DPH7
Type rw
Bit Field SMOD
DPH6
rw
DPH5
rw
DPH4
rw
DPH3
rw
DPH2
rw
DPH1
rw
DPH0
rw
Data Pointer Register High
PCON
Reset: 00
0
GF1
rw
GF0
rw
0
IDLE
rw
Power Control Register
Type
rw
r
r
TCON
Reset: 00
Bit Field
Type
TF1
rwh
TR1
rw
TF0
rwh
TR0
rw
IE1
IT1
IE0
rwh
IT0
Timer Control Register
rwh
rw
rw
TMOD
Reset: 00
Bit Field GATE
1
T1S
T1M
rw
GATE
0
T0S
T0M
rw
Timer Mode Register
Type
rw
rw
rw
rw
8A
8B
TL0
Reset: 00
Bit Field
Type
VAL
rwh
VAL
rwh
VAL
rwh
VAL
rwh
H
H
H
H
H
H
Timer 0 Register Low
TL1
Reset: 00
Bit Field
Type
H
Timer 1 Register Low
8C
8D
94
TH0
Reset: 00
Bit Field
Type
H
Timer 0 Register High
TH1
Reset: 00
Bit Field
Type
H
Timer 1 Register High
MEX1
Reset: 00
Bit Field
Type
CB
r
NB
rw
IB
H
H
H
Memory Extension Register 1
95
96
MEX2
Reset: 00
Bit Field
Type
MCM
rw
MCB
rw
H
Memory Extension Register 2
rw
MEX3 Reset: 00
Memory Extension Register 3
Bit Field MCB1
9
0
r
MXB1
MXM
rw
MXB
rw
H
9
Type
rw
rw
Data Sheet
30
V1.0, 2010-03
XC858CA
Functional Description
Table 4
CPU Register Overview (cont’d)
Addr Register Name
Bit
Bit Field
7
0
r
6
5
4
3
MXSP
2
1
0
97
MEXSP
Reset: 7F
H
H
Memory Extension Stack
Pointer Register
Type
rwh
98
SCON
Reset: 00
Bit Field
Type
SM0
rw
SM1
rw
SM2
rw
REN
rw
TB8
rw
RB8
rwh
TI
RI
H
H
Serial Channel Control Register
rwh
rwh
99
SBUF
Reset: 00
Bit Field
Type
VAL
rwh
H
H
H
Serial Data Buffer Register
A2
EO
Reset: 00
Bit Field
0
TRAP_
EN
0
DPSE
L0
H
Extended Operation Register
Type
r
0
r
rw
ES
r
EX1
rw
rw
EX0
rw
A8
B8
B9
IEN0
Reset: 00
Bit Field
Type
EA
rw
ET2
rw
ET1
rw
ET0
rw
H
H
H
H
H
Interrupt Enable Register 0
rw
IP
Reset: 00
Bit Field
Type
0
r
PT2
rw
PS
PT1
rw
PX1
rw
PT0
rw
PX0
rw
Interrupt Priority Register
rw
IPH
Reset: 00
Bit Field
Type
0
r
PT2H
rw
PSH
rw
PT1H
rw
PX1H
rw
PT0H
rw
PX0H
rw
H
Interrupt Priority High Register
D0
PSW
Reset: 00
Bit Field
Type
CY
AC
rwh
F0
RS1
rw
RS0
rw
OV
F1
P
H
H
H
H
Program Status Word Register
rwh
rw
rwh
ACC2
rw
rw
rh
E0
E8
ACC
Reset: 00
Bit Field ACC7
Type rw
ACC6
rw
ACC5
rw
ACC4
rw
ACC3
rw
ACC1
rw
ACC0
rw
H
H
Accumulator Register
IEN1
Reset: 00
Bit Field ECCIP ECCIP ECCIP ECCIP
EXM
EX2
ESSC
EADC
Interrupt Enable Register 1
3
2
1
0
Type
rw
B7
rw
rw
B6
rw
rw
B5
rw
rw
B4
rw
rw
B3
rw
B2
rw
B1
rw
B0
F0
B
Reset: 00
Reset: 00
Bit Field
Type
H
H
H
B Register
rw
rw
rw
rw
F8
IP1
Bit Field PCCIP PCCIP PCCIP PCCIP
PXM
PX2
PSSC
PADC
H
Interrupt Priority 1 Register
3
2
1
0
Type
rw
rw
rw
rw
rw
rw
rw
rw
F9
IPH1
Reset: 00
Bit Field PCCIP PCCIP PCCIP PCCIP PXMH
PX2H
PSSC
H
PADC
H
H
H
Interrupt Priority 1 High Register
3H
rw
2H
rw
1H
rw
0H
rw
Type
rw
rw
rw
rw
3.2.4.2 System Control Registers
The system control SFRs can be accessed in the mapped memory area (RMAP = 0).
Table 5 SCU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
8F
SYSCON0
Reset: 04
Bit Field
Type
0
r
IMOD
E
0
r
1
r
0
r
RMAP
rw
H
H
System Control Register 0
rw
Data Sheet
31
V1.0, 2010-03
XC858CA
Functional Description
Table 5
SCU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
BF
SCU_PAGE
Reset: 00
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rwh
H
H
Page Register
RMAP = 0, PAGE 0
B3
MODPISEL
Bit Field
0
URRIS JTAGT JTAGT EXINT EXINT EXINT URRIS
H
H
Peripheral Input Select Register
H
DIS
rw
CKS
rw
2IS
rw
1IS
rw
0IS
rw
Type
r
rw
rw
B4
IRCON0
Reset: 00
Bit Field
0
EXINT EXINT EXINT
EXINT EXINT EXINT
EXINT
3
H
H
Interrupt Request Register 0
6
5
4
2
1
0
Type
r
rwh
rwh
rwh
rwh
rwh
RIR
rwh
TIR
rwh
EIR
B5
B6
B7
IRCON1
Reset: 00
Bit Field
0
CANS CANS ADCS ADCS
H
H
H
H
H
Interrupt Request Register 1
RC2
rwh
0
RC1
rwh
R1
R0
Type
r
rwh
rwh
rwh
0
rwh
rwh
IRCON2
Reset: 00
Bit Field
CANS
RC3
CANS
RC0
Interrupt Request Register 2
Type
r
rwh
r
rwh
EXICON0
Reset: F0
Bit Field
Type
EXINT3
EXINT2
EXINT1
EXINT0
H
H
H
External Interrupt Control
Register 0
rw
rw
rw
rw
BA
EXICON1
Reset: 3F
Bit Field
Type
0
r
EXINT6
rw
EXINT5
rw
EXINT4
rw
H
H
External Interrupt Control
Register 1
BB
NMICON
Reset: 00
Bit Field
0
NMI
NMI
0
NMI
NMI
NMI
NMI
NMI Control Register
ECC
VDDP
rw
OCDS FLASH
PLL
rw
WDT
Type
r
rw
r
rw
rw
rw
BC
BD
BE
NMISR
Reset: 00
Bit Field
0
FNMI
ECC
FNMI
0
FNMI
FNMI
FNMI
PLL
FNMI
WDT
H
H
NMI Status Register
VDDP
OCDS FLASH
Type
r
rwh
rwh
r
rwh
rwh
rwh
rwh
R
BCON
Reset: 20
Bit Field
BGSEL
NDOV BRDIS
EN
BRPRE
H
H
Baud Rate Control Register
Type
rw
rw
rw
rw
rw
BG
Reset: 00
Bit Field
Type
BR_VALUE
rwh
H
H
Baud Rate Timer/Reload
Register
E9
FDCON
Reset: 00
Bit Field
BGS
rw
SYNE ERRS
EOFS
BRK
NDOV
rwh
FDM
rw
FDEN
rw
H
H
Fractional Divider Control
Register
N
YN
YN
Type
rw
rwh
rwh
rwh
EA
EB
FDSTEP
Reset: 00
Bit Field
Type
STEP
rw
H
H
Fractional Divider Reload
Register
FDRES
Reset: 00
Bit Field
Type
RESULT
rh
H
H
Fractional Divider Result
Register
RMAP = 0, PAGE 1
Data Sheet
32
V1.0, 2010-03
XC858CA
Functional Description
Table 5
SCU Register Overview (cont’d)
Addr Register Name
Bit
Bit Field
7
6
5
PRODID
r
4
3
2
1
VERID
r
0
B3
ID
Reset: 49
H
H
H
Identity Register
Type
B4
PMCON0
Reset: 80
Bit Field VDDP
WARN
WDT
RST
WKRS
WK
SD
rw
PD
WS
H
Power Mode Control Register 0
SEL
Type
rh
rwh
rwh
rw
0
rwh
0
rw
B5
B6
B7
PMCON1
Reset: 00
Bit Field
0
r
CAN_
DIS
T2CC
SSC_
DIS
ADC_
DIS
H
H
H
H
Power Mode Control Register 1
U_DIS
Type
rw
r
rw
r
rw
rw
OSC_CON
Reset: XX
Bit Field PLLRD PLLBY PLLPD
0
XPD
OSC
SS
EORD EXTO
H
OSC Control Register
RES
rwh
P
RES
rwh
SCR
rh
Type
rwh
rw
r
rw
rwh
PLL_CON
Reset: 18
Bit Field
NDIV
rw
PLLR
PLL_L
OCK
H
PLL Control Register
Type
rh
rh
BA
BB
CMCON
Reset: 10
Bit Field
KDIV
rw
0
FCCF
G
CLKREL
H
H
H
H
H
H
Clock Control Register
Type
r
rw
rw
PASSWD
Reset: 07
Bit Field
PASS
PROT
MODE
rw
Password Register
ECT_S
Type
w
TLEN
rw
rh
BE
COCON
Reset: 00
Bit Field
Type
COUTS
rw
0
r
COREL
rw
Clock Output Control Register
E9
MISC_CON
Reset: 00
Bit Field ADCE ADCE
0
r
DFLAS
HEN
H
H
Miscellaneous Control Register
TR0_
MUX
TR1_
MUX
Type
rw
rw
NDIV
rw
rwh
EA
PLL_CON1
Reset: 20
Bit Field
Type
PDIV
H
H
PLL Control Register 1
rw
0
EB
CR_MISC Reset: 00 or 01
H
Bit Field
0
T2CCF
G
HDRS
T
H
H
Reset Status Register
Type
r
rw
r
rwh
RMAP = 0, PAGE 3
B3
XADDRH
Reset: F0
Bit Field
Type
ADDRH
rw
H
H
On-chip XRAM Address Higher
Order
B4
IRCON3
Reset: 00
Bit Field
0
CANS
RC5
CANS
RC4
0
0
H
H
H
H
Interrupt Request Register 3
Type
r
rwh
r
rwh
r
B5
B6
IRCON4
Reset: 00
Bit Field
0
CANS
RC7
0
CANS
RC6
0
H
Interrupt Request Register 4
Type
r
rwh
r
rwh
r
MODIEN
Reset: 07
Bit Field
0
r
CM5E CM4E RIREN TIREN EIREN
H
Peripheral Interrupt Enable
Register
N
N
Type
rw
rw
rw
rw
rw
Data Sheet
33
V1.0, 2010-03
XC858CA
Functional Description
Table 5
SCU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
B7
MODPISEL1
Reset: 00
Bit Field
EXINT6IS
UR1RIS
T21EX
0
r
H
H
Peripheral Input Select Register
1
IS
Type
rw
0
rw
rw
BA
BB
MODPISEL2
Reset: 00
Bit Field
T2EXI
S
T21IS
rw
T2IS
T1IS
rw
T0IS
rw
H
H
Peripheral Input Select Register
2
Type
r
rw
rw
PMCON2
Reset: 00
Bit Field
0
r
UART T21_D
H
H
Power Mode Control Register 2
1_DIS
rw
IS
Type
rw
BD
BE
MODSUSP
Reset: 01
Bit Field
0
CCTS T21SU T2SUS
0
r
WDTS
USP
H
H
Module Suspend Control
Register
USP
rw
SP
rw
P
Type
r
0
r
rw
rw
MODPISEL3
Reset: 00
Bit Field
Type
CIS
rw
SIS
rw
MIS
H
H
Peripheral Input Select Register
3
rw
EA
MODPISEL4
Reset: 00
Bit Field
Type
0
r
EXINT5IS
rw
EXINT4IS
rw
EXINT3IS
rw
H
H
Peripheral Input Select Register
4
3.2.4.3 WDT Registers
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6 WDT Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
BB
WDTCON
Reset: 00
Bit Field
0
r
WINB WDTP
0
r
WDTE WDTR WDTI
H
H
Watchdog Timer Control
Register
EN
rw
R
N
S
N
Type
rh
rw
rwh
rw
BC
BD
BE
WDTREL
Reset: 00
Bit Field
Type
WDTREL
H
H
H
H
Watchdog Timer Reload
Register
rw
WDTWINB
Reset: 00
Bit Field
Type
WDTWINB
rw
H
Watchdog Window-Boundary
Count Register
WDTL
Reset: 00
Bit Field
Type
WDT
rh
H
Watchdog Timer Register Low
BF
WDTH
Reset: 00
Bit Field
Type
WDT
rh
H
H
Watchdog Timer Register High
3.2.4.4 Port Registers
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Data Sheet
34
V1.0, 2010-03
XC858CA
Functional Description
Table 7
Port Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
B2
PORT_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rwh
H
H
Page Register
RMAP = 0, PAGE 0
80
86
90
91
92
93
P0_DATA
Reset: 00
Reset: 00
Bit Field
Type
P7
rwh
P7
rw
P6
rwh
P6
rw
P5
rwh
P5
rw
P4
rwh
P4
rw
P3
rwh
P3
rw
P2
rwh
P2
rw
P1
rwh
P1
rw
P0
rwh
P0
rw
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
P0 Data Register
P0_DIR
Bit Field
Type
P0 Direction Register
P1_DATA
Reset: 00
Bit Field
Type
P7
rwh
P7
rw
P6
rwh
P6
rw
P5
rwh
P5
rw
P4
rwh
P4
rw
P3
rwh
P3
rw
P2
rwh
P2
rw
P1
rwh
P1
rw
P0
rwh
P0
rw
P1 Data Register
P1_DIR
Reset: 00
Bit Field
Type
P1 Direction Register
P5_DATA
Reset: 00
Bit Field
Type
P7
rwh
P7
rw
P6
rwh
P6
rw
P5
rwh
P5
rw
P4
rwh
P4
rw
P3
rwh
P3
rw
P2
rwh
P2
rw
P1
rwh
P1
rw
P0
rwh
P0
rw
P5 Data Register
P5_DIR
Reset: 00
Bit Field
Type
P5 Direction Register
B0
P3_DATA
Reset: 00
Bit Field
Type
P7
rwh
P7
rw
P6
rwh
P6
rw
P5
rwh
P5
rw
P4
rwh
P4
rw
P3
rwh
P3
rw
P2
rwh
P2
rw
P1
rwh
P1
rw
P0
rwh
P0
rw
H
P3 Data Register
B1
P3_DIR
Reset: 00
Bit Field
Type
H
P3 Direction Register
C8
P4_DATA
Reset: 00
Bit Field
Type
P7
rwh
P7
rw
P6
rwh
P6
rw
P5
rwh
P5
rw
P4
rwh
P4
rw
P3
rwh
P3
rw
P2
rwh
P2
rw
P1
rwh
P1
rw
P0
rwh
P0
rw
H
P4 Data Register
C9
P4_DIR
Reset: 00
Bit Field
Type
H
P4 Direction Register
RMAP = 0, PAGE 1
80
86
90
91
92
93
P0_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
H
H
H
H
H
P0 Pull-Up/Pull-Down Select
Register
P0_PUDEN
Reset: C4
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
H
H
H
P0 Pull-Up/Pull-Down Enable
Register
P1_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P1 Pull-Up/Pull-Down Select
Register
P1_PUDEN
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P1 Pull-Up/Pull-Down Enable
Register
P5_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P5 Pull-Up/Pull-Down Select
Register
P5_PUDEN
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P5 Pull-Up/Pull-Down Enable
Register
Data Sheet
35
V1.0, 2010-03
XC858CA
Functional Description
Table 7
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
B0
P3_PUDSEL
Reset: BF
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
H
H
P3 Pull-Up/Pull-Down Select
Register
Type
rw
rw
rw
rw
rw
rw
rw
rw
B1
P3_PUDEN
Reset: 40
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P3 Pull-Up/Pull-Down Enable
Register
C8
P4_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P4 Pull-Up/Pull-Down Select
Register
C9
P4_PUDEN
Reset: 04
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P4 Pull-Up/Pull-Down Enable
Register
RMAP = 0, PAGE 2
80
86
90
91
92
93
P0_ALTSEL0
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
P0 Alternate Select 0 Register
P0_ALTSEL1
Reset: 00
Bit Field
Type
H
P0 Alternate Select 1 Register
P1_ALTSEL0
Reset: 00
Bit Field
Type
H
P1 Alternate Select 0 Register
P1_ALTSEL1
Reset: 00
Bit Field
Type
H
P1 Alternate Select 1 Register
P5_ALTSEL0
Reset: 00
Bit Field
Type
H
P5 Alternate Select 0 Register
P5_ALTSEL1
Reset: 00
Bit Field
Type
H
P5 Alternate Select 1 Register
B0
P3_ALTSEL0
Reset: 00
Bit Field
Type
H
H
P3 Alternate Select 0 Register
B1
P3_ALTSEL1
Reset: 00
Bit Field
Type
H
H
P3 Alternate Select 1 Register
C8
P4_ALTSEL0
Reset: 00
Bit Field
Type
H
H
P4 Alternate Select 0 Register
C9
P4_ALTSEL1
Reset: 00
Bit Field
Type
H
H
P4 Alternate Select 1 Register
RMAP = 0, PAGE 3
80
P0_OD
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P6
rw
P6
rw
P5
rw
P5
rw
P4
rw
P4
rw
P3
rw
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P0
rw
P0
rw
H
H
P0 Open Drain Control Register
86
P0_DS
Reset: FF
Bit Field
Type
H
H
P0 Drive Strength Control
Register
90
P1_OD
Reset: 00
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P1 Open Drain Control Register
Data Sheet
36
V1.0, 2010-03
XC858CA
Functional Description
Table 7
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
91
P1_DS
Reset: FF
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
H
H
P1 Drive Strength Control
Register
Type
rw
rw
rw
rw
rw
rw
rw
rw
92
93
P5_OD
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P6
rw
P6
rw
P5
rw
P5
rw
P4
rw
P4
rw
P3
rw
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P0
rw
P0
rw
H
H
P5 Open Drain Control Register
P5_DS
Reset: FF
Bit Field
Type
H
H
H
P5 Drive Strength Control
Register
B0
P3_OD
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P6
rw
P6
rw
P5
rw
P5
rw
P4
rw
P4
rw
P3
rw
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P0
rw
P0
rw
H
P3 Open Drain Control Register
B1
P3_DS
Reset: FF
Bit Field
Type
H
H
H
P3 Drive Strength Control
Register
C8
P4_OD
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P6
rw
P6
rw
P5
rw
P5
rw
P4
rw
P4
rw
P3
rw
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P0
rw
P0
rw
H
P4 Open Drain Control Register
C9
P4_DS
Reset: FF
Bit Field
Type
H
H
P4 Drive Strength Control
Register
3.2.4.5 ADC Registers
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 8 ADC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D1
ADC_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
Page Register
RMAP = 0, PAGE 0
CA
ADC_GLOBCTR Reset: 30
Bit Field ANON
DW
rw
CTC
rw
0
r
H
H
Global Control Register
Type
rw
CB
ADC_GLOBSTR Reset: 00
Bit Field
0
r
CHNR
0
r
SAMP BUSY
LE
H
H
Global Status Register
Type
rh
rh
rh
CC
ADC_PRAR
Reset: 00
Bit Field ASEN
1
ASEN
0
0
r
ARBM CSM1 PRIO1 CSM0 PRIO0
H
H
Priority and Arbitration Register
Type
rw
rw
rw
rw
rw
BOUND0
rw
rw
rw
CD
CE
ADC_LCBR
Reset: B7
Bit Field
Type
BOUND1
rw
H
H
Limit Check Boundary Register
ADC_INPCR0
Reset: 00
Bit Field
Type
STC
rw
H
H
Input Class 0 Register
Data Sheet
37
V1.0, 2010-03
XC858CA
Functional Description
Table 8
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
CF
ADC_ETRCR
Reset: 00
Bit Field SYNE
SYNE
ETRSEL1
ETRSEL0
H
H
External Trigger Control
Register
N1
N0
Type
rw
rw
rw
rw
RMAP = 0, PAGE 1
CA
ADC_CHCTR0
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
H
H
H
H
H
H
H
H
Channel Control Register 0
CB
ADC_CHCTR1
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 1
CC
CD
CE
ADC_CHCTR2
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 2
ADC_CHCTR3
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 3
ADC_CHCTR4
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 4
CF
D2
ADC_CHCTR5
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 5
ADC_CHCTR6
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 6
D3
ADC_CHCTR7
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 7
RMAP = 0, PAGE 2
CA
ADC_RESR0L
Reset: 00
Bit Field
Type
RESULT
0
r
VF
rh
DRC
rh
CHNR
H
H
H
H
H
H
H
H
H
Result Register 0 Low
rh
rh
CB
ADC_RESR0H
Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 0 High
CC
CD
CE
ADC_RESR1L
Reset: 00
Bit Field
Type
RESULT
rh
0
r
VF
rh
DRC
rh
CHNR
rh
H
Result Register 1 Low
ADC_RESR1H
Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 1 High
ADC_RESR2L
Reset: 00
Bit Field
Type
RESULT
rh
0
r
VF
rh
DRC
rh
CHNR
rh
H
Result Register 2 Low
CF
D2
ADC_RESR2H
Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 2 High
ADC_RESR3L
Reset: 00
Bit Field
Type
RESULT
rh
0
r
VF
rh
DRC
rh
CHNR
rh
H
Result Register 3 Low
D3
ADC_RESR3H
Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 3 High
RMAP = 0, PAGE 3
Data Sheet
38
V1.0, 2010-03
XC858CA
Functional Description
Table 8
ADC Register Overview (cont’d)
Addr Register Name
Bit
Bit Field
7
6
RESULT
rh
5
4
VF
rh
3
DRC
rh
2
1
CHNR
rh
0
CA
ADC_RESRA0L Reset: 00
H
H
H
Result Register 0, View A Low
Type
CB
ADC_RESRA0H Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 0, View A High
CC
CD
CE
ADC_RESRA1L Reset: 00
H
Bit Field
Type
RESULT
rh
VF
rh
DRC
rh
CHNR
rh
H
H
Result Register 1, View A Low
ADC_RESRA1H Reset: 00
H
Bit Field
Type
RESULT
rh
Result Register 1, View A High
ADC_RESRA2L Reset: 00
H
Bit Field
Type
RESULT
rh
VF
rh
DRC
rh
CHNR
rh
H
Result Register 2, View A Low
CF
D2
ADC_RESRA2H Reset: 00
H
Bit Field
Type
RESULT
rh
H
Result Register 2, View A High
ADC_RESRA3L Reset: 00
H
Bit Field
Type
RESULT
rh
VF
rh
DRC
rh
CHNR
rh
H
Result Register 3, View A Low
D3
ADC_RESRA3H Reset: 00
H
Bit Field
Type
RESULT
rh
H
Result Register 3, View A High
RMAP = 0, PAGE 4
CA
ADC_RCR0
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
H
H
H
H
H
Result Control Register 0
Type
rw
rw
r
rw
r
rw
CB
ADC_RCR1
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
Result Control Register 1
Type
rw
rw
r
rw
r
rw
CC
CD
CE
ADC_RCR2
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
Result Control Register 2
Type
rw
rw
r
rw
r
rw
ADC_RCR3
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
Result Control Register 3
Type
rw
rw
r
rw
r
VFC2
w
rw
VFC0
w
ADC_VFCR
Reset: 00
Bit Field
Type
0
VFC3
w
VFC1
w
H
Valid Flag Clear Register
r
RMAP = 0, PAGE 5
CA
ADC_CHINFR
Reset: 00
Bit Field CHINF CHINF CHINF CHINF CHINF CHINF CHINF CHINF
H
H
Channel Interrupt Flag Register
7
6
5
4
3
2
1
0
Type
rh
rh
rh
rh
rh
rh
rh
rh
CB
ADC_CHINCR
Reset: 00
Bit Field CHINC CHINC CHINC CHINC CHINC CHINC CHINC CHINC
H
H
Channel Interrupt Clear Register
7
6
5
4
3
2
1
0
Type
w
w
w
w
w
w
w
w
CC
ADC_CHINSR
Reset: 00
Bit Field CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS
H
H
Channel Interrupt Set Register
7
6
5
4
3
2
1
0
Type
w
w
w
w
w
w
w
w
Data Sheet
39
V1.0, 2010-03
XC858CA
Functional Description
Table 8
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
CD
ADC_CHINPR
Reset: 00
Bit Field CHINP CHINP CHINP CHINP CHINP CHINP CHINP CHINP
H
H
Channel Interrupt Node Pointer
Register
7
6
5
4
3
2
1
0
Type
rw
rw
rw
rw
rw
rw
rw
rw
CE
ADC_EVINFR
Reset: 00
Bit Field EVINF EVINF EVINF EVINF
0
EVINF EVINF
H
H
H
H
H
Event Interrupt Flag Register
7
6
5
4
1
0
Type
rh
rh
rh
rh
r
rh
rh
CF
D2
ADC_EVINCR
Reset: 00
Bit Field EVINC EVINC EVINC EVINC
0
EVINC EVINC
Event Interrupt Clear Flag
Register
7
6
5
4
1
0
Type
w
w
w
w
r
w
w
ADC_EVINSR
Reset: 00
Bit Field EVINS EVINS EVINS EVINS
0
EVINS EVINS
H
H
Event Interrupt Set Flag Register
7
6
5
4
1
0
Type
w
w
w
w
r
w
w
D3
ADC_EVINPR
Reset: 00
Bit Field EVINP EVINP EVINP EVINP
0
EVINP EVINP
H
Event Interrupt Node Pointer
Register
7
6
5
4
1
0
Type
rw
rw
rw
rw
r
rw
rw
RMAP = 0, PAGE 6
CA
ADC_CRCR1
Reset: 00
Conversion Request Control
Register 1
Bit Field
Type
CH7
rwh
CH6
rwh
CH5
rwh
CH4
rwh
0
r
H
H
H
CB
ADC_CRPR1
Reset: 00
Bit Field CHP7
CHP6
rwh
CHP5
rwh
CHP4
rwh
0
r
H
Conversion Request Pending
Register 1
Type
rwh
Rsv
CC
CD
CE
ADC_CRMR1
Reset: 00
Bit Field
LDEV
CLRP
ND
SCAN
ENSI
ENTR
0
ENGT
H
H
H
H
Conversion Request Mode
Register 1
Type
r
w
w
rw
rw
0
rw
r
rw
ADC_QMR0
Reset: 00
Bit Field
CEV
TREV
FLUS
H
CLRV
ENTR
0
ENGT
H
Queue Mode Register 0
Type
w
w
0
w
w
r
rw
r
rw
ADC_QSR0
Reset: 20
Bit Field
Rsv
EMPT
Y
EV
0
r
FILL
rh
H
Queue Status Register 0
Type
r
r
rh
RF
rh
rh
V
CF
D2
ADC_Q0R0
Reset: 00
Bit Field EXTR
Type rh
Bit Field EXTR
Type rh
Bit Field EXTR
Type
ENSI
rh
0
r
REQCHNR
H
H
H
H
Queue 0 Register 0
rh
V
rh
REQCHNR
rh
ADC_QBUR0
Reset: 00
ENSI
rh
RF
rh
0
r
H
Queue Backup Register 0
rh
D2
ADC_QINR0
Reset: 00
ENSI
w
RF
w
0
r
REQCHNR
w
H
Queue Input Register 0
w
Data Sheet
40
V1.0, 2010-03
XC858CA
Functional Description
3.2.4.6 Timer 2 Compare/Capture Unit Registers
The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area
(RMAP = 0).
Table 9
T2CCU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
C7
T2_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rwh
H
H
Page Register
RMAP = 0, PAGE 0
C0
T2_T2CON
Reset: 00
Bit Field
TF2
rwh
EXF2
rwh
0
r
EXEN
2
TR2
C/T2
rw
CP/
H
H
H
Timer 2 Control Register
RL2
Type
rw
rwh
rw
C1
T2_T2MOD
Reset: 00
Bit Field
T2RE
GS
T2RH
EN
EDGE PREN
SEL
T2PRE
DCEN
H
Timer 2 Mode Register
Type
rw
rw
rw
rw
rw
rw
C2
C3
T2_RC2L
Reset: 00
Bit Field
Type
RC2
H
H
H
Timer 2 Reload/Capture
Register Low
rwh
T2_RC2H
Reset: 00
Bit Field
Type
RC2
rwh
H
Timer 2 Reload/Capture
Register High
C4
C5
C6
T2_T2L
Reset: 00
Bit Field
Type
THL2
rwh
H
H
H
H
H
H
Timer 2 Register Low
T2_T2H
Reset: 00
Bit Field
Type
THL2
rwh
Timer 2 Register High
T2_T2CON1
Reset: 03
Bit Field
0
r
TF2EN EXF2E
N
Timer 2 Control Register 1
Type
rw
rw
RMAP = 0, PAGE 1
C0
T2CCU_CCEN
T2CCU Capture/Compare
Enable Register
Reset: 00
Bit Field
Type
CCM3
rw
CCM2
rw
CCM1
rw
CCM0
rw
H
H
C1
T2CCU_CCTBSELReset: 00
Bit Field CASC
CCTT
OV
CCTB
5
CCTB
4
CCTB
3
CCTB
2
CCTB
1
CCTB
0
H
H
T2CCU Capture/Compare Time
Base Select Register
Type
rw
rwh
rw
rw
rw
rw
rw
rw
C2
C3
C4
T2CCU_CCTRELLReset: 00
H
Bit Field
Type
CCTREL
H
H
H
T2CCU Capture/Compare
Timer Reload Register Low
rw
T2CCU_CCTRELHReset: 00
H
Bit Field
Type
CCTREL
rw
T2CCU Capture/Compare
Timer Reload Register High
T2CCU_CCTL
Reset: 00
Bit Field
Type
CCT
rwh
H
T2CCU Capture/Compare
Timer Register Low
Data Sheet
41
V1.0, 2010-03
XC858CA
Functional Description
Table 9
T2CCU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
C5
T2CCU_CCTH
Reset: 00
Bit Field
CCT
rwh
H
H
T2CCU Capture/Compare
Timer Register High
Type
C6
T2CCU_CCTCON Reset: 00
T2CCU CaptureCcompare
Timer Control Register
Bit Field
Type
CCTPRE
rw
CCTO CCTO TIMSY CCTS
H
H
VF
VEN
rw
N
T
rwh
rw
rw
RMAP = 0, PAGE 2
C0
T2CCU_COSHDWReset: 00
Bit Field ENSH TXOV COOU COOU COOU COOU COOU COOU
H
H
T2CCU Capture/compare
Enable Register
DW
rwh
T5
T4
T3
T2
T1
T0
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
C1
C2
C3
C4
C5
C6
T2CCU_CC0L
Reset: 00
Bit Field
Type
CCVALL
H
H
H
H
H
H
H
H
H
H
H
H
T2CCU Capture/Compare
Register 0 Low
rwh
T2CCU_CC0H
Reset: 00
Bit Field
Type
CCVALH
rwh
T2CCU Capture/compare
Register 0 High
T2CCU_CC1L
Reset: 00
Bit Field
Type
CCVALL
rwh
T2CCU Capture/compare
Register 1 Low
T2CCU_CC1H
Reset: 00
Bit Field
Type
CCVALH
rwh
T2CCU Capture/compare
Register 1 High
T2CCU_CC2L
Reset: 00
Bit Field
Type
CCVALL
rwh
T2CCU Capture/compare
Register 2 Low
T2CCU_CC2H
Reset: 00
Bit Field
Type
CCVALH
rwh
T2CCU Capture/compare
Register 2 High
RMAP = 0, PAGE 3
C0
C1
C2
C3
C4
C5
C6
T2CCU_COCON Reset: 00
Bit Field CCM5 CCM4 CM5F
CM4F
rwh
POLB
rw
POLA
rw
COMOD
H
H
H
H
H
H
H
H
H
H
H
H
H
H
T2CCU Compare Control
Register
Type
rw
rw
rwh
rw
T2CCU_CC3L
Reset: 00
Bit Field
Type
CCVALL
T2CCU Capture/compare
Register 3 Low
rwh
T2CCU_CC3H
Reset: 00
Bit Field
Type
CCVALH
rwh
T2CCU Capture/compare
Register 3 High
T2CCU_CC4L
Reset: 00
Bit Field
Type
CCVALL
rwh
T2CCU Capture/compare
Register 4 Low
T2CCU_CC4H
Reset: 00
Bit Field
Type
CCVALH
rwh
T2CCU Capture/compare
Register 4 High
T2CCU_CC5L
Reset: 00
Bit Field
Type
CCVALL
rwh
T2CCU Capture/compare
Register 5 Low
T2CCU_CC5H
Reset: 00
Bit Field
Type
CCVALH
rwh
T2CCU Capture/compare
Register 5 High
Data Sheet
42
V1.0, 2010-03
XC858CA
Functional Description
Table 9
T2CCU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0, PAGE 4
C2
T2CCU_CCTDTCLReset: 00
Bit Field
Type
DTM
rw
H
H
H
T2CCU Capture/Compare
Timer Dead-Time Control
Register Low
C3
T2CCU_CCTDTCHReset: 00
T2CCU Capture/Compare
Timer Dead-Time Control
Register High
Bit Field DTRE
S
DTR2
rh
DTR1
rh
DTR0 DTLEV DTE2
rh rw rw
DTE1
rw
DTE0
rw
H
Type
rwh
3.2.4.7 Timer 21 Registers
The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 10 T21 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
C0
T21_T2CON
Reset: 00
Bit Field
TF2
rwh
EXF2
rwh
0
r
EXEN
2
TR2
C/T2
rw
CP/
H
H
Timer 2 Control Register
RL2
Type
rw
rwh
rw
C1
T21_T2MOD
Reset: 00
Bit Field
T2RE
GS
T2RH
EN
EDGE PREN
SEL
T2PRE
DCEN
H
H
Timer 2 Mode Register
Type
rw
rw
rw
rw
rw
rw
rw
rw
C2
C3
T21_RC2L
Reset: 00
Bit Field
Type
RC2
H
H
H
Timer 2 Reload/Capture
Register Low
rwh
T21_RC2H
Reset: 00
Bit Field
Type
RC2
rwh
H
Timer 2 Reload/Capture
Register High
C4
C5
C6
T21_T2L
Reset: 00
Bit Field
Type
THL2
rwh
H
H
H
H
H
H
Timer 2 Register Low
T21_T2H
Reset: 00
Bit Field
Type
THL2
rwh
Timer 2 Register High
T21_T2CON1
Reset: 03
Bit Field
0
r
TF2EN EXF2E
N
Timer 2 Control Register 1
Type
rw
rw
3.2.4.8 UART1 Registers
The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).
Data Sheet
43
V1.0, 2010-03
XC858CA
Functional Description
Table 11
UART1 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
C8
SCON
Reset: 00
Bit Field
Type
SM0
rw
SM1
rw
SM2
rw
REN
rw
TB8
rw
RB8
rwh
TI
RI
H
H
Serial Channel Control Register
rwh
rwh
C9
SBUF
Reset: 00
Bit Field
Type
VAL
rwh
H
H
H
H
Serial Data Buffer Register
CA
CB
BCON
Reset: 00
Bit Field
Type
0
r
BRPRE
rw
R
H
H
Baud Rate Control Register
rw
BG
Reset: 00
Bit Field
Type
BR_VALUE
rwh
Baud Rate Timer/Reload
Register
CC
CD
CE
FDCON
Reset: 00
Bit Field
Type
0
r
NDOV
rwh
FDM
rw
FDEN
rw
H
H
H
H
H
Fractional Divider Control
Register
FDSTEP
Reset: 00
Bit Field
Type
STEP
rw
H
Fractional Divider Reload
Register
FDRES
Reset: 00
Bit Field
Type
RESULT
rh
H
Fractional Divider Result
Register
CF
SCON1
Reset: 07
Bit Field
Type
0
r
NDOV
EN
TIEN
rw
RIEN
rw
H
Serial Channel Control Register
1
rw
3.2.4.9 SSC Registers
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 12 SSC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A9
SSC_PISEL
Reset: 00
Bit Field
Type
0
r
CIS
rw
SIS
rw
MIS
rw
H
H
Port Input Select Register
AA
AA
AB
AB
SSC_CONL
Reset: 00
Bit Field
Type
LB
rw
PO
rw
PH
rw
HB
rw
BM
rw
H
H
H
H
H
Control Register Low
Programming Mode
SSC_CONL
Reset: 00
Bit Field
Type
0
r
BC
rh
H
H
H
Control Register Low
Operating Mode
SSC_CONH
Reset: 00
Bit Field
Type
EN
rw
MS
rw
0
r
AREN
rw
BEN
rw
PEN
rw
REN
rw
TEN
rw
Control Register High
Programming Mode
SSC_CONH
Reset: 00
Bit Field
Type
EN
rw
MS
rw
0
r
BSY
rh
BE
PE
RE
TE
Control Register High
Operating Mode
rwh
rwh
rwh
rwh
Data Sheet
44
V1.0, 2010-03
XC858CA
Functional Description
Table 12
SSC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
AC
AD
AE
SSC_TBL
Reset: 00
Bit Field
TB_VALUE
H
H
Transmitter Buffer Register Low
Type
rw
RB_VALUE
rh
SSC_RBL
Reset: 00
Bit Field
Type
H
H
Receiver Buffer Register Low
SSC_BRL
Reset: 00
Bit Field
Type
BR_VALUE
rw
H
H
H
Baud Rate Timer Reload
Register Low
AF
SSC_BRH
Reset: 00
Bit Field
Type
BR_VALUE
rw
H
Baud Rate Timer Reload
Register High
3.2.4.10 MultiCAN Registers
The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).
Table 13 CAN Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D8
ADCON
Reset: 00
Bit Field
Type
V3
rw
V2
rw
V1
rw
V0
rw
AUAD
rw
BSY
rh
RWEN
rw
H
H
CAN Address/Data Control
Register
D9
ADL
Reset: 00
Bit Field
Type
CA9
rwh
CA8
rwh
CA7
rwh
CA6
rwh
CA5
rwh
CA4
rwh
CA3
rwh
CA2
rwh
H
H
H
H
H
H
H
CAN Address Register Low
DA
DB
ADH
Reset: 00
Bit Field
Type
0
r
CA13
rwh
CA12
rwh
CA11
rwh
CA10
rwh
H
H
CAN Address Register High
DATA0
Reset: 00
Bit Field
Type
CD
rwh
CD
rwh
CD
rwh
CD
rwh
CAN Data Register 0
DC
DD
DE
DATA1
Reset: 00
Bit Field
Type
H
H
CAN Data Register 1
DATA2
Reset: 00
Bit Field
Type
CAN Data Register 2
DATA3
Reset: 00
Bit Field
Type
H
CAN Data Register 3
3.2.4.11 OCDS Registers
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Data Sheet
45
V1.0, 2010-03
XC858CA
Functional Description
Table 14
OCDS Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
E9
MMCR2
Reset: 8U
Bit Field STMO EXBC DSUS MBCO ALTDI MMEP MMOD JENA
H
H
H
Monitor Mode Control 2
Register
DE
rw
P
N
E
Type
rw
rw
rwh
rw
rwh
rh
rh
EA
EB
MEXTCR
Reset: 0U
Bit Field
Type
0
r
BANKBPx
rw
H
Memory Extension Control
Register
MMWR1
Reset: 00
Bit Field
Type
MMWR1
H
H
H
H
Monitor Work Register 1
rw
EC
F1
MMWR2
Reset: 00
Bit Field
Type
MMWR2
H
Monitor Work Register 2
rw
MMCR
Reset: 00
Bit Field MEXIT MEXIT
_P
0
r
MSTE MRAM MRAM
TRF
rh
RRF
rh
H
Monitor Mode Control Register
P
S_P
w
S
Type
w
rwh
rw
rwh
F2
F3
F4
F5
MMSR
Reset: 00
Bit Field MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWB0
H
H
Monitor Mode Status Register
M
F
F
F
F
Type
rw
rwh
rwh
rwh
rwh
rwh
rwh
rwh
MMBPCR
Reset: 00
Bit Field SWBC
HWB3C
HWB2C
HWB1
C
HWB0C
H
H
H
H
H
Breakpoints Control Register
Type rw
rw
rw
rw
rw
MMICR
Reset: 00
Bit Field DVEC DRET COMR MSTS
MMUI
E_P
MMUI RRIE_
RRIE
rw
Monitor Mode Interrupt Control
Register
T
R
ST
EL
rh
E
P
w
Type
rwh
rwh
rwh
w
rw
MMDR
Reset: 00
Bit Field
Type
MMRR
rh
H
Monitor Mode Data Transfer
Register
Receive
F6
F7
HWBPSR
Reset: 00
Bit Field
0
r
BPSEL
_P
BPSEL
rw
H
H
H
Hardware Breakpoints Select
Register
Type
w
HWBPDR
Reset: 00
Bit Field
Type
HWBPxx
rw
H
Hardware Breakpoints Data
Register
Data Sheet
46
V1.0, 2010-03
XC858CA
Functional Description
3.2.4.12 Flash Registers
The Flash SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 15 Flash Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
D1
D2
D3
FCON
Reset: 10
Bit Field
0
FBSY
rh
YE
1
NVST
R
MAS1
ERAS PROG
E
H
H
H
H
H
H
H
P-Flash Control Register
Type
r
rwh
YE
r
rw
rw
rw
rw
EECON
Reset: 10
Bit Field
0
EEBS
Y
1
NVST
R
MAS1
ERAS PROG
E
D-Flash Control Register
Type
r
rh
rwh
r
rw
rw
rw
rw
FCS
Reset: 80
Bit Field
1
SBEIE FTEN
0
EEDE
RR
EESE
RR
FDER
R
FSER
R
Flash Control and Status
Register
Type
r
rw rwh
r
rwh
rwh
rwh
rwh
D4
D5
D6
FEAL
Reset: 00
Bit Field
Type
ECCEADDR
rh
H
H
H
Flash Error Address Register,
Low Byte
FEAH
Reset: 00
Bit Field
Type
ECCEADDR
rh
H
Flash Error Address Register,
High Byte
FTVAL
Reset: 78
Bit Field MODE
OFVAL
rw
H
Flash Timer Value Register
Type
rw
DD
FCS1
Reset: 00
Bit Field
0
r
EEAB
ORT
H
H
Flash Control and Status
Register 1
Type
rwh
Data Sheet
47
V1.0, 2010-03
XC858CA
Functional Description
3.3
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The pagination of the Flash memory allows each page
to be erased independently.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
In-System Programming (ISP) via UART
In-Application Programming (IAP)
Error Correction Code (ECC) for dynamic correction of single-bit errors
Background program and erase operations for CPU load minimization
Support for aborting erase operation
Minimum program width
of 1-byte for D-Flash and 2-bytes for P-Flash
1-page minimum erase width
1-byte read access
Flash is delivered in erased state (read all ones)
Operating supply voltage: 2.5 V ± 7.5 %
Read access time: 1 × tCCLK = 38 ns1)
Program time for 1 wordline: 1.6 ms2)
Page erase time: 20 ms
Mass erase time: 200 ms
1) Values shown here are typical values. fsys = 144 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the maximum
frequency range for Flash read access.
2) Values shown here are typical values. fsys = 144 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the typical frequency
range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing.
Data Sheet
48
V1.0, 2010-03
XC858CA
Functional Description
Table 16 shows the Flash data retention and endurance targets for Industrial profile.
Table 16
Flash Data Retention and Endurance for Industrial Profile
(Operating Conditions apply)
Retention
Program Flash
15 years
Endurance1)2)
Size
Remarks
1000 cycles
up to 60 Kbytes
Data Flash
15 years
10 years
5 years
1 year
1000 cycles
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
10,000 cycles
30,000 cycles
100,000 cycles
1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase.
2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase.
Data Sheet
49
V1.0, 2010-03
XC858CA
Functional Description
3.3.1
Flash Bank Pagination
The XC858 product family offers Flash devices with 64 Kbytes, 52 Kbytes or 36Kbyte of
embedded Flash memory. Each Flash device consists of a Program Flash (P-Flash) and
a single Data Flash (D-Flash) bank. P-Flash has 120 pages of 8 wordlines per page with
64 bytes per wordline. D-Flash has 64 pages of 2 wordlines per page with 32 bytes per
wordline. Both types can be used for code and data storage. The label “Data” neither
implies that the D-Flash is mapped to the data memory region, nor that it can only be
used for data storage. It is used to distinguish the different page width and wordline of
each Flash bank.
The internal structure of each Flash bank represents a page architecture for flexible
erase capability. The minimum erase width is always a complete page. The D-Flash
bank is divided into smaller size for extended erasing and reprogramming capability;
even numbers for each page size are provided to allow greater flexibility and the ability
to adapt to a wide range of application requirements.
Data Sheet
50
V1.0, 2010-03
XC858CA
Functional Description
3.4
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC858 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1
Interrupt Source
Figure 12 to Figure 16 give a general overview of the interrupt sources and nodes, and
their corresponding control and status flags.
WDT Overflow
PLL Loss of Clock
FNMIWDT
NMIISR.0
NMIWDT
NMICON.0
FNMIPLL
NMIISR.1
NMIPLL
NMICON.1
Flash Timer Overflow
FNMIFLASH
NMIISR.2
>=1
Non
Maskable
Interrupt
0073
NMIFLASH
NMICON.2
H
FNMIVDDP
NMIISR.5
VDDP Pre-Warning
Flash ECC Error
NMIVDDP
NMICON.5
FNMIECC
NMIISR.6
NMIECC
NMICON.6
Figure 12
Non-Maskable Interrupt Request Sources
Data Sheet
51
V1.0, 2010-03
XC858CA
Functional Description
Highest
Timer 0
TF0
Lowest
Overflow
Priority Level
TCON.5
000B
001B
ET0
H
H
IP.1/
IPH.1
IEN0.1
Timer 1
TF1
Overflow
P
o
l
TCON.7
ET1
IP.3/
IPH.3
IEN0.3
l
i
n
g
UART
Receive
RI
SCON.0
>=1
UART
S
e
q
u
e
n
c
0023
0003
TI
ES
IEN0.4
H
H
Transmit
IP.4/
IPH.4
SCON.1
IE0
TCON.1
EINT0
e
EX0
IT0
IP.0/
IPH.0
IEN0.0
TCON.0
EXINT0
EXICON0.0/1
IE1
EINT1
TCON.3
0013
EX1
H
IT1
IP.2/
IPH.2
IEN0.2
TCON.2
EXINT1
EA
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 13
Interrupt Request Sources (Part 1)
Data Sheet
52
V1.0, 2010-03
XC858CA
Functional Description
Timer 2
TF2
Overflow
TF2EN
T2_T2CON.7
T2_T2CON1.1
>=1
T2EX
Highest
EXF2
T2_T2CON.6 EXF2EN
T2_T2CON1.0
EXEN2
T2_T2CON.3
EDGES
EL
T2_T2MOD.5
Lowest
Priority Level
CCT
Overflow
CCTOVF
T2CCU_CCTCON.3
CCTOVEN
T2CCU_CCTCON.2
>=1
Normal Divider
Overflow
NDOV
FDCON.2
NDOVEN
BCON.5
P
002B
ET2
IEN0.5
H
End of
EOFSYN
FDCON.4
IP.5/
o
l
Syn Byte
IPH.5
SYNEN
FDCON.6
l
Syn Byte Error
ERRSYN
FDCON.5
i
MultiCAN
Node 0
n
g
CANSRC0
IRCON2.0
ADC Service
Request 0
S
e
q
u
e
n
c
ADCSRC0
IRCON1.3
ADC Service
Request 1
ADCSRC1
IRCON1.4
>=1
MultiCAN
Node 1
CANSRC1
IRCON1.5
0033
EADC
IEN1.0
H
IP1.0/
IPH1.0
e
MultiCAN
Node 2
CANSRC2
IRCON1.6
EA
IEN0.7
Bit-
addressable
Request flag is cleared by hardware
Figure 14
Interrupt Request Sources (Part 2)
Data Sheet
53
V1.0, 2010-03
XC858CA
Functional Description
SSC Error
SSC Transmit
SSC Receive
Highest
EIR
IRCON1.0
EIREN
MODIEN.0
Lowest
Priority Level
TIR
IRCON1.1
>=1
TIREN
MODIEN.1
003B
ESSC
IEN1.1
H
IP1.1/
IPH1.1
RIR
IRCON1.2
RIREN
MODIEN.2
P
o
l
EXINT2
EINT2
IRCON0.2
l
i
n
g
EXINT2
EXICON0.4/5
RI
UART1_SCON.0
RIEN
UART1_SCON1.0
S
e
q
u
e
n
c
>=1
UART1
TI
UART1_SCON.1
TIEN
UART1_SCON1.1
>=1
0043
Timer 21
Overflow
TF2
T21_T2CON.7
H
EX2
IEN1.2
IP1.2/
IPH1.2
TF2EN
e
T21_T2CON1.1
>=1
EXF2
T21_T2CON.6
T21EX
EXF2EN
EXEN2
T21_T2CON1.0
T21_T2CON.3
EDGES
EL
T21_T2MOD.5
UART1 Normal
Divider Overflow
NDOV
NDOVEN
UART1_FDCON.2
UART1_SCON1.2
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 15
Interrupt Request Sources (Part 3)
Data Sheet
54
V1.0, 2010-03
XC858CA
Functional Description
Highest
Lowest
Priority Level
T2CC0/
EINT3
EXINT3
IRCON0.3
EXINT3
EXICON0.6/7
P
o
l
EXINT4
T2CC1/
EINT4
IRCON0.4
l
EXINT4
i
EXICON1.0/1
n
g
T2CC2/
EINT5
EXINT5
004B
EXM
H
IRCON0.5
S
IP1.3/
IPH1.3
e
q
u
e
n
c
e
IEN1.3
EXINT5
EXICON1.2/3
>=1
T2CC3/
EINT6
EXINT6
IRCON0.6
EXINT6
EXICON1.4/5
Compare Channel 4
Compare Channel 5
CM4F
CM4EN
T2CCU_COCON.4
MODIEN.3
CM5F
CM5EN
EA
T2CCU_COCON.5
MODIEN.4
MultiCAN Node 3
CANSRC3
IRCON2.4
Bit-
addressable
Request flag is cleared by hardware
Figure 16
Interrupt Request Sources (Part 4)
Data Sheet
55
V1.0, 2010-03
XC858CA
Functional Description
Highest
Lowest
Priority Level
CANSRC4
IRCON3.1
MultiCAN Node 4
MultiCAN Node 5
P
o
l
0053
005B
0063
H
H
ECCIP0
IEN1.4
IP1.4/
IPH1.4
l
i
n
g
CANSRC5
IRCON3.5
ECCIP1
IEN1.5
IP1.5/
IPH1.5
S
e
q
u
e
n
c
MultiCAN Node 6
MultiCAN Node 7
CANSRC6
IRCON4.1
H
H
ECCIP2
IEN1.6
IP1.6/
IPH1.6
e
IRCON4.4
CANSRC7
IRCON4.5
006B
ECCIP3
IEN1.7
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 17
Interrupt Request Sources (Part 5)
Data Sheet
56
V1.0, 2010-03
XC858CA
Functional Description
3.4.2
Interrupt Source and Vector
Each interrupt event source has an associated interrupt vector address for the interrupt
node it belongs to. This vector is accessed to service the corresponding interrupt node
request. The interrupt service of each interrupt source can be individually enabled or
disabled via an enable bit. The assignment of the XC858 interrupt sources to the
interrupt vector address and the corresponding interrupt node enable bits are
summarized in Table 17.
Table 17
Interrupt Vector Addresses
Interrupt
Vector
Assignment for XC858
Enable Bit
SFR
Source
Address
NMI
0073H
Watchdog Timer NMI
PLL NMI
Flash Timer NMI
NMIWDT
NMIPLL
NMIFLASH
NMIVDDP
NMIECC
EX0
ET0
EX1
ET1
ES
NMICON
VDDP Prewarning NMI
Flash ECC NMI
External Interrupt 0
Timer 0
External Interrupt 1
Timer 1
XINTR0
XINTR1
XINTR2
XINTR3
XINTR4
XINTR5
0003H
000BH
0013H
001BH
0023H
002BH
IEN0
UART
T2CCU
ET2
UART Fractional Divider
(Normal Divider Overflow)
MultiCAN Node 0
Data Sheet
57
V1.0, 2010-03
XC858CA
Functional Description
Table 17
Interrupt Vector Addresses (cont’d)
Interrupt
Vector
Assignment for XC858
Enable Bit
SFR
Source
Address
XINTR6
0033H
MultiCAN Nodes 1 and 2
EADC
IEN1
ADC[1:0]
SSC
External Interrupt 2
T21
XINTR7
XINTR8
003BH
0043H
ESSC
EX2
UART1
UART1 Fractional Divider
(Normal Divider Overflow)
XINTR9
004BH
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
T2CCU
EXM
MultiCAN Node 3
MultiCAN Node 4
MultiCAN Node 5
MultiCAN Node 6
MultiCAN Node 7
XINTR10
XINTR11
XINTR12
XINTR13
0053H
005BH
0063H
006BH
ECCIP0
ECCIP1
ECCIP2
ECCIP3
Data Sheet
58
V1.0, 2010-03
XC858CA
Functional Description
3.4.3
Interrupt Priority
An interrupt that is currently being serviced can only be interrupted by a higher-priority
interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of
the highest priority cannot be interrupted by any other interrupt request.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 18.
Table 18
Source
Priority Structure within Interrupt Level
Level
Non-Maskable Interrupt (NMI)
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
(highest)
1
2
3
4
5
UART Interrupt
T2CCU,UART Normal Divider Overflow, MultiCAN 6
Interrupt
ADC, MultiCAN Interrupt
SSC Interrupt
External Interrupt 2, Timer 21, UART1, UART1
Normal Divider Overflow Interrupt
7
8
9
External Interrupt [6:3], MultiCAN Interrupt
MultiCAN interrupt
MultiCAN Interrupt
MultiCAN Interrupt
MultiCAN Interrupt
10
11
12
13
14
Data Sheet
59
V1.0, 2010-03
XC858CA
Functional Description
3.5
Parallel Ports
The XC858 has 40 port pins organized into five parallel ports: Port 0 (P0), Port 1 (P1),
Port 3 (P3), Port 4 (P4) and Port 5 (P5). Each pin has a pair of internal pull-up and pull-
down devices that can be individually enabled or disabled. These ports are bidirectional
and can be used as general purpose input/output (GPIO) or to perform alternate
input/output functions for the on-chip peripherals. When configured as an output, the
open drain mode can be selected.
Bidirectional Port Features
•
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Configurable drive strength
Transfer of data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Data Sheet
60
V1.0, 2010-03
XC858CA
Functional Description
Figure 18 shows the structure of a bidirectional port pin.
Px_PUDSEL
Pull-up/Pull-down
SelectRegister
Pull-up/Pull-down
ControlLogic
Internal Bus
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_DS
Drive Strength
ControlRegister
Px_OD
Open Drain
ControlRegister
OpenDrain/Output
ControlLogic
Px_DIR
Direction Register
Px_ALTSEL0
Alternate SelectRegister 0
Px_ALTSEL1
Pull
Device
Alternate SelectRegister 1
AltDataOut 3
AltDataOut 2
AltDataOut1
Output
Driver
11
10
01
Pin
0
1
00
Out
In
Input
Driver
Px_Data
Data Register
Schmitt Trigger
AltDataIn
Pad
Figure 18
General Structure of Bidirectional Port
Data Sheet
61
V1.0, 2010-03
XC858CA
Functional Description
3.6
Power Supply System with Embedded Voltage Regulator
The XC858 microcontroller requires two different levels of power supply:
•
•
5.0 V for the Embedded Voltage Regulator (EVR) and Ports
2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 19 shows the XC858 power supply system. A power supply of 5.0 V must be
provided from the external power supply pin. The 2.5 V power supply for the logic is
generated by the EVR. The EVR helps to reduce the power consumption of the whole
chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
On-chip Peripheral
OSC logic
Memory
ADC
FLASH
PLL
VDDC(2.5V)
XTAL1&
XTAL2
GPIO
Ports
EVR
(P0-P5)
VDDP(5.0V)
VSSP
Figure 19
XC858 Power Supply System
EVR Features
•
•
•
Input voltage (VDDP): 5.0 V
Output voltage (VDDC): 2.5 V ± 7.5%
Low power voltage regulator provided in power-down mode
• VDDP prewarning detection
• VDDC brownout detection
Data Sheet
62
V1.0, 2010-03
XC858CA
Functional Description
3.7
Reset Control
The XC858 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC858 is first powered up, the status of certain pins (see Table 20) must be
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
The second type of reset in XC858 is the hardware reset. This reset function can be used
during normal operation or when the chip is in power-down mode. A reset input pin
RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
3.7.1
Module Reset Behavior
Table 19 lists the functions of the XC858 and the various reset types that affect these
functions. The symbol “■” signifies that the particular function is reset to its default state.
Table 19
Effect of Reset on Device Functions
Module/
Wake-Up
Watchdog Hardware
Power-On
Reset
■
Brownout
Reset
■
Function
Reset
Reset
■
Reset
■
CPU Core
Peripherals
■
■
■
■
■
■
On-Chip
Not affected, Not affected, Not affected, Affected, un- Affected, un-
Static RAM
Reliable
Reliable
Reliable
reliable
reliable
Oscillator,
■
Not affected ■
■
■
PLL
Port Pins
EVR
■
■
■
■
■
■
The voltage Not affected Not affected ■
regulator is
switched on
FLASH
NMI
■
■
■
■
■
■
■
■
Disabled
Disabled
Data Sheet
63
V1.0, 2010-03
XC858CA
Functional Description
3.7.2
Booting Scheme
When the XC858 is reset, it must identify the type of configuration with which to start the
different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 20
shows the available boot options in the XC858.
Table 20
MBC TMS P0.0 Type of Mode
XC858 Boot Selection 1)
PC Start Value
1
0
0
0
X
X
User Mode2); on-chip OSC/PLL non-bypassed 0000H
BSL Mode; (UART/ MultiCAN Mode3)4) and
Alternate BSL Mode5)); on-chip OSC/PLL non-
bypassed
0000H
0
1
1
1
0
0
OCDS Mode; on-chip OSC/PLL non-
bypassed
0000H
User (JTAG) Mode6); on-chip OSC/PLL non- 0000H
bypassed (normal)
1) In addition to the pins MBC, TMS and P0.0, TM pin also requires an external pull down for all the boot options.
2) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals
zero.
3) UART or MultiCAN BSL is decoded by firmware based on the protocol for product variant with MultiCAN. If no
MultiCAN variant, UART BSL is used.
4) In MultiCAN BSL mode, the clock source is switched to XTAL by firmware, bypassing the on-chip oscillator.
This avoids any frequency invariance with the on-chip oscillator and allows other frequency clock input, thus
ensuring accurate baud rate detection (especially at high bit rates).
5) Alternate BSL Mode is a user defined BSL code programmed in Flash. It is entered if the AltBSLPassword is
valid.
6) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Note: The boot options are valid only with the default set of UART and JTAG pins.
Data Sheet
64
V1.0, 2010-03
XC858CA
Functional Description
3.8
Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC858. The power consumption is indirectly proportional to the frequency, whereas the
performance of the microcontroller is directly proportional to the frequency. During user
program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features
•
•
•
•
•
Phase-Locked Loop (PLL) for multiplying clock source by different factors
PLL Base Mode
Prescaler Mode
PLL Mode
Power-down mode support
The CGU consists of an oscillator circuit and a PLL. In the XC858, the oscillator can be
from either of these two sources: the on-chip oscillator (4 MHz) or the external oscillator
(2 MHz to 20 MHz). The term “oscillator” is used to refer to both on-chip oscillator and
external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be
used by default.The external oscillator can be selected via software. In addition, the PLL
provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows
emergency routines to be executed for system recovery or to perform system shut down.
Data Sheet
65
V1.0, 2010-03
XC858CA
Functional Description
PLL_LOCK
Wrapper
PLL
External
oscillator
watchdog
lock
detect
EXTOSCR
fSYS
NR:1
OSC
Switching
circuitry
PLL
core
fvco
fp
fn
fosc
OD:1
KDIV
PLLR
NF:1
PLL
watchdog
OSCSS
PDIV PLLPD NDIV
PLLBYP
Figure 20
CGU Block Diagram
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external
clock source.
(3.1)
fSYS = fOSC
PLL Mode
The CPU clock is derived from the oscillator clock, divided by the NR factor (PDIV),
multiplied by the NF factor (NDIV), and divided by the OD factor (KDIV). PLL output must
Data Sheet
66
V1.0, 2010-03
XC858CA
Functional Description
not be bypassed for this PLL mode. The PLL mode is used during normal system
operation.
(3.2)
NF
NR x OD
fSYS = fOSC
x
System Frequency Selection
For the XC858, the value of NF, NR and OD can be selected by bits NDIV, PDIV and
KDIV respectively for different oscillator inputs inorder to obtain the required fsys. But the
combination of these factors must fulfill the following condition:
•
•
100 MHz < fVCO < 175 MHz
800 kHz < fOSC / (2 * NR) < 8 MHz
Table 21 provides examples on how the typical system frequency of fsys = 144 MHz
and maximum frequency of 160 MHz (CPU clock = 24 MHz)can be obtained for the
different oscillator sources.
Table 21
Oscillator
On-chip
System frequency (fsys = 144 MHz)
fosc
N
P
2
2
4
3
2
K
1
1
1
1
1
fsys
4 MHz
4 MHz
8 MHz
6 MHz
4 MHz
72
80
72
72
72
144 MHz
160 MHz
144 MHz
144 MHz
144 MHz
External
3.8.1
Recommended External Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 2 MHz to
20 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and
depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry. RQ values are typically specified by the crystal vendor. An
external feedback resistor Rf is also required in the external oscillator circuitry. The exact
values and related operating range are dependent on the crystal frequency and have to
be determined and optimized together with the crystal vendor using the negative
Data Sheet
67
V1.0, 2010-03
XC858CA
Functional Description
resistance method. Oscillation measurement with the final target system is strongly
recommended to verify the input amplitude at XTAL1 and to determine the actual
oscillation allowance (margin negative resistance) for the oscillator-crystal system.
When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is
left open (unconnected).
The oscillator can also be used in combination with a ceramic resonator. The final
circuitry must also be verified by the resonator vendor. Figure 21 shows the
recommended external oscillator circuitries for both operating modes, external crystal
mode and external input clock mode.
fOSC
fOSC
External Clock
Signal
XTAL1
XTAL1
2 - 20
MHz
XC858
Oscillator
XC858
Oscillator
Rf
RQ
RX2
XTAL2
XTAL2
CX1
CX2
Fundamental
Mode Crystal
VSS
VSS
Figure 21
External Oscillator Circuitry
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
Data Sheet
68
V1.0, 2010-03
XC858CA
Functional Description
3.8.2
Clock Management
The CGU generates all clock signals required within the microcontroller from a single
clock, fsys. During normal system operation, the typical frequencies of the different
modules are as follow:
•
•
•
•
CPU clock: CCLK, SCLK = 24 MHz
MultiCAN clock : MCANCLK = 24 or 48 MHz
T2CCU clock : T2CCUCLK = 24 or 48 MHz
Peripheral clock: PCLK = 24 MHz
In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The
clock output frequency, which is derived from the clock output divider (bit COREL), can
further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output
frequency has a 50% duty cycle. Figure 22 shows the clock distribution of the XC858.
T2CCFG
T2CCU
CLK
T2CCU
FCCFG
MCAN
CLK
MultiCAN
CLKREL
SD
PCLK
Peripherals
1
OSCSS
FCLK
SCLK
CCLK
/2
CORE
External
OSC
fsys
fosc
PLL
On-chip
OSC
0
/3
NF,NR,OD
COREL
TLEN
Toggle
Latch
CLKOUT
COUTS
Figure 22
Clock Generation from fsys
Data Sheet
69
V1.0, 2010-03
XC858CA
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 22.
Table 22
System frequency (fsys = 144 MHz)
Power Saving Mode Action
Idle
Clock to the CPU is disabled.
Slow-down
Clocks to the CPU and all the peripherals are divided by a
common programmable factor defined by bit field
CMCON.CLKREL.
Power-down
Oscillator and PLL are switched off.
Data Sheet
70
V1.0, 2010-03
XC858CA
Functional Description
3.9
Power Saving Modes
The power saving modes of the XC858 provide flexible power consumption through a
combination of techniques, including:
•
•
•
•
Stopping the CPU clock
Stopping the clocks of individual system components
Reducing clock speed of some peripheral components
Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 23) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
•
•
•
Idle mode
Slow-down mode
Power-down mode
ACTIVE
any interrupt
& SD=0
EXINT0/RXD pin
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
clear SD
bit
POWER-DOWN
IDLE
set IDLE
bit
set PD
bit
any interrupt
& SD=1
EXINT0/RXD pin
& SD=1
SLOW-DOWN
Figure 23
Transition between Power Saving Modes
Data Sheet
71
V1.0, 2010-03
XC858CA
Functional Description
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC858 system reset. Hence, routine service of the WDT confirms
that the system is functioning properly. This ensures that an accidental malfunction of
the XC858 will be aborted in a user-specified time period.
In debug mode, the WDT is default suspended and stops counting. Therefore, there is
no need to refresh the WDT during debugging.
Features
•
•
•
•
•
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of fPCLK/2 or fPCLK/128
Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit
timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be
preset to a user-programmable value via a watchdog service access in order to modify
the watchdog expire time period. The lower 8 bits are reset on each service access.
Figure 24 shows the block diagram of the WDT unit.
WDT
WDTREL
Control
Clear
WDT Low Byte
1:2
MUX
WDT High Byte
fPCLK
1:128
Overflow/Time-out Control &
Window-boundary control
FNMIWDT
WDTRST
.
WDTIN
ENWDT
Logic
ENWDT_P
WDTWINB
Figure 24
WDT Block Diagram
Data Sheet
72
V1.0, 2010-03
XC858CA
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is
entered. The prewarning period lasts for 30H count, after which the system is reset
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000H to the value obtained from the concatenation of WDTWINB and
00H.
After being serviced, the WDT continues counting up from the value (<WDTREL> * 28).
The time period for an overflow of the WDT is programmable in two ways:
•
•
The input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128
The reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
The period, PWDT, between servicing the WDT and the next overflow can be determined
by the following formula:
2
(1 + WDTIN × 6) × (216 – WDTREL × 28)
PWDT = -----------------------------------------------------------------------------------------------------
fPCLK
(3.3)
If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 25. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be
smaller than WDTREL.
Data Sheet
73
V1.0, 2010-03
XC858CA
Functional Description
Count
FFFFH
WDTWINB
WDTREL
time
No refresh
allowed
Refresh allowed
Figure 25
WDT Timing Diagram
Table 23 lists the possible watchdog time ranges that can be achieved using a certain
module clock. Some numbers are rounded to 3 significant digits.
Table 23
Reload value
In WDTREL
Watchdog Time Ranges
Prescaler for fPCLK
2 (WDTIN = 0)
24 MHz
128 (WDTIN = 1)
24 MHz
FFH
7FH
00H
21.3 µs
2.75 ms
5.46 ms
1.37 ms
176 ms
350 ms
3.11
UART and UART1
The XC858 provides two Universal Asynchronous Receiver/Transmitter (UART and
UART1) modules for full-duplex asynchronous reception/transmission. Both are also
receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features
•
Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– Fixed or variable baud rate
Receive buffered
•
•
Multiprocessor communication
Data Sheet
74
V1.0, 2010-03
XC858CA
Functional Description
•
Interrupt generation on the completion of a data transmission or reception
The UART modules can operate in the four modes shown in Table 24.
Table 24
UART Modes
Operating Mode
Baud Rate
PCLK/2
Variable
PCLK/32 or fPCLK/641)
Variable
Mode 0: 8-bit shift register
Mode 1: 8-bit shift UART
Mode 2: 9-bit shift UART
Mode 3: 9-bit shift UART
f
f
1) For UART1 module, the baud rate is fixed at fPCLK/64.
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
f
PCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock
and can be configured to eitherfPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is
available. The variable baud rate is set by the underflow rate on the dedicated baud-rate
generator. For UART module, the variable baud rate alternatively can be set by the
overflow rate on Timer 1.
3.11.1
Baud-Rate Generator
Both UART modules have their own dedicated baud-rate generator, which is based on
a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and
fractional divider) for generating a wide range of baud rates based on its input clock fPCLK
see Figure 26.
,
Data Sheet
75
V1.0, 2010-03
XC858CA
Functional Description
Fractional Divider
8-Bit Reload Value
FDSTEP
1
FDEN&FDM
FDM
1
0
Adder
fDIV
00
01
11
0
1
fBR
8-Bit Baud Rate Timer
0
fMOD
FDRES
(overflow)
10
FDEN
R
fDIV
fPCLK
Prescaler
clk
11
10
NDOV
01
00
‘0’
Figure 26
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the
output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (fBR) value is dependent on the following parameters:
•
•
•
Input clock fPCLK
Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON
Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional
divider mode)
•
8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
Data Sheet
76
V1.0, 2010-03
XC858CA
Functional Description
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
fPCLK
where 2BRPRE × (BR_VALUE + 1) > 1
-----------------------------------------------------------------------------------
baud rate =
16 × 2BRPRE × (BR_VALUE + 1)
(3.4)
fPCLK
STEP
----------------------------------------------------------------------------------- --------------
baud rate =
×
16 × 2BRPRE × (BR_VALUE + 1)
256
(3.5)
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Table 25 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 25
Typical Baud rates for UART with Fractional Divider disabled
Baud rate
Prescaling Factor Reload Value
Deviation Error
(2BRPRE)
(BR_VALUE + 1)
78 (4EH)
19.2 kBaud
9600 Baud
4800 Baud
2400 Baud
1 (BRPRE=000B)
1 (BRPRE=000B)
2 (BRPRE=001B)
4 (BRPRE=010B)
0.17 %
0.17 %
0.17 %
0.17 %
156 (9CH)
156 (9CH)
156 (9CH)
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 26 lists the resulting deviation errors from generating a baud rate of
57.6 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
77
V1.0, 2010-03
XC858CA
Functional Description
Table 26
Deviation Error for UART with Fractional Divider enabled
fPCLK
Prescaling Factor Reload Value
STEP
Deviation
(2BRPRE)
(BR_VALUE + 1)
6 (6H)
Error
24 MHz
12 MHz
8 MHz
6 MHz
1
1
1
1
59 (3BH)
59 (3BH)
59 (3BH)
236 (ECH)
+0.03 %
+0.03 %
+0.03 %
+0.03 %
3 (3H)
2 (2H)
6 (6H)
3.11.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
2SMOD × fPCLK
Mode 1, 3 baud rate= ----------------------------------------------------
32 × 2 × (256 – TH1)
(3.6)
3.12
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 26). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.
The output frequency in normal divider mode is derived as follows:
1
-----------------------------
fMOD = fDIV
×
256 – STEP
(3.7)
Data Sheet
78
V1.0, 2010-03
XC858CA
Functional Description
3.13
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features
•
Master and slave mode operation
– Full-duplex or half-duplex operation
Transmit and receive buffered
•
•
Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
•
•
•
Variable baud rate
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 27 shows the block diagram of the SSC.
Data Sheet
79
V1.0, 2010-03
XC858CA
Functional Description
PCLK
SS_CLK
MS_CLK
Baud-rate
Generator
Clock
Control
Shift
Clock
RIR
TIR
EIR
Receive Int. Request
Transmit Int. Request
Error Int. Request
SSC Control Block
Register CON
Status
Control
TXD(Master)
RXD(Slave)
Pin
Control
16-Bit Shift
Register
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 27
SSC Block Diagram
Data Sheet
80
V1.0, 2010-03
XC858CA
Functional Description
3.14
Timer 0 and Timer 1
Timer 0 and Timer 1 can function as both timers or counters. When functioning as a
timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input
clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are
incremented in response to a 1-to-0 transition (falling edge) at their respective external
input pins, T0 or T1.
Timer 0 and 1 are fully compatible and can be configured in four different operating
modes for use in a variety of applications, see Table 27. In modes 0, 1 and 2, the two
timers operate independently, but in mode 3, their functions are specialized.
Table 27
Mode
0
Timer 0 and Timer 1 Modes
Operation
13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
1
2
3
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet
81
V1.0, 2010-03
XC858CA
Functional Description
3.15
Timer 2 and Timer 21
Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible
and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel
capture mode, see Table 28. As a timer, the timers count with an input clock of PCLK/12
(if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the
counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is
disabled).
Table 28
Mode
Timer 2 Modes
Description
Auto-reload Up/Down Count Disabled
•
•
•
Count up only
Start counting from 16-bit reload value, overflow at FFFFH
Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
Programmble reload value in register RC2
Interrupt is generated with reload event
•
•
Up/Down Count Enabled
•
•
•
Count up or down, direction determined by level at input pin T2EX
No interrupt is generated
Count up
– Start counting from 16-bit reload value, overflow at FFFFH
– Reload event triggered by overflow condition
– Programmble reload value in register RC2
Count down
– Start counting from FFFFH, underflow at value defined in register
RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFFH
•
Channel
capture
•
•
•
•
•
•
•
Count up only
Start counting from 0000H, overflow at FFFFH
Reload event triggered by overflow condition
Reload value fixed at 0000H
Capture event triggered by falling/rising edge at pin T2EX
Captured timer value stored in register RC2
Interrupt is generated with reload or capture event
Data Sheet
82
V1.0, 2010-03
XC858CA
Functional Description
3.16
Timer 2 Capture/Compare Unit
The T2CCU (Timer 2 Capture/Compare Unit) consists of the standard Timer 2 unit and
a Capture/compare unit (CCU). The Capture/Compare Timer (CCT) is part of the CCU.
Control is available in the T2CCU to select individually for each of its 16-bit
capture/compare channel, either the Timer 2 or the Capture/Compare Timer (CCT) as
the time base. Both timers have a resolution of 16 bits.The clock frequency of T2CCU,
fT2CCU, could be set at PCLK frequency or 2 times the PCLK frequency.
The T2CCU can be used for various digital signal generation and event capturing like
pulse generation, pulse width modulation, pulse width measuring etc. Target
applications include various automotive control as well as industrial (frequency
generation, digital-to-analog conversion, process control etc.).
T2CCU Features
•
Option to select individually for each channel, either Timer 2 or Capture/Compare
Timer as time base
•
•
•
•
•
•
Extremely flexible Capture/Compare Timer count rate by cascading with Timer 2
Capture/Compare Timer may be ‘reset’ immediately by triggering overflow event
16-bit resolution
Six compare channels in total
Four capture channels multiplexed with the compare channels, in total
Shadow register for each compare register
– Transfer via software control or on timer overflow.
Compare Mode 0: Compare output signal changes from the inactive level to active
level on compare match. Returns to inactive level on timer overflow.
– Active level can be defined by register bit for channel groups A and B.
– Support of 0% to 100% duty cycle in compare mode 0.
Compare Mode 1: Full control of the software on the compare output signal level, for
the next compare match.
•
•
•
•
Concurrent Compare Mode with channel 0
Capture Mode 0: Capture on any external event (rising/falling/both edge) at the 4 pins
T2CC0 to T2CC3.
•
•
Capture Mode 1: Capture upon writing to the low byte of the corresponding channel
capture register.
Capture mode 0 or 1 can be established independently on the 4 capture channels.
Data Sheet
83
V1.0, 2010-03
XC858CA
Functional Description
3.17
Controller Area Network (MultiCAN)
The MultiCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN
node can receive and transmit standard frames with 11-bit identifiers as well as extended
frames with 29-bit identifiers.
Both CAN nodes share a common set of message objects, where each message object
may be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects may be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double chained lists, where each CAN node has
it’s own list of message objects. A CAN node stores frames only into message objects
that are allocated to the list of the CAN node. It only transmits messages from objects of
this list. A powerful, command driven list controller performs all list operations.
The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are
programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects
each CAN node to a bus transceiver.
MultiCANModule Kernel
CANSRC[7:0]
Interrupt
Controller
TXDC1
Message
Object
Buffer
CAN
fCAN
Clock
Node 1
Linked
List
Control
RXDC1
TXDC0
RXDC0
Port
Control
Control
CAN
32
Node 0
Objects
A[13: 2]
D[31:0]
Address
Decoder &
Data
control
CAN Control
AccessMediator
MultiCAN_XC8_overview
Figure 28
Features
Overview of the MultiCAN
•
Compliant to ISO 11898.
Data Sheet
84
V1.0, 2010-03
XC858CA
Functional Description
•
•
•
•
CAN functionality according to CAN specification V2.0 B active.
Dedicated control registers are provided for each CAN node.
A data transfer rate up to 1 MBaud is supported.
Flexible and powerful message transfer control and error handling capabilities are
implemented.
•
•
Advanced CAN bus bit timing analysis and baud rate detection can be performed for
each CAN node via the frame counter.
Full-CAN functionality: A set of 32 message objects can be individually
– allocated (assigned) to any CAN node
– configured as transmit or receive object
– setup to handle frames with 11-bit or 29-bit identifier
– counted or assigned a timestamp via a frame counter
– configured to remote monitoring mode
•
Advanced Acceptance Filtering:
– Each message object provides an individual acceptance mask to filter incoming
frames.
– A message object can be configured to accept only standard or only extended
frames or to accept both standard and extended frames.
– Message objects can be grouped into 4 priority classes.
– The selection of the message to be transmitted first can be performed on the basis
of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.
Advanced Message Object Functionality:
•
•
– Message Objects can be combined to build FIFO message buffers of arbitrary
size, which is only limited by the total number of message objects.
– Message objects can be linked to form a gateway to automatically transfer frames
between 2 different CAN buses. A single gateway can link any two CAN nodes. An
arbitrary number of gateways may be defined.
Advanced Data Management:
– The Message objects are organized in double chained lists.
– List reorganizations may be performed any time, even during full operation of the
CAN nodes.
– A powerful, command driven list controller manages the organization of the list
structure and ensures consistency of the list.
– Message FIFOs are based on the list structure and can easily be scaled in size
during CAN operation.
– Static Allocation Commands offer compatibility with TwinCAN applications, which
are not list based.
•
Advanced Interrupt Handling:
– Up to 8 interrupt output lines are available. Most interrupt requests can be
individually routed to one of the 8 interrupt output lines.
– Message postprocessing notifications can be flexibly aggregated into a dedicated
register field of 64 notification bits.
Data Sheet
85
V1.0, 2010-03
XC858CA
Functional Description
3.18
Analog-to-Digital Converter
The XC858 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with
eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at AN0 - AN7.
Features
•
•
•
•
•
Successive approximation
8-bit or 10-bit resolution
Eight analog channels
Four independent result registers
Result data protection for slow CPU access
(wait-for-read mode)
•
•
•
•
Single conversion mode
Autoscan functionality
Limit checking for conversion results
Data reduction filter
(accumulation of up to 2 conversion results)
Two independent conversion request sources with programmable priority
Selectable conversion request trigger
Flexible interrupt generation with configurable service nodes
Programmable sample time
•
•
•
•
•
•
•
•
•
Programmable clock divider
Cancel/restart feature for running conversions
Integrated sample and hold circuitry
Compensation of offset errors
Low power modes
3.18.1
ADC Clocking Scheme
A common module clock fADC generates the various clock signals used by the analog and
digital parts of the ADC module:
• fADCA is input clock for the analog part.
• fADCI is internal clock for the analog part (defines the time base for conversion length
and the sample time). This clock is generated internally in the analog part, based on
the input clock fADCA to generate a correct duty cycle for the analog components.
• fADCD is input clock for the digital part.
Figure 29 shows the clocking scheme of the ADC module. The prescaler ratio is
selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected
when the maximum performance of the ADC is not required.
Data Sheet
86
V1.0, 2010-03
XC858CA
Functional Description
fADC = fPCLK
fADCD
arbiter
registers
interrupts
digital part
fADCA
CTC
MUX
÷32
÷ 4
÷3
fADCI
analog
components
÷ 2
clock prescaler
analog part
Figure 29
ADC Clocking Scheme
For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as
shown in Table 29.
Table 29
fADCI Frequency Selection
Module Clock fADC
CTC
Prescaling Ratio Analog Clock fADCI
24 MHz
00B
÷ 2
12 MHz
01B
÷ 3
8 MHz
10B
÷ 4
6 MHz
11B (default)
÷ 32
750 kHz
During slow-down mode, fADC may be reduced further, for example, to 12 MHz or 6 MHz.
However, it is important to note that the conversion error could increase due to loss of
charges on the capacitors, if fADC becomes too low during slow-down mode.
3.18.2
ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
Data Sheet
87
V1.0, 2010-03
XC858CA
Functional Description
•
•
•
•
Synchronization phase (tSYN
Sample phase (tS)
)
Conversion phase
Write result phase (tWR)
conversion start
trigger
Source
Channel
interrupt
Result
interrupt
interrupt
Sample Phase
Conversion Phase
fADCI
BUSY Bit
SAMPLE Bit
tSYN
tS
Write Result Phase
tWR
tCONV
Figure 30
ADC Conversion Timing
Data Sheet
88
V1.0, 2010-03
XC858CA
Functional Description
3.19
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
•
•
•
•
Use the built-in debug functionality of the XC800 Core
Add a minimum of hardware overhead
Provide support for most of the operations by a Monitor Program
Use standard interfaces to communicate with the Host (a Debugger)
Features
•
Set breakpoints on instruction address and on address range within the Program
Memory
•
•
•
•
Set breakpoints on internal RAM address range
Support unlimited software breakpoints in Flash/RAM code region
Process external breaks via JTAG and upon activating a dedicated pin
Step through the program code
The OCDS functional blocks are shown in Figure 31. The Monitor Mode Control (MMC)
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals.
After processing memory address and control signals from the core, the MMC provides
proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and
a Monitor RAM (for work-data and Monitor-stack).
The OCDS system is accessed through the JTAG1), which is an interface dedicated
exclusively for testing and debugging activities and is not normally used in an
application. The dedicated MBC pin is used for external configuration and debugging
control.
Note: All the debug functionality described here can normally be used only after XC858
has been started in OCDS mode.
1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports
(Ports 1 and 2/Port 5).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet
89
V1.0, 2010-03
XC858CA
Functional Description
JTAG Module
Memory
Control
Unit
TMS
TCK
TDI
TCK
TDI
Debug
JTAG
Interface
User
Boot/
TDO
TDO
Program Monitor
Control
Memory
ROM
Reset
Monitor Mode Control
MBC
Monitor &
Bootstrap loader
Control line
User
Internal
RAM
Monitor
RAM
Suspend
Control
System
Control
Unit
Reset
Clock
Reset Clock Debug PROG PROG Memory
Interface & IRAM Data Control
Addresses
- parts of
OCDS
XC800 Core
OCDS_XC886C-Block_Diagram-UM-v0.2
Figure 31
3.19.1
OCDS Block Diagram
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is
also true immediately after reset.
The JTAG ID register contents for the XC858 Flash devices are given in Table 30.
Table 30
Device Type
Flash
JTAG ID Summary
Device Name
JTAG ID
XC858CA-16FF
XC858CA-13FF
XC858CA-9FF
1018 2083H
1018 3083H
1018 4083H
Data Sheet
90
V1.0, 2010-03
XC858CA
Functional Description
3.20
Chip Identification Number
The XC858 identity (ID) register is located at Page 1 of address B3H. The value of ID
register is 49H. However, for easy identification of product variants, the Chip
Identification Number, which is an unique number assigned to each product variant, is
available. The differentiation is based on the product, variant type and device step
information.
Two methods are provided to read a device’s chip identification number:
•
•
In-application subroutine, GET_CHIP_INFO
Bootstrap loader (BSL) mode A
Table 31 lists the chip identification numbers of available XC858 Flash device variants.
Table 31 Chip Identification Number
Product Variant
Chip Identification Number
AC-Step
Flash Devices
XC858CA-16FF
XC858CA-13FF
XC858CA- 9FF
4B5800C3H
4B5904C3H
4B5A08C3H
Data Sheet
91
V1.0, 2010-03
XC858CA
Electrical Parameters
4
Electrical Parameters
Chapter 4 provides the characteristics of the electrical parameters which are
implementation-specific for the XC858.
4.1
General Parameters
The general parameters are described here to aid the users in interpreting the
parameters mainly in Section 4.2 and Section 4.3.
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XC858
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•
CC
These parameters indicate Controller Characteristics, which are distinctive features
of the XC858 and must be regarded for a system design.
SR
•
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC858 is designed in.
Data Sheet
92
V1.0, 2010-03
XC858CA
Electrical Parameters
4.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC858 can be subjected to without
permanent damage.
Table 32
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
min.
-40
-65
-40
-0.5
max.
85
150
120
6
Ambient temperature
Storage temperature
Junction temperature
TA
TST
TJ
°C
°C
°C
V
under bias
under bias
Voltage on power supply pin with VDDP
respect to VSS
Voltage on any pin with respect VIN
to VSS
-0.5
VDDP
+
V
Whatever is
lower
0.5 or
max. 6
Input current on any pin during
overload condition
IIN
-10
–
10
50
mA
mA
Absolute sum of all input currents Σ|IIN|
during overload condition
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pin with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
93
V1.0, 2010-03
XC858CA
Electrical Parameters
4.1.3
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC858. All parameters mentioned in the following table refer to these
operating conditions, unless otherwise noted.
Table 33
Parameter
Operating Condition Parameters
Symbol Limit Values
Unit Notes/
Conditions
min.
4.5
0
max.
5.5
Digital power supply voltage VDDP
V
5V Device
Digital ground voltage
CPU Clock Frequency1)
Ambient temperature
VSS
fCCLK
TA
V
24
85
MHz
°C
-40
SAF-XC858
1) fCCLK is the input frequency to the XC800 core. Please refer to Figure 22 for detailed description.
Data Sheet
94
V1.0, 2010-03
XC858CA
Electrical Parameters
4.2
DC Parameters
The electrical characteristics of the DC Parameters are detailed in this section.
4.2.1
Input/Output Characteristics
Table 34 provides the characteristics of the input/output pins of the XC858.
Table 34
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
V
DDP = 5 V Range
Output low voltage
VOL
VOH
CC –
0.6
–
V
V
IOL = 9 mA (DS = 0)1)
IOL = 12 mA (DS = 1)2)
Output high voltage
CC 2.4
I
OH = -20 mA (DS = 0)1)
I
OH = -25 mA (DS = 1)2)
Input low voltage
Input high voltage
Input Hysteresis
Input low voltage at
XTAL1
VIL
VIH
HYS
VILX
SR -0.3
SR 2.2
CC 0.35
SR -0.3
0.8
VDDP
–
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode3)4)
0.8
Input high voltage at
XTAL1
Pull-up current
VIHX
IPU
SR 3.4
VDDP
V
SR –
-88
SR –
66
-20
–
10
–
µA
µA
µA
µA
µA
VIH,min
VIL,max
VIL,max
VIH,min
Pull-down current
IPD
Input leakage current IOZ1
CC -1
1
0 < VIN < VDDP
,
TA ≤ 85°C5)
Overload current on
any pin
Absolute sum of
overload currents
Voltage on any pin
during VDDP power off
IOV
SR -5
5
mA
mA
V
6)
7)
Σ|IOV| SR –
VPO SR –
25
0.3
Data Sheet
95
V1.0, 2010-03
XC858CA
Electrical Parameters
Table 34
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
Maximum current per IM SR SR –
25
mA
mA
pin (excluding VDDP
and VSS)
Maximum current for
Σ|IM|
SR –
150
all pins (excluding
V
DDP and VSS)
6)
6)
Maximum current into IMVDDP SR –
200
200
mA
mA
VDDP
Maximum current out IMVSS SR –
of VSS
1) DS = 0 refers to the pin having a weak drive strength which is programmable via Px_DS register.
2) DS = 1 refers to the pin having a strong drive strength which is programmable via Px_DS register.
3) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses
switching due to external system noise.
4) P0.1 has a minimum input hysteresis of 0.25V.
5) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and
RESET pin have internal pull devices and are not included in the input leakage current characteristic.
6) Not subjected to production test, verified by design/characterization.
7) Not subjected to production test, verified by design/characterization. However, for applications with strict low
power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin
when VDDP is powered off.
Data Sheet
96
V1.0, 2010-03
XC858CA
Electrical Parameters
4.2.2
Supply Threshold Characteristics
Table 35 provides the characteristics of the supply threshold in the XC858.
5.0V
VDDPPW
VDDP
2.5V
VDDCBO
VDDCRDR
VDDC
VDDCPOR
Figure 32
Supply Threshold Parameters
Table 35
Supply Threshold Parameters (Operating Conditions apply)
Parameters
Symbol
Limit Values
Unit
min.
CC 1.7
VDDCRDR CC 1.2
CC 3.8
VDDCPOR CC 1.7
typ.
1.9
–
4.2
1.9
max.
2.2
–
4.5
2.2
V
DDC brownout voltage1)
RAM data retention voltage
DDP prewarning voltage
Power-on reset voltage1)2)
VDDCBO
V
V
V
V
V
VDDPPW
1) Detection is enabled in both active and power-down mode.
2) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
Data Sheet
97
V1.0, 2010-03
XC858CA
Electrical Parameters
4.2.3
ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (VSS) must be
externally connected to one single star point in the system. The voltage difference
between the ground pins must not exceed 200mV.
Table 36
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Parameter
Symbol
Limit Values
min. typ . max.
Unit Test Conditions/
Remarks
1)
Analog reference
voltage
Analog reference
ground
Analog input
voltage range
ADC clocks
VAREF
VAGND
VAIN
SR VAGND VDDP VDDP
V
+ 1
+ 0.05
1)
SR VSS - VSS VAREF
V
0.05
- 1
SR VAGND
–
VAREF
V
fADC
fADCI
–
–
24
–
–
142)
MHz module clock1)
MHz internal analog clock1)
See Figure 29
1)
Sample time
tS
tC
CC (2 + INPCR0.STC) × µs
tADCI
1)
Conversion time
CC See Section 4.2.3.1 µs
Differential
Nonlinearity
|EADNL| CC –
–
1.5
LSB 10-bit conversion
Integral
Nonlinearity
|EAINL| CC –
–
2.5
LSB 10-bit conversion
Offset
Gain
Switched
capacitance at the
reference voltage
input
|EAOFF| CC –
|EAGAIN| CC –
CAREFSW CC –
–
–
10
3
2.5
14
LSB 10-bit conversion
LSB 10-bit conversion
pF
1)3)
1)4)
Switched
CAINSW CC –
4
5
pF
capacitance at the
analog voltage
inputs
Data Sheet
98
V1.0, 2010-03
XC858CA
Electrical Parameters
Table 36
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Parameter
Symbol
Limit Values
min. typ . max.
Unit Test Conditions/
Remarks
1)
Input resistance of RAREF
CC –
1
2
kΩ
the reference input
1)
Input resistance of RAIN
theselectedanalog
channel
CC –
1
3
kΩ
1) Not subjected to production test, verified by design/characterization.
2) This value includes the maximum oscillator deviation.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
4) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.
Data Sheet
99
V1.0, 2010-03
XC858CA
Electrical Parameters
Analog Input Circuitry
REXT
RAIN, On
ANx
VAIN
CEXT
CAINSW
VAGNDx
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFSW
VAGNDx
Figure 33
ADC Input Circuits
Data Sheet
100
V1.0, 2010-03
XC858CA
Electrical Parameters
4.2.3.1 ADC Conversion Timing
Conversion time, tC = tADC × ( 1 + r × (3 + n + STC) ) , where
r = CTC + 2 for CTC = 00B, 01B or 10B,
r = 32 for CTC = 11B,
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
tADC = 1 / fADC
Data Sheet
101
V1.0, 2010-03
XC858CA
Electrical Parameters
4.2.4
Power Supply Current
Table 37 and Table 38 provide the characteristics of the power supply current in the
XC858.
Table 37
Power Supply Current Parameters (Operating Conditions apply;
DDP = 5V range)
V
Parameter
Symbol
Limit Values Unit Test Conditions
typ.1) max.2)
V
DDP = 5V Range
3)
Active Mode
Idle Mode
Active Mode with slow-down
enabled
Idle Mode with slow-down
enabled
IDDP
IDDP
IDDP
37.5
29.2
10
45
35
15
mA
mA
mA
4)
5)
6)
IDDP
9.2
14
mA
1) The typical IDDP values are based on preliminary measurements and are to be used as reference only. These
values are periodically measured at TA = + 25 °C and VDDP = 5.0 V.
2) The maximum IDDP values are measured under worst case conditions (TA = + 85 °C and VDDP = 5.5 V).
3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz with on-
chip oscillator of 4 MHz, RESET = VDDP; all other pins are disconnected, no load on ports.
4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz, RESET = VDDP; all other pins are disconnected, no load on ports.
5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no
load on ports.
6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
clock to all peripherals enabled and running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP
;
all other pins are disconnected, no load on ports.
Data Sheet
102
V1.0, 2010-03
XC858CA
Electrical Parameters
Table 38
Power Down Current (Operating Conditions apply; VDDP = 5V range)
Parameter
Symbol
Limit Values Unit Test Conditions
typ.1) max.2)
V
DDP = 5V Range
Power-Down Mode
IPDP
20
-
60
200
µA TA = + 25 °C3)4)
µA TA = + 85 °C4)5)
1) The typical IPDP values are based on preliminary measurements and are to be used as reference only. These
values are measured at VDDP = 5.0 V.
2) The maximum IPDP values are measured at VDDP = 5.5 V.
3) IPDP has a maximum value of 350 µA at TA = + 85 °C.
4) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be
input with either internal pull devices enabled or driven externally to ensure no floating inputs.
5) Not subjected to production test, verified by design/characterization.
Data Sheet
103
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3
AC Parameters
The electrical characteristics of the AC Parameters are detailed in this section.
4.3.1
Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 34, Figure 35 and Figure 36.
VDDP
90%
90%
10%
10%
VSS
tF
tR
Figure 34
Rise/Fall Time Parameters
VDDP
VDDE / 2
VDDE / 2
Test Points
VSS
Figure 35
Testing Waveform, Output Delay
VLoad + 0.1 V
VLoad - 0.1 V
VOH - 0.1 V
VOL - 0.1 V
Timing
Reference
Points
Figure 36
Testing Waveform, Output High Impedance
Data Sheet
104
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3.2
Output Rise/Fall Times
Table 39 provides the characteristics of the output rise/fall times in the XC858.
Table 39
Output Rise/Fall Times Parameters (Operating Conditions apply)
Parameter
Symbol
Limit
Unit Test Conditions
Values
min. max.
V
DDP = 5V Range
Rise/fall times
tR, tF
–
10
ns
20 pF.1) 2)3)
1) Rise/Fall time measurements are taken with 10% - 90% of pad supply.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF.
V
DDP
90%
90%
10%
10%
V
SS
tF
tR
Figure 37
Rise/Fall Times Parameters
Data Sheet
105
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3.3
Power-on Reset and PLL Timing
Table 40 provides the characteristics of the power-on reset and PLL timing in the
XC858.
Table 40
Power-On Reset and PLL Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
1)
On-Chip Oscillator
start-up time
PLL lock-in in time
tOSCST
tLOCK
CC –
–
500
ns
1)
CC –
–
–
–
200
1.8
µs
ns
1)2)
PLL accumulated jitter DP
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
2) PLL lock at 144 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 72 and P = 1.
VDDP
VPAD
VDDC
tOSCST
OSC
PLL
PLL unlock
tLOCK
PLL lock
3)As Programmed
2)Pull/Input
Pads
1)
Pad state undefined
III) Reset is released
and start of program
I)until EVR is stable II)until PLL is locked
Figure 38
Power-on Reset Timing
Data Sheet
106
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3.4
On-Chip Oscillator Characteristics
Table 41 provides the characteristics of the on-chip oscillator in the XC858.
Table 41
On-chip Oscillator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Nominal frequency
fNOM CC 3.88 4
4.12 MHz under nominal
conditions1) after
IFX-backend trimming
Long term frequency ∆fLT CC -5
–
5
%
%
with respect to fNOM, over
lifetime and temperature
(-40°C to 85°C), for one
given device after
deviation
trimming
Short term frequency ∆fST CC -1.0 –
1.0
with respect to fNOM, over
core supply voltage
(2.5 V ± 7.5%), for one
given device after
trimming
deviation
1) Nominal condition: VDDC = 2.5 V, TA = + 25°C.
Data Sheet
107
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3.5
External Data Memory Characteristics
Table 42 shows the timing of the external data memory read cycle.
Table 42
External Data Memory Read Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
Max.
Unit Test
Conditions
Min.
1)
1)
1)
1)
1)
RD pulse width
Address valid to RD
RD to valid data in
Address to valid data in t4
Data hold after RD
t1
t2
t3
CC 2*fCCLK - 17
CC fCCLK - 12
SR -
SR -
SR 0.5*fCCLK -17 -
-
-
ns
ns
1.5*fCCLK - 27 ns
3*fCCLK - 7
ns
ns
t5
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Addresses
RD
DATA ADDRESS
t1
t2
t3
t5
D[7:0]
VALID
t4
Figure 39
External Data Memory Read Cycle
Data Sheet
108
V1.0, 2010-03
XC858CA
Electrical Parameters
Table 43 shows the timing of the external data memory write cycle.
Table 43
Parameter
External Data Memory Write Timing (Operating Conditions apply)
Symbol Limit Values Unit Test
Conditions
Min.
Max.
1)
1)
1)
1)
1)
WR pulse width
Address valid to WR
Data valid to WR transition t3
Data setup before WR
t1
t2
CC fCCLK - 10
CC 2*fCCLK - 7
SR fCCLK - 5
SR 9*fCCLK - 13
SR 6*fCCLK - 3
-
-
-
-
-
ns
ns
ns
ns
ns
t4
t5
Data hold after WR
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
DATA ADDRESS
Addresses
WR
t2
t1
t3
t5
D[7:0]
VALID
t4
Figure 40
External Data Memory Write Cycle
Data Sheet
109
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3.6
External Clock Drive XTAL1
Table 44 shows the parameters that define the external clock supply for XC858. These
timing parameters are based on the direct XTAL1 drive of clock input signals. They are
not applicable if an external crystal or ceramic resonator is considered.
Table 44
External Clock Drive Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min.
Max.
500
-
-
10
10
1)2)
Oscillator period
High time
tosc
t1
SR 50
SR 15
SR 15
SR -
ns
ns
ns
ns
2)3)
2)3)
Low time
t2
2)3)
Rise time
t3
2)3)
Fall time
t4
SR -
ns
1) The clock input signals with 45-55% duty cycle are used.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3) The clock input signal must reach the defined levels VILX and VIHX
.
t1
t3
t4
VIHX
VILX
0.5 VDDC
t2
tOSC
External Clock Drive XTAL1
Figure 41
Data Sheet
110
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3.7
JTAG Timing
Table 45 provides the characteristics of the JTAG timing in the XC858.
Table 45
TCK Clock Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min max
Unit Test Conditions
1)
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
tTCK SR
50
20
20
-
-
-
-
4
4
ns
ns
ns
ns
1)
t1
t2
t3
t4
SR
SR
SR
SR
1)
1)
1)
-
ns
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
0.9 V DDP
0.5 V DDP
0.1 V DDP
TCK
t1
t2
t4
t3
tTCK
Figure 42
TCK Clock Timing
Table 46
JTAG Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min max
Unit Test Conditions
1)
TMS setup to TCK
TMS hold to TCK
TDI setup to TCK
TDI hold to TCK
t1
t2
t1
t2
SR
SR
SR
SR
CC
8
0
8
4
-
-
ns
1)
-
ns
1)
-
ns
1)
-
ns
1)
TDO valid output from TCK t3
24
ns
Data Sheet
111
V1.0, 2010-03
XC858CA
Electrical Parameters
Table 46
JTAG Timing (Operating Conditions apply; CL = 50 pF) (cont’d)
Parameter
Symbol
Limits
min max
Unit Test Conditions
1)
TDO high impedance to valid t4
CC
CC
-
-
18
ns
output from TCK
1)
TDO valid output to high
impedance from TCK
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
t5
21
ns
TCK
t2
t1
TMS
TDI
t2
t1
t4
t3
t5
TDO
Figure 43
JTAG Timing
Data Sheet
112
V1.0, 2010-03
XC858CA
Electrical Parameters
4.3.8
SSC Master Mode Timing
Table 47 provides the characteristics of the SSC timing in the XC858.
Table 47
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
Unit Test Conditions
min.
2*TSSC
0
max.
–
5
1)2)
SCLK clock period
MTSR delay from SCLK
t0
t1
CC
ns
ns
2)
CC
SR
SR
2)
MRST setup to SCLK
MRST hold from SCLK
t2
t3
13
0
–
–
ns
2)
ns
1) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3ns. TCPU is the CPU clock period.
2) 1Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
MRST1)
valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 44
SSC Master Mode Timing
Data Sheet
113
V1.0, 2010-03
XC858CA
Package and Quality Declaration
5
Package and Quality Declaration
Chapter 5 provides the information of the XC858 package and reliability section.
5.1
Package Parameters
Table 48 provides the thermal characteristics of the PG-LQFP-64-4 package used in
XC858.
Table 48
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Max.
Unit
Notes
Min.
Thermalresistancejunction RTJC CC -
13.8
K/W
K/W
-
-
case1)
Thermalresistancejunction RTJL CC -
34.6
lead1)
1) The thermal resistances between the case and the ambient (RTCA) , the lead and the ambient (RTLA) are to be
combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead
(RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient
(RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA
)
depend on the external system (PCB, case) characteristics, and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ=TA+RTJA × PD, where the RTJA is
the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA
can be obtained from the upper four partial thermal resistances, by
a) simply adding only the two thermal resistances (junction lead and lead ambient), or
b) by taking all four resistances into account, depending on the precision needed.
Data Sheet
114
V1.0, 2010-03
XC858CA
Package and Quality Declaration
5.2
Package Outline
Figure 45 shows the package outlines of the XC858.
Figure 45
PG-LQFP-64-4 Package Outline
Data Sheet
115
V1.0, 2010-03
XC858CA
Package and Quality Declaration
5.3
Quality Declaration
Table 49 shows the characteristics of the quality parameters in the XC858.
Table 49
Parameter
Quality Parameters
Symbol Limit Values
Unit Notes
Min.
Max.
ESD susceptibility
according to Human Body
Model (HBM)
ESD susceptibility
according to Charged
Device Model (CDM) pins
VHBM
-
2000
V
V
Conforming to
EIA/JESD22-
A114-B
VCDM
-
500
Conforming to
JESD22-C101-C
Data Sheet
116
V1.0, 2010-03
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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