SAK-C164CI-L16M3V_技术文档

Data Sheet, V1.0, Jan. 2003

C164CI-3V

Low Power

16-Bit Single-Chip Microcontroller

Preliminary

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2003-01

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

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circuits, descriptions and charts stated herein.

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For further information on technology, delivery terms and conditions and prices please contact your nearest

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Data Sheet, V1.0, Jan. 2003

C164CI-3V

Low Power

16-Bit Single-Chip Microcontroller

Preliminary

Microcontrollers

N e v e r s t o p t h i n k i n g .

C164CI-3V

Preliminary

Revision History:

2003-01

V1.0

Previous Version:

---

Page

Subjects (major changes since last revision)

Controller Area Network (CAN): License of Robert Bosch GmbH

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Preliminary

16-Bit Single-Chip Microcontroller

C166 Family

C164CI-3V

C164CI/SI, C164CL/SL

• High Performance 16-bit CPU with 4-Stage Pipeline

– 125 ns Instruction Cycle Time at 16 MHz CPU Clock

– 625 ns Multiplication (16 × 16 bit), 1250 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 Mbytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 62 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),

via prescaler or via direct clock input

• On-Chip Memory Modules

– 2 Kbytes On-Chip Internal RAM (IRAM)

– 2 Kbytes On-Chip Extension RAM (XRAM)

– up to 64 Kbytes On-Chip Program Mask ROM

• On-Chip Peripheral Modules

– 8-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 µs

– 8-Channel General Purpose Capture/Compare Unit (CAPCOM2)

– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)

– Multi-Functional General Purpose Timer Unit with 3 Timers

– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects

(Full CAN/Basic CAN)

– On-Chip Real Time Clock

• Up to 4 Mbytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Four Optional Programmable Chip-Select Signals

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 59 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

Data Sheet

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C164CI-L16M3V

Low Power

Preliminary

• Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,

Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 80-Pin MQFP Package, 0.65 mm pitch

This document describes several derivatives of the C164 group. Table 1 enumerates

these derivatives and summarizes the differences. As this document refers to all of these

derivatives, some descriptions may not apply to a specific product.

Table 1

C164CI-3V Derivative Synopsis

Derivative¹⁾

Program

Memory

CAPCOM6 CAN Interf. Operating

Frequency

SAK-C164CI-8R16M3V 64 Kbytes ROM Full function CAN1

SAF-C164CI-8R16M3V

16 MHz

SAK-C164SI-8R16M3V 64 Kbytes ROM Full function ---

SAF-C164SI-8R16M3V

16 MHz

SAK-C164CL-8R16M3V 64 Kbytes ROM Reduced fct. CAN1

SAF-C164CL-8R16M3V

SAK-C164SL-8R16M3V 64 Kbytes ROM Reduced fct. ---

SAF-C164SL-8R16M3V

SAK-C164CL-6R16M3V 48 Kbytes ROM Reduced fct. CAN1

SAF-C164CL-6R16M3V

SAK-C164SL-6R16M3V 48 Kbytes ROM Reduced fct. ---

SAF-C164SL-6R16M3V

SAK-C164CI-L16M3V

SAF-C164CI-L16M3V

---

Full function CAN1

1)

This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices

starting with and including design step DA.

For simplicity all versions are referred to by the term C164CI-3V throughout this

document.

Data Sheet

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Low Power

Preliminary

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C164CI-3V please refer to the “Product

Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Introduction

The C164CI-3V derivatives of the Infineon C166 Family of full featured single-chip

CMOS microcontrollers are especially suited for cost sensitive applications. They

combine high CPU performance (up to 8 million instructions per second) with high

peripheral functionality and enhanced IO-capabilities. They also provide clock

generation via PLL and various on-chip memory modules such as program ROM or

OTP, internal RAM, and extension RAM.

V_AREFV_AGNDV_DDV_SS

Port 0

16 Bit

XTAL1

XTAL2

Port 1

16 Bit

RSTIN

Port 3

9 Bit

RSTOUT

NMI

C164CI-3V

Port 4

6 Bit

EA

ALE

RD

Port 8

4 Bit

Port 5

8 Bit

WR/WRL

MCL04869

Figure 1

Logic Symbol

Data Sheet

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Preliminary

Pin Configuration

(top view)

V_AREF

P5.4/AN4/T2EUD

P5.5/AN5/T4EUD

P5.6/AN6/T2IN

V_SS

1

2

3

4

5

6

7

8

9

60

59 P1H.0/A8/CC6POS0/EX0IN

58 P1L.7/A7/CTRAP

57 P1L.6/A6/COUT63

V_SS

56

P5.7/AN7/T4IN

V_SS

55 XTAL1

54 XTAL2

V_DD

P3.4/T3EUD

P3.6/T3IN

P3.8/MRST 10

P3.9/MTSR 11

V_DD

53

52 P1L.5/A5/COUT62

51 P1L.4/A4/CC62

50 P1L.3/A3/COUT61

49 P1L.2/A2/CC61

48 P1L.1/A1/COUT60

47 P1L.0/A0/CC60

46 P0H.7/AD15

C164CI-3V

P3.10/TxD0 12

P3.11/RxD0 13

P3.12/BHE/WRH 14

P3.13/SCLK 15

P3.15/CLKOUT/FOUT 16

P4.0/A16/CS3 17

P4.1/A17/CS2 18

P4.2/A18/CS1 19

45 P0H.6/AD14

44 P0H.5/AD13

43 P0H.4/AD12

42 P0H.3/AD11

V_SS

20

41

MCP04870

Figure 2

*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.

Table 2 on the pages below lists the possible assignments.

The marked input signals are available only in devices with a full-function CAPCOM6.

They are not available in devices with a reduced-function CAPCOM6.

Data Sheet

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Preliminary

Table 2

Pin Definitions and Functions

Symbol Pin

No.

Input Function

Outp.

P5

I

Port 5 is an 8-bit input-only port with Schmitt-Trigger charact.

The pins of Port 5 also serve as analog input channels for the

A/D converter, or they serve as timer inputs:

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

76

77

78

79

2

I

AN0

AN1

AN2

AN3

AN4,

AN5,

AN6,

T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.

3

4

T2IN

GPT1 Timer T2 Input for

Count/Gate/Reload/Capture

GPT1 Timer T4 Input for

Count/Gate/Reload/Capture

P5.7

5

I

AN7,

T4IN

P3

IO

Port 3 is a 9-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 3 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or special).

The following Port 3 pins also serve for alternate functions:

P3.4

P3.6

8

9

I

T3EUD

T3IN

GPT1 Timer T3 External Up/Down Control Input

GPT1 Timer T3 Count/Gate Input

P3.8

P3.9

P3.10

P3.11

P3.12

10

11

12

13

14

I/O

O

I/O

O

I/O

O

MRST

MTSR

TxD0

RxD0

BHE

SSC Master-Receive/Slave-Transmit Inp./Outp.

SSC Master-Transmit/Slave-Receive Outp./Inp.

ASC0 Clock/Data Output (Async./Sync.)

ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe

SSC Master Clock Output / Slave Clock Input.

WRH

SCLK

P3.13

P3.15

15

16

CLKOUT System Clock Output (= CPU Clock),

FOUT Programmable Frequency Output

O

Data Sheet

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Preliminary

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

P4

IO

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 4 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 4 is

selectable (TTL or special).

Port 4 can be used to output the segment address lines, the

optional chip select lines, and for serial interface lines:¹⁾

P4.0

P4.1

P4.2

P4.3

P4.5

P4.6

17

18

19

22

23

24

O

I

A16

CS3

A17

CS2

A18

CS1

A19

CS0

A20

Least Significant Segment Address Line,

Chip Select 3 Output

Segment Address Line,

Chip Select 2 Output

Segment Address Line,

Chip Select 1 Output

Segment Address Line,

Chip Select 0 Output

Segment Address Line,

CAN1_RxD CAN 1 Receive Data Input

A21

CAN1_TxD CAN 1 Transmit Data Output

O

Most Significant Segment Address Line,

RD

25

26

O

External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR/

WRL

O

External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL-mode

this pin is activated for low byte data write accesses on a

16-bit bus, and for every data write access on an 8-bit bus.

See WRCFG in register SYSCON for mode selection.

ALE

27

O

Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the

multiplexed bus modes.

Data Sheet

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Preliminary

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

EA

28

I

External Access Enable pin.

A low level at this pin during and after Reset forces the

C164CI-3V to latch the configuration from PORT0 and pin

RD, and to begin instruction execution out of external

memory.

A high level forces the C164CI-3V to latch the configuration

from pins RD and ALE, and to begin instruction execution out

of the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

PORT0

P0L.0-7 29-

36

P0H.0-7 37-39,

42-46

IO

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state.

In case of an external bus configuration, PORT0 serves as

the address (A) and address/data (AD) bus in multiplexed

bus modes and as the data (D) bus in demultiplexed bus

modes.

Demultiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

D0 – D7

I/O

16-bit

D0 – D7

D8 – D15

Multiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

16-bit

AD0 – AD7 AD0 – AD7

A8 – A15 AD8 – AD15

Data Sheet

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Preliminary

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

PORT1

P1L.0-7 47-52,

57-59

P1H.0-7 59,

62-68

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state. PORT1 is used as the

16-bit address bus (A) in demultiplexed bus modes and also

after switching from a demultiplexed bus mode to a

multiplexed bus mode.

The following PORT1 pins also serve for alt. functions:

P1L.0

P1L.1

P1L.2

P1L.3

P1L.4

P1L.5

P1L.6

P1L.7

47

48

49

50

51

52

57

58

I/O

O

I/O

O

I/O

O

CC60

COUT60 CAPCOM6: Output of Channel 0

CC61 CAPCOM6: Input / Output of Channel 1

COUT61 CAPCOM6: Output of Channel 1

CC62 CAPCOM6: Input / Output of Channel 2

CAPCOM6: Input / Output of Channel 0

COUT62 CAPCOM6: Output of Channel 2

COUT63 Output of 10-bit Compare Channel

I

CTRAP

CAPCOM6: Trap Input

CTRAP is an input pin with an internal pullup resistor. A low

level on this pin switches the compare outputs of the

CAPCOM6 unit to the logic level defined by software.

CC6POS0 CAPCOM6: Position 0 Input, **)

P1H.0 59

P1H.1 62

P1H.2 63

P1H.3 64

I

EX0IN

CC6POS1 CAPCOM6: Position 1 Input, **)

EX1IN Fast External Interrupt 1 Input

CC6POS2 CAPCOM6: Position 2 Input, **)

Fast External Interrupt 0 Input

EX2IN

Fast External Interrupt 2 Input

EX3IN

Fast External Interrupt 3 Input,

T7IN

CAPCOM2: Timer T7 Count Input

P1H.4 65

P1H.5 66

P1H.6 67

P1H.7 68

I/O

CC24IO

CC25IO

CC26IO

CC27IO

CAPCOM2: CC24 Capture Inp./Compare Outp.

CAPCOM2: CC25 Capture Inp./Compare Outp.

CAPCOM2: CC26 Capture Inp./Compare Outp.

CAPCOM2: CC27 Capture Inp./Compare Outp.

Note: The marked (**) input signals are available only in

devices with a full function CAPCOM6.

Data Sheet

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Preliminary

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

XTAL2 54

XTAL1 55

O

I

XTAL2:

XTAL1:

Output of the oscillator amplifier circuit.

Input to the oscillator amplifier and input to

the internal clock generator

To clock the device from an external source, drive XTAL1,

while leaving XTAL2 unconnected. Minimum and maximum

high/low and rise/fall times specified in the AC

Characteristics must be observed.

RSTIN 69

I/O

Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C164CI-

3V. An internal pullup resistor permits power-on reset using

only a capacitor connected to V_SS.

A spike filter suppresses input pulses <10 ns. Input pulses

>100 ns safely pass the filter. The minimum duration for a

safe recognition should be 100 ns + 2 CPU clock cycles.

In bidirectional reset mode (enabled by setting bit BDRSTEN

in register SYSCON) the RSTIN line is internally pulled low

for the duration of the internal reset sequence upon any reset

(HW, SW, WDT). See note below this table.

RST

OUT

70

71

O

I

Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or

a watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the C164CI-3V to go into

power down mode. If NMI is high, when PWRDN is

executed, the part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

Data Sheet

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Preliminary

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input Function

Outp.

P8

IO

Port 8 is a 4-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 8 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 8 is

selectable (TTL or special). Port 8 pins provide inputs/

outputs for CAPCOM2 and serial interface lines.¹⁾

P8.0

P8.1

P8.2

P8.3

72

73

74

75

I/O

I

I/O

O

I/O

I

I/O

O

CC16IO

CAPCOM2: CC16 Capture Inp./Compare Outp.,

CAN1_RxD CAN 1 Receive Data Input

CC17IO

CAN1_TxD CAN 1 Transmit Data Output

CC18IO

CAN1_RxD CAN 1 Receive Data Input

CC19IO

CAN1_TxD CAN 1 Transmit Data Output

CAPCOM2: CC17 Capture Inp./Compare Outp.,

CAPCOM2: CC18 Capture Inp./Compare Outp.,

CAPCOM2: CC19 Capture Inp./Compare Outp.,

V_AREF

1

–

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

V_AGND80

V_DD

7, 21,

Digital Supply Voltage:

40, 53,

61

+3.3 V during normal operation and idle mode.

≥2.5 V during power down mode.

V_SS

6, 20,

41, 56,

60

–

Digital Ground.

1)

The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module

several assignments can be selected.

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared

automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the

bootstrap loader may be activated when P0L.4 is low.

• Pin RSTIN may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet

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Preliminary

Functional Description

The architecture of the C164CI-3V combines advantages of both RISC and CISC

processors and of advanced peripheral subsystems in a very well-balanced way. In

addition the on-chip memory blocks allow the design of compact systems with maximum

performance.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the C164CI-3V.

Note: All time specifications refer to a CPU clock of 16 MHz

(see definition in the AC Characteristics section).

C166-Core

ProgMem

IRAM

Internal

RAM

16

Data

32

16

ROM: 48/64

OTP: 64

KByte

Instr. / Data

CPU

2 KByte

Osc / PLL

XTAL

XRAM

2 KByte

PEC

External Instr. / Data

16-Level

Priority

Interrupt Controller

RTC WDT

16

Interrupt Bus

Peripheral Data Bus

16

CAN

Rev 2.0B active

ADC ASC0 SSC GPT1

CCOM2CCOM6

10-Bit

(USART)

(SPI)

T2

T3

T4

T7

T8

T12

T13

8

EBC

Channels

XBUS Control

External Bus

Control

6

16

BRGen

Port 0

16

Port 5

Port 3

Port 8

4

8

9

MCB04323_4ci

Figure 3

Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are

connected to the CPU via separate buses. A fourth bus, the XBUS, connects external

resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).

The XBUS resources (XRAM, CAN) of the C164CI-3V can be enabled or disabled during

initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules

that are disabled consume neither address space nor port pins.

Data Sheet

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Preliminary

Memory Organization

The memory space of the C164CI-3V is configured in a Von Neumann architecture

which means that code memory, data memory, registers and I/O ports are organized

within the same linear address space which includes 16 Mbytes. The entire memory

space can be accessed bytewise or wordwise. Particular portions of the on-chip memory

have additionally been made directly bitaddressable.

The C164CI-3V incorporates 64/48 Kbytes of on-chip mask-programmable ROM (not in

the ROM-less derivative, of course) for code or constant data. The lower 32 Kbytes of

the on-chip ROM can be mapped either to segment 0 or segment 1.

2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined

variables, for the system stack, general purpose register banks and even for code. A

register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,

…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the C166 Family.

2 Kbytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks,

or code. The XRAM is accessed like external memory and therefore cannot be used for

the system stack or for register banks and is not bitaddressable. The XRAM permits 16-

bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 4 Mbytes of external RAM and/or ROM can be connected to the

microcontroller.

Data Sheet

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Preliminary

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus

Controller (EBC). It can be programmed either to Single Chip Mode when no external

memory is required, or to one of four different external memory access modes, which are

as follows:

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/

output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses

and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,

Memory Tri-State Time, Length of ALE and Read Write Delay) have been made

programmable to allow the user the adaption of a wide range of different types of

memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs

ADDRSELx / BUSCONx) which control the access to different resources with different

bus characteristics. These address windows are arranged hierarchically where

BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to

locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 4 external CS signals (3 windows plus default) can be generated in order to save

external glue logic. The C164CI-3V offers the possibility to switch the CS outputs to an

unlatched mode. In this mode the internal filter logic is switched off and the CS signals

are directly generated from the address. The unlatched CS mode is enabled by setting

CSCFG (SYSCON.6).

For applications which require less than 4 Mbytes of external memory space, this

address space can be restricted to 1 Mbyte, 256 Kbyte, or to 64 Kbyte. In this case

Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an

address space of 4 Mbytes is used.

Note: When the on-chip CAN Module is used with the interface lines assigned to Port 4,

the CAN lines override the segment address lines and the segment address

output on Port 4 is therefore limited to 4 bits i.e. address lines A19 … A16.

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Preliminary

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic

and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a

separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C164CI-3V’s instructions can be

executed in just one machine cycle which requires 2 CPU clocks (4 TCL). For example,

shift and rotate instructions are always processed during one machine cycle

independent of the number of bits to be shifted. All multiple-cycle instructions have been

optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16

bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline

optimization, the so-called ‘Jump Cache’, reduces the execution time of repeatedly

performed jumps in a loop from 2 cycles to 1 cycle.

Figure 4

CPU Block Diagram

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The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.

These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer

(CP) register determines the base address of the active register bank to be accessed by

the CPU at any time. The number of register banks is only restricted by the available

internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The

system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the

stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly

compared against the stack pointer value upon each stack access for the detection of a

stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently

be utilized by a programmer via the highly efficient C164CI-3V instruction set which

includes the following instruction classes:

– Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes

and words. A variety of direct, indirect or immediate addressing modes are provided to

specify the required operands.

Data Sheet

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Preliminary

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of

internal program execution), the C164CI-3V is capable of reacting very fast to the

occurrence of non-deterministic events.

The architecture of the C164CI-3V supports several mechanisms for fast and flexible

response to service requests that can be generated from various sources internal or

external to the microcontroller. Any of these interrupt requests can be programmed to

being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is

suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a

single byte or word data transfer between any two memory locations with an additional

increment of either the PEC source or the destination pointer. An individual PEC transfer

counter is implicity decremented for each PEC service except when performing in the

continuous transfer mode. When this counter reaches zero, a standard interrupt is

performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data.

The C164CI-3V has 8 PEC channels each of which offers such fast interrupt-driven data

transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable

flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via

its related register, each source can be programmed to one of sixteen interrupt priority

levels. Once having been accepted by the CPU, an interrupt service can only be

interrupted by a higher prioritized service request. For the standard interrupt processing,

each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high

precision requirements. These fast interrupt inputs feature programmable edge

detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with

an individual trap (interrupt) number.

Table 3 shows all of the possible C164CI-3V interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt

request bit (xIR).

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Table 3

C164CI-3V Interrupt Nodes

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Trap

Vector

Location Number

Fast External Interrupt 0 CC8IR

Fast External Interrupt 1 CC9IR

Fast External Interrupt 2 CC10IR

Fast External Interrupt 3 CC11IR

CC8IE

CC9IE

CC10IE

CC11IE

T2IE

CC8INT

CC9INT

00’0060_H18_H

00’0064_H19_H

CC10INT 00’0068_H1A_H

CC11INT 00’006C_H1B_H

GPT1 Timer 2

GPT1 Timer 3

GPT1 Timer 4

T2IR

T2INT

T3INT

T4INT

ADCINT

00’0088_H22_H

00’008C_H23_H

00’0090_H24_H

00’00A0_H28_H

T3IR

T3IE

T4IR

T4IE

A/D Conversion

Complete

ADCIR

ADCIE

A/D Overrun Error

ASC0 Transmit

ADEIR

S0TIR

ADEIE

S0TIE

ADEINT

S0TINT

00’00A4_H29_H

00’00A8_H2A_H

ASC0 Transmit Buffer S0TBIR

S0TBIE

S0RIE

S0EIE

SCTIE

SCRIE

SCEIE

CC16IE

CC17IE

CC18IE

CC19IE

CC24IE

CC25IE

CC26IE

CC27IE

T7IE

S0TBINT 00’011C_H47_H

ASC0 Receive

ASC0 Error

S0RIR

S0EIR

SCTIR

SCRIR

SCEIR

S0RINT

S0EINT

SCTINT

SCRINT

SCEINT

00’00AC_H2B_H

00’00B0_H2C_H

00’00B4_H2D_H

00’00B8_H2E_H

00’00BC_H2F_H

SSC Transmit

SSC Receive

SSC Error

CAPCOM Register 16 CC16IR

CAPCOM Register 17 CC17IR

CAPCOM Register 18 CC18IR

CAPCOM Register 19 CC19IR

CAPCOM Register 24 CC24IR

CAPCOM Register 25 CC25IR

CAPCOM Register 26 CC26IR

CAPCOM Register 27 CC27IR

CC16INT 00’00C0_H30_H

CC17INT 00’00C4_H31_H

CC18INT 00’00C8_H32_H

CC19INT 00’00CC_H33_H

CC24INT 00’00E0_H38_H

CC25INT 00’00E4_H39_H

CC26INT 00’00E8_H3A_H

CC27INT 00’00EC_H3B_H

CAPCOM Timer 7

CAPCOM Timer 8

CAPCOM6 Interrupt

CAN Interface 1

T7IR

T7INT

00’00F4_H3D_H

00’00F8_H3E_H

00’00FC_H3F_H

00’0100_H40_H

00’010C_H43_H

T8IR

T8IE

T8INT

CC6IR

XP0IR

XP3IR

CC6IE

XP0IE

XP3IE

CC6INT

XP0INT

XP3INT

PLL/OWD and RTC

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Table 3

C164CI-3V Interrupt Nodes (cont’d)

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Trap

Vector

T12INT

T13INT

Location Number

CAPCOM 6 Timer 12

CAPCOM 6 Timer 13

T12IR

T13IR

T12IE

00’0134_H4D_H

00’0138_H4E_H

T13IE

CAPCOM 6 Emergency CC6EIR

CC6EIE

CC6EINT 00’013C_H4F_H

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The C164CI-3V also provides an excellent mechanism to identify and to process

exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.

Hardware traps cause immediate non-maskable system reaction which is similar to a

standard interrupt service (branching to a dedicated vector table location). The

occurence of a hardware trap is additionally signified by an individual bit in the trap flag

register (TFR). Except when another higher prioritized trap service is in progress, a

hardware trap will interrupt any actual program execution. In turn, hardware trap services

can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

–

– Hardware Reset

– Software Reset

– W-dog Timer Overflow

RESET

00’0000_H

00_H

III

Class A Hardware Traps:

– Non-Maskable Interrupt NMI

NMITRAP 00’0008_H

STOTRAP 00’0010_H

STUTRAP 00’0018_H

02_H

04_H

06_H

II

– Stack Overflow

– Stack Underflow

STKOF

STKUF

Class B Hardware Traps:

– Undefined Opcode

– Protected Instruction

Fault

UNDOPC BTRAP

PRTFLT BTRAP

00’0028_H

0A_H

I

– Illegal Word Operand

Access

– Illegal Instruction

Access

– Illegal External Bus

Access

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028_H

0A_H

I

Reserved

–

[2C_H–

3C_H]

[0B_H–

0F_H]

–

Software Traps

– TRAP Instruction

Any

Current

CPU

Priority

[00’0000_H– [00_H–

00’01FC_H] 7F_H]

in steps

of 4_H

Data Sheet

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The Capture/Compare Unit CAPCOM2

The general purpose CAPCOM2 unit supports generation and control of timing

sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM

units are typically used to handle high speed I/O tasks such as pulse and waveform

generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software

timing, or time recording relative to external events.

Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for

the capture/compare register array.

Each dual purpose capture/compare register, which may be individually allocated to

either CAPCOM timer and programmed for capture or compare function, has one port

pin associated with it which serves as an input pin for triggering the capture function, or

as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current

contents of the allocated timer will be latched (‘capture’d) into the capture/compare

register in response to an external event at the port pin which is associated with this

register. In addition, a specific interrupt request for this capture/compare register is

generated. Either a positive, a negative, or both a positive and a negative external signal

transition at the pin can be selected as the triggering event. The contents of all registers

which have been selected for one of the five compare modes are continuously compared

with the contents of the allocated timers. When a match occurs between the timer value

and the value in a capture/compare register, specific actions will be taken based on the

selected compare mode.

Table 5

Compare Modes (CAPCOM2)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1

Mode 2

Mode 3

Pin toggles on each compare match;

several compare events per timer period are possible

Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double

Register Mode

Two registers operate on one pin; pin toggles on each compare

match;

several compare events per timer period are possible.

Registers CC16 & CC24 ➞ pin CC16IO

Registers CC17 & CC25 ➞ pin CC17IO

Registers CC18 & CC26 ➞ pin CC18IO

Registers CC19 & CC27 ➞ pin CC19IO

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The Capture/Compare Unit CAPCOM6

The CAPCOM6 unit supports generation and control of timing sequences on up to three

16-bit capture/compare channels plus one 10-bit compare channel.

In compare mode the CAPCOM6 unit provides two output signals per channel which

have inverted polarity and non-overlapping pulse transitions. The compare channel can

generate a single PWM output signal and is further used to modulate the capture/

compare output signals.

In capture mode the contents of compare timer 12 is stored in the capture registers upon

a signal transition at pins CCx.

Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked

by the prescaled CPU clock.

Mode

Select Register

CC6MSEL

Period Register

Trap Register

CTRAP

T12P

CC60

COUT60

Offset Register

T12OF

CC Channel 0

CC60

f_CPU

CC61

COUT61

CC Channel 1

CC61

Port

Control

Logic

Compare

Timer T12

16-Bit

CC62

COUT62

CC Channel 2

CC62

Control Register

CTCON

Compare

Timer T13

10-Bit

f_CPU

Compare Register

CMP13

COUT63

Block

Commutation

Control

CC6POS0

CC6POS1

CC6POS2

Period Register

T13P

CC6MCON.H

MCB04109

The timer registers (T12, T13) are not directly accessible.

The period and offset registers are loading a value into the timer registers.

The shaded blocks are available in the full function module only.

Figure 5

CAPCOM6 Block Diagram

For motor control applications both subunits may generate versatile multichannel PWM

signals which are basically either controlled by compare timer 12 or by a typical hall

sensor pattern at the interrupt inputs (block commutation).

Note: Multichannel signal generation is provided only in devices with a full CAPCOM6.

Data Sheet

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General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which

may be used for many different time related tasks such as event timing and counting,

pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates three 16-bit timers. Each timer may operate independently in

a number of different modes, or may be concatenated with another timer.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for

one of four basic modes of operation, which are Timer, Gated Timer, Counter, and

Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from

the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer

to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the

operation of a timer is controlled by the ‘gate’ level on an external input pin. For these

purposes, each timer has one associated port pin (TxIN) which serves as gate or clock

input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD) to

facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected

to the incremental position sensor signals A and B via their respective inputs TxIN and

TxEUD. Direction and count signals are internally derived from these two input signals,

so the contents of the respective timer Tx corresponds to the sensor position. The third

position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-

flow/underflow. The state of this latch may be used internally to clock timers T2 and T4

for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload

or capture registers for timer T3. When used as capture or reload registers, timers T2

and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a

signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2

or T4 triggered either by an external signal or by a selectable state transition of its toggle

latch T3OTL.

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T2EUD

U/D

Interrupt

Request

(T2IR)

2ⁿ: 1

GPT1 Timer T2

f_CPU

T2IN

T2

Mode

Control

Reload

Capture

Interrupt

Request

(T3IR)

f_CPU

2ⁿ: 1

Toggle FF

T3OTL

T3

Mode

Control

T3IN

GPT1 Timer T3

U/D

T3EUD

Other

Timers

Capture

Reload

T4IN

T4

Mode

Control

Interrupt

Request

(T4IR)

2ⁿ: 1

GPT1 Timer T4

U/D

f_CPU

T4EUD

MCT04825_4

n = 3 … 10

Figure 6

Block Diagram of GPT1

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Real Time Clock

The Real Time Clock (RTC) module of the C164CI-3V consists of a chain of 3 divider

blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer

(accessible via registers RTCH and RTCL). The RTC module is directly clocked with the

on-chip oscillator frequency divided by 32 via a separate clock driver (f_RTC= f_OSC/32)

and is therefore independent from the selected clock generation mode of the C164CI-

3V. All timers count up.

The RTC module can be used for different purposes:

• System clock to determine the current time and date

• Cyclic time based interrupt

• 48-bit timer for long term measurements

T14REL

Reload

f_RTC

T14

8:1

Interrupt

Request

RTCH

RTCL

MCD04432

Figure 7

RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

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A/D Converter

For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels

and a sample and hold circuit has been integrated on-chip. It uses the method of

successive approximation. The sample time (for loading the capacitors) and the

conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register

(ADDAT): either an interrupt request will be generated when the result of a previous

conversion has not been read from the result register at the time the next conversion is

complete, or the next conversion is suspended in such a case until the previous result

has been read.

For applications which require less than 8 analog input channels, the remaining channel

inputs can be used as digital input port pins.

The A/D converter of the C164CI-3V supports four different conversion modes. In the

standard Single Channel conversion mode, the analog level on a specified channel is

sampled once and converted to a digital result. In the Single Channel Continuous mode,

the analog level on a specified channel is repeatedly sampled and converted without

software intervention. In the Auto Scan mode, the analog levels on a prespecified

number of channels (standard or extension) are sequentially sampled and converted. In

the Auto Scan Continuous mode, the number of prespecified channels is repeatedly

sampled and converted. In addition, the conversion of a specific channel can be inserted

(injected) into a running sequence without disturbing this sequence. This is called

Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the

conversion results into a table in memory for later evaluation, without requiring the

overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs

calibration cycles. This automatic self-calibration constantly adjusts the converter to

changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal

operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise

those pins used for analog input can be disconnected from the digital IO or input stages

under software control. This can be selected for each pin separately via register P5DIDIS

(Port 5 Digital Input Disable).

Data Sheet

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Serial Channels

Serial communication with other microcontrollers, processors, terminals or external

peripheral components is provided by two serial interfaces with different functionality, an

Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous

Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller

families and supports full-duplex asynchronous communication at up to 500 Kbit/s and

half-duplex synchronous communication at up to 2.0 Mbit/s (@ 16 MHz CPU clock).

A dedicated baud rate generator allows to set up all standard baud rates without

oscillator tuning. For transmission, reception and error handling 4 separate interrupt

vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or

received, preceded by a start bit and terminated by one or two stop bits. For

multiprocessor communication, a mechanism to distinguish address from data bytes has

been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a

shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop

back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated, if the last

character received has not been read out of the receive buffer register at the time the

reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 4.0 Mbit/s

(@ 16 MHz CPU clock). It may be configured so it interfaces with serially linked

peripheral components. A dedicated baud rate generator allows to set up all standard

baud rates without oscillator tuning. For transmission, reception and error handling

3 separate interrupt vectors are provided.

The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift

clock which can be generated by the SSC (master mode) or by an external master (slave

mode). The SSC can start shifting with the LSB or with the MSB and allows the selection

of shifting and latching clock edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. Transmit and receive error supervise the correct handling

of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet

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CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and

reception of CAN frames in accordance with the CAN specification V2.0 part B (active),

i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit

identifiers as well as extended frames with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message

object 15 may be configured for Basic CAN functionality. Both modes provide separate

masks for acceptance filtering which allows to accept a number of identifiers in Full CAN

mode and also allows to disregard a number of identifiers in Basic CAN mode. All

message objects can be updated independent from the other objects and are equipped

for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/

s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus

transceiver. The interface pins are assigned via software.

Note: When the CAN interface is assigned to Port 4, the respective segment address

lines on Port 4 cannot be used. This will limit the external address space.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be

disabled in the time interval until the EINIT (end of initialization) instruction has been

executed. Thus, the chip’s start-up procedure is always monitored. The software has to

be designed to service the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/

256. The high byte of the Watchdog Timer register can be set to a prespecified reload

value (stored in WDTREL) in order to allow further variation of the monitored time

interval. Each time it is serviced by the application software, the high byte of the

Watchdog Timer is reloaded. Thus, time intervals between 32 µs and 1049 ms can be

monitored (@ 16 MHz).

The default Watchdog Timer interval after reset is 8.2 ms (@ 16 MHz).

Data Sheet

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Parallel Ports

The C164CI-3V provides up to 59 I/O lines which are organized into five input/output

ports and one input port. All port lines are bit-addressable, and all input/output lines are

individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O

ports are true bidirectional ports which are switched to high impedance state when

configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)

for push/pull operation or open-drain operation via control registers. During the internal

reset, all port pins are configured as inputs.

The input threshold of Port 3, Port 4, and Port 8 is selectable (TTL or CMOS like), where

the special CMOS like input threshold reduces noise sensitivity due to the input

hysteresis. The input threshold may be selected individually for each byte of the

respective ports.

All port lines have programmable alternate input or output functions associated with

them. All port lines that are not used for these alternate functions may be used as general

purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external

memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 and

the optional chip select signals in systems where segmentation is enabled to access

more than 64 Kbytes of memory.

Ports P1L, P1H, and P8 are associated with the capture inputs or compare outputs of

the CAPCOM units and/or serve as external interrupt inputs.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control

signal BHE/WRH, and the system clock output CLKOUT (or the programmable

frequency output FOUT).

Port 5 is used for the analog input channels to the A/D converter or timer control signals.

The edge characteristics (transition time) and driver characteristics (output current) of

the C164CI-3V’s port drivers can be selected via the Port Output Control registers

(POCONx).

Data Sheet

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Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip

oscillator (either with a crystal or via external clock drive). For this operation the PLL

provides a clock signal which is used to supervise transitions on the oscillator clock. This

PLL clock is independent from the XTAL1 clock. When the expected oscillator clock

transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and

supplies the CPU with the PLL clock signal. Under these circumstances the PLL will

oscillate with its basic frequency.

In direct drive mode the PLL base frequency is used directly (f_CPU= 2 … 5 MHz).

In prescaler mode the PLL base frequency is divided by 2 (f_CPU= 1 … 2.5 MHz).

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.

In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the

CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also

no interrupt request will be generated in case of a missing oscillator clock.

Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.

Thus the oscillator watchdog may also be disabled via hardware by (externally)

pulling the RD line low upon a reset, similar to the standard reset configuration via

PORT0.

Data Sheet

29

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Power Management

The C164CI-3V provides several means to control the power it consumes either at a

given time or averaged over a certain timespan. Three mechanisms can be used (partly

in parallel):

• Power Saving Modes switch the C164CI-3V into a special operating mode (control

via instructions).

Idle Mode stops the CPU while the peripherals can continue to operate.

Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may

optionally continue running). Sleep Mode can be terminated by external interrupt

signals.

• Clock Generation Management controls the distribution and the frequency of

internal and external clock signals (control via register SYSCON2).

Slow Down Mode lets the C164CI-3V run at a CPU clock frequency of f_OSC/1 … 32

(half for prescaler operation) which drastically reduces the consumed power. The PLL

can be optionally disabled while operating in Slow Down Mode.

External circuitry can be controlled via the programmable frequency output FOUT.

• Peripheral Management permits temporary disabling of peripheral modules (control

via register SYSCON3).

Each peripheral can separately be disabled/enabled. A group control option disables

a major part of the peripheral set by setting one single bit.

The on-chip RTC supports intermittend operation of the C164CI-3V by generating cyclic

wakeup signals. This offers full performance to quickly react on action requests while the

intermittend sleep phases greatly reduce the average power consumption of the system.

Data Sheet

30

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Instruction Set Summary

Table 6 lists the instructions of the C164CI-3V in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation

of the instructions, parameters for conditional execution of instructions, and the opcodes

for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailled description of each instruction.

Table 6

Mnemonic

ADD(B)

ADDC(B)

SUB(B)

SUBC(B)

MUL(U)

DIV(U)

Instruction Set Summary

Description

Bytes

2 / 4

2

Add word (byte) operands

Add word (byte) operands with Carry

Subtract word (byte) operands

Subtract word (byte) operands with Carry

(Un)Signed multiply direct GPR by direct GPR (16-16-bit)

(Un)Signed divide register MDL by direct GPR (16-/16-bit)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)

Complement direct word (byte) GPR

Negate direct word (byte) GPR

2

DIVL(U)

CPL(B)

NEG(B)

AND(B)

OR(B)

2

Bitwise AND, (word/byte operands)

Bitwise OR, (word/byte operands)

Bitwise XOR, (word/byte operands)

Clear direct bit

2 / 4

2

XOR(B)

BCLR

BSET

Set direct bit

2

BMOV(N)

Move (negated) direct bit to direct bit

AND/OR/XOR direct bit with direct bit

4

BAND, BOR,

BXOR

4

BCMP

Compare direct bit to direct bit

4

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

Compare word (byte) operands

2 / 4

2

Compare word data to GPR and decrement GPR by 1/2

Compare word data to GPR and increment GPR by 1/2

Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR

SHL / SHR

ROL / ROR

ASHR

Shift left/right direct word GPR

2

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

Data Sheet

31

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Table 6

Instruction Set Summary (cont’d)

Description

Mnemonic

MOV(B)

MOVBS

MOVBZ

Bytes

Move word (byte) data

2 / 4

Move byte operand to word operand with sign extension

Move byte operand to word operand with zero extension

Jump absolute/indirect/relative if condition is met

2 / 4

4

JMPA, JMPI,

JMPR

JMPS

J(N)B

JBC

Jump absolute to a code segment

4

Jump relative if direct bit is (not) set

Jump relative and clear bit if direct bit is set

Jump relative and set bit if direct bit is not set

JNBS

CALLA, CALLI, Call absolute/indirect/relative subroutine if condition is met

CALLR

CALLS

PCALL

Call absolute subroutine in any code segment

4

Push direct word register onto system stack and call

absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

Push/pop direct word register onto/from system stack

2

4

PUSH, POP

SCXT

Push direct word register onto system stack und update

register with word operand

RET

Return from intra-segment subroutine

Return from inter-segment subroutine

2

RETS

RETP

Return from intra-segment subroutine and pop direct

word register from system stack

RETI

Return from interrupt service subroutine

Software Reset

2

SRST

4

IDLE

Enter Idle Mode

4

PWRDN

SRVWDT

DISWDT

EINIT

Enter Power Down Mode (supposes NMI-pin being low)

Service Watchdog Timer

4

Disable Watchdog Timer

4

Signify End-of-Initialization on RSTOUT-pin

Begin ATOMIC sequence

4

ATOMIC

EXTR

2

Begin EXTended Register sequence

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

Null operation

2

EXTP(R)

EXTS(R)

NOP

2 / 4

2

Data Sheet

32

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Special Function Registers Overview

Table 7 lists all SFRs which are implemented in the C164CI-3V in alphabetical order.

The following markings assist in classifying the listed registers:

“b” in the “Name” column marks Bit-addressable SFRs.

“E” in the “Physical Address” column marks (E)SFRs within the Extended SFR-Space.

“X” in the “Physical Address” column marks registers within the on-chip X-peripherals.

“m” in the “Physical Address” column marks SFRs without short 8-bit address.

An SFR can be specified via its individual mnemonic name. Depending on the selected

addressing mode, an SFR can be accessed via its physical address (using the Data

Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Table 7

Name

C164CI-3V Registers, Ordered by Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

ADCIC

b FF98_H

CC_HA/D Converter End of Conversion

Interrupt Control Register

0000_H

ADCON

b FFA0_H

D0_H

50_H

A/D Converter Control Register

A/D Converter Result Register

A/D Converter 2 Result Register

Address Select Register 1

Address Select Register 2

Address Select Register 3

Address Select Register 4

0000_H

ADDAT

FEA0_H

ADDAT2

F0A0_HE 50_H

ADDRSEL1

ADDRSEL2

ADDRSEL3

ADDRSEL4

ADEIC

FE18_H

FE1A_H

0C_H

0D_H

0E_H

0F_H

FE1C_H

FE1E_H

b FF9A_H

CD_HA/D Converter Overrun Error Interrupt

Control Register

BUSCON0 b FF0C_H

BUSCON1 b FF14_H

BUSCON2 b FF16_H

BUSCON3 b FF18_H

BUSCON4 b FF1A_H

86_H

8A_H

8B_H

8C_H

8D_H

Bus Configuration Register 0

Bus Configuration Register 1

Bus Configuration Register 2

Bus Configuration Register 3

Bus Configuration Register 4

CAN1 Bit Timing Register

CAN1 Control / Status Register

CAN1 Global Mask Short

0000_H

UUUU_H

XX01_H

UFUU_H

C1BTR

EF04_HX ---

EF00_HX ---

C1CSR

C1GMS

C1LARn

C1LGML

EF06_HX ---

EFn4_HX ---

EF0A_HX ---

CAN Lower Arbitration Register (msg. n) UUUU_H

CAN Lower Global Mask Long

UUUU_H

Data Sheet

33

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Table 7

Name

C164CI-3V Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

C1LMLM

EF0E_HX ---

EFn6_HX ---

CAN Lower Mask of Last Message

UUUU_H

UU_H

C1MCFGn

CAN Message Configuration Register

(msg. n)

C1MCRn

C1PCIR

C1UARn

C1UGML

C1UMLM

CC10IC

CC11IC

CC16

EFn0_HX ---

EF02_HX ---

EFn2_HX ---

EF08_HX ---

EF0C_HX ---

CAN Message Control Register (msg. n) UUUU_H

CAN1 Port Control / Interrupt Register XXXX_H

CAN Upper Arbitration Register (msg. n) UUUU_H

CAN Upper Global Mask Long

CAN Upper Mask of Last Message

External Interrupt 2 Control Register

External Interrupt 3 Control Register

CAPCOM Register 16

UUUU_H

0000_H

b FF8C_H

C6_H

C7_H

30_H

b FF8E_H

FE60_H

CC16IC

CC17

b F160_HE B0_H

FE62_H31_H

b F162_HE B1_H

FE64_H32_H

b F164_HE B2_H

FE66_H33_H

b F166_HE B3_H

CAPCOM Reg. 16 Interrupt Ctrl. Reg.

CAPCOM Register 17

CC17IC

CC18

CAPCOM Reg. 17 Interrupt Ctrl. Reg.

CAPCOM Register 18

CC18IC

CC19

CAPCOM Reg. 18 Interrupt Ctrl. Reg.

CAPCOM Register 19

CC19IC

CC20

CAPCOM Reg. 19 Interrupt Ctrl. Reg.

CAPCOM Register 20

FE68_H

FE6A_H

FE6C_H

FE6E_H

FE70_H

34_H

35_H

36_H

37_H

38_H

CC21

CAPCOM Register 21

CC22

CAPCOM Register 22

CC23

CAPCOM Register 23

CC24

CAPCOM Register 24

CC24IC

CC25

b F170_HE B8_H

FE72_H39_H

b F172_HE B9_H

FE74_H3A_H

b F174_HE BA_H

FE76_H3B_H

b F176_HE BB_H

CAPCOM Reg. 24 Interrupt Ctrl. Reg.

CAPCOM Register 25

CC25IC

CC26

CAPCOM Reg. 25 Interrupt Ctrl. Reg.

CAPCOM Register 26

CC26IC

CC27

CAPCOM Reg. 26 Interrupt Ctrl. Reg.

CAPCOM Register 27

CC27IC

CAPCOM Reg. 27 Interrupt Ctrl. Reg.

Data Sheet

34

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Table 7

Name

C164CI-3V Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

FE78_H

FE7A_H

FE7C_H

FE7E_H

FE30_H

FE32_H

FE34_H

Addr.

3C_H

3D_H

3E_H

3F_H

18_H

CC28

CC29

CC30

CC31

CC60

CC61

CC62

CC6EIC

CAPCOM Register 28

CAPCOM Register 29

CAPCOM Register 30

CAPCOM Register 31

CAPCOM 6 Register 0

CAPCOM 6 Register 1

CAPCOM 6 Register 2

0000_H

19_H

1A_H

b F188_HE C4_H

CAPCOM 6 Emergency Interrrupt

Control Register

0000_H

CC6CIC

b F17E_HE BF_H

CAPCOM 6 Interrupt Control Register

CAPCOM 6 Mode Control Register

CAPCOM 6 Mode Interrupt Ctrl. Reg.

CAPCOM 6 Mode Select Register

External Interrupt 0 Control Register

External Interrupt 1 Control Register

CAPCOM Mode Control Register 4

CAPCOM Mode Control Register 5

CAPCOM Mode Control Register 6

CAPCOM Mode Control Register 7

CAPCOM 6 Timer 13 Compare Reg.

CPU Context Pointer Register

0000_H

00FF_H

0000_H

FC00_H

0000_H

CC6MCON b FF32_H

99_H

9B_H

CC6MIC

CC6MSEL

CC8IC

CC9IC

CCM4

CCM5

CCM6

CCM7

CMP13

CP

b FF36_H

F036_HE 1B_H

b FF88_H

C4_H

C5_H

91_H

92_H

93_H

94_H

1B_H

08_H

04_H

b FF8A_H

b FF22_H

b FF24_H

b FF26_H

b FF28_H

FE36_H

FE10_H

CSP

FE08_H

CPU Code Segment Pointer Register

(8 bits, not directly writeable)

CTCON

DP0H

DP0L

DP1H

DP1L

DP3

b FF30_H

98_H

CAPCOM 6 Compare Timer Ctrl. Reg.

P0H Direction Control Register

P0L Direction Control Register

P1H Direction Control Register

P1L Direction Control Register

Port 3 Direction Control Register

Port 4 Direction Control Register

1010_H

00_H

b F102_HE 81_H

b F100_HE 80_H

b F106_HE 83_H

b F104_HE 82_H

00_H

b FFC6_H

b FFCA_H

E3_H

E5_H

0000_H

00_H

DP4

Data Sheet

35

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Table 7

Name

C164CI-3V Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

b FFD6_H

FE00_H

Addr.

EB_H

00_H

DP8

Port 8 Direction Control Register

00_H

DPP0

DPP1

DPP2

DPP3

EXICON

EXISEL

FOCON

IDCHIP

IDMANUF

IDMEM

IDPROG

IDMEM2

ISNC

CPU Data Page Pointer 0 Reg. (10 bits)

CPU Data Page Pointer 1 Reg. (10 bits)

CPU Data Page Pointer 2 Reg. (10 bits)

CPU Data Page Pointer 3 Reg. (10 bits)

External Interrupt Control Register

External Interrupt Source Select Reg.

Frequency Output Control Register

Identifier

0000_H

0001_H

0002_H

0003_H

0000_H

XXXX_H

1820_H

XXXX_H

0000_H

00_H

FE02_H

01_H

FE04_H

02_H

FE06_H

03_H

b F1C0_HE E0_H

b F1DA_HE ED_H

b FFAA_H

D5_H

F07C_HE 3E_H

F07E_HE 3F_H

F07A_HE 3D_H

F078_HE 3C_H

F076_HE 3B_H

b F1DE_HE EF_H

Identifier

Interrupt Subnode Control Register

CPU Multiply Divide Control Register

CPU Multiply Divide Reg. – High Word

CPU Multiply Divide Reg. – Low Word

Port 3 Open Drain Control Register

Port 4 Open Drain Control Register

Port 8 Open Drain Control Register

Constant Value 1’s Register (read only)

Port 0 High Reg. (Upper half of PORT0)

Port 0 Low Reg. (Lower half of PORT0)

Port 1 High Reg. (Upper half of PORT1)

Port 1 Low Reg. (Lower half of PORT1)

Port 3 Register

MDC

b FF0E_H

FE0C_H

87_H

06_H

07_H

MDH

MDL

FE0E_H

ODP3

ODP4

ODP8

ONES

P0H

b F1C6_HE E3_H

b F1CA_HE E5_H

b F1D6_HE EB_H

00_H

b FF1E_H

b FF02_H

b FF00_H

b FF06_H

b FF04_H

b FFC4_H

b FFC8_H

b FFA2_H

b FFA4_H

b FFD4_H

8F_H

81_H

80_H

83_H

82_H

E2_H

E4_H

D1_H

D2_H

EA_H

FFFF_H

00_H

P0L

00_H

P1H

00_H

P1L

00_H

P3

0000_H

00_H

P4

Port 4 Register (7 bits)

P5

Port 5 Register (read only)

XXXX_H

0000_H

00_H

P5DIDIS

P8

Port 5 Digital Input Disable Register

Port 8 Register (8 bits)

Data Sheet

36

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Table 7

Name

C164CI-3V Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

PDCR

PECC0

PECC1

PECC2

PECC3

PECC4

PECC5

PECC6

PECC7

PICON

PSW

F0AA_HE 55_H

Port Driver Control Register

0000_H

FEC0_H

FEC2_H

FEC4_H

FEC6_H

FEC8_H

FECA_H

FECC_H

FECE_H

60_H

61_H

62_H

63_H

64_H

65_H

66_H

67_H

PEC Channel 0 Control Register

PEC Channel 1 Control Register

PEC Channel 2 Control Register

PEC Channel 3 Control Register

PEC Channel 4 Control Register

PEC Channel 5 Control Register

PEC Channel 6 Control Register

PEC Channel 7 Control Register

b F1C4_HE E2_H

Port Input Threshold Control Register

CPU Program Status Word

Port Temperature Compensation Reg.

System Startup Config. Reg. (Rd. only)

Reset Control Register

0000_H

XX_H

b FF10_H

b F0AE_H

88_H

57_H

PTCR

RP0H

b F108_HE 84_H

RSTCON b F1E0_Hm ---

00XX_H

no

RTCH

RTCL

S0BG

F0D6_HE 6B_H

F0D4_HE 6A_H

RTC High Register

RTC Low Register

no

FEB4_H

5A_H

Serial Channel 0 Baud Rate Generator

Reload Register

0000_H

S0CON

S0EIC

b FFB0_H

b FF70_H

D8_H

B8_H

Serial Channel 0 Control Register

0000_H

Serial Channel 0 Error Interrupt Ctrl.

Reg.

S0RBUF

S0RIC

FEB2_H

59_H

B7_H

Serial Channel 0 Receive Buffer Reg.

(read only)

XXXX_H

0000_H

b FF6E_H

Serial Channel 0 Receive Interrupt

Control Register

S0TBIC

S0TBUF

S0TIC

b F19C_HE CE_H

Serial Channel 0 Transmit Buffer

Interrupt Control Register

FEB0_H

58_H

B6_H

Serial Channel 0 Transmit Buffer Reg.

(write only)

b FF6C_H

Serial Channel 0 Transmit Interrupt

Control Register

Data Sheet

37

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Table 7

Name

C164CI-3V Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

SP

FE12_H

09_H

CPU System Stack Pointer Register

FC00_H

0000_H

XXXX_H

0000_H

FA00_H

FC00_H

¹⁾0xx0_H

0000_H

no

SSCBR

F0B4_HE 5A_H

SSC Baudrate Register

SSCCON b FFB2_H

D9_H

BB_H

SSC Control Register

SSCEIC

SSCRB

SSCRIC

SSCTB

SSCTIC

STKOV

STKUN

b FF76_H

SSC Error Interrupt Control Register

SSC Receive Buffer

F0B2_HE 59_H

b FF74_H

BA_H

SSC Receive Interrupt Control Register

SSC Transmit Buffer

F0B0_HE 58_H

b FF72_H

B9_H

0A_H

0B_H

89_H

SSC Transmit Interrupt Control Register

CPU Stack Overflow Pointer Register

CPU Stack Underflow Pointer Register

CPU System Configuration Register

CPU System Configuration Register 1

CPU System Configuration Register 2

CPU System Configuration Register 3

CAPCOM 6 Timer 12 Interrupt Ctrl. Reg.

CAPCOM 6 Timer 12 Offset Register

CAPCOM 6 Timer 12 Period Register

FE14_H

FE16_H

SYSCON b FF12_H

SYSCON1 b F1DC_HE EE_H

SYSCON2 b F1D0_HE E8_H

SYSCON3 b F1D4_HE EA_H

T12IC

T12OF

T12P

T13IC

T13P

T14

b F190_HE C8_H

F034_HE 1A_H

F030_HE 18_H

b F198_HE CC_HCAPCOM 6 Timer 13 Interrupt Ctrl. Reg.

F032_HE 19_H

F0D2_HE 69_H

F0D0_HE 68_H

CAPCOM 6 Timer 13 Period Register

RTC Timer 14 Register

T14REL

T2

RTC Timer 14 Reload Register

GPT1 Timer 2 Register

no

FE40_H

b FF40_H

b FF60_H

FE42_H

20_H

A0_H

B0_H

21_H

A1_H

B1_H

22_H

A2_H

B2_H

0000_H

T2CON

T2IC

GPT1 Timer 2 Control Register

GPT1 Timer 2 Interrupt Control Register

GPT1 Timer 3 Register

T3

T3CON

T3IC

b FF42_H

b FF62_H

FE44_H

GPT1 Timer 3 Control Register

GPT1 Timer 3 Interrupt Control Register

GPT1 Timer 4 Register

T4

T4CON

T4IC

b FF44_H

b FF64_H

GPT1 Timer 4 Control Register

GPT1 Timer 4 Interrupt Control Register

Data Sheet

38

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Table 7

Name

C164CI-3V Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

T7

F050_HE 28_H

CAPCOM Timer 7 Register

0000_H

T78CON

T7IC

b FF20_H

90_H

b F17A_HE BD_H

F054_HE 2A_H

F052_HE 29_H

CAPCOM Timer 7 and 8 Ctrl. Reg.

CAPCOM Timer 7 Interrupt Ctrl. Reg.

CAPCOM Timer 7 Reload Register

CAPCOM Timer 8 Register

0000_H

00XX_H

0000_H

²⁾00xx_H

0000_H

T7REL

T8

T8IC

b F17C_HE BE_H

F056_HE 2B_H

CAPCOM Timer 8 Interrupt Ctrl. Reg.

CAPCOM Timer 8 Reload Register

Trap Flag Register

T8REL

TFR

b FFAC_H

b FF34_H

FEAE_H

D6_H

9A_H

57_H

D7_H

TRCON

WDT

CAPCOM 6 Trap Enable Ctrl. Reg.

Watchdog Timer Register (read only)

Watchdog Timer Control Register

CAN1 Module Interrupt Control Register

Unassigned Interrupt Control Reg.

PLL/RTC Interrupt Control Register

Constant Value 0’s Register (read only)

WDTCON

XP0IC

XP1IC

XP3IC

FFAE_H

b F186_HE C3_H

b F18E_HE C7_H

b F19E_HE CF_H

ZEROS

b FF1C_H

8E_H

1)

The system configuration is selected during reset.

2)

The reset value depends on the indicated reset source.

Data Sheet

39

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Absolute Maximum Ratings

Table 8

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

150

6.5

Storage temperature

Junction temperature

T_ST

T_J

-65

-40

-0.5

°C

V

–

under bias

–

Voltage on V_DDpins with V_DD

respect to ground (V_SS)

Voltage on any pin with

respect to ground (V_SS)

V_IN

-0.5

-10

–

V

_DD+ 0.5 V

–

Input current on any pin

during overload condition

–

10

mA

Absolute sum of all input

currents during overload

condition

–

|100|

Power dissipation

P_DISS

–

1.5

W

–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN> V_DDor V_IN< V_SS) the

voltage on V_DDpins with respect to ground (V_SS) must not exceed the values

defined by the absolute maximum ratings.

Data Sheet

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V1.0, 2003-01

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Low Power

Preliminary

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the C164CI-3V. All parameters specified in the following sections refer to

these operating conditions, unless otherwise noticed.

Table 9

Operating Condition Parameters

Parameter

Symbol

Limit Values

min. max.

3.0 3.6

Unit Notes

Digital supply voltage

V_DD

V

Active mode,

_CPUmax= 16 MHz

f

2.5¹⁾

3.6

V

PowerDown mode

Digital ground voltage

Overload current

V_SS

I_OV

0

Reference voltage

–

±5

mA Per pin²⁾³⁾

3)

Absolute sum of overload Σ|I_OV

|

50

mA

currents

External Load

Capacitance

C_L

T_A

–

0

100

70

pF

Pin drivers in

default mode⁴⁾⁵⁾

Ambient temperature

°C

SAB-C164CI-3V

…

-40

85

°C

SAF-C164CI-3V …

125

SAK-C164CI-3V

…

1)

Output voltages and output currents will be reduced when V_DDleaves the range defined for active mode.

2)

Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input overload

currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.

Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,

etc.

3)

4)

Not 100% tested, guaranteed by design and characterization.

The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output

current may lead to increased delays or reduced driving capability (C_L).

5)

The current version of the C164CI-3V is equipped with port drivers, which provide reduced driving capability

and reduced control. Please refer to the actual errata sheet for details.

Data Sheet

41

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C164CI-L16M3V

Low Power

Preliminary

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C164CI-

3V and partly its demands on the system. To aid in interpreting the parameters right,

when evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C164CI-3V will provide signals with the respective characteristics.

SR (System Requirement):

The external system must provide signals with the respective characteristics to the

C164CI-3V.

DC Characteristics

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Conditions

min.

max.

Input low voltage (TTL,

all except XTAL1)

V_ILSR -0.5

0.8

V

–

Input low voltage XTAL1

V_IL2SR -0.5

V_ILSSR -0.5

0.3 V_DD

V

–

Input low voltage

1.3

(Special Threshold)

Input high voltage (TTL,

all except RSTIN, XTAL1)

V_IHSR 1.8

V_DD

0.5

+

V

–

Input high voltage RSTIN

(when operated as input)

V_IH1SR 0.6 V_DDV_DD

0.5

Input high voltage XTAL1

V_IH2SR 0.7 V_DDV_DD

0.5

Input high voltage

(Special Threshold)

V_IHSSR 0.8 V_DDV_DD

- 0.2

0.5

Input Hysteresis

HYS

150

–

mV Series resistance

(Special Threshold)

= 0 Ω

Output low voltage²⁾

Output high voltage⁴⁾

V_OLCC –

0.45

–

V

I

_OL≤ I_OLnom

3)

V_OHCC V_DD

-

_OH≥ I_OHnom

0.45

Input leakage current (Port 5)

I_OZ1CC –

±200

±500

nA 0 V < V_IN< V_DD

Input leakage current (all other) I_OZ2CC –

nA 0.45 V < V_IN<

V_DD

RSTIN inactive current⁵⁾

Data Sheet

I_RSTH

–

-5

µA V_IN= V_IH1

6)

42

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Preliminary

DC Characteristics (cont’d)

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Conditions

min.

max.

–

RSTIN active current⁵⁾

RD/WR inact. current⁸⁾

RD/WR active current⁸⁾

ALE inactive current⁸⁾

ALE active current⁸⁾

Port 4 inactive current⁸⁾

Port 4 active current⁸⁾

PORT0 configuration current⁹⁾

I_RSTL

-100

–

µA V_IN= V_IL

7)

6)

I_RWH

-10

–

µA

V

_OUT= 2.4 V

7)

I_RWL

-500

–

_OUT= V_OLmax

_OUT= 2.4 V

6)

I_ALEL

20

–

7)

I_ALEH

500

–

6)

I_P4H

-10

–

_OUT= 2.4 V

7)

I_P4L

-500

–

_OUT= V_OL1max

6)

I_P0H

-5

µA V_IN= V_IHmin

µA V_IN= V_ILmax

µA 0 V < V_IN< V_DD

7)

I_P0L

-100

–

XTAL1 input current

Pin capacitance¹⁰⁾

I_ILCC –

C_IOCC –

±20

10

pF

f = 1 MHz

(digital inputs/outputs)

T_A= 25 °C

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current I_OV

.

2)

3)

For pin RSTIN this specification is only valid in bidirectional reset mode.

As a rule, with decreasing output current the output levels approach the respective supply level (V_OL→ V_SS

V_OH→ V_DD). However, only the levels for nominal output currents are guaranteed.

See Table 10, Current Limits for Port Output Drivers.

,

4)

This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

5)

6)

7)

8)

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is valid during Reset and during Adapt-mode. The Port 4 current values are only valid for

pins P4.3-0, which can act as CS outputs.

9)

This specification is valid during Reset if required for configuration, and during Adapt-mode.

¹⁰⁾Not 100% tested, guaranteed by design and characterization.

Data Sheet

43

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C164CI-L16M3V

Low Power

Preliminary

Table 10

Current Limits for Port Output Drivers

Port Output Driver

Mode

Maximum Output Current

Nominal Output Current

(I_OLnom, -I_OHnom)

1)

(I_OLmax, -I_OHmax

)

(PORT0, PORT1,

Port 2, Port 4, ALE,

RD, WR, BHE,

-----

1.6 mA

CLKOUT, RSTOUT,

RSTIN²⁾)

All other outputs

-----

0.5 mA

1)

An output current above |I_OXnom| is not specified for the C164CI-3V.

Valid for V_OLin bidirectional reset mode only.

2)

Power Consumption C164CI-3V

(Operating Conditions apply)

Parameter

Sym-

bol

Limit Values

Unit Test

Conditions

min.

max.

Power supply current (active)

with all peripherals active

I_DD

–

1 +

1.5 × f_CPU

mA RSTIN = V_IL

_CPUin [MHz]¹⁾

mA RSTIN = V_IH1

_CPUin [MHz]¹⁾

µA RSTIN = V_IH1

_OSCin [MHz]¹⁾

f

Idle mode supply current

with all peripherals active

I_IDX

1 +

0.7 × f_CPU

f

2)

Idle mode supply current

with all peripherals deactivated,

PLL off, SDD factor = 32

I_IDO

500 +

50 × f_OSC

f

2)

Sleep and Power-down mode

supply current with RTC running

I_PDR

–

200 +

25 × f_OSC

µA

V

f

_DD= V_DDmax

_OSCin [MHz]³⁾

3)

Sleep and Power-down mode

I_PDO

30

V_DD= V_DDmax

supply current with RTC disabled

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 9.

These parameters are tested at V_DDmaxand maximum CPU clock with all outputs disconnected and all inputs

at V_ILor V_IH.

2)

3)

This parameter is determined mainly by the current consumed by the oscillator (see Figure 8). This current,

however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical

circuitry and may change in case of a not optimized external oscillator circuitry.

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V_DD- 0.1 V to V_DD, all outputs (including pins configured as outputs) disconnected.

Data Sheet

44

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

I [µA]

3000

2000

1000

I_IDOmax

I_IDOtyp

I_PDRmax

I_PDOmax

10

20

30

40

f

_OSC[MHz]

Figure 8

Idle and Power Down Supply Current as a Function of Oscillator

Frequency

Data Sheet

45

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C164CI-L16M3V

Low Power

Preliminary

I [mA]

100

80

60

40

20

I_DD3max

I_DD3typ

I_IDX3max

I_IDX3typ

10

15

20

25

f

_CPU[MHz]

Figure 9

Supply/Idle Current as a Function of Operating Frequency

for ROM Derivatives

Data Sheet

46

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

AC Characteristics

Definition of Internal Timing

The internal operation of the C164CI-3V is controlled by the internal CPU clock f_CPU

.

Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus

cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).

Phase Locked Loop Operation

f_OSC

TCL

f_CPU

TCL

Direct Clock Drive

f_OSC

TCL

f_CPU

TCL

Prescaler Operation

f_OSC

TCL

f_CPU

MCT04338

TCL

Figure 10

Generation Mechanisms for the CPU Clock

The CPU clock signal f_CPUcan be generated from the oscillator clock signal f_OSCvia

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate f_CPU. This influence must

be regarded when calculating the timings for the C164CI-3V.

Note: The example for PLL operation shown in Figure 10 refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5.

Upon a long hardware reset register RP0H is loaded with the logic levels present on the

upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

Data Sheet

47

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C164CI-L16M3V

Low Power

Preliminary

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register

RSTCON under software control.

Table 11 associates the combinations of these three bits with the respective clock

generation mode.

Table 11

C164CI-3V Clock Generation Modes

CLKCFG¹⁾CPU Frequency External Clock

Notes

(RP0H.7-5) f_CPU= f_OSC× F

Input Range²⁾

2.5 to 4 MHz

3.33 to 5.33 MHz

5 to 8 MHz

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

f

_OSC× 4

_OSC× 3

_OSC× 2

_OSC× 5

_OSC× 1

_OSC× 1.5

_OSC/ 2

Default configuration

–

2 to 3.2 MHz

1 to 16 MHz

–

Direct drive³⁾

6.66 to 10.66 MHz

2 to 32 MHz

–

CPU clock via prescaler

–

_OSC× 2.5

4 to 6.4 MHz

1)

2)

3)

Please note that pin P0.15 (corresponding to RP0H.7) is inverted in emulation mode, and thus also in EHM.

The external clock input range refers to a CPU clock range of 10 … 16 MHz.

The maximum frequency depends on the duty cycle of the external clock signal.

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001_B) the CPU clock is derived from

the internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of f_CPUis half the frequency of f_OSCand the high and low time of f_CPU(i.e.

the duration of an individual TCL) is defined by the period of the input clock f_OSC

.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

calculated using the period of f_OSCfor any TCL.

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is

enabled and provides the CPU clock (see Table 11). The PLL multiplies the input

frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.

f

_CPU= f_OSC× F). With every F’th transition of f_OSCthe PLL circuit synchronizes the CPU

clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock

frequency does not change abruptly.

Data Sheet

48

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C164CI-L16M3V

Low Power

Preliminary

Due to this adaptation to the input clock the frequency of f_CPUis constantly adjusted so

it is locked to f_OSC. The slight variation causes a jitter of f_CPUwhich also effects the

duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be

calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is

constantly adjusting its output frequency so it corresponds to the applied input frequency

(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than

for one single TCL (see formula and Figure 11).

For a period of N × TCL the minimum value is computed using the corresponding

deviation D :

N

(N × TCL)_min= N × TCL_NOM- D ; D [ns] = ±(13.3 + N × 6.3)/f_CPU[MHz],

N

where N = number of consecutive TCLs and 1 ≤ N ≤ 40.

So for a period of 3 TCLs @ 16 MHz (i.e. N = 3): D = (13.3 + 3 × 6.3)/16 = 2.013 ns,

3

and (3TCL)_min= 3TCL_NOM- 2.013 ns = 91.7 ns (@ f_CPU= 16 MHz).

This is especially important for bus cycles using waitstates and e.g. for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter

is neglectible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).

Max. jitter D_N

ns

This approximated formula is valid for

±30

<

25 MHz.

CPU

1

N

40 and 10 MHz

f

–

10 MHz

16 MHz

±26.5

±20

20 MHz

25 MHz

±10

±1

N

1

10

20

30

40

MCD04455

Figure 11

Approximated Maximum Accumulated PLL Jitter

Data Sheet

49

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Direct Drive

When direct drive is configured (CLKCFG = 011_B) the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input

clock signal.

The frequency of f_CPUdirectly follows the frequency of f_OSCso the high and low time of

f

_CPU(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

f_OSC

.

The timings listed below that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective circumstances. This minimum value

can be calculated via the following formula:

TCL_min= 1/f_OSC× DC_min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of f_OSCis compensated

so the duration of 2TCL is always 1/f_OSC. The minimum value TCL_mintherefore has to

be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that

require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/f_OSC

.

Data Sheet

50

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C164CI-L16M3V

Low Power

Preliminary

AC Characteristics

External Clock Drive XTAL1

(Operating Conditions apply)

Table 12

External Clock Drive Characteristics

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

Oscillator period t_OSCSR 62

max. min.

max.

500¹⁾ns

1000

31

8

500

–

94¹⁾

10

–

High time²⁾

Low time²⁾

Rise time²⁾

t₁

t₂

t₃

t₄

SR 31³⁾

SR –

–

8

–

ns

8

–

6

10

Fall time²⁾

SR –

–

6

–

1)

The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation

mode. Please see respective table above.

2)

3)

The clock input signal must reach the defined levels V_IL2and V_IH2

.

The minimum high and low time refers to a duty cycle of 50%. The maximum operating freqency (f_CPU) in direct

drive mode depends on the duty cycle of the clock input signal.

t₁

t₃

t₄

V_IH2

V_IL

0.5 V_DD

t₂

t_OSC

MCT02534

Figure 12

External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 16 MHz.

It is strongly recommended to measure the oscillation allowance (or margin) in the

final target system (layout) to determine the optimum parameters for the oscillator

operation. Please refer to the limits specified by the crystal supplier.

When driven by an external clock signal it will accept the specified frequency

range (see Table 12). Operation at lower input frequencies is possible but is

guaranteed by design only (not 100% tested).

Data Sheet

51

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Low Power

Preliminary

A/D Converter Characteristics

(Operating Conditions apply)

Table 13

A/D Converter Characteristics

Symbol Limit Values

min. max.

_AREFSR 2.6 _DD+ 0.1 V

_AGNDSR V_SS- 0.1 V_SS+ 0.2 V

Parameter

Unit Test

Conditions

1)

Analog reference supply

Analog reference ground

V

–

2)

Analog input voltage range V_AINSR V_AGND

V_AREF

6.25

V

3)

4)

Basic clock frequency

Conversion time

f_BC

t_C

0.5

CC –

MHz

–

40 t_BC

+

t_S+ 2t_CPU

3328 t_BC

±4

t_CPU= 1 / f_CPU

5)

Calibration time after reset t_CALCC –

–

1)

Total unadjusted error

TUE CC –

_AREFSR –

LSB

kΩ

Internal resistance of

R

t

_BC/ 60

t

_BCin [ns]⁶⁾⁷⁾

reference voltage source

- 0.25

Internal resistance of analog R_ASRCSR –

t_S/ 450

kΩ t_Sin [ns]⁷⁾⁸⁾

source

- 0.25

7)

ADC input capacitance

C_AINCC –

33

pF

1)

TUE is tested at V_AREF= V_DD+ 0.1 V, V_AGND= 0 V. It is guaranteed by design for all other voltages within the

defined voltage range.

If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V

(i.e. V_AREF= V_DD+0.2 V) the maximum TUE is increased to ±5 LSB. This range is not 100% tested.

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see I_OV

specification) does not exceed 10 mA.

During the reset calibration sequence the maximum TUE may be ±8 LSB.

2)

V_AINmay exceed V_AGNDor V_AREFup to the absolute maximum ratings. However, the conversion result in

these cases will be X000_Hor X3FF_H, respectively.

3)

4)

The limit values for f_BCmust not be exceeded when selecting the CPU frequency and the ADCTC setting.

This parameter includes the sample time t_S, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the basic clock t_BCdepend on programming and can be taken from Table 14.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

5)

6)

During the reset calibration conversions can be executed (with the current accuracy). The time required for

these conversions is added to the total reset calibration time.

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within each conversion step. The maximum internal resistance results from the programmed conversion

timing.

7)

Not 100% tested, guaranteed by design and characterization.

Data Sheet

52

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C164CI-L16M3V

Low Power

Preliminary

8)

During the sample time the input capacitance C_AINcan be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within t_S.

After the end of the sample time t_S, changes of the analog input voltage have no effect on the conversion result.

Values for the sample time t_Sdepend on programming and can be taken from Table 14.

Sample time and conversion time of the C164CI-3V’s A/D Converter are programmable.

Table 14 should be used to calculate the above timings.

The limit values for f_BCmust not be exceeded when selecting ADCTC.

Table 14

A/D Converter Computation Table

ADCON.13|12 Sample time

ADCON.15|14 A/D Converter

(ADCTC)

Basic Clock f_BC

(ADSTC)

t_S

00

01

10

11

f_CPU/ 4

f_CPU/ 2

f_CPU/ 16

f_CPU/ 8

00

01

10

11

t

_BC× 8

_BC× 16

_BC× 32

_BC× 64

Converter Timing Example:

Assumptions:

f_CPU= 12.5 MHz (i.e. t_CPU= 80 ns), ADCTC = ‘01’, ADSTC = ‘00’.

Basic clock

Sample time

f_BC

t_S

= f_CPU/ 2 = 6.25 MHz, i.e. t_BC= 160 ns.

= t_BC× 8 = 1280 ns.

Conversion time t_C

= t_S+ 40 t_BC+ 2 t_CPU= (1280 + 6400 + 160) ns = 7.8 µs.

Data Sheet

53

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C164CI-L16M3V

Low Power

Preliminary

Testing Waveforms

2.4 V

1.8 V

0.8 V

1.8 V

0.8 V

Test Points

0.45 V

AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.

Timing measurements are made at _IHmin for a logic ’1’ and _ILmax for a logic ’0’.

V

MCA04414

Figure 13

Input Output Waveforms

V_Load+ 0.1 V

V_OH- 0.1 V

Timing

Reference

Points

V_Load- 0.1 V

V_OL+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

but begins to float when a 100 mV change from the loaded V_OH

/

V_OLlevel occurs (I_OH

/

I

_OL= 20 mA).

MCA00763

Figure 14

Float Waveforms

Data Sheet

54

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx

registers and represent the special characteristics of the programmed memory cycle.

The following table describes, how these variables are to be computed.

Table 15

Memory Cycle Variables

Symbol Values

Description

ALE Extension

t_A

TCL × <ALECTL>

Memory Cycle Time Waitstates t_C

Memory Tristate Time

2TCL × (15 - <MCTC>)

2TCL × (1 - <MTTC>)

t_F

Note: Please respect the maximum operating frequency of the respective derivative.

AC Characteristics

Multiplexed Bus

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(187.5 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 16 MHz 1 / 2TCL = 1 to 16 MHz

min.

max.

min.

max.

ALE high time

t₅CC 17 + t_A

t₆CC 11 + t_A

t₇CC 21 + t_A

t₈CC 21 + t_A

t₉CC -10 + t_A

t₁₀CC –

–

TCL - 14

+ t_A

–

ns

Address setup to ALE

Address hold after ALE

–

TCL - 20

+ t_A

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ t_A

–

ALE falling edge to RD,

WR (no RW-delay)

–

-10 + t_A

–

Address float after RD,

WR (with RW-delay)

6

–

6

Address float after RD,

WR (no RW-delay)

t₁₁CC –

37

–

TCL + 6

RD, WR low time

(with RW-delay)

t₁₂CC 46 + t_C

2TCL - 16 –

+ t_C

Data Sheet

55

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C164CI-L16M3V

Low Power

Preliminary

Multiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(187.5 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 16 MHz 1 / 2TCL = 1 to 16 MHz

min. max.

min.

max.

RD, WR low time

(no RW-delay)

t₁₃CC 78 + t_C

–

3TCL - 16 –

+ t_C

ns

RD to valid data in

(with RW-delay)

t₁₄SR –

35 + t_C

66 + t_C

–

0

–

2TCL - 28 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 28 ns

+ t_C

ALE low to valid data in

t₁₆SR –

64 + t_A

+ t_C

3TCL - 30 ns

+ t_A+ t_C

Address to valid data in

t₁₇SR –

82 + 2t_A

+ t_C

4TCL - 43 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data float after RD

Data valid to WR

Data hold after WR

t₁₉SR –

49 + t_F

2TCL - 14 ns

+ t_F

t₂₂CC 37 + t_C

t₂₃CC 49 + t_F

–

2TCL - 26 –

+ t_C

ns

–

2TCL - 14 –

+ t_F

ALE rising edge after RD, t₂₅CC 49 + t_F

WR

–

2TCL - 14 –

+ t_F

Address hold after RD,

WR

ALE falling edge to CS¹⁾t₃₈CC -8 - t_A

CS low to Valid Data In¹⁾t₃₉SR –

t₂₇CC 49 + t_F

–

2TCL - 14 –

+ t_F

10 - t_A

-8 - t_A

10 - t_A

66

–

3TCL - 28 ns

+ t_C

+ 2t_A

+ t_C+ 2t_A

CS hold after RD, WR¹⁾t₄₀CC 76 + t_F

–

3TCL - 18 –

+ t_F

ns

ALE fall. edge to RdCS, t₄₂CC 25 + t_A

–

TCL - 6

–

WrCS (with RW delay)

+ t_A

Data Sheet

56

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Multiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(187.5 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 16 MHz 1 / 2TCL = 1 to 16 MHz

min.

max.

min.

max.

ALE fall. edge to RdCS, t₄₃CC -6 + t_A

WrCS (no RW delay)

–

-6

+ t_A

–

ns

Address float after RdCS, t₄₄CC –

WrCS (with RW delay)

0

–

0

Address float after RdCS, t₄₅CC –

WrCS (no RW delay)

31

TCL

RdCS to Valid Data In

(with RW delay)

t₄₆SR –

t₄₇SR –

33 + t_C

2TCL - 30 ns

+ t_C

RdCS to Valid Data In

(no RW delay)

64 + t_C

3TCL - 30 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 51 + t_C

(with RW delay)

–

2TCL - 12 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 82 + t_C

(no RW delay)

3TCL - 12 –

+ t_C

Data valid to WrCS

t₅₀CC 41 + t_C

2TCL - 22 –

+ t_C

Data hold after RdCS

Data float after RdCS

t₅₁SR 0

t₅₂SR –

–

0

–

43 + t_F

2TCL - 20 ns

+ t_F

Address hold after

RdCS, WrCS

t₅₄CC 43 + t_F

t₅₆CC 43 + t_F

–

2TCL - 20 –

+ t_F

ns

Data hold after WrCS

2TCL - 20 –

+ t_F

1)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

57

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A21-A16

(A15-A8)

BHE, CSxE

Address

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

Data In

t₁₀

t₈

t₁₄

t₁₂

t₄₆

t₄₈

RD

t₅₁

t₄₄

t₄₂

t₅₂

RdCSx

Write Cycle

BUS

t₂₃

Address

Data Out

t₅₆

t₁₀

t₈

t₂₂

WR,

WRL,

WRH

t₁₂

t₅₀

t₄₄

t₄₂

WrCSx

t₄₈

Figure 15

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

58

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₃₈

t₁₆

t₂₅

t₄₀

t₂₇

ALE

t₃₉

CSxL

t₁₇

A21-A16

(A15-A8)

Address

BHE, CSxE

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

Data In

t₁₀

t₈

t₁₄

t₁₂

t₄₆

t₄₈

RD

t₅₁

t₅₂

t₄

t₄₂

RdCSx

Write Cycle

BUS

t₂₃

Address

Data Out

t₅₆

t₁₀

t₈

t₂₂

WR,

WRL,

WRH

t₁₂

t₅₀

t₄₄

t₄₂

WrCSx

t₄₈

Figure 16

External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

59

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₁₆

t₂₅

ALE

t₃₈

t₃₉

t₄₀

CSxL

t₁₇

t₂₇

A21-A16

(A15-A8)

Address

BHE, CSxE

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

Data In

t₉

t₁₁

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₄₃

t₄₅

t₅₂

RdCSx

Write Cycle

BUS

t₂₃

Address

Data Out

t₅₆

t₉

t₁₁

t₂₂

WR,

WRL,

WRH

t₁₃

t₅₀

t₄₃

t₄₅

WrCSx

t₄₉

Figure 17

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

60

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₁₆

t₂₅

t₄₀

t₂₇

ALE

t₃₈

t₃₉

CSxL

t₁₇

A21-A16

(A15-A8)

Address

BHE, CSxE

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

Data In

t₉

t₁₁

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₅₂

t₄₃

t₄₅

RdCSx

Write Cycle

BUS

t₂₃

Address

Data Out

t₅₆

t₉

t₁₁

t₂₂

WR,

WRL,

WRH

t₁₃

t₅₀

t₄₃

t₄₅

WrCSx

t₄₉

Figure 18

External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

61

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

AC Characteristics

Demultiplexed Bus

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(125 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 16 MHz

1 / 2TCL = 1 to 16 MHz

min.

max.

min.

max.

ALE high time

t₅CC 17 + t_A

t₆CC 11 + t_A

t₈CC 21 + t_A

t₉CC -10 + t_A

t₁₂CC 47 + t_C

t₁₃CC 78 + t_C

t₁₄SR –

–

TCL - 14

+ t_A

–

ns

Address setup to ALE

–

TCL - 20

+ t_A

–

ALE falling edge to RD,

WR (with RW-delay)

–

TCL - 10

+ t_A

ALE falling edge to RD,

WR (no RW-delay)

–

-10

+ t_A

RD, WR low time

(with RW-delay)

–

2TCL - 16 –

+ t_C

RD, WR low time

(no RW-delay)

–

3TCL - 16 –

+ t_C

RD to valid data in

(with RW-delay)

35 + t_C

66 + t_C

–

0

–

2TCL - 28 ns

+ t_C

RD to valid data in

(no RW-delay)

t₁₅SR –

3TCL - 28 ns

+ t_C

ALE low to valid data in

t₁₆SR –

64 +

t_A+ t_C

3TCL - 30 ns

+ t_A+ t_C

Address to valid data in

t₁₇SR –

82 +

2t_A+ t_C

4TCL - 43 ns

+ 2t_A+ t_C

Data hold after RD

rising edge

t₁₈SR 0

–

ns

Data float after RD rising t₂₀SR –

49 +

2t_A+ t_F

2TCL - 14 ns

+ 2t_A

+ t_F

edge (with RW-delay¹⁾)

1)

Data float after RD rising t₂₁SR –

21 +

2t_A+ t_F

–

TCL - 10

ns

edge (no RW-delay¹⁾)

+ 2t_A

1)

+ t_F

Data Sheet

62

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Demultiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(125 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 16 MHz

1 / 2TCL = 1 to 16 MHz

min.

max.

min. max.

Data valid to WR

t₂₂CC 37 + t_C

–

2TCL - 26 –

+ t_C

ns

Data hold after WR

t₂₄CC 21 + t_F

TCL - 10

+ t_F

–

ALE rising edge after RD, t₂₆CC -12 + t_F

-12 + t_F

WR

Address hold after WR²⁾t₂₈CC 0 + t_F

ALE falling edge to CS³⁾t₃₈CC -8 - t_A

CS low to Valid Data In³⁾t₃₉SR –

–

0 + t_F

-8 - t_A

–

ns

10 - t_A

66 +

3TCL - 28 ns

t_C+ 2t_A

+ t_C+ 2t_A

CS hold after RD, WR³⁾t₄₁CC 15 + t_F

–

TCL - 16

+ t_F

–

ns

ALE falling edge to RdCS, t₄₂CC 25 + t_A

WrCS (with RW-delay)

–

TCL - 6

+ t_A

ALE falling edge to RdCS, t₄₃CC -6 + t_A

–

-6

WrCS (no RW-delay)

+ t_A

RdCS to Valid Data In

(with RW-delay)

t₄₆SR –

t₄₇SR –

33 + t_C

–

2TCL - 30 ns

+ t_C

RdCS to Valid Data In

(no RW-delay)

64 + t_C

3TCL - 30 ns

+ t_C

RdCS, WrCS Low Time t₄₈CC 51 + t_C

(with RW-delay)

–

2TCL - 12 –

+ t_C

ns

RdCS, WrCS Low Time t₄₉CC 82 + t_C

(no RW-delay)

3TCL - 12 –

+ t_C

Data valid to WrCS

t₅₀CC 41 + t_C

2TCL - 22 –

+ t_C

Data hold after RdCS

t₅₁SR 0

t₅₃SR –

–

0

–

Data float after RdCS

(with RW-delay)¹⁾

43 + t_F

2TCL - 20 ns

1)

+ 2t_A+ t_F

Data Sheet

63

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Demultiplexed Bus (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(125 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 16 MHz

1 / 2TCL = 1 to 16 MHz

min.

t₆₈SR –

max.

min.

max.

Data float after RdCS

(no RW-delay)¹⁾

11 + t_F

–

TCL - 20

+ 2t_A+ t_F

ns

1)

Address hold after

RdCS, WrCS

t₅₅CC -16 + t_F

t₅₇CC 15 + t_F

–

-16 + t_F

–

Data hold after WrCS

TCL - 16

–

+ t_F

1)

RW-delay and t_Arefer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2)

Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3)

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Data Sheet

64

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₁₇

t₂₈

A21-A16

A15-A0

Address

BHE, CSxE

t₆

t₅₅

t₂₀

t₁₈

Read Cycle

BUS

(D15-D8)

D7-D0

Data In

t₈

t₁₄

RD

t₁₂

t₄₆

t₄₈

t₅₁

t₅₃

t₄₂

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

t₂₄

Data Out

t₅₇

t₈

t₂₂

WR,

WRL,

WRH

t₁₂

t₅₀

t₄₂

WrCSx

t₄₈

Figure 19

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet

65

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₁₆

t₃₉

t₁₇

t₂₆

ALE

t₃₈

t₄₁

CSxL

t₂₈

A21-A16

A15-A0

BHE,

Address

t₆

t₅₅

t₂₀

t₁₈

CSxE

Read Cycle

BUS

(D15-D8)

D7-D0

Data In

t₈

t₁₄

t₁₂

t₄₆

t₄₈

RD

t₅₁

t₅₃

t₄₂

RdCSx

Write Cycle

t₂₄

BUS

(D15-D8)

D7-D0

Data Out

t₅₇

t₈

t₂₂

WR,

WRL,

WRH

t₁₂

t₅₀

t₄₂

WrCSx

t₄₈

Figure 20

External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet

66

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₁₆

t₂₆

ALE

t₃₈

t₃₉

t₄₁

CSxL

t₁₇

t₂₈

A21-A16

A15-A0

Address

BHE, CSxE

t₆

t₅₅

t₂₁

t₁₈

Read Cycle

BUS

(D15-D8)

D7-D0

Data In

t₉

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₆₈

t₄₃

RdCSx

Write Cycle

t₂₄

BUS

(D15-D8)

D7-D0

Data Out

t₅₇

t₉

t₂₂

WR,

WRL,WRH

t₁₃

t₅₀

t₄₃

WrCSx

t₄₉

Figure 21

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet

67

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

t₅

t₁₆

t₃₉

t₁₇

t₂₆

ALE

t₃₈

t₄₁

CSxL

t₂₈

A21-A16

A15-A0

Address

BHE, CSxE

t₆

t₅₅

t₂₁

t₁₈

Read Cycle

BUS

(D15-D8)

D7-D0

Data In

t₉

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₄₃

t₆₈

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

t₂₄

Data Out

t₅₇

t₉

t₂₂

WR,

WRL, WRH

t₁₃

t₅₀

t₄₃

WrCSx

t₄₉

Figure 22

External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet

68

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

AC Characteristics

CLKOUT

(Operating Conditions apply)

Parameter

Symbol Max. CPU Clock Variable CPU Clock Unit

= 16 MHz 1 / 2TCL = 1 to 16 MHz

min.

max.

63

min.

max.

2TCL

–

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

t₂₉CC 63

t₃₀CC 21

t₃₁CC 19

t₃₂CC –

2TCL

TCL - 10

TCL - 12

–

ns

–

12

t₃₃CC –

8

–

8

CLKOUT rising edge to

ALE falling edge

t₃₄CC 0 + t_A

8 + t_A

0 + t_A

8 + t_A

Running cycle¹⁾

t₃₃

MUX/Tristate ³⁾

t₃₂

CLKOUT

ALE

t₃₀

t₃₄

t₂₉

t₃₁

4)

2)

Command

RD, WR

Figure 23

CLKOUT Timing

Notes

1)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted here.

2)

3)

For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without

MTTC waitstate this delay is zero.

The next external bus cycle may start here.

4)

Data Sheet

69

V1.0, 2003-01

C164CI-L16M3V

Low Power

Preliminary

Package Outlines

P-MQFP-80-7

(Plastic Metric Quad Flat Package)

H

0.65

±0.15

0.88

C

0.1

12.35

±0.08

0.3

M

0.12 A-B D C 80x

17.2

14¹⁾

0.2 A-B D 4x

0.2 A-B D H 4x

D

B

A

80

Index Marking

1

0.6 x 45˚

¹⁾Does not include plastic or metal protrusion of 0.25 max. per side

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

V1.0, 2003-01

SMD = Surface Mounted Device

Data Sheet

70

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	SAK-C164CI-L16M3V
厂家：	Infineon
描述：	RISC Microcontroller, 16-Bit, MROM, C166 CPU, 16MHz, CMOS, PQFP80, 0.65 MM, PLASTIC, MQFP-80 微控制器
文件：	总75页 (文件大小：1166K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAK-C164CI-L16M3V [INFINEON]

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