SAK-C167CR-L33MTR_技术文档

Data Sheet, V3.2, July 2001

C167CR

C167SR

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2001-07

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

Attention please!

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characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

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For further information on technology, delivery terms and conditions and prices please contact your nearest

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Due to technical requirements components may contain dangerous substances. For information on the types in

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Data Sheet, V3.2, July 2001

C167CR

C167SR

16-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

C167CR

Revision History:

2001-07

V3.2

Previous Version:

2000-04

2000-02

1999-10

1999-06

1999-03

1998-03

V3.1

V3.0

(Introduction of clock-related timing)

(Summarizes and replaces all older docs)

(C167SR/CR, 25 MHz Addendum)

07.97 / 12.96 (C167CR-4RM)

12.96

06.95

(C167CR-16RM)

(C167CR, C167SR)

06.94 / 05.93 (C167)

Page

Subjects (major changes since last revision)

Minor typos corrected

Several

4

Pin designations corrected (pins 108, 99, 98)

Port 8 designations corrected

5

10

46

58

Direction for P1H.4 … P1H.7 corrected

Note 4 added, notes 8, 9 updated

Note 2 detailed

69

Package drawing updated¹⁾

1)

New package due to new assembly line. P-MQFP-144-1 for current deliveries only, will be discontinued.

Controller Area Network (CAN): License of Robert Bosch GmbH

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16-Bit Single-Chip Microcontroller

C166 Family

C167CR/C167SR

• High Performance 16-bit CPU with 4-Stage Pipeline

– 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock

– 400/303 ns Multiplication (16 × 16 bit), 800/606 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 MBytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),

via prescaler or via direct clock input

• On-Chip Memory Modules

– 2 KBytes On-Chip Internal RAM (IRAM)

– 2 KBytes On-Chip Extension RAM (XRAM)

– 128/32 KBytes On-Chip Mask ROM

• On-Chip Peripheral Modules

– 16-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8 µs

– Two 16-Channel Capture/Compare Units

– 4-Channel PWM Unit

– Two Multi-Functional General Purpose Timer Units with 5 Timers

– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects

(Full CAN / Basic CAN)

• Up to 16 MBytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Five Programmable Chip-Select Signals

– Hold- and Hold-Acknowledge Bus Arbitration Support

• Idle and Power Down Modes

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 111 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

Data Sheet

1

V3.2, 2001-07

C167CR

C167SR

• Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,

Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 144-Pin MQFP Package

This document describes several derivatives of the C167 group. Table 1 enumerates

these derivatives and summarizes the differences. As this document refers to all of these

derivatives, some descriptions may not apply to a specific product.

Table 1

Derivative¹⁾

C167CR Derivative Synopsis

Program Memory

XRAM

CAN Interface

SAK-C167SR-LM

SAB-C167SR-LM

SAK-C167SR-L33M

SAB-C167SR-L33M

---

2 KByte

---

SAK-C167CR-LM

SAF-C167CR-LM

SAB-C167CR-LM

SAK-C167CR-L33M

SAB-C167CR-L33M

---

2 KByte

CAN1

SAK-C167CR-4RM

SAB-C167CR-4RM

SAK-C167CR-4R33M

SAB-C167CR-4R33M

32 KByte ROM

128 KByte ROM

2 KByte

CAN1

SAK-C167CR-16RM

SAK-C167CR-16R33M

1)

This Data Sheet is valid for devices manufactured in 0.5 µm technology, i.e. devices starting with and including

design step GA(-T)6.

For simplicity all versions are referred to by the term C167CR throughout this document.

Data Sheet

2

V3.2, 2001-07

C167CR

C167SR

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the

required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C167CR please refer to the “Product Catalog

Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Introduction

The C167CR derivatives are high performance derivatives of the Infineon C166 Family

of full featured single-chip CMOS microcontrollers. They combine high CPU

performance (up to 16.5 million instructions per second) with high peripheral functionality

and enhanced IO-capabilities. They also provide clock generation via PLL and various

on-chip memory modules such as program ROM, internal RAM, and extension RAM.

V_AREFV_AGNDV_DD

V_SS

Port 0

16 Bit

XTAL1

XTAL2

Port 1

16 Bit

RSTIN

RSTOUT

Port 2

16 Bit

NMI

Port 3

15 Bit

EA

C167CR

Port 4

8 Bit

READY

ALE

Port 6

8 Bit

RD

WR/WRL

Port 7

8 Bit

Port 5

16 Bit

Port 8

8 Bit

MCL04411

Figure 1

Logic Symbol

Data Sheet

3

V3.2, 2001-07

C167CR

C167SR

Pin Configuration

(top view)

P6.0/CS0

P6.1/CS1

P6.2/CS2

P6.3/CS3

P6.4/CS4

P6.5/HOLD

P6.6/HLDA

P6.7/BREQ

P8.0/CC16IO

P8.1/CC17IO

P8.2/CC18IO

P8.3/CC19IO

P8.4/CC20IO

P8.5/CC21IO

P8.6/CC22IO

P8.7/CC23IO

V_DD

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

P0H.0/AD8

P0L.7/AD7

P0L.6/AD6

P0L.5/AD5

P0L.4/AD4

P0L.3/AD3

P0L.2/AD2

P0L.1/AD1

P0L.0/AD0

EA

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

ALE

READY

WR/WRL

RD

V_SS

V_DD

P4.7/A23

V_SS

P4.6/A22/CAN1_TxD

P4.5/A21/CAN1_RxD

P4.4/A20

P4.3/A19

P4.2/A18

P4.1/A17

P4.0/A16

OWE

V_SS

C167CR

P7.0/POUT0

P7.1/POUT1

P7.2/POUT2

P7.3/POUT3

P7.4/CC28IO

P7.5/CC29IO

P7.6/CC30IO

P7.7/CC31IO

P5.0/AN0

P5.1/AN1

P5.2/AN2

P5.3/AN3

P5.4/AN4

V_DD

P3.15/CLKOUT

P3.13/SCLK

P3.12/BHE/WRH

P3.111/RxD0

P3.10/TxD0

P3.9/MTSR

P3.8/MRST

P3.7/T2IN

P5.5/AN5

P5.6/AN6

P5.7/AN7

P5.8/AN8

74

73

P5.9/AN9

P3.6/T3IN

MCP04410

Figure 2

Data Sheet

4

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions

Input Function

Symbol Pin

Num. Outp.

P6

IO

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 6 outputs can be configured as push/

pull or open drain drivers.

The Port 6 pins also serve for alternate functions:

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

1

2

3

4

5

6

7

O

I

CS0

CS1

CS2

CS3

CS4

HOLD

HLDA

Chip Select 0 Output

Chip Select 1 Output

Chip Select 2 Output

Chip Select 3 Output

Chip Select 4 Output

External Master Hold Request Input

Hold Acknowledge Output (master mode)

or Input (slave mode)

I/O

P6.7

8

O

BREQ

Bus Request Output

P8

IO

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 8 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 8 is

selectable (TTL or special).

The following Port 8 pins also serve for alternate functions:

P8.0

P8.1

P8.2

P8.3

P8.4

P8.5

P8.6

P8.7

9

I/O

CC16IO

CC17IO

CC18IO

CC19IO

CC20IO

CC21IO

CC22IO

CC23IO

CAPCOM2: CC16 Capture Inp./Compare Outp.

CAPCOM2: CC17 Capture Inp./Compare Outp.

CAPCOM2: CC18 Capture Inp./Compare Outp.

CAPCOM2: CC19 Capture Inp./Compare Outp.

CAPCOM2: CC20 Capture Inp./Compare Outp.

CAPCOM2: CC21 Capture Inp./Compare Outp.

CAPCOM2: CC22 Capture Inp./Compare Outp.

CAPCOM2: CC23 Capture Inp./Compare Outp.

10

11

12

13

14

15

16

Data Sheet

5

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

P7

IO

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 7 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 7 is

selectable (TTL or special).

The following Port 7 pins also serve for alternate functions:

P7.0

P7.1

P7.2

P7.3

P7.4

P7.5

P7.6

P7.7

19

20

21

22

23

24

25

26

O

I/O

POUT0

POUT1

POUT2

POUT3

CC28IO

CC29IO

CC30IO

CC31IO

PWM Channel 0 Output

PWM Channel 1 Output

PWM Channel 2 Output

PWM Channel 3 Output

CAPCOM2: CC28 Capture Inp./Compare Outp.

CAPCOM2: CC29 Capture Inp./Compare Outp.

CAPCOM2: CC30 Capture Inp./Compare Outp.

CAPCOM2: CC31 Capture Inp./Compare Outp.

P5

I

Port 5 is a 16-bit input-only port with Schmitt-Trigger

characteristic.

The pins of Port 5 also serve as analog input channels for the

A/D converter, or they serve as timer inputs:

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

27

28

29

30

31

32

33

34

35

36

39

40

41

42

43

44

I

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10,

AN11,

AN12,

AN13,

AN14,

AN15,

P5.8

P5.9

P5.10

P5.11

P5.12

P5.13

P5.14

P5.15

T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.

T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.

T6IN

T5IN

GPT2 Timer T6 Count Inp.

GPT2 Timer T5 Count Inp.

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.

T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.

Data Sheet

6

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

P2

IO

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 2 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 2 is

selectable (TTL or special).

The following Port 2 pins also serve for alternate functions:

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.8

47

48

49

50

51

52

53

54

57

I/O

I

I/O

I

I/O

I

I/O

I

I/O

I

CC0IO

CC1IO

CC2IO

CC3IO

CC4IO

CC5IO

CC6IO

CC7IO

CC8IO

EX0IN

CC9IO

EX1IN

CC10IO

EX2IN

CC11IO

EX3IN

CC12IO

EX4IN

CC13IO

EX5IN

CC14IO

EX6IN

CC15IO

EX7IN

T7IN

CAPCOM1: CC0 Capture Inp./Compare Output

CAPCOM1: CC1 Capture Inp./Compare Output

CAPCOM1: CC2 Capture Inp./Compare Output

CAPCOM1: CC3 Capture Inp./Compare Output

CAPCOM1: CC4 Capture Inp./Compare Output

CAPCOM1: CC5 Capture Inp./Compare Output

CAPCOM1: CC6 Capture Inp./Compare Output

CAPCOM1: CC7 Capture Inp./Compare Output

CAPCOM1: CC8 Capture Inp./Compare Output,

Fast External Interrupt 0 Input

CAPCOM1: CC9 Capture Inp./Compare Output,

Fast External Interrupt 1 Input

CAPCOM1: CC10 Capture Inp./Compare Outp.,

Fast External Interrupt 2 Input

CAPCOM1: CC11 Capture Inp./Compare Outp.,

Fast External Interrupt 3 Input

CAPCOM1: CC12 Capture Inp./Compare Outp.,

Fast External Interrupt 4 Input

P2.9

58

59

60

61

62

63

64

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

I/O

I

I/O

I

I/O

I

CAPCOM1: CC13 Capture Inp./Compare Outp.,

Fast External Interrupt 5 Input

CAPCOM1: CC14 Capture Inp./Compare Outp.,

Fast External Interrupt 6 Input

CAPCOM1: CC15 Capture Inp./Compare Outp.,

Fast External Interrupt 7 Input,

CAPCOM2: Timer T7 Count Input

Data Sheet

7

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

P3

IO

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 3 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or special).

The following Port 3 pins also serve for alternate functions:

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

P3.10

P3.11

P3.12

65

66

67

68

69

70

73

74

75

76

77

78

79

I

O

I

O

I

T0IN

CAPCOM1 Timer T0 Count Input

GPT2 Timer T6 Toggle Latch Output

T6OUT

CAPIN

T3OUT

T3EUD

T4IN

GPT2 Register CAPREL Capture Input

GPT1 Timer T3 Toggle Latch Output

GPT1 Timer T3 External Up/Down Control Input

GPT1 Timer T4 Count/Gate/Reload/Capture Inp

GPT1 Timer T3 Count/Gate Input

GPT1 Timer T2 Count/Gate/Reload/Capture Inp

SSC Master-Receive/Slave-Transmit Inp./Outp.

SSC Master-Transmit/Slave-Receive Outp./Inp.

ASC0 Clock/Data Output (Async./Sync.)

ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe

SSC Master Clock Output / Slave Clock Input.

I

T3IN

T2IN

I/O

O

I/O

O

I/O

O

MRST

MTSR

T×D0

R×D0

BHE

WRH

SCLK

P3.13

P3.15

80

81

CLKOUT System Clock Output (= CPU Clock)

OWE

(V_PP)

84

I

Oscillator Watchdog Enable. This input enables the oscillator

watchdog when high or disables it when low e.g. for testing

purposes. An internal pullup device holds this input high if

nothing is driving it.

For normal operation pin OWE should be high or not

connected.

In order to drive pin OWE low draw a current of at least

200 µA.

Data Sheet

8

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

P4

IO

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

Port 4 can be used to output the segment address lines and

for serial bus interfaces:

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

85

86

87

88

89

90

O

I

O

A16

A17

A18

A19

A20

A21

Least Significant Segment Address Line

Segment Address Line

Segment Address Line,

CAN1_RxD CAN 1 Receive Data Input

A22 Segment Address Line,

CAN1_TxD CAN 1 Transmit Data Output

P4.6

91

P4.7

RD

92

95

A23

Most Significant Segment Address Line

O

External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR/

WRL

96

O

External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL-mode

this pin is activated for low byte data write accesses on a

16-bit bus, and for every data write access on an 8-bit bus.

See WRCFG in register SYSCON for mode selection.

READY 97

I

Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force

the insertion of memory cycle time waitstates until the pin

returns to a low level.

An internal pullup device will hold this pin high when nothing

is driving it.

ALE

EA

98

99

O

I

Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the

multiplexed bus modes.

External Access Enable pin. A low level at this pin during and

after Reset forces the C167CR to begin instruction execution

out of external memory. A high level forces execution out of

the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

Data Sheet

9

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

PORT0

P0L.0-7 100-

107

P0H.0-7 108,

111-

IO

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state.

In case of an external bus configuration, PORT0 serves as

the address (A) and address/data (AD) bus in multiplexed

bus modes and as the data (D) bus in demultiplexed bus

modes.

117

Demultiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

D0 – D7

I/O

16-bit

D0 – D7

D8 – D15

Multiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

16-bit

AD0 – AD7 AD0 – AD7

A8 – A15 AD8 – AD15

PORT1

P1L.0-7 118-

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state. PORT1 is used as the

16-bit address bus (A) in demultiplexed bus modes and also

after switching from a demultiplexed bus mode to a

multiplexed bus mode.

125

P1H.0-7 128-

135

The following PORT1 pins also serve for alternate functions:

P1H.4 132

P1H.5 133

P1H.6 134

P1H.7 135

I

CC24IO

CC25IO

CC26IO

CC27IO

CAPCOM2: CC24 Capture Input

CAPCOM2: CC25 Capture Input

CAPCOM2: CC26 Capture Input

CAPCOM2: CC27 Capture Input

XTAL2 137

XTAL1 138

O

I

XTAL2:

XTAL1:

Output of the oscillator amplifier circuit.

Input to the oscillator amplifier and input to

the internal clock generator

To clock the device from an external source, drive XTAL1,

while leaving XTAL2 unconnected. Minimum and maximum

high/low and rise/fall times specified in the AC

Characteristics must be observed.

Data Sheet

10

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

RSTIN 140

I/O

Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C167CR.

An internal pullup resistor permits power-on reset using only

a capacitor connected to V_SS.

A spike filter suppresses input pulses <10 ns. Input pulses

>100 ns safely pass the filter. The minimum duration for a

safe recognition should be 100 ns + 2 CPU clock cycles.

In bidirectional reset mode (enabled by setting bit BDRSTEN

in register SYSCON) the RSTIN line is internally pulled low

for the duration of the internal reset sequence upon any reset

(HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle and to

let the PLL lock a reset duration of ca. 1 ms is

recommended.

RST

OUT

141

142

O

I

Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or

a watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the C167CR to go into

power down mode. If NMI is high, when PWRDN is

executed, the part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

V_AREF37

V_AGND38

–

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

Data Sheet

11

V3.2, 2001-07

C167CR

C167SR

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

Input Function

Num. Outp.

V_DD

17, 46, –

Digital Supply Voltage:

56, 72,

82, 93,

109,

+5 V during normal operation and idle mode.

≥2.5 V during power down mode.

126,

136,

144

V_SS

18, 45, –

55, 71,

83, 94,

110,

Digital Ground.

127,

139,

143

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared

automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated as if it were a hardware reset. In particular, the

bootstrap loader may be activated when P0L.4 is low.

• Pin RSTIN may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet

12

V3.2, 2001-07

C167CR

C167SR

Functional Description

The architecture of the C167CR combines advantages of both RISC and CISC

processors and of advanced peripheral subsystems in a very well-balanced way. In

addition the on-chip memory blocks allow the design of compact systems with maximum

performance.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the C167CR.

Note: All time specifications refer to a CPU clock of 33 MHz

(see definition in the AC Characteristics section).

C166-Core

ProgMem

IRAM

Internal

RAM

16

Data

32

16

ROM

128/32

KByte

Instr. / Data

CPU

2 KByte

XTAL

Osc / PLL

WDT

XRAM

PEC

External Instr. / Data

2 KByte

16-Level

Priority

Interrupt Controller

16

Interrupt Bus

Peripheral Data Bus

16

CAN

Rev 2.0B active

ADC ASC0 SSC

GPT PWM CCOM2CCOM1

10-Bit

(USART)

(SPI)

T2

T3

T4

T7

T0

16

Channels

EBC

T8

T1

8

XBUS Control

External Bus

Control

16

T5

T6

BRGen

Port 0

Port 1

Port 5

Port 3

Port 7

8

Port 8

8

16

15

Figure 3

Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are

connected to the CPU via separate buses. A fourth bus, the XBUS, connects external

resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).

Data Sheet

13

V3.2, 2001-07

C167CR

C167SR

Memory Organization

The memory space of the C167CR is configured in a Von Neumann architecture which

means that code memory, data memory, registers and I/O ports are organized within the

same linear address space which includes 16 MBytes. The entire memory space can be

accessed bytewise or wordwise. Particular portions of the on-chip memory have

additionally been made directly bitaddressable.

The C167CR incorporates 128/32 KBytes (depending on the derivative) of on-chip

mask-programmable ROM for code or constant data. The lower 32 KBytes of the on-chip

ROM can be mapped either to segment 0 or segment 1.

2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined

variables, for the system stack, general purpose register banks and even for code. A

register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,

…, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are

used for controlling and monitoring functions of the different on-chip units. Unused SFR

addresses are reserved for future members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user

stacks, or code. The XRAM is accessed like external memory and therefore cannot be

used for the system stack or for register banks and is not bitaddressable. The XRAM

permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided

on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the

microcontroller.

Data Sheet

14

V3.2, 2001-07

C167CR

C167SR

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus

Controller (EBC). It can be programmed either to Single Chip Mode when no external

memory is required, or to one of four different external memory access modes, which are

as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/

output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses

and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,

Memory Tri-State Time, Length of ALE and Read Write Delay) have been made

programmable to allow the user the adaption of a wide range of different types of

memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs

ADDRSELx / BUSCONx) which control the access to different resources with different

bus characteristics. These address windows are arranged hierarchically where

BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to

locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 5 external CS signals (4 windows plus default) can be generated in order to save

external glue logic. The C167CR offers the possibility to switch the CS outputs to an

unlatched mode. In this mode the internal filter logic is switched off and the CS signals

are directly generated from the address. The unlatched CS mode is enabled by setting

CSCFG (SYSCON.6).

Access to very slow memories or memories with varying access times is supported via

a particular ‘Ready’ function.

A HOLD/HLDA protocol is available for bus arbitration and allows to share external

resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN

in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)

are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA

pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA

is switched to input. This allows to directly connect the slave controller to another master

controller without glue logic.

For applications which require less than 16 MBytes of external memory space, this

address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case

Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an

address space of 16 MBytes is used.

Data Sheet

15

V3.2, 2001-07

C167CR

C167SR

Note: When the on-chip CAN Module is to be used the segment address output on

Port 4 must be limited to 4 bits (i.e. A19 … A16) in order to enable the alternate

function of the CAN interface pins. CS lines can be used to increase the total

amount of addressable external memory.

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic

and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a

separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C167CR’s instructions can be

executed in just one machine cycle which requires 60 ns at 33 MHz CPU clock. For

example, shift and rotate instructions are always processed during one machine cycle

independent of the number of bits to be shifted. All multiple-cycle instructions have been

optimized so that they can be executed very fast as well: branches in 2 cycles, a

16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another

pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of

repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

CPU

16

Internal

RAM

SP

STKOV

STKUN

MDH

MDL

R15

Exec. Unit

Instr. Ptr.

Instr. Reg.

Mul/Div-HW

Bit-Mask Gen

General

Purpose

Registers

R15

ALU

32

4-Stage

Pipeline

(16-bit)

ROM

Barrel - Shifter

Context Ptr.

R0

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

16

R0

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Data Page Ptr.

Code Seg. Ptr.

MCB02147

Figure 4

CPU Block Diagram

Data Sheet

16

V3.2, 2001-07

C167CR

C167SR

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.

These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer

(CP) register determines the base address of the active register bank to be accessed by

the CPU at any time. The number of register banks is only restricted by the available

internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The

system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the

stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly

compared against the stack pointer value upon each stack access for the detection of a

stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently

be utilized by a programmer via the highly efficient C167CR instruction set which

includes the following instruction classes:

– Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes

and words. A variety of direct, indirect or immediate addressing modes are provided to

specify the required operands.

Data Sheet

17

V3.2, 2001-07

C167CR

C167SR

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of

internal program execution), the C167CR is capable of reacting very fast to the

occurrence of non-deterministic events.

The architecture of the C167CR supports several mechanisms for fast and flexible

response to service requests that can be generated from various sources internal or

external to the microcontroller. Any of these interrupt requests can be programmed to

being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is

suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a

single byte or word data transfer between any two memory locations with an additional

increment of either the PEC source or the destination pointer. An individual PEC transfer

counter is implicitly decremented for each PEC service except when performing in the

continuous transfer mode. When this counter reaches zero, a standard interrupt is

performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data.

The C167CR has 8 PEC channels each of which offers such fast interrupt-driven data

transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable

flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via

its related register, each source can be programmed to one of sixteen interrupt priority

levels. Once having been accepted by the CPU, an interrupt service can only be

interrupted by a higher prioritized service request. For the standard interrupt processing,

each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high

precision requirements. These fast interrupt inputs feature programmable edge

detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with

an individual trap (interrupt) number.

Table 3 shows all of the possible C167CR interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt

request bit (xIR).

Data Sheet

18

V3.2, 2001-07

C167CR

C167SR

Table 3

C167CR Interrupt Nodes

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Trap

Vector

Location Number

00’0040_H10_H

00’0044_H11_H

00’0048_H12_H

00’004C_H13_H

00’0050_H14_H

00’0054_H15_H

00’0058_H16_H

00’005C_H17_H

00’0060_H18_H

00’0064_H19_H

CAPCOM Register 0

CAPCOM Register 1

CAPCOM Register 2

CAPCOM Register 3

CAPCOM Register 4

CAPCOM Register 5

CAPCOM Register 6

CAPCOM Register 7

CAPCOM Register 8

CAPCOM Register 9

CC0IR

CC1IR

CC2IR

CC3IR

CC4IR

CC5IR

CC6IR

CC7IR

CC8IR

CC9IR

CC0IE

CC0INT

CC1INT

CC2INT

CC3INT

CC4INT

CC5INT

CC6INT

CC7INT

CC8INT

CC9INT

CC1IE

CC2IE

CC3IE

CC4IE

CC5IE

CC6IE

CC7IE

CC8IE

CC9IE

CAPCOM Register 10 CC10IR

CAPCOM Register 11 CC11IR

CAPCOM Register 12 CC12IR

CAPCOM Register 13 CC13IR

CAPCOM Register 14 CC14IR

CAPCOM Register 15 CC15IR

CAPCOM Register 16 CC16IR

CAPCOM Register 17 CC17IR

CAPCOM Register 18 CC18IR

CAPCOM Register 19 CC19IR

CAPCOM Register 20 CC20IR

CAPCOM Register 21 CC21IR

CAPCOM Register 22 CC22IR

CAPCOM Register 23 CC23IR

CAPCOM Register 24 CC24IR

CAPCOM Register 25 CC25IR

CAPCOM Register 26 CC26IR

CAPCOM Register 27 CC27IR

CAPCOM Register 28 CC28IR

CAPCOM Register 29 CC29IR

CC10IE

CC11IE

CC12IE

CC13IE

CC14IE

CC15IE

CC16IE

CC17IE

CC18IE

CC19IE

CC20IE

CC21IE

CC22IE

CC23IE

CC24IE

CC25IE

CC26IE

CC27IE

CC28IE

CC29IE

CC10INT 00’0068_H1A_H

CC11INT 00’006C_H1B_H

CC12INT 00’0070_H1C_H

CC13INT 00’0074_H1D_H

CC14INT 00’0078_H1E_H

CC15INT 00’007C_H1F_H

CC16INT 00’00C0_H30_H

CC17INT 00’00C4_H31_H

CC18INT 00’00C8_H32_H

CC19INT 00’00CC_H33_H

CC20INT 00’00D0_H34_H

CC21INT 00’00D4_H35_H

CC22INT 00’00D8_H36_H

CC23INT 00’00DC_H37_H

CC24INT 00’00E0_H38_H

CC25INT 00’00E4_H39_H

CC26INT 00’00E8_H3A_H

CC27INT 00’00EC_H3B_H

CC28INT 00’00E0_H3C_H

CC29INT 00’0110_H44_H

Data Sheet

19

V3.2, 2001-07

C167CR

C167SR

Table 3

C167CR Interrupt Nodes (cont’d)

Source of Interrupt or Request

PEC Service Request Flag

Enable

Flag

Interrupt Vector

Vector Location Number

Trap

CAPCOM Register 30 CC30IR

CAPCOM Register 31 CC31IR

CC30IE

CC31IE

T0IE

CC30INT 00’0114_H45_H

CC31INT 00’0118_H46_H

CAPCOM Timer 0

CAPCOM Timer 1

CAPCOM Timer 7

CAPCOM Timer 8

GPT1 Timer 2

T0IR

T1IR

T7IR

T8IR

T2IR

T3IR

T4IR

T5IR

T6IR

CRIR

ADCIR

T0INT

T1INT

T7INT

T8INT

T2INT

T3INT

T4INT

T5INT

T6INT

CRINT

ADCINT

00’0080_H20_H

00’0084_H21_H

00’00F4_H3D_H

00’00F8_H3E_H

00’0088_H22_H

00’008C_H23_H

00’0090_H24_H

00’0094_H25_H

00’0098_H26_H

00’009C_H27_H

00’00A0_H28_H

T1IE

T7IE

T8IE

T2IE

GPT1 Timer 3

T3IE

GPT1 Timer 4

T4IE

GPT2 Timer 5

T5IE

GPT2 Timer 6

T6IE

GPT2 CAPREL Reg.

CRIE

ADCIE

A/D Conversion

Complete

A/D Overrun Error

ASC0 Transmit

ADEIR

S0TIR

ADEIE

S0TIE

S0TBIE

S0RIE

S0EIE

SCTIE

SCRIE

SCEIE

PWMIE

XP0IE

XP1IE

XP2IE

XP3IE

ADEINT

S0TINT

00’00A4_H29_H

00’00A8_H2A_H

ASC0 Transmit Buffer S0TBIR

S0TBINT 00’011C_H47_H

ASC0 Receive

ASC0 Error

S0RIR

S0EIR

SCTIR

SCRIR

SCEIR

PWMIR

XP0IR

XP1IR

XP2IR

XP3IR

S0RINT

S0EINT

SCTINT

SCRINT

SCEINT

00’00AC_H2B_H

00’00B0_H2C_H

00’00B4_H2D_H

00’00B8_H2E_H

00’00BC_H2F_H

SSC Transmit

SSC Receive

SSC Error

PWM Channel 0 … 3

CAN Interface 1

Unassigned node

PLL/OWD

PWMINT 00’00FC_H3F_H

XP0INT

XP1INT

XP2INT

XP3INT

00’0100_H40_H

00’0104_H41_H

00’0108_H42_H

00’010C_H43_H

Data Sheet

20

V3.2, 2001-07

C167CR

C167SR

The C167CR also provides an excellent mechanism to identify and to process

exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.

Hardware traps cause immediate non-maskable system reaction which is similar to a

standard interrupt service (branching to a dedicated vector table location). The

occurrence of a hardware trap is additionally signified by an individual bit in the trap flag

register (TFR). Except when another higher prioritized trap service is in progress, a

hardware trap will interrupt any actual program execution. In turn, hardware trap services

can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

–

– Hardware Reset

– Software Reset

– W-dog Timer Overflow

RESET

00’0000_H

00_H

III

Class A Hardware Traps:

– Non-Maskable Interrupt NMI

NMITRAP 00’0008_H

STOTRAP 00’0010_H

STUTRAP 00’0018_H

02_H

04_H

06_H

II

– Stack Overflow

– Stack Underflow

STKOF

STKUF

Class B Hardware Traps:

– Undefined Opcode

– Protected Instruction

Fault

UNDOPC BTRAP

PRTFLT BTRAP

00’0028_H

0A_H

I

– Illegal Word Operand

Access

– Illegal Instruction

Access

– Illegal External Bus

Access

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028_H

0A_H

I

Reserved

–

[2C_H–

3C_H]

[0B_H–

0F_H]

–

Software Traps

– TRAP Instruction

Any

Current

CPU

Priority

[00’0000_H– [00_H–

00’01FC_H] 7F_H]

in steps

of 4_H

Data Sheet

21

V3.2, 2001-07

C167CR

C167SR

Capture/Compare (CAPCOM) Units

The CAPCOM units support generation and control of timing sequences on up to

32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically

used to handle high speed I/O tasks such as pulse and waveform generation, pulse

width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time

recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time

bases for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal

system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows

precise adjustments to the application specific requirements. In addition, external count

inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare

registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/

compare registers, each of which may be individually allocated to either CAPCOM timer

T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.

Each register has one port pin associated with it which serves as an input pin for

triggering the capture function, or as an output pin (except for CC24 … CC27) to indicate

the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current

contents of the allocated timer will be latched (‘captured’) into the capture/compare

register in response to an external event at the port pin which is associated with this

register. In addition, a specific interrupt request for this capture/compare register is

generated. Either a positive, a negative, or both a positive and a negative external signal

transition at the pin can be selected as the triggering event. The contents of all registers

which have been selected for one of the five compare modes are continuously compared

with the contents of the allocated timers. When a match occurs between the timer value

and the value in a capture/compare register, specific actions will be taken based on the

selected compare mode.

Data Sheet

22

V3.2, 2001-07

C167CR

C167SR

Table 5

Compare Modes (CAPCOM)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1

Mode 2

Mode 3

Pin toggles on each compare match;

several compare events per timer period are possible

Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double

Two registers operate on one pin;

Register Mode

pin toggles on each compare match;

several compare events per timer period are possible.

Data Sheet

23

V3.2, 2001-07

C167CR

C167SR

Reload Reg. TxREL

CAPCOM Timer Tx

f_CPU

TxIN

2ⁿ: 1

Tx

Input

Control

Interrupt

Request

(TxIR)

GPT2 Timer T6

Over/Underflow

CCxIO

Mode

Control

(Capture

or

16-Bit

16 Capture Inputs

16 Compare Outputs

Capture/

Compare

Registers

16 Capture/Compare

Interrupt Request

Compare)

CCxIO

f_CPU

2ⁿ: 1

Ty

Input

Control

Interrupt

Request

(TyIR)

CAPCOM Timer Ty

Reload Reg. TyREL

GPT2 Timer T6

Over/Underflow

MCB02143B

x = 0, 7

y = 1, 8

n = 3 … 10

Figure 5

CAPCOM Unit Block Diagram

PWM Module

The Pulse Width Modulation Module can generate up to four PWM output signals using

edge-aligned or center-aligned PWM. In addition the PWM module can generate PWM

burst signals and single shot outputs. The frequency range of the PWM signals covers

4 Hz to 16.5 MHz (referred to a CPU clock of 33 MHz), depending on the resolution of

the PWM output signal. The level of the output signals is selectable and the PWM

module can generate interrupt requests.

Data Sheet

24

V3.2, 2001-07

C167CR

C167SR

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which

may be used for many different time related tasks such as event timing and counting,

pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate

modules, GPT1 and GPT2. Each timer in each module may operate independently in a

number of different modes, or may be concatenated with another timer of the same

module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for

one of four basic modes of operation, which are Timer, Gated Timer, Counter, and

Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from

the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer

to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the

operation of a timer is controlled by the ‘gate’ level on an external input pin. For these

purposes, each timer has one associated port pin (TxIN) which serves as gate or clock

input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD) to

facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected

to the incremental position sensor signals A and B via their respective inputs TxIN and

TxEUD. Direction and count signals are internally derived from these two input signals,

so the contents of the respective timer Tx corresponds to the sensor position. The third

position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-

flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out

monitoring of external hardware components, or may be used internally to clock timers

T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload

or capture registers for timer T3. When used as capture or reload registers, timers T2

and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a

signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2

or T4 triggered either by an external signal or by a selectable state transition of its toggle

latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite

state transitions of T3OTL with the low and high times of a PWM signal, this signal can

be constantly generated without software intervention.

Data Sheet

25

V3.2, 2001-07

C167CR

C167SR

T2EUD

f_CPU

T2IN

U/D

Interrupt

Request

2ⁿ: 1

GPT1 Timer T2

T2

Mode

Control

Reload

Capture

Interrupt

Request

f_CPU

2ⁿ: 1

Toggle FF

T3OTL

T3

Mode

Control

T3IN

GPT1 Timer T3

T3OUT

U/D

T3EUD

Other

Timers

Capture

Reload

T4IN

T4

Mode

Control

Interrupt

Request

2ⁿ: 1

GPT1 Timer T4

U/D

f_CPU

T4EUD

MCT02141

n = 3 … 10

Figure 6

Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control

and time measurement. It includes two timers (T5, T6) and a capture/reload register

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU

clock via a programmable prescaler or with external signals. The count direction (up/

down) for each timer is programmable by software or may additionally be altered

dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is

supported via the output toggle latch (T6OTL) of timer T6, which changes its state on

each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin

T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the

CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The

CAPREL register may capture the contents of timer T5 based on an external signal

transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared

after the capture procedure. This allows the C167CR to measure absolute time

differences or to perform pulse multiplication without software overhead.

Data Sheet

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V3.2, 2001-07

C167CR

C167SR

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of

GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3

operates in Incremental Interface Mode.

T5EUD

f_CPU

T5IN

2ⁿ: 1

T5

Mode

Control

U/D

Interrupt

Request

GPT2 Timer T5

Clear

Capture

Interrupt

Request

T3

MUX

CT3

CAPIN

GPT2 CAPREL

Interrupt

Request

GPT2 Timer T6

U/D

T6OTL

T6OUT

T6IN

T6

Mode

Control

Other

Timers

f_CPU

2ⁿ: 1

T6EUD

MCB03999

n = 2 … 9

Figure 7

Block Diagram of GPT2

Data Sheet

27

V3.2, 2001-07

C167CR

C167SR

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input

channels and a sample and hold circuit has been integrated on-chip. It uses the method

of successive approximation. The sample time (for loading the capacitors) and the

conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register

(ADDAT): either an interrupt request will be generated when the result of a previous

conversion has not been read from the result register at the time the next conversion is

complete, or the next conversion is suspended in such a case until the previous result

has been read.

For applications which require less than 16 analog input channels, the remaining

channel inputs can be used as digital input port pins.

The A/D converter of the C167CR supports four different conversion modes. In the

standard Single Channel conversion mode, the analog level on a specified channel is

sampled once and converted to a digital result. In the Single Channel Continuous mode,

the analog level on a specified channel is repeatedly sampled and converted without

software intervention. In the Auto Scan mode, the analog levels on a prespecified

number of channels are sequentially sampled and converted. In the Auto Scan

Continuous mode, the number of prespecified channels is repeatedly sampled and

converted. In addition, the conversion of a specific channel can be inserted (injected) into

a running sequence without disturbing this sequence. This is called Channel Injection

Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the

conversion results into a table in memory for later evaluation, without requiring the

overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs

calibration cycles. This automatic self-calibration constantly adjusts the converter to

changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal

operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise

those pins used for analog input can be disconnected from the digital IO or input stages

under software control. This can be selected for each pin separately via register P5DIDIS

(Port 5 Digital Input Disable).

Data Sheet

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V3.2, 2001-07

C167CR

C167SR

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external

peripheral components is provided by two serial interfaces with different functionality, an

Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous

Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller

families and supports full-duplex asynchronous communication at up to 781 Kbit/s/

1.03 Mbit/s and half-duplex synchronous communication at up to 3.1/4.1 Mbit/s (@ 25/

33 MHz CPU clock).

A dedicated baud rate generator allows to set up all standard baud rates without

oscillator tuning. For transmission, reception and error handling 4 separate interrupt

vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or

received, preceded by a start bit and terminated by one or two stop bits. For

multiprocessor communication, a mechanism to distinguish address from data bytes has

been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a

shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop

back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated, if the last

character received has not been read out of the receive buffer register at the time the

reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25/8.25 Mbit/s

(@ 25/33 MHz CPU clock). It may be configured so it interfaces with serially linked

peripheral components. A dedicated baud rate generator allows to set up all standard

baud rates without oscillator tuning. For transmission, reception, and error handling three

separate interrupt vectors are provided.

The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift

clock which can be generated by the SSC (master mode) or by an external master (slave

mode). The SSC can start shifting with the LSB or with the MSB and allows the selection

of shifting and latching clock edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. Transmit and receive error supervise the correct handling

of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet

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V3.2, 2001-07

C167CR

C167SR

CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and

reception of CAN frames in accordance with the CAN specification V2.0 part B (active),

i.e. the on-chip CAN-Module can receive and transmit standard frames with 11-bit

identifiers as well as extended frames with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message

object 15 may be configured for Basic CAN functionality. Both modes provide separate

masks for acceptance filtering which allows to accept a number of identifiers in Full CAN

mode and also allows to disregard a number of identifiers in Basic CAN mode. All

message objects can be updated independent from the other objects and are equipped

for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/

s. The CAN-Module uses two pins of Port 4 to interface to an external bus transceiver.

Note: When the CAN interface is to be used the segment address output on Port 4 must

be limited to 4 bits, i.e. A19 … A16. This is necessary to enable the alternate

function of the CAN interface pins.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be

disabled in the time interval until the EINIT (end of initialization) instruction has been

executed. Thus, the chip’s start-up procedure is always monitored. The software has to

be designed to service the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2

or by 128. The high byte of the Watchdog Timer register can be set to a prespecified

reload value (stored in WDTREL) in order to allow further variation of the monitored time

interval. Each time it is serviced by the application software, the high byte of the

Watchdog Timer is reloaded. Thus, time intervals between 15.5 µs and 254 ms can be

monitored (@ 33 MHz).

The default Watchdog Timer interval after reset is 3.97 ms (@ 33 MHz).

Data Sheet

30

V3.2, 2001-07

C167CR

C167SR

Parallel Ports

The C167CR provides up to 111 I/O lines which are organized into eight input/output

ports and one input port. All port lines are bit-addressable, and all input/output lines are

individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O

ports are true bidirectional ports which are switched to high impedance state when

configured as inputs. The output drivers of five I/O ports can be configured (pin by pin)

for push/pull operation or open-drain operation via control registers. During the internal

reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 7, and Port 8 is selectable (TTL or CMOS like),

where the special CMOS like input threshold reduces noise sensitivity due to the input

hysteresis. The input threshold may be selected individually for each byte of the

respective ports.

All port lines have programmable alternate input or output functions associated with

them. All port lines that are not used for these alternate functions may be used as general

purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external

memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in

systems where segmentation is enabled to access more than 64 KBytes of memory.

Port 2, Port 8 and Port 7 (and parts of PORT1) are associated with the capture inputs or

compare outputs of the CAPCOM units and/or with the outputs of the PWM module.

Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select

signals.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control

signal BHE/WRH, and the system clock output (CLKOUT).

Port 5 is used for the analog input channels to the A/D converter or timer control signals.

The edge characteristics (transition time) of the C167CR’s port drivers can be selected

via the Port Driver Control Register (PDCR). Two bits select fast edges (‘0’) or reduced

edges (‘1’) for bus interface pins and non-bus pins separately.

PDCR.0 = BIPEC controls PORT0, PORT1, Port 4, RD, WR, ALE, CLKOUT, BHE/WRH.

PDCR.4 = NBPEC controls Port 3, Port 8, RSTOUT, RSTIN (bidir. reset mode).

Data Sheet

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V3.2, 2001-07

C167CR

C167SR

Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip

oscillator (either with a crystal or via external clock drive). For this operation the PLL

provides a clock signal which is used to supervise transitions on the oscillator clock. This

PLL clock is independent from the XTAL1 clock. When the expected oscillator clock

transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and

supplies the CPU with the PLL clock signal. Under these circumstances the PLL will

oscillate with its basic frequency.

In direct drive mode the PLL base frequency is used directly (f_CPU= 2 … 5 MHz).

In prescaler mode the PLL base frequency is divided by 2 (f_CPU= 1 … 2.5 MHz).

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled via hardware by (externally) pulling low pin

OWE (internal pullup provides high level if not connected). In this case (OWE = ‘0’) the

PLL remains idle and provides no clock signal, while the CPU clock signal is derived

directly from the oscillator clock or via prescaler. Also no interrupt request will be

generated in case of a missing oscillator clock.

Data Sheet

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V3.2, 2001-07

C167CR

C167SR

Instruction Set Summary

Table 6 lists the instructions of the C167CR in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation

of the instructions, parameters for conditional execution of instructions, and the opcodes

for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Table 6

Mnemonic

ADD(B)

ADDC(B)

SUB(B)

SUBC(B)

MUL(U)

DIV(U)

Instruction Set Summary

Description

Bytes

2 / 4

Add word (byte) operands

Add word (byte) operands with Carry

Subtract word (byte) operands

Subtract word (byte) operands with Carry

(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

DIVL(U)

CPL(B)

NEG(B)

AND(B)

OR(B)

Complement direct word (byte) GPR

Negate direct word (byte) GPR

Bitwise AND, (word/byte operands)

Bitwise OR, (word/byte operands)

Bitwise XOR, (word/byte operands)

Clear direct bit

2

2 / 4

2

XOR(B)

BCLR

BSET

Set direct bit

2

BMOV(N)

Move (negated) direct bit to direct bit

AND/OR/XOR direct bit with direct bit

4

BAND, BOR,

BXOR

4

BCMP

Compare direct bit to direct bit

4

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

Compare word (byte) operands

2 / 4

Compare word data to GPR and decrement GPR by 1/2 2 / 4

Compare word data to GPR and increment GPR by 1/2

2 / 4

2

Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR

SHL / SHR

ROL / ROR

ASHR

Shift left/right direct word GPR

2

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

Data Sheet

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V3.2, 2001-07

C167CR

C167SR

Table 6

Instruction Set Summary (cont’d)

Description

Mnemonic

MOV(B)

MOVBS

MOVBZ

Bytes

Move word (byte) data

2 / 4

Move byte operand to word operand with sign extension 2 / 4

Move byte operand to word operand with zero extension 2 / 4

JMPA, JMPI,

JMPR

Jump absolute/indirect/relative if condition is met

4

JMPS

J(N)B

JBC

Jump absolute to a code segment

4

Jump relative if direct bit is (not) set

Jump relative and clear bit if direct bit is set

Jump relative and set bit if direct bit is not set

JNBS

CALLA, CALLI,

CALLR

Call absolute/indirect/relative subroutine if condition is met 4

CALLS

PCALL

Call absolute subroutine in any code segment

4

Push direct word register onto system stack and call

absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

Push/pop direct word register onto/from system stack

2

4

PUSH, POP

SCXT

Push direct word register onto system stack and update

register with word operand

RET

Return from intra-segment subroutine

Return from inter-segment subroutine

2

RETS

RETP

Return from intra-segment subroutine and pop direct

word register from system stack

RETI

Return from interrupt service subroutine

Software Reset

2

SRST

4

IDLE

Enter Idle Mode

4

PWRDN

SRVWDT

DISWDT

EINIT

Enter Power Down Mode (supposes NMI-pin being low)

Service Watchdog Timer

4

Disable Watchdog Timer

4

Signify End-of-Initialization on RSTOUT-pin

Begin ATOMIC sequence

4

ATOMIC

EXTR

2

Begin EXTended Register sequence

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

Null operation

2

EXTP(R)

EXTS(R)

NOP

2 / 4

2

Data Sheet

34

V3.2, 2001-07

C167CR

C167SR

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C167CR in alphabetical

order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the

Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical

Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column

“Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected

addressing mode, an SFR can be accessed via its physical address (using the Data

Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Note: Registers within device specific interface modules (CAN) are only present in the

corresponding device, of course.

Table 7

Name

C167CR Registers, Ordered by Name

Physical 8-Bit Description

Reset

Value

Address

Addr.

ADCIC

b FF98_H

CC_HA/D Converter End of Conversion

Interrupt Control Register

0000_H

ADCON

b FFA0_H

D0_H

50_H

A/D Converter Control Register

A/D Converter Result Register

A/D Converter 2 Result Register

Address Select Register 1

Address Select Register 2

Address Select Register 3

Address Select Register 4

0000_H

ADDAT

FEA0_H

ADDAT2

F0A0_HE 50_H

ADDRSEL1

ADDRSEL2

ADDRSEL3

ADDRSEL4

ADEIC

FE18_H

FE1A_H

0C_H

0D_H

0E_H

0F_H

FE1C_H

FE1E_H

b FF9A_H

CD_HA/D Converter Overrun Error Interrupt

Control Register

BUSCON0 b FF0C_H

BUSCON1 b FF14_H

BUSCON2 b FF16_H

BUSCON3 b FF18_H

BUSCON4 b FF1A_H

86_H

8A_H

8B_H

8C_H

8D_H

Bus Configuration Register 0

Bus Configuration Register 1

Bus Configuration Register 2

Bus Configuration Register 3

Bus Configuration Register 4

CAN1 Bit Timing Register

CAN1 Control / Status Register

CAN1 Global Mask Short

0XX0_H

0000_H

UUUU_H

XX01_H

UFUU_H

XX_H

C1BTR

C1CSR

C1GMS

C1IR

EF04_HX ---

EF00_HX ---

EF06_HX ---

EF02_HX ---

CAN1 Interrupt Register

Data Sheet

35

V3.2, 2001-07

C167CR

C167SR

Table 7

Name

C167CR Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

C1LGML

C1LMLM

C1UAR

EF0A_HX ---

EF0E_HX ---

EFn2_HX ---

CAN1 Lower Global Mask Long

UUUU_H

CAN1 Lower Mask of Last Message

CAN1 Upper Arbitration Register

(message n)

C1UGML

C1UMLM

CAPREL

CC0

EF08_HX ---

EF0C_HX ---

CAN1 Upper Global Mask Long

CAN1 Upper Mask of Last Message

GPT2 Capture/Reload Register

CAPCOM Register 0

UUUU_H

0000_H

FE4A_H

FE80_H

25_H

40_H

CC0IC

CC1

b FF78_H

FE82_H

BC_HCAPCOM Register 0 Interrupt Ctrl. Reg.

41_H

4A_H

C6_H

4B_H

C7_H

4C_H

C8_H

4D_H

C9_H

4E_H

CAPCOM Register 1

CC10

FE94_H

CAPCOM Register 10

CC10IC

CC11

b FF8C_H

FE96_H

CAPCOM Reg. 10 Interrupt Ctrl. Reg.

CAPCOM Register 11

CC11IC

CC12

b FF8E_H

FE98_H

CAPCOM Reg. 11 Interrupt Ctrl. Reg.

CAPCOM Register 12

CC12IC

CC13

b FF90_H

FE9A_H

CAPCOM Reg. 12 Interrupt Ctrl. Reg.

CAPCOM Register 13

CC13IC

CC14

b FF92_H

FE9C_H

CAPCOM Reg. 13 Interrupt Ctrl. Reg.

CAPCOM Register 14

CC14IC

CC15

b FF94_H

FE9E_H

CA_HCAPCOM Reg. 14 Interrupt Ctrl. Reg.

4F_HCAPCOM Register 15

CB_HCAPCOM Reg. 15 Interrupt Ctrl. Reg.

CC15IC

CC16

b FF96_H

FE60_H

30_H

CAPCOM Register 16

CC16IC

CC17

b F160_HE B0_H

FE62_H31_H

b F162_HE B1_H

FE64_H32_H

b F164_HE B2_H

FE66_H33_H

b F166_HE B3_H

CAPCOM Reg. 16 Interrupt Ctrl. Reg.

CAPCOM Register 17

CC17IC

CC18

CAPCOM Reg. 17 Interrupt Ctrl. Reg.

CAPCOM Register 18

CC18IC

CC19

CAPCOM Reg. 18 Interrupt Ctrl. Reg.

CAPCOM Register 19

CC19IC

CAPCOM Reg. 19 Interrupt Ctrl. Reg.

Data Sheet

36

V3.2, 2001-07

C167CR

C167SR

Table 7

Name

C167CR Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

b FF7A_H

FE84_H

Addr.

CC1IC

CC2

BD_HCAPCOM Reg. 1 Interrupt Ctrl. Reg.

0000_H

42_H

34_H

CAPCOM Register 2

CC20

FE68_H

CAPCOM Register 20

CC20IC

CC21

b F168_HE B4_H

FE6A_H35_H

b F16A_HE B5_H

FE6C_H36_H

b F16C_HE B6_H

FE6E_H37_H

b F16E_HE B7_H

FE70_H38_H

b F170_HE B8_H

FE72_H39_H

b F172_HE B9_H

FE74_H3A_H

b F174_HE BA_H

FE76_H3B_H

b F176_HE BB_H

FE78_H3C_H

CAPCOM Reg. 20 Interrupt Ctrl. Reg.

CAPCOM Register 21

CC21IC

CC22

CAPCOM Reg. 21 Interrupt Ctrl. Reg.

CAPCOM Register 22

CC22IC

CC23

CAPCOM Reg. 22 Interrupt Ctrl. Reg.

CAPCOM Register 23

CC23IC

CC24

CAPCOM Reg. 23 Interrupt Ctrl. Reg.

CAPCOM Register 24

CC24IC

CC25

CAPCOM Reg. 24 Interrupt Ctrl. Reg.

CAPCOM Register 25

CC25IC

CC26

CAPCOM Reg. 25 Interrupt Ctrl. Reg.

CAPCOM Register 26

CC26IC

CC27

CAPCOM Reg. 26 Interrupt Ctrl. Reg.

CAPCOM Register 27

CC27IC

CC28

CAPCOM Reg. 27 Interrupt Ctrl. Reg.

CAPCOM Register 28

CC28IC

CC29

b F178_HE BC_HCAPCOM Reg. 28 Interrupt Ctrl. Reg.

FE7A_H

3D_H

CAPCOM Register 29

CC29IC

CC2IC

CC3

b F184_HE C2_H

CAPCOM Reg. 29 Interrupt Ctrl. Reg.

CAPCOM Reg. 2 Interrupt Ctrl. Reg.

CAPCOM Register 3

b FF7C_H

FE86_H

BE_H

43_H

3E_H

CC30

FE7C_H

CAPCOM Register 30

CC30IC

CC31

b F18C_HE C6_H

FE7E_H3F_H

CAPCOM Reg. 30 Interrupt Ctrl. Reg.

CAPCOM Register 31

CC31IC

CC3IC

CC4

b F194_HE CA_HCAPCOM Reg. 31 Interrupt Ctrl. Reg.

b FF7E_H

BF_H

44_H

CAPCOM Reg. 3 Interrupt Ctrl. Reg.

CAPCOM Register 4

FE88_H

Data Sheet

37

V3.2, 2001-07

C167CR

C167SR

Table 7

Name

C167CR Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

C0_H

45_H

CC4IC

CC5

b FF80_H

CAPCOM Reg. 4 Interrupt Ctrl. Reg.

CAPCOM Register 5

0000_H

FE8A_H

CC5IC

b FF82_H

C1_H

CAPCOM Register 5 Interrupt Control

Register

CC6

FE8C_H

b FF84_H

FE8E_H

46_H

C2_H

47_H

C3_H

48_H

C4_H

49_H

C5_H

A9_H

AA_H

AB_H

CAPCOM Register 6

0000_H

FC00_H

0000_H

CC6IC

CC7

CAPCOM Reg. 6 Interrupt Ctrl. Reg.

CAPCOM Register 7

CC7IC

CC8

b FF86_H

FE90_H

CAPCOM Reg. 7 Interrupt Ctrl. Reg.

CAPCOM Register 8

CC8IC

CC9

b FF88_H

FE92_H

CAPCOM Reg. 8 Interrupt Ctrl. Reg.

CAPCOM Register 9

CC9IC

CCM0

CCM1

CCM2

CCM3

CCM4

CCM5

CCM6

CCM7

CP

b FF8A_H

b FF52_H

b FF54_H

b FF56_H

b FF58_H

b FF22_H

b FF24_H

b FF26_H

b FF28_H

FE10_H

CAPCOM Reg. 9 Interrupt Ctrl. Reg.

CAPCOM Mode Control Register 0

CAPCOM Mode Control Register 1

CAPCOM Mode Control Register 2

AC_HCAPCOM Mode Control Register 3

91_H

92_H

93_H

94_H

08_H

B5_H

04_H

CAPCOM Mode Control Register 4

CAPCOM Mode Control Register 5

CAPCOM Mode Control Register 6

CAPCOM Mode Control Register 7

CPU Context Pointer Register

CRIC

CSP

b FF6A_H

FE08_H

GPT2 CAPREL Interrupt Ctrl. Register

CPU Code Segment Pointer Register

(read only)

DP0L

DP0H

DP1L

DP1H

DP2

b F100_HE 80_H

b F102_HE 81_H

b F104_HE 82_H

b F106_HE 83_H

P0L Direction Control Register

P0H Direction Control Register

P1L Direction Control Register

P1H Direction Control Register

Port 2 Direction Control Register

Port 3 Direction Control Register

00_H

b FFC2_H

b FFC6_H

E1_H

E3_H

0000_H

DP3

Data Sheet

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V3.2, 2001-07

C167CR

C167SR

Table 7

Name

C167CR Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

b FFCA_H

b FFCE_H

b FFD2_H

b FFD6_H

FE00_H

Addr.

E5_H

E7_H

E9_H

EB_H

00_H

01_H

02_H

03_H

DP4

Port 4 Direction Control Register

Port 6 Direction Control Register

Port 7 Direction Control Register

Port 8 Direction Control Register

CPU Data Page Pointer 0 Reg. (10 bits)

CPU Data Page Pointer 1 Reg. (10 bits)

CPU Data Page Pointer 2 Reg. (10 bits)

CPU Data Page Pointer 3 Reg. (10 bits)

External Interrupt Control Register

CPU Multiply Divide Control Register

CPU Multiply Divide Reg. – High Word

CPU Multiply Divide Reg. – Low Word

Port 2 Open Drain Control Register

Port 3 Open Drain Control Register

Port 6 Open Drain Control Register

Port 7 Open Drain Control Register

Port 8 Open Drain Control Register

Constant Value 1’s Register (read only)

Port 0 High Reg. (Upper half of PORT0)

Port 0 Low Reg. (Lower half of PORT0)

Port 1 High Reg. (Upper half of PORT1)

Port 1 Low Reg. (Lower half of PORT1)

Port 2 Register

00_H

DP6

DP7

00_H

DP8

00_H

DPP0

DPP1

DPP2

DPP3

EXICON

MDC

MDH

MDL

ODP2

ODP3

ODP6

ODP7

ODP8

ONES

P0H

0000_H

0001_H

0002_H

0003_H

0000_H

00_H

FE02_H

FE04_H

FE06_H

b F1C0_HE E0_H

b FF0E_H

FE0C_H

87_H

06_H

07_H

FE0E_H

b F1C2_HE E1_H

b F1C6_HE E3_H

b F1CE_HE E7_H

b F1D2_HE E9_H

b F1D6_HE EB_H

00_H

FF1E_H

b FF02_H

b FF00_H

b FF06_H

b FF04_H

b FFC0_H

b FFC4_H

b FFC8_H

b FFA2_H

8F_H

81_H

80_H

83_H

82_H

E0_H

E2_H

E4_H

D1_H

D2_H

E6_H

E8_H

EA_H

FFFF_H

00_H

P0L

00_H

P1H

00_H

P1L

00_H

P2

0000_H

00_H

P3

Port 3 Register

P4

Port 4 Register (8 bits)

P5

Port 5 Register (read only)

XXXX_H

0000_H

00_H

P5DIDIS b FFA4_H

Port 5 Digital Input Disable Register

Port 6 Register (8 bits)

P6

P7

P8

b FFCC_H

b FFD0_H

b FFD4_H

Port 7 Register (8 bits)

00_H

Port 8 Register (8 bits)

00_H

Data Sheet

39

V3.2, 2001-07

C167CR

C167SR

Table 7

Name

C167CR Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

FEC0_H

FEC2_H

FEC4_H

FEC6_H

FEC8_H

FECA_H

FECC_H

FECE_H

Addr.

60_H

61_H

62_H

63_H

64_H

65_H

66_H

67_H

PECC0

PECC1

PECC2

PECC3

PECC4

PECC5

PECC6

PECC7

PICON

PDCR

PP0

PEC Channel 0 Control Register

PEC Channel 1 Control Register

PEC Channel 2 Control Register

PEC Channel 3 Control Register

PEC Channel 4 Control Register

PEC Channel 5 Control Register

PEC Channel 6 Control Register

PEC Channel 7 Control Register

Port Input Threshold Control Register

Pin Driver Control Register

0000_H

XX_H

b F1C4_HE E2_H

F0AA_HE 55_H

F038_HE 1C_H

F03A_HE 1D_H

F03C_HE 1E_H

F03E_HE 1F_H

PWM Module Period Register 0

PWM Module Period Register 1

PWM Module Period Register 2

PWM Module Period Register 3

CPU Program Status Word

PP1

PP2

PP3

PSW

b FF10_H

88_H

PT0

F030_HE 18_H

F032_HE 19_H

F034_HE 1A_H

F036_HE 1B_H

PWM Module Up/Down Counter 0

PWM Module Up/Down Counter 1

PWM Module Up/Down Counter 2

PWM Module Up/Down Counter 3

PWM Module Pulse Width Register 0

PWM Module Pulse Width Register 1

PWM Module Pulse Width Register 2

PWM Module Pulse Width Register 3

PWM Module Control Register 0

PWM Module Control Register 1

PWM Module Interrupt Control Register

System Start-up Config. Reg. (Rd. only)

PT1

PT2

PT3

PW0

FE30_H

FE32_H

FE34_H

FE36_H

18_H

19_H

1A_H

1B_H

98_H

99_H

PW1

PW2

PW3

PWMCON0b FF30_H

PWMCON1b FF32_H

PWMIC

RP0H

b F17E_HE BF_H

b F108_HE 84_H

S0BG

FEB4_H

5A_H

Serial Channel 0 Baudrate Generator

Reload Register

0000_H

S0CON

b FFB0_H

D8_H

Serial Channel 0 Control Register

0000_H

Data Sheet

40

V3.2, 2001-07

C167CR

C167SR

Table 7

Name

C167CR Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

S0EIC

b FF70_H

B8_H

Serial Chan. 0 Error Interrupt Ctrl. Reg.

0000_H

XX_H

S0RBUF

FEB2_H

59_H

Serial Channel 0 Receive Buffer Reg.

(read only)

S0RIC

b FF6E_H

B7_H

Serial Channel 0 Receive Interrupt

Control Register

0000_H

00_H

S0TBIC

S0TBUF

S0TIC

b F19C_HE CE_HSerial Channel 0 Transmit Buffer

Interrupt Control Register

FEB0_H

b FF6C_H

FE12_H

58_H

B6_H

09_H

Serial Channel 0 Transmit Buffer Reg.

(write only)

Serial Channel 0 Transmit Interrupt

Control Register

0000_H

SP

CPU System Stack Pointer Register

SSC Baudrate Register

FC00_H

0000_H

XXXX_H

0000_H

FA00_H

FC00_H

¹⁾0xx0_H

0000_H

SSCBR

F0B4_HE 5A_H

SSCCON b FFB2_H

D9_H

BB_H

SSC Control Register

SSCEIC

SSCRB

SSCRIC

SSCTB

SSCTIC

STKOV

STKUN

b FF76_H

SSC Error Interrupt Control Register

SSC Receive Buffer

F0B2_HE 59_H

b FF74_H

BA_H

SSC Receive Interrupt Control Register

SSC Transmit Buffer

F0B0_HE 58_H

b FF72_H

B9_H

0A_H

0B_H

89_H

28_H

A8_H

SSC Transmit Interrupt Control Register

CPU Stack Overflow Pointer Register

CPU Stack Underflow Pointer Register

CPU System Configuration Register

CAPCOM Timer 0 Register

FE14_H

FE16_H

SYSCON b FF12_H

T0 FE50_H

T01CON b FF50_H

CAPCOM Timer 0 and Timer 1 Ctrl. Reg.

T0IC

T0REL

T1

b FF9C_H

FE54_H

CE_HCAPCOM Timer 0 Interrupt Ctrl. Reg.

2A_H

29_H

CF_H

2B_H

20_H

A0_H

CAPCOM Timer 0 Reload Register

CAPCOM Timer 1 Register

FE52_H

T1IC

T1REL

T2

b FF9E_H

FE56_H

CAPCOM Timer 1 Interrupt Ctrl. Reg.

CAPCOM Timer 1 Reload Register

GPT1 Timer 2 Register

FE40_H

T2CON

b FF40_H

GPT1 Timer 2 Control Register

Data Sheet

41

V3.2, 2001-07

C167CR

C167SR

Table 7

Name

C167CR Registers, Ordered by Name (cont’d)

Physical 8-Bit Description

Reset

Value

Address

Addr.

B0_H

21_H

A1_H

B1_H

22_H

A2_H

B2_H

23_H

A3_H

B3_H

24_H

A4_H

B4_H

T2IC

T3

b FF60_H

GPT1 Timer 2 Interrupt Control Register

GPT1 Timer 3 Register

0000_H

²⁾00XX_H

0000_H

FE42_H

b FF42_H

b FF62_H

FE44_H

T3CON

T3IC

T4

GPT1 Timer 3 Control Register

GPT1 Timer 3 Interrupt Control Register

GPT1 Timer 4 Register

T4CON

T4IC

T5

b FF44_H

b FF64_H

FE46_H

GPT1 Timer 4 Control Register

GPT1 Timer 4 Interrupt Control Register

GPT2 Timer 5 Register

T5CON

T5IC

T6

b FF46_H

b FF66_H

FE48_H

GPT2 Timer 5 Control Register

GPT2 Timer 5 Interrupt Control Register

GPT2 Timer 6 Register

T6CON

T6IC

T7

b FF48_H

b FF68_H

GPT2 Timer 6 Control Register

GPT2 Timer 6 Interrupt Control Register

CAPCOM Timer 7 Register

F050_HE 28_H

T78CON b FF20_H

90_H

CAPCOM Timer 7 and 8 Ctrl. Reg.

CAPCOM Timer 7 Interrupt Ctrl. Reg.

CAPCOM Timer 7 Reload Register

CAPCOM Timer 8 Register

T7IC

b F17A_HE BE_H

F054_HE 2A_H

T7REL

T8

F052_HE 29_H

b F17C_HE BF_H

F056_HE 2B_H

T8IC

CAPCOM Timer 8 Interrupt Ctrl. Reg.

CAPCOM Timer 8 Reload Register

Trap Flag Register

T8REL

TFR

b FFAC_H

FEAE_H

D6_H

57_H

D7_H

WDT

Watchdog Timer Register (read only)

Watchdog Timer Control Register

CAN1 Module Interrupt Control Register

Unassigned Interrupt Control Register

WDTCON

XP0IC

XP1IC

XP2IC

XP3IC

FFAE_H

b F186_HE C3_H

b F18E_HE C7_H

b F196_HE CB_HUnassigned Interrupt Control Register

b F19E_HE CF_H

b FF1C_H8E_H

PLL/OWD Interrupt Control Register

ZEROS

Constant Value 0’s Register (read only)

1)

The system configuration is selected during reset.

2)

The reset value depends on the indicated reset source.

Data Sheet

42

V3.2, 2001-07

C167CR

C167SR

Absolute Maximum Ratings

Table 8

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

150

6.5

Storage temperature

Junction temperature

T_ST

T_J

-65

-40

-0.5

°C

V

–

under bias

Voltage on V_DDpins with V_DD

respect to ground (V_SS)

–

Voltage on any pin with

respect to ground (V_SS)

V_IN

-0.5

-10

–

V

_DD+ 0.5 V

–

Input current on any pin

during overload condition

–

10

mA

Absolute sum of all input

currents during overload

condition

–

|100|

Power dissipation

P_DISS

–

1.5

W

–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN> V_DDor V_IN< V_SS) the

voltage on V_DDpins with respect to ground (V_SS) must not exceed the values

defined by the absolute maximum ratings.

Data Sheet

43

V3.2, 2001-07

C167CR

C167SR

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the C167CR. All parameters specified in the following sections refer to these

operating conditions, unless otherwise noticed.

Table 9

Operating Condition Parameters

Symbol Limit Values Unit Notes

min. max.

4.5 5.5

Parameter

Digital supply voltage

V_DD

V

Active mode,

_CPUmax= 33 MHz

f

2.5¹⁾5.5

0

V

Power Down mode

Digital ground voltage

Overload current

V_SS

I_OV

Reference voltage

–

5

mA Per pin ²⁾³⁾

3)

Absolute sum of overload Σ|I_OV|

currents

50

mA

External Load Capacitance C_L

–

50

pF

Pin drivers in

fast edge mode

(PDCR.BIPEC = ‘0’)

30

Pin drivers in

reduced edge mode

(PDCR.BIPEC = ‘1’)³⁾

100

Pin drivers in

fast edge mode,

f

_CPUmax= 25 MHz⁴⁾

Ambient temperature

T_A

0

70

°C

SAB-C167CR …

SAF-C167CR …

SAK-C167CR …

-40

85

125

1)

Output voltages and output currents will be reduced when V_DDleaves the range defined for active mode.

2)

Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input overload

currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.

Proper operation is not guaranteed if overload conditions occur on functional pins like XTAL1, RD, WR, etc.

3)

4)

Not 100% tested, guaranteed by design and characterization.

The increased capacitive load is valid for the 25 MHz-derivatives up to a CPU clock frequency of 25 MHz.

Under these circumstances the timing parameters as specified in the “C167CR Data Sheet 1999-06” are valid.

Data Sheet

44

V3.2, 2001-07

C167CR

C167SR

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C167CR

and partly its demands on the system. To aid in interpreting the parameters right, when

evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C167CR will provide signals with the respective timing characteristics.

SR (System Requirement):

The external system must provide signals with the respective timing characteristics to

the C167CR.

DC Characteristics

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

max.

Input low voltage (TTL,

all except XTAL1)

V_ILSR -0.5

0.2 V_DD

- 0.1

V

–

Input low voltage XTAL1

V_IL2SR -0.5

0.3 V_DD

V

–

Input low voltage

V_ILSSR -0.5

2.0

(Special Threshold)

Input high voltage (TTL,

all except RSTIN and XTAL1)

V_IHSR 0.2 V_DDV_DD

+ 0.9 0.5

+

V

–

Input high voltage RSTIN

(when operated as input)

V_IH1SR 0.6 V_DDV_DD

0.5

Input high voltage XTAL1

V_IH2SR 0.7 V_DDV_DD

0.5

Input high voltage

(Special Threshold)

V_IHSSR 0.8 V_DDV_DD

- 0.2

0.5

Input Hysteresis

HYS

400

–

mV Series resistance

(Special Threshold)

= 0 Ω

Output low voltage

V_OLCC –

0.45

V

I

_OL= 2.4 mA

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT, RSTIN²⁾)

Output low voltage

(all other outputs)

V_OL1CC –

V

I

_OL= 1.6 mA

Data Sheet

45

V3.2, 2001-07

C167CR

C167SR

DC Characteristics (cont’d)

(Operating Conditions apply)¹⁾

Parameter

Symbol

Limit Values Unit Test Condition

min.

V_OHCC 2.4

0.9 V_DD

max.

Output high voltage³⁾

(PORT0, PORT1, Port 4, ALE,

RD, WR, BHE, CLKOUT,

RSTOUT)

–

V

I

_OH= -2.4 mA

_OH= -0.5 mA

Output high voltage³⁾

(all other outputs)

V

_OH1CC 2.4

0.9 V_DD

_OZ1CC –

_OZ2CC –

–

V

I

_OH= -1.6 mA

_OH= -0.5 mA

–

Input leakage current (Port 5)

I

200

500

nA 0 V < V_IN< V_DD

Input leakage current

(all other)⁴⁾

nA 0.45 V < V_IN< V_DD

6)

RSTIN inactive current⁵⁾

RSTIN active current⁵⁾

READY/RD/WR inact. current⁸⁾I_RWH

READY/RD/WR active current⁸⁾I_RWL

ALE inactive current⁸⁾

ALE active current⁸⁾

Port 6 inactive current⁸⁾

Port 6 active current⁸⁾

I_RSTH

–

-10

–

µA V_IN= V_IH1

7)

I_RSTL

-100

–

µA V_IN= V_IL

6)

-40

–

µA V_OUT= 2.4 V

µA V_OUT= V_OLmax

µA V_OUT= 2.4 V

µA V_OUT= V_OL1max

µA V_IN= V_IHmin

µA V_IN= V_ILmax

µA 0 V < V_IN< V_DD

7)

-500

–

6)

I_ALEL

40

–

7)

I_ALEH

500

–

6)

I_P6H

-40

–

7)

I_P6L

-500

–

6)

PORT0 configuration current⁹⁾I_P0H

-10

–

7)

I_P0L

-100

XTAL1 input current

Pin capacitance¹⁰⁾

(digital inputs/outputs)

I_ILCC –

C_IOCC –

20

10

pF f = 1 MHz

T_A= 25 °C

1)

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current I_OV

.

2)

3)

Valid in bidirectional reset mode only.

This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

4)

5)

6)

7)

This parameter is not valid for pins READY, ALE, RD, and WR while the respective pull device is on.

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 kΩ.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

Data Sheet

46

V3.2, 2001-07

C167CR

C167SR

8)

This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins

are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The

READY-pullup is always active, except for Powerdown mode.

9)

This specification is valid during Reset and during Adapt-mode.

Not 100% tested, guaranteed by design and characterization.

10)

Power Consumption C167CR

(Operating Conditions apply)

Parameter

Symbol

Limit Values

min. max.

15 + 2.5 × mA RSTIN = V_IL

_CPUin [MHz]¹⁾

Unit Test Condition

Power supply current (active) I_DD

with all peripherals active

–

f_CPU

f

Idle mode supply current

I_ID

10 + 1.0 × mA RSTIN = V_IH1

f_CPU

f

_CPUin [MHz]¹⁾

2)

Power-down mode supply

current

I_PD

50

µA

V_DD= V_DDmax

1)

The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8.

These parameters are tested at V_DDmaxand maximum CPU clock with all outputs disconnected and all inputs

at V_ILor V_IH.

2)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V_DD- 0.1 V to V_DD, all outputs (including pins configured as outputs) disconnected.

Data Sheet

47

V3.2, 2001-07

C167CR

C167SR

I [mA]

140

I_DDmax

120

100

I_DDtyp

80

60

40

20

I_IDmax

I_IDtyp

10

20

30

40

f

_CPU[MHz]

Figure 8

Supply/Idle Current as a Function of Operating Frequency

AC Characteristics

Definition of Internal Timing

The internal operation of the C167CR is controlled by the internal CPU clock f_CPU. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)

operations.

Data Sheet

48

V3.2, 2001-07

C167CR

C167SR

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see Figure 9).

Phase Locked Loop Operation

f_OSC

TCL

f_CPU

TCL

Direct Clock Drive

f_OSC

TCL

f_CPU

TCL

Prescaler Operation

f_OSC

TCL

f_CPU

MCT04338

TCL

Figure 9

Generation Mechanisms for the CPU Clock

The CPU clock signal f_CPUcan be generated from the oscillator clock signal f_OSCvia

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate f_CPU. This influence must

be regarded when calculating the timings for the C167CR.

Note: The example for PLL operation shown in Figure 9 refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5.

Upon a long hardware reset register RP0H is loaded with the logic levels present on the

upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

P0.15-13 (P0H.7-5).

Table 10 associates the combinations of these three bits with the respective clock

generation mode.

Data Sheet

49

V3.2, 2001-07

C167CR

C167SR

Table 10

C167CR Clock Generation Modes

CPU Frequency External Clock

f

CLKCFG

(P0H.7-5)

Notes

_CPU= f_OSC× F Input Range¹⁾

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

f_OSC× 4

f_OSC× 3

f_OSC× 2

f_OSC× 5

f_OSC× 1

f_OSC× 1.5

2.5 to 8.25 MHz

3.33 to 11 MHz

5 to 16.5 MHz

2 to 6.6 MHz

1 to 33 MHz

Default configuration

–

Direct drive²⁾

6.66 to 22 MHz

2 to 66 MHz

–

f

_OSC/ 2

CPU clock via prescaler

0 0 0

f_OSC× 2.5

4 to 13.2 MHz

–

1)

The external clock input range refers to a CPU clock range of 10 … 33 MHz (PLL operation).

2)

The maximum frequency depends on the duty cycle of the external clock signal.

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001_B) the CPU clock is derived from

the internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of f_CPUis half the frequency of f_OSCand the high and low time of f_CPU(i.e.

the duration of an individual TCL) is defined by the period of the input clock f_OSC

.

The timings listed in the AC Characteristics that refer to TCLs therefore can be

calculated using the period of f_OSCfor any TCL.

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is

enabled and provides the CPU clock (see Table 10). The PLL multiplies the input

frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.

f

_CPU= f_OSC× F). With every F’th transition of f_OSCthe PLL circuit synchronizes the CPU

clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock

frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of f_CPUis constantly adjusted so

it is locked to f_OSC. The slight variation causes a jitter of f_CPUwhich also effects the

duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be

calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is

constantly adjusting its output frequency so it corresponds to the applied input frequency

(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than

Data Sheet

50

V3.2, 2001-07

C167CR

C167SR

for one single TCL (see formula and Figure 10).

For a period of N × TCL the minimum value is computed using the corresponding

deviation D :

N

(N × TCL)_min= N × TCL_NOM- D

D [ns] = (13.3 + N × 6.3) / f_CPU[MHz],

N

where N = number of consecutive TCLs and 1 ≤ N ≤ 40.

So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D = (13.3 + 3 × 6.3) / 25 = 1.288 ns,

3

and (3TCL)_min= 3TCL_NOM- 1.288 ns = 58.7 ns (@ f_CPU= 25 MHz).

This is especially important for bus cycles using waitstates and e.g. for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter

is neglectible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 10).

Max. jitter D_N

30

10 MHz

26.5

This approximated formula is valid for

ns

20

1

N

40 and 10 MHz f_CPU33 MHz.

16 MHz

20 MHz

25 MHz

33 MHz

10

1

N

1

5

10

20

40

MCD04413

Figure 10

Approximated Maximum Accumulated PLL Jitter

Data Sheet

51

V3.2, 2001-07

C167CR

C167SR

Direct Drive

When direct drive is configured (CLKCFG = 011_B) the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input

clock signal.

The frequency of f_CPUdirectly follows the frequency of f_OSCso the high and low time of

f

_CPU(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

f_OSC

.

The timings listed below that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective circumstances. This minimum value

can be calculated via the following formula:

TCL_min= 1/f_OSC× DC_min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of f_OSCis compensated

so the duration of 2TCL is always 1/f_OSC. The minimum value TCL_mintherefore has to

be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that

require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/f_OSC

.

Data Sheet

52

V3.2, 2001-07

C167CR

C167SR

AC Characteristics

External Clock Drive XTAL1

(Operating Conditions apply)

Table 11

External Clock Drive Characteristics

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

Oscillator period t_OSCSR 30

max.

min.

max.

min.

45¹⁾

10

–

max.

500¹⁾ns

–

8

15

5

–

5

High time²⁾

Low time²⁾

Rise time²⁾

t₁

t₂

t₃

t₄

SR 15³⁾

SR –

–

ns

5

–

10

Fall time²⁾

SR –

–

1)

The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation

mode. Please see respective table above.

2)

3)

The clock input signal must reach the defined levels V_IL2and V_IH2

.

The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f_CPU) in

direct drive mode depends on the duty cycle of the clock input signal.

t₁

t₃

t₄

V_IH2

V_IL

0.5 V_DD

t₂

t_OSC

MCT02534

Figure 11

External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 40 MHz.

It is strongly recommended to measure the oscillation allowance (or margin) in the

final target system (layout) to determine the optimum parameters for the oscillator

operation. Please refer to the limits specified by the crystal supplier.

When driven by an external clock signal it will accept the specified frequency

range. Operation at lower input frequencies is possible but is guaranteed by

design only (not 100% tested).

Data Sheet

53

V3.2, 2001-07

C167CR

C167SR

A/D Converter Characteristics

(Operating Conditions apply)

Table 12

A/D Converter Characteristics

Parameter

Symbol

Limit Values

min. max.

Unit Test

Condition

1)

Analog reference supply

Analog reference ground

V_AREFSR 4.0

V

_DD+ 0.1 V

V_AGNDSR V_SS- 0.1 V_SS+ 0.2 V

–

2)

Analog input voltage range V_AINSR V_AGND

V_AREF

V

3)

4)

Basic clock frequency

Conversion time

f_BC

t_C

0.5

CC –

6.25

MHz

–

40t_BC+t_S

+ 2t_CPU

t

_CPU= 1/f_CPU

5)

Calibration time after reset t_CALCC –

3328 t_BC

–

1)

Total unadjusted error

TUE CC –

R_AREFSR –

2

LSB

kΩ

Internal resistance of

reference voltage source

t

_BC/ 60

- 0.25

t

_BCin [ns]⁶⁾⁷⁾

Internal resistance of

analog source

R_ASRCSR –

C_AINCC –

t_S/ 450

- 0.25

kΩ

t_Sin [ns]⁷⁾⁸⁾

7)

ADC input capacitance

33

pF

1)

TUE is tested at V_AREF= 5.0 V, V_AGND= 0 V, V_DD= 4.9 V. It is guaranteed by design for all other voltages

within the defined voltage range.

If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V

(i.e. V_AREF= V_DD+ 0.2 V) the maximum TUE is increased to 3 LSB. This range is not 100% tested.

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see I_OV

specification) does not exceed 10 mA.

During the reset calibration sequence the maximum TUE may be 4 LSB.

2)

V_AINmay exceed V_AGNDor V_AREFup to the absolute maximum ratings. However, the conversion result in

these cases will be X000 or X3FF , respectively.

H

3)

4)

The limit values for f_BCmust not be exceeded when selecting the CPU frequency and the ADCTC setting.

This parameter includes the sample time t_S, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the basic clock t_BCdepend on programming and can be taken from Table 13.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

5)

6)

During the reset calibration conversions can be executed (with the current accuracy). The time required for

these conversions is added to the total reset calibration time.

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within each conversion step. The maximum internal resistance results from the programmed conversion

timing.

7)

Not 100% tested, guaranteed by design and characterization.

Data Sheet

54

V3.2, 2001-07

C167CR

C167SR

8)

During the sample time the input capacitance C_AINcan be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within t_S.

After the end of the sample time t_S, changes of the analog input voltage have no effect on the conversion result.

Values for the sample time t_Sdepend on programming and can be taken from Table 13.

Sample time and conversion time of the C167CR’s A/D Converter are programmable.

Table 13 should be used to calculate the above timings.

The limit values for f_BCmust not be exceeded when selecting ADCTC.

Table 13

A/D Converter Computation Table

ADCON.15|14

(ADCTC)

A/D Converter

Basic clock f_BC

ADCON.13|12

(ADSTC)

Sample time

t_S

00

01

10

11

f

_CPU/ 4

_CPU/ 2

_CPU/ 16

_CPU/ 8

00

01

10

11

t_BC× 8

t_BC× 16

t_BC× 32

t_BC× 64

Converter Timing Example:

Assumptions:

f_CPU= 25 MHz (i.e. t_CPU= 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.

Basic clock

Sample time

Conversion time t_C

f_BC

t_S

= f_CPU/ 4 = 6.25 MHz, i.e. t_BC= 160 ns.

= t_BC× 8 = 1280 ns.

= t_S+ 40 t_BC+ 2 t_CPU= (1280 + 6400 + 80) ns = 7.8 µs.

Data Sheet

55

V3.2, 2001-07

C167CR

C167SR

Testing Waveforms

2.4 V

1.8 V

0.8 V

1.8 V

0.8 V

Test Points

0.45 V

AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’.

Timing measurements are made at _IHmin for a logic ’1’ and _ILmax for a logic ’0’.

V

MCA04414

Figure 12

Input Output Waveforms

V_Load+ 0.1 V

V_OH- 0.1 V

Timing

Reference

Points

V_Load- 0.1 V

V_OL+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,

but begins to float when a 100 mV change from the loaded V_OH

/

V_OLlevel occurs (I_OH

/

I

_OL= 20 mA).

MCA00763

Figure 13

Float Waveforms

Data Sheet

56

V3.2, 2001-07

C167CR

C167SR

AC Characteristics

Table 14

CLKOUT Reference Signal

Parameter

Symbol

Limits

min. max.

Unit

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

tc₅CC

30¹⁾

ns

tc₆CC 8

tc₇CC 6

tc₈CC –

tc₉CC –

–

4

1)

The CLKOUT cycle time is influenced by the PLL jitter.

For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for f_CPU> 25 MHz).

For longer periods the relative deviation decreases (see PLL deviation formula).

tc₉

tc₇

tc₈

tc₅

tc₆

CLKOUT

MCT04415

Figure 14

CLKOUT Signal Timing

Variable Memory Cycles

The bus timing shown below is programmable via the BUSCONx registers. The duration

of ALE and two types of waitstates can be selected. This table summarizes the possible

bus cycle durations.

Table 15

Variable Memory Cycles

Bus Cycle Type

Bus Cycle Duration

Unit 25/33 MHz, 0 Waitstates

Demultiplexed bus cycle

with normal ALE

4 + 2 × (15 - <MCTC>) TCL 80 ns / 60.6 ns

+ 2 × (1 - <MTTC>)

Demultiplexed bus cycle

with extended ALE

6 + 2 × (15 - <MCTC>) TCL 120 ns / 90.9 ns

+ 2 × (1 - <MTTC>)

Multiplexed bus cycle with 6 + 2 × (15 - <MCTC>) TCL 120 ns / 90.9 ns

normal ALE + 2 × (1 - <MTTC>)

Multiplexed bus cycle with 8 + 2 × (15 - <MCTC>) TCL 160 ns / 121.2 ns

extended ALE

+ 2 × (1 - <MTTC>)

Data Sheet

57

V3.2, 2001-07

C167CR

C167SR

Table 16

External Bus Cycle Timing (Operating Conditions apply)

Symbol Limits

Parameter

Unit

min.

max.

Output delay from CLKOUT falling edge

Valid for: address, BHE, early CS, write data out, ALE

tc₁₀CC -2

tc₁₁CC -2

tc₁₂CC -2

11

ns

Output delay from CLKOUT rising edge

Valid for: latched CS, ALE low

6

8

Output delay from CLKOUT rising edge

Valid for: WR low (no RW delay), RD low (no RW

delay)

Output delay from CLKOUT falling edge

Valid for: RD/WR low (with RW delay), RD high (with

RW delay)

tc₁₃CC -2

6

ns

Input setup time to CLKOUT falling edge

Valid for: read data in

tc₁₄SR 14

tc₁₅SR 0

tc₁₇CC -2

tc₁₈CC -2

tc₁₉CC -2

tc₂₀CC –

tc₂₁CC -5

–

6

–

4

7

–

ns

Input hold time after CLKOUT falling edge

Valid for: read data in¹⁾

Output hold time after CLKOUT falling edge

Valid for: address, BHE, early CS²⁾

Output hold time after CLKOUT edge³⁾

Valid for: write data out

Output delay from CLKOUT falling edge

Valid for: WR high

Turn off delay after CLKOUT edge³⁾

Valid for: write data out

Turn on delay after CLKOUT falling edge³⁾

Valid for: write data out

1)

Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD. Therefore the read data may be removed immediately after the rising edge of RD. Address changes

before the end of RD have also no impact on (demultiplexed) read cycles.

2)

3)

Due to comparable propagation delays (at comparable capacitive loads) the address does not change before

WR goes high. The minimum output delay (tc_17min) is therefore the actual value of tc₁₉.

Not 100% tested, guaranteed by design and characterization.

Data Sheet

58

V3.2, 2001-07

C167CR

C167SR

General Notes For The Following Timing Figures

These standard notes apply to all subsequent timing figures. Additional individual notes

are placed at the respective figure.

1)

The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature (bit

BUSCON.RWDCx).

2)

A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive.

A bus cycle is extended here, if an MTTC waitstate is selected.

3)

CLKOUT

Normal ALE Cycle

tc₁₁

tc₁₀

Normal ALE

Extended ALE Cycle

tc₁₀

Extended ALE

CSxL

tc₁₁

tc₁₀

tc₁₇

A23-A0

BHE, CSxE

Valid

tc₁₃

tc₁₂

tc₁₉

WRL, WRH,

WR, WrCS

1)

tc₁₀

tc₂₀

tc₂₁

tc₁₈

D15-D0

Data OUT

2)

MCTC

3)

MTTC

MCT04416

Figure 15

Demultiplexed Bus, Write Access

Data Sheet

59

V3.2, 2001-07

C167CR

C167SR

CLKOUT

Normal ALE Cycle

tc₁₁

tc₁₀

Normal ALE

Extended ALE Cycle

tc₁₀

Extended ALE

CSxL

tc₁₁

tc₁₀

tc₁₇

A23-A0,

BHE, CSxE

Valid

tc₁₃

tc₁₂

tc₁₃

RD,

RdCS

1)

tc₁₅

tc₁₄

D15-D0

Data IN

2)

MCTC

3)

MTTC

MCT04417

Figure 16

Demultiplexed Bus, Read Access

Data Sheet

60

V3.2, 2001-07

C167CR

C167SR

CLKOUT

Normal ALE Cycle

tc₁₁

tc₁₀

Normal ALE

Extended ALE Cycle

tc₁₀

Extended ALE

CSxL

tc₁₁

tc₁₀

tc₁₇

A23-A16

BHE, CSxE

Valid

tc₁₃

tc₁₂

tc₁₉

WRL, WRH,

WR, WrCS

1)

tc₁₀

tc₁₇

tc₂₀

tc₂₁

tc₁₈

AD15-AD0

Low Address

Data OUT

(Normal ALE)

tc₁₀

tc₂₀

tc₂₁

tc₁₇

tc₁₈

AD15-AD0

(Extended ALE)

Low Address

2)

MCTC

3)

MTTC

MCT04418

Figure 17

Multiplexed Bus, Write Access

Data Sheet

61

V3.2, 2001-07

C167CR

C167SR

CLKOUT

Normal ALE Cycle

tc₁₁

tc₁₀

Normal ALE

Extended ALE Cycle

tc₁₀

Extended ALE

CSxL

tc₁₁

tc₁₀

tc₁₇

A23-A16

BHE, CSxE

Valid

tc₁₃

tc₁₂

tc₁₃

RD,

RdCS

1)

tc₁₀

tc₂₀

tc₁₇

tc₁₅

tc₂₁

tc₁₄

AD15-AD0

(Normal ALE)

Low Address

Data IN

tc₁₀

tc₂₀

tc₁₅

tc₂₁

tc₁₇

tc₁₄

AD15-AD0

(Extended ALE)

Low Address

Data IN

2)

MCTC

3)

MTTC

MCT04419

Figure 18

Multiplexed Bus, Read Access

Data Sheet

62

V3.2, 2001-07

C167CR

C167SR

Bus Cycle Control via READY Input

The duration of an external bus cycle can be controlled by the external circuitry via the

READY input signal.

Synchronous READY permits the shortest possible bus cycle but requires the input

signal to be synchronous to the reference signal CLKOUT.

Asynchronous READY puts no timing constraints on the input signal but incurs one

waitstate minimum due to the additional synchronization stage.

Table 17

READY Timing (Operating Conditions apply)

Parameter

Symbol

Limits

max.

Unit

min.

tc₂₅CC 12

Input setup time to CLKOUT rising edge

Valid for: READY input

–

ns

Input hold time after CLKOUT rising edge

Valid for: READY input

Asynchronous READY input low time⁶⁾

tc₂₆CC 0

tc₂₇CC tc₅+ tc₂₅

Notes (Valid also for Figure 19)

4)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

READY sampled HIGH at this sampling point generates a READY controlled waitstate,

READY sampled LOW at this sampling point terminates the currently running bus cycle.

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT,

it must fulfill tc₂₇in order to be safely synchronized.

5)

6)

Proper deactivation of READY is guaranteed if READY is deactivated in response to the trailing (rising) edge

of the corresponding command (RD or WR).

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a

demultiplexed bus without MTTC waitstate this delay is zero.

If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first

valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current

cycle, and on the MCTC waitstates and the ALE mode of the next following cycle. If the current cycle uses a

multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time.

7)

8)

Data Sheet

63

V3.2, 2001-07

C167CR

C167SR

Running Cycle⁴⁾

READY WS

MUX/MTTC

7)

CLKOUT

D15-D0

tc₁₅

tc₁₄

Data IN

tc₁₀

tc₂₀

tc₁₈

tc₂₁

D15-D0

Data OUT

tc₁₃

tc₁₂

tc₁₃

/

tc₁₉

Command

(RD, WR)

1)

6)

tc₂₆

tc₂₅

Synchronous

READY

5)

tc₂₇

tc₂₆

tc₂₅

tc₂₆

tc₂₅

Asynchronous

READY

5)

8)

MCT04420

Figure 19

READY Timings

Data Sheet

64

V3.2, 2001-07

C167CR

C167SR

External Bus Arbitration

Table 18

Bus Arbitration Timing (Operating Conditions apply)

Symbol Limits

max.

Parameter

Unit

min.

HOLD input setup time to CLKOUT falling edge tc₂₈SR 18

–

ns

CLKOUT to BREQ delay

CLKOUT to HLDA delay

CSx release¹⁾

tc₂₉CC -4

tc₃₀CC -4

tc₃₁CC 0

tc₃₂CC -2

tc₃₃CC 0

tc₃₄CC 0

6

10

6

CSx drive

Other signals release¹⁾

Other signals drive¹⁾

10

6

1)

Not 100% tested, guaranteed by design and characterization.

Data Sheet

65

V3.2, 2001-07

C167CR

C167SR

CLKOUT

HOLD

HLDA

BREQ

CS

tc₂₈

tc₃₀

1)

tc₂₉

2)

tc₃₁

3)

tc₃₃

Other

Signals

MCT04421

Figure 20

External Bus Arbitration, Releasing the Bus

Notes

1)

The C167CR will complete the currently running bus cycle before granting bus access.

This is the first possibility for BREQ to get active.

2)

3)

The CS outputs will be resistive high (pullup) after t₃₃. Latched CS outputs are driven high for 1 TCL before

the output drivers are switched off.

Data Sheet

66

V3.2, 2001-07

C167CR

C167SR

CLKOUT

HOLD

HLDA

BREQ

CS

5)

tc₂₈

tc₃₀

tc₂₉

4)

tc₃₂

tc₃₄

Other

Signals

MCT04422

Figure 21

External Bus Arbitration, (Regaining the Bus)

Notes

4)

This is the last chance for BREQ to trigger the indicated regain-sequence.

Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.

Please note that HOLD may also be deactivated without the C167CR requesting the bus.

The next C167CR driven bus cycle may start here.

5)

Data Sheet

67

V3.2, 2001-07

C167CR

C167SR

External XRAM Access

If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed

(during hold states) by an external master like an asynchronous SRAM.

Table 19

XRAM Access Timing (Operating Conditions apply)¹⁾

Symbol Limits

Parameter

Unit

min.

max.

–

Address setup time before RD/WR falling edge

Address hold time after RD/WR rising edge

Data turn on delay after RD falling edge

Data output valid delay after address latched

Data turn off delay after RD rising edge

Write data setup time before WR rising edge

Write data hold time after WR rising edge

WR pulse width

t₄₀SR 4

t₄₁SR 0

t₄₂CC 1

t₄₃CC –

t₄₄CC 1

t₄₅SR 10

t₄₆SR 2

t₄₇SR 20

t₄₈SR t₄₀

ns

–

40

14

–

WR signal recovery time

–

1)

The minimum access cycle time is 60 ns.

t₄₀

t₄₁

Address

t₄₇

t₄₈

Command

(RD, WR)

t₄₆

t₄₅

Write Data

t₄₃

t₄₂

t₄₄

Read Data

MCT04423

Figure 22

External Access to the XRAM

Data Sheet

68

V3.2, 2001-07

C167CR

C167SR

Package Outlines

P-MQFP-144-6

(Plastic Metric Quad Flat Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

V3.2, 2001-07

SMD = Surface Mounted Device

Data Sheet

69

Infineon goes for Business Excellence

“Business excellence means intelligent approaches and clearly

defined processes, which are both constantly under review and

ultimately lead to good operating results.

Better operating results and business excellence mean less

idleness and wastefulness for all of us, more professional

success, more accurate information, a better overview and,

thereby, less frustration and more satisfaction.”

Dr. Ulrich Schumacher

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	SAK-C167CR-L33MTR
厂家：	Infineon
描述：	Microcontroller, 16-Bit, MROM, 33MHz, CMOS, PQFP144, MQFP-144 微控制器
文件：	总74页 (文件大小：954K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAK-C167CR-L33MTR [INFINEON]

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