SAK-TC1796-256F150E BE [INFINEON]
The TC1796 - member of the AUDO-NG family - is optimized for highly demanding applications where embedded real-time performance and DSP capabilities combined with an extremely fast interrupt response time and highest level of fault tolerance are needed.;
| 型号： | SAK-TC1796-256F150E BE |
| 厂家： | 
Infineon |
| 描述： | The TC1796 - member of the AUDO-NG family - is optimized for highly demanding applications where embedded real-time performance and DSP capabilities combined with an extremely fast interrupt response time and highest level of fault tolerance are needed. |
| 文件： | 总134页 (文件大小：4061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V1.0, Apr. 2008
TC1796
32-Bit Single-Chip Microcontroller
TriCore
Microcontrollers
Edition 2008-04
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.0, Apr. 2008
TC1796
32-Bit Single-Chip Microcontroller
TriCore
Microcontrollers
TC1796
TC1796 Data Sheet
Revision History: V1.0, 2008-04
Previous Version: V1.0, 2008-04 “Preliminary”
Page
Subjects (major changes since last revision)
“Preliminary” status removed. No changes in content.
Changes from V0.7, 2006-03 to V1.0, 2008-04 Preliminary
32
The list of not connected pins (N.C.) improved by adding several
formerly as VSS labeled pins.
69
80
85
96
Watchdog timer, double reset detection, description corrected.
RTID register updated for the design step BE.
The description of the inactive device current improved.
ADC parameters sample and conversion time moved to a dedicated
table.
107
115
126
131
The description of the power supply sequence improved..
BFCLKO clock, duty cycle description extended.
MLI timing, maximum operating frequency limit extended, t31 added.
The drawing of the package updated.
Green package variant included.
133
Example of a temperature profile corrected.
Trademarks
TriCore® is a trademark of Infineon Technologies AG.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet
V1.0, 2008-04
TC1796
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TC1796 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pad Driver and Input Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pull-Up/Pull-Down Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . 35
2.1
2.2
2.3
2.4
2.5
2.5.1
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
System Architecture and On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . . 36
On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Architectural Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
External Bus Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Peripheral Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DMA Controller and Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) . . . . . . . . . . 48
High-Speed Synchronous Serial Interfaces (SSC0, SSC1) . . . . . . . . . . . . 50
Micro Second Bus Interfaces (MSC0, MSC1) . . . . . . . . . . . . . . . . . . . . . . 52
MultiCAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Micro Link Serial Bus Interface (MLI0, MLI1) . . . . . . . . . . . . . . . . . . . . . . . 57
General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Functionality of GPTA0/GPTA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Functionality of LTCA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Analog-to-Digital Converter (ADC0, ADC1) . . . . . . . . . . . . . . . . . . . . . . . . 63
Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . . . . . . . . . 65
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clock Generation and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.14.1
3.14.2
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.1
4.1.1
Data Sheet
5
V1.0, 2008-04
TC1796
Table of Contents
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.9.1
4.3.9.2
4.3.10
4.3.11
4.3.12
4.3.12.1
4.3.12.2
4.3.12.3
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 83
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Analog to Digital Converters (ADC0/ADC1) . . . . . . . . . . . . . . . . . . . . . 92
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . 99
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Debug Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
EBU Demultiplexed Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Demultiplexed Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Demultiplexed Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
EBU Burst Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 128
Synchronous Serial Channel (SSC) Master Mode Timing . . . . . . . . 129
5
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Package Parameters (P/PG-BGA-416-4) . . . . . . . . . . . . . . . . . . . . . . . . 130
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1
5.2
5.3
5.4
Data Sheet
6
V1.0, 2008-04
TC1796
Summary of Features
1
Summary of Features
•
High-performance 32-bit super-scalar TriCore V1.3 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 150 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
•
•
– 32 Kbyte Code Memory (CMEM)
Multiple on-chip memories
– 2 Mbyte Program Flash Memory (PFLASH) with ECC
– 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 136 Kbyte Data Memory (LDRAM, SRAM, SBRAM)
– 8 Kbyte Dual-Ported Memory (DPRAM)
– 48 Kbyte Code Scratchpad Memory (SPRAM)
– 16 Kbyte Instruction Cache (ICACHE)
– 16 Kbyte BootROM (BROM)
•
•
16-Channel DMA Controller
32-bit External Bus Interface Unit (EBU) with
– 75 dedicated address/data bus, clock, and control lines
– Synchronous burst Flash access capability
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
•
•
High performing on-chip bus structure
– Two 64-bit Local Memory Buses between EBU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– 32-bit Remote Peripheral Bus (RPB) for high-speed on-chip peripheral units
– Two bus bridges (LFI Bridge, DMA Controller)
Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
•
•
– 32 Kbyte Code Memory (CMEM)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Two High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
Data Sheet
7
V1.0, 2008-04
TC1796
Summary of Features
– One MultiCAN Module with four CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two 16-channel Analog-to-Digital Converter units (ADC) with selectable 8-bit, 10-
bit, or 12-bit resolution
– One 4-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated
comb filters for hardware data reduction: supporting 10-bit resolution, min.
conversion time of 280ns
•
•
•
•
•
44 analog input lines for ADC and FADC
123 digital general purpose I/O lines, 4 input lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 and 2 (CPU, PCP3, DMA)
Dedicated Emulation Device chip for multi-core debugging, tracing, and calibration
via USB V1.1 interface available (TC1796ED)
•
•
•
•
•
•
Power Management System
Clock Generation Unit with PLL
Core supply voltage of 1.5 V
I/O voltage of 3.3 V
Full automotive temperature range: -40° to +125°C
P/PG-BGA-416-4 package
Data Sheet
8
V1.0, 2008-04
TC1796
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the TC1796 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1
TC1796 Derivative Synopsis
Derivative
SAK-TC1796-256F150E
Ambient Temperature Range
TA = -40oC to +125oC
Data Sheet
9
V1.0, 2008-04
TC1796
General Device Information
2
General Device Information
2.1
TC1796 Block Diagram
FPU
DMI
PMI
SPRAM: Scratch-Pad RAM
ICACHE: Instruction cache
LDRAM Local data RAM
DPRAM: Dual-port RAM
56 KB LDRAM
8 KB DPRAM
TriCore
(TC1M)
48 KB SPRAM
16 KB ICACHE
CPS
BROM: Boot ROM
PFLASH: Program Flash Memory
DFLASH: Data Flash Memory
SBRAM: Stand-by Data Memory
Program Local Memory Bus
Data Local Memory Bus
P LMB
DLMB
PBCU
EBU
DBCU
SRAM:
PRAM:
Data Memory
PCP Parameter Memory
CMEM: PCP Code Memory
PMU
DMU
PLMB:
DLMB:
Program Local Memory Bus
16 KB BROM
2 MB PFLASH
128 KB DFLASH
Data Local Memory Bus
64 KB SRAM
RPB:
Remote Peripheral Bus
16 KB SBRAM
SPB:
System Peripheral Bus
shaded: only available in TC1796ED
Emulation Memory
Interface
LFI Bridge
OCDS Debug
Interface
/JTAG
16 KB PRAM
SSC0
SSC1
ASC0
ASC1
PCP2
Core
STM
SBCU
Ports
32 KB CMEM
ADC0
ADC1
GPTA0
GPTA1
LTCA2
fCPU
fFPI
SCU
PLL
FADC
RBCU
DMA
SMIF
MultiCAN
(with 4
CAN
MSC
0
MSC
1
MLI
0
MLI
1
MEM
CHK
Nodes)
MCB05573_mod
Figure 1
TC1796 Block Diagram
Data Sheet
10
V1.0, 2008-04
TC1796
General Device Information
2.2
Logic Symbol
TSTRES
TESTMODE
D[31:0]
A[23:0]
HDRST
PORST
NMI
General
Control
5
Chip
External Bus
Select
Unit Interface
13
Control
BYPASS
BFCLKI
BFLCKO
XTAL1
XTAL2
VDDOSC
VDDOSC3
VSSOSC
16
16
14
16
16
8
Oscillator
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Alternate
Functions :
MLI0 / SCU
SSC0 / SSC1 /
GPTA
TRST
TCK
TDI
TDO
TMS
GPTA
JTAG /
OCDS
ASC0 / ASC1 /
MSC0 / MSC1 /MLI0
BRKIN
BRKOUT
TC1796
12
8
ASC0 / ASC1 /
SSC1 / CAN
TR[15:0]
TRCLK
ADC0 / ADC1
8
MLI1 /
GPTA
9
11
13
2
VDDEBU
VDDP
9
MSC0 / MSC1 /
GPTA
4
VDD
HWCFG
Digital Circuitry
Power Supply
Port 10
VDDFL3
VDDSBRAM
VSS
6
8
Dedicated
SSC0 I/O Lines
62
LVDS MSC Outputs
VFAREF
VFAGND
VDDMF
VSSMF
VDDAF
VSSAF
ADC
AN[43:0]
Analog Inputs
FADC Analog
Power Supply
2
2
VAREFx
VAGNDx
VDDM
ADC0 /ADC1
Analog
Power Supply
VSSM
10
N.C.
MCA05583_mod
Figure 2
TC1796 Logic Symbol
Data Sheet
11
V1.0, 2008-04
TC1796
General Device Information
2.3
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SO
N1
FCL
P1A
HD
RST
BY
PASS
A
B
A
VDDFL3
NMI
VDDP VSS
N.C. P2.9 P2.13 P2.15 P0.14 P0.5 P0.2 P0.1 P0.0 P3.14 P3.5 P3.1 P5.1 P5.2 P5.7
P2.6 P2.7 P2.10 P2.14 P0.9 P0.6 P0.4 P0.3 P3.15 P3.6 P3.3 P3.0 P5.0 P5.3 P5.6
P2.5 P2.8 P2.11 P2.12 P0.12 P0.10 P0.8 P0.7 P3.7 P3.10 P3.9 P3.4 P3.2 P5.5 P5.4
P9.0 P9.3 P10.0
P9.1 P9.2 P10.1
SO
P1A
FCL
N1
PO TEST
MODE
VDDFL3
VDDP VSS
VDD
VDD
B
RST
BRK
IN
SO
P0A
FCL FCL
N0
C
VDDP VSS
C
P9.6 P9.8 P10.2 N.C.
P0A
SO
N0
BRK
OUT
D
D
VDDP VSS
VDD
VDDP VSS
P3.8 P3.12 P3.13 P3.11
VDD
VDDP VSS
VDD TDO
P2.4 P2.3 P2.2 P0.15 P0.13 P0.11
P6.12 P6.11 P6.6 P6.9
P9.4 P9.5 P9.7 P10.3
VDD
E
TCK TDI
E
VDD
TRST
N.C.
OSC3
VSS
VDD
F
TMS
F
P6.14 P6.10 P6.4 P6.8
OSC
OSC
TST
RES
XTAL XTAL
G
G
H
P6.15 P6.13 P6.7 P6.5
2
1
H
VDD
VSS
VDDEBU VDDEBU VDDEBU VDDEBU
P8.1 P8.0 N.C.
P8.4 P8.3 P8.2
P8.7 P8.5 P8.6
J
J
A5
A9
A0
A6
A1
A3
A7
A2
A4
A8
K
K
VDDP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TR12 TR13 TR15
TR11 TR10 TR14
L
L
VSS
P1.15 P1.14 P1.13 P1.11
P1.10 P1.9 P1.8 P1.5
P1.3 P1.7 P1.6 P1.4
A13
M
N
VSS
VSS
VSS
VDDEBU
M
N
TR9 TR8
A12 A11 A10
VSS
VSS
VSS
VSS
A15 A16 A17 A14
P
VDD
VSS
P
P1.2 P1.1 P1.0 P1.12
A19 A20 A18
A21 A23 A22
VDD
R
R
VDD
VSS
P7.1 P7.0
TR6 TR7 TR5
SBRAM
TR
T
T
VDDEBU
P7.6 P7.5 P7.4
TR3 TR1
CLK
D1
D9
D3
D5
D8
D0
D2
D4
D7
U
U
AN23 P7.7 P7.3 P7.2
AN22 AN21 AN19 AN16
TR4 TR2 TR0
D6
VDD
V
V
D13
W
Y
VDDM
VSS
W
Y
AN20 AN17 AN13
AN18 AN14 AN10
D16 D12
VSSM
VDDEBU
D18 D14 D10
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
AN15 AN11 AN5 AN2
D19 D22 D17 D11
VDD
AN12 AN9 AN3 AN7
D21 D20 D15
D28 D25 D23
SLSO
1
VAGND1
VDDAF VSS
VDD
VDDP VSS VDDEBU VSS
VDD
VDDEBU VSS
N.C.
AN8 AN4 AN32 AN38 AN42
AN6 AN1 AN34 AN40 AN35
AN26 AN24
AN27 AN25
P4.4 P4.8 P4.12
VAREF1
VSSAF
SLSI0 VDDP BC1 HLDA CS3 CS2 CS1
BREQ
P4.0 P4.2 P4.5 P4.11 P4.15
N.C. D31 D27 D24
SLSO MRST
CS
COMB
VAREF0
VFAGND VDDMF
VDDP BC0 BC3
WAIT CS0 N.C. N.C.
RD/
AN0 AN33 AN36 AN41
N.C. AN37 AN39 AN43
AN28 AN30
AN29 AN31
P4.1 P4.3 P4.7 P4.13
0
D30 D29 D26
0
SCLK MTSR
BF
BF
VAGND0
VFAREF VSSMF
VDDP
HOLD
17
BC2
18
MR/W
19
RD
ADV BAA
P4.6 P4.9 P4.10 P4.14
10 11 12 13
N.C.
26
0
0
CLKI CLKO
WR
1
2
3
4
5
6
7
8
9
14
15
16
20
21
22
23
24
25
MCA05584
Figure 3
TC1796 Pinning for P/PG-BGA-416-4 Package (Top view)
Data Sheet
12
V1.0, 2008-04
TC1796
General Device Information
2.4
Pad Driver and Input Classes Overview
The TC1796 provides different types and classes of input and output lines. For
understanding of the abbreviations in Table 2 starting at the next page, Table 4 gives an
overview on the pad type and class types.
2.5
Pin Definitions and Functions
Data Sheet
13
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
External Bus Interface Lines (EBU)
Pin Definitions and Functions
Power Functions
D[31:0]
I/O B1
VDDEBU EBU Data Bus Lines
The EBU Data Bus Lines D[31:0] serve as
external data bus.
Data bus line 0
D0
T26
T24
U26
T25
V26
U25
U23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1
Data bus line 1
D2
Data bus line 2
D3
Data bus line 3
D4
Data bus line 4
D5
Data bus line 5
D6
Data bus line 6
D7
W26 I/O
Data bus line 7
D8
V25
U24
Y26
I/O
I/O
I/O
Data bus line 8
D9
Data bus line 9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
Data bus line 10
Data bus line 11
Data bus line 12
Data bus line 13
Data bus line 14
Data bus line 15
Data bus line 16
Data bus line 17
Data bus line 18
Data bus line 19
Data bus line 20
Data bus line 21
Data bus line 22
Data bus line 23
Data bus line 24
Data bus line 25
Data bus line 26
Data bus line 27
Data bus line 28
Data bus line 29
Data bus line 30
Data bus line 31
AA26 I/O
W25 I/O
V24
Y25
I/O
I/O
AB26 I/O
W24 I/O
AA25 I/O
Y24
I/O
AA23 I/O
AB25 I/O
AB24 I/O
AA24 I/O
AC26 I/O
AD26 I/O
AC25 I/O
AE26 I/O
AD25 I/O
AC24 I/O
AE25 I/O
AE24 I/O
AD24 I/O
Data Sheet
14
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
A[23:0]
O
B1
VDDEBU EBU Address Bus Lines A[23:0]
The EBU Address Bus Lines serve as
external address bus.
Address bus line 0
A0
J24
J25
J26
K25
K26
J23
K24
L25
L26
K23
M26
M25
M24
L24
N26
N23
N24
N25
P26
P24
P25
R24
R26
R25
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A1
Address bus line 1
A2
Address bus line 2
A3
Address bus line 3
A4
Address bus line 4
A5
Address bus line 5
A6
Address bus line 6
A7
Address bus line 7
A8
Address bus line 8
A9
Address bus line 9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
Address bus line 10
Address bus line 11
Address bus line 12
Address bus line 13
Address bus line 14
Address bus line 15
Address bus line 16
Address bus line 17
Address bus line 18
Address bus line 19
Address bus line 20
Address bus line 21
Address bus line 22
Address bus line 23
B1
B1
VDDEBU Chip Select Output Lines
CS0
CS1
CS2
CS3
AE21 O
AD21 O
AD20 O
AD19 O
Chip select output line 0
Chip select output line 1
Chip select output line 2
Chip select output line 3
CS
AE19 O
VDDEBU Combined Chip Select Output for Global
COMB
Select / Emulator Memory
Region/Emulator Overlay Memory
Data Sheet
15
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
BFCLKO AF25 O
B2
VDDEBU Burst Mode Flash Clock Output (non-
differential)
BFCLKI AF24 I
B1
Burst Mode Flash Clock Input
(feedback clock)
RD
RD/WR
ADV
AF20 O
AF21 O
AF22 O
AF19 O
B1
B1
B1
B1
Read Control Line
Write Control Line
Address Valid Output
MR/W
Motorola-style Read/Write Control
Signal
B1
Byte Control Lines
Byte control line 0
Byte control line 1
Byte control line 2
Byte control line 3
BC0
BC1
BC2
BC3
AE17 O
AD17 O
AF18 O
AE18 O
WAIT
BAA
HOLD
HLDA
BREQ
AE20 I
AF23 O
AF17 I
AD18 O
AD22 O
B1
B1
B1
B1
B1
Wait Input for inserting Wait-States
Burst Address Advance Output
Hold Request Input
Hold Acknowledge Output
Bus Request Output
Data Sheet
16
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
Parallel Ports
P0
I/O A1
VDDP
Port 0
Port 0 is a 16-bit bidirectional general-
purpose I/O port.
P0.0
A9
A8
A7
B8
B7
A6
B6
C8
C7
B5
C6
D6
C5
D5
A5
D4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 0 I/O line 0
P0.1
Port 0 I/O line 1
P0.2
Port 0 I/O line 2
P0.3
Port 0 I/O line 3
P0.4
Port 0 I/O line 4
P0.5
Port 0 I/O line 5
P0.6
Port 0 I/O line 6
P0.7
Port 0 I/O line 7
P0.8
Port 0 I/O line 8
P0.9
Port 0 I/O line 9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
Port 0 I/O line 10
Port 0 I/O line 11
Port 0 I/O line 12
Port 0 I/O line 13
Port 0 I/O line 14
Port 0 I/O line 15
The states of the Port 0 pins are latched into
the software configuration input register
SCU_SCILR at the rising edge of HDRST.
Therefore, Port 0 pins can be used for
operating mode selections by software.
Data Sheet
17
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A1/A2 VDDP
Pin Definitions and Functions (cont’d)
Power Functions
P1
Port 1
Port 1 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for the MLI0 interface or as external
trigger input lines.
P1.0
P1.1
P1.2
P1.3
P3
P2
P1
N1
I
I
I
I
I
A1
A1
A1
A1
A1
REQ0
REQ1
REQ2
REQ3
External trigger input 0
External trigger input 1
External trigger input 3
External trigger input 2
TREADY0B MLI0 transmit channel
ready input B
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
N4
M4
N3
N2
M3
M2
M1
L4
O
I
A2
A1
A2
A2
A1
A2
A1
A1
TCLK0
MLI0 transmit channel clock
output
TREADY0A MLI0 transmit channel
ready input A
TVALID0A
TDATA0
RCLK0A
O
O
I
MLI0 transmit channel valid
output A
MLI0 transmit channel data
output
MLI0 receive channel clock
input A
O
I
RREADY0A MLI0 receive channel ready
output A
RVALID0A
MLI0 receive channel valid
input A
I
RDATA0A
MLI0 receive channel data
input A
P1.12
P1.13
P4
L3
O
I
A2
A1
SYSCLK
RCLK0B
System clock output
MLI0 receive channel clock
input B
P1.14
P1.15
L2
L1
I
I
A1
A1
RVALID0B
RDATA0B
MLI0 receive channel valid
input B
MLI0 receive channel data
input B
Data Sheet
18
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A1/A2 VDDP
Pin Definitions and Functions (cont’d)
Power Functions
P2
Port 2
Port 2 is a 14-bit bi-directional general-
purpose I/O port which can be used
alternatively for the six upper SSC slave
select outputs or for GPTA I/O lines.
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
D3
D2
D1
C1
B1
B2
O
O
O
O
O
O
A2
A2
A2
A2
A2
A2
SLSO2
SLSO3
SLSO4
SLSO5
SLSO6
SLSO7
Slave select output line 2
Slave select output line 3
Slave select output line 4
Slave select output line 5
Slave select output line 6
Slave select output line 7
P2.8
C2
A2
B3
C3
C4
A3
B4
A4
I/O A1
I/O A1
I/O A1
I/O A1
I/O A1
I/O A1
I/O A1
I/O A1
IN0 / OUT0 line of GPTA
IN1 / OUT1 line of GPTA
IN2 / OUT2 line of GPTA
IN3 / OUT3 line of GPTA
IN4 / OUT4 line of GPTA
IN5 / OUT5 line of GPTA
IN6 / OUT6 line of GPTA
IN7 / OUT7 line of GPTA
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
Data Sheet
19
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A1
Pin Definitions and Functions (cont’d)
Power Functions
P3
VDDP
Port 3
Port 3 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for GPTA I/O lines.
P3.0
B12
A12
C13
B11
C12
A11
B10
C9
D10
C11
C10
D13
D11
D12
A10
B9
IN8 / OUT8 line of GPTA
IN9 / OUT9 line of GPTA
IN10 / OUT10 line of GPTA
IN11 / OUT11 line of GPTA
IN12 / OUT12 line of GPTA
IN13 / OUT13 line of GPTA
IN14 / OUT14 line of GPTA
IN15 / OUT15 line of GPTA
IN16 / OUT16 line of GPTA
IN17 / OUT17 line of GPTA
IN18 / OUT18 line of GPTA
IN19 / OUT19 line of GPTA
IN20 / OUT20 line of GPTA
IN21 / OUT21 line of GPTA
IN22 / OUT22 line of GPTA
IN23 / OUT23 line of GPTA
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.9
P3.8
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15.
Data Sheet
20
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A1/A2 VDDP
Pin Definitions and Functions (cont’d)
Power Functions
P4
Port 4
Port 4 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for GPTA I/O lines.
P4.0
AD10 I/O A21)
AE10 I/O A21)
AD11 I/O A21)
AE11 I/O A21)
AC12 I/O A21)
AD12 I/O A21)
AF10 I/O A21)
AE12 I/O A21)
AC13 I/O A1
AF11 I/O A1
AF12 I/O A1
AD13 I/O A1
AC14 I/O A1
AE13 I/O A1
AF13 I/O A1
AD14 I/O A1
IN24 / OUT24 line of GPTA
IN25 / OUT25 line of GPTA
IN26 / OUT26 line of GPTA
IN27 / OUT27 line of GPTA
IN28 / OUT28 line of GPTA
IN29 / OUT29 line of GPTA
IN30 / OUT30 line of GPTA
IN31 / OUT31 line of GPTA
IN32 / OUT32 line of GPTA
IN33 / OUT33 line of GPTA
IN34 / OUT34 line of GPTA
IN35 / OUT35 line of GPTA
IN36 / OUT36 line of GPTA
IN37 / OUT37 line of GPTA
IN38 / OUT38 line of GPTA
IN39 / OUT39 line of GPTA
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P4.8
P4.9
P4.10
P4.11
P4.12
P4.13
P4.14
P4.15
Data Sheet
21
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A2
Pin Definitions and Functions (cont’d)
Power Functions
P5
VDDP
Port 5
Port 5 is an 8-bit bi-directional general-
purpose I/O port which can be alternatively
used for ASC0/1 or MSC0/1 lines.
P5.0
B13
I/O
RXD0A
ASC0 receiver input /
output A
P5.1
P5.2
A13
A14
O
I/O
TXD0A
RXD1A
ASC0 transmitter output A
ASC1 receiver input /
output A
P5.3
B14
O
TXD1A
ASC1 transmitter output A
P5.3 is latched with the
rising edge of PORST if
BYPASS = 1 and stored in
inverted state as bit
OSC_CON.MOSC.
MSC0 device select
output 0
P5.4
C15
O
O
EN00
RREADY0B MLI0 receive channel ready
output B
SDI0
EN10
P5.5
P5.6
C14
B15
I
O
MSC0 serial data input
MSC1 device select
output 0
O
I
TVALID0B
SDI1
MLI0 transmit channel valid
output B
P5.7
A15
MSC1 serial data input
Data Sheet
22
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A2
Pin Definitions and Functions (cont’d)
Power Functions
P6
VDDP
Port 6
Port 6 is a 12-bit bi-directional general-
purpose I/O port which can be alternatively
used for SSC1, ASC0/1, and CAN I/O lines.
P6.4
P6.5
F3
O
I
MTSR1
SSC1 master transmit
output / SSC1 slave receive
input
G4
I
MRST1
SSC1 master receive input /
SSC1 slave transmit output
SSC1 clock input / output
SSC1 slave select input
CAN node 0 receiver input
ASC0 receiver input /
output B
O
I/O
I
P6.6
P6.7
P6.8
E3
G3
F4
SCLK1
SLSI1
I
RXDCAN0
RXD0B
I/O
P6.9
E4
F2
E2
O
TXDCAN0
CAN node 0 transmitter
output
O
I
I/O
TXD0B
RXDCAN1
RXD1B
ASC0 transmitter output B
CAN node 1 receiver input
ASC1 receiver input /
output B
P6.10
P6.11
O
TXDCAN1
CAN node 1 transmitter
output
O
I
O
TXD1B
RXDCAN2
TXDCAN2
ASC1 transmitter output B
CAN node 2 receiver input
CAN node 2 transmitter
output
P6.12
P6.13
E1
G2
P6.14
P6.15
F1
G1
I
O
RXDCAN3
TXDCAN3
CAN node 3 receiver input
CAN node 3 transmitter
output
Data Sheet
23
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A1
Pin Definitions and Functions (cont’d)
Power Functions
P7
VDDP
Port 7
Port 7 is an 8-bit bi-directional general-
purpose I/O port which can be alternatively
used as external trigger input lines and for
ADC0/1 external multiplexer control.
P7.0
P7.1
R3
R2
I
REQ4
REQ5
External trigger input 4
External trigger input 5
I
O
AD0EMUX2 ADC0 external multiplexer
control output 2
P7.2
P7.3
U4
U3
O
O
AD0EMUX0 ADC0 external multiplexer
control output 0
AD0EMUX2 ADC0 external multiplexer
control output 1
P7.4
P7.5
P7.6
T3
T2
T1
I
REQ6
REQ7
External trigger input 6
External trigger input 7
I
O
AD1EMUX0 ADC1 external multiplexer
control output 0
P7.7
U2
O
AD1EMUX1 ADC1 external multiplexer
control output 1
Data Sheet
24
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A1/A2 VDDP
Pin Definitions and Functions (cont’d)
Power Functions
P8
Port 8
Port 8 is an 8-bit bi-directional general-
purpose I/O port which can be alternatively
used for the MLI1 interface or as GPTA I/O
lines.
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
H2
H1
J3
O
A2
TCLK1
MLI1 transmit channel clock
output
I/O A2
I
IN40/OUT40 I/O line of GPTA
TREADY1A MLI1 transmit channel
ready input A
IN41/OUT41 I/O line of GPTA
TVALID1A
A1
I/O A1
A2
O
MLI1 transmit channel valid
output A
I/O A2
A2
IN42/OUT42 I/O line of GPTA
J2
O
TDATA1
MLI1 transmit channel data
output
IN43/OUT43 I/O line of GPTA
RCLK1A MLI1 receive channel clock
input A
I/O A2
I A1
J1
I/O A1
O A2
IN44/OUT44 I/O line of GPTA
RREADY1A MLI1 receive channel ready
output A
IN45/OUT45 I/O line of GPTA
RVALID1A
K2
K3
K1
I/O A2
A1
I
MLI1 receive channel
validinput A
I/O A1
A1
IN46/OUT46 I/O line of GPTA
I
RDATA1A
MLI1 receive channel data
input A
IN47/OUT47 I/O line of GPTA
I/O A1
Data Sheet
25
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
I/O A2
Pin Definitions and Functions (cont’d)
Power Functions
P9
VDDP
Port 9
Port 9 is a 9-bit bi-directional general-
purpose I/O port which can be alternatively
used as GPTA or MSC0/1 I/O lines.
P9.0
P9.1
A19
B19
I/O
O
IN48/OUT48 I/O line of GPTA
EN12
MSC1 device select
output 2
I/O
O
IN49/OUT49 I/O line of GPTA
EN11
MSC1 device select
output 1
P9.2
P9.3
P9.4
B20
A20
D18
I/O
O
IN50/OUT50 I/O line of GPTA
SOP1B
MSC1 serial data output
I/O
O
IN51/OUT51 I/O line of GPTA
FCLP1
MSC1 clock output
I/O
O
IN52/OUT52 I/O line of GPTA
EN03
MSC0 device select
output 3
P9.5
P9.6
D19
C19
I/O
O
IN53/OUT53 I/O line of GPTA
EN02
MSC0 device select
output 2
I/O
O
IN54/OUT54 I/O line of GPTA
EN01
MSC0 device select
output 1
P9.7
P9.8
D20
C20
I/O
O
O
IN55/OUT55 I/O line of GPTA
SOP0B
FCLP0B
MSC0 serial data output
MSC0 clock output
Data Sheet
26
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
A1
Pin Definitions and Functions (cont’d)
Power Functions
P10
I
VDDP
Hardware Configuration Inputs / Port 10
These inputs are boot mode (hardware
configuration) control inputs. They are
latched with the rising edge of HDRST.
Port 10 input line 0 / HWCFG0
P10.0
P10.1
P10.2
P10.3
A21
B21
C21
D21
I
I
I
I
Port 10 input line 1 / HWCFG1
Port 10 input line 2 / HWCFG2
Port 10 input line 3 / HWCFG3
After reset (HDRST = 1) the state of the
Port 10 input pins may be modified from the
reset configuration state. There actual state
can be read via software (P10_IN register).
During normal operation input HWCFG1
serves as emergency shut-off control input
for certain I/O lines (e.g. GPTA related
outputs).
Dedicated Peripheral I/Os
SLSO0
SLSO1
MTSR0
AE14 O
AC15 O
AF15 O
I
A2
VDDP
SSC0 Slave Select Output Line 0
SSC0 Slave Select Output Line 1
SSC0 Master Transmit Output /
SSC0 Slave Receive Input
MRST0
AE15 I
O
SSC0 Master Receive Input /
SSC0 Slave Transmit Output
SCLK0
SLSI0
AF14 I/O
AD15 I
SSC0 Clock Input/Output
SSC0 Slave Select Input
Data Sheet
27
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
MSC Outputs
C
VDDP
LVDS MSC Clock and Data Outputs2)
MSC0 differential driver clock output
positive A
FCLP0A C18
O
O
O
O
O
O
O
O
FCLN0
SOP0A
SON0
C17
C16
D17
MSC0 differential driver clock output
negative
MSC0 differential driver serial data output
positive A
MSC0 differential driver serial data output
negative
FCLP1A A17
MSC1 differential driver clock output
positive A
FCLN1
SOP1A
SON1
B17
B16
A16
MSC1 differential driver clock output
negative
MSC1 differential driver serial data output
positive A
MSC1 differential driver serial data output
negative
Data Sheet
28
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
Analog Inputs
AN[43:0]
I
D
–
ADC Analog Input Port
The ADC Analog Input Port provides 44
analog input lines for the A/D converters
ADC0, ADC1, and FADC.
Analog input 0
AN0
AE1
AD2
AA4
AB3
AC2
AA3
AD1
AB4
AC1
AB2
Y3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AN1
Analog input 1
AN2
Analog input 2
AN3
Analog input 3
AN4
Analog input 4
AN5
Analog input 5
AN6
Analog input 6
AN7
Analog input 7
AN8
Analog input 8
AN9
Analog input 9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
Analog input 10
Analog input 11
Analog input 12
Analog input 13
Analog input 14
Analog input 15
Analog input 16
Analog input 17
Analog input 18
Analog input 19
Analog input 20
Analog input 21
Analog input 22
Analog input 23
Analog input 24
Analog input 25
Analog input 26
Analog input 27
Analog input 28
Analog input 29
Analog input 30
Analog input 31
AA2
AB1
W3
Y2
AA1
V4
W2
Y1
V3
W1
V2
V1
U1
AC8
AD8
AC7
AD7
AE6
AF6
AE7
AF7
Data Sheet
29
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
D
–
ADC Analog Input Port (cont’d)
Analog input 32
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
AN40
AN41
AN42
AN43
AC3
AE2
AD3
AD5
AE3
AF2
AC4
AF3
AD4
AE4
AC5
AF4
I
I
I
I
I
I
I
I
I
I
I
I
Analog input 33
Analog input 34
Analog input 35
Analog input 36
Analog input 37
Analog input 38
Analog input 39
Analog input 40
Analog input 41
Analog input 42
Analog input 43
TR[15:0]
O
A3
VDDP
OCDS Level 2 Debug Trace Lines2)
(located on center balls)
Trace output line 0
Trace output line 1
Trace output line 2
Trace output line 3
Trace output line 4
Trace output line 5
Trace output line 4
Trace output line 7
Trace output line 8
Trace output line 9
Trace output line 10
Trace output line 11
Trace output line 12
Trace output line 13
Trace output line 14
Trace output line 15
TR0
U12
T12
U11
T11
U10
R12
R10
R11
M11
M10
L11
L10
K10
K11
L12
K12
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
TR1
TR2
TR3
TR4
TR5
TR6
TR7
TR8
TR9
TR10
TR11
TR12
TR13
TR14
TR15
TRCLK
T10
O
A4
Trace Clock for OCDS Level 2 Debug
Trace Lines1)
(located on a center ball)
Data Sheet
30
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
System I/O
TRST
TCK
TDI
TDO
TMS
F23
I
I
I
O
I
A2
A2
A1
A2
A1
VDDP
JTAG Module Reset/Enable Input2)
JTAG Module Clock Input2)
JTAG Module Serial Data Input
JTAG Module Serial Data Output
E24
E25
D25
F24
JTAG Module State Machine Control
Input
BRKIN
C26
D26
I/O A3
I/O A3
OCDS Break Input (Alternate Output)2)
OCDS Break Output (Alternate Input)2)
BRK
OUT
NMI
A22
I
–
Non-Maskable Interrupt Input
(input pad with input spike-filter.)
HDRST A23
I/O A2
Hardware Reset Input / Reset Indication
Output
(open drain pad with input spike-filter.)
PORST B22
BYPASS A24
I
I
–
Power-on Reset Input
(input pad with input spike-filter.)
A1
PLL Bypass Select Input
This input has to be held stable between to
power-on resets. With BYPASS = 1 the
spike filters in the HDRST, PORST, and
NMI inputs are switched off.
TEST
B23
I
I
–
–
Test Mode Select Input
MODE
For normal operation of the TC1796, this
pin should be connected to high level.
(input pad, test function only, without input
spike-filter.)
TSTRES G24
Test Reset Input
For normal operation of the TC1796, this
pin should be connected to low level.
Otherwise an unpredictable reset behavior
may occur.
(input pad, test function only, without input
spike-filter.)
Data Sheet
31
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
XTAL1
G26
G25
I
O
n.a.
VDD
Oscillator / PLL / Clock Generator
XTAL2
Input / Output Pins2)
N.C.
A1
–
–
–
Not Connected
C22
These pins are reserved for future
extension and should not be connected
externally.
G23
H3
AF1
AF26
AC21
AD23
AE22
AE23
Power Supplies
VDDM
VSSM
W4
Y4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC0/1 Analog Part Power Supply (3.3V)
ADC0/1 Analog Part Ground for VDDM
FADC Analog Part Power Supply (3.3V)
VFADC Analog Part Ground for VDDAF
FADC Analog Part Log. Pow. Sup. (1.5V)
FADC Analog Part Log Ground for VDDAF
ADC0 Reference Voltage
ADC0 Reference Ground
ADC1 Reference Voltage
ADC1 Reference Ground
FADC Reference Voltage
VDDMF
VSSMF
VDDAF
VSSAF
VAREF0
VAGND0
VAREF1
VAGND1
VFAREF
VFAGND
VDDOSC
AE9
AF9
AC9
AD9
AE5
AF5
AD6
AC6
AF8
AE8
F26
FADC Reference Ground
3)
Main Oscillator Power Supply (1.5V)
Main Oscillator Power Supply (3.3V)
Main Oscillator Ground
VDDOSC3 E26
VSSOSC
VDDFL3
3)
F25
A18
B18
Power Supply for Flash (3.3V)
VDDSBRAM R1
–
–
–
Power Supply for Stand-by SRAM (1.5V)
Data Sheet
32
V1.0, 2008-04
TC1796
General Device Information
Table 2
Symbol Pins I/O Pad
Class Supply
Pin Definitions and Functions (cont’d)
Power Functions
VDDEBU
H23
H24
H25
H26
M23
T23
–
–
–
EBU Power Supply (2.3 - 3.3V)
Y23
AC18
AC22
VDD
B26
C25
D9
–
–
–
Core Power Supply (1.5V)
D16
D24
E23
H4
P23
R4
V23
AB23
AC11
AC20
VDDP
A25
B24
C23
D7
D14
D22
K4
–
–
–
Port Power Supply (3.3V)
(also for OCDS)
AC16
AD16
AE16
AF16
VSS
See
Table
3
–
–
–
Ground
15 VSS lines are located at outer balls.
47 VSS lines are located at center balls.
1) In order to minimize noise coupling to the on-chip A/D converters, it is recommended to use these pins as less
as possible in strong driver mode.
Data Sheet
33
V1.0, 2008-04
TC1796
General Device Information
2) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range),
an undefined output driving level may occur at these pins.
3) Not bonded externally in the BC and BD steps of TC1796. An option for bonding them in future steps and
products is kept open.
Table 3
VSS Balls
VSS Outer Balls
VSS Center Balls
A26, B25, C24, D8, D15, D23, J4, L23,
K[17:13], L[17:13], M[17:12],
R23, T4, W23, AC10, AC17, AC19, AC23 N[17:10], P[17:10],
R[17:13], T[17:13], U[17:13]
Data Sheet
34
V1.0, 2008-04
TC1796
General Device Information
2.5.1
Pull-Up/Pull-Down Behavior of the Pins
Table 4
Pins
List of Pull-Up/Pull-Down Reset Behavior of the Pins
PORST = 0
PORST = 1
TSTRES,
Weak pull-up device active
TDI, TMS,
TESTMODE,
BRKOUT, BRKIN,
all GPIOs,
RD, RD/WR,
ADV, BC[3:0], MR/W,
WAIT, BAA, HOLD,
HLDA, BREQ,
D[31:0], A[23,0],
CS[3:0], CSCOMB
NMI, PORST
BYPASS,
Weak pull-down device active
Weak pull-up device active
High-impedance
SLSO0, SLSO1,
MTSR0, MRST0,
SCLK0, SLSI0,
TDO,
BFCLKI
BFCLKO
HDRST
Weak pull-up device active
Open-drain device drives 0
(strong pull-down)
Push-pull driver active
Weak pull-up device active
Open-drain device active
TRST, TCK
High-impedance
Weak pull-down device active
Data Sheet
35
V1.0, 2008-04
TC1796
Functional Description
3
Functional Description
The following section gives an overview of the sub systems and the modules of the
TC1796 and their connectivity.
3.1
System Architecture and On-Chip Bus Systems
The TC1796 has four independent on-chip buses (see also TC1796 block diagram in
Figure 1):
•
•
•
•
Program Local Memory Bus (PLMB)
Data Local Memory Bus (DLMB)
System Peripheral Bus (SPB)
Remote Peripheral Bus (RPB)
The two LMB Buses (Program Local Memory Bus PLMB and Data Local Memory Bus
DLMB) connect the TriCore CPU to its local resources for data and instruction fetches.
The PLMB/DLMB Buses are synchronous and pipelined buses with variable block size
transfer support. The protocol supports 8-, 16-, 32-, and 64-bit single transactions and
variable length 64-bit block transfers.
The System Peripheral Bus (SPB) is accessible by the CPU via the LFI Bridge. The
LFI Bridge is a bi-directional bus bridge between the DLMB and the SPB. It supports all
transactions types of both buses, DLMB Bus and FPI Bus. It handles address translation
and transaction type translation between the two buses. The LFI Bridge further supports
the pipelining of both connected buses. Therefore, no additional delay is created except
for bus protocol conversions.
The Remote Peripheral Bus (RPB) connects the peripherals with high data rates (SSC,
ADC, FADC) with the Dual-port memory (DPRAM) in the DMI, relieving the SPB and the
PLMB/DLMB Buses from these data transfers. The RPB is controlled by a bus switch
which is located in the DMA controller.
The two LMB Buses are running at CPU clock speed (clock rate of fCPU) while SPB and
RPB are running at system clock speed (clock rate of fSYS). Note that fSYS can be equal
to fCPU or half the fCPU frequency.
Data Sheet
36
V1.0, 2008-04
TC1796
Functional Description
3.2
On-Chip Memories
As shown in the TC1796 block diagram on Page 10, some of the TC1796 units provide
on-chip memories that are used as program or data memory.
•
Program memory in PMU and PMI
– 2 Mbyte on-chip Program Flash (PFLASH)
– 16 Kbyte Boot ROM (BROM)
– 48 Kbyte Scratch-Pad RAM (SPRAM)
– 16 Kbyte Instruction Cache (ICACHE)
Data memory in DMU, PMU and DMI
– 56 Kbyte Local Data RAM (LDRAM)
– 8 Kbyte Dual-port RAM (DPRAM)
•
– 64 Kbyte Data Memory (SRAM)
– 16 Kbyte data memory (SBRAM) for standby operation during power-down
– 128 Kbyte on-chip Data Flash (DFLASH)
Memory of the PCP2
•
•
– 32 Kbyte Code Memory (CMEM)
– 16 Kbyte Parameter Memory (PRAM)
On-chip SRAMs with parity error detection
Features of the Program Flash
•
•
•
2 Mbyte on-chip program Flash memory
Usable for instruction code execution or constant data storage
256-byte wide program interface
– 256 bytes are programmed into PFLASH page in one step/command
256-bit read interface
•
– Transfer from PFLASH to CPU/PMI by four 64-bit single-cycle burst transfers
Dynamic correction of single-bit errors during read access
Detection of double bit errors
•
•
•
Fixed sector architecture
– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte, and three 512 Kbyte sectors
– Each sector separately erasable
– Each sector separately write-protectable
•
•
Configurable read protection for complete PFLASH with sophisticated read access
supervision, combined with write protection for complete PFLASH (protection against
“Trojan horse” software)
Configurable write protection for each sector
– Each sector separately write-protectable
– With capability to be re-programmed
– With capability to be locked forever (OTP)
•
•
•
Password mechanism for temporarily disable write or read protection
On-chip programming voltage generation
PFLASH is delivered in erased state (read all zeros)
Data Sheet
37
V1.0, 2008-04
TC1796
Functional Description
•
•
JEDEC standard based command sequences for PFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
Margin check for detection of problematic PFLASH bits
Features of the Data Flash
•
•
•
128 Kbyte on-chip data Flash memory, organized in two 64 Kbyte banks
Usable for data storage with EEPROM functionality
128 Byte program interface
– 128 bytes are programmed into one DFLASH page by one step/command
64-bit read interface (no burst transfers)
•
•
•
•
Dynamic correction of single-bit errors during read access
Detection of double bit errors
Fixed sector architecture
– Two 64 Kbyte banks/sectors
– Each sector separately erasable
•
Configurable read protection (combined with write protection) for complete DFLASH
together with PFLASH read protection
•
•
•
•
•
•
Password mechanism to temporarily disable write and read protection
Erasing/programming of one bank possible while reading data from the other bank
Programming of one bank possible while erasing the other bank
On-chip generation of programming voltage
DFLASH is delivered in erased state (read all zeros)
JEDEC-standard based command sequences for DFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
Margin check for detection of problematic DFLASH bits
•
Data Sheet
38
V1.0, 2008-04
TC1796
Functional Description
3.3
Architectural Address Map
Table 5 shows the overall architectural address map as defined for the TriCore and
implemented in TC1796.
Table 5
TC1796 Architectural Address Map
Seg- Contents
Size
Description
ment
0-7
8
Global
8 × 256
Reserved (MMU space), cached
Mbyte
Global
Memory
256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH,
BROM, memory reserved for Emulation, cached
9
Global
Memory
256 Mbyte FPI space; cached
10
Global
Memory
256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH,
BROM, memory reserved for Emulation, non-
cached
11
12
13
Global
256 Mbyte FPI space; non-cached
Memory
Local LMB
Memory
DMI
PMI
EXTPER
EXTEMU
256 Mbyte DMU, bottom 4 Mbyte visible from FPI Bus in
segment 14, cached
64 Mbyte
64 Mbyte
96 Mbyte
16 Mbyte
Local Data Memory RAM, non-cached
Local Code Memory RAM, non-cached
External Peripheral Space, non-cached
External Emulator Range, non-cached
Boot ROM space, BROM mirror; non-cached
BOOTROM 16 Mbyte
14
15
EXTPER
128 Mbyte External Peripheral Space non-speculative, no
execution, non-cached
CPU[0 ..15] 16 × 8
image region Mbyte
Non-speculative, no execution, non-cached
LMBPER
CSFRs
INTPER
256
Mbyte
CSFRs of CPUs[0 ..15];
LMB & Internal Peripheral Space; non-speculative,
no execution, non-cached
Data Sheet
39
V1.0, 2008-04
TC1796
Functional Description
3.4
Memory Protection System
The TC1796 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the currently executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the kinds of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1796, numbered 0 and 1,
which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU.
Because the TC1796 uses a Harvard-style memory architecture, each Memory
Protection Register Set is broken down into a Data Protection Register Set and a Code
Protection Register Set. Each Data Protection Register Set can specify up to four
address ranges to receive particular protection modes. Each Code Protection Register
Set can specify up to two address ranges to receive particular protection modes.
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Mode Register) which determines the memory access modes which apply to the
specified range.
Data Sheet
40
V1.0, 2008-04
TC1796
Functional Description
3.5
External Bus Unit
The External Bus Unit (EBU) of the TC1796 is the units that controls the transactions
between external memories or peripheral units with the internal memories and peripheral
units. The EBU is a part of the PMU and communicates with CPU and PMI via the
Program Local Memory Bus. This configuration allows to get fast access times especially
when using external burst FLASH memory devices.
32
Data
Bus
Data Path
Control
Asynchronous
Access
State Machine
Control
Lines
64
32
Burst Access
State Machine
Program
Local
Memory
PLMB
Data
64
Region
Selection
Bus
Arbitration
Signals
External Bus
Arbitration
PLMB
Address
24
Address
Bus
Address Path
Control
External Bus Unit EBU
MCB05713
Figure 4
EBU Block Diagram
The following features are supported by the EBU:
•
•
64-bit internal Program Local Memory Bus (PLMB) interface
32-bit external demultiplexed bus interface
– Asynchronous read/write accesses support Intel-style and Motorola-style interface
signals
– Synchronous burst FLASH memory read
– Five programmable regions associated each to one chip select output
– Flexibly programmable access parameters for each chip select region
– Little-endian and Big-endian support
– Programmable wait state control
Scalable external bus frequency
•
– Derived from PLMB frequency (fCPU) divided by 1, 2, 3, or 4
– Max. 75 MHz
Data Sheet
41
V1.0, 2008-04
TC1796
Functional Description
•
Data buffering supported
– Code prefetch buffer
– Read/write buffer
External bus arbitration control capability for the EBU bus
Automatic self-configuration on boot from external memory
•
•
3.6
Peripheral Control Processor
The Peripheral Control Processor (PCP2) in the TC1796 performs tasks that would
normally be performed by the combination of a DMA controller and its supporting CPU
interrupt service routines in a traditional computer system. It could easily be considered
as the host processor’s first line of defence as an interrupt-handling engine. The PCP2
can off-load the CPU from having to service time-critical interrupts. This provides many
benefits, including:
•
•
•
Avoiding large interrupt-driven task context-switching latencies in the host processor
Reducing the cost of interrupts in terms of processor register and memory overhead
Improving the responsiveness of interrupt service routines to data-capture and data-
transfer operations
•
Easing the implementation of multitasking operating systems.
The PCP2 has an architecture that efficiently supports DMA-type transactions to and
from arbitrary devices and memory addresses within the TC1796 and also has
reasonable stand-alone computational capabilities.
The PCP2 in the TC1796 contains an improved version of the TC1775’s PCP with the
following enhancements:
•
•
•
•
•
Optimized context switching
Support for nested interrupts
Enhanced instruction set
Enhanced instruction execution speed
Enhanced interrupt queueing
The PCP2 is made up of several modular blocks as follows (see Figure 5):
•
•
•
•
•
•
PCP2 Processor Core
Code Memory (CMEM)
Parameter Memory (PRAM)
PCP2 Interrupt Control Unit (PICU)
PCP2 Service Request Nodes (PSRN)
System bus interface to the Flexible Peripheral Interface (FPI Bus)
Data Sheet
42
V1.0, 2008-04
TC1796
Functional Description
Code
Memory
CMEM
Parameter
Memory
PRAM
PCP2
Processor
Core
PCP2 Service
Req. Nodes
PSRNs
PCP2 Interrupt
Control Unit
PICU
FPI-Interface
FPI Bus
PCP2 Interrupt
Arbitration Bus
CPU Interrupt
Arbitration Bus
MCB05666a
Figure 5
Table 6
PCP2 Block Diagram
PCP2 Instruction Set Overview
Instruction Group
DMA primitives
Load/Store
Description
Efficient DMA channel implementation
Transfer data between PRAM or FPI memory and the general
purpose registers, as well as move or exchange values
between registers
Arithmetic
Divide/Multiply
Logical
Add, subtract, compare and complement
Divide and multiply
And, Or, Exclusive Or, Negate
Shift right or left, rotate right or left, prioritize
Set, clear, insert and test bits
Jump conditionally, jump long, exit
No operation, Debug
Shift
Bit Manipulation
Flow Control
Miscellaneous
Data Sheet
43
V1.0, 2008-04
TC1796
Functional Description
3.7
DMA Controller and Memory Checker
The Direct Memory Access (DMA) Controller of the TC1796 transfers data from data
source locations to data destination locations without intervention of the CPU or other
on-chip devices. One data move operation is controlled by one DMA channel. Sixteen
DMA channels are provided in two independent DMA Sub-Blocks with eight DMA
channels each. The Bus Switch provides the connection of two DMA Sub-Blocks to the
two FPI Bus interfaces and an MLI bus interface. In the TC1796, the FPI Bus interfaces
are connected to System Peripheral Bus and the Remote Peripheral Bus. The third
specific bus interface provides a connection to Micro Link Interface modules (two MLI
modules in the TC1796) and other DMA-related devices (Memory Checker module in the
TC1796). Figure 6 shows the implementation details and interconnections of the DMA
module.
fDMA
DMA Controller
DMA Sub-Block 0
Clock
Control
System
Peripheral
Bus
DMA
Channels
00-07
Request
Selection/
Arbitration
Transaction
Control Unitl
DMA
Requests of
On-chip
Periph.
Remote
Peripheral
Bus
CH0n_OUT
Bus
Switch
Units
DMA Sub-Block 1
DMA
Channels
10-17
MLI0
MLI1
Request
Selection/
Arbitration
Address
Decoder
Transaction
Control Unit
Memory
Checker
CH1n_OUT
Arbiter/
Switch
Control
Interrupt
Request
Nodes
SR[15:0]
DMA Interrupt Control
MCB05680
Figure 6
DMA Controller Block Diagram
Data Sheet
44
V1.0, 2008-04
TC1796
Functional Description
Features
•
16 independent DMA channels
– 8 DMA channels in each DMA Sub-Block
– Up to 8 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within a DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
Programmable priority of the DMA Sub-Blocks on the bus interfaces
Buffer capability for move actions on the buses (at least 1 move per bus is buffered).
Individually programmable operation modes for each DMA channel
– Single mode: stops and disables DMA channel after a predefined number of DMA
transfers
•
•
•
– Continuous mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated.
– Programmable address modification
•
Full 32-bit addressing capability of each DMA channel
– 4 GByte address range
– Support of circular buffer addressing mode
•
•
•
Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
Micro Link bus interface support
Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
•
Flexible interrupt generation (the service request node logic for the MLI channels is
also implemented in the DMA module)
•
•
All buses connected to the DMA module must work at the same frequency.
Read/write requests of the System Bus Side to the Remote Peripherals are bridged
to the Remote Peripheral Bus (only the DMA is master on the RPB)
Memory Checker
The Memory Checker Module (MEMCHK) makes it possible to check the data
consistency of memories. Any SPB bus master may access the memory checker.
Preferable the DMA controller does it as described hereafter. It uses 8-bit, 16-bit, or 32-
bit DMA moves to read from the selected address area and to write the value read in a
memory checker input register. With each write operation to the memory checker input
register, a polynomial checksum calculation is triggered and the result of the calculation
is stored in the memory checker result register.
The memory checker uses the standard Ethernet polynomial, which is given by:
G32 = x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x +1
Data Sheet
45
V1.0, 2008-04
TC1796
Functional Description
Note: Although the polynomial above is used for generation, the generation algorithm
differs from the one that is used by the Ethernet protocol.
3.8
Interrupt System
The TC1796 interrupt system provides a flexible and time-efficient means for processing
interrupts. An interrupt request can be serviced either by the CPU or by the Peripheral
Control Processor (PCP). These units are called “Service Providers”. Interrupt requests
are called “Service Requests” rather than “Interrupt Requests” in this document because
they can be serviced by either of the Service Providers.
Each peripheral in the TC1796 can generate service requests. Additionally, the Bus
Control Units, the Debug Unit, the PCP, and even the CPU itself can generate service
requests to either of the two Service Providers.
As shown in Figure 7, each TC1796 unit that can generate service requests is
connected to one or more Service Request Nodes (SRN). Each SRN contains a Service
Request Control Register. Two arbitration buses connect the SRNs with two Interrupt
Control Units, which handle interrupt arbitration among competing interrupt service
requests, as follows:
•
The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and
administers the CPU Interrupt Arbitration Bus.
•
The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP2
and administers the PCP2 Interrupt Arbitration Bus.
The PCP2 can make service requests directly to itself (via the PICU), or it can make
service requests to the CPU. The Debug Unit can generate service requests to the PCP2
or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can
make service requests to the PCP. The CPU Service Request Nodes are activated
through software.
Depending on the selected system clock frequency fSYS, the number of fSYS clock cycles
per arbitration cycle must be selected as follows:
• fSYS < 60MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1
• fSYS > 60MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0
Data Sheet
46
V1.0, 2008-04
TC1796
Functional Description
PCP
Interrupt
Arbitration Bus
CPU
Interrupt
Arbitration Bus
Service
Requestors
Service Req.
PCP Interrupt
Control Unit
Interrupt
Service
Providers
Nodes
2 SRNs
2 SRNs
4 SRNs
2 SRNs
3 SRNs
3 SRNs
4 SRNs
4 SRNs
16 SRNs
4 SRNs
4 SRNs
4 SRNs
38 SRNs
38 SRNs
16 SRNs
2 SRNs
1 SRN
2
2
PICU
Int.
2
2
MSC0
MSC1
MLI0
Req.
Int. Ack.
CCPN
2
PIPN
2
4
4
4
Service Req.
Nodes
2
PCP2
2
MLI1
2
5
5
5 SRNs
5 SRNs
2 SRNs
5 SRNs
3
3
SSC0
SSC1
ASC0
ASC1
MultiCAN
ADC0
ADC1
FADC
GPTA0
GPTA1
LTCA2
STM
3
5
5
5
2
3
3
3
2
4
4
4
5
5
5
Software
& Break-
point
4
4
4
Interrupts
16
16
4
CPU Interrupt
Control Unit
16
4
CPU
ICU
Int.
Req.
4
Int. Ack.
CCPN
4
PIPN
4
4
4
4
Service Req.
Nodes
Service
Requestors
4
38
38
38
38
16
16
2
1
1
1
1
1
1
1
1
8
8
1
1
1
1
38
38
16
2
1
1
1
1
8
1
1
1 SRN
1 SRN
1 SRN
1 SRN
8 SRNs
1 SRN
1 SRN
DBCU
PBCU
SBCU
RBCU
2
1
1
FPU
DMA
1
1
1
Flash
1 SRN
Cerberus
Software
1
2
2
Ext. Int.
2 SRNs
2
MCB05742
Figure 7
Block Diagram of the TC1796 Interrupt System
Data Sheet
47
V1.0, 2008-04
TC1796
Functional Description
3.9
Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1)
Figure 8 shows a global view of the functional blocks and interfaces of the two
Asynchronous/Synchronous Serial Interfaces ASC0 and ASC1.
fASC
Clock
Control
P5.0 /
RXD0A
A2
A2
RXD_I0
RXD_I1
RXD_O
TXD_O
P5.1 /
TXD0A
Address
Decoder
ASC0
Module
(Kernel)
P6.8 /
RXD0B
A2
A2
EIR
TBIR
TIR
P6.9 /
TXD0B
Interrupt
Control
RIR
Port 5
&
Port 6
Control
ASC0_RDR
ASC0_TDR
To
DMA
P5.2 /
RXD1A
A2
A2
RXD_I0
RXD_I1
RXD_O
TXD_O
P5.3 /
TXD1A
ASC1
Module
(Kernel)
P6.10 /
RXD1B
A2
A2
EIR
TBIR
TIR
P6.11 /
TXD1B
Interrupt
Control
RIR
ASC1_RDR
ASC1_TDR
To
DMA
MCB05773
Figure 8
Block Diagram of the ASC Interfaces
The Asynchronous/Synchronous Serial Interfaces provide serial communication
between the TC1796 and other microcontrollers, microprocessors, or external
peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In Asynchronous
Data Sheet
48
V1.0, 2008-04
TC1796
Functional Description
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data are double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal which can be very accurately
adjusted by a prescaler implemented as a fractional divider.
Each ASC module, ASC0 and ASC1, communicates with the external world via two I/O
lines. The RXD line is the receive data input signal (in Synchronous Mode also output).
TXD is the transmit output signal. In the TC1796, the two I/O lines of each ASC can be
alternatively switched to different pairs of GPIO lines.
Clock control, address decoding, and interrupt service request control are managed
outside the ASC module kernel.
Features
•
Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baud rate from 4.69 Mbit/s to 1.12 Bit/s (@ 75 MHz clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
•
Half-duplex 8-bit synchronous operating mode
– Baud rate from 9.38 Mbit/s to 763 Bit/s (@ 75 MHz clock)
Double buffered transmitter/receiver
•
•
Interrupt generation
– On a transmit buffer empty condition
– On a transmit last bit of a frame condition
– On a receive buffer full condition
– On an error condition (frame, parity, overrun error)
Data Sheet
49
V1.0, 2008-04
TC1796
Functional Description
3.10
High-Speed Synchronous Serial Interfaces (SSC0, SSC1)
Figure 9 shows a global view of the functional blocks and interfaces of the two High-
Speed Synchronous Serial interfaces SSC0 and SSC1.
MRSTA
MRSTB
MTSR
A2
A2
A2
MRST0
MTSR0
SCLK0
fSSC0
fCLC0
Master
Slave
Clock
Control
MTSRA
MTSRB
MRST
SSC0
Module
(Kernel)
Address
Decoder
SCLKA
SCLKB
SCLK
Slave
8-Stage RXFIFO
8-Stage TXFIFO
EIR
TIR
RIR
Master
Interrupt
Control
SLSI1
SLSI[7:2] 1)
SLSI0
A2
A2
A2
Slave
SLSO0
SLSO1
SLSO0
SLSO1
M/S Selected
SSC Enabled
SSC0_RDR
SSC0_TDR
To
DMA
Master
Master
SLSO[7:2]
SLSO[7:2]
P2.2 /
SLSO2
A2
A2
Port 2
Control
fSSC1
P2.7 /
SLSO7
Clock
Control
fCLC1
MRSTA
MRSTB
MTSR
Master
Slave
P6.4 /
MTSR1
A2
A2
A2
A2
Address
Decoder
MTSRA
MTSRB
MRST
SSC1
Module
(Kernel)
P6.5 /
MRST1
Port 6
Control
EIR
TIR
RIR
P6.6 /
SCLK1
Interrupt
Control
SCLKA
SCLKB
SCLK
Slave
Master
Slave
P6.7 /
SLSI1
SSC1_RDR
SSC1_TDR
SLSI1
SLSI[7:2] 1)
To
DMA
1) These lines are not connected
MCA05791
Figure 9
Block Diagram of the SSC Interfaces
The SSC allows full-duplex and half-duplex serial synchronous communication up to
37.5 Mbit/s (@ 75 MHz module clock) with Receive and Transmit FIFO support. (FIFO
only in SSC0). The serial clock signal can be generated by the SSC itself (Master Mode)
Data Sheet
50
V1.0, 2008-04
TC1796
Functional Description
or can be received from an external master (Slave Mode). Data width, shift direction,
clock polarity and phase are programmable. This allows communication with SPI-
compatible devices. Transmission and reception of data is double-buffered. A shift clock
generator provides the SSC with a separate serial clock signal. One slave select input is
available for Slave Mode operation. Eight programmable slave select outputs (chip
selects) are supported in Master Mode. The I/O lines of the SSC0 module are connected
to dedicated device pins while the SSC1 module I/O lines are wired with general purpose
I/O port lines.
Features
•
Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
Flexible data format
•
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
•
•
Baud rate generation from 37.5 Mbit/s to 572.2 Bit/s (@ 75 MHz module clock)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Flexible SSC pin configuration
•
•
•
One slave select input SLSI in slave mode
Eight programmable slave select outputs SLSO in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
SSC0 with 8-stage receive FIFO (RXFIFO) and 8-stage transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 2- to 16-bit FIFO data width
•
– Programmable receive/transmit interrupt trigger level
– Receive and Transmit FIFO filling level indication
– Overrun error generation
– Underflow error generation
Data Sheet
51
V1.0, 2008-04
TC1796
Functional Description
3.11
Micro Second Bus Interfaces (MSC0, MSC1)
The Micro Second Channel (MSC) interfaces provides a serial communication link
typically used to connect power switches or other peripheral devices. The serial
communication link is build up by a fast synchronous downstream channel and a slow
asynchronous upstream channel. Figure 10 shows a global view the interface signals of
the MSC interface.
fMSC0
FCLP
C
C
C
C
FCLP0A
FCLN0
SOP0A
SON0
Clock
Control
fCLC0
FCLN
SOP
SON
Address
Decoder
A2 P9.8 / FCLP0B
MSC0
Module
(Kernel)
P9.7 / SOP0B
P5.4 / EN00
P9.6 / EN01
A2
A2
A2
SR[1:0]
Interrupt
Control
EN0
EN1
EN2
EN3
Port 5
&
Port 9
Control
SR[3:2]
16
To DMA
A2 P9.5 / EN02
ALTINL[15:0]
(from GPTA)
ALTINH[15:0]
16
P9.4 / EN03
A2
A2
SDI[0]1)
P5.5 /
SDI0
EMGSTOPMSC
(from SCU)
SR15 (from CAN)
FCLP
FCLN
SOP
C
C
FCLP1A
fMSC1
FCLN1
Clock
Control
fCLC1
C
SOP1A
SON
SON1
C
Address
Decoder
P9.3 / FCLP1B
P9.2 / SOP1B
P5.6 / EN10
P9.1 / EN11
P9.0 / EN12
A2
A2
A2
A2
A2
MSC1
Module
(Kernel)
EN0
EN1
EN2
EN3
SR[1:0]
Interrupt
Control
Port 5
&
Port 9
Control
SR[3:2]
16
To DMA
N.C.
ALTINL[15:0]
(from GPTA)
ALTINH[15:0]
SDI[0]1)
P5.7 /
SDI1
16
A2
1) SDI[7:1] are connected to high level.
MCA05823
Figure 10
Block Diagram of the MSC Interfaces
Data Sheet
52
V1.0, 2008-04
TC1796
Functional Description
The downstream and upstream channels of the MSC module communicate with the
external world via nine I/O lines. Eight output lines are required for the serial
communication of the downstream channel (clock, data, and enable signals). One out of
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The
source of the serial data to be transmitted by the downstream channel can be MSC
register contents or data that is provided at the ALTINL/ALTINH input lines. These input
lines are typically connected to other on-chip peripheral units (for example with a timer
unit like the GPTA). An emergency stop input signal allows to set bits of the serial data
stream to dedicated values in emergency case.
Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.
Features
•
Fast synchronous serial interface to connect power switches in particular, or other
peripheral devices via serial buses
•
High-speed synchronous serial transmission on downstream channel
– Maximum serial output clock frequency: fFCL = fMSC/2
(= 37.5 Mbit/s @ 75 MHz module clock)
– Fractional clock divider for precise frequency control of serial clock fMSC
– Command, data, and passive frame types
– Start of serial frame: Software-controlled, timer-controlled, or free-running
– Programmable upstream data frame length (16 or 12 bits)
– Transmission with or without SEL bit
– Flexible chip select generation indicates status during serial frame transmission
– Emergency stop without CPU intervention
•
Low-speed asynchronous serial reception on upstream channel
– Baud rate: fMSC divided by 8, 16, 32, 64, 128, 256, or 512
– Standard asynchronous serial frames
– Parity error checker
– 8-to-1 input multiplexer for SDI lines
– Built-in spike filter on SDI lines
Data Sheet
53
V1.0, 2008-04
TC1796
Functional Description
3.12
MultiCAN Controller (CAN)
Figure 11 shows a global view of the MultiCAN module with its functional blocks and
interfaces.
fCAN
MultiCAN Module Kernel
CAN
P6.15 /
TXDCAN3
P6.14 /
RXDCAN3
Clock
Control
A2
A2
fCLC
TXDC3
RXDC3
Node 3
Address
Decoder
P6.13 /
TXDCAN2
P6.12 /
RXDCAN2
TXDC2
RXDC2
A2
A2
Message
Object
Buffer
CAN
Node 2
Linked
List
Control
Port 6
Control
DMA
TXDC1
RXDC1
CAN
Node 1
128
Objects
P6.11 /
TXDCAN1
P6.10 /
RXDCAN1
A2
A2
INT_O
[3:0]
Interrupt
Control
TXDC0
RXDC0
CAN
Node 0
INT_O
[15:4]
P6.9 /
TXDCAN0
P6.8 /
RXDCAN0
A2
A2
INT_
O15
LTCA2
GPTA1
GPTA0
CAN Control
Timing Control and Synchronization
ECTT1
ECTT2
P1.3 /
REQ3
P7.5 /
REQ7
ECTT3
A1
A1
Scheduler
ECTT4
ECTT5
ScheduleTiming DataMemory
SCU
Ext.Req.
Unit
Time-Triggered Extension TTCAN
MCA05864
Figure 11
Block Diagram of MultiCAN Module with Time-Triggered Extension
The MultiCAN module contains four independently operating CAN nodes with Full-CAN
functionality that are able to exchange Data and Remote Frames via a gateway function.
Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
All four CAN nodes share a common set of message objects. Each message object can
be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects can be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has it’s own list of message objects. A CAN node stores frames only into message
Data Sheet
54
V1.0, 2008-04
TC1796
Functional Description
objects that are allocated to the message object list of the CAN node, and it transmits
only messages belonging to this message object list. A powerful, command-driven list
controller performs all message object list operations.
MultiCAN Features
•
CAN functionality conforms to CAN specification V2.0 B active for each CAN node
(compliant to ISO 11898)
•
•
•
•
•
•
Four independent CAN nodes
128 independent message objects (shared by the CAN nodes)
Dedicated control registers for each CAN node
Data transfer rate up to 1Mbit/s, individually programmable for each node
Flexible and powerful message transfer control and error handling capabilities
Full-CAN functionality: message objects can be individually
– Assigned to one of the four CAN nodes
– Configured as transmit or receive object
– Configured as message buffer with FIFO algorithm
– Configured to handle frames with 11-bit or 29-bit identifiers
– Provided with programmable acceptance mask register for filtering
– Monitored via a frame counter
– Configured for Remote Monitoring Mode
•
•
•
Automatic Gateway Mode support
16 individually programmable interrupt nodes
Analyzer mode for CAN bus monitoring
Data Sheet
55
V1.0, 2008-04
TC1796
Functional Description
Time-Triggered Extension (TTCAN)
In addition to the event-driven CAN functionality, a deterministic behavior can be
achieved for CAN node 0 by an extension module that supports time-triggered CAN
(TTCAN) functionality. The TTCAN protocol is compliant with the confirmed
standardization proposal for ISO 11898-4 and fully conforms to the existing CAN
protocol.
The time-triggered functionality is added as higher-layer extension (session layer) to the
CAN protocol in order to be able to operate in safety critical applications. The new
features allow a deterministic behavior of a CAN network and the synchronization of
networks. A global time information is available. The time-triggered extension is based
on a scheduler mechanism with a timing control unit and a dedicated timing data part.
TTCAN Features
•
•
•
•
•
•
•
•
•
Full support of basic cycle and system matrix functionality
Support of reference messages level 1 and level 2
Usable as time master
Arbitration windows supported in time-triggered mode
Global time information available
CAN node 0 can be configured either for event-driven or for time-triggered mode
Built-in scheduler mechanism and a timing synchronization unit
Write protection for scheduler timing data memory
Module-external CAN time trigger inputs (ECTTx lines) can be used as transmit
trigger for a reference message
Timing-related interrupt functionality
Parity protection for scheduler memory
•
•
Data Sheet
56
V1.0, 2008-04
TC1796
Functional Description
3.13
Micro Link Serial Bus Interface (MLI0, MLI1)
The Micro Link Interface (MLI) is a fast synchronous serial interface that allows to
exchange data between microcontrollers of the 32-bit AUDO microcontroller family
without intervention of a CPU or other bus masters. Figure 12 shows how two
microcontrollers are typically connected together via their MLI interfaces. The MLI
operates in both microcontrollers as a bus master on the system bus.
Controller 1
CPU
Controller 2
CPU
Peripheral
A
Peripheral
B
Peripheral
C
Peripheral
D
Memory
MLI
MLI
Memory
System Bus
System Bus
MCA05869
Figure 12
Features
Typical Micro Link Interface Connection
•
Synchronous serial communication between MLI transmitters and MLI receivers
located on the same or on different microcontroller devices
Automatic data transfer/request transactions between local/remote controller
Fully transparent read/write access supported (= remote programming)
Complete address range of remote controller available
Specific frame protocol to transfer commands, addresses and data
Error control by parity bit
•
•
•
•
•
•
•
32-bit, 16-bit, and 8-bit data transfers
Programmable baud rate:
– MLI transmitter baud rate: max. fMLI/2 (= 37.5 Mbit/s @ 75 MHz module clock)
– MLI receiver baud rate: max. fMLI
•
Multiple remote (slave) controllers supported
MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and MLI
transmitters via a 4-line serial I/O bus each. Several I/O lines of these I/O buses are
available outside the MLI module kernel as four-line output or input buses.
Figure 13 shows the functional blocks of the two MLI modules with its interfaces.
Data Sheet
57
V1.0, 2008-04
TC1796
Functional Description
TCLK
P1.3 / TREADY0B
A1
TREADYA
TREADYB
TREADYD
A2 P1.4 / TCLK0
P1.5 / TREADY0A
P1.6 / TVALID0A
A1
A2
fMLI0
fDMA
TVALIDA
TVALIDB
TVALIDD
TDATA
Clock
Control
A2 P1.7 / TDATA0
Address
Decoder
RCLKA
P1.8 / RCLK0A
A1
A2
Port 1
Control
RCLKB
P1.9 / RREADY0A
MLI0
Module
(Kernel)
RCLKD
SR[3:0]
Interrupt
Control
RREADYA
RREADYB
RREADYD
RVALIDA
RVALIDB
RVALIDD
RDATAA
RDATAB
RDATAD
A1 P1.10 / RVALID0A
P1.11 / RDATA0A
A1
A1 P1.13 / RCLK0B
SR[7:4]
To DMA
BRKOUT
P1.14 / RVALID0B
P1.15 / RDATA0B
A1
A1
Cerberus
P5.4 / RREADY0B
A2
A2
Port 5
Control
P5.6 / TVALID0B
MCA05906
fMLI1
fDMA
TCLK
Clock
Control
TREADYA
TREADYD
TVALIDA
TVALIDD
TDATA
A2 P8.0 / TCLK1
P8.1 / TREADY1A
P8.2 / TVALID1A
A1
A2
Address
Decoder
A2 P8.3 / TDATA1
RCLKA
MLI1
Module
(Kernel)
Port 8
Control
SR[1:0]
RCLKD
Interrupt
Control
P8.4 / RCLK1A
A1
RREADYA
RREADYD
RVALIDA
RVALIDD
RDATAA
RDATAD
SR[3:2]
SR[7:4]
A2 P8.5 / RREADY1A
A1 P8.6 / RVALID1A
Not
Connected
To DMA
P8.7 / RDATA1A
A1
BRKOUT
Cerberus
MCA05907
Figure 13
Block Diagram of the MLI Modules
Data Sheet
58
V1.0, 2008-04
TC1796
Functional Description
3.14
General Purpose Timer Array
The GPTA provides a set of timer, compare and capture functionalities that can be
flexibly combined to form signal measurement and signal generation units. They are
optimized for tasks typical of engine, gearbox, and electrical motor control applications,
but can also be used to generate simple and complex signal waveforms needed in other
industrial applications.
The TC1796 contains two General Purpose Timer Arrays (GPTA0 and GPTA1) with
identical functionality, plus an additional Local Timer Cell Array (LTCA2). Figure 14
shows a global view of the GPTA modules.
GPTA0
GPTA1
Clock Generation Unit
Clock Generation Unit
FPC0
FPC1
FPC2
FPC3
FPC4
FPC5
FPC0
DCM0
DCM0
PDL0
FPC1 PDL0
FPC2
DCM1
DCM2
DCM3
DCM1
DCM2
DCM3
DIGITAL
PLL
DIGITAL
PLL
FPC3
PDL1
FPC4 PDL1
FPC5
fGPTA Clock Distribution Unit
Clock Distribution Unit
Clock
Conn.
Signal
Generation Unit
Signal
Generation Unit
GT0
GT1
GT0
GT1
LTCA2
GTC00
GTC01
GTC02
GTC03
LTC00
LTC01
LTC02
LTC03
GTC00
GTC01
GTC02
GTC03
LTC00
LTC01
LTC02
LTC03
LTC00
LTC01
LTC02
LTC03
Global
Timer
Cell Array
Global
Timer
Cell Array
Local
Timer
Cell Array
Local
Timer
Cell Array
Local
Timer
Cell Array
GTC30
GTC31
GTC30
GTC31
LTC62
LTC63
LTC62
LTC63
LTC62
LTC63
I/O Line
Sharing Unit
I/O Line Sharing Unit
Interrupt Sharing Unit
I/O Line Sharing Unit
Interrupt Sharing Unit
Interrupt
Sharing Unit
MCB05910
Figure 14
Block Diagram of the GPTA Modules
Data Sheet
59
V1.0, 2008-04
TC1796
Functional Description
3.14.1
Functionality of GPTA0/GPTA1
Each of the General Purpose Timer Arrays (GPTA0 and GPTA1) provides a set of
hardware modules required for high speed digital signal processing:
•
•
Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
•
•
•
•
Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may be also used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or
triggered by various external or internal events.
•
Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following sections summarize the specific features of the GPTA units. The clock
signal fGPTA is the input clock of the GPTA modules (max. 75 MHz in TC1796).
Clock Generation Unit
•
Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA module clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock.
– fGPTA/2 maximum input signal frequency in Filter Modes
Phase Discriminator Logic (PDL)
•
– Two independent units
– Two operating modes (2 and 3 sensor signals)
Data Sheet
60
V1.0, 2008-04
TC1796
Functional Description
– fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input
signal frequency in 3-sensor Mode.
Duty Cycle Measurement (DCM)
– Four independent units
•
•
•
– 0 - 100% margin and time-out handling
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Digital Phase Locked Loop (PLL)
– One unit
– Arbitrary multiplication factor between 1 and 65535
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Clock Distribution Unit (CDU)
– One unit
– Provides nine clock output signals:
fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock
Signal Generation Unit
•
•
•
Global Timers (GT)
– Two independent units
– Two operating modes (Free Running Timer and Reload Timer)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Global Timer Cell (GTC)
– 32 units related to the Global Timers
– Two operating modes (Capture, Compare and Capture after Compare)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Local Timer Cell (LTC)
– 64 independent units
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Interrupt Sharing Unit
286 interrupt sources, generating up to 92 service requests
•
Data Sheet
61
V1.0, 2008-04
TC1796
Functional Description
I/O Sharing Unit
•
Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and
MSC interface.
3.14.2
Functionality of LTCA2
One Local Timer Cells Area provides a set of Local Timer Cells.
•
64 Local Timer Cells (LTCs)
– Three basic operating modes (Timer, Capture and Compare) for 63 units.
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Data Sheet
62
V1.0, 2008-04
TC1796
Functional Description
3.15
Analog-to-Digital Converter (ADC0, ADC1)
The two ADC modules of the TC1796 are analog to digital converters with 8-bit, 10-bit,
or 12-bit resolution including sample & hold functionality.
VDD
VDDM
VAGND0 VSS VSSM VAREF0
P7.1 /
AD0EMUX2
P7.2 /
AD0EMUX0
P7.3 /
AD0EMUX1
A1
A1
A1
GRPS
fADC
fCLC
EMUX0
EMUX1
Clock
Control
Port 7
Control
ASGT
8
2
9
Address
Decoder
From Ports
SW0TR, SW0GT
ETR, EGT
QTR, QGT
TTR, TGT
External
Request
Unit
From MSC0/1
From GPTA
ADC0
Module
Kernel
SR
[3:0]
(SCU)
Interrupt
Control
AIN0
D
D
D
AN0
AN1
AN2
Group 0
AIN15
SR[7:4]
To DMA
AIN16
Group 1
AIN31
Synchronization Bridge
AIN0
Group 0
AIN16
AIN15
AN41
AN42
AN43
D
D
D
Not
Used
AIN30
AIN31
Die Temp.
Sensor
ADC1
Module
Kernel
ASGT
SW0TR, SW0GT
ETR, EGT
QTR, QGT
TTR, TGT
Address
Decoder
8
2
From Ports
External
Request
Unit
From MSC0/1
From GPTA
(SCU)
SR[3:0]
9
Interrupt
Control
P7.6 /
AD1EMUX0
P7.7 /
AD1EMUX1
EMUX0
EMUX1
A1
A1
Port 7
Control
SR[7:4]
To DMA
VAGND1 VSS VSSM VAREF1
VDD
VDDM
MCA06033
Figure 15
Block Diagram of the ADC Module
Data Sheet
63
V1.0, 2008-04
TC1796
Functional Description
The A/D converters operate by the method of the successive approximation. A
multiplexer selects between up to 32 analog inputs that can be connected with the 16
conversion channels in each ADC module. An automatic self-calibration adjusts the ADC
modules to changing temperatures or process variations.
External Clock control, address decoding, and service request (interrupt) control is
managed outside the ADC module kernel. A synchronization bridge is used for
synchronization of two ADC modules. External trigger conditions are controlled by an
External Request Unit. This unit generates the control signals for auto-scan control
(ASGT), software trigger control (SW0TR, SW0GT), the event trigger control (ETR,
EGT), queue control (QTR, QGT), and timer trigger control (TTR, TGT).
Features
•
•
8-bit, 10-bit, 12-bit A/D conversion
Minimum conversion times (without sample time, @ 75 MHz module clock):
– 1.05 µs @ 8-bit resolution
– 1.25 µs @ 10-bit resolution
– 1.45 µs @ 12-bit resolution
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Extended channel status information on request source
Successive approximation conversion method
Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution
Integrated sample & hold functionality
Direct control of up to 16(32) analog input channels per ADC
Dedicated control and status registers for each analog channel
Powerful conversion request sources
Selectable reference voltages for each channel
Programmable sample and conversion timing schemes
Limit checking
Flexible ADC module service request control unit
Synchronization of the two on-chip A/D converters
Automatic control of external analog multiplexers
Equidistant samples initiated by timer
External trigger and gating inputs for conversion requests
Power reduction and clock control feature
On-chip die temperature sensor output voltage measurement via ADC1
Data Sheet
64
V1.0, 2008-04
TC1796
Functional Description
3.16
Fast Analog-to-Digital Converter Unit (FADC)
The FADC module of the TC1796 basically is a 4-channel A/D converter with 10-bit
resolution that operates by the method of the successive approximation.
The main FADC functional blocks shown in Figure 16 are:
•
•
•
The Input Stage contains the differential inputs and the programmable amplifier.
The A/D Converter is responsible for the analog-to-digital conversion.
The Data Reduction Unit contains programmable anti aliasing and data reduction
filters.
The Channel Trigger Control block defines the trigger and gating conditions for the
four FADC channels. The gating source inputs GS[7:0] and trigger source inputs
TS[7:0] are connected with GPTA0 module outputs, with GPIO port lines, and
external request unit outputs.
The Channel Timers can independently trigger the conversion of each FADC
channel.
The A/D control block is responsible for the overall FADC functionality.
•
•
•
The FADC module is supplied by the following power supply and reference voltage lines:
• VDDMF/VDDMF: FADC Analog Part Power Supply (3.3V)
• VDDAF/VDDAF
:
FADC Analog Part Logic Power Supply (1.5V)
• VFAREF/VFAGND: FADC Reference Voltage/FADC Reference Ground
Data Sheet
65
V1.0, 2008-04
TC1796
Functional Description
VFAREF VDDAF VDDMF
VFAGND VSSAF
VSSMF
fFADC
fCLC
Clock
Control
FAIN0P
FAIN0N
FAIN1P
FAIN1N
FAIN2P
FAIN2N
FAIN3P
FAIN3N
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
D
D
D
D
D
D
D
D
Address
Decoder
FADC
Module
Kernel
SR[3:0]
Interrupt
Control
To DMA
OUT1
OUT9
OUT18
OUT26
OUT2
OUT10
OUT19
OUT27
P1.0 / REQ0
P1.1 / REQ1
P7.0 / REQ4
P7.1 / REQ5
A1
A1
A1
A1
GPTA0
GS[7:0]
TS[7:0]
PDOUT2
PDOUT3
External Request Unit
(SCU)
MCA06053
Figure 16
Features
Block Diagram of the FADC Module
•
•
Extreme fast conversion: 21 cycles of fFADC (= 280ns @ fFADC = 75 MHz)
10-bit A/D conversion
– Higher resolution by averaging of consecutive conversions is supported
Successive approximation conversion method
Four differential input channels
•
•
•
•
•
•
•
•
•
Offset and gain calibration support for each channel
Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel
Free-running (Channel Timers) or triggered conversion modes
Trigger and gating control for external signals
Built-in Channel Timers for internal triggering
Channel timer request periods independently selectable for each channel
Selectable, programmable anti aliasing and data reduction filter block
Data Sheet
66
V1.0, 2008-04
TC1796
Functional Description
3.17
System Timer
The TC1796’s STM is designed for global system timing applications requiring both high
precision and long range.
Features
•
•
•
•
•
•
•
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation based on compare match with partial STM content
Driven by max. 75 MHz (= fSYS, default after reset = fSYS/2)
Counting starts automatically after a reset operation
STM is reset by:
– Watchdog reset
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
•
•
STM is not reset at a hardware reset
STM can be halted in debug/suspend mode
The STM is an upward counter, running either at the system clock frequency fSYS or at a
fraction of it. In case of a power-on reset, a watchdog reset, or a software reset, the STM
is reset. After one of these reset conditions, the STM is enabled and immediately starts
counting up. It is not possible to affect the contents of the timer during normal operation
of the TC1796. The timer registers can only be read but not written to. The STM can be
optionally disabled or suspended for power-saving and debugging purposes via its clock
control register. In suspend mode of the TC1796, the STM clock is stopped but all
registers are still readable.
The System Timer can be read in sections from seven registers, STM_TIM0 through
STM_TIM6, which select increasingly higher-order 32-bit ranges of the System Timer.
These can be viewed as individual 32-bit timers, each with a different resolution and
timing range. For getting a synchronous and consistent reading of the complete STM
contents, a capture register (STM_CAP), is implemented. It latches the contents of the
high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is
read. Thus, it holds the upper value of the timer at exactly the same time when the lower
part is read. The second read operation would then read the contents of the STM_CAP
to get the complete timer value.
The content of the 56-bit System Timer can be compared against the content of two
compare values stored in the compare registers. Interrupts can be generated on a
compare match of the STM with the STM_CMP0 or STM_CMP1 registers.
The maximum clock period is 256 × fSTM. At fSTM = 75 MHz, for example, the STM counts
30.47 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflowing.
Data Sheet
67
V1.0, 2008-04
TC1796
Functional Description
Figure 17 shows an overview on the System Timer with the options for reading parts of
STM contents.
STM Module
31
23
15
7
0
Compare Register 0
STM_CMP0
31
23
15
7
0
Compare Register1
STM_CMP1
STMIR1
STMIR0
55
47
39
31
23
15
7
0
Interrupt
Control
56-Bit System Timer
Enable /
Disable
00H
00H
STM_CAP
STM_TIM6
Clock
Control
fSTM
STM_TIM5
STM_TIM4
Address
Decoder
STM_TIM3
STM_TIM2
STM_TIM1
STM_TIM0
PORST
MCB05746
Figure 17
General Block Diagram of the STM Module Registers
Data Sheet
68
V1.0, 2008-04
TC1796
Functional Description
3.18
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1796 in a user-specified time period. When enabled, the WDT will
cause the TC1796 system to be reset if the WDT is not serviced within a user-
programmable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1796 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the EndInit
feature and monitors its modifications. A system-wide line is connected to the End-of-
Initialization (Endinit) feature and monitors its modifications. A system-wide line is
connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection)
A further enhancement in the TC1796’s WDT is its reset pre-warning operation. Instead
of immediately resetting the device on the detection of an error (the way that standard
Watchdogs do), the WDT first issues an Non-Maskable Interrupt (NMI) to the CPU
before finally resetting the device at a specified time period later. This gives the CPU a
chance to save system state to memory for later examination of the cause of the
malfunction, an important aid in debugging.
Features
•
•
•
16-bit Watchdog counter
Selectable input frequency: fSYS/256 or fSYS/16384
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Pre-warning Modes
•
•
Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated password access mechanism with fixed and user-definable password
fields
•
•
•
•
•
Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and limited.
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation.
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system
malfunction is assumed and the TC1796 is held in reset until a power-on reset. This
prevents the device from being periodically reset if, for instance, connection to the
external memory has been lost such that even system initialization could not be
performed
Data Sheet
69
V1.0, 2008-04
TC1796
Functional Description
•
Important debugging support is provided through the reset pre-warning operation by
first issuing an NMI to the CPU before finally resetting the device after a certain
period of time.
3.19
System Control Unit
The System Control Unit (SCU) of the TC1796 handles several system control tasks.
These system control tasks of the SCU are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock system selection and control
Reset and boot operation control
Power management control
Configuration input sampling
External Request Unit
System clock output control
Chip select generation for EBU
EBU pull devices control
On-chip SRAM Parity Control
Pad driver temperature compensation control
Emergency stop input control for GPTA outputs
Die Temperature Sensor
GPTA1 input IN0 control
Pad Test Mode control for dedicated pins
ODCS level 2 trace control
NMI control
Miscellaneous SCU control
3.20
Boot Options
The TC1796 booting schemes provide a number of different boot options for the start of
code execution. Table 7 shows the boot options available in the TC1796.
Data Sheet
70
V1.0, 2008-04
TC1796
Functional Description
Table 7
TC1796 Boot Selections
BRKIN HWCFG Type of Boot
Boot ROM Exit
Jump Address
[3:0]
Normal Boot Options
1
0000B
Enter bootstrap loader mode 1:
Serial ASC0 boot via ASC0 pins
D400 0000H
0001B
Enter bootstrap loader mode 2:
Serial CAN boot via CAN pins
0010B
0011B
Start from internal PFLASH
A000 0000H
Alternate boot mode (ABM): start from internal As defined in
PFLASH after CRC check is correctly executed; ABM header or
enter a serial bootstrap loader mode1) if CRC
check fails.
D400 0000H
0100B
0101B
Start from external memory with EBU as master, A100 0000H
using CS0; automatic EBU configuration2);
Alternate boot mode (ABM): start from external As defined in
memory with CRC check and EBU as master, ABM header or
using CS0; enter a serial bootstrap loader
D400 0000H
mode2) if CRC checks fails;
automatic EBU configuration2);
0110B
0111B
Start from external memory with EBU as
participant, using CS0;
A100 0000H
automatic EBU configuration2);
Alternate boot mode (ABM): start from external As defined in
memory with CRC check and EBU as
ABM header or
participant, using CS0; enter a serial bootstrap D400 0000H
loader mode2) if CRC checks fails;
automatic EBU configuration2);
1000B
Start from emulation memory if emulation
device TC1796ED is available; in case of
TC1796: Execute stop loop;
If TC1796ED:
AFF0 0000H
1111B
Enter bootstrap loader mode 3:
Serial ASC0 boot via CAN pins
Reserved; execute stop loop;
D400 0000H
–
Others
Data Sheet
71
V1.0, 2008-04
TC1796
Functional Description
Table 7
TC1796 Boot Selections (cont’d)
BRKIN HWCFG Type of Boot
Boot ROM Exit
Jump Address
[3:0]
Debug Boot Options
0
0000B
1000B
Tri-state chip
Go to external emulator space with EBU as
master, using CSEMU/CSCOMB
–
DE00 0000H
Others
Reserved; execute stop loop;
–
1) The type of the alternate bootstrap loader mode is selected by the value of the SCU_SCLIR.SWOPT[2:0] bit
field, which contains the levels of the P0.[2:0] latched in with the rising edge of the HDRST. For more details
on ABM, see the User’s Manual.
2) The EBU fetches the boot configuration from address offset 4 using CS0.
Data Sheet
72
V1.0, 2008-04
TC1796
Functional Description
3.21
Power Management System
The TC1796 power management system allows software to configure the various
processing units so that they automatically adjust to draw the minimum necessary power
for the application. There are three power management modes:
•
•
•
Run Mode
Idle Mode
Sleep Mode
The operation of each system component in each of these states can be configured by
software. The power-management modes provide flexible reduction of power
consumption through a combination of techniques, including stopping the CPU clock,
stopping the clocks of other system components individually, and individually clock-
speed reduction of some peripheral components.
Besides these explicit software-controlled power-saving modes, in the TC1796 special
attention has been paid for automatic power-saving in those operating units which are
currently not required or idle. In that case they are shut off automatically until their
operation is required again.
Table 8 describes the features of the power management modes.
Table 8
Mode
Run
Power Management Mode Summary
Description
The system is fully operational. All clocks and peripherals are enabled,
as determined by software.
Idle
The CPU clock is disabled, waiting for a condition to return it to Run
Mode. Idle Mode can be entered by software when the processor has no
active tasks to perform. All peripherals remain powered and clocked.
Processor memory is accessible to peripherals. A reset, Watchdog Timer
event, a falling edge on the NMI pin, or any enabled interrupt event will
return the system to Run Mode.
Sleep
The system clock signal is distributed only to those peripherals
programmed to operate in Sleep Mode. The other peripheral module will
be shut down by the suspend signal. Interrupts from operating
peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset
event will return the system to Run Mode. Entering this state requires an
orderly shut-down controlled by the Power Management State Machine.
In typical operation, Idle Mode and Sleep Mode may be entered and exited frequently
during the run time of an application. For example, system software will typically cause
the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its
tasks. In Sleep Mode and Idle Mode, wake-up is performed automatically when any
enabled interrupt signal is detected, or if the Watchdog Timer signals the CPU with an
NMI trap.
Data Sheet
73
V1.0, 2008-04
TC1796
Functional Description
3.22
On-Chip Debug Support
Figure 18 shows a block diagram of the TC1796 OCDS system.
TriCore
SBCU
CPU
RBCU
Watchdog
Timer
PCP2
(WDT)
M
TR[15:0]
TRCLK
U
X
DMA
Controller
Cerberus
(Bus Bridge)
OCDS
System
System
Control Unit
(OSCU)
Peripheral
Bus
SPB
TDI
Peripheral
Unit 1
TDO
TMS
TCK
TRST
JTAG
Debug
Interface
(JDI)
JTAG
SPB
Peripheral
Unit m
Controller
RPB
Peripheral
Unit 1
Multi Core
Break
BRKIN
RPB
Peripheral
Unit n
Switch
BRKOUT
(MCBS)
MCB05756_mod
Figure 18
OCDS System Block Diagram
The TC1796 basically supports three levels of debug operation:
•
•
•
OCDS Level 1 debug support
OCDS Level 2 debug support
OCDS Level 3 debug support
Data Sheet
74
V1.0, 2008-04
TC1796
Functional Description
OCDS Level 1 Debug Support
The OCDS Level 1 debug support is mainly assigned for real-time software debugging
purposes which have a demand for low-cost standard debugger hardware.
The OCDS Level 1 debug support is based on a JTAG interface which can be used by
the external debug hardware to communicate with the system. The on-chip Cerberus
module controls the interactions between the JTAG interface and the on-chip modules.
The external debug hardware may become master of the internal buses and read or
write the on-chip register/memory resources. The Cerberus also allows to define
breakpoint and trigger conditions as well as to control user program execution (run/stop,
break, single-step).
OCDS Level 2 Debug Support
The OCDS Level 2 debug support allows to implement program tracing capabilities for
enhanced debuggers by extending the OCDS Level 1 debug functionality with an
additional 16-bit wide trace port with trace clock. With the trace extension the following
four trace capabilities are provided (only one of the four trace capabilities can be
selected at a time):
•
•
•
•
Trace capability of the CPU program flow
Trace capability of the PCP2 program flow
Trace capability of the DMA Controller transaction requests
Trace capability of the DMA Controller move engine status information
OCDS Level 3 Debug Support
The OCDS Level 3 debug support is based on a special emulation device, the
TC1796ED, which provides additional features required for high-end emulation
purposes. The TC1796ED is a device which includes the TC1796 product chip and
additional emulation extension hardware in a package with the same footprint as the
TC1796.
Data Sheet
75
V1.0, 2008-04
TC1796
Functional Description
3.23
Clock Generation and PLL
The TC1796 clock system performs the following functions:
•
Acquires and buffers incoming clock signals to create a master clock frequency
Distributes in-phase synchronized clock signals throughout the TC1796’s entire clock
tree
•
•
Divides a system master clock frequency into lower frequencies required by the
different modules for operation.
•
•
•
Dynamically reduces power consumption during operation of functional units
Statically reduces power consumption through programmable power-saving modes
Reduces electromagnetic interference (EMI) by switching off unused modules
The clock system must be operational before the TC1796 is able to run. Therefore, it also
contains special logic to handle power-up and reset operations. Its services are
fundamental to the operation of the entire system, so it contains special fail-safe logic.
Features
•
•
•
PLL operation for multiplying clock source by different factors
Direct drive capability for direct clocking
Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
•
Sleep and Power-Down Mode support
The TC1796 Clock Generation Unit (CGU) as shown in Figure 19 allows a very flexible
clock generation. It basically consists of an main oscillator circuit and a Phase- Locked
Loop (PLL). The PLL can converts a low-frequency external clock signal from the
oscillator circuit to a high-speed internal clock for maximum performance.
The system clock fSYS is generated from an oscillator clock fOSC in either of four
hardware/software selectable ways:
•
Direct Drive Mode (PLL Bypass):
In Direct Drive Mode, the PLL is bypassed and the CGU clock outputs are directly fed
from the clock signal fOSC, i.e. fCPU = fOSC and fSYS = fOSC/2 or fOSC. This allows
operation of the TC1796 with a reasonably small fundamental mode crystal.
VCO Bypass Mode (Prescaler Mode):
•
•
In VCO Bypass Mode, fCPU and fSYS are derived from fOSC by the two divider stages,
P-Divider and K-Divider. The system clock fSYS can be equal to fCPU or fCPU/2.
PLL Mode:
In PLL Mode, the PLL is running. The VCO clock fVCO is derived from fOSC, divided by
the P factor, multiplied by the PLL (N-Divider). The clock signals fCPU and fSYS are
derived from fVCO by the K-Divider. The system clock fSYS can be equal to fCPU or
f
CPU/2.
•
PLL Base Mode:
In PLL Base Mode, the PLL is running at its VCO base frequency and fCPU and fSYS
Data Sheet
76
V1.0, 2008-04
TC1796
Functional Description
are derived from fVCO only by the K-Divider. In this mode, the system clock fSYS can
be equal to fCPU or fCPU/2.
XTAL1
fCPU
fSYS
Clock Generation Unit (CGU)
Main
Osc.
Circuit
fOSC
Clock
Output
Control
M
U
X
XTAL2
P-
Divider
K-
Divider
≥1
fP
fN
fVCO
Phase
Detect.
VCO
N-
Divider
PLL
PLL
Lock
Osc.
Run
Detect.
Detect.
BYPASS
Oscillator Control Register
OSC_CON
PLL Clock Control and Status Register
PLL_CLC
System Control Unit (SCU)
P5.3 /
TXD1A
MCB05600
Figure 19
Clock Generation Unit
Recommended Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz
to 25 MHz. Additionally are necessary, two load capacitances CX1 and CX2, and
depending on the crystal type a series resistor RX2 to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1
and CX2 values shown in Figure 20 can be used as starting points for the negative
resistance evaluation and for non-productive systems. The exact values and related
operating range are dependent on the crystal frequency and have to be determined and
Data Sheet
77
V1.0, 2008-04
TC1796
Functional Description
optimized together with the crystal vendor using the negative resistance method.
Oscillation measurement with the final target system is strongly recommended to verify
the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin
negative resistance) for the oscillator-crystal system.
When using an external clock signal, it must be connected to XTAL1. XTAL2 is left open
(unconnected). The external clock frequency can be in the range of 0 - 40 MHz if the PLL
is bypassed and 4 - 40 MHz if the PLL is used.
The oscillator can also be used in combination with a ceramic resonator. The final
circuitry must be also verified by the resonator vendor.
Figure 20 shows the recommended external oscillator circuitries for both operating
modes, external crystal mode and external input clock mode.
VDDOSC VDDOSC3
VDDOSC VDDOSC3
fOSC
fOSC
External Clock
Signal
XTAL1
XTAL1
41) - 40
MHz
4 - 25
MHz
TC1796
TC1796
Oscillator
Oscillator
RQ
RX2
CX2
XTAL2
XTAL2
CX1
Fundamental
Mode Crystal
VSSOSC
VSSOSC
1) in case of PLL bypass 0 MHz
1)
1)
CX1
,
CX2
RX2
Crystal Frequency
4 MHz
8 MHz
33 pF
18 pF
12 pF
10 pF
0
0
0
0
12 MHz
16 - 25 MHz
1) Note that these are evaluation start values!
MCS05601
Figure 20
Oscillator Circuitries
A block capacitor between VDDOSC1)/VDDOSC3 and VSSOSC is recommended, too.
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
1) VDDOSC and VSSOSC are not bonded externally in the BC and BD steps of TC1796. An option for bonding them
in future steps and products is kept open.
Data Sheet
78
V1.0, 2008-04
TC1796
Functional Description
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
3.24
Power Supply
The TC1796 has several power supply lines for different voltage classes:
•
1.5 V: Core logic and memory, oscillator, and A/D converter supply
3.3 V: I/O ports, Flash memories, oscillator, and A/D converter supply with reference
voltages
•
•
2.3 V to 3.3 V: External bus interface supply
Figure 21 shows the power supply concept of the TC1796 with the power supply pins
and its connections to the functional units.
VAREF0
(3.3 V)
VAGND0
VDDM
(3.3 V)
VSSM
VAREF1
(3.3 V)
VAGND1
VDDAF
(1.5 V)
VSSAF
VFAREF VDDMF
(3.3 V) (3.3 V)
VFAGND VSSMF
VSS
62
2
2
2
2
2
2
TC1796
ADC0
ADC1
FADC
Ports
Core
PLL
PMI/PMU
DMI/DMU
Memories
Stand-by
SBRAM
FLASH
EBU
OSC
Memories
11
9
13
1
2
3
VDDP
VDDEBU
VDD
VDDSBRAM
VDDFL3
VDDOSC (1.5 V)
(3.3 V) (2.3 - 3.3 V)
(1.5 V)
(1.5 V)
(3.3 V)
V
DDOSC3 (3.3 V)
VSSOSC
tc1796_PwrSupply
Figure 21
Power Supply Concept of TC1796
Data Sheet
79
V1.0, 2008-04
TC1796
Functional Description
3.25
Identification Register Values
The Identification Registers uniquely identify a module or the whole device.
Table 9
Short Name
SCU_ID
MANID
CHIPID
RTID
TC1796 Identification Registers
Address
Value
Stepping
–
–
–
BA-Step
BB-Step
BC-Step
BD-Step
BE-Step
–
–
–
–
–
–
–
BA-, BB-Step
BC-, BD-, BE-Step
BA-, BB-Step
BC-, BD-, BE-Step
BA-, BB-Step
BC-, BD-, BE-Step
–
–
–
–
–
–
–
F000 0008H
F000 0070H
F000 0074H
F000 0078H
002C C002H
0000 1820H
0000 8A02H
0000 0000H
0000 0001H
0000 0100H
0000 0101H
0000 0300H
0000 6A0AH
0000 C006H
0000 6307H
0028 C002H
0028 C002H
0000 4402H
0000 4402H
0029 C003H
0029 C004H
0029 C003H
0029 C004H
002A C003H
002A C004H
001A C002H
002B C002H
0020 C003H
0000 6A0AH
0000 4530H
0000 4510H
0027 C002H
SBCU_ID
STM_ID
F000 0108H
F000 0208H
F000 0408H
F000 0808H
F000 0908H
F000 0A08H
F000 0B08H
F000 1808H
CBS_JPDID
MSC0_ID
MSC1_ID
ASC0_ID
ASC1_ID
GPTA0_ID
GPTA1_ID
LTCA2_ID
F000 2008H
F000 2808H
DMA_ID
CAN_ID
PCP_ID
RBCU_ID
SSC0_ID
SSC1_ID
FADC_ID
F000 3C08H
F000 4008H
F004 3F08H
F010 0008H
F010 0108H
F010 0208H
F010 0308H
Data Sheet
80
V1.0, 2008-04
TC1796
Functional Description
Table 9
TC1796 Identification Registers (cont’d)
Short Name
ADC0_ID
MLI0_ID
MLI1_ID
MCHK_ID
CPS_ID
CPU_ID
EBU_ID
PMU_ID
FLASH_ID
DMU_ID
DBCU_ID
DMI_ID
Address
Value
Stepping
F010 0408H
F010 C008H
F010 C108H
F010 C208H
F7E0 FF08H
F7E1 FE18H
F800 0008H
F800 0508H
F800 2008H
F801 0108H
F87F FA08H
F87F FC08H
F87F FD08H
F87F FF08H
F87F FE08H
0030 C002H
0025 C005H
0025 C005H
001B C001H
0015 C006H
000A C005H
0014 C005H
002E C002H
0031 C002H
002D C002H
000F C005H
0008 C004H
000B C004H
000C C005H
000F C005H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PMI_ID
LFI_ID
PBCU_ID
Data Sheet
81
V1.0, 2008-04
TC1796
Electrical Parameters
4
Electrical Parameters
4.1
General Parameters
4.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1796
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1796 and must be regarded for a system design.
SR
•
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1796 designed in.
Data Sheet
82
V1.0, 2008-04
TC1796
Electrical Parameters
4.1.2
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 4.2.1.
Table 10
Pad Driver and Pad Classes Overview
Class Power Type Sub Class
Speed Load Leakage Termination
1)
Supply
Grade
A
3.3V
LVTTL A1
6 MHz 100 pF 500 nA
No
I/O,
(e.g. GPIO)
LVTTL
output
A2
40
50 pF 6 µA
50 pF 6 µA
Series
termination
recommended
(e.g.
MHz
serial I/Os)
A3
(e.g.
Trace Outputs,
serial I/Os)
75
Series
MHz
termination
recommended
(for f > 25 MHz)
A4
150
25 pF 6 µA
50 pF 6 µA
Series
(e.g.
MHz
termination
recommended
Trace Clock)
B
2.375 - LVTTL B1
40
MHz
No
3.6V2)
I/O
(e.g.
External Bus
Interface)
B2
75
MHz
35 pF
Series
(e.g.
termination
recommended
(for f > 25 MHz)
Bus Clock)
C
D
3.3V
–
LVDS
–
50
–
Parallel
MHz
termination3),
100 Ω ± 10%
Analog inputs, reference voltage inputs
1) Values are for TJmax = 150 °C.
2) AC characteristics for EBU pins are valid for 2.5 V ± 5% and 3.3 V ± 5%.
3) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.
Data Sheet
83
V1.0, 2008-04
TC1796
Electrical Parameters
4.1.3
Absolute Maximum Ratings
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the
voltage on the related VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Table 11
Parameter
Absolute Maximum Rating Parameters
Symbol Values
Min. Typ. Max.
Unit Note /
Test Con
dition
Ambient temperature
Storage temperature
Junction temperature
TA
TST
TJ
SR -40
SR -65
SR -40
–
–
–
–
125
150
150
2.25
°C
°C
°C
V
Under bias
–
Under bias
–
Voltage at 1.5 V power supply VDD
–
1)
pins with respect to VSS
SR
Voltage at 3.3 V power supply VDDEBU
–
–
3.75
V
V
–
2)
pins with respect to VSS
VDDP SR
Voltage on any Class A input VIN
pin and dedicated input pins
with respect to VSS
SR -0.5 –
VDDP + 0.5
Whatever
is lower
or max. 3.7
Voltage on any Class B input VIN
SR -0.5 –
-0.5 –
V
DDEBU + 0.5 V
Whatever
is lower
Whatever
is lower
pin with respect to VSS
or max. 3.7
Voltage on any Class D
VAIN
V
DDM + 0.5
V
analog input pin with respect VAREFx
or
to VAGND
SR
max. 3.7
Voltage on any Class D
VAINF
-0.5 –
V
DDMF + 0.5 V
Whatever
is lower
analog input pin with respect VFAREF
or
to VSSAF
SR
max. 3.7
1503)
753)
CPU & LMB Bus Frequency fCPU SR –
FPI Bus Frequency fSYS SR –
–
–
MHz –
MHz –
1) Applicable for VDD, VDDSBRAM, VDDOSC, VDDPLL, and VDDAF
.
2) Applicable for VDDP, VDDEBU, VDDFL3, DDM, and VDDMF
V
.
3) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
Data Sheet
84
V1.0, 2008-04
TC1796
Electrical Parameters
4.1.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1796. All parameters specified in the following table refer to these
operating conditions, unless otherwise noticed.
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1796. All parameters specified in the following table refer to these
operating conditions, unless otherwise noted.
Table 12
Parameter
Operating Condition Parameters
Symbol Values
Typ. Max.
Unit Note /
Test Condition
Min.
Digital supply voltage1) VDD
SR 1.42
–
1.583)
3.474)
3.474)
V
V
V
–
VDDOSC2) SR
VDDP
SR 3.13
DDOSC3 SR
VDDEBU SR 2.375 –
–
For Class A pins
(3.3V ± 5%)
For Class B (EBU)
pins
V
VDDFL3 SR 3.13
–
–
3.474)
1.583)
V
V
–
–
5)
VDDSBRAM
1.42
SR
SR 1.0
6)
Voltage on VDDSBRAM
power supply pin to
ensure data retention
VDR
–
–
V
Digital ground voltage
Ambient temperature
under bias
VSS
TA
SR 0
SR –
–
–
V
–
–
-40 +125 °C
Analog supply voltages –
–
–
–
–
See separate
specification
Page 92, Page 99
CPU clock
Short circuit current
fCPU
ISC
SR –7)
SR -5
–
–
–
1508) MHz –
+5
20
9)
mA
Absolute sum of short
circuit currents of a pin
group (see Table 13)
Σ|ISC| SR –
mA See note10)
Inactive device pin
current
IID
SR -1
–
1
mA Voltage on all
power supply pins
V
DDx = 0
Data Sheet
85
V1.0, 2008-04
TC1796
Electrical Parameters
Table 12
Parameter
Operating Condition Parameters
Symbol Values
Typ. Max.
Unit Note /
Test Condition
Min.
Σ|ISC| SR –
Absolute sum of short
circuit currents of the
device
–
100
mA See note10)
External load
capacitance
CL
SR –
–
–
pF
Depending on pin
class. See DC
characteristics
1) Digital supply voltages applied to the TC1796 must be static regulated voltages which allow a typical voltage
swing of ±5%.
2) VDDOSC and VSSOSC are not bonded externally in the BC and BD steps of TC1796. An option for bonding them
in future steps and products is kept open.
3) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 µs and the cumulated summary of the pulses does not exceed 1 h.
4) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than
100 µs and the cumulated summary of the pulses does not exceed 1 h
5) The VDDSB must be properly connected and supplied with power. If not, the TC1796 will not operate. In case
of a stand-by operation, the core voltage must not float, but must be pulled low, in order to avoid internal cross-
currents.
6) This applies only during power down state. During normal SRAM operation regular VDD has to be applied.
7) The TC1796 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time restriction
no lower frequency boundary is tested, however.
8) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
9) Applicable for digital outputs.
10) See additional document “TC1796 Pin Reliability in Overload“ for overload current definitions.
Table 13
Group
Pin Groups for Overload/Short-Circuit Current Sum Parameter
Pins
1
2
3
4
5
6
7
8
P4.[7:0]
P4.[14:8]
P4.15, SLSO[1:0], SCLK0, MTSR0, MRST0, SLSI0
WAIT, HOLD, BC[3:0], HLDA, MR/W, BAA, CSCOMB
CS[3:0], RD, RD/WR, BREQ, ADV, BFCLKO
BFCLKI, D[31:24]
D[23:16]
D[15:8]
Data Sheet
86
V1.0, 2008-04
TC1796
Electrical Parameters
Table 13
Group
9
Pin Groups for Overload/Short-Circuit Current Sum Parameter
Pins
D[7:0]
10
11
12
A[23:16]
A[15:8]
A[7:0]
13
TSTRES, TDI, TMS, TCK, TRST, TDO, BRKOUT, BRKIN, TESTMODE
14
P10.[3:0], BYPASS, NMI, PORST, HDRST
15
P9.[8:0]
16
FCLP[1:0]A, FCLN[1:0], SOP[1:0]A, SON[1:0]
17
P5.[7:0]
18
P3.[7:0]
19
P3.[15:8]
20
P0.[7:0]
21
P0.[15:8]
22
P2.[15:7]
23
24
25
P2.[6:2], P6.9, P6.8, P6.6, P6.11
P6.[15:12], P6.10, P6.7, P6.[5:4]
P8.[7:0]
26
27
28
P1.[15:13], P1.[11:8], P1.5
P1.12, P1.[7:6], P1.[4:0]
TR[15:8]
29
30
TR[7:1], TRCLK
TR0, P7.[7:0]
Data Sheet
87
V1.0, 2008-04
TC1796
Electrical Parameters
4.2
DC Parameters
4.2.1
Input/Output Pins
Table 14
Input/Output DC-Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
General Parameters
Pull-up current1)
|IPUH
|
10
20
5
–
–
–
–
100
200
85
µA VIN < VIHAmin
;
CC
class A1/A2/Input pads.
µA VIN <VIHAmin
;
class A3/A4 pads.
µA VIN < VIHBmin
;
class B1/B2 pads.
Pull-down
current1)
|IPDL
|
10
150
µA VIN >VILAmax
;
CC
CC
class A1/A2/Input pads.
VIN > VILBmax
;
class B1/B2 pads
20
–
–
–
200
10
µA VIN > VILAmax
;
class A3/A4 pads.
Pin capacitance1) CIO
pF f = 1 MHzTA = 25 °C
(Digital I/O)
Input only Pads (VDDP = 3.13 to 3.47 V = 3.3 V ± 5%)
Input low voltage VILA
-0.3
–
0.34 ×
V
V
–
Class A1/A2 pins
SR
VDDP
Input high voltage VIHA
0.64 × –
SR VDDP
VDDP
+
Whatever is lower
Class A1/A2 pins
0.3 or
max.
3.6
Ratio VIL/VIH
Input hysteresis
CC 0.53
–
–
–
–
–
V
–
5)2)
HYSA
0.1 ×
CC VDDP
Input leakage
current
IOZI
–
–
±3000 nA
±6000
V
DDP/2-1 < VIN < VDDP/2+1
CC
Otherwise3)
Data Sheet
88
V1.0, 2008-04
TC1796
Electrical Parameters
Table 14
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
Output low
VOLA
–
–
0.4
V
IOL = 2 mA for strong
driver mode,
voltage4)
CC
IOL = 1.8 mA for medium
driver mode, A2 pads
IOL = 1.4 mA for medium
driver mode, A1 pads
IOL = 370 µA for weak
driver mode
Output high
voltage3)
VOHA
2.4
–
–
–
V
V
I
OH = -2 mA for strong
driver mode,
OH = -1.8 mA for medium
driver mode, A1/A2 pads
OH = -370 µA for weak
driver mode
OH = -1.4 mA for strong
driver mode,
OH = -1 mA for medium
driver mode, A1/A2 pads
CC
I
I
V
DDP - –
I
0.4
I
I
OH = -280 µA for weak
driver mode
–
Input low voltage VILA
-0.3
–
0.34 ×
VDDP
VDDP
0.3 or
3.6
V
V
Class A1/2 pins
SR
Input high voltage VIHA
0.64 × –
SR VDDP
+
Whatever is lower
Class A1/2 pins
Ratio VIL/VIH
Input hysteresis
CC 0.53
–
–
–
–
–
V
–
5)2)
HYSA
0.1 ×
CC VDDP
Input leakage
current Class
A2/3/4 pins
Input leakage
current
Class A1 pins
IOZA24
–
–
–
±3000 nA
±6000
V
DDP/2-1 < VIN < VDDP/2+1
Otherwise3)
IOZA1
–
±500
nA 0 V < VIN < VDDP
CC
Data Sheet
89
V1.0, 2008-04
TC1796
Electrical Parameters
Table 14
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Class B Pads (VDDEBU = 2.375 to 3.47 V)
Output low voltage VOLB CC –
–
–
0.4
–
V
V
IOL = 2 mA
IOL = 2 mA
Output high
VOHB
VDDEBU
voltage
CC - 0.4
Input low voltage VILB
Input high voltage VIHB
–
-0.3 0.34 ×
V
V
–
SR
VDDEBU
0.64 × –
SR VDDEBU
VDDEBU
+0.3 or
3.6
Whatever is lower
Ratio VIL/VIH
Input hysteresis
CC 0.53
–
–
–
–
–
V
–
5)
HYSB
0.1 ×
CC VDDEBU
Input leakage
current
Class B pins
IOZB
–
–
±3000 nA
±6000
V
V
DDEBU/2-0.6 < VIN <
CC
DDEBU/2+0.66)
Otherwise3)
Class C Pads (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
Output low voltage VOL CC 815
–
–
–
–
–
mV Parallel termination
100 Ω ± 1%
Output high
voltage
VOH CC
1545
600
mV Parallel termination
100 Ω ± 1%
Output differential VOD CC 150
mV Parallel termination
voltage
100 Ω ± 1%
Output offset
voltage
VOS CC 1075
1325
140
mV Parallel termination
100 Ω ± 1%
Output impedance R0 CC 40
Ω
–
Class D Pads
See ADC Characteristics
–
–
–
–
–
1) Not subject to production test, verified by design / characterization.
2) The pads that have spike-filter function in the input path: PORST, HDRST, NMI, do not have hysteresis.
3) Only one of these parameters is tested, the other is verified by design characterization
4) Max. resistance between pin and next power supply pin 25 Ω for strong driver mode
(verified by design characterization).
Data Sheet
90
V1.0, 2008-04
TC1796
Electrical Parameters
5) Function verified by design, value verified by design characterization.
Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce.
It cannot be guaranteed that it suppresses switching due to external system noise.
6) VDDEBU = 2.5 V ± 5%. For VDDEBU = 3.3 ± 5% see class A2 pads.
Data Sheet
91
V1.0, 2008-04
TC1796
Electrical Parameters
4.2.2
Analog to Digital Converters (ADC0/ADC1)
Table 15
ADC Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Typ.
3.3
Unit Note /
Test Condition
Min.
VDDM SR 3.13
SR 1.42
Max.
3.471)
1.582)
Analog supply
voltage
V
V
–
VDD
1.5
Power supply for
ADC digital part,
internal supply
Analog ground
voltage
VSSM SR -0.1
–
0.1
V
V
–
Analog reference VAREFx SR VAGNDx VDDM
VDDM+
–
voltage17)
+1V
0.05
1)3)4)
Analog reference VAGNDx SR VSSMx - 0
V
AREF - V
–
–
–
ground17)
0.05V
1V
Analog input
voltage range
VAIN
SR VAGNDx
–
VAREFx
V
Analog reference VAREFx
-
VDDM/2 –
VDDM + V
0.05
voltage range5)17) VAGNDx SR
VDDM
IDDM
tPUC
SR –
CC –
2.5
4
mA For each module6)
rms
supply current
Power-up
calibration time
–
3840
fADC
–
CLK
Internal ADC
clocks
fBC
fANA
CC 2
CC 0.5
–
–
–
–
–
40
10
±1
±2
±4
MHz fBC = fANA × 4
MHz fANA = fBC / 4
LSB 8-bit conversion.
Total unadjusted TUE7) CC –
error5)
–
–
LSB 10-bit conversion
LSB 12-bit conversion
8)9)
–
–
±8
LSB 12-bit conversion
10)9)
DNL error11) 5)
INL error11)5)
TUEDNL
TUEINL
–
–
±1.5
±1.5
±3.0
±3.0
LSB 12-bit conversion
12)9)
CC
CC
LSB 12-bit conversion
12)9)
Data Sheet
92
V1.0, 2008-04
TC1796
Electrical Parameters
Table 15
ADC Characteristics (cont’d) (Operating Conditions apply)
Parameter
Symbol
Values
Typ.
±0.5
Unit Note /
Test Condition
Min.
–
Max.
±3.5
Gain error11)5)
Offset error11)5)
TUEGAIN
LSB 12-bit conversion
12)9)
CC
TUEOFF
–
±1.0
–
±4.0
300
LSB 12-bit conversion
12)9)
CC
Input leakage
IOZ1
CC -1000
-200
nA
nA
nA
nA
nA
nA
nA
nA
µA
(0% VDDM) < VIN <
(2% VDDM
(2% VDDM) < VIN <
(95% VDDM
(95% VDDM) <VIN <
(98% VDDM
(98% VDDM) <VIN <
(100% VDDM
(0% VDDM) < VIN <
(2% VDDM
(2% VDDM) < VIN <
(95% VDDM
(95% VDDM) <VIN <
(98% VDDM
current at analog
inputs AN0, AN1,
AN4 to AN7,
)
–
400
)
AN24 to AN31.
-200
–
1000
3000
200
see Figure 24
)
13) 14)
-200
–
)
Input leakage
current at the
other analog
inputs, that is
AN2, AN3,
IOZ1
CC -1000
-200
–
)
–
300
)
-200
–
1000
3000
±1
AN8 to AN23,
AN32 to AN43
)
-200
–
(98% VDDM) <VIN <
see Figure 24
14)
(100% VDDM
)
Input leakage
current at VAREF
IOZ2
CC –
–
0 V < VAREF
<
VDDM, no
conversion
running
Input current at
IAREF CC –
35
–
75
25
µA
0 V < VAREF
<
17)
15)
VAREF0/1
rms VDDM
9)
Total capacitance CAREFTOT
–
pF
of the voltage
reference
CC
inputs16)17)
9)18)
Switched
CAREFSW
–
15
93
20
pF
capacitance at the
positive reference
voltage input17)
CC
Data Sheet
V1.0, 2008-04
TC1796
Electrical Parameters
Table 15
ADC Characteristics (cont’d) (Operating Conditions apply)
Parameter
Symbol
Values
Typ.
1
Unit Note /
Test Condition
Min.
–
Max.
1.5
Resistance of the RAREF
reference voltage
input path16)
kΩ
500 Ohm
CC
increased for
AN[1:0] used as
reference input9)
6)9)
Total capacitance CAINTOT
of the analog
–
–
–
–
25
7
pF
pF
CC
CC
inputs16)
9)19)
9)
Switched
CAINSW
capacitance at the
analog voltage
inputs
ON resistance of RAIN
the transmission
gates in the
analog voltage
path
CC –
1
1.5
kΩ
ON resistance for RAIN7T CC 200
300
1000
Ω
Test feature
available only for
AIN79)
the ADC test (pull-
down for AIN7)
Current through
resistance for the
ADC test (pull-
down for AIN7)
IAIN7T CC –
15 rms 30 peak mA Test feature
available only for
AIN79)
1) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 µs and the cumulated
summary of the pulses does not exceed 1 h.
2) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 µs and the cumulated
summary of the pulses does not exceed 1 h.
3) A running conversion may become inexact in case of violating the normal operating conditions (voltage
overshoot).
4) If
the
reference
voltage
VAREF
increases
or
the
VDDM
decreases,
so
that
V
AREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decreases by 4LSB12.
5) If a reduced reference voltage in a range of VDDM/2 to VDDM is used, then the ADC converter errors increase.
If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase
with the factor 1/k.
If a reduced reference voltage in a range of 1 V to VDDM/2 is used, then there are additional decrease in the
ADC speed and accuracy.
6) Current peaks of up to 6 mA with a duration of max. 2 ns may occur
7) TUE is tested at VAREF = 3.3 V, VAGND = 0 V and VDDM = 3.3 V
Data Sheet
94
V1.0, 2008-04
TC1796
Electrical Parameters
8) ADC module capability.
9) Not subject to production test, verified by design / characterization.
10) Value under typical application conditions due to integration (switching noise, etc.).
11) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error.
12) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25.
For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625.
13) The leakage current definition is a continuous function, as shown in Figure 24. The numerical values defined
determine the characteristic points of the given continuous linear approximation - they do not define step
function.
14) Only one of these parameters is tested, the other is verified by design characterization.
15) IAREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion
with a duration of up to tC = 25µs can be calculated with the formula IAREF_MAX = QCONV/tC. Every conversion
needs a total charge of QCONV = 150pC from VAREF
.
All ADC conversions with a duration longer than tC = 25µs consume an IAREF_MAX = 6µA.
16) For the definition of the parameters see also Figure 23.
17) Applies to AIN0 and AIN1, when used as auxiliary reference inputs.
18) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this smaller capacitances are successively switched to the reference voltage.
19) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx is lower then VAREF/2, typically 0.85V.
Data Sheet
95
V1.0, 2008-04
TC1796
Electrical Parameters
Table 16
Sample and Conversion Time (Operating Conditions apply)
Parameter Symbol
Values
Typ.
Unit Note
Min.
Max.
Sample
time
tS
CC
4 × (CHCONn.STC + 2) × tBC
µs
µs
µs
µs
µs
–
–
8 × tBC
–
–
Conversion tC CC
tS + 40 × tBC + 2 × tDIV
tS + 48 × tBC + 2 × tDIV
tS + 56 × tBC + 2 × tDIV
8-bit conversion
10-bit conversion
12-bit conversion
time
A/D Converter Module
Sample
Programmable
Time tS
fANA
fDIV
fBC
Fractional
Programmable
Counter
fCLC
Clock Divider
1:4
Divider
(1:1) to (1:256)
CON.CTC
CHCONn.STC
fTIMER
Arbiter
Control Unit
(Timer)
Control/Status Logic
Interrupt Logic
(1:20)
External Trigger Logic
External Multiplexer Logic
Request Generation Logic
MCA04657_mod
Figure 22
ADC0/ADC1 Clock Circuit
Data Sheet
96
V1.0, 2008-04
TC1796
Electrical Parameters
Analog Input Circuitry
RAIN, On
REXT
ANx
VAIN
CEXT
CAINSW
=
CAINTOT - CAINSW
VAGNDx
RAIN7T
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFTOT - CAREFSW
CAREFSW
VAGNDx
Analog_InpRefDiag
Figure 23
ADC0/ADC1 Input Circuits
Data Sheet
97
V1.0, 2008-04
TC1796
Electrical Parameters
IOZ1
3uA
AN0, AN1,
AN4 - AN7,
AN24 - AN31
1uA
400nA
300nA
VIN[VDDM %]
-200nA
95% 98%100%
2%
-1uA
IOZ1
3uA
Others
1uA
300nA
200nA
VIN[VDDM%]
95% 98%100%
-200nA
2%
-1uA
ADC Leakage 7.vsd
Figure 24
ADC0/ADC1Analog Inputs Leakage
Data Sheet
98
V1.0, 2008-04
TC1796
Electrical Parameters
4.2.3
Fast Analog to Digital Converter (FADC)
Table 17
FADC Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Typ. Max.
–
–
–
Unit
Note /
Test Condition
Min.
10)
DNL error
INL error
Gradient error1)10)
EDNL CC –
EINL CC –
±1
±4
±3
LSB
LSB
%
10)
EGRAD
EGRAD
EGRAD
–
–
–
With calibration,
gain 1, 22)
Without calibration
gain 1, 2, 4
Without calibration
gain 8
With calibration2)
Without calibration
–
CC
CC
CC
CC
–
–
±5
±6
%
%
Offset error10)
EOFF
–
–
–
–
–
–
±204)
±604)
±60
mV
mV
mV
3)
Reference error of
internal VFAREF/2
Analog supply
voltages
EREF
CC
VDDMF SR 3.13
VDDAF SR 1.42
–
–
–
3.475)
1.586)
0.1
V
V
V
–
–
–
Analog ground
voltage
Analog reference
voltage
Analog reference
ground
VSSAF
-0.1
SR
SR
VFAREF
VFAGND
3.13
–
3.475)7)
V
V
V
Nominal 3.3 V
V
SSAF - –
VSSAF
–
–
SR 0.05V
+0.05V
Analog input voltage VAINF
VFAGND
–
VDDMF
range
SR
Analog supply
currents
IDDMF SR –
IDDAF SR –
–
–
–
9
17
150
mA
mA
µA
rms
–
8)
Input current at each IFAREF
–
–
–
Independent of
conversion
0 V < VIN < VDDMF
VFAREF
CC
CC
CC
Input leakage current IFOZ2
–
–
±500
±8
nA
9)
at VFAREF
Input leakage current IFOZ3
µA
0 V < VIN < VDDMF
at VFAGND
Data Sheet
99
V1.0, 2008-04
TC1796
Electrical Parameters
Table 17
FADC Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Values
Typ. Max.
–
Unit
Note /
Test Condition
Min.
CC –
Conversion time
Converter Clock
Input resistance of
the analog voltage
path (Rn, Rp)
tC
21
CLK of 10-bit conversion
fADC
MHz
kΩ
fADC CC –
–
–
75
200
–
10)
RFAIN
100
CC
Channel Amplifier
Cutoff Frequency
Settling Time of a
Channel Amplifier
after changing ENN
or ENP
fCOFF
tSET
2
–
–
–
5
MHz
–
–
CC
CC –
µsec
1) Calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8.
2) Calibration should be performed at each power-up. In case of continuous operation, calibration should be
performed minimum once per week.
3) The offset error voltage drifts over the whole temperature range maximum ±3 LSB.
4) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must
be multiplied with the applied gain.
5) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 µs and the cumulated
summary of the pulses does not exceed 1 h.
6) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 µs and the cumulated
sum of the pulses does not exceed 1 h.
7) A running conversion may become inexact in case of violating the normal operating conditions (voltage
overshoots).
8) Current peaks of up to 40 mA with a duration of max. 2 ns may occur
9) This value applies in power-down mode.
10) Not subject to production test, verified by design / characterization.
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized. The offset calibration must run first,
followed by the gain calibration.
Data Sheet
100
V1.0, 2008-04
TC1796
Electrical Parameters
FADC Analog Input Stage
RN
FAINxN
-
+
VFAREF/2
VFAGND
+
RP
FAINxP
-
FADC Reference Voltage
Input Circuitry
VFAREF
IFAREF
VFAREF
VFAGND
FADC_InpRefDiag
Figure 25
FADC Input Circuits
Data Sheet
101
V1.0, 2008-04
TC1796
Electrical Parameters
4.2.4
Oscillator Pins
Table 18
Oscillator Pins Characteristics (Operating Conditions apply)
Parameter
Symbol
Min.
fOSC CC 4
Values
Typ. Max.
–
–
Unit Note /
Test Condition
Frequency Range
25
0.3 ×
VDDOSC3
MHz –
Input low voltage at VILX SR -0.2
V
–
XTAL11)
Input high voltage at VIHX SR 0.7 ×
–
–
VDDOSC3
V
–
XTAL11)
VDDOSC3
+ 0.2
Input current at
XTAL1
IIX1 CC –
±25
µA
0 V < VIN < VDDOSC3
1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 × VDDOSC3 is
necessary.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal
supplier.
Data Sheet
102
V1.0, 2008-04
TC1796
Electrical Parameters
4.2.5
Temperature Sensor
Table 19
Temperature Sensor Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Cond
Min. Typ.
Max.
ition
Temperature
TSR
SR -40
150
°C
µs
°C
–
Sensor Range
Start-up time after
resets inactive
Sensor Inaccuracy TTSA
tTSST SR –
–
10
–
CC –
SR –
–
–
±10
10
–
A/D Converter clock fANA
MHz conversion
with ADC1
for DTS signal
Table 20
Parameter
Temperature Sensor Characteristics (Operating Conditions apply)
Symbol Typical Value Unit Note
Temperature of TTS CC TTS× = (ADC_Code - 487) 0.396 - 40 °C
10-bit ADC
the die at the
result
sensor location
TTS× = (ADC_Code - 1948) 0.099 - 40 °C
12-Bit ADC
result
Data Sheet
103
V1.0, 2008-04
TC1796
Electrical Parameters
4.2.6
Power Supply Current
???
Table 21
Power Supply Currents (Operating Conditions apply)
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note /
Test Condition
PORST low current at IDD_PORST
–
–
300
mA The PLL running at
the base frequency
VDD
CC
PORST low current at IDDP_PORST
–
–
25
mA The PLL running at
the base frequency
V
DDP, and PORST high
CC
current without any port
activity
Active mode core
IDD
10
–
–
–
–
–
–
–
–
–
700
–
mA
f
CPU=150MHzfCPU/f
supply current1)2)
CC
CC
CC
CC
CC
CC
CC
SR
SYS = 2:1
Active mode analog
supply current
IDDAx;
IDDMx
mA See ADC0/1
FADC
Stand-by RAM supply ISBSB
–
9
mA
mA
mA
VDDSB = 1V,
current in stand-by
Tj = 150oC
3)
Oscillator and PLL core IDDOSC
–
5
–
power supply
Oscillator and PLL pads IDDOSC3
–
3.6
50
80
–
power supply
LVDS port supply
ILVDS
IDDFL3
PD
–
mA LVDS pads active
4)
(via VDDP
)
Flash power supply
current
Maximum Allowed
Power Dissipation5)
–
mA
–
–
–
PD ×
RTJA
<
worst case
TA = 125oC
25oC
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each custom
application will most probably be lower than this value, but must be evaluated separately.
2) The IDD decreases for typically 120 mA if the fCPU is decreased for 50 MHz, at constant TJ = 150C, for the
Infineon Max Power Loop.
The dependency in this range is, at constant junction temperature, linear.
3) VDDOSC and VSSOSC are not bonded externally in the BC and BD steps of TC1796. An option for bonding them
in future steps and products is kept open.
4) In case the LVDS pads are disabled, the power consumption pro pair is negligible (less than 1µA).
5) For the calculation of junction to ambient thermal resistance RTJA, see Page 130.
Data Sheet
104
V1.0, 2008-04
TC1796
Electrical Parameters
4.3
AC Parameters
All AC parameters are defined with the temperature compensation disabled. That
means, keeping the pads constantly at maximum strength.
4.3.1
Testing Waveforms
VDDP
VDDEBU
90%
90%
10%
10%
VSS
tR
tF
rise_fall
Figure 26
Rise/Fall Time Parameters
VDDP
VDDEBU
VDDE / 2
VDDE / 2
Test Points
VSS
mct04881_a.vsd
Figure 27
Testing Waveform, Output Delay
VLoad+ 0.1 V
VLoad- 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VOL - 0.1 V
MCT04880_new
Figure 28
Testing Waveform, Output High Impedance
Data Sheet
105
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.2
Output Rise/Fall Times
Table 22
Output Rise/Fall Times (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min. Typ. Max.
Class A1 Pads
Rise/fall
t
RA1, tFA1
–
–
–
–
50
ns
ns
Regular (medium) driver, 50 pF
Regular (medium) driver, 150 pF
Regular (medium) driver, 20 nF
Weak driver, 20 pF
times 1)
140
18000
150
550
Weak driver, 150 pF
65000
Weak driver, 20 000 pF
Class A2 Pads
Rise/fall
t
RA2, tFA2
3.3
Strong driver, sharp edge, 50 pF
Strong driver, sharp edge, 100pF
Strong driver, medium edge, 50 pF
Strong driver, soft edge, 50 pF
Medium driver, 50 pF
times 1)
6
5.5
16
50
140
18000
150
550
65000
Medium driver, 150 pF
Medium driver, 20 000 pF
Weak driver, 20 pF
Weak driver, 150 pF
Weak driver, 20 000 pF
Class A3 Pads
Rise/fall
t
RA3, tFA3
RA3, tFA3
tRB, tFB
–
–
–
–
–
–
2.5
2.0
ns
ns
ns
50 pF
25 pF
times 1)
Class A4 Pads
Rise/fall
t
times 1)
Class B Pads
Rise/fall
3.0
4.0
7.0
35 pF
50 pF
100 pF
times 1)2)
Class C Pads
Rise/fall
times
tRC, tFC
–
–
2
ns
–
1) Not all parameters are subject to production test, but verified by design/characterization and test correlation.
Data Sheet
106
V1.0, 2008-04
TC1796
Electrical Parameters
2) Parameter test correlation for VDDEBU = 2.5 V ± 5%
4.3.3
Power Sequencing
There is a restriction for the power sequencing of the 3.3 V domain including VDDEBU as
shown in Figure 29: it must always be higher than 1.5 V domain - 0.5 V. The grey area
shows the valid range for V3.3V and VDDEBU relative to an exemplary 1.5 V ramp.
V
DDP, VDDOSC3, VDDFL3, VDDM, VDDMF belong to the 3.3 V power supply domain, that is
referenced in Figure 29 as V3.3. The VDDM and VDDMF sub domains are connected with
anti parallel ESD protection diodes in TC1796 design steps BC and BD. The VDDM
,
V
DDMF, VDDP, VDDOSC3 sub domains are connected with anti parallel ESD protection
diodes in TC1796 design step BE.
VDD, VDDOSC and VDDAF belong to the 1.5 V power supply domain, referenced as V1.5.
V
DDEBU belongs to its own 2.5V to 3.3V domain.
3.3V
V3.3, VDDEBU
V1.5
1.5V
V3.3, VDDEBU > V1.5 - 0.5V
Time
VDDP
(3.3V)
PORST
Time
PowerSeq 2
Figure 29
VDDP / VDDEBU / VDD Power Up Sequence
All ground pins VSS must be externally connected to one single star point in the system.
The difference voltage between the ground pins must not exceed 200 mV.
The PORST signal must be activated at latest before any power supply voltage falls
below the levels shown on the figure below. In this case, only the memory row of a Flash
memory that was a target of a write at the moment of the power loss will contain
unreliable content. Additionally, the PORST signal should be activated as soon as
possible. The sooner the PORST signal is activated, the less time the system operates
outside of the normal operating power supply range.
Data Sheet
107
V1.0, 2008-04
TC1796
Electrical Parameters
Power Supply Voltage
VDDP, VDDEBU,
VDDP
3.3V
VDDFL3
3.13V
-5%
VDDPmin
VPORST3.3
2.9V
-12%
t
PORST
t
VDD
1.5V
VDD
1.42V
-5%
VDDmin
1.32V
-12%
VPORST1.5min
t
t
PORST
PowerDown3.3_1.5_reset_only.vsd
Figure 30
Power Down / Power Loss Sequence
Data Sheet
108
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.4
Power, Pad and Reset Timing
Table 23
Power, Pad and Reset Timing Parameters
Parameter
Symbol
Values
Unit Note /
Test Con
Min.
Typ. Max.
dition
Min. VDDP voltage to ensure
V
DDPPA CC 0.6
–
–
V
–
defined pad states1)
Oscillator start-up time2)
Minimum PORST active time tPOA
after power supplies are stable
at operating levels
tOSCS CC –
–
–
10
–
ms
ms
–
–
SR 10
HDRST pulse width
tHD
CC 1024
clock
–
–
fSYS
–
cycles3)6)
PORST rise time
Setup time to PORST rising
edge4)
tPOR
tPOS
SR –
SR 0
–
–
50
–
ms
ns
–
–
Hold time from PORST rising tPOH
SR 100
SR 0
–
–
–
–
–
–
ns
ns
ns
–
–
–
edge4)
Setup time to HDRST rising
tHDS
edge5)
Hold time from HDRST rising tHDH
SR 100 +
edge5)
(2 × 1/
6)
fSYS
)
Ports inactive after PORST
reset active7)8)
Ports inactive after HDRST
reset active
tPIP
tPI
CC –
–
–
150
ns
–
–
CC –
150 + ns
5 × 1/
fSYS
Minimum VDDP PORST
VPORST3.3
–
–
–
–
2.9
V
V
–
–
activation threshold9)
SR
Minimum VDD PORST
VPORST1.5
1.32
activation threshold9)
SR
CC –
Power on Reset Boot Time9) tBP
–
–
2
350
ms
µs
–
–
Hardware/Software Reset
tB
CC 150
Boot Time at fCPU=150MHz10)
Data Sheet
109
V1.0, 2008-04
TC1796
Electrical Parameters
1) This parameter is valid under assumption that PORST signal is constantly at low level during the power-
up/power-down of the VDDP
.
2) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of
0,3*VDDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
3) Any HDRST activation is internally prolonged to 1024 FPI bus clock (fSYS) cycles.
4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST
switched-on (BYPASS = 0).
5) The setup/hold values are applicable for Port 0 and Port 10 input pins with noise suppression filter of HDRST
switched-on (BYPASS = 0), independently whether HDRST is used as input or output.
6) fSYS = fCPU/2
7) Not subject to production test, verified by design / characterization.
8) This parameter includes the delay of the analog spike filter in the PORST pad.
9) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
user instruction has entered the CPU and its processing starts.
10) The duration of the boot time is defined between the following events:
1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction
has entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024 × TSYS
.
If the HDRST pulse is longer than 1024 × TSYS, only the time beyond the 1024 × TSYS should be added to the
boot time (HDRST falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
Data Sheet
110
V1.0, 2008-04
TC1796
Electrical Parameters
VDDPPA
VDDPPA
VDDP
VDDPR
VDD
toscs
OSC
tPOA
tPOA
PORST
HDRST
thd
thd
1)
2)
1)
2)
2)
Pads
tpi
Pad-
state
Pad-
state
undefined
1) as programmed
undefined
2) Tri-state, pull device active
reset_beh1
Figure 31
Power, Pad and Reset Timing
Data Sheet
111
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.5
Phase Locked Loop (PLL)
Note: All PLL characteristics defined on this and the next page are verified by design
characterization.
Table 24
PLL Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Con
Min.
dition
Accumulated jitter
DP
See
–
–
–
–
Figure 3
2
VCO frequency range
fVCO
400
600
500
140
150
200
–
–
–
–
–
–
–
–
500
700
600
320
400
480
200
MHz –
MHz –
MHz –
MHz –
MHz –
MHz –
PLL base frequency1)
fPLLBASE
PLL lock-in time
tL
µs
–
1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
the K factor after reset).
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the CPU
clock fCPU) is constantly adjusted to the selected frequency. The relation between fVCO
and fSYS is defined by: fVCO = K × fCPU. The PLL causes a jitter of fCPU and affects the
clock outputs BFCLKO, TRCLK, and SYSCLK (P1.12) which are derived from the PLL
clock fVCO
.
There will be defined two formulas that define the (absolute) approximate maximum
value of jitter DP in ns dependent on the K-factor, the CPU clock frequency fCPU in MHz,
and the number P of consecutive fCPU clock periods.
7000 × P
P × K < 385
Dp[ns] = ------------------------------------------ + 0, 535
fcpu2[MHz] × K
(1)
(2)
2700000
P × K ≥ 385
Dp[ns] = --------------------------------------------- + 0 , 5 3 5
fcpu2[MHz] × K2
Data Sheet
112
V1.0, 2008-04
TC1796
Electrical Parameters
Note: The frequency of system clock fSYS can be selected to be either fCPU or fCPU/2.
With rising number P of clock cycles the maximum jitter increases linearly up to a value
of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum
accumulated jitter remains at a constant value. Further, a lower CPU clock frequency
f
CPU results in a higher absolute maximum jitter value.
Figure 32 gives the jitter curves for several K/fCPU combinations.
±20.0
fCPU = 50 MHz (K = 8)
fCPU = 100 MHz (K = 4)
DP
ns
±16.0
±12.0
±8.0
±4.0
±0.0
fCPU = 120 MHz (K = 4)
fCPU = 150 MHz (K = 4)
fCPU = 100 MHz (K = 7)
fCPU = 50 MHz (K = 14)
0
20
40
60
80
100
120
oo
P
DP
= Max. jitter
P
= Number of consecutive fCPU periods
K
= K-divider of PLL
TC1976_PLL_JITT
Figure 32
Approximated Maximum Accumulated PLL Jitter for Typical CPU
Clock Frequencies fCPU (overview)
Data Sheet
113
V1.0, 2008-04
TC1796
Electrical Parameters
±4.0
ns
±3.5
fCPU = 50 MHz (K = 8)
fCPU = 50 MHz (K = 14)
DP
±3.0
±2.5
±2.0
±1.5
±1.0
±0.5
±0.0
fCPU = 100 MHz (K = 4)
fCPU = 100 MHz (K = 7)
fCPU = 150 MHz (K = 4)
0
2
4
6
8
10
12
14
16
18
20
P
DP
= Max. jitter
P
= Number of consecutive fCPU periods
K
= K-divider of PLL
TC1976_PLL_DETAIL
Figure 33
Approximated Maximum Accumulated PLL Jitter for Typical CPU
Clock Frequencies fCPU (detail)
Note: The specified PLL jitter values are valid if the capacitive load at the External Bus
Unit (EBU) is limited to CL=20pF.
Note: The maximum peak-to-peak noise on the Core Supply Voltage (measured
between VDD at pin E23 and VSS at pin D23, or adjacent supply pairs) is limited to
a peak-to-peak voltage of VPP = 30mV. This condition can be achieved by
appropriate blocking of the Core Supply Voltage as near as possible to the supply
pins and using PCB supply and ground planes.=20pF.
Data Sheet
114
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.6
BFCLKO Output Clock Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%;
TA = -40 °C to +125 °C; CL = 35 pF
Table 25
BFCLK0 Output Clock Timing Parameters1)
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Con
Min.
dition
BFCLKO clock period
BFCLKO high time
BFCLKO low time
BFCLKO rise time
BFCLKO fall time
t
BFCLKO CC 13.332)
–
–
–
–
–
50
–
–
–
3
3
55
ns
ns
ns
ns
ns
%
–
–
–
–
–
t5
t6
t7
t8
CC 3
CC 3
CC –
CC –
BFCLKO duty cycle t5/(t5 + t6)3) DC24 CC 45
divider of
2, 4, ...4)
BFCLKO duty cycle t5/(t5 + t6)3) DC3 CC 30
33.33 36
%
divider of
3 4)
BFCLKO high time reduction5) dt5
1) Not subject to production test, verified by design/characterization.
CC –
–
1.1
ns
CL = 20pF
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K-divider setting
determines the duty cycle.
4) The division ratio between LMB and BFCLKO frequency is set by EBU_BFCON.EXTCLOCK.
5) Due to asymmetry of the delays and slopes of the rising and falling edge of the pad. The influence of the PLL
jitter is included in this parameter. This parameter should be applied taking the typical value of the duty cycle
in the account, not the minimum or maximum value.
tBFCLKO
0.9 VDD
0.5 VDDP05
BFCLKO
0.1 VDD
t8
t7
t5
t6
MCT04883_mod
Figure 34
BFCLKO Output Clock Timing
Data Sheet
115
V1.0, 2008-04
TC1796
Electrical Parameters
BFCLK Timing and PLL Jitter
The BFCLK timing is important for calculating the timing of an external flash memory. In
principle BFCLK timing can be derived from the PLL jitter formulas. In case of only EBU
synchronous read access to the flash device the worst case jitter is partially lower.
For one BFCLK with a cycle time of 13,33 ns the maximum jitter is
t
JPP = |+/-620 ps|
For two BFCLKs with an accumulated cycle time of 26,66 ns the maximum jitter is
JPACC = |+/- 660 ps|
t
Data Sheet
116
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.7
Debug Trace Timing
VSS = 0 V; VDDP = 3.13 to 3.47 V (Class A); TA = -40 °C to +125 °C;
CL (TRCLK) = 25 pF; CL (TR[15:0]) = 50 pF;
Table 26
Debug Trace Timing Parameter1)
Parameter
Symbol
Min.
Values
Typ.
Unit Note /
Test Con
Max.
dition
TR[15:0] new state from
TRCLK rising edge
t9
CC -1
–
4
ns
–
1) Not subject to production test, verified by design/characterization.
TRCLK
t9
Old State
New State
TR[15:0]
Trace_Tmg
Figure 35
Debug Trace Timing
Data Sheet
117
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.8
JTAG Interface Timing
Operating Conditions apply, CL = 50 pF
Table 27
Parameter
TCK Clock Timing Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
TCK clock period1)
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
tTCK
t1
t2
t3
t4
.
SR 25
–
–
–
–
–
–
–
–
4
4
ns
ns
ns
ns
ns
–
–
–
–
–
SR 10
SR 10
SR –
SR –
1) fTCK should be lower or equal to fSYS
tTCK
0.9 VDD
0.1 VDD
0.5 VDDP
TCK
t4
t3
t1
t2
JTAG_TCK
Figure 36
TCK Clock Timing
Data Sheet
118
V1.0, 2008-04
TC1796
Electrical Parameters
Table 28
Parameter
JTAG Timing Parameters1)
Symbol
Values
Typ. Max.
Unit Note /
Test Con
dition
Min.
TMS setup to TCK rising edge t1
SR 6.0
–
–
–
–
–
–
–
–
–
–
–
13
–
14
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
TMS hold to TCK rising edge
TDI setup to TCK rising edge
TDI hold to TCK rising edge
t2
t1
t2
t3
t3
t4
SR 6.0
SR 6.0
SR 6.0
CC –
CC 3.0
CC –
TDO valid output from TCK
CL = 50 pF
CL = 20 pF
CL = 50 pF
falling edge2)
TDO high impedance to valid
output from TCK falling edge2)
TDO valid output to high
impedance from TCK falling
edge2)
t5
CC –
–
13.5
ns
CL = 50 pF
1) fTCK should be lower or equal to fSYS
.
2) The falling edge on TCK is used to capture the TDO timing.
TCK
t1
t1
t2
t2
TMS
TDI
t4
t3
t5
TDO
Jtag
Figure 37
JTAG Timing
Note: The JTAG module is fully compliant with IEEE1149.1-2000 with JTAG clock at
20 MHz. The JTAG clock at 40MHz is possible with the modified timing diagram
shown in Figure 37.
Data Sheet
119
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.9
EBU Demultiplexed Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40 °C to +125 °C; CL = 35 pF;
Table 29
Parameter
EBU Demultiplexed Timing Parameters1)
Symbol Values
Typ. Max.
Unit Note /
Test Con
Min.
CC 0
dition
Output delay from BFCLKO
rising edge2)
t10
t12
–
–
–
–
–
–
–
5
3
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
–
RD active/inactive after
CC 0
–
–
–
–
–
–
BFCLKO rising edge2)
Data setup to BFCLKO rising t13
SR 8.5
SR 0
SR 3
SR 2
SR 0
edge2)
Data hold from BFCLKO rising t14
edge2)
WAIT setup (low or high) to
t15
t16
BFCLKO rising edge2)
WAIT hold (low or high) from
BFCLKO rising edge2)
Data hold after RD/WR rising t17
edge
1) Not subject to production test, verified by design/characterization.
2) Valid for BFCON.EXTCLOCK = 00B.
Data Sheet
120
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.9.1 Demultiplexed Read Timing
Address
Phase
Command Del. Command
Phase (opt.) Phase
Recovery New Addr.
Phase (opt.)
Phase
BFCLKO
t10
t10
t10
Next
A[23:0]
ADV
Valid Address
Inval. Address
Addr.
t10
t10
t10
t10
t10
t10
CS[3:0]
CSCOMB
t12
t12
RD
RD/WR
MR/W
D[31:0]
BC[3:0]
WAIT
t14
t13
Valid Data
t10
t10
t10
t16
t15
DemuxRD_1.vsd
Figure 38
EBU Demultiplexed Read Timing
Data Sheet
121
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.9.2 Demultiplexed Write Timing
Address
Phase
Command Del. Command
Data Hold
Phase
Recovery New Addr.
Phase (opt.)
Phase
Phase (opt.)
Phase
BFCLKO
t10
t10
t10
Next
A[23:0]
ADV
Valid Address
Inval. Address
Addr.
t10
t10
t10
t10
t10
t10
CS[3:0]
CSCOMB
RD
t10
t10
RD/WR
MR/W
D[31:0]
BC[3:0]
WAIT
t17
t10
t10
t10
t10
Data Out
t10
t10
t10
t10
t16
t15
DemuxWR_1.vsd
Figure 39
EBU Demultiplexed Write Timing
Data Sheet
122
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.10
EBU Burst Mode Read Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40 °C to +125 °C; CL = 35 pF;
Table 30
EBU Burst Mode Read Timing Parameters1)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
Output delay from BFCLKO
rising edge
RD active/inactive after
BFCLKO rising edge
CSx output delay from
BFCLKO rising edge
t10
t12
t21
CC 0
–
–
–
–
–
–
–
–
5
ns
ns
ns
ns
ns
ns
ns
ns
–
CC 0
5
4
4
–
–
–
–
–
–
–
–
–
–
–
CC 0
CC 0
SR 3
SR 0
SR 3
SR 2
ADV/BAA active/inactive after t22
BFCLKO rising edge2)
Data setup to BFCLKI rising
edge
t23
Data hold from BFCLKI rising t24
edge
WAIT setup (low or high) to
BFCLKI rising edge
t25
WAIT hold (low or high) from t26
BFCLKI rising edge
1) Not subject to production test, verified by design/characterization.
2) This parameter is valid for BFCON.EBSE0 = 1 (or BFCON.EBSE1 = 1). Note that t22 is increased by:
1/2 of the LMB bus clock period TCPU = 1/fCPU when BFCON.EBSE0 = 0 (or BFCON.EBSE1 = 0).
Data Sheet
123
V1.0, 2008-04
TC1796
Electrical Parameters
Address
Phase(s)
Command
Phase(s)
Burst
Burst
Recovery
Phase(s)
Next Addr.
Phase(s)
Phase(s)
Phase(s)
BFCLKI
1)
BFCLKO
t10
t10
Next
A[23:0]
ADV
Burst Start Address
Addr.
t22
t22
t22
t10
t10
t10
CS[3:0]
CSCOMB
t12
t12
t22
t24
RD
t22
BAA
t24
t23
t23
D[31:0]
(32-Bit)
Data (Addr+0)
Data (Addr+4)
D[15:0]
(16-Bit)
Data (Addr+0)
Data (Addr+2)
t26
t25
WAIT
1)
Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0:BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1:BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRD_4.vsd
Figure 40
EBU Burst Mode Read Timing
Data Sheet
124
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.11
EBU Arbitration Signal Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40°C to +125 °C; CL = 35 pF;
Table 31
EBU Arbitration Signal Timing Parameters1)
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Con
Min.
dition
Output delay from CLKOUT
rising edge
Data setup to CLKOUT
falling edge
Data hold from CLKOUT
falling edge
t27
t28
t29
CC –
–
–
–
3
–
–
ns
ns
ns
–
SR 8
SR 2
–
–
1) Not subject to production test, verified by design/characterization.
BFCLKO
t27
t27
HLDA Output
t27
t27
BREQ Output
BFCLKO
t28
t29
t28
t29
HOLD Input
HLDA Input
EBUArb_1
Figure 41
EBU Arbitration Signal Timing
Data Sheet
125
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.12
Peripheral Timings
Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.
4.3.12.1 Micro Link Interface (MLI) Timing
Table 32
MLI Timing Parameters (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note /
Test Con
dition
TCLK clock period1)2)
RCLK clock period
MLI outputs delay from
TCLK rising edge
t30
t31
t35
CC 23)
SR 1
CC 0
–
–
–
–
–
8
1 / fSYS
1 / fSYS
ns
–
–
–
MLI inputs setup to RCLK
falling edge
MLI inputs hold to RCLK
falling edge
t36
t37
SR 4
SR 4
CC 0
–
–
–
–
–
8
ns
ns
ns
–
–
–
RREADY output delay from t38
RCLK falling edge
1) TCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) TCLK high and low times can be minimum 1 × TMLI.
3) When fSYS = 75 MHz, t30 = 26,67ns
Data Sheet
126
V1.0, 2008-04
TC1796
Electrical Parameters
t30
0.9 VDDP
0.1 VDDP
TCLKx
t35
t35
TDATAx
TVALIDx
TREADYx
RCLKx
t31
t37
t36
RDATAx
RVALIDx
t38
t38
RREADYx
MLI_Tmg_2.vsd
Figure 42
MLI Interface Timing
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Data Sheet
127
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.12.2 Micro Second Channel (MSC) Interface Timing
Table 33
MSC Interface Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
FCLP clock period1)2)
SOP/ENx outputs delay
from FCLP rising edge
t40 CC 2 × TMSC
t45 CC -10
–
–
10
ns
ns
–
–
3)
SDI bit time
SDI rise time
SDI fall time
t46 CC 8 × TMSC
t48 SR
–
100
100
ns
ns
ns
–
–
–
t49 SR
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 × TMSC
.
3) TMSCmin = TSYS = 1/fSYS. When fSYS = 75 MHz, t40 = 26,67ns
t40
0.9 VDDP
0.1 VDDP
FCLP
t45
t45
SOP
EN
t48
t49
0.9 VDDP
0.1 VDDP
SDI
t46
t46
MSC_Tmg_1.vsd
Figure 43
MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
128
V1.0, 2008-04
TC1796
Electrical Parameters
4.3.12.3 Synchronous Serial Channel (SSC) Master Mode Timing
Table 34
SSC Master Mode Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
SCLK clock period1)2)
MTSR/SLSOx delay from
SCLK rising edge
t50 CC 2 × TSSC
t51 CC 0
–
–
–
8
ns
ns
–
–
3)
MRST setup to SCLK
falling edge
MRST hold from SCLK
falling edge
t52 SR 10
t53 SR 5
–
–
–
–
ns
ns
–
–
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 × TSSC
.
3) TSSCmin = TSYS = 1/fSYS. When fSYS = 75 MHz, t50 = 26,67ns
t50
SCLK1)2)
t51
t51
MTSR1)
t52
t53
Data
MRST1)
valid
t51
SLSOx2)
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_Tmg_1.vsd
Figure 44
SSC Master Mode Timing
Data Sheet
129
V1.0, 2008-04
TC1796
Package and Reliability
5
Package and Reliability
5.1
Package Parameters (P/PG-BGA-416-4)
Table 35
Thermal Characteristics of the Package
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condi
Min.
Max.
tion
Thermal resistance junction RTJCT CC –
8
K/W –
K/W –
case top1)
Thermal resistance junction RTJCB CC –
15
case bottom1)
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the
case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under
user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA
can be obtained from the upper four partial thermal resistances.
Data Sheet
130
V1.0, 2008-04
TC1796
Package and Reliability
5.2
Package Outline
25 x 1 = 25
A26
A1
AF1
1
+0.07
-0.13
416x
ø0.63
M
ø0.25
A B C
C
0.15
A
C
M
ø0.1
Index Marking
±0.2
±0.5
±0.2
20
24
27
Index Marking
(sharp edge)
B
GPA09537
Figure 45
P/PG-BGA-416-4, Plastic Low Profile Pitch Ball Grid Array
You can find our packages, sorts of packing and others in our Infineon Internet Web Site.
Data Sheet
131
V1.0, 2008-04
TC1796
Package and Reliability
5.3
Flash Memory Parameters
The data retention time of the TC1796’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Table 36
Parameter
Flash Parameters
Symbol
Values
Typ. Max.
Unit Note /
Test Condition
Min.
Program / Data Flash tRET CC 20
–
–
–
–
–
years Max. 1000
Retention Time,
erase/program
Physical Sector1)2)
cycles
Program / Data Flash tRETL CC 20
–
–
years Max. 100
Retention Time
erase/program
Logical Sector1)2)
cycles
Data Flash
Endurance
(128 KB)
NE CC 15 000
–
–
Max.dataretention
time 5 years
Data Flash
NE8 CC 120 000 –
Max.dataretention
time 5 years
Endurance,
EEPROM Emulation
(8 × 16 KB)
Programming Time
tPR CC –
tERP CC –
–
–
5
5
ms
s
–
per Page3)
Program Flash
Erase Time
per 256-KB Sector
f
CPU = 150 MHz
CPU = 150 MHz
Data Flash
tERD CC –
–
–
2.5
–
s
f
Erase Time
per 64-KB Sector
Wake-up time
tWU CC 4300 ×
1/fCPU
–
–
+ 40µs
1) Storage and inactive time included.
2) At average weighted junction temperature Tj = 100oC, or
the retention time at average weighted temperature of Tj = 110oC is minimum 10 years, or
the retention time at average weighted temperature of Tj = 150oC is minimum 0.7 years.
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
Data Sheet
132
V1.0, 2008-04
TC1796
Package and Reliability
5.4
Quality Declarations
Table 37
Parameter
Quality Parameters
Symbol
Values
Unit Note / Test Condition
Min. Typ. Max.
Operation
Lifetime1)2)
tOP
–
–
–
–
–
–
–
–
24000 hours at average weighted junction
temperature Tj = 127oC
66000 hours at average weighted junction
temperature Tj = 100oC
20
years at average weighted junction
temperature Tj = 85oC
ESD susceptibility VHBM
according to
Human Body
Model (HBM)
2000
V
Conforming to
EIA/JESD22-A114-B
ESD susceptibility VHBM1
–
–
–
–
500
500
V
V
–
of the LVDS pins
ESD susceptibility VCDM
Conforming to
JESD22-C101-C
according to
Charged Device
Model (CDM)
Moisture
MSL
–
–
3
–
Conforming to Jedec
J-STD-020C for 240°C
Sensitivity Level
1) This lifetime refers only to the time when the device is powered on.
2) One example of a detailed temperature profile is:
2000 hours at Tj = 150oC
16000 hours at Tj = 125oC
6000 hours at Tj = 110oC
This example is equivalent to the operation lifetime and average temperatures given in the table.
Data Sheet
133
V1.0, 2008-04
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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