SAK-TC275TP-64F200N DC [INFINEON]
SAK-TC275TP-64F200N DC 属于第一代 Aurix TC27xT 产品。其创新多核心架构基于多达三个独立 32 位 TriCore CPU，专为满足极高的安全标准，同时大幅提高性能而设计。TC27xT 系列产品配备 200 MHz TriCore、5V 或 3.3V 单电压供电和强大的通用定时器模块 (GTM)，旨在降低复杂度、实现同类产品中极其优秀的功耗并节省大量成本。;
| 型号： | SAK-TC275TP-64F200N DC |
| 厂家： | 
Infineon |
| 描述： | SAK-TC275TP-64F200N DC 属于第一代 Aurix TC27xT 产品。其创新多核心架构基于多达三个独立 32 位 TriCore CPU，专为满足极高的安全标准，同时大幅提高性能而设计。TC27xT 系列产品配备 200 MHz TriCore、5V 或 3.3V 单电压供电和强大的通用定时器模块 (GTM)，旨在降低复杂度、实现同类产品中极其优秀的功耗并节省大量成本。 |
| 文件： | 总279页 (文件大小：3805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Bit
Microcontroller
TC270 / TC275 / TC277
32-Bit Single-Chip Micocontroller
DC-Step
32-Bit Single-Chip Micocontroller
Data Sheet
V 1.0, 2017-01
Microcontrollers
Edition 2017-01
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TC270 / TC275 / TC277 DC-Step
Revision History
Page or Item
Subjects (major changes since previous revision)
V 1.0, 2017-01
The history is documented in the last chapter
Data Sheet
3
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
4
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
Package and Pinning Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TC275x Pin Definition and Functions: LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TC275x LQFP176 Package Variant Pin Configuration' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TC277x Pin Definition and Functions: BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
TC277xBGA292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
TC270x Bare Die Pad Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Pad Openings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.3 V only Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
High performance LVDS Pads (LVDSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Medium performance LVDS Pads (LVDSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
MSC Timing 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.14.1
3.15
3.15.1
3.15.2
3.15.3
3.15.4
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
Data Sheet
TOC-1
V 1.0, 2017-01
TC270 / TC275 / TC277 DC-Step
3.29
Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 256
ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
TC270 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
3.29.1
3.29.2
3.29.3
3.29.4
3.30
3.31
3.32
3.33
3.34
3.34.1
3.34.2
3.35
4
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
4.1
Changes from TC27xDB_v10 to 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Data Sheet
2
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Summary of Features
1
Summary of Features
The TC27x product family has the following features:
•
•
High Performance Microcontroller with three CPU cores
Two 32-bit super-scalar TriCore CPUs (TC1.6P), each having the following features:
–
–
–
–
–
–
–
–
–
–
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Multiply-accumulate unit able to sustain 2 MAC operations per cycle
Fully pipelined Floating point unit (FPU)
up to 200 MHz operation at full temperature range
up to 120 Kbyte Data Scratch-Pad RAM (DSPR)
up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
16 Kbyte Instruction Cache (ICACHE)
8 Kbyte Data Cache (DCACHE)
•
Power Efficient scalar TriCore CPU (TC1.6E), having the following features:
–
–
–
–
–
–
Binary code compatibility with TC1.6P
up to 200 MHz operation at full temperature range
up to 112 Kbyte Data Scratch-Pad RAM (DSPR)
up to 24 Kbyte Instruction Scratch-Pad RAM (PSPR)
8 Kbyte Instruction Cache (ICACHE)
0.125Kbyte Data Read Buffer (DRB)
•
•
Lockstepped shadow cores for one TC1.6P and for TC1.6E
Multiple on-chip memories
–
–
–
–
–
All embedded NVM and SRAM are ECC protected
up to 4 Mbyte Program Flash Memory (PFLASH)
up to 384 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
32 Kbyte Memory (LMU)
BootROM (BROM)
•
•
•
64-Channel DMA Controller with safe data transfer
Sophisticated interrupt system (ECC protected)
High performance on-chip bus structure
–
–
–
64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (SFI Bridge)
•
•
•
•
•
Optional Hardware Security Module (HSM) on some variants
Safety Management Unit (SMU) handling safety monitor alarms
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
Hardware I/O Monitor (IOM) for checking of digital I/O
Versatile On-chip Peripheral Units
–
Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
Data Sheet
3
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Summary of Features
–
–
–
–
Four Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
One MultiCAN+ Module with 4 CAN nodes and 256 free assignable message objects for high efficiency
data handling via FIFO buffering and gateway data transfer
–
–
–
10 Single Edge Nibble Transmission (SENT) channels for connection to sensors
One FlexRayTM module with 2 channels (E-Ray) supporting V2.1
One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management
–
–
–
–
–
–
One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
One General Purpose 12 Timer Unit (GPT120)
Three channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
Peripheral Sensor Interface with Serial PHY (PSI5-S)
Optional Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
Optional IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)
•
•
Versatile Successive Approximation ADC (VADC)
Cluster of 8 independent ADC kernels
–
– Input voltage range from 0 V to 5.5V (ADC supply)
Delta-Sigma ADC (DSADC)
–
Six channels
•
•
•
•
•
•
•
Digital programmable I/O ports
On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
Power Management System and on-chip regulators
Clock Generation Unit with System PLL and Flexray PLL
Embedded Voltage Regulator
Data Sheet
4
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply voltage
The package and the type of delivery.
For the available ordering codes for the TC270 / TC275 / TC277 please refer to the
"AURIX™ TC2x Data Sheet Addendum", which summarizes all available variants.
Table 1-1 Overview of TC27x Functions
Feature
TC1.6P / TC1.6E
CPU Core
Type
2 / 1 /
1 / 1
P Cores / Checker Cores /
E Cores / Checker Cores
200 MHz
yes
Max. Freq.
FPU
4 Mbyte
Program Flash
Data Flash
Cache
Size
384 Kbyte
Size
16 Kbyte / 8 Kbyte
8 Kbyte / -
Instruction (P / E)
Data (P / E)
120 Kbyte / 32 Kbyte 2)
SRAM
Size TC1.6P
(DSPR/PSPR)
112 Kbyte / 24 Kbyte 1) 2)
Size TC1.6E (DSPR/PSPR)
Size LMU
Channels
Channels
Converter
Channels
TIM
32 Kbyte
64
DMA
ADC
48 + 12
8
6
DSADC
GTM
4
3
TOM
5 / 4
1 / 1
1
ATOM / MCS
CMU / ICM
PSM
1
TBU
2
SPE
1 / 1
1 / 1
2
CMP / MON
BRC / DPLL
GPT12
Timer
2
CCU6
3
STM
Modules
1
FlexRay
Modules
2
Channels
Data Sheet
5
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Summary of Features
Table 1-1 Overview of TC27x Functions (cont’d)
Feature
4
CAN
Nodes
256
Message Objects
4
QSPI
Channels
4
ASCLIN
I2C
Interfaces
1
Interfaces
10
SENT
PSI5
Channels
3
Modules
1
PSI5-S
HSSL
Modules
1
Channels
2
MSC
Channels
1
Ethernet
ASIL
Channels
up to ASIL-D
Level
1
FCE
Modules
1
Safety support
SMU
1
IOM
1
Security
HSM
Yes
Embedded Voltage Regulator
Embedded Voltage Regulator
Embedded Voltage Regulator
Low Power Feature
Packages
DCDC from 5 V / 3.3 V to 1.3 V
Yes
LDO from 5 V / 3.3 V to 1.3 V
Yes
Yes
LDO from 5 V to 3.3 V
Standby RAM
Type
LF-BGA-292-6 / PG-LQFP-176-22
5 V CMOS / 3.3 V CMOS / LVDS
−40 … +125°C
I/O
Type
Tambient
Range
1) Address range starts at lowest address defined in the User’s Manual. For reference see the Memory Maps chapter of the
User’s Manual.
2) To ensure the processor cores are provided with a constant stream of instructions the Instruction Fetch Units will
speculatively fetch instructions from the up to 64 bytes ahead of the current PC.
If the current PC is within 64 bytes of the top of an instruction memory the Instruction Fetch Unit may attempt to
speculatively fetch instruction from beyond the physical range. This may then lead to error conditions and alarms being
triggered by the bus and memory systems.
It is therefore recommended that the upper 64 bytes of any memory be unused for instruction storage.
Data Sheet
6
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning Definitions
2
Package and Pinning Definitions
This chapter gives a pinning of the different packages of the TC270 / TC275 / TC277.
Data Sheet
7
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
2.1
TC275x Pin Definition and Functions: LQFP176
Figure 2-1 is showing the TC275x Logic Symbol for the package variant: QFP176.
P02.0
1
132
131
130
129
P20. 14
P20. 13
P20. 12
P20. 11
P02.1
P02.2
P02.3
P02.4
2
3
4
5
128
127
126
125
P20. 10
P20. 9
P20. 8
P20. 7
P02.5
P02.6
P02.7
P02.8
6
7
8
9
124
123
122
121
P20. 6
VDD
ESR0
PORST
V
DD/VDDSB
P00.0
P00.1
P00.2
10
11
12
13
120
119
118
117
ESR1
P20. 3
P20. 2 / TESTMODE
P20. 1
P20. 0
P00.3
P00.4
P00.5
P00.6
14
15
16
17
116
115
114
113
P00.7
P00.8
P00.9
18
19
20
21
TCK
TRST
P21. 7 / TDO
TMS
P00.10
112
111
110
109
P00.11
P00.12
VDD
VEXT
VAREF2
22
23
24
25
26
P21. 6 / TDI
P21. 5
P21. 4
TC27x
P21. 3
108
107
106
105
104
P21. 2
P21. 1
P21. 0
VAGND
2
27
28
29
30
AN47
AN46
AN45
VDDP
3
103
102
101
100
XTAL2
XTAL1
VSS
AN44
AN39
AN38
AN37
31
32
33
34
VDD
99
98
97
96
VEXT
AN36
AN35
AN33
AN32
35
36
37
38
P22. 3
P22. 2
P22. 1
95
94
93
92
P22. 0
P23. 5
P23. 4
P23. 3
P23. 2
AN29
AN28
AN27
AN26
39
40
41
42
91
90
89
AN25
AN24
43
44
P23. 1
P23. 0
Figure 2-1 TC275x Logic Symbol for the package variant LQFP176.
Data Sheet
8
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
2.1.1
TC275x LQFP176 Package Variant Pin Configuration'
Table 2-1 Port 00 Functions
Pin
11
Symbol
P00.0
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN9
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
HWOU
T
12
P00.1
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN10
ARX3E
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN5A
DS5NA
VADCG7.5
CIFD10
P00.1
ASCLIN3 input
CAN node 1 input
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 5 input A
DSADC negative analog input of channel 5, pin A
VADC analog input channel 5 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
–
Reserved
DSCOUT5
–
DSADC channel 5 output
Reserved
SPC0
SENT output
CC60
CCU61 output
Data Sheet
9
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
13
Symbol
P00.2
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN11
SENT1B
DSDIN5A
DS5PA
VADCG7.4
CIFD11
P00.2
SENT input
DSADC channel 5 input A
DSADC positive analog input of channel 5, pin A
VADC analog input channel 4 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT11
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
TXDCAN3
–
PSI5 output
CAN node 3 output
Reserved
COUT60
P00.3
CCU61 output
14
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN12
RXDCAN3A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG7.3
DSITR5F
CIFD12
P00.3
CAN node 3 input
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input A
VADC analog input channel 3 of group 7
DSADC channel 5 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
Data Sheet
10
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
15
Symbol
P00.4
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN13
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG7.2
CIFD13
P00.4
SENT input
DSADC channel 3 input A
DSADC input
VADC analog input channel 2 of group 7 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT13
PSISTX
–
PSI5-S output
Reserved
PSITX1
VADCG4BFL0
SPC3
PSI5 output
VADC output
SENT output
COUT61
P00.5
CCU61 output
16
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN14
PSIRX2A
SENT4B
CC62INB
CC62INA
DSCIN2A
VADCG7.1
CIFD14
P00.5
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 2 input A
VADC analog input channel 1 of group 7 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT14
DSCGPWMN
–
DSADC output
Reserved
DSCOUT2
VADCG4BFL1
SPC4
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
Data Sheet
11
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
17
Symbol
P00.6
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN15
SENT5B
DSDIN2A
VADCG7.0
DSITR4F
CIFD15
SENT input
DSADC channel 2 input A
VADC analog input channel 0 of group 7
DSADC channel 4 input F
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG4BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
P00.7
CCU61 output
18
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN16
SENT6B
CC60INC
CCPOS0A
T12HRB
T2INA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSCIN4A
DS4NA
DSADC channel 4 input A
DSADC negative analog input of channel 4, pin A
VADC analog input channel 5 of group 6
CIF input
VADCG6.5
CIFCLK
P00.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG4BFL3
DSCOUT4
VADCEMUX11
SPC6
VADC output
DSADC channel 4 output
VADC output
SENT output
CC60
CCU61 output
Data Sheet
12
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
19
Symbol
P00.8
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN17
SENT7B
CC61INC
CCPOS1A
T13HRB
T2EUDA
DSDIN4A
DS4PA
VADCG6.4
CIFVSNC
P00.8
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSADC channel 4 input A
DSADC channel 4 input A
VADC analog input channel 4 of group 6
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
SPC7
VADC output
SENT output
CC61
CCU61 output
Data Sheet
13
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
20
Symbol
P00.9
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN18
SENT8B
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
DSCIN1A
VADCG6.3
DSITR3F
CIFHSNC
P00.9
SENT input
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
DSADC channel 1 input A
VADC analog input channel 3 of group 6
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
DSCOUT1
–
QSPI3 output
ASCLIN3 output
DSADC channel 1 output
Reserved
SPC8
SENT output
CC62
CCU61 output
21
P00.10
TIN19
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT9B
DSDIN1A
VADCG6.2
P00.10
TOUT19
–
SENT input
DSADC channel 1 input A
VADC analog input channel 2 of group 6 (MD)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
SPC9
SENT output
COUT63
CCU61 output
Data Sheet
14
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
22
Symbol
P00.11
TIN20
CTRAPA
T12HRE
DSCIN0A
VADCG6.1
P00.11
TOUT20
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
CCU60 input
CCU61 input
DSADC channel 0 input A
VADC analog input channel 1 of group 6 (MD)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
DSCOUT0
–
DSADC channel 0 output
Reserved
–
Reserved
–
Reserved
23
P00.12
TIN21
ACTS3A
DSDIN0A
VADCG6.0
P00.12
TOUT21
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN3 input
DSADC channel 0 input A
VADC analog input channel 0 of group 6
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
Data Sheet
15
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-2 Port 02 Functions
Pin
1
Symbol
P02.0
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN0
ARX2G
REQ6
ASCLIN2 input
SCU input
CC60INA
CC60INB
CIFD0
P02.0
CCU60 input
CCU61 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY output
SLSO31
DSCGPWMN
TXDCAN0
TXDA
CC60
CCU60 output
2
P02.1
LP / PU1 General-purpose input
/ VEXT
TIN1
GTM input
REQ14
ARX2B
RXDCAN0A
RXDA2
CIFD1
P02.1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT1
–
Reserved
SLSO32
DSCGPWMP
–
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
16
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
3
Symbol
P02.2
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN2
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
PSI5 output
SLSO33
PSITX0
TXDCAN2
TXDB
CAN node 2 output
ERAY output
CC61
CCU60 output
General-purpose input
GTM input
4
P02.3
LP /
PU1 /
VEXT
TIN3
ARX1G
RXDCAN2B
RXDB2
PSIRX0B
DSCIN5B
SDI11
ASCLIN1 input
CAN node 2 input
ERAY input
PSI5 input
DSADC channel 5 input B
MSC1 input
CIFD3
CIF input
P02.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
DSCOUT5
–
ASCLIN2 output
QSPI3 output
DSADC channel 5 output
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
17
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
5
Symbol
P02.4
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN4
SLSI3A
ECTT1
QSPI3 input
TTCAN input
RXDCAN0D
CC62INA
CC62INB
DSDIN5B
SDA0A
CIFD4
CAN node 0 input
CCU60 input
CCU61 input
DSADC channel 5 input B
I2C0 input
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXENA
CC62
ERAY output
CCU60 output
General-purpose input
GTM input
6
P02.5
MP+ /
PU1 /
VEXT
TIN5
MRST3A
ECTT2
QSPI3 input
TTCAN input
PSIRX1B
PSISRXB
SENT3C
DSCIN4B
SCL0A
PSI5 input
PSI5-S input
SENT input
DSADC channel 4 input B
I2C0 input
CIFD5
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
DSCOUT4
SCL0
CAN node 0 output
QSPI3 output
DSADC channel 4 output
I2C0 output
TXENB
COUT62
ERAY output
CCU60 output
Data Sheet
18
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
7
Symbol
P02.6
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN6
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
DSDIN4B
DSITR5E
P02.6
DSADC channel 4 input B
DSADC channel 5 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
Data Sheet
19
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
8
Symbol
P02.7
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN7
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
DSITR4E
P02.7
DSADC channel 3 input B
DSADC channel 4 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSCOUT3
VADCEMUX01
SPC1
DSADC channel 3 output
VADC output
SENT output
CC61
CCU60 output
Data Sheet
20
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
9
Symbol
P02.8
Ctrl
Type
Function
I
LP / PU1 General-purpose input
/
TIN8
GTM input
VEXT
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
CIFD8
DSDIN3B
DSITR3E
P02.8
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
Table 2-3 Port 10 Functions
Pin
168
Symbol
Ctrl
Type
Function
P10.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN102
T6EUDB
GPT120 input
General-purpose output
GTM output
P10.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT102
–
Reserved
SLSO110
QSPI1 output
Reserved
–
VADCG6BFL0
VADC output
Reserved
–
–
Reserved
Data Sheet
21
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-3 Port 10 Functions (cont’d)
Pin
169
Symbol
P10.1
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL1
END03
–
170
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
QSPI1 input
GPT120 input
SCU input
REQ2
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL2
END02
–
Data Sheet
22
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-3 Port 10 Functions (cont’d)
Pin
171
Symbol
P10.3
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG6BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
172
P10.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN106
MTSR1C
CCPOS0C
T3INB
QSPI1 input
CCU60 input
GPT120 input
General-purpose output
GTM output
P10.4
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT106
–
Reserved
SLSO18
MTSR1
EN00
QSPI1 output
QSPI1 output
MSC0 output
MSC0 output
Reserved
END02
–
173
P10.5
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
INJ01
SCU input
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
QSPI1 output
GPT120 output
ASCLIN2 output
Reserved
SLSO38
SLSO19
T6OUT
ASLSO2
-
Data Sheet
23
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-3 Port 10 Functions (cont’d)
Pin
174
Symbol
P10.6
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
MTSR3B
HWCFG5
P10.6
ASCLIN2 input
QSPI3 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
T3OUT
-
ASCLIN2 output
QSPI3 output
GPT120 output
Reserved
MRST1
VADCG7BFL0
P10.7
QSPI1 output
VADC output
General-purpose input
GTM input
175
LP /
PU1 /
VEXT
TIN109
ACTS2A
MRST3B
REQ4
ASCLIN2 input
QSPI3 input
SCU input
CCPOS1C
T3EUDB
P10.7
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT109
–
Reserved
MRST3
VADCG7BFL1
–
QSPI3 output
VADC output
Reserved
–
Reserved
–
Reserved
Data Sheet
24
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-3 Port 10 Functions (cont’d)
Pin
176
Symbol
P10.8
TIN110
SCLK3B
REQ5
CCPOS2C
T4INB
P10.8
TOUT110
ARTS2
SCLK3
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
SCU input
CCU60 input
GPT120 input
General-purpose output
GTM output
ASCLIN2 output
QSPI3 output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
–
Reserved
–
Reserved
–
Reserved
Table 2-4 Port 11 Functions
Pin
160
Symbol
P11.2
Ctrl
Type
Function
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
TIN95
P11.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT95
END03
SLSO05
SLSO15
EN01
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
CCU60 output
Data Sheet
25
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-4 Port 11 Functions (cont’d)
Pin
161
Symbol
P11.3
Ctrl
Type
Function
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
TIN96
MRST1B
SDI03
P11.3
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT96
–
Reserved
MRST1
TXDA
QSPI1 output
ERAY output
Reserved
–
ETHTXD0
COUT62
P11.6
ETH output
CCU60 output
General-purpose input
GTM input
162
MPR /
PU1 /
VFLEX
TIN97
SCLK1B
P11.6
QSPI1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT97
TXENB
SCLK1
TXENA
FCLP0
ETHTXEN
COUT61
P11.9
ERAY output
QSPI1 output
ERAY output
MSC0 output
ETH output
CCU60 output
General-purpose input
GTM input
163
MP+ /
PU1 /
VFLEX
TIN98
MTSR1B
RXDA1
ETHRXD1
P11.9
QSPI1 input
ERAY input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT98
–
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
MSC0 output
Reserved
–
COUT60
CCU60 output
Data Sheet
26
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-4 Port 11 Functions (cont’d)
Pin
165
Symbol
P11.10
TIN99
Ctrl
Type
Function
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXDB1
ETHRXD0
SDI00
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY input
ETH input
MSC0 input
P11.10
TOUT99
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
General-purpose input
GTM input
166
P11.11
TIN100
ETHCRSDVA
ETHRXDVA
ETHCRSB
P11.11
TOUT100
END02
SLSO04
SLSO14
EN00
MP+ /
PU1 /
VFLEX
ETH input
ETH input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY output
CCU60 output
TXENB
CC61
Data Sheet
27
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-4 Port 11 Functions (cont’d)
Pin
167
Symbol
Ctrl
Type
Function
P11.12
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
TIN101
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
ETHRXCLKA
ETH input
(Not for productive purposes)
P11.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT101
ATX1
ASCLIN1 output
GTM output
GTMCLK2
TXDB
ERAY output
TXDCAN3
EXTCLK1
CC60
CAN node 3 output
SCU output
CCU60 output
Table 2-5 Port 13 Functions
Pin
156
Symbol
P13.0
TIN91
P13.0
TOUT91
END03
SCLK2N
EN01
FCLN0
FCLND0
–
Ctrl
Type
Function
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC0 output
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
MSC0 output (LVDS)
Reserved
157
P13.1
TIN92
SCL0B
P13.1
TOUT92
–
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
–
MSC0 output (LVDS)
I2C0 output
Reserved
Data Sheet
28
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-5 Port 13 Functions (cont’d)
Pin
158
Symbol
P13.2
TIN93
CAPINA
SDA0B
P13.2
TOUT93
–
Ctrl
Type
Function
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MTSR2N
FCLP0
SON0
SDA0
SOND0
P13.3
TIN94
P13.3
TOUT94
–
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
MSC0 output (LVDS)
General-purpose input
GTM input
159
LVDSM_P /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR2P
–
QSPI2 output (LVDS)
Reserved
SOP0
–
MSC0 output (LVDS)
Reserved
–
Reserved
Table 2-6 Port 14 Functions
Pin
142
Symbol
P14.0
Ctrl
Type
Function
General-purpose input
I
MP+ /
PU1 /
VEXT
TIN80
GTM input
P14.0
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
TXDA
O3
O4
O5
ERAY output
ERAY output
TXDB
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function.
ASCLK0
COUT62
O6
O7
ASCLIN0 output
CCU60 output
Data Sheet
29
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-6 Port 14 Functions (cont’d)
Pin
143
Symbol
P14.1
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN81
REQ15
ARX0A
SCU input
ASCLIN0 input
Recommended as Boot loader pin.
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function.
RXDA3
RXDB3
EVRWUPA
P14.1
TOUT81
ATX0
–
ERAY input
ERAY input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
P14.2
TIN82
CCU60 output
General-purpose input
GTM input
144
LP /
PU1 /
VEXT
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
SLSO21
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
Data Sheet
30
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-6 Port 14 Functions (cont’d)
Pin
145
Symbol
P14.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN83
ARX2A
REQ10
HWCFG3_BMI
SDI02
ASCLIN2 input
SCU input
SCU input
MSC0 input
P14.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT83
ATX2
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
146
P14.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN84
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT84
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
31
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-6 Port 14 Functions (cont’d)
Pin
147
Symbol
P14.5
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN85
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT85
–
–
Reserved
–
Reserved
–
Reserved
TXDB
–
ERAY output
Reserved
148
P14.6
TIN86
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT86
–
Reserved
SLSO22
QSPI2 output
Reserved
–
–
Reserved
TXENB
–
ERAY output
Reserved
149
P14.7
TIN87
RXDB0
P14.7
TOUT87
ARTS0
SLSO24
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ERAY input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
32
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-6 Port 14 Functions (cont’d)
Pin
150
Symbol
P14.8
TIN88
ARX1D
RXDCAN2D
RXDA0
P14.8
TOUT88
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
CAN node 2 input
ERAY input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
151
P14.9
TIN89
ACTS0A
P14.9
TOUT89
END03
EN01
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
MSC0 output
MSC0 output
Reserved
TXENB
TXENA
–
ERAY output
ERAY output
Reserved
152
P14.10
TIN90
P14.10
TOUT90
END02
EN00
ATX1
TXDCAN2
TXDA
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
MSC0 output
ASCLIN1 output
CAN node 2 output
ERAY output
Reserved
Data Sheet
33
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-7 Port 15 Functions
Pin
133
Symbol
P15.0
TIN71
P15.0
TOUT71
ATX1
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
Reserved
SLSO013
–
TXDCAN2
ASCLK1
–
CAN node 2 output
ASCLIN1 output
Reserved
134
P15.1
TIN72
REQ16
ARX1A
RXDCAN2A
SLSI2B
EVRWUPB
P15.1
TOUT72
ATX1
LP /
PU1 /
VEXT
General-purpose input
GTM input
SCU input
ASCLIN1 input
CAN node 2 input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
Reserved
–
Reserved
–
Reserved
135
P15.2
TIN73
SLSI2A
MRST2E
P15.2
TOUT73
ATX0
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
Data Sheet
34
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-7 Port 15 Functions (cont’d)
Pin
136
Symbol
P15.3
TIN74
ARX0B
SCLK2A
RXDCAN1A
P15.3
TOUT74
ATX0
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
QSPI2 input
CAN node 1 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
137
P15.4
TIN75
MRST2A
REQ0
SCL0C
P15.4
TOUT75
ATX1
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
SCL0
I2C0 output
CC62
CCU60 output
Data Sheet
35
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-7 Port 15 Functions (cont’d)
Pin
138
Symbol
P15.5
TIN76
ARX1B
MTSR2A
REQ13
SDA0C
P15.5
TOUT76
ATX1
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
General-purpose input
GTM input
139
P15.6
TIN77
MTSR2B
P15.6
TOUT77
ATX3
MP /
PU1 /
VEXT
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
MTSR2
–
SCLK2
ASCLK3
CC60
QSPI2 output
ASCLIN3 output
CCU60 output
General-purpose input
GTM input
140
P15.7
TIN78
ARX3A
MRST2B
P15.7
TOUT78
ATX3
MP /
PU1 /
VEXT
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
36
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-7 Port 15 Functions (cont’d)
Pin
141
Symbol
P15.8
TIN79
SCLK2B
REQ1
P15.8
TOUT79
–
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
ASCLIN3 output
CCU60 output
Table 2-8 Port 20 Functions
Pin
116
Symbol
P20.0
TIN59
RXDCAN3C
T6EUDA
REQ9
SYSCLK
TGI0
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
CAN node 3 input
GPT120 input
SCU input
HSCT input
OCDS input
P20.0
TOUT59
ATX3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
Data Sheet
37
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
117
Symbol
Ctrl
Type
Function
P20.1
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN60
TGI1
OCDS input
General-purpose output
GTM output
Reserved
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
TOUT60
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO1
HWOU
T
OCDS; ENx
118
P20.2
I
LP /
General-purpose input
PU /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
OCDS input
P20.2
O0
O1
O2
O3
O4
O5
O6
O7
I
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
General-purpose input
GTM input
–
–
–
–
–
–
–
119
P20.3
TIN61
T6INA
ARX3C
P20.3
TOUT61
ATX3
SLSO09
SLSO29
TXDCAN3
–
LP /
PU1 /
VEXT
GPT120 input
ASCLIN3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
QSPI0 output
QSPI2 output
CAN node 3 output
Reserved
–
Reserved
Data Sheet
38
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
124
Symbol
P20.6
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN62
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT62
ARTS1
SLSO08
SLSO28
–
ASCLIN1 output
QSPI0 output
QSPI2 output
Reserved
WDT2LCK
–
SCU output
Reserved
125
P20.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN63
ACTS1A
RXDCAN0B
P20.7
ASCLIN1 input
CAN node 0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT63
–
Reserved
–
Reserved
–
Reserved
–
Reserved
WDT1LCK
COUT63
P20.8
SCU output
CCU61 output
General-purpose input
GTM input
126
MP /
PU1 /
VEXT
TIN64
P20.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT64
ASLSO1
SLSO00
SLSO10
TXDCAN0
WDT0LCK
CC60
ASCLIN1 output
QSPI0 output
QSPI1 output
CAN node 0 output
SCU output
CCU61 output
Data Sheet
39
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
127
Symbol
P20.9
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN65
ARX1C
RXDCAN3E
REQ11
SLSI0B
P20.9
ASCLIN1 input
CAN node 3 input
SCU input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT65
–
Reserved
SLSO01
SLSO11
–
QSPI0 output
QSPI1 output
Reserved
WDTSLCK
CC61
SCU output
CCU61 output
General-purpose input
GTM input
128
P20.10
TIN66
P20.10
TOUT66
ATX1
MP /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
CAN node 3 output
ASCLIN1 output
CCU61 output
General-purpose input
GTM input
SLSO06
SLSO27
TXDCAN3
ASCLK1
CC62
129
P20.11
TIN67
SCLK0A
P20.11
TOUT67
–
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
COUT60
CCU61 output
Data Sheet
40
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
130
Symbol
P20.12
TIN68
MRST0A
P20.12
TOUT68
–
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST0
MTSR0
–
QSPI0 output
QSPI0 output
Reserved
–
Reserved
COUT61
P20.13
TIN69
SLSI0A
P20.13
TOUT69
–
CCU61 output
General-purpose input
GTM input
131
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO02
SLSO12
SCLK0
–
QSPI0 output
QSPI1 output
QSPI0 output
Reserved
COUT62
P20.14
TIN70
MTSR0A
P20.14
TOUT70
–
CCU61 output
General-purpose input
GTM input
132
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
41
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-9 Port 21 Functions
Pin
105
Symbol
Ctrl
Type
Function
P21.0
I
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
TIN51
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT51
–
–
Reserved
–
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
HSM1
HWOU
T
HSM output 1
106
P21.1
I
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
TIN52
ETHMDIOB
ETH input
(Not for production purposes)
P21.1
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM output
Reserved
TOUT52
–
–
Reserved
–
Reserved
–
Reserved
ETHMDIO
ETH output
(Not for production purposes)
–
O7
Reserved
HSM2
HWOU
T
HSM output 2
Data Sheet
42
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-9 Port 21 Functions (cont’d)
Pin
107
Symbol
P21.2
TIN53
MRST2CN
MRST3FN
ARX3GN
EMGSTOPB
RXDN
P21.2
TOUT53
ASLSO3
–
Ctrl
Type
Function
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
QSPI2 input (LVDS)
QSPI3 input (LVDS)
ASCLIN3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
–
Reserved
108
P21.3
TIN54
MRST2CP
MRST3FP
ARX3GP
RXDP
P21.3
TOUT54
–
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
QSPI2 input (LVDS)
QSPI3 input (LVDS)
ASCLIN3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDIOD
HWOU
T
ETH input/output
Data Sheet
43
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-9 Port 21 Functions (cont’d)
Pin
109
Symbol
P21.4
TIN55
P21.4
TOUT55
–
Ctrl
Type
Function
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDN
P21.5
TIN56
P21.5
TOUT56
ASCLK3
–
HSCT output (LVDS)
General-purpose input
GTM input
110
LVDSH_P/
PU1 /
VDDP3
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDP
P21.6
TIN57
ARX3F
TGI2
TDI
HSCT output (LVDS)
General-purpose input
GTM input
1111)
A2 /
PU /
VDDP3
ASCLIN3 input
OCDS input
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
TOUT57
ASLSO3
–
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
Reserved
–
Reserved
SYSCLK
–
HSCT output
Reserved
T3OUT
TGO2
GPT120 output
OCDS; ENx
HWOU
T
Data Sheet
44
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-9 Port 21 Functions (cont’d)
Pin
113
Symbol
P21.7
TIN58
DAP2
TGI3
Ctrl
Type
Function
I
A2 /
PU /
VDDP3
General-purpose input
GTM input
OCDS input
OCDS input
TDO
OCDS (JTAG) input
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ. In DAP mode this pin
is used as P21.7 and controlled by the related
port control logic
ETHRXERB
T5INA
P21.7
TOUT58
ATX3
ASCLK3
–
ETH input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
T6OUT
TGO3
TDO
GPT120 output
OCDS; ENx
HWOU
T
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ. In DAP mode this pin
is used as P21.7 and controlled by the related
port control logic
1) For an Emulation Device in a non Fusion Quad package this pin is used as VDDPSB (3.3V)
Data Sheet
45
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-10 Port 22 Functions
Pin
95
Symbol
P22.0
Ctrl
Type
Function
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN47
MTSR3E
P22.0
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT47
ATX3N
MTSR3
SCLK3N
FCLN1
FCLND1
–
ASCLIN3 output (LVDS)
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
96
P22.1
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
TIN48
MRST3E
P22.1
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT48
ATX3P
MRST3
SCLK3P
FCLP1
–
ASCLIN3 output (LVDS)
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
97
P22.2
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN49
SLSI3D
P22.2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT49
–
Reserved
SLSO312
MTSR3N
SON1
SOND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
46
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-10 Port 22 Functions (cont’d)
Pin
98
Symbol
P22.3
TIN50
SCLK3E
P22.3
TOUT50
–
Ctrl
Type
Function
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK3
MTSR3P
SOP1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
Table 2-11 Port 23 Functions
Pin
89
Symbol
P23.0
TIN41
P23.0
TOUT41
–
Ctrl
Type
Function
General-purpose input
I
LP /
PU1 /
VEXT
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
90
P23.1
TIN42
SDI10
P23.1
TOUT42
ARTS1
SLSO313
GTMCLK0
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
MSC1 input
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
GTM output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
EXTCLK0
–
SCU output
Reserved
Data Sheet
47
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-11 Port 23 Functions (cont’d)
Pin
91
Symbol
Ctrl
Type
Function
P23.2
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN43
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT43
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
92
P23.3
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN44
INJ10
MSC1 input
General-purpose output
GTM output
Reserved
P23.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT44
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
93
P23.4
TIN45
P23.4
TOUT45
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO35
END12
EN10
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Data Sheet
48
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-11 Port 23 Functions (cont’d)
Pin
94
Symbol
P23.5
TIN46
P23.5
TOUT46
–
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO34
END13
EN11
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Table 2-12 Port 32 Functions
Pin
84
Symbol
P32.0
Ctrl
Type
LP /
Function
I
General-purpose input
EVR13 SMPS
-> PD,
GPIO - > PU
/
TIN36
GTM input
PMU input
FDEST
VGATE1N
SMPS mode: analog output. External Pass Device
gate control for EVR13
VEXT
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT36
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
86
P32.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN38
ARX3D
ASCLIN3 input
CAN node 3 input
General-purpose output
GTM output
ASCLIN3 output
Reserved
RXDCAN3B
P32.2
O0
O1
O2
O3
O4
O5
O6
O7
TOUT38
ATX3
–
–
Reserved
–
Reserved
DCDCSYNC
–
SCU output
Reserved
Data Sheet
49
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-12 Port 32 Functions (cont’d)
Pin
87
Symbol
P32.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN39
P32.3
TOUT39
ATX3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
ASCLK3
TXDCAN3
–
ASCLIN3 output
CAN node 3 output
Reserved
–
Reserved
88
P32.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN40
ACTS1B
SDI12
P32.4
TOUT40
–
ASCLIN1 input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
END12
GTMCLK1
EN10
MSC1 output
GTM output
MSC1 output
SCU output
EXTCLK1
COUT63
CCU60 output
Table 2-13 Port 33 Functions
Pin
70
Symbol
Ctrl
Type
Function
P33.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN22
DSITR0E
DSADC channel 0 input E
General-purpose output
GTM output
P33.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT22
–
Reserved
–
Reserved
–
Reserved
–
Reserved
VADCG2BFL0
–
VADC output
Reserved
Data Sheet
50
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
71
Symbol
P33.1
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN23
PSIRX0C
SENT9C
DSCIN2B
DSITR1E
P33.1
PSI5 input
SENT input
DSADC channel 2 input B
DSADC channel 1 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT23
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT2
VADCEMUX02
VADCG2BFL1
–
DSADC channel 2 output
VADC output
VADC output
Reserved
72
P33.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN24
SENT8C
DSDIN2B
DSITR2E
P33.2
SENT input
DSADC channel 2 input B
DSADC channel 2 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT24
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
VADCEMUX01
VADCG2BFL2
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
51
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
73
Symbol
P33.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN25
PSIRX1C
SENT7C
DSCIN1B
P33.3
PSI5 input
SENT input
DSADC channel 1 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT25
–
Reserved
–
Reserved
DSCOUT1
VADCEMUX00
VADCG2BFL3
–
DSADC channel 1 output
VADC output
VADC output
Reserved
74
P33.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN26
SENT6C
CTRAPC
DSDIN1B
DSITR0F
P33.4
SENT input
CCU61 input
DSADC channel 1 input B
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
–
ASCLIN2 output
Reserved
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
52
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
75
Symbol
P33.5
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN27
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
DSITR1F
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 1 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
76
P33.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN28
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
-
ASCLIN2 output
Reserved
PSITX2
PSI5 output
VADCEMUX10
VADCG1BFL0
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
53
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
77
Symbol
P33.7
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN29
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO37
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
VADCG1BFL1
–
VADC output
Reserved
78
P33.8
MP /
HighZ/
VEXT
General-purpose input
GTM input
TIN30
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI3 output
Reserved
SLSO32
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
79
P33.9
TIN31
P33.9
TOUT31
ATX2
SLSO31
ASCLK2
–
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI3 output
ASCLIN2 output
Reserved
–
Reserved
CC62
CCU61 output
Data Sheet
54
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
80
Symbol
P33.10
TIN32
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3C
P33.10
TOUT32
SLSO16
SLSO311
ASLSO1
PSISCLK
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
QSPI1 output
QSPI3 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
P33.11
TIN33
CCU61 output
General-purpose input
GTM input
81
MP /
PU1 /
VEXT
SCLK3D
P33.11
TOUT33
ASCLK1
SCLK3
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC output
CCU61 output
General-purpose input
GTM input
82
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR3D
P33.12
TOUT34
ATX1
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
ASCLIN1 output
Reserved
MTSR3
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
55
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
83
Symbol
P33.13
TIN35
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1F
MRST3D
DSSGNB
INJ11
ASCLIN1 input
QSPI3 input
DSADC input
MSC1 input
P33.13
TOUT35
ATX1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
QSPI2 output
Reserved
MRST3
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
Table 2-14 Port 40 Functions
Pin
44
Symbol
P40.0
Ctrl
Type
Function
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 0 of group 3
VADCG3.0
DS2PB
DSADC: positive analog input channe of DSADC 2, pin
B
CCPOS0D
SENT0A
P40.1
CCU60 input
SENT input
43
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 1 of group 3 (MD)
DSADC: negative analog of input channel 2, pin B
CCU60 input
VADCG3.1
DS2NB
CCPOS1B
SENT1A
P40.2
SENT input
42
41
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 2 of group 3 (MD)
CCU60 input
VADCG3.2
CCPOS1D
SENT2A
P40.3
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 3 of group 3
CCU60 input
VADCG3.3
CCPOS2B
SENT3A
SENT input
Data Sheet
56
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-14 Port 40 Functions (cont’d)
Pin
38
Symbol
P40.4
Ctrl
Type
Function
I
S /
General-purpose input
HighZ /
VDDM
VADCG4.0
CCPOS2D
SENT4A
P40.5
VADC analog input channel 0 of group 4
CCU60 input
SENT input
37
35
I
I
S /
HighZ /
VDDM
General-purpose input
VADCG4.1
CCPOS0D
SENT5A
P40.6
VADC analog input channel 1 of group 4 (MD)
CCU61 input
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG4.4
DS3PA
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
CCU61 input
CCPOS1B
SENT6A
P40.7
SENT input
34
33
32
I
I
I
S /
HighZ /
VDDM
General-purpose input
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input of channel 3, pin A
CCU61 input
CCPOS1D
SENT7A
P40.8
SENT input
S /
HighZ /
VDDM
General-purpose input
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel 3, pin B
CCU61 input
CCPOS2B
SENT8A
P40.9
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input of channel 3, pin B
CCU61 input
CCPOS2D
SENT9A
SENT input
Table 2-15 Analog Inputs
Pin
67
Symbol
AN0
Ctrl
Type
Function
I
D /
Analog input 0
HighZ /
VDDM
VADCG0.0
DS1PA
AN1
VADC analog input channel 0 of group 0
DSADC: positive analog of input channel 1, pin A
Analog input 1
66
I
D /
HighZ /
VDDM
VADCG0.1
DS1NA
VADC analog input channel 1 of group 0 (MD)
DSADC: negative analog input of channel 1, pin A
Data Sheet
57
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-15 Analog Inputs (cont’d)
Pin
65
Symbol
AN2
Ctrl
Type
Function
I
D /
Analog input 2
HighZ /
VDDM
VADCG0.2
DS0PA
AN3
VADC analog input channel 2 of group 0 (MD)
DSADC: positive analog input of channel 0, pin A
Analog input 3
64
I
D /
HighZ /
VDDM
VADCG0.3
DS0NA
AN4
VADC analog input channel 3 of group 0
DSADC: negative analog input of channel 0, pin A
Analog input 4
63
62
61
60
I
I
I
I
D /
HighZ /
VDDM
VADCG0.4
VADC analog input channel 4 of group 0
AN5
D /
HighZ /
VDDM
Analog input 5
VADCG0.5
VADC analog input channel 5 of group 0
AN6
D /
HighZ /
VDDM
Analog input 6
VADCG0.6
VADC analog input channel 6 of group 0
AN7
D /
Analog input 7
HighZ /
VDDM
VADCG0.7
VADC analog input channel 7 of group 0 (with pull
down diagnostics)
59
58
57
AN8
I
I
I
D /
HighZ /
VDDM
Analog input 8
VADCG1.0
VADC analog input channel 0 of group 1
AN10
D /
HighZ /
VDDM
Analog input 10
VADCG1.2
VADC analog input channel 2 of group 1 (MD)
AN11
D /
Analog input 11
HighZ /
VDDM
VADCG1.3
VADC analog input channel 3 of group 1 (with pull
down diagnostics)
56
55
50
49
48
AN12
I
I
I
I
I
D /
HighZ /
VDDM
Analog input 12
VADCG1.4
VADC analog input channel 4 of group 1
AN13
D /
HighZ /
VDDM
Analog input 13
VADCG1.5
VADC analog input channel 5 of group 1
AN16
D /
HighZ /
VDDM
Analog input 16
VADCG2.0
VADC analog input channel 0 of group 2
AN17
D /
HighZ /
VDDM
Analog input 17
VADCG2.1
VADC analog input channel 1 of group 2 (MD)
AN18
D /
Analog input 18
HighZ /
VDDM
VADCG2.2
VADC analog input channel 2 of group 2 (MD)
Data Sheet
58
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-15 Analog Inputs (cont’d)
Pin
47
Symbol
AN19
Ctrl
Type
Function
I
D /
Analog input 19
HighZ /
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
46
45
AN20
I
I
I
I
I
I
D /
HighZ /
VDDM
Analog input 20
VADCG2.4
DS2PA
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 2, pin A
Analog input 21
AN21
D /
HighZ /
VDDM
VADCG2.5
DS2NA
VADC analog input channel 5 of group 2
DSADC: negative analog input of channel
of DSADC 2, pin A
44
43
AN24
I
S /
HighZ /
VDDM
Analog input 24
VADCG3.0
DS2PB
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
SENT input channel 0, pin A
SENT0A
AN25
I
S /
Analog input 24
HighZ /
VDDM
VADCG3.1
DS2NB
VADC analog input channel 1 of group 3 (MD)
DSADC: negative analog input of channel 2, pin B
SENT input channel 1, pin A
SENT1A
AN26
42
41
I
I
S /
HighZ /
VDDM
Analog input 26
VADCG3.2
SENT2A
AN27
VADC analog input channel 2 of group 3 (MD)
SENT input channel 2, pin A
S /
Analog input 27
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
SENT3A
AN28
SENT input channel 3, pin A
Analog input 28
40
39
38
I
I
I
D /
HighZ /
VDDM
VADCG3.4
VADC analog input channel 4 of group 3
AN29
D /
HighZ /
VDDM
Analog input 29
VADCG3.5
VADC analog input channel 5 of group 3
AN32
S /
Analog input 32
HighZ /
VDDM
VADCG4.0
SENT4A
AN33
VADC analog input channel 0 of group 4
SENT input channel 4, pin A
Analog input 33
37
36
I
I
S /
HighZ /
VDDM
VADCG4.1
SENT5A
AN35
VADC analog input channel 1 of group 4 (MD)
SENT input channel 5, pin A
Analog input 35
D /
HighZ /
VDDM
VADCG4.3
VADC analog input channel 3 of group 4 (with pull
down diagnostics)
Data Sheet
59
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-15 Analog Inputs (cont’d)
Pin
35
Symbol
AN36
Ctrl
Type
Function
I
S /
Analog input 34
HighZ /
VDDM
VADCG4.4
DS3PA
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel
of DSADC 3, pin A
SENT6A
AN37
SENT input channel 6, pin A
Analog input 37
34
33
32
I
I
I
S /
HighZ /
VDDM
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input of channel
of DSADC 3, pin A
SENT7A
AN38
SENT input channel 7, pin A
Analog input 38
S /
HighZ /
VDDM
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel
of DSADC 3, pin B
SENT8A
AN39
SENT input channel 8, pin A
Analog input 39
S /
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input of channel
of DSADC 3, pin B
SENT9A
AN44
SENT input channel 9, pin A
Analog input 44
31
30
29
28
I
I
I
I
D /
HighZ /
VDDM
VADCG5.4
DS3PC
VADC analog input channel 4 of group 5
DSADC: positive analog input of channel
of DSADC 3, pin C
AN45
D /
HighZ /
VDDM
Analog input 45
VADCG5.5
DS3NC
VADC analog input channel 5 of group 5
DSADC: negative analog input of channel
of DSADC 3, pin C
AN46
D /
HighZ /
VDDM
Analog input 46
VADCG5.6
DS3PD
VADC analog input channel 6 of group 5
DSADC: positive analog input of channel
of DSADC 3, pin D
AN47
D /
Analog input 47
HighZ /
VDDM
VADCG5.7
DS3ND
VADC analog input channel 7 of group 5
DSADC: negative analog input of channel
of DSADC 3, pin D
Data Sheet
60
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-16 System I/O
Pin
121
Symbol
Ctrl
Type
Function
PORST
I
I /
Power On Reset Input
PD /
VEXT
Additional strong PD in case of power fail.
122
ESR0
I/O
MP /
OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished. See
also SCU chapter for details.
Default after power-on can be different. See also SCU
chapter ´Reset Control Unit´ and SCU_IOCR register
description.
EVRWUP
ESR1
I
EVR Wakeup Pin
120
85
I/O
MP / PU1 / External System Request Reset 1
VEXT
Default NMI function.
See also SCU chapter ´Reset Control Unit´ and
SCU_IOCR register description.
EVRWUP
VGATE1P
I
EVR Wakeup Pin
O
VGATE1P External Pass Device gate control for EVR13
/
- /
VEXT
112
114
115
102
103
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
TRST
I
A2 /
PD /
VDDP3
JTAG Module Reset/Enable Input
TCK
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
XTAL1
XTAL2
I
XTAL1 /
- /
VDDP3
Main Oscillator/PLL/Clock Generator Input
O
XTAL2 /
- /
Main Oscillator/PLL/Clock Generator Output
VDDP3
Table 2-17 Supply
Pin
52
Symbol
Ctrl
Type
Vx
Function
VAREF1
I
Positive Analog Reference Voltage 1
51
VAGND1
I
Vx
Negative Analog Reference Voltage 1
Data Sheet
61
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
Table 2-17 Supply (cont’d)
Pin
26
Symbol
Ctrl
Type
Vx
Function
VAREF2
I
Positive Analog Reference Voltage 2
27
VAGND2
VDDM
I
I
I
I
Vx
Vx
Vx
Vx
Negative Analog Reference Voltage 2
ADC Analog Power Supply (3.3V / 5V)
Digital Ground
54
101
10
VSS
VDD / VDDSB
Emulation Device: Emulation SRAM Standby Power
Supply (1.3V) (Emulation Device only).
Production Device: VDD (1.3V).
123, 68,
24
VDD
VDD
I
I
Vx
Vx
Digital Core Power Supply (1.3V)
100
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (1.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
153, 99,
69, 25
VEXT
I
I
I
Vx
Vx
Vx
External Power Supply (5V / 3.3V)
154
104
VDDP3
VDDP3
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power Supply for
VFLEX.
Digital Power Supply for Oscillator, LVDSH and A2
pads (3.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (3.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
155
164
53
VDDFL3
VFLEX
VSSM
I
I
I
Vx
Vx
Vx
Flash Power Supply (3.3V)
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
Analog Ground for VDDM
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
Data Sheet
62
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP+ (5V/3.3V, LVTTL)
MPR = Pad class MPR (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSH (LVDS/CMOS 3.3V)
S = Pad class S (ADC overlayed with General Purpose Input)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply (the Exposed Pad is also considered as VSS and shall be connected to ground)
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
2.1.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during PORST active
Control of the Emergency Stop function:
1)The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak
internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General
Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
63
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC275x Pin Definition and Functions:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
•
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
2.1.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-18 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2)Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
64
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
2.2
TC277x Pin Definition and Functions: BGA292
Figure 2-2 is showing the TC277x Logic Symbol for the package variant: BGA292.
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Y
W
V
U
T
VSS
P32.3
P32.2
P32.0 P33.13 P33.11
P33.9
P33.7
P33.5
P33.3
P33.1
AN5
AN10 VAGND1 VAREF1 VDDM VSSM
AN20
AN21
NC
Y
W
V
U
T
VGATE1
VEXT
P23.0
P23.2
P23.4
P22.2
P22.0
VDDP3
VSS
VEXT
P23.1
P23.3
P22.3
P22.1
VDD
P32.4
P33.12 P33.10
P
P33.8
P33.6
P33.4
P33.2
P33.0
AN2
AN8
AN11
AN13
AN16
AN18
AN19
AN24
AN26
AN28
AN25
AN27
AN29
17
16
15
14
13
12
11
10
9
8
7
6
5
4
VSS
P32.7
P32.6
P33.15
P34.5
P34.3
P34.1
AN1
AN3
AN7
AN9
AN14
AN17
NC
U
T
U
P23.5
P23.6
P22.5
P22.7
P22.9
VSS
P32.5
P33.14
P34.4
VDD
P34.2 VEVRSB AN0
AN4
AN6
AN12
AN15
AN22
AN23
AN34
AN38
AN40
AN42
AN30
AN31
AN32
AN36
AN41
AN43
VAGND2 VAREF2
T
R
P
N
M
L
P23.7
P22.4
P22.6
P22.8
Top-View
AN35
AN37
AN45
AN47
AN33
AN39
AN44
AN46
R
P
N
M
L
R
P
N
M
L
R
P
N
M
L
VSS
(AGBT (AGBT
TX0P)
VSS
VSS
VSS
VSS
VSS
VSS
VDD
TX0N)
VSS
VDD
VSS
VDD
VSS
XTAL1 XTAL2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(AGBT
ERR)
VSS
(AGBT
CLKN)
VSS
TRST
P21.2
P21.3
P20.2
P20.1
P20.7
P22.11 P22.10
VSS
VSS
VSS
VSS
P00.12 P00.11
VSS
(AGBT
CLKP)
NC
(VDDPSB)
K
J
P21.4
P21.5
P20.0
P20.3
P20.8
P21.0
P21.1
P21.6
TMS
TCK
P00.10 P00.8
P00.9
P00.5
P00.3
P00.1
P02.7
P02.5
P02.3
P02.1
VSS
P00.7
P00.4
P00.2
P00.0
P02.8
P02.6
P02.4
P02.2
P02.0
K
J
K
J
K
J
VSS
VDD
VSS
P01.7
P01.5
P01.3
P00.6
P01.6
P01.4
VDD
(VDDSB)
H
G
F
H
G
F
P21.7
VSS
VSS
VSS
VSS
H
G
F
H
G
F
VDD
(VDDSB)
PORST ESR1
VDD
P20.6
P20.9
ESR0
P02.10 P02.11
E
D
C
B
A
P20.11 P20.10
P20.13 P20.12
E
D
VSS VDDFL3 P15.5
P14.2
P12.0
P12.1
P11.0
P11.1
P11.7
P11.8
P11.13
VSS
P02.9
E
D
E
D
C
B
A
VSS VDDFL3 P15.7
P15.8
14
P14.7
13
P14.9 P14.10 P11.4
P11.6
9
P11.5 P11.14 P11.15 VFLEX
VSS
4
17
16
15
12
11
10
8
7
6
5
P20.14
P15.0
P15.2
VSS
VDDP3 P15.3
P14.0
P14.4
P14.3
P14.6
P13.0
P13.2
P11.3 P11.10 P11.12 P10.1
P10.4
P10.5
P10.8
VEXT
VSS
VDDP3 P15.1
19 18
P15.4
P15.6
P14.1
P14.5
P14.8
P13.1
P13.3
P11.2
P11.9 P11.11 P10.0
P10.3
P10.2
P10.6
P10.7
VEXT
NC
20
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 2-2 TC277x Logic Symbol for the package variant BGA292.
Data Sheet
65
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
2.2.1
TC277xBGA292 Package Variant Pin Configuration
Table 2-19 Port 00 Functions
Pin
G1
Symbol
P00.0
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN9
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
HWOU
T
G2
P00.1
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN10
ARX3E
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN5A
DS5NA
VADCG7.5
CIFD10
P00.1
ASCLIN3 input
CAN node 1 input
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 5 input A
DSADC negative analog input of channel 5, pin A
VADC analog input channel 5 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
–
Reserved
DSCOUT5
–
DSADC channel 5 output
Reserved
SPC0
SENT output
CC60
CCU61 output
Data Sheet
66
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
H1
Symbol
P00.2
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN11
SENT1B
DSDIN5A
DS5PA
VADCG7.4
CIFD11
P00.2
SENT input
DSADC channel 5 input A
DSADC positive analog input of channel 5, pin A
VADC analog input channel 4 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT11
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
TXDCAN3
–
PSI5 output
CAN node 3 output
Reserved
COUT60
P00.3
CCU61 output
H2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN12
RXDCAN3A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG7.3
DSITR5F
CIFD12
P00.3
CAN node 3 input
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input A
VADC analog input channel 3 of group 7
DSADC channel 5 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
Data Sheet
67
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
J1
Symbol
P00.4
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN13
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG7.2
CIFD13
P00.4
SENT input
DSADC channel 3 input A
DSADC input
VADC analog input channel 2 of group 7 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT13
PSISTX
–
PSI5-S output
Reserved
PSITX1
VADCG4BFL0
SPC3
PSI5 output
VADC output
SENT output
COUT61
P00.5
CCU61 output
J2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN14
PSIRX2A
SENT4B
CC62INB
CC62INA
DSCIN2A
VADCG7.1
CIFD14
P00.5
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 2 input A
VADC analog input channel 1 of group 7 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT14
DSCGPWMN
–
DSADC output
Reserved
DSCOUT2
VADCG4BFL1
SPC4
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
Data Sheet
68
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
J4
Symbol
P00.6
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN15
SENT5B
DSDIN2A
VADCG7.0
DSITR4F
CIFD15
SENT input
DSADC channel 2 input A
VADC analog input channel 0 of group 7
DSADC channel 4 input F
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG4BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
P00.7
CCU61 output
K1
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN16
SENT6B
CC60INC
CCPOS0A
T12HRB
T2INA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSCIN4A
DS4NA
DSADC channel 4 input A
DSADC negative analog input of channel 4, pin A
VADC analog input channel 5 of group 6
CIF input
VADCG6.5
CIFCLK
P00.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG4BFL3
DSCOUT4
VADCEMUX11
SPC6
VADC output
DSADC channel 4 output
VADC output
SENT output
CC60
CCU61 output
Data Sheet
69
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
K4
Symbol
P00.8
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN17
SENT7B
CC61INC
CCPOS1A
T13HRB
T2EUDA
DSDIN4A
DS4PA
VADCG6.4
CIFVSNC
P00.8
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSADC channel 4 input A
DSADC channel 4 input A
VADC analog input channel 4 of group 6
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
SPC7
VADC output
SENT output
CC61
CCU61 output
Data Sheet
70
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
K2
Symbol
P00.9
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN18
SENT8B
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
DSCIN1A
VADCG6.3
DSITR3F
CIFHSNC
P00.9
SENT input
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
DSADC channel 1 input A
VADC analog input channel 3 of group 6
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
DSCOUT1
–
QSPI3 output
ASCLIN3 output
DSADC channel 1 output
Reserved
SPC8
SENT output
CC62
CCU61 output
K5
P00.10
TIN19
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT9B
DSDIN1A
VADCG6.2
P00.10
TOUT19
–
SENT input
DSADC channel 1 input A
VADC analog input channel 2 of group 6 (MD)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
SPC9
SENT output
COUT63
CCU61 output
Data Sheet
71
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
L1
Symbol
P00.11
TIN20
CTRAPA
T12HRE
DSCIN0A
VADCG6.1
P00.11
TOUT20
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
CCU60 input
CCU61 input
DSADC channel 0 input A
VADC analog input channel 1 of group 6 (MD)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
DSCOUT0
–
DSADC channel 0 output
Reserved
–
Reserved
–
Reserved
L2
P00.12
TIN21
ACTS3A
DSDIN0A
VADCG6.0
P00.12
TOUT21
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN3 input
DSADC channel 0 input A
VADC analog input channel 0 of group 6
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
Data Sheet
72
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-20 Port 01 Functions
Pin
G5
Symbol
Ctrl
Type
Function
P01.3
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN111
SLSI3B
QSPI3 input
General-purpose output
GTM output
P01.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT111
–
Reserved
–
Reserved
SLSO39
QSPI3 output
CAN node 1 output
Reserved
TXDCAN1
–
–
Reserved
G4
P01.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN112
RXDCAN1C
CAN node 1 input
General-purpose output
GTM output
P01.4
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT112
–
Reserved
–
Reserved
SLSO310
QSPI3 output
Reserved
–
–
Reserved
–
Reserved
H5
P01.5
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN113
MRST3C
QSPI3 input
General-purpose output
GTM output
P01.5
O0
O1
O2
O3
O4
O5
O6
O7
TOUT113
–
Reserved
–
Reserved
MRST3
QSPI3 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
73
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-20 Port 01 Functions (cont’d)
Pin
H4
Symbol
Ctrl
Type
Function
P01.6
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN114
MTSR3C
QSPI3 input
General-purpose output
GTM output
Reserved
P01.6
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT114
–
–
Reserved
MTSR3
QSPI3 output
Reserved
–
–
Reserved
–
Reserved
J5
P01.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN115
SCLK3C
QSPI3 input
General-purpose output
GTM output
Reserved
P01.7
O0
O1
O2
O3
O4
O5
O6
O7
TOUT115
–
–
Reserved
SCLK3
QSPI3 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
74
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-21 Port 02 Functions
Pin
B1
Symbol
P02.0
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN0
ARX2G
REQ6
ASCLIN2 input
SCU input
CC60INA
CC60INB
CIFD0
P02.0
CCU60 input
CCU61 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY output
SLSO31
DSCGPWMN
TXDCAN0
TXDA
CC60
CCU60 output
C2
P02.1
LP / PU1 General-purpose input
/ VEXT
TIN1
GTM input
REQ14
ARX2B
RXDCAN0A
RXDA2
CIFD1
P02.1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT1
–
Reserved
SLSO32
DSCGPWMP
–
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
75
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-21 Port 02 Functions (cont’d)
Pin
C1
Symbol
P02.2
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN2
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
PSI5 output
SLSO33
PSITX0
TXDCAN2
TXDB
CAN node 2 output
ERAY output
CC61
CCU60 output
General-purpose input
GTM input
D2
P02.3
LP /
PU1 /
VEXT
TIN3
ARX1G
RXDCAN2B
RXDB2
PSIRX0B
DSCIN5B
SDI11
ASCLIN1 input
CAN node 2 input
ERAY input
PSI5 input
DSADC channel 5 input B
MSC1 input
CIFD3
CIF input
P02.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
DSCOUT5
–
ASCLIN2 output
QSPI3 output
DSADC channel 5 output
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
76
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-21 Port 02 Functions (cont’d)
Pin
D1
Symbol
P02.4
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN4
SLSI3A
ECTT1
QSPI3 input
TTCAN input
RXDCAN0D
CC62INA
CC62INB
DSDIN5B
SDA0A
CIFD4
CAN node 0 input
CCU60 input
CCU61 input
DSADC channel 5 input B
I2C0 input
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXENA
CC62
ERAY output
CCU60 output
General-purpose input
GTM input
E2
P02.5
MP+ /
PU1 /
VEXT
TIN5
MRST3A
ECTT2
QSPI3 input
TTCAN input
PSIRX1B
PSISRXB
SENT3C
DSCIN4B
SCL0A
PSI5 input
PSI5-S input
SENT input
DSADC channel 4 input B
I2C0 input
CIFD5
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
DSCOUT4
SCL0
CAN node 0 output
QSPI3 output
DSADC channel 4 output
I2C0 output
TXENB
COUT62
ERAY output
CCU60 output
Data Sheet
77
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-21 Port 02 Functions (cont’d)
Pin
E1
Symbol
P02.6
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN6
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
DSDIN4B
DSITR5E
P02.6
DSADC channel 4 input B
DSADC channel 5 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
Data Sheet
78
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-21 Port 02 Functions (cont’d)
Pin
F2
Symbol
P02.7
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN7
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
DSITR4E
P02.7
DSADC channel 3 input B
DSADC channel 4 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSCOUT3
VADCEMUX01
SPC1
DSADC channel 3 output
VADC output
SENT output
CC61
CCU60 output
Data Sheet
79
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-21 Port 02 Functions (cont’d)
Pin
F1
Symbol
P02.8
Ctrl
Type
Function
I
LP / PU1 General-purpose input
/
TIN8
GTM input
VEXT
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
CIFD8
DSDIN3B
DSITR3E
P02.8
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
E4
P02.9
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN116
P02.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT116
ATX2
ASCLIN2 output
Reserved
–
–
Reserved
TXDCAN1
–
CAN node 1 output
Reserved
–
Reserved
Data Sheet
80
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-21 Port 02 Functions (cont’d)
Pin
F5
Symbol
Ctrl
Type
Function
P02.10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN117
ARX2C
ASCLIN2 input
CAN node 1 input
General-purpose output
GTM output
Reserved
RXDCAN1E
P02.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT117
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
F4
P02.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN118
P02.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT118
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-22 Port 10 Functions
Pin
A7
Symbol
Ctrl
Type
Function
P10.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN102
T6EUDB
GPT120 input
General-purpose output
GTM output
P10.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT102
–
Reserved
SLSO110
QSPI1 output
Reserved
–
VADCG6BFL0
VADC output
Reserved
–
–
Reserved
Data Sheet
81
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-22 Port 10 Functions (cont’d)
Pin
B7
Symbol
P10.1
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL1
END03
–
A5
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
QSPI1 input
GPT120 input
SCU input
REQ2
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL2
END02
–
Data Sheet
82
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-22 Port 10 Functions (cont’d)
Pin
A6
Symbol
P10.3
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG6BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
B6
P10.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN106
MTSR1C
CCPOS0C
T3INB
QSPI1 input
CCU60 input
GPT120 input
General-purpose output
GTM output
P10.4
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT106
–
Reserved
SLSO18
MTSR1
EN00
QSPI1 output
QSPI1 output
MSC0 output
MSC0 output
Reserved
END02
–
B5
P10.5
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
INJ01
SCU input
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
QSPI1 output
GPT120 output
ASCLIN2 output
Reserved
SLSO38
SLSO19
T6OUT
ASLSO2
-
Data Sheet
83
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-22 Port 10 Functions (cont’d)
Pin
A4
Symbol
P10.6
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
MTSR3B
HWCFG5
P10.6
ASCLIN2 input
QSPI3 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
T3OUT
-
ASCLIN2 output
QSPI3 output
GPT120 output
Reserved
MRST1
VADCG7BFL0
P10.7
QSPI1 output
VADC output
General-purpose input
GTM input
A3
LP /
PU1 /
VEXT
TIN109
ACTS2A
MRST3B
REQ4
ASCLIN2 input
QSPI3 input
SCU input
CCPOS1C
T3EUDB
P10.7
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT109
–
Reserved
MRST3
VADCG7BFL1
–
QSPI3 output
VADC output
Reserved
–
Reserved
–
Reserved
Data Sheet
84
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-22 Port 10 Functions (cont’d)
Pin
B4
Symbol
P10.8
TIN110
SCLK3B
REQ5
CCPOS2C
T4INB
P10.8
TOUT110
ARTS2
SCLK3
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
SCU input
CCU60 input
GPT120 input
General-purpose output
GTM output
ASCLIN2 output
QSPI3 output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
–
Reserved
–
Reserved
–
Reserved
Table 2-23 Port 11 Functions
Pin
Symbol
P11.0
TIN119
ARX3B
P11.0
TOUT119
ATX3
–
Ctrl
Type
Function
E10
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
ASCLIN3 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
ETHTXD3
–
ETH output
Reserved
E9
P11.1
TIN120
P11.1
TOUT120
ASCLK3
ATX3
–
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
–
Reserved
ETHTXD2
–
ETH output
Reserved
Data Sheet
85
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-23 Port 11 Functions (cont’d)
Pin
Symbol
P11.2
Ctrl
Type
Function
A10
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
TIN95
P11.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT95
END03
SLSO05
SLSO15
EN01
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
P11.3
CCU60 output
General-purpose input
GTM input
B10
MPR /
PU1 /
VFLEX
TIN96
MRST1B
SDI03
P11.3
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT96
–
Reserved
MRST1
TXDA
QSPI1 output
ERAY output
Reserved
–
ETHTXD0
COUT62
P11.4
ETH output
CCU60 output
General-purpose input
GTM input
D10
MP+ /
PU1 /
VFLEX
TIN121
ETHRXCLKB
P11.4
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT121
ASCLK3
–
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
ETHTXER
–
ETH output
Reserved
Data Sheet
86
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-23 Port 11 Functions (cont’d)
Pin
D8
Symbol
P11.5
TIN122
ETHTXCLKA
P11.5
TOUT122
–
Ctrl
Type
Function
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
D9
P11.6
TIN97
SCLK1B
P11.6
TOUT97
TXENB
SCLK1
TXENA
FCLP0
ETHTXEN
COUT61
P11.7
TIN123
ETHRXD3
P11.7
TOUT123
–
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
General-purpose output
GTM output
ERAY output
QSPI1 output
ERAY output
MSC0 output
ETH output
O0
O1
O2
O3
O4
O5
O6
O7
I
CCU60 output
General-purpose input
GTM input
E8
LP /
PU1 /
VFLEX
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
87
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-23 Port 11 Functions (cont’d)
Pin
E7
Symbol
P11.8
TIN124
ETHRXD2
P11.8
TOUT124
–
Ctrl
Type
Function
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
A9
P11.9
TIN98
MTSR1B
RXDA1
ETHRXD1
P11.9
TOUT98
–
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
ERAY input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
–
MSC0 output
Reserved
COUT60
CCU60 output
Data Sheet
88
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-23 Port 11 Functions (cont’d)
Pin
B9
Symbol
P11.10
TIN99
Ctrl
Type
Function
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXDB1
ETHRXD0
SDI00
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY input
ETH input
MSC0 input
P11.10
TOUT99
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
General-purpose input
GTM input
A8
P11.11
TIN100
ETHCRSDVA
ETHRXDVA
ETHCRSB
P11.11
TOUT100
END02
SLSO04
SLSO14
EN00
MP+ /
PU1 /
VFLEX
ETH input
ETH input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY output
CCU60 output
TXENB
CC61
Data Sheet
89
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-23 Port 11 Functions (cont’d)
Pin
B8
Symbol
Ctrl
Type
Function
P11.12
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
O0
TIN101
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
P11.12
General-purpose output
GTM output
ASCLIN1 output
GTM output
ERAY output
CAN node 3 output
SCU output
TOUT101
O1
O2
O3
O4
O5
O6
O7
I
ATX1
GTMCLK2
TXDB
TXDCAN3
EXTCLK1
CC60
CCU60 output
General-purpose input
GTM input
E6
P11.13
LP /
PU1 /
VFLEX
TIN125
ETHRXERA
ETH input
P11.13
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT125
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
D7
P11.14
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN126
ETHCRSDVB
ETH input
ETHRXDVB
ETH input
ETHCRSA
ETH input
P11.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT126
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
90
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-23 Port 11 Functions (cont’d)
Pin
D6
Symbol
Ctrl
Type
Function
P11.15
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN127
ETHCOL
ETH input
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT127
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-24 Port 12 Functions
Pin
Symbol
Ctrl
Type
Function
E12
P12.0
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN128
ETHRXCLKC
ETH input
RXDCAN0C
CAN node 0 input
General-purpose output
GTM output
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT128
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDC
ETH output
–
Reserved
E11
P12.1
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN129
P12.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT129
ASLSO3
ASCLIN3 output
Reserved
–
–
Reserved
TXDCAN0
CAN node 0 output
Reserved
–
–
Reserved
ETHMDIOC
HWOU
T
ETH input/output
Data Sheet
91
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-25 Port 13 Functions
Pin
Symbol
P13.0
TIN91
P13.0
TOUT91
END03
SCLK2N
EN01
Ctrl
Type
Function
B12
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC0 output
QSPI2 output (LVDS)
MSC0 output
FCLN0
FCLND0
–
MSC0 output (LVDS)
MSC0 output (LVDS)
Reserved
A12
P13.1
TIN92
SCL0B
P13.1
TOUT92
–
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
MSC0 output (LVDS)
I2C0 output
–
Reserved
B11
P13.2
TIN93
CAPINA
SDA0B
P13.2
TOUT93
–
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR2N
FCLP0
SON0
SDA0
SOND0
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
MSC0 output (LVDS)
Data Sheet
92
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-25 Port 13 Functions (cont’d)
Pin
Symbol
P13.3
TIN94
P13.3
TOUT94
–
Ctrl
Type
Function
A11
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR2P
–
QSPI2 output (LVDS)
Reserved
SOP0
–
MSC0 output (LVDS)
Reserved
–
Reserved
Table 2-26 Port 14 Functions
Pin
Symbol
P14.0
Ctrl
Type
Function
B16
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN80
P14.0
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
TXDA
O3
O4
O5
ERAY output
ERAY output
TXDB
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function.
ASCLK0
COUT62
O6
O7
ASCLIN0 output
CCU60 output
Data Sheet
93
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-26 Port 14 Functions (cont’d)
Pin
Symbol
P14.1
Ctrl
Type
Function
A15
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN81
REQ15
ARX0A
SCU input
ASCLIN0 input
Recommended as Boot loader pin.
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function.
RXDA3
RXDB3
EVRWUPA
P14.1
TOUT81
ATX0
–
ERAY input
ERAY input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
P14.2
TIN82
CCU60 output
General-purpose input
GTM input
E13
LP /
PU1 /
VEXT
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
SLSO21
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
Data Sheet
94
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-26 Port 14 Functions (cont’d)
Pin
Symbol
P14.3
Ctrl
Type
Function
B14
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN83
ARX2A
REQ10
HWCFG3_BMI
SDI02
ASCLIN2 input
SCU input
SCU input
MSC0 input
P14.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT83
ATX2
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
B15
P14.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN84
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT84
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
95
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-26 Port 14 Functions (cont’d)
Pin
Symbol
P14.5
Ctrl
Type
Function
A14
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN85
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT85
–
–
Reserved
–
Reserved
–
Reserved
TXDB
–
ERAY output
Reserved
B13
P14.6
TIN86
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT86
–
Reserved
SLSO22
QSPI2 output
Reserved
–
–
Reserved
TXENB
–
ERAY output
Reserved
D13
P14.7
TIN87
RXDB0
P14.7
TOUT87
ARTS0
SLSO24
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ERAY input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
96
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-26 Port 14 Functions (cont’d)
Pin
Symbol
P14.8
TIN88
ARX1D
RXDCAN2D
RXDA0
P14.8
TOUT88
–
Ctrl
Type
Function
A13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
CAN node 2 input
ERAY input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
D12
P14.9
TIN89
ACTS0A
P14.9
TOUT89
END03
EN01
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
MSC0 output
MSC0 output
Reserved
TXENB
TXENA
–
ERAY output
ERAY output
Reserved
D11
P14.10
TIN90
P14.10
TOUT90
END02
EN00
ATX1
TXDCAN2
TXDA
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
MSC0 output
ASCLIN1 output
CAN node 2 output
ERAY output
Reserved
Data Sheet
97
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-27 Port 15 Functions
Pin
Symbol
P15.0
TIN71
P15.0
TOUT71
ATX1
Ctrl
Type
Function
B20
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
Reserved
SLSO013
–
TXDCAN2
ASCLK1
–
CAN node 2 output
ASCLIN1 output
Reserved
A18
P15.1
TIN72
REQ16
ARX1A
RXDCAN2A
SLSI2B
EVRWUPB
P15.1
TOUT72
ATX1
LP /
PU1 /
VEXT
General-purpose input
GTM input
SCU input
ASCLIN1 input
CAN node 2 input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
Reserved
–
Reserved
–
Reserved
C19
P15.2
TIN73
SLSI2A
MRST2E
P15.2
TOUT73
ATX0
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
Data Sheet
98
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-27 Port 15 Functions (cont’d)
Pin
Symbol
P15.3
TIN74
ARX0B
SCLK2A
RXDCAN1A
P15.3
TOUT74
ATX0
Ctrl
Type
Function
B17
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
QSPI2 input
CAN node 1 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
A17
P15.4
TIN75
MRST2A
REQ0
SCL0C
P15.4
TOUT75
ATX1
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
SCL0
I2C0 output
CC62
CCU60 output
Data Sheet
99
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-27 Port 15 Functions (cont’d)
Pin
Symbol
P15.5
TIN76
ARX1B
MTSR2A
REQ13
SDA0C
P15.5
TOUT76
ATX1
Ctrl
Type
Function
E14
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
General-purpose input
GTM input
A16
P15.6
TIN77
MTSR2B
P15.6
TOUT77
ATX3
MP /
PU1 /
VEXT
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
MTSR2
–
SCLK2
ASCLK3
CC60
QSPI2 output
ASCLIN3 output
CCU60 output
General-purpose input
GTM input
D15
P15.7
TIN78
ARX3A
MRST2B
P15.7
TOUT78
ATX3
MP /
PU1 /
VEXT
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
100
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-27 Port 15 Functions (cont’d)
Pin
Symbol
P15.8
TIN79
SCLK2B
REQ1
P15.8
TOUT79
–
Ctrl
Type
Function
D14
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
ASCLIN3 output
CCU60 output
Table 2-28 Port 20 Functions
Pin
Symbol
P20.0
TIN59
RXDCAN3C
T6EUDA
REQ9
SYSCLK
TGI0
Ctrl
Type
Function
H20
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
CAN node 3 input
GPT120 input
SCU input
HSCT input
OCDS input
P20.0
TOUT59
ATX3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
Data Sheet
101
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-28 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
G19
P20.1
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN60
TGI1
OCDS input
General-purpose output
GTM output
Reserved
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
TOUT60
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO1
HWOU
T
OCDS; ENx
H19
P20.2
I
LP /
General-purpose input
PU /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
OCDS input
P20.2
O0
O1
O2
O3
O4
O5
O6
O7
I
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
General-purpose input
GTM input
–
–
–
–
–
–
–
G20
P20.3
TIN61
T6INA
ARX3C
P20.3
TOUT61
ATX3
SLSO09
SLSO29
TXDCAN3
–
LP /
PU1 /
VEXT
GPT120 input
ASCLIN3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
QSPI0 output
QSPI2 output
CAN node 3 output
Reserved
–
Reserved
Data Sheet
102
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-28 Port 20 Functions (cont’d)
Pin
Symbol
P20.6
Ctrl
Type
Function
F17
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN62
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT62
ARTS1
SLSO08
SLSO28
–
ASCLIN1 output
QSPI0 output
QSPI2 output
Reserved
WDT2LCK
–
SCU output
Reserved
F19
P20.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN63
ACTS1A
RXDCAN0B
P20.7
ASCLIN1 input
CAN node 0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT63
–
Reserved
–
Reserved
–
Reserved
–
Reserved
WDT1LCK
COUT63
P20.8
SCU output
CCU61 output
General-purpose input
GTM input
F20
MP /
PU1 /
VEXT
TIN64
P20.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT64
ASLSO1
SLSO00
SLSO10
TXDCAN0
WDT0LCK
CC60
ASCLIN1 output
QSPI0 output
QSPI1 output
CAN node 0 output
SCU output
CCU61 output
Data Sheet
103
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-28 Port 20 Functions (cont’d)
Pin
Symbol
P20.9
Ctrl
Type
Function
E17
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN65
ARX1C
RXDCAN3E
REQ11
SLSI0B
P20.9
ASCLIN1 input
CAN node 3 input
SCU input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT65
–
Reserved
SLSO01
SLSO11
–
QSPI0 output
QSPI1 output
Reserved
WDTSLCK
CC61
SCU output
CCU61 output
General-purpose input
GTM input
E19
P20.10
TIN66
P20.10
TOUT66
ATX1
MP /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
CAN node 3 output
ASCLIN1 output
CCU61 output
General-purpose input
GTM input
SLSO06
SLSO27
TXDCAN3
ASCLK1
CC62
E20
P20.11
TIN67
SCLK0A
P20.11
TOUT67
–
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
COUT60
CCU61 output
Data Sheet
104
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-28 Port 20 Functions (cont’d)
Pin
Symbol
P20.12
TIN68
MRST0A
P20.12
TOUT68
–
Ctrl
Type
Function
D19
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST0
MTSR0
–
QSPI0 output
QSPI0 output
Reserved
–
Reserved
COUT61
P20.13
TIN69
SLSI0A
P20.13
TOUT69
–
CCU61 output
General-purpose input
GTM input
D20
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO02
SLSO12
SCLK0
–
QSPI0 output
QSPI1 output
QSPI0 output
Reserved
COUT62
P20.14
TIN70
MTSR0A
P20.14
TOUT70
–
CCU61 output
General-purpose input
GTM input
C20
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
105
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-29 Port 21 Functions
Pin
Symbol
Ctrl
Type
Function
K17
P21.0
I
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
TIN51
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT51
–
–
Reserved
–
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
HSM1
HWOU
T
HSM output 1
J17
P21.1
I
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
TIN52
ETHMDIOB
ETH input
(Not for production purposes)
P21.1
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM output
Reserved
TOUT52
–
–
Reserved
–
Reserved
–
Reserved
ETHMDIO
ETH output
(Not for production purposes)
–
O7
Reserved
HSM2
HWOU
T
HSM output 2
Data Sheet
106
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-29 Port 21 Functions (cont’d)
Pin
Symbol
P21.2
TIN53
MRST2CN
MRST3FN
ARX3GN
EMGSTOPB
RXDN
P21.2
TOUT53
ASLSO3
–
Ctrl
Type
Function
K19
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
QSPI2 input (LVDS)
QSPI3 input (LVDS)
ASCLIN3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
–
Reserved
J19
P21.3
TIN54
MRST2CP
MRST3FP
ARX3GP
RXDP
P21.3
TOUT54
–
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
QSPI2 input (LVDS)
QSPI3 input (LVDS)
ASCLIN3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDIOD
HWOU
T
ETH input/output
Data Sheet
107
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-29 Port 21 Functions (cont’d)
Pin
Symbol
P21.4
TIN55
P21.4
TOUT55
–
Ctrl
Type
Function
K20
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDN
P21.5
TIN56
P21.5
TOUT56
ASCLK3
–
HSCT output (LVDS)
General-purpose input
GTM input
J20
LVDSH_P/
PU1 /
VDDP3
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDP
P21.6
TIN57
ARX3F
TGI2
TDI
HSCT output (LVDS)
General-purpose input
GTM input
H17
A2 /
PU /
VDDP3
ASCLIN3 input
OCDS input
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
TOUT57
ASLSO3
–
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
Reserved
–
Reserved
SYSCLK
–
HSCT output
Reserved
T3OUT
TGO2
GPT120 output
OCDS; ENx
HWOU
T
Data Sheet
108
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-29 Port 21 Functions (cont’d)
Pin
Symbol
P21.7
TIN58
DAP2
TGI3
Ctrl
Type
Function
H16
I
A2 /
PU /
VDDP3
General-purpose input
GTM input
OCDS input
OCDS input
TDO
OCDS (JTAG) input
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ. In DAP mode this pin
is used as P21.7 and controlled by the related
port control logic
ETHRXERB
T5INA
P21.7
TOUT58
ATX3
ASCLK3
–
ETH input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
T6OUT
TGO3
TDO
GPT120 output
OCDS; ENx
HWOU
T
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ. In DAP mode this pin
is used as P21.7 and controlled by the related
port control logic
Data Sheet
109
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-30 Port 22 Functions
Pin
Symbol
P22.0
Ctrl
Type
Function
P20
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN47
MTSR3E
P22.0
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT47
ATX3N
MTSR3
SCLK3N
FCLN1
FCLND1
–
ASCLIN3 output (LVDS)
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
P19
P22.1
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
TIN48
MRST3E
P22.1
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT48
ATX3P
MRST3
SCLK3P
FCLP1
–
ASCLIN3 output (LVDS)
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
R20
P22.2
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN49
SLSI3D
P22.2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT49
–
Reserved
SLSO312
MTSR3N
SON1
SOND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
110
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-30 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
R19
P22.3
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
TIN50
SCLK3E
QSPI3 input
P22.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT50
–
Reserved
SCLK3
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
MTSR3P
SOP1
–
–
Reserved
P16
P22.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN130
P22.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT130
–
Reserved
–
Reserved
SLSO012
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
P17
P22.5
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN131
MTSR0C
QSPI0 input
P22.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT131
–
Reserved
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
111
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-30 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
N16
P22.6
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN132
MRST0C
QSPI0 input
General-purpose output
GTM output
Reserved
P22.6
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT132
–
–
Reserved
MRST0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
N17
P22.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN133
SCLK0C
QSPI0 input
General-purpose output
GTM output
Reserved
P22.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT133
–
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
M16
P22.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN134
SCLK0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.8
O0
O1
O2
O3
O4
O5
O6
O7
TOUT134
–
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
112
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-30 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
M17
P22.9
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN135
MRST0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.9
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT135
–
–
Reserved
MRST0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
L16
P22.10
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN136
MTSR0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT136
–
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
L17
P22.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN137
P22.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT137
–
–
Reserved
SLSO010
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
113
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-31 Port 23 Functions
Pin
Symbol
Ctrl
Type
Function
V20
P23.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN41
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT41
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
U19
P23.1
TIN42
SDI10
P23.1
TOUT42
ARTS1
SLSO313
GTMCLK0
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
GTM output
Reserved
EXTCLK0
–
SCU output
Reserved
U20
P23.2
TIN43
P23.2
TOUT43
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
114
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-31 Port 23 Functions (cont’d)
Pin
Symbol
P23.3
TIN44
INJ10
P23.3
TOUT44
–
Ctrl
Type
Function
T19
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
T20
P23.4
TIN45
P23.4
TOUT45
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO35
END12
EN10
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
T17
P23.5
TIN46
P23.5
TOUT46
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO34
END13
EN11
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Data Sheet
115
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-31 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
R17
P23.6
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN138
P23.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT138
–
–
Reserved
SLSO011
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
R16
P23.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN139
P23.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT139
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-32 Port 32 Functions
Pin
Symbol
P32.0
Ctrl
Type
LP /
Function
Y17
I
General-purpose input
EVR13 SMPS
-> PD,
GPIO - > PU
/
TIN36
GTM input
PMU input
FDEST
VGATE1N
SMPS mode: analog output. External Pass Device
gate control for EVR13
VEXT
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT36
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
116
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-32 Port 32 Functions (cont’d)
Pin
Symbol
P32.2
TIN38
ARX3D
RXDCAN3B
P32.2
TOUT38
ATX3
Ctrl
Type
Function
Y18
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN3 input
CAN node 3 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
DCDCSYNC
–
SCU output
Reserved
Y19
P32.3
TIN39
P32.3
TOUT39
ATX3
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
ASCLK3
TXDCAN3
–
ASCLIN3 output
CAN node 3 output
Reserved
–
Reserved
W18
P32.4
TIN40
ACTS1B
SDI12
P32.4
TOUT40
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
END12
GTMCLK1
EN10
MSC1 output
GTM output
MSC1 output
SCU output
EXTCLK1
COUT63
CCU60 output
Data Sheet
117
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-32 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
T15
P32.5
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN140
P32.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT140
ATX2
ASCLIN2 output
Reserved
–
–
Reserved
–
Reserved
TXDCAN2
CAN node 2 output
Reserved
–
U15
P32.6
LP /
PU1 /
VEXT
General-purpose input
OCDS input
TGI4
TIN141
GTM input
RXDCAN2C
CAN node 2 input
ASCLIN2 input
General-purpose output
GTM output
ARX2F
P32.6
O0
O1
O2
O3
O4
O5
O6
O7
TOUT141
–
Reserved
–
Reserved
SLSO212
QSPI2 output
Reserved
–
–
Reserved
–
Reserved
TGO4
HWOU
T
OCDS; ENx
U16
P32.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN142
TGI5
OCDS input
General-purpose output
GTM output
Reserved
P32.7
O0
O1
O2
O3
O4
O5
O6
O7
TOUT142
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO5
HWOU
T
OCDS; ENx
Data Sheet
118
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-33 Port 33 Functions
Pin
Symbol
P33.0
Ctrl
Type
Function
W10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN22
DSITR0E
P33.0
DSADC channel 0 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT22
–
Reserved
–
Reserved
–
Reserved
–
Reserved
VADCG2BFL0
–
VADC output
Reserved
Y10
P33.1
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN23
PSIRX0C
SENT9C
DSCIN2B
DSITR1E
P33.1
PSI5 input
SENT input
DSADC channel 2 input B
DSADC channel 1 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT23
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT2
VADCEMUX02
VADCG2BFL1
–
DSADC channel 2 output
VADC output
VADC output
Reserved
W11
P33.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN24
SENT8C
DSDIN2B
DSITR2E
P33.2
SENT input
DSADC channel 2 input B
DSADC channel 2 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT24
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
VADCEMUX01
VADCG2BFL2
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
119
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-33 Port 33 Functions (cont’d)
Pin
Symbol
P33.3
Ctrl
Type
Function
Y11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN25
PSIRX1C
SENT7C
DSCIN1B
P33.3
PSI5 input
SENT input
DSADC channel 1 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT25
–
Reserved
–
Reserved
DSCOUT1
VADCEMUX00
VADCG2BFL3
–
DSADC channel 1 output
VADC output
VADC output
Reserved
W12
P33.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN26
SENT6C
CTRAPC
DSDIN1B
DSITR0F
P33.4
SENT input
CCU61 input
DSADC channel 1 input B
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
–
ASCLIN2 output
Reserved
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
120
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-33 Port 33 Functions (cont’d)
Pin
Symbol
P33.5
Ctrl
Type
Function
Y12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN27
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
DSITR1F
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 1 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
W13
P33.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN28
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
-
ASCLIN2 output
Reserved
PSITX2
PSI5 output
VADCEMUX10
VADCG1BFL0
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
121
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-33 Port 33 Functions (cont’d)
Pin
Symbol
P33.7
Ctrl
Type
Function
Y13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN29
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO37
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
VADCG1BFL1
–
VADC output
Reserved
W14
P33.8
MP /
HighZ/
VEXT
General-purpose input
GTM input
TIN30
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI3 output
Reserved
SLSO32
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
Y14
P33.9
TIN31
P33.9
TOUT31
ATX2
SLSO31
ASCLK2
–
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI3 output
ASCLIN2 output
Reserved
–
Reserved
CC62
CCU61 output
Data Sheet
122
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-33 Port 33 Functions (cont’d)
Pin
Symbol
P33.10
TIN32
Ctrl
Type
Function
W15
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3C
P33.10
TOUT32
SLSO16
SLSO311
ASLSO1
PSISCLK
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
QSPI1 output
QSPI3 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
P33.11
TIN33
CCU61 output
General-purpose input
GTM input
Y15
MP /
PU1 /
VEXT
SCLK3D
P33.11
TOUT33
ASCLK1
SCLK3
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC output
CCU61 output
General-purpose input
GTM input
W16
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR3D
P33.12
TOUT34
ATX1
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
ASCLIN1 output
Reserved
MTSR3
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
123
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-33 Port 33 Functions (cont’d)
Pin
Symbol
P33.13
TIN35
ARX1F
MRST3D
DSSGNB
INJ11
P33.13
TOUT35
ATX1
Ctrl
Type
Function
Y16
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
QSPI3 input
DSADC input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
QSPI2 output
Reserved
MRST3
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
General-purpose input
GTM input
T14
P33.14
TIN143
TGI6
LP /
PU1 /
VEXT
OCDS input
SCLK2D
P33.14
TOUT143
–
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
CC62
CCU60 output
OCDS; ENx
TGO6
HWOU
T
Data Sheet
124
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-33 Port 33 Functions (cont’d)
Pin
Symbol
P33.15
TIN144
TGI7
Ctrl
Type
Function
U14
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
OCDS input
General-purpose output
GTM output
Reserved
P33.15
TOUT144
–
O0
O1
O2
O3
O4
O5
O6
O7
SLSO211
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
COUT62
TGO7
CCU60 output
OCDS; ENx
HWOU
T
Table 2-34 Port 34 Functions
Pin
Symbol
P34.1
TIN146
P34.1
TOUT146
ATX0
–
Ctrl
Type
Function
U11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
TXDCAN0
–
CAN node 0 output
Reserved
–
Reserved
COUT63
P34.2
TIN147
ARX0D
RXDCAN0G
P34.2
TOUT147
–
CCU60 output
General-purpose input
GTM input
T12
LP /
PU1 /
VEXT
ASCLIN0 input
CAN node 0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CC60
CCU60 output
Data Sheet
125
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-34 Port 34 Functions (cont’d)
Pin
Symbol
P34.3
TIN148
P34.3
TOUT148
–
Ctrl
Type
Function
U12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
SLSO210
–
QSPI2 output
Reserved
–
Reserved
COUT60
P34.4
TIN149
MRST2D
P34.4
TOUT149
–
CCU60 output
General-purpose input
GTM input
T13
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
MRST2
–
QSPI2 output
Reserved
–
Reserved
CC61
P34.5
TIN150
MTSR2D
P34.5
TOUT150
–
CCU60 output
General-purpose input
GTM input
U13
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
MTSR2
–
QSPI2 output
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
126
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-35 Port 40 Functions
Pin
W2
Symbol
P40.0
Ctrl
Type
Function
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 0 of group 3
VADCG3.0
DS2PB
DSADC: positive analog input channe of DSADC 2, pin
B
CCPOS0D
SENT0A
P40.1
CCU60 input
SENT input
W1
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 1 of group 3 (MD)
DSADC: negative analog of input channel 2, pin B
CCU60 input
VADCG3.1
DS2NB
CCPOS1B
SENT1A
P40.2
SENT input
V2
V1
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 2 of group 3 (MD)
CCU60 input
VADCG3.2
CCPOS1D
SENT2A
P40.3
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
CCPOS2B
SENT3A
P40.4
CCU60 input
SENT input
P4
R1
N4
I
I
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 0 of group 4
CCU60 input
VADCG4.0
CCPOS2D
SENT4A
P40.5
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 1 of group 4 (MD)
CCU61 input
VADCG4.1
CCPOS0D
SENT5A
P40.6
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
CCU61 input
VADCG4.4
DS3PA
CCPOS1B
SENT6A
P40.7
SENT input
P2
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 5 of group 4
DSADC: negative analog input of channel 3, pin A
CCU61 input
VADCG4.5
DS3NA
CCPOS1D
SENT7A
SENT input
Data Sheet
127
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-35 Port 40 Functions (cont’d)
Pin
N5
Symbol
P40.8
Ctrl
Type
Function
I
S /
General-purpose input
HighZ /
VDDM
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel 3, pin B
CCU61 input
CCPOS2B
SENT8A
P40.9
SENT input
P1
I
S /
General-purpose input
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input of channel 3, pin B
CCU61 input
CCPOS2D
SENT9A
SENT input
Table 2-36 Analog Inputs
Pin
Symbol
AN0
Ctrl
Type
Function
T10
I
D /
Analog input 0
HighZ /
VDDM
VADCG0.0
DS1PA
AN1
VADC analog input channel 0 of group 0
DSADC: positive analog of input channel 1, pin A
Analog input 1
U10
W9
U9
I
I
I
D /
HighZ /
VDDM
VADCG0.1
DS1NA
AN2
VADC analog input channel 1 of group 0 (MD)
DSADC: negative analog input of channel 1, pin A
Analog input 2
D /
HighZ /
VDDM
VADCG0.2
DS0PA
AN3
VADC analog input channel 2 of group 0 (MD)
DSADC: positive analog input of channel 0, pin A
Analog input 3
D /
HighZ /
VDDM
VADCG0.3
DS0NA
AN4
VADC analog input channel 3 of group 0
DSADC: negative analog input of channel 0, pin A
Analog input 4
T9
Y9
T8
U8
I
I
I
I
D /
HighZ /
VDDM
VADCG0.4
VADC analog input channel 4 of group 0
AN5
D /
HighZ /
VDDM
Analog input 5
VADCG0.5
VADC analog input channel 5 of group 0
AN6
D /
HighZ /
VDDM
Analog input 6
VADCG0.6
VADC analog input channel 6 of group 0
AN7
D /
Analog input 7
HighZ /
VDDM
VADCG0.7
VADC analog input channel 7 of group 0 (with pull
down diagnostics)
W8
AN8
I
D /
Analog input 8
HighZ /
VDDM
VADCG1.0
VADC analog input channel 0 of group 1
Data Sheet
128
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-36 Analog Inputs (cont’d)
Pin
U7
Symbol
AN9
Ctrl
Type
Function
I
D /
Analog input 9
HighZ /
VDDM
VADCG1.1
VADC analog input channel 1 of group 1 (MD)
Y8
AN10
I
I
D /
HighZ /
VDDM
Analog input 10
VADCG1.2
VADC analog input channel 2 of group 1 (MD)
W7
AN11
D /
Analog input 11
HighZ /
VDDM
VADCG1.3
VADC analog input channel 3 of group 1 (with pull
down diagnostics)
T7
AN12
I
I
I
I
I
I
I
I
D /
HighZ /
VDDM
Analog input 12
VADCG1.4
VADC analog input channel 4 of group 1
W6
U6
T6
AN13
D /
HighZ /
VDDM
Analog input 13
VADCG1.5
VADC analog input channel 5 of group 1
AN14
D /
HighZ /
VDDM
Analog input 14
VADCG1.6
VADC analog input channel 6 of group 1
AN15
D /
HighZ /
VDDM
Analog input 15
VADCG1.7
VADC analog input channel 7 of group 1
W5
U5
W4
W3
AN16
D /
HighZ /
VDDM
Analog input 16
VADCG2.0
VADC analog input channel 0 of group 2
AN17
D /
HighZ /
VDDM
Analog input 17
VADCG2.1
VADC analog input channel 1 of group 2 (MD)
AN18
D /
HighZ /
VDDM
Analog input 18
VADCG2.2
VADC analog input channel 2 of group 2 (MD)
AN19
D /
Analog input 19
HighZ /
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
Y3
Y2
AN20
I
I
I
I
I
I
D /
HighZ /
VDDM
Analog input 20
VADCG2.4
DS2PA
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 2, pin A
Analog input 21
AN21
D /
HighZ /
VDDM
VADCG2.5
DS2NA
VADC analog input channel 5 of group 2
DSADC: negative analog input of channel
of DSADC 2, pin A
T5
AN22
I
D /
Analog input 22
HighZ /
VDDM
VADCG2.6
VADC analog input channel 6 of group 2
Data Sheet
129
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-36 Analog Inputs (cont’d)
Pin
R5
Symbol
AN23
Ctrl
Type
Function
I
D /
Analog input 23
HighZ /
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
W2
W1
AN24
I
I
S /
HighZ /
VDDM
Analog input 24
VADCG3.0
DS2PB
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
SENT input channel 0, pin A
SENT0A
AN25
S /
Analog input 24
HighZ /
VDDM
VADCG3.1
DS2NB
VADC analog input channel 1 of group 3 (MD)
DSADC: negative analog input of channel 2, pin B
SENT input channel 1, pin A
SENT1A
AN26
V2
V1
I
I
S /
HighZ /
VDDM
Analog input 26
VADCG3.2
SENT2A
AN27
VADC analog input channel 2 of group 3 (MD)
SENT input channel 2, pin A
S /
Analog input 27
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
SENT3A
AN28
SENT input channel 3, pin A
Analog input 28
U2
U1
T4
R4
P4
I
I
I
I
I
D /
HighZ /
VDDM
VADCG3.4
VADC analog input channel 4 of group 3
AN29
D /
HighZ /
VDDM
Analog input 29
VADCG3.5
VADC analog input channel 5 of group 3
AN30
D /
HighZ /
VDDM
Analog input 30
VADCG3.6
VADC analog input channel 6 of group 3
AN31
D /
HighZ /
VDDM
Analog input 31
VADCG3.7
VADC analog input channel 7 of group 3
AN32
S /
Analog input 32
HighZ /
VDDM
VADCG4.0
SENT4A
AN33
VADC analog input channel 0 of group 4
SENT input channel 4, pin A
Analog input 33
R1
P5
I
I
S /
HighZ /
VDDM
VADCG4.1
SENT5A
AN34
VADC analog input channel 1 of group 4 (MD)
SENT input channel 5, pin A
Analog input 34
D /
HighZ /
VDDM
VADCG4.2
VADC analog input channel 2 of group 4 (MD)
Data Sheet
130
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-36 Analog Inputs (cont’d)
Pin
R2
Symbol
AN35
Ctrl
Type
Function
I
D /
Analog input 35
HighZ /
VDDM
VADCG4.3
VADC analog input channel 3 of group 4 (with pull
down diagnostics)
N4
P2
N5
P1
AN36
I
I
I
I
S /
HighZ /
VDDM
Analog input 34
VADCG4.4
DS3PA
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel
of DSADC 3, pin A
SENT6A
AN37
SENT input channel 6, pin A
Analog input 37
S /
HighZ /
VDDM
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input of channel
of DSADC 3, pin A
SENT7A
AN38
SENT input channel 7, pin A
Analog input 38
S /
HighZ /
VDDM
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel
of DSADC 3, pin B
SENT8A
AN39
SENT input channel 8, pin A
Analog input 39
S /
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input of channel
of DSADC 3, pin B
SENT9A
AN40
SENT input channel 9, pin A
Analog input 40
M5
M4
L5
L4
I
I
I
I
D /
HighZ /
VDDM
VADCG5.0
VADC analog input channel 0 of group 5
AN41
D /
HighZ /
VDDM
Analog input 41
VADCG5.1
VADC analog input channel 1 of group 5 (MD)
AN42
D /
HighZ /
VDDM
Analog input 42
VADCG5.2
VADC analog input channel 2 of group 5 (MD)
AN43
D /
Analog input 43
HighZ /
VDDM
VADCG5.3
VADC analog input channel 3 of group 5 (with pull
down diagnostics)
N1
AN44
I
D /
Analog input 44
HighZ /
VDDM
VADCG5.4
DS3PC
VADC analog input channel 4 of group 5
DSADC: positive analog input of channel
of DSADC 3, pin C
Data Sheet
131
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-36 Analog Inputs (cont’d)
Pin
N2
Symbol
AN45
Ctrl
Type
Function
I
D /
Analog input 45
HighZ /
VDDM
VADCG5.5
DS3NC
VADC analog input channel 5 of group 5
DSADC: negative analog input of channel
of DSADC 3, pin C
M1
M2
AN46
I
I
D /
HighZ /
VDDM
Analog input 46
VADCG5.6
DS3PD
VADC analog input channel 6 of group 5
DSADC: positive analog input of channel
of DSADC 3, pin D
AN47
D /
Analog input 47
HighZ /
VDDM
VADCG5.7
DS3ND
VADC analog input channel 7 of group 5
DSADC: negative analog input of channel
of DSADC 3, pin D
Table 2-37 System I/O
Pin
Symbol
Ctrl
Type
Function
G17
PORST
I
I /
Power On Reset Input
PD /
VEXT
Additional strong PD in case of power fail.
F16
ESR0
I/O
MP /
OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished. See
also SCU chapter for details.
Default after power-on can be different. See also SCU
chapter ´Reset Control Unit´ and SCU_IOCR register
description.
EVRWUP
ESR1
I
EVR Wakeup Pin
G16
W17
I/O
MP / PU1 / External System Request Reset 1
VEXT
Default NMI function.
See also SCU chapter ´Reset Control Unit´ and
SCU_IOCR register description.
EVRWUP
VGATE1P
I
EVR Wakeup Pin
O
VGATE1P External Pass Device gate control for EVR13
/
- /
VEXT
K16
L19
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
TRST
I
A2 /
JTAG Module Reset/Enable Input
PD /
VDDP3
Data Sheet
132
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-37 System I/O (cont’d)
Pin
J16
Symbol
TCK
Ctrl
Type
Function
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
M20
M19
XTAL1
XTAL2
I
XTAL1 /
- /
VDDP3
Main Oscillator/PLL/Clock Generator Input
O
XTAL2 /
- /
Main Oscillator/PLL/Clock Generator Output
VDDP3
Table 2-38 Supply
Pin
Y6
Symbol
Ctrl
Type
Vx
Function
VAREF1
I
Positive Analog Reference Voltage 1
Y7
VAGND1
VAREF2
I
I
I
I
I
Vx
Vx
Vx
Vx
Vx
Negative Analog Reference Voltage 1
Positive Analog Reference Voltage 2
Negative Analog Reference Voltage 2
ADC Analog Power Supply (3.3V / 5V)
T1
T2
VAGND2
VDDM
Y5
G8, H7
VDD / VDDSB
Emulation Device: Emulation SRAM Standby Power
Supply (1.3V) (Emulation Device only).
Production Device: VDD (1.3V).
P8, P13,
N7, N14,
H14, G13
VDD
VDD
I
I
Vx
Vx
Digital Core Power Supply (1.3V)
N19
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (1.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
A2, B3,
V19, W20
VEXT
I
I
Vx
Vx
External Power Supply (5V / 3.3V)
B18, A19 VDDP3
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power Supply for
VFLEX.
N20
VDDP3
I
Vx
Digital Power Supply for Oscillator, LVDSH and A2
pads (3.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (3.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
Data Sheet
133
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-38 Supply (cont’d)
Pin Symbol
E15, D16 VDDFL3
Ctrl
Type
Vx
Function
I
Flash Power Supply (3.3V)
D5
VFLEX
VSSM
I
I
I
Vx
Vx
Vx
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
Y4
Analog Ground for VDDM
T11
VEVRSB
Standby Power Supply (3.3V/5V) for the Standby
SRAM (CPU0.DSPR).
If Standby mode is not used: To be handled like VEXT
(3.3V/5V).
B2, D4,
VSS
I
Vx
Digital Ground
E5, L20,
T16, U17,
W19, Y20
E16, D17, VSS
B19, A20
I
I
Vx
Vx
Digital Ground (outer balls)
Digital Ground (center balls)
P9, P12,
N9, N10,
N11, N12
VSS
VSS
VSS
VSS
VSS
M7, M8,
M10, M11,
M13, M14
I
I
I
I
I
Vx
Vx
Vx
Vx
Vx
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
L8, L9,
L10, L11,
L12, L13
K8, K9,
K10, K11,
K12, K13
J7, J8,
J10, J11,
J13, J14
H9, H10, VSS
H11, H12,
G9, G10,
G11, G12
P10
P11
L7
VSS
VSS
VSS
I
I
I
Vx
Vx
Vx
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT TX0N
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT TX0P
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT CLKN
Data Sheet
134
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
Table 2-38 Supply (cont’d)
Pin
K7
Symbol
Ctrl
Type
Vx
Function
VSS
I
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT CLKP
L14
K14
VSS
I
I
Vx
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT ERR
NC / VDDPSB
NCVDDP Emulation Device: Power Supply (3.3V) for DAP/JTAG
SB
pad group. Can be connected to VDDP or can be left
unsupplied (see document ´AurixED´ / Aurix Emulation
Devices specification).
Production Device:
This pin is not connected on package level. It can be
connected on PCB level to VDDP or Ground or can be
left unsupplied.
A1, Y1, U4 NC
I
NC
Not Connected.
These pins are not connected on package level and
will not be used for future extensions.
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP+ (5V/3.3V, LVTTL)
MPR = Pad class MPR (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSH (LVDS/CMOS 3.3V)
S = Pad class S (ADC overlayed with General Purpose Input)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
1)The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak
internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General
Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
Data Sheet
135
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
2.2.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during PORST active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
•
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
136
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC277x Pin Definition and Functions:
•
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
2.2.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-39 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2)Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
137
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
2.3
TC270x Bare Die Pad Definition
The TC270x Bare Die Logic Symbol is shown in Figure 2-3.
Table 2-40 describes the pads of the TC270x Bare Die. It describes also the mapping of VADC / DS-ADC
channels to the analog inputs (ANx) and the mapping of Port functions to the pads.
Note:The detailed description of the port functions (Px.y) can be found in the User’s Manual chapter “General
Purpose I/O Ports and Peripheral I/O LInes (Ports)“.
Pad 172
Pad 85
Pad 84
Pad 173
Y
0.0
X
Pad 1
Pad 255
Pad 332
Pad 256
Figure 2-3 TC270x Logic Symbol for the Bare Die.
Table 2-40 List of the TC270x Bare Die Pads
Number
Pad Name
P10.8
Pad Type
X
Y
Comment
GPIO
1
2
LP / PU1 / VEXT 3265500
-3460000
-3380000
P02.0
MP+ / PU1 /
VEXT
3374000
GPIO
3
4
5
6
7
P02.9
P02.1
VSS
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
-3300000
-3200000
-3125000
-3050000
-2950000
GPIO
GPIO
Vx
3374000
Must be bonded to VSS
P02.10
P02.2
LP / PU1 / VEXT 3265500
GPIO
GPIO
MP+ / PU1 /
VEXT
3374000
8
P02.11
VEXT
P02.3
LP / PU1 / VEXT 3265500
Vx 3374000
-2850000
-2775000
-2670000
GPIO
9
Must be bonded to VEXT
GPIO
10
LP / PU1 / VEXT 3265500
Data Sheet
138
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
11
P02.4
MP+ / PU1 /
VEXT
3265500
-2540000
GPIO
12
13
VSS
Vx
3374000
3265500
-2465000
-2390000
Must be bonded to VSS
GPIO
P02.5
MP+ / PU1 /
VEXT
14
15
16
17
18
19
20
21
22
P02.6
VEXT
P02.7
P02.8
VSS
MP / PU1 / VEXT 3374000
Vx 3374000
-2300000
-2195000
-2110000
-2040000
-1940000
-1883500
-1818500
-1688500
-1644500
GPIO
Must be bonded to VEXT
GPIO
MP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3374000
GPIO
Vx
3374000
Must be bonded to VSS
GPIO
P01.3
VDD
LP / PU1 / VEXT 3265500
Vx
Vx
Vx
3374000
3374000
3374000
Must be bonded to VDD
Must be bonded to VSS
VSS
VSS
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
22.
23
VDD
Vx
3374000
-1514500
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
21.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
P01.4
VSS
LP / PU1 / VEXT 3265500
Vx 3374000
-1449500
-1394500
-1339500
-1239500
-1139500
-1068500
-968500
-868500
-241000
-141000
-41000
GPIO
Must be bonded to VSS
P01.5
P01.6
P01.7
VEXT
VSS
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
GPIO
GPIO
GPIO
Vx
Vx
3374000
3374000
Must be bonded to VEXT
Must be bonded to VSS
P00.0
P00.1
P00.2
P00.3
VSS
MP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
GPIO
GPIO
GPIO
GPIO
Vx
3374000
19000
Must be bonded to VSS
P00.4
P00.5
P00.6
VEXT
P00.7
P00.8
P00.9
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3265500
79000
GPIO
179000
279000
339000
399000
459000
549000
GPIO
GPIO
Vx
3374000
Must be bonded to VEXT
LP / PU1 / VEXT 3265500
LP / PU1 / VEXT 3374000
LP / PU1 / VEXT 3265500
GPIO
GPIO
GPIO
Data Sheet
139
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
43
Pad Name
P00.10
P00.11
VSS
Pad Type
X
Y
Comment
LP / PU1 / VEXT 3374000
LP / PU1 / VEXT 3265500
609000
689000
749000
809000
864000
964000
1064000
1164000
1239000
1299000
1419000
GPIO
44
GPIO
45
Vx
3374000
Must be bonded to VSS
GPIO
46
P00.12
VDD
LP / PU1 / VEXT 3265500
47
Vx
Vx
Vx
Vx
Vx
Vx
Vx
3374000
3374000
3374000
3374000
3265500
3374000
3374000
Must be bonded to VDD
Must be bonded to VSS
Must be bonded to VSS
Must be bonded to VDD
Must be bonded to VEXT
Must be bonded to VSS
48
VSS
49
VSS
50
VDD
51
VEXT
VSS
52
53
VAREF3
Positive Analog Reference
Voltage 3
54
55
56
VAREF2
VAGND3
VAGND2
VDDM
Vx
Vx
Vx
Vx
3265500
3374000
3265500
1479000
1539000
1599000
Positive Analog Reference
Voltage 2
NegativeAnalog Reference
Voltage 3
NegativeAnalog Reference
Voltage 2
57
58
3374000
3265500
1659000
1719000
Must be bonded to VEXT
Analog input
AN47(VADC5.7/ D
DS3ND)
59
60
61
62
AN46(VADC5.6/ D
DS3PD)
3374000
3265500
3374000
3265500
1779000
1839000
1899000
1959000
Analog input
Analog input
Analog input
AN45(VADC5.5/ D
DS3NC)
AN44(VADC5.4/ D
DS3PC)
AN43 (VADC5.3) D
Analog input (with pull
down diagnostics)
63
64
65
66
AN42 (VADC5.2) D
AN41 (VADC5.1) D
AN40 (VADC5.0) D
3374000
3265500
3374000
3265500
2019000
2079000
2139000
2199000
Analog input
Analog input
Analog input
AN39(VADC4.7/ S
DS3NB), P40.9 (
SENT9A)
Analog input, GPI (SENT)
67
68
AN38(VADC4.6/ S
DS3PB), P40.8 (
SENT8A)
3374000
3265500
2259000
2319000
Analog input, GPI (SENT)
Analog input, GPI (SENT)
AN37(VADC4.5/ S
DS3NA), P40.7 (
SENT7A)
Data Sheet
140
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
69
Pad Name
Pad Type
X
Y
Comment
VDDM
Vx
3374000
3265500
2379000
2439000
Must be bonded to VEXT
Analog input, GPI (SENT)
70
AN36(VADC4.4/ S
DS3PA), P40.6 (
SENT6A)
71
72
VSSM
Vx
3374000
3265500
2499000
2559000
Must be bonded to VSS
AN35 (VADC4.3) D
Analog input (with pull
down diagnostics)
73
74
AN34 (VADC4.2) D
3374000
3265500
2619000
2679000
Analog input
AN33
S
Analog input, GPI (SENT)
(VADC4.1),
P40.5 ( SENT5A)
75
AN32
S
3374000
2765000
Analog input, GPI (SENT)
(VADC4.0),
P40.4 ( SENT4A)
76
77
78
79
80
AN31 (VADC3.7) D
AN30 (VADC3.6) D
AN29 (VADC3.5) D
AN28 (VADC3.4) D
3265500
3374000
3265500
3374000
3265500
2825000
2885000
2945000
3045000
3105000
Analog input
Analog input
Analog input
GPIO
AN27
S
Analog input (with pull
down diagnostics), GPI
(SENT)
(VADC3.3),
P40.3 ( SENT3A)
81
82
83
AN26
(VADC3.2),
P40.2 ( SENT2A)
S
3265500
3265500
3265500
3205000
3305000
3405000
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
AN25(VADC3.1/ S
DS2NB), P40.1 (
SENT1A)
AN24(VADC3.0/ S
DS2PB), P40.0 (
SENT0A)
84
85
86
87
88
VDDM
VSSM
Vx
Vx
3374000
3134000
3074000
3014000
2954000
3465000
3705000
3596500
3705000
3596500
Must be bonded to VEXT
Must be bonded to VSS
Analog input
AN23 (VADC2.7) D
AN22 (VADC2.6) D
Analog input
AN21(VADC2.5/ D
DS2NA)
Analog input
89
90
AN20(VADC2.4/ D
DS2PA)
2854000
2754000
3596500
3596500
Analog input
AN19 (VADC2.3) D
Analog input (with pull
down diagnostics)
91
92
AN18 (VADC2.2) D
AN17 (VADC2.1) D
2654000
2554000
3596500
3596500
Analog input
Analog input
Data Sheet
141
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
93
Pad Name
Pad Type
X
Y
Comment
AN16 (VADC2.0) D
AN15 (VADC1.7) D
2494000
2434000
2374000
3705000
3596500
3705000
Analog input
Analog input
94
95
VAGND1
VAGND0
VAREF1
VAREF0
Vx
NegativeAnalog Reference
Voltage 1
96
97
98
Vx
Vx
Vx
2314000
2254000
2194000
3596500
3705000
3596500
NegativeAnalog Reference
Voltage 0
Positive Analog Reference
Voltage 1
Positive Analog Reference
Voltage 0
99
VSSM
Vx
Vx
Vx
2134000
2074000
2014000
1954000
1894000
1829000
1724000
1664000
1604000
3705000
3596500
3705000
3596500
3705000
3596500
3596500
3705000
3596500
Must be bonded to VSS
Must be bonded to VSS
Must be bonded to VSS
Analog input
100
101
102
103
104
105
106
107
VSSM
VSSMREF
AN14 (VADC1.6) D
VDDM
VDDM
Vx
Vx
Must be bonded to VEXT
Must be bonded to VEXT
Analog input
AN13 (VADC1.5) D
AN12 (VADC1.4) D
AN11 (VADC1.3) D
Analog input
Analog input (with pull
down diagnostics)
108
109
110
111
AN10 (VADC1.2) D
1544000
1484000
1424000
1364000
3705000
3569500
3705000
3596500
Analog input
Analog input
Analog input
AN9 (VADC1.1)
AN8 (VADC1.0)
AN7 (VADC0.7)
D
D
D
Analog input (with pull
down diagnostics)
112
113
114
115
AN6 (VADC0.6)
AN5 (VADC0.5)
AN4 (VADC0.4)
D
D
D
D
1304000
1244000
1184000
1124000
3705000
3596500
3705000
3596500
Analog input
Analog input
Analog input
Analog input
AN3 (VADC0.3 /
DS0NA)
116
117
VSSM
Vx
D
1064000
1004000
3705000
3596500
Must be bonded to VSS
Analog input
AN2 (VADC0.2 /
DS0PA)
118
119
VDDM
Vx
D
944000
884000
3705000
3596500
Must be bonded to VEXT
Analog input
AN1 (VADC0.1 /
DS1NA)
120
AN0 (VADC0.0 /
DS1PA)
D
807000
3705000
Analog input
121
122
VEXT
VSS
Vx
Vx
427000
377000
3596500
3705000
Must be bonded to VEXT
Must be bonded to VSS
Data Sheet
142
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
123
Pad Name
P34.1
VSS
Pad Type
LP / PU1 / VEXT 322000
Vx 267000
X
Y
Comment
3596500
3705000
3596500
3705000
3596500
3705000
3596500
3705000
3705000
3705000
GPIO
124
Must be bonded to VSS
GPIO
125
P34.2
P34.3
VEXT
P34.4
P34.5
VSS
LP / PU1 / VEXT 212000
LP / PU1 / VEXT 142000
126
GPIO
127
Vx
87000
Must be bonded to VEXT
GPIO
128
LP / PU1 / VEXT 22000
LP / PU1 / VEXT -38000
129
GPIO
130
Vx
Vx
Vx
-93000
Must be bonded to VSS
Must be bonded to VDD
131
VDD
-193000
-323000
132
VSS
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
131.
133
VSS
Vx
-363000
3705000
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
130.
134
135
136
VDD
Vx
Vx
Vx
-493000
-560000
-625000
3705000
3596500
3705000
Must be bonded to VDD
Must be bonded to VEXT
VEVRSB
EVR_OFF
Must be bonded to
VSS+F178
137
138
139
140
141
142
143
144
145
146
147
VEXT
P33.0
P33.1
P33.2
P33.3
P33.4
VSS
Vx
-725000
3705000
3596500
3705000
3596500
3705000
3596500
3705000
3596500
3705000
3596500
3705000
Must be bonded to VEXT
LP / PU1 / VEXT -790000
LP / PU1 / VEXT -855000
LP / PU1 / VEXT -915000
LP / PU1 / VEXT -985000
LP / PU1 / VEXT -1045000
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
-1100000
Must be bonded to VSS
P33.5
P33.6
P33.7
P33.8
LP / PU1 / VEXT -1155000
LP / PU1 / VEXT -1250000
LP / PU1 / VEXT -1310000
GPIO
GPIO
GPIO
GPIO
MP / HighZ /
VEXT
-1420000
148
149
150
151
152
153
154
P33.9
LP / PU1 / VEXT -1490000
Vx -1545000
3596500
3705000
3596500
3705000
3596500
3705000
3596500
GPIO
VEXT
Must be bonded to VEXT
P33.10
P33.14
P33.11
P33.15
P33.12
MP / PU1 / VEXT -1610000
LP / PU1 / VEXT -1680000
MP / PU1 / VEXT -1750000
LP / PU1 / VEXT -1820000
MP / PU1 / VEXT -1890000
GPIO
GPIO
GPIO
GPIO
GPIO
Data Sheet
143
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
155
Pad Name
VSS
Pad Type
X
Y
Comment
Vx
-1955000
3705000
3596500
3705000
3705000
3596500
Must be bonded to VSS
GPIO
156
P33.13
VSS
MP / PU1 / VEXT -2040000
157
Vx
Vx
-2105000
-2205000
-2260000
Must be bonded to VSS
Must be bonded to VDD
GPIO
158
VDD
159
P32.0
LP / EVR13
SMPS -> PD,
GPIO -> PU1 /
VEXT
160
161
VGATE1N
(SMPS)
VGATE1N
-2315000
-2365000
3705000
3596500
Must be bonded to VSS if
EVR13 SMPS is not used.
Must be bonded to NMOS
gate if EVR13 SMPS used.
VGATE1P
(SMPS)
VGATE1P
Must be bonded to VEXT if
EVR13 SMPS is not used.
Must be bonded to PMOS
gate if EVR13 SMPS used.
162
163
VGATE3P (LDO) VGATE3P
VGATE1P (LDO) VGATE1P
-2415000
-2465000
3705000
3596500
Must be bonded to VSS
Must be bonded to VSS if
no external P channel
MOSFET used for EVR13
LDO generation. Must be
bonded to external P
channnel MOSFET if
external LDO pass device
used.
164
165
166
167
168
169
170
VEXT
P32.2
P32.3
P32.6
P32.5
VSS
Vx
-2515000
3705000
3596500
3596500
3705000
3596500
3705000
3596500
Must be bonded to VEXT
LP / PU1 / VEXT -2570000
LP / PU1 / VEXT -2714000
LP / PU1 / VEXT -2774000
LP / PU1 / VEXT -2849000
GPIO
GPIO
GPIO
GPIO
Vx
-2904000
-2989000
Must be bonded to VSS
GPIO
P32.4
MP+ / PU1 /
VEXT
171
172
173
174
P32.7
P23.0
VSS
LP / PU1 / VEXT -3069000
LP / PU1 / VEXT -3129000
3705000
3596500
3391000
3316000
GPIO
GPIO
Vx
-3374000
-3265500
Must be bonded to VSS
GPIO
P23.1
MP+ / PU1 /
VEXT
175
176
177
P23.2
P23.3
P23.4
LP / PU1 / VEXT -3374000
LP / PU1 / VEXT -3265500
3236000
3125000
3045000
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
-3374000
Data Sheet
144
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
178
Pad Name
P23.6
Pad Type
X
Y
Comment
LP / PU1 / VEXT -3265500
2965000
2910000
2835000
GPIO
179
VEXT
Vx
-3374000
-3265500
Must be bonded to VEXT
GPIO
180
P23.5
MP+ / PU1 /
VEXT
181
182
P23.7
P22.0
LP / PU1 / VEXT -3374000
2755000
2685000
GPIO
GPIO
MP / LVDSM_N/ -3265500
PU1 / VEXT
183
P22.1
MP / LVDS_P / -3265500
PU1 / VEXT
2335000
GPIO
184
185
VSS
Vx
-3374000
2270000
2205000
Must be bonded to VSS
GPIO
P22.2
MP / LVDSM_N/ -3265500
PU1 / VEXT
186
P22.3
MP / LVDS_P / -3265500
PU1 / VEXT
1855000
GPIO
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
VEXT
VEXT
Reserved
VDD
Vx
Vx
Vx
Vx
Vx
-3374000
-3265500
-3374000
-3374000
-3374000
1790000
1735000
1680000
1580000
1480000
1425000
1370000
1270000
1215000
1155000
1095000
1040000
940000
885000
825000
765000
710000
655000
520000
420000
312500
Must be bonded to VEXT
Must be bonded to VEXT
Must be bonded to VSS
Must be bonded to VDD
Must be bonded to VSS
GPIO
VSS
P22.4
VSS
LP / PU1 / VEXT -3265500
Vx
Vx
-3374000
-3374000
Must be bonded to VSS
Must be bonded to VDD
GPIO
VDD
P22.5
P22.6
P22.7
VSS
LP / PU1 / VEXT -3265500
LP / PU1 / VEXT -3374000
LP / PU1 / VEXT -3265500
GPIO
GPIO
Vx
Vx
-3374000
-3374000
Must be bonded to VSS
Must be bonded to VDD
GPIO
VDD
P22.8
P22.9
P22.10
VSS
LP / PU1 / VEXT -3265500
LP / PU1 / VEXT -3374000
LP / PU1 / VEXT -3265500
GPIO
GPIO
Vx
-3374000
Must be bonded to VSS
GPIO
P22.11
VDDOSC
VSSOSC
XTAL1
LP / PU1 / VEXT -3265500
Vx
-3374000
-3374000
-3265500
Must be bonded to VDD
Must be bonded to VSS
Vx
XTAL1
Main Oscillator/PLL/Clock
Generator Input. Must be
bonded to external quartz
or resonator
Data Sheet
145
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
208
XTAL2
XTAL2
-3265500
212500
Main Oscillator/PLL/Clock
Generator Input. Must be
bonded to external quartz
or resonator
209
210
211
212
213
214
VSSOSC3
VDDOSC3
VDDP3
VDDP3
VSS
Vx
Vx
Vx
Vx
Vx
-3374000
-3265500
-3374000
-3265500
-3374000
-3374000
105000
55000
Must be bonded to VSS
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VSS
GPIO
-35000
-95000
-145000
-245000
P21.0
A2 / PU1 /
VDDP3
215
P21.1
A2 / PU1 /
VDDP3
-3265500
-3374000
-345000
GPIO
216
217
VSS
Vx
-395000
-457500
Must be bonded to VSS
GPIO
P21.2
LVDSH_N / PU1 -3265500
/ VDDP3
218
P21.3
LVDSH_P / PU1 -3265500
/ VDDP3
-557500
GPIO
219
220
VDDP3
P21.4
Vx
-3374000
-620000
-694500
Must be bonded to VDDP3
GPIO
LVDSH_N / PU1 -3265500
/ VDDP3
221
P21.5
LVDSH_P / PU1 -3265500
/ VDDP3
-845500
GPIO
222
223
224
225
226
227
VDD
Vx
Vx
-3374000
-3374000
-920000
Must be bonded to VDD
Must be bonded to VSS
GPIO, TDI
VSS
-1020000
-1070000
-1120000
-1345000
-1395000
P21.6
A2 / PU / VDDP3 -3265500
VDDP3
VSS
Vx
Vx
-3374000
-3374000
Must be bonded to VDDP3
Must be bonded to VSS
TMS / DAP1
A2 / PD / VDDP3 -3265500
JTAG Module State
Machine Control Input /
Device Access Port Line 1
228
229
P21.7
A2 / PU / VDDP3 -3374000
A2 / PU / VDDP3 -3265500
-1445000
-1535000
GPIO, TDO
TRST (N)
JTAG Module
Reset/Enable Input
230
TCK / DAP0
A2 / PU / VDDP3 -3374000
-1585000
JTAG Module Clock Input /
Device Access Port Line 0
231
232
233
P20.0
P20.1
P20.2
MP / PU1 / VEXT -3265500
LP / PU1 / VEXT -3374000
LP / PU / VEXT -3265500
-1720000
-1790000
-1845000
GPIO
GPIO
Testmode pin must be
bonded
234
VSS
Vx
-3374000
146
-1895000
Must be bonded to VSS
Data Sheet
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
235
Pad Name
Pad Type
X
Y
Comment
P20.3
LP / PU1 / VEXT -3265500
MP / PU1 / VEXT -3374000
-1950000
-2020000
GPIO
236
ESR1 (N) /
EVRWUP
External System Request
Reset 1. Default NMI
function. EVR Wakeup Pin.
237
PORST (N)
I / PD1 / VEXT
-3265500
-2102500
Power On Reset Input.
Additional strong PD in
case of power fail.
238
239
VEXT
Vx
-3374000
-3265500
-2170000
-2235000
Must be bonded to VEXT
ESR0 (N) /
EVRWUP
MP / OD
External System Request
Reset 0. Default
configuration during and
after reset is open-drain
driver. The driver drives low
during power-on reset. EVR
Wakeup Pin.
240
241
VDD
VSS
Vx
Vx
-3374000
-3374000
-2310000
-2440000
Must be bonded to VDD
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
240.
242
VSS
Vx
-3374000
-2480000
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
239.
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
VDD
Vx
-3374000
-2610000
-2665000
-2720000
-2775000
-2865000
-2935000
-2990000
-3055000
-3155000
-3235000
-3300000
-3365000
-3465000
-3596500
-3596500
-3705000
-3705000
-3596500
Must be bonded to VDD
P20.6
VSS
LP / PU1 / VEXT -3265500
Vx -3374000
GPIO
Must be bonded to VSS
P20.7
P20.8
P20.9
VEXT
P20.10
P20.11
P20.12
VSS
LP / PU1 / VEXT -3265500
MP / PU1 / VEXT -3374000
LP / PU1 / VEXT -3265500
GPIO
GPIO
GPIO
Vx
-3374000
Must be bonded to VEXT
MP / PU1 / VEXT -3265500
MP / PU1 / VEXT -3374000
MP / PU1 / VEXT -3265500
GPIO
GPIO
GPIO
Vx
-3374000
Must be bonded to VSS
P20.13
P20.14
P15.0
P15.1
P15.2
P15.3
VEXT
MP / PU1 / VEXT -3265500
MP / PU1 / VEXT -3265500
LP / PU1 / VEXT -3134000
LP / PU1 / VEXT -3034000
MP / PU1 / VEXT -2964000
MP / PU1 / VEXT -2864000
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
-2799000
Must be bonded to VEXT
Data Sheet
147
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
261
Pad Name
P15.4
P15.5
P15.6
VSS
Pad Type
X
Y
Comment
MP / PU1 / VEXT -2734000
MP / PU1 / VEXT -2634000
MP / PU1 / VEXT -2522000
-3705000
-3705000
-3596500
-3705000
-3596500
-3705000
-3596500
GPIO
262
GPIO
263
GPIO
264
Vx
-2457000
Must be bonded to VSS
265
P15.7
P15.8
P14.0
MP / PU1 / VEXT -2392000
MP / PU1 / VEXT -2312000
GPIO
GPIO
GPIO
266
267
MP+ / PU1 /
VEXT
-2222000
268
269
270
P14.1
VEXT
P14.2
MP / PU1 / VEXT -2122000
Vx -2057000
-3596500
-3705000
-3596500
GPIO
Must be bonded to VEXT
LP / PU1 / VEXT -2002000
Must be bonded to VEXT if
EVR13 active. Must be
bonded to VSS if EVR13
inactive.
271
272
273
274
P14.3
P14.4
VSS
LP / PU1 / VEXT -1942000
LP / PU1 / VEXT -1872000
-3705000
-3596500
-3705000
-3596500
GPIO
GPIO
Vx
-1817000
-1742000
Must be bonded to VSS
GPIO
P14.5
MP+ / PU1 /
VEXT
275
P14.6
MP+ / PU1 /
VEXT
-1642000
-3705000
GPIO
276
277
278
P14.7
P14.8
P14.9
LP / PU1 / VEXT -1562000
LP / PU1 / VEXT -1502000
-3596500
-3705000
-3596500
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
-1422000
279
P14.10
MP+ / PU1 /
VEXT
-1322000
-3596500
GPIO
280
281
282
283
284
Reserved
VEXT
VSS
Vx
Vx
Vx
Vx
Vx
-1247000
-1197000
-1147000
-1097000
-1017000
-3705000
-3596500
-3705000
-3596500
-3705000
Must be bonded to VSS
Must be bonded to VEXT
Must be bonded to VSS
Must be bonded to VEXT
VEXT
VSS
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
284.
285
286
VDDP3
VSS
Vx
Vx
-994500
-972000
-3596500
-3705000
Must be bonded to VDDP3
Must be bonded to VSS.
Double Pad (Elephant
Pad), shared with Pad Nr
282.
287
VDDP3
Vx
-877000
148
-3596500
Must be bonded to VDDP3
Data Sheet
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
288
Pad Name
VDDFL3
VDDFL3
VDDFL3
VSS
Pad Type
X
Y
Comment
Vx
Vx
Vx
Vx
-777000
-697000
-629500
-577000
-3596500
-3705000
-3596500
-3705000
-3596500
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VSS
GPIO
289
290
291
292
P13.0
MP / LVDSM_N/ -512000
PU1 / VEXT
293
P13.1
MP / LVDS_P / -162000
PU1 / VEXT
-3596500
GPIO
294
295
VEXT
P13.2
Vx
-97000
-3705000
-3596500
Must be bonded to VEXT
GPIO
MP / LVDSM_N/ -32000
PU1 / VEXT
296
297
298
299
P13.3
P12.0
P12.1
P11.0
MP / LVDS_P / 318000
PU1 / VEXT
-3596500
-3596500
-3705000
-3596500
GPIO
GPIO
GPIO
GPIO
LP / PU1 /
VFLEX
458000
518000
598000
LP / PU1 /
VFLEX
MP+ / PU1 /
VFLEX
300
301
VSSFLEX
P11.1
Vx
673000
748000
-3705000
-3596500
Must be bonded to VSS
GPIO
MP+ / PU1 /
VFLEX
302
303
304
305
306
307
308
309
310
311
VFLEX
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P11.9
P11.8
VSSFLEX
Vx
823000
-3705000
-3596500
-3596500
-3705000
-3596500
-3705000
-3596500
-3705000
-3596500
-3705000
Must be bonded to VEXT or
VDDP3
MPR / PU1 /
VFLEX
898000
GPIO
MPR / PU1 /
VFLEX
998000
GPIO
MP+ / PU1 /
VFLEX
1098000
1178000
1258000
1338000
1418000
1498000
1553000
GPIO
LP / PU1 /
VFLEX
GPIO
MPR / PU1 /
VFLEX
GPIO
LP / PU1 /
VFLEX
GPIO
MP+ / PU1 /
VFLEX
GPIO
LP / PU1 /
VFLEX
GPIO
Vx
Must be bonded to VSS
Data Sheet
149
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
Table 2-40 List of the TC270x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
312
VFLEX
Vx
1603000
-3596500
Must be bonded to VEXT or
VDDP3
313
314
P11.10
P11.13
LP / PU1 /
VFLEX
1698000
1758000
-3705000
-3596500
GPIO
LP / PU1 /
VFLEX
GPIO
315
316
VSSFLEX
P11.11
Vx
1813000
1888000
-3705000
-3596500
Must be bonded to VSS
GPIO
MP+ / PU1 /
VFLEX
317
318
319
P11.12
P11.14
P11.15
MPR / PU1 /
VFLEX
1988000
2068000
2128000
-3596500
-3705000
-3596500
GPIO
GPIO
GPIO
LP / PU1 /
VFLEX
LP / PU1 /
VFLEX
320
321
322
323
324
VDD
VSS
Vx
Vx
Vx
2183000
2283000
2403000
-3705000
-3705000
-3705000
-3596500
-3705000
Must be bonded to VDD
Must be bonded to VSS
Must be bonded to VSS
GPIO
VSS
P10.0
P10.1
LP / PU1 / VEXT 2458000
MP+ / PU1 /
VEXT
2543000
GPIO
325
326
327
P10.2
P10.3
P10.4
MP / PU1 / VEXT 2643000
MP / PU1 / VEXT 2723000
-3705000
-3596500
-3705000
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
2834000
328
329
330
331
332
VEXT
P10.5
P10.6
VSS
Vx
2909000
-3596500
-3705000
-3596500
-3705000
-3596500
Must be bonded to VEXT
LP / PU1 / VEXT 2964000
LP / PU1 / VEXT 3024000
GPIO
GPIO
Vx
3079000
Must be bonded to VSS
GPIO
P10.7
LP / PU1 / VEXT 3134000
Legend:
Column “Number”:
Running number of pads in the pad frame
Column “Name”:
Symbolic name of the pad.
The functions mapped on GPIO pads “Px.y” are described in the User’s Manual chapter ”General Purpose I/O
Ports and Peripheral I/O LInes (Ports)”
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP+ (5V/3.3V, LVTTL)
Data Sheet
150
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
MPR = Pad class MPR (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSH (LVDS/CMOS 3.3V)
S = Pad class S (ADC overlayed with General Purpose Input)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
Column “X” / “Y”:
Pad opening center coordinates (in nm)
2.3.1
Pad Openings
Two different pad openings are used:
•
•
Standard Pad Opening is 70um x 75um where 70um is the width of the opening (width as seen from the die
side) and 75um is the depth of the opening (from the die side into the silicon).
Double Pad or Elephant Pad Opening is 130um x 75um where 130um is the width of the opening (width as
seen from the die side) and 75um is the depth of the opening (from the die side into the silicon). The Double
Pad openings are represented with two opening coordinates and two pad numbers. Double Pads are used only
for supply and can be identified by the words ´Double Pad´ or ´Elephant Pad´ in the Comment column.
2.3.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
1)The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak
internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General
Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups are active at GPIOs (Px.y) pins during
and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input
funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality).
3) If HWCFG[6] is connected to ground, port pins are predominantly in HighZ during and after reset. Exceptions are P33.8
(HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7
(port pins overlayed with JTAG functionality).
Data Sheet
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TC270 / TC275 / TC277 DC-Step
Package and Pinning DefinitionsTC270x Bare Die Pad Definition
•
•
Input state and
PU or HighZ depending on HWCFG[6] level latched during PORST active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
•
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
2.3.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-41 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
•
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In
case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
152
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationParameter Interpretation
3
Electrical Specification
3.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC270 / TC275 / TC277 and partly
its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they
are marked with an two-letter abbreviation in column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of the TC270 / TC275 /
TC277 and must be regarded for a system design.
•
SR
Such parameters indicate System Requirements which must provided by the microcontroller system in which
the TC270 / TC275 / TC277 designed in.
Data Sheet
153
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationAbsolute Maximum Ratings
3.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3-1 Absolute Maximum Ratings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Storage Temperature
T
ST SR
-65
-
170
°C
upto 65h @ TJ =
150°C; upto 15h @ TJ
= 170°C
Voltage at VDD power supply
pins with respect to VSS
V
V
DD SR
-
-
-
-
1.9
V
V
1)
Voltage at VDDP3 and VDDFL3
DDP3 SR
4.43
power supply pins with respect
1)
to VSS
Voltage at VDDM, VEXT and
V
DDM SR
-
-
-
7.0
V
V
V
FLEX power supply pins with
1)
respect to VSS
Voltage on any class A2 and
LVDSH input pin with respect
VIN SR
-0.5
min(
VDDP3
0.6 , 4.23
Whatever is lower
+
1)2)
to VSS
)
Voltage on all other input pins VIN SR
with respect to VSS
-0.5
-10
-
-
-
7.0
10
V
1)2)
Input current on any pin during IIN SR
mA
mA
overload condition 3)
Absolute maximum sum of all ΣIIN SR
input circuit currents during
overload condition 3)
-100
100
1) Valid for cumulated for up to 2.8h and pulse forms following a power supply switch on phase, where the rise and fall times
are releated to the system capacities and coils.
2) Voltages below VINmin have no Impact to the device reliabiltiy as Long as the times and currents defined in section Pin
Reliability in Overload for the affected pad(s) are not violated.
3) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may
damage the device.
Data Sheet
154
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPin Reliability in Overload
3.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience overload currents and
voltages that go beyond their own IO power supplies specification.
The following table defines overload conditions that will not cause any negative reliability impact if all the following
conditions are met:
•
•
full operation life-time is not exceeded
Operating Conditions are met for
–
–
pad supply levels
temperature
If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters
functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still
possible in most cases but with relaxed parameters.
Note:An overload condition on one or more pins does not require a reset.
Table 3-2 Overload Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-5
-15 1)
Max.
5
15 1)
Input current on any digital pin IIN
during overload condition
-
-
mA
mA
except LVDS pins
except LVDS pins;
limited to max. 20
pulses with 1ms pulse
length
Input current on LVDS pin
during overload condition
IINLVDS
-3
-
-
3
mA
mA
Absolute maximum sum of all IING
input circuit currents during
overload condition
-50
50
Input current on analog input
pin during overload condition
IINANA
-3
-5
-
-
3
5
mA
mA
limited to 60h over
lifetime
Absolute sum of all ADC inputs IINSCA
during overload condition
-20
-
-
20
mA
mA
Absolute maximum sum of all ΣIINS
input circuit currents during
overload condition
-100
100
Signal voltage over/undershoot VOUS
at GPIOs
V
SS - 2
-
VEXT/FLEX
+ 2
V
limited to 60h over
lifetime; Valid for LP,
MP, MP+, and MPR
pads
Inactive device pin current
during overload condtion 2)
IID
-1
-
-
1
mA
mA
All power supply
voltages VDDx = 0
Sum of all inactive device pin IIDS
-100
100
currents 2)
Data Sheet
155
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
digital inputs, negative 3)
KOVDN CC
-
2*10-4
6*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
LP and A2 pads; -2mA
< IIN < 0mA
-
-
-
-
1*10-2
Overload injected on
GPIO non LVDS pad
and affecting neighbor
LP and A2 pads; -5mA
< IIN < -2mA
1.7*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
MP, MP+, and MPR
pads; -2mA < IIN <
0mA
-
-
-
-
2*10-2
Overload injected on
GPIO non LVDS pad
and affecting neighbor
MP, MP+, and MPR
pads; -5mA < IIN < -
2mA
0.3
Overload injected on
LVDS pad and
affecting neighbor
LVDS pads
-
-
-
-
0.93
couplingbetweenpads
21.2 and 21.3
Overload coupling factor for
digital inputs, positive 3)
KOVDP CC
1*10-5
Overload injected on
GPIO non LVDS pad
and affecting neighbor
GPIO non LVDS pads
-
-
-
-
1*10-4
5*10-4
Overload injected on
GPIO pad and
affecting neighbor
P32.0 pad
Overload injected on
LVDS pad and
affecting neighbor
LVDS pads
Data Sheet
156
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
analog inputs, negative
KOVAN CC
-
-
6*10-4 4)
Analog Inputs overlaid
with class LP pads or
pull down diagnostics;
-1mA < IIN < 0mA
-
-
1*10-2
Analog Inputs overlaid
with class LP pads or
pull down diagnostics;
-5mA < IIN < -1mA
-
-
-
-
1*10-4
1*10-5
else; -5mA < IIN < 0mA
5mA < IIN < 0mA
Overload coupling factor for
analog inputs, positive
KOVAP CC
1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters.
2) Limitations for time and supply levels specified in this section are not valid for this parameter.
3) Overload is measured as increase of pad leakage caused by injection on neighbor pad.
4) For analogue inputs overlaid with DSADC function the VCM holdbuffer shall be enabled, in case DSADCs are enabled.
Note:DSADC input pins count as analog pins as they are overlaid with VADC pins.
Table 3-3 PN-Junction Characteristics for positive Overload
Pad Type
IIN = 3 mA
IIN = 5 mA
F / A2
UIN = VDDP3 + 0.5 V
UIN = VEXT / FLEX + 0.75 V
UIN = VEXT + 0.75 V
UIN = VDDP3 + 0.5 V
UIN = VDDM + 0.75 V
UIN = VDDP3 + 0.6 V
LP / MP / MP+ / MPR
UIN = VEXT / FLEX + 0.8 V
LVDSM
LVDSH
D
-
-
-
Table 3-4 PN-Junction Characteristics for negative Overload
Pad Type
IIN = -3 mA
IIN = -5 mA
F / A2
UIN = VSS - 0.5 V
UIN = VSS - 0.75 V
UIN = VSS - 0.75 V
UIN = VSS - 0.5 V
UIN = VSS - 0.75 V
UIN = VSS - 0.6 V
LP / MP / MP+ / MPR
UIN = VSS - 0.8 V
LVDSM
LVDSH
D
-
-
-
Data Sheet
157
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationOperating Conditions
3.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the
TC270 / TC275 / TC277. All parameters specified in the following tables refer to these operating conditions, unless
otherwise noticed.
Digital supply voltages applied to the TC270 / TC275 / TC277 must be static regulated voltages.
All parameters specified in the following tables refer to these operating conditions (see table below), unless
otherwise noticed in the Note / Test Condition column.
Table 3-5 Operating Conditions
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
200
200
200
200
200
200
400
100
200
100
200
100
200
100
100
100
80
SRI frequency
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SRI SR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mA
Max System Frequency
CPU0 Frequency
CPU1 Frequency
CPU2 Frequency
PLL output frequency
PLL_ERAY output frequency
SPB frequency
MAX SR
CPU0 SR
CPU1 SR
CPU2 SR
PLL SR
-
-
-
-
20
PLLERAY SR 20
SPB SR
-
-
-
-
-
-
-
-
-
-
-
-
-
ASCLIN fast frequency
ASCLIN slow frequency
Baud2 frequency
Baud1 frequency
FSI2 frequency
ASCLINF SR
ASCLINS SR
BAUD2 SR
BAUD1 SR
FSI2 SR
FSI frequency
FSI SR
GTM frequency
GTM SR
STM SR
STM frequency
ERAY frequency
BBB frequency
ERAY SR
BBB SR
100
100
100
MultiCAN frequency
CAN SR
Absolute sum of short circuit
currents of the device
ΣISC_D SR
Ambient Temperature
TA SR
-40
-40
-40
-
-
-
125
150
170
°C
°C
°C
valid for all SAK
products
valid for all SAL
products
valid for all SAL
products without
package
Junction Temperature
TJ SR
-40
-40
-
-
150
170
°C
°C
valid for all SAK
products
valid for all SAL
products
Data Sheet
158
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationOperating Conditions
Table 3-5 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Core Supply Voltage 1)
V
DD SR
1.17
1.3
1.43 2)
V
Only required if
externally supplied
ADC analog supply voltage
V
V
DDM SR
EXT SR
2.97
2.97
5.0
-
5.5 3)
4.5
V
V
Digital external supply voltage
for LP, MP, MP+ and LVDSM
pads and EVR 4)
3.3V pad parameters
are valid
4.5
5.0
-
5.5 3)
4.5
V
V
V
V
5V pad parameters are
valid
Digital supply voltage for Flex
port
V
FLEX SR
2.97
4.5
3.3V pad parameters
are valid
5.0
3.3
5.5 3)
3.63 6)
5V pad parameters are
valid
Digital supply voltage for
LVDSH and A2 pads 5)
V
V
DDP3 SR
2.97
3.3V pad parameters
are valid; only required
if externally supplied
Flash supply voltage 3.3V 1)
DDFL3 SR 2.97
3.3
3.63
V
Only required if
externally supplied
Digital ground voltage
V
V
SS SR
0
-
-
V
V
V
V
Analog ground voltage for VDDM
SSM CC
-0.1
0
-
0.1
Voltage to ensure defined pad VDDPPA CC 0.72
-
-
A2 and LVDSH
states 7)
1.4
-
LP, MP, MP+, MPR
and LVDSM
Digital external supply voltage
for EVR and during Standby
mode
V
EVRSB SR 2.97
-
5.5
V
only available in BGA
package. VEVRSB is
bonded together with
V
EXT supply pin in
LQFP package.
1) No external inductive load permissible if EVR is used. All VDD pins shall be connected together externally on the PCB.
2) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
3) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
4) All VEXT pins shall be connected together externally on the PCB.
5) All VDDP3 pins shall be connected together externally on the PCB.
6) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
7) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-up/power-down
of VDDP3
.
Data Sheet
159
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TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
3.5
5 V / 3.3 V switchable Pads
Pad classes LP, MP, MP+, and MPR support both Automotive Level (AL) or TTL level (TTL) operation. Parameters
are defined for AL operation and degrade in TTL operation.
Table 3-6 Standard_Pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pin capacitance (digital
inputs/outputs)
CIO CC
-
6
10
pF
ns
Spike filter always blocked
pulse duration
t
SF1 CC
-
-
80
-
PORST only
PORST only
Spike filter pass-through pulse tSF2 CC
220
-
ns
duration
PORST pad output current 1)
I
PORST CC 11
13
-
-
mA
mA
V
EXT = 3.0V; VPORST
0.9V; TJ = 165°C
EXT = 4.5V; VPORST
1.0V
=
=
-
-
V
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
Table 3-7 Class LP 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for LP pad 1) HYSLP CC 0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input Leakage current for LP
pad
I
OZLP CC
-150
150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
-
350
nA
nA
else
Input leakage current for P32.0 IOZP320 CC -4900
4900
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-9400
-
9400
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); for TJ >
150°C
-5800
-
-
-
-
-
5800
nA
nA
µA
µA
µA
else
-12000
12000
else; for TJ > 150°C
Pull-up current for LP pad
I
PUHLP CC
|30|
|43|
-
-
V
V
V
IHmin; AL
-
IHmin; TTL
|107|
ILmax; AL and TTL
Data Sheet
160
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TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-7 Class LP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
|100|
-
Pull-down current for LP pad
I
PDLLP CC
-
µA
V
V
V
IHmin; AL and TTL
ILmax; AL
|46|
|21|
200
-
µA
-
-
µA
ILmax; TTL
On-Resistance for LP pad,
weak driver 2)
RDSONLPW
CC
620
1040
Ohm
PMOS/NMOS ;
I
OH=0.5mA ;
IOL=0.5mA
On-Resistance for LP pad,
medium driver 2)
Rise / fall time for LP pad 3)
RDSONLPM
CC
50
-
155
260
Ohm
PMOS/NMOS ;
IOH=2mA ; IOL=2mA
t
LP CC
-
-
-
-
-
95+2.1 * ns
CL
CL≤50pF ; pin out
driver=weak
-
200+2.9 * ns
( CL - 50 )
CL≥50pF ; CL≤200pF ;
pin out driver=weak
-
25+0.5 * ns
CL
CL≤50pF ; pin out
driver=medium
-
50+0.75 * ns
( CL - 50 )
CL≥50pF ; CL≤200pF ;
pin out driver=medium
Input high voltage for LP pad
Input low voltage for LP pad
V
V
V
IHLP SR
ILLP SR
ILHLP CC
(0.73*VEX
T/FLEX)-
0.25
2.03 4)
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
-
(0.52*VEX
T/FLEX)-
0.25
0.8 5)
-
-
-
V
V
Hysteresis active, TTL
Input low / high voltage for LP
pad
1.85
3.0
Hysteresis inactive;
not available for P14.2,
P14.4, and P15.1
Pad set-up time for LP pad
t
SET_LP CC
-
-
-
100
ns
Input leakage current for P02.1 IOZ021 CC
-150
1030
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ >
150°C
-150
-
340
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ =
150°C
-420
-350
-
-
-
-
-
1100
380
|105|
-
nA
nA
µA
µA
µA
else; TJ > 150°C
else; TJ = 150°C
Pull down current for P32_0 pin IPDLP320 CC -
|41|
|16|
V
V
V
IHmin; AL and TTL
ILmax; AL
-
ILmax; TTL
Data Sheet
161
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TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-7 Class LP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull Up Current for P32_0 pin
I
PUHP320 CC |25|
-
-
-
-
-
µA
µA
µA
mA
V
V
V
IHmin; AL
|38|
-
-
IHmin; TTL
|112|
10
ILmax; AL and TTL
Short Circuit current for LP pad ISC SR
-10
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-8 Class LP 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for LP pad 1) HYSLP CC 0.05 *
VEXT/FLEX
Input Leakage current for LP
pad
I
OZLP CC
-150
-
150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
-
350
nA
nA
else
Input leakage current for P32.0 IOZP320 CC -4900
4900
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-9400
-
9400
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); for TJ >
150 °C
-5800
-
5900
nA
nA
µA
µA
µA
µA
µA
µA
Ohm
else
-12000
-
12000
else; for TJ > 150°C
Pull-up current for LP pad
I
I
PUHLP CC
|17|
|19|
-
-
-
V
V
V
V
V
V
IHmin; AL
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for LP pad
PDLLP CC
-
-
|22|
|11|
250
-
-
-
ILmax; TTL
On-Resistance for LP pad,
weak driver 2)
RDSONLPW
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA ;
IOL=0.25mA
Data Sheet
162
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-8 Class LP 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance for LP pad,
medium driver 2)
RDSONLPM
CC
70
235
400
Ohm
; NMOS/PMOS ;
IOH=1mA ; IOL=1mA
Rise / fall time for LP pad 3)
t
LP CC
-
-
-
-
-
-
-
-
-
150+3.4 * ns
CL
CL≤50pF ; pin out
driver=weak
320+4.5 * ns
( CL - 50 )
CL≥50pF ; CL≤200pF ;
pin out driver=weak
30+0.8*C ns
CL≤50pF ; pin out
driver=medium
L
70+1.1 * ( ns
CL - 50 )
CL≥50pF ; CL≤200pF ;
pin out driver=medium
Input high voltage for LP pad
Input low voltage for LP pad
V
V
V
IHLP SR
ILLP SR
ILHLP CC
(0.73*VEX
T/FLEX)-
0.25
1.6 4)
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Input low / high voltage for LP
pad
1.1
1.9
Hysteresis inactive;
not available for P14.2,
P14.4, and P15.1
Pad set-up time for LP pad
t
SET_LP CC
-
-
-
100
920
ns
Input leakage current for P02.1 IOZ021 CC
-150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ >
150°C
-150
-
330
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ =
150°C
-360
-350
-
-
-
-
-
-
-
-
-
1000
nA
nA
µA
µA
µA
µA
µA
µA
mA
else; TJ > 150°C
else; TJ = 150°C
375
Pull down current for P32_0 pin IPDLP320 CC -
|17|
|80|
V
V
V
V
V
V
IHmin; AL and TTL
ILmax; AL
-
|6|
-
ILmax; TTL
Pull Up Current for P32_0 pin
I
PUHP320 CC |12|
-
IHmin; AL
|14|
-
-
IHmin; TTL
|80|
10
ILmax; AL and TTL
Short Circuit current for LP pad ISC SR
-10
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
Data Sheet
163
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-9 Class MP 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for MP pad 1) HYSMP CC 0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input Leakage current for MP
pad
I
I
OZMP CC
-500
500
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1000
-
1000
nA
else
Pull-up current for MP pad
PUHMP CC |30|
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|43|
-
-
-
IHmin; TTL
-
|107|
|100|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP pad
I
PDLMP CC
-
-
|46|
|21|
-
-
-
ILmax; TTL
On-Resistance for MP pad,
weak driver 2)
RDSONMPW 200
CC
620
1040
PMOS/NMOS ;
I
OH=0.5mA ;
IOL=0.5mA
On-Resistance for MP pad,
medium driver 2)
RDSONMPM
CC
50
20
155
75
260
130
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA ; IOL=2mA
PMOS/NMOS ;
IOH=8mA ; IOL=8mA
On-Resistance for MP pad,
strong driver 2)
RDSONMPS
CC
Data Sheet
164
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-9 Class MP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise / fall time for MP pad 3)
t
MP CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF ; pin out
driver=weak
L
-
-
-
200+2.9*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=weak
25+0.5*C ns
CL≤50pF ; pin out
driver=medium
L
50 + 0.75 ns
CL≥50pF ; CL≤200pF ;
* ( CL - 50
)
pin out driver=medium
-
-
-
-
17.5+0.25 ns
*CL
CL≤50pF ;
edge=medium ; pin out
driver=strong
30+0.3*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=medium ; pin out
driver=strong
-
-
-
-
7+0.2*CL ns
CL≤50pF ; edge=sharp
; pin out driver=strong
17+0.3*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=strong
Input high voltage for MP pad
Input low voltage for MP pad
V
V
IHMP SR
(0.73*VEX
T/FLEX)-
0.25
2.03 4)
-
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
ILMP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP VILHMP CC 1.85
3.0
pad
Pad set-up time for MP pad
t
SET_MP CC
-
-
-
100
10
ns
Short Circuit current for MP pad ISC SR
-10
mA
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Data Sheet
165
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-10 Class MP 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for MP pad 1) HYSMP CC 0.05 *
VEXT/FLEX
Input Leakage current for MP
pad
I
OZMP CC
-500
-
500
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1000
-
1000
nA
else
Pull-up current for MP pad
I
PUHMP CC |17|
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP pad
I
PDLMP CC
-
-
|22|
|11|
-
-
-
ILmax; TTL
On-Resistance for MP pad,
weak driver 2)
RDSONMPW 250
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA ;
IOL=0.25mA
On-Resistance for MP pad,
medium driver 2)
RDSONMPM
CC
70
20
-
235
400
200
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA ; IOL=1mA
On-Resistance for MP pad,
strong driver 2)
Rise / fall time for MP pad 3)
RDSONMPS
CC
110
PMOS/NMOS ;
I
OH=4mA ; IOL=4mA
t
MP CC
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF ; pin out
driver=weak
-
320+4.5*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=weak
-
30+0.8*C ns
CL≤50pF ; pin out
driver=medium
L
-
70+1.1*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=medium
-
32.5+0.35 ns
CL≤50pF ;
*CL
edge=medium ; pin out
driver=strong
-
-
50+0.45*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=medium ; pin out
driver=strong
-
-
-
-
14.5+0.35 ns
*CL
CL≤50pF ; edge=sharp
; pin out driver=strong
32+0.5*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=strong
Data Sheet
166
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-10 Class MP 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for MP pad
V
V
IHMP SR
(0.73*VEX
T/FLEX)-
0.25
1.6 4)
-
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP pad
ILMP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP VILHMP CC 1.1
1.9
pad
Pad set-up time for MP pad
t
SET_MP CC
-
-
-
100
10
ns
Short Circuit current for MP pad ISC SR
-10
mA
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-11 Class MP+ 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input hysteresis for MP+ pad 1) HYSMPP
0.09 *
CC
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input leakage current for MP+
pad
I
I
OZMPP CC -750
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPP CC |30|
-
-
-
-
-
-
-
1500
nA
µA
µA
µA
µA
µA
µA
else
Pull-up current for MP+ pad
-
V
V
V
V
V
V
IHmin; AL
|43|
-
-
IHmin; TTL
|107|
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP+ pad IPDLMPP CC
-
|100|
|46|
|21|
-
-
ILmax; TTL
Data Sheet
167
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-11 Class MP+ 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-resistance for MP+ pad,
weak driver 2)
RDSONMPPW 200
CC
620
1040
Ohm
PMOS/NMOS ;
IOH=0.5mA ;
IOL=0.5mA
On-resistance for MP+ pad,
medium driver 2)
RDSONMPPM 50
CC
155
260
90
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA ; IOL=2mA
On-resistance for MP+ pad,
strong driver 2)
Rise/fall time for MP+ pad 3)
RDSONMPPS 20
CC
55
-
PMOS/NMOS ;
I
OH=8mA ; IOL=8mA
t
MPP CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF ; pin out
driver=weak
L
-
200+2.9*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=weak
-
25+0.5*C ns
CL≤50pF ; pin out
driver=medium
L
-
50+0.75*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=medium
-
9+0.16*C ns
CL≤50pF ;
edge=medium ; pin out
L
driver=strong
-
-
17+0.2*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=medium ; pin out
driver=strong
-
-
-
-
4+0.16*C ns
CL≤50pF ; edge=sharp
; pin out driver=strong
L
12+0.21*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=strong
-
-
-
5
ns
from 0.8V to 2.0V
(RMII) ; CL=25pF ;
edge=sharp ; pin out
driver=strong
-
-
4.5
-
ns
V
CL=15pF ; edge=sharp
; pin out driver=strong
Input high voltage for MP+ pad VIHMPP SR (0.73*VEX
Hysteresis active, AL
T/FLEX)-
0.25
2.03 4)
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP+ pad
V
ILMPP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP+ VILHMPP CC 1.85
3.0
pad
Data Sheet
168
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-11 Class MP+ 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
100
10
Pad set-up time for MP+ pad
t
SET_MPP CC -
SCMPP SR -10
-
-
ns
Short circuit current for MP+
pad 6)
I
mA
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-12 Class MP+ 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input hysteresis for MP+ pad 1) HYSMPP
0.05 *
CC
VEXT/FLEX
Input leakage current for MP+
pad
I
OZMPP CC -750
-
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPP CC |17|
-
1500
nA
else
Pull-up current for MP+ pad
I
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP+ pad IPDLMPP CC
-
-
|22|
|11|
-
-
-
ILmax; TTL
On-resistance for MP+ pad,
weak driver 2)
RDSONMPPW 250
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA ;
IOL=0.25mA
On-resistance for MP+ pad,
medium driver 2)
RDSONMPPM 70
CC
235
75
400
130
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA ; IOL=1mA
PMOS/NMOS ;
IOH=4mA ; IOL=4mA
On-resistance for MP+ pad,
strong driver 2)
RDSONMPPS 20
CC
Data Sheet
169
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-12 Class MP+ 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time for MP+ pad 3)
t
MPP CC
-
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF ; pin out
driver=weak
-
-
-
-
320+4.5*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=weak
30+0.8*C ns
CL≤50pF ; pin out
driver=medium
L
70+1.1*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=medium
20+0.2*C ns
CL≤50pF ;
edge=medium ; pin out
L
driver=strong
-
-
30+0.3*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=medium ; pin out
driver=strong
-
-
-
-
13+0.2*C ns
CL≤50pF ; edge=sharp
; pin out driver=strong
L
23+0.3*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=strong
-
-
-
-
-
5
ns
ns
V
from 0.8V to 2.0V
(RMII) ; CL=25pF ;
edge=sharp ; pin out
driver=strong
4.5
from 0.2 * VEXT/FLEX to
0.8 * VEXT/FLEX
;
CL=15pF ; edge=sharp
; pin out driver=strong
Input high voltage for MP+ pad VIHMPP SR (0.73*VEX
-
-
Hysteresis active, AL
T/FLEX)-
0.25
1.6 4)
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP+ pad
V
ILMPP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP+ VILHMPP CC 1.1
1.9
pad
Pad set-up time for MP+ pad
t
SET_MPP CC -
SCMPP SR -10
-
-
100
10
ns
Short circuit current for MP+
pad 6)
I
mA
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
Data Sheet
170
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-13 Class MPR 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for MPR pads HYSMPR
0.09 *
VEXT/FLEX
1)
CC
0.075*
VEXT/FLEX
-
-
-
V
TTL
Input leakage current class
MPR
I
I
OZMPR CC -750
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPR CC |30|
-
1500
nA
else
Pull-up current
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|43|
-
-
-
IHmin; TTL
-
|107|
|100|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current
I
PDLMPR CC -
-
|46|
|21|
-
-
-
ILmax; TTL
On-resistance of the MPR pad, RDSONMPRW 200
weak driver 2)
CC
620
1040
PMOS/NMOS ;
I
OH=0.5mA ;
IOL=0.5mA
On-resistance of the MPR pad, RDSONMPRM 50
medium driver 2)
CC
On-resistance of the MPR pad, RDSONMPRS 20
strong driver 2)
CC
155
55
260
90
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA ; IOL=2mA
PMOS/NMOS ;
OH=8mA ; IOL=8mA
I
Data Sheet
171
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-13 Class MPR 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time 3)
t
MPR CC
-
-
-
-
-
-
95+2.1*C ns
CL≤50pF ; pin out
driver=weak
L
-
-
-
-
200+2.9*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=weak
25+0.5*C ns
CL≤50pF ; pin out
driver=medium
L
50+0.75*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=medium
9+0.16*C ns
CL≥0pF ; CL≤50pF ;
edge=medium ; pin out
driver=strong
L
-
-
17+0.2*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=medium ; pin out
driver=strong
-
-
-
-
4+0.16*C ns
CL≤50pF ; edge=sharp
; pin out driver=strong
L
12+0.21*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=strong
-
-
-
-
-
5
ns
ns
V
from 0.8V to 2.0V
(RMII) ; CL=25pF ;
edge=sharp ; pin out
driver=strong
4.5
from 0.2 * VEXT/FLEX to
0.8 * VEXT/FLEX
;
CL=15pF ; edge=sharp
; pin out driver=strong
Input high voltage, class MPR
pads
V
V
V
IHMPR SR (0.73*VEX
-
-
Hysteresis active, AL
T/FLEX)-
0.25
2.03 4)
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage, class MPR
pads
ILMPR SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage, class
MPR pads
ILHMPR SR 1.2
2.3
Pad set-up time
t
SET_MPR CC -
-
-
100
10
ns
Short circuit current Class MPR ISC SR
-10
mA
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
Data Sheet
172
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
Table 3-14 Class MPR 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for MPR pads HYSMPR
0.05 *
VEXT/FLEX
1)
CC
Input leakage current class
MPR
I
OZMPR CC -750
-
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPR CC |17|
-
1500
nA
else
Pull-up current
I
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current
I
PDLMPR CC -
-
|22|
|11|
-
-
-
ILmax; TTL
On-resistance of the MPR pad, RDSONMPRW 250
weak driver 2)
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA ;
IOL=0.25mA
On-resistance of the MPR pad, RDSONMPRM 70
medium driver 2)
CC
On-resistance of the MPR pad, RDSONMPRS 20
strong driver 2)
CC
235
75
400
130
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA ; IOL=1mA
PMOS/NMOS ;
OH=4mA ; IOL=4mA
I
Data Sheet
173
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-14 Class MPR 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time 3)
t
MPR CC
-
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF ; pin out
driver=weak
-
-
-
-
320+4.5*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=weak
30+0.8*C ns
CL≤50pF ; pin out
driver=medium
L
70+1.1*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
pin out driver=medium
20+0.2*C ns
CL≥0pF ; CL≤50pF ;
edge=medium ; pin out
driver=strong
L
-
-
30+0.3*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=medium ; pin out
driver=strong
-
-
-
-
13+0.2*C ns
CL≤50pF ; edge=sharp
; pin out driver=strong
L
23+0.3*( ns
CL-50)
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=strong
-
-
-
-
-
5
ns
ns
V
from 0.8V to 2.0V
(RMII) ; CL=25pF ;
edge=sharp ; pin out
driver=strong
4.5
from 0.2 * VEXT/FLEX to
0.8 * VEXT/FLEX
;
CL=15pF ; edge=sharp
; pin out driver=strong
Input high voltage, class MPR
pads
V
V
V
IHMPR SR (0.73*VEX
-
-
Hysteresis active, AL
T/FLEX)-
0.25
1.6 4)
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage, class MPR
pads
ILMPR SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage, class
MPR pads
ILHMPR SR 0.8
1.7
Pad set-up time
t
SET_MPR CC -
-10
-
-
100
10
ns
Short circuit current Class MPR ISC SR
mA
absolute max value
(PSI5)
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
Data Sheet
174
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
Table 3-15 Class S
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
75
Input frequency
-
-
-
-
-
-
-
-
MHz
MHz
V
Hysteresis active
-
150
-
Hysteresis inactive
Input Hysteresis for S pad 1)
Pull-up current for S pad
HYSS CC
0.3
|30|
-
I
PUHS CC
-
µA
VIHmin
VILmax
VIHmin
VILmax
|107|
|100|
-
µA
Pull-down current for S pad
I
PDLS CC
-
µA
|46|
-350
µA
Input Leakage current Class S IOZS CC
350
nA
Analog Inputs with pull
down diagnostics
-150
-
-
-
150
nA
V
else
Input voltage high for S pad
Input voltage low for S pad
V
V
IHS SR
ILS SR
(0.73*VDD
M)-0.25
Hysteresis active
(0.52*VDD
M)-0.25
-
-
-
V
Hysteresis active
Input low threshold variation for VILSD SR
-50
50
mV
max. variation of 1ms;
VDDM=constant
S pad 2)
Input capacitance for S pad
Pad set-up time for S pad
C
INS CC
-
-
-
-
10
pF
ns
t
SETS CC
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VILSD is implemented to ensure J2716 specification. For details of dedicated pins please see AP32286 for details.
Table 3-16 Class I 5V
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
PORST pad only
150
-
Input Hysteresis for I pad 1)
HYSI CC
0.07 *
VEXT/FLEX
0.09 *
VEXT/FLEX
-
-
-
-
V
V
AL
0.075 *
TTL
VEXT/FLEX
Pull-up current for I pad
Data Sheet
I
PUHI CC
|30|
|43|
-
-
-
-
-
µA
µA
µA
V
V
V
IHmin; AL
-
IHmin; TTL
|107|
ILmax; AL and TTL
175
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-16 Class I 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
|100|
-
Pull-down current for I pad
I
PDLI CC
-
-
-
-
µA
µA
µA
nA
V
V
V
IHmin; AL and TTL
ILmax; AL
|46|
|21|
-150
-
ILmax; TTL
Input Leakage Current for I pad IOZI CC
150
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
2.03 2)
-
-
-
350
nA
V
else
Input high voltage for I pad
Input low voltage for I pad
V
V
IHI SR
-
-
Hysteresis active, TTL
(0.73*VEX
T/FLEX)-
0.25
V
Hysteresis active; AL;
not available for the
PORST pad
ILI SR
-
-
-
-
0.8 3)
V
V
Hysteresis active, TTL
(0.52*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low / high voltage for I pad VILHI CC
Pad set-up time for I pad SETI CC
1.85
-
-
-
3.0
V
Hysteresis inactive
t
100
ns
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VIHx = 0.27 * VEXT/FLEX + 0.545V
3) VILx = 0.17 * VEXT/FLEX
Table 3-17 Class I 3.3V
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
PORST pad only
100
-
Input Hysteresis for I pad 1)
HYSI CC
0.045 *
VEXT/FLEX
0.05 *
-
-
V
AL and TTL
VEXT/FLEX
Pull-up current for I pad
I
I
PUHI CC
|17|
|19|
-
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
µA
nA
V
V
V
V
V
V
IHmin; AL
-
IHmin; TTL
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for I pad
PDLI CC
-
|22|
|11|
-150
-
ILmax; TTL
Input Leakage Current for I pad IOZI CC
150
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
350
nA
else
Data Sheet
176
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-17 Class I 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for I pad
V
V
IHI SR
1.6 2)
-
-
-
-
V
V
Hysteresis active, TTL
(0.73*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low voltage for I pad
ILI SR
-
-
-
-
0.5 3)
V
V
Hysteresis active, TTL
(0.52*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low / high voltage for I pad VILHI CC
Pad set-up time for I pad SETI CC
1.1
-
-
-
1.9
V
Hysteresis inactive
t
100
ns
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VIHx = 0.27 * VEXT/FLEX + 0.545V
3) VILx = 0.17 * VEXT/FLEX
Table 3-18 Driver Mode Selection for LP Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Driver Setting
medium (LPm)
weak (LPw)
X
X
X
X
0
1
Table 3-19 Driver Mode Selection for MP / MP+ Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Driver Setting
X
0
0
Speed grade 1
Strong sharp edge
(MPss / MP+ss / MPRss)
X
X
X
0
1
1
1
0
1
Speed grade 2
Speed grade 3
Speed grade 4
Strong medium edge (MPsm / MP+sm)
medium (MPm / MP+m / MPRm)
weak (MPw / MP+w / MPRw)
Data Sheet
177
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification3.3 V only Pads
3.6
3.3 V only Pads
Pad classes LP, MP and MP+ support both Automotive Level (AL) or TTL level (TTL) operation. Parameters are
defined for AL operation and degrade in TTL operation.
Table 3-20 Class A2
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input Hysteresis for A2 pad 1) HYSA2 CC 0.1 *
fIN SR
-
-
-
MHz
V
TTL;else
VDDP3
0.06 *
VDDP3
-
-
-
V
valid for P21.6 and
P21.7
Input Leakage current for A2
pad
I
OZA2 CC
-300
300
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-800
-
-
500
|100|
-
nA
else
Pull-up current for A2 pad
I
I
PUHA2 CC
-
µA
VIHmin
|25|
|23|
-
-
µA
VILmax
Pull-down current for A2 pad
PDLA2 CC
-
-
µA
VIHmin
-
|100|
325
µA
VILmax
On-Resistance for A2 pad,
weak driver 2)
RDSONA2W
CC
100
200
Ohm
PMOS/NMOS ;
I
OH=0.5mA ;
IOL=0.5mA
On-Resistance for A2 pad,
medium driver 2)
RDSONA2M
CC
40
20
-
70
35
-
100
50
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA ; IOL=2mA
On-Resistance for A2 pad,
strong driver 2)
Rise/fall time for A2 pad 3)
RDSONA2S
CC
PMOS/NMOS ;
I
OH=8mA ; IOL=8mA
t
A2 CC
20+0.8*C ns
CL≤50pF ; pin out
driver=weak
L
-
-
17.5+0.85 ns
CL≥50pF ; CL≤200pF ;
*CL
pin out driver=weak
-
-
12+0.16* ns
CL≤50pF ; pin out
CL
driver=medium
-
-
11.5+0.17 ns
CL≥50pF ; CL≤200pF ;
*CL
pin out driver=medium
-
-
6+0.06*C ns
CL≤50pF ;
edge=medium ; pin out
L
driver=strong
-
-
5.5+0.07* ns
CL
CL≥50pF ; CL≤200pF ;
edge=medium ; pin out
driver=strong
-
-
-
-
0.0+0.12* ns
CL
CL≤50pF ; edge=sharp
; pin out driver=strong
0.0+0.12* ns
CL
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=strong
Data Sheet
178
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical Specification3.3 V only Pads
Table 3-20 Class A2 (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for A2 pad
Input low voltage for A2 pad
Pad set-up time for A2 pad
V
IHA2 SR
2.04 4)
-
-
V
TTL;valid for all A2
pads except
TMS/DAP1, TRST,
and TCK/DAP0
0.7 *
VDDP3
-
-
-
V
V
valid for TMS/DAP1,
TRST, and TCK/DAP0
V
ILA2 SR
-
0.8 5)
TTL;valid for all A2
pads except
TMS/DAP1, TRST,
and TCK/DAP0
-
-
0.3 *
VDDP3
V
valid for TMS/DAP1,
TRST, and TCK/DAP0
t
SETA2 CC
-
-
-
-
100
20
ns
%
Deviation of symmetry for rising SYM CC
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VDDP3
4) VIHx = 0.57 * VDDP3 - 0.03V
.
5) VILx = 0.25 * VDDP3 + 0.058V
Table 3-21 Driver Mode Selection for A2 Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
Strong sharp edge
Strong medium edge
medium
X
X
X
X
0
0
1
1
0
1
0
1
weak
Table 3-22 Driver Mode Selection for F Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Reduced Strong sharp edge
Reduced Strong medium edge
medium
weak
Data Sheet
179
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
3.7
High performance LVDS Pads (LVDSH)
This LVDS pad type is used for the high speed chip to chip communication inferface of the new TC270 / TC275 /
TC277. It compose out of a LVDSH pad and a Class F pad.
This pad combination is always supplied by the 3.3V supply rail.
Table 3-23 Class F
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
-
Input frequency
Input Hysteresis for F pad 1)
fIN SR
-
-
-
MHz
V
HYSF CC 0.1 *
TTL
VDDP3
Input Leakage Current for F
pad
I
OZF CC
-1000
-1500
-300
-
-
-
1000
1500
300
nA
nA
nA
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.2 and P21.3; TJ =
150°C
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.2 and P21.3; TJ =
170°C
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.4 and P21.5
-2000
-3000
-600
-
-
-
2000
3000
600
nA
nA
nA
else; valid for P21.2
and P21.3; TJ = 150°C
else; valid for P21.2
and P21.3; TJ = 170°C
else; valid for P21.4
and P21.5
Pull-up current for F pad
I
I
PUHF CC
PDLF CC
|25|
-
-
-
µA
VIHmin
-
|100|
|100|
-
µA
VILmax
Pull-down current for class F
pads
-
-
µA
VIHmin
|25|
100
-
µA
VILmax
On resistance for F pad, weak RDSONFW
200
325
Ohm
PMOS/NMOS ;
IOH=0.5mA ;
driver 2)
CC
IOL=0.5mA
On resistance for F pad,
medium driver 2)
RDSONFM
CC
40
70
50
100
80
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA ; IOL=2mA
PMOS/NMOS ;
IOH=4mA ; IOL=4mA
On resistance for F pad, strong RDSONFS CC 20
driver 2)
Data Sheet
180
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-23 Class F (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time for F pad 3)
t
rfF CC
-
-
-
-
-
-
20+0.8*C ns
CL≤50pF ; pin out
driver=weak
L
-
-
-
-
17.5+0.85 ns
*CL
CL≥50pF ; CL≤200pF ;
pin out driver=weak
12+0.16* ns
CL
CL≤50pF ; pin out
driver=medium
11.5+0.17 ns
*CL
CL≥50pF ; CL≤200pF ;
pin out driver=medium
7+0.16*C ns
CL≤50pF ;
edge=medium ; pin out
L
driver=reduced strong
-
-
-
-
-
-
6.5+0.17* ns
CL
CL≥50pF ; CL≤200pF ;
edge=meduim ; pin out
driver>reduced strong
4+0.16*C ns
CL≤50pF ; edge=sharp
; pin out
driver=reduced strong
L
3.5+0.17* ns
CL
CL≥50pF ; CL≤200pF ;
edge=sharp ; pin out
driver=reduced strong
Input high voltage for F pad
Input low voltage for F pad
Pad set-up time for F pad
V
V
IHF SR
ILF SR
2.04 4)
-
-
-
-
-
V
TTL
TTL
-
-
-
0.8 5)
100
20
V
t
SETF CC
ns
%
Deviation of symmetry for rising SYM CC
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VDDP3
4) VIHx = 0.57 * VDDP3 - 0.03V
.
5) VILx = 0.25 * VDDP3 + 0.058V
CL = 2.5 pF for all LVDSH parameters.
Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
0.5
Output impedance
Rise time 1)
R0 CC
-
-
Ohm
ns
Vcm = 1.0 V and 1.4 V
t
rise20 CC
ZL = 100 Ohm ±5%
@2 pF
Fall time 1)
t
fall20 CC
-
-
0.5
ns
ZL = 100 Ohm ±5% @
2 pF
Output differential voltage
Data Sheet
V
OD CC
250
-
400
mV
RT = 100 Ohm ±5%
181
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Output voltage high
Output voltage low
V
V
OH CC
OL CC
-
-
1475
mV
RT = 100 Ohm ±5%
(400 mV/2) + 1275 mV
925
-
-
-
mV
mV
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
Output offset (Common mode) VOS CC
1125
1275
voltage
Input voltage range
VI SR
0
0
-
-
1600
2000
mV
mV
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±10%
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±20%
Input differential threshold
Delta output impedance
V
idth SR
-100
-
-
-
-
-
100
10
25
25
55
mV
%
Driver ground potential
difference < 925 mV
dR0 SR
-
Vcm = 1.0 V and 1.4 V
(mismatch Pd and Pn)
Change in VOS between 0 and dVOS CC
1
-
mV
mV
%
RT = 100 Ohm ±5%
Change in Vod between 0 and dVod CC
1
-
RT = 100 Ohm ±5%
Duty cycle
t
duty CC
45
1) Rise / fall times are defined for 20% - 80% of VOD
Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
140
250
1375
-
Output impedance
R0 CC
-
-
-
-
-
Ohm
mV
mV
mV
mV
Vcm = 1.0 V and 1.4 V
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
Output differential voltage
Output voltage high
Output voltage low
V
V
V
OD CC
OH CC
OL CC
150
-
1025
1125
Output offset (Common mode) VOS CC
1275
voltage
Input voltage range
VI SR
idth SR
825
-100
-
-
-
-
-
-
1575
100
25
mV
mV
mV
mV
%
Driver ground potential
difference < 50 mV
Input differential threshold
V
Driver ground potential
difference < 50 mV
Change in VOS between 0 and dVOS CC
1
RT = 100 Ohm ±5%
Change in Vod between 0 and dVod CC
1
-
25
RT = 100 Ohm ±5%
Duty cycle
t
duty CC
45
55
Data Sheet
182
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL) (cont’d)
Parameter Symbol Values
Typ.
Unit
Note / Test Condition
Min.
Max.
1)
V
OD Fall time
t
fall10 CC
-
-
0.5
ns
ns
ZL = 100 Ohm ±5% @
2pF
1)
VOD Rise time
t
rise10 CC
-
-
0.5
ZL = 100 Ohm ±5% @
2pF
1) Rise / fall times are defined for 10% - 90% of VOD
default after start-up = CMOS function
Data Sheet
183
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMedium performance LVDS Pads (LVDSM)
3.8
Medium performance LVDS Pads (LVDSM)
This LVDS pad type is used for the medium speed chip to chip communication inferface of the new TC270 / TC275
/ TC277. It compose out of a LVDSM pad and a MP pad.
This pad combination is always supplied by the 5V or 3.3V.
For the parameters of the MP pad please see Chapter 3.5.
Table 3-26 LVDSM
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
2.5
Output impedance
Fall time
RO CC
tF CC
100
-
Ohm
ns
Zload = 100 Ohm;
termination 100 Ohm
±1%
Rise time
tR CC
-
-
2.5
ns
Zload = 100 Ohm;
termination 100 Ohm
±1%
Pad set-up time
tSET_LVDS
CC
-
10
-
13
µs
Output Differential Voltage
Output voltage high
Output voltage low
Output Offset Voltage
V
V
V
V
OD CC
OH CC
OL CC
OS CC
250
-
400
1475
-
mV
mV
mV
mV
termination 100 Ohm
±1%
-
termination 100 Ohm
±1%
925
1125
-
termination 100 Ohm
±1%
-
1275
termination 100 Ohm
±1%
default after start-up = CMOS function
Data Sheet
184
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationVADC Parameters
3.9
VADC Parameters
VADC parameter are valid for VDDM = 4.5 V to 5.5 V.
This tables also covers the parameters for Class D pads.
Table 3-27 VADC
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Analog reference voltage 1)
Analog reference ground
V
V
V
AREF SR
VAGND
1.0
+
-
VDDM
0.05
+
+
V
V
AGND SR VSSM
-
-
VSSM
0.05
0.05
Analog input voltage range
Converter reference clock
AIN SR
VAGND
-
VAREF
20
V
f
ADCI SR
CONV CC
2
-
-
MHz
pC
Charge consumption per
conversion 2) 3)
Q
50
75
VAIN = 5 V, charge
consumed from
reference pin,
precharging disabled
-
-
-
-
-
10
22
-
pC
VAIN = 5 V, charge
consumed from
reference pin,
precharging enabled
Conversion time for 12-bit
result
t
t
C12 CC
(16 +
Includes sample time
and post calibration
STC) x
tADCI + 2 x
tVADC
Conversion time for 10-bit
result
C10 CC
(14 +
-
Includes sample time
Includes sample time
Includes sample time
STC) x
tADCI + 2 x
tVADC
Conversion time for 8-bit result tC8 CC
(12 +
-
STC) x
tADCI + 2 x
tVADC
Conversion time for fast
compare mode
t
CF CC
(4 + STC) -
x tADCI + 2
x tVADC
Broken wire detection delay
against VAGND
t
t
BWG CC
BWR CC
-
-
-
-
120
cycles Result below 10%
cycles Result above 80%
4)
Broken wire detection delay
-
60
5)
against VAREF
Input leakage at analog inputs IOZ1 CC
-350
350
nA
Analog Inputs overlaid
with class LP pads or
pull down diagnostics
-150
-4 6)
-
-
150
4 6)
nA
else
Total Unadjusted Error 1)
Data Sheet
TUE CC
LSB
12-bit resolution
185
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationVADC Parameters
Table 3-27 VADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
3
INL Error
EAINL CC
-3
-
-
-
-
-
LSB
LSB
LSB
LSB
pF
12-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
Gain Error 1)
DNL error 1)
Offset Error 1)
EAGAIN CC -3.5
EADNL CC -3
EAOFF CC -4
3.5
3
4
Total capacitance of an analog CAINT CC
-
30
input
Switched capacitance of an
analog input
CAINS CC
2
4
7
pF
Resistance of the analog input RAIN CC
path
-
-
-
-
1.5
1.8
kOhm else
kOhm valid for analog inputs
mapped to GPIOs
Switched capacitance of a
reference input
CAREFS CC
-
-
30
pF
RMS Noise 7)
ENRMS CC
OZ2 CC
-
0.5
-
0.8 6)8)
7
LSB
Positive reference VAREFx pin
I
-7
µA
µA
µA
µA
µA
µA
µA
µA
V
V
AREFx = VAREF2
AREF>VDDMV;
;
;
;
;
leakage
TJ>150°C
-4
-
-
-
-
-
-
-
4
V
V
AREFx = VAREF2
AREF>VDDMV;
TJ≤150°C
-2
3
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ>150°C
-1
1
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ≤150°C
Negative reference VAGNDx pin IOZ3 CC
leakage
-13
-7
13
7
V
V
AGNDx = VAGND2
AGND<VSSMV;
;
;
;
;
TJ>150°C
V
V
AGNDx = VAGND2
AGND<VSSMV;
TJ≤150°C
-3.3
-2.85
2.5
1
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ>150°C
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ≤150°C
Resistance of the reference
input path
CSD resistance 9)
R
R
AREF CC
CSD CC
-
-
-
-
1
kOhm
kOhm
28
Data Sheet
186
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationVADC Parameters
Table 3-27 VADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
35 - 8*VIN kOhm 0 V ≤ VIN ≤ 2.5 V
Resistance of the multiplexer
diagnostics pull-down device
R
R
R
MDD CC
MDU CC
PDD CC
25 + 1*VIN
-
-
-5 +
13*VIN
15 +
16*VIN
kOhm 2.5 V ≤ VIN ≤ VDDM
Resistance of the multiplexer
diagnostics pull-up device
45 - 6*VIN
-
90 -
16*VIN
kOhm 0 V ≥ VIN ≤ 2.5 V
40 - 4*VIN
-
-
65 - 6*VIN kOhm 2.5 V ≤ VIN ≤ VDDM
Resistance of the pull-down
test device 10)
-
0.3
kOhm
CSD voltage accuracy 11) 12)
dVCSD CC -
WU CC
-
-
10
12
%
Wakeup time
t
-
µs
1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor
1/k. VAREF must be decoupled with an external capacitor.
2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx
.
3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual.
4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 500 ms.
5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.
6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
7) This parameter is valid for soldered devices and requires careful analog board design.
8) Value is defined for one sigma Gauss distribution.
9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS
.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad
itself adds another 200-Ohm series resistance, when measuring through the pin.
11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.
12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current
of max. VAREF / 45 kOhm.
The following VADC parameter are valid for VDDM = 2.97 V to 3.63 V.
Table 3-28 VADC_33V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Analog reference voltage 1)
Analog reference ground
V
V
V
AREF SR
VAGND
1.0
+
-
VDDM
0.05
+
+
V
V
AGND SR VSSM
-
-
VSSM
0.05
0.05
Analog input voltage range
Converter reference clock
AIN SR
VAGND
-
-
VAREF
V
f
ADCI SR
2
20
MHz
Data Sheet
187
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Charge consumption per
conversion 2) 3)
QCONV CC
-
35
50
pC
VAIN = 3.3 V, charge
consumed from
reference pin,
precharging disabled
-
-
-
-
-
8
17
-
pC
VAIN = 3.3 V, charge
consumed from
reference pin,
precharging enabled
Conversion time for 12-bit
result
t
t
C12 CC
(16 +
Includes sample time
and post calibration
STC) x
tADCI + 2 x
tVADC
Conversion time for 10-bit
result
C10 CC
(14 +
-
Includes sample time
Includes sample time
Includes sample time
STC) x
tADCI + 2 x
tVADC
Conversion time for 8-bit result tC8 CC
(12 +
-
STC) x
tADCI + 2 x
tVADC
Conversion time for fast
compare mode
t
CF CC
(4 + STC) -
x tADCI + 2
x tVADC
Broken wire detection delay
against VAGND
t
t
BWG CC
BWR CC
-
-
-
-
120
cycles Result below 10%
cycles Result above 80%
4)
Broken wire detection delay
-
60
5)
against VAREF
Input leakage at analog inputs IOZ1 CC
-350
350
nA
Analog Inputs overlaid
with class LP pads or
pull down diagnostics
-150
-12 6)
-
-
150
12 6)
nA
else
Total Unadjusted Error 1)
TUE CC
EAINL CC
LSB
12-bit Resolution; TJ >
150 °C
-6 6)
-12
-5
-
-
-
-
-
6 6)
12
5
LSB
LSB
LSB
LSB
LSB
12-bit Resolution; TJ ≤
150 °C
INL Error
12-bit Resolution; TJ >
150 °C
12-bit Resolution; TJ ≤
150 °C
Gain Error 1)
EAGAIN CC -6
-5.5
6
12-bit Resolution; TJ >
150 °C
5.5
12-bit Resolution; TJ ≤
150 °C
Data Sheet
188
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DNL error 1)
Offset Error 1)
EADNL CC -4
EAOFF CC -6
-
-
4
6
LSB
LSB
12-bit resolution
12-bit Resolution; TJ >
150 °C
-5
-
5
LSB
pF
12-bit Resolution; TJ ≤
150 °C
Total capacitance of an analog CAINT CC
input
-
-
30
7
Switched capacitance of an
analog input
CAINS CC
2
-
4
-
pF
Resistance of the analog input RAIN CC
path
4.5
30
kOhm
pF
Switched capacitance of a
reference input
CAREFS CC
-
-
RMS Noise 7)
ENRMS CC
OZ2 CC
-
-
-
1.7 6)8)
6
LSB
µA
Positive reference VAREFx pin
I
-6
V
V
AREFx = VAREF2
AREF>VDDMV;
;
;
;
;
leakage
TJ>150°C
-3.5
-2
-
-
-
-
-
-
-
3.5
2.5
1
µA
µA
µA
µA
µA
µA
µA
V
V
AREFx = VAREF2
AREF>VDDMV;
TJ≤150°C
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ>150°C
-1
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ≤150°C
Negative reference VAGNDx pin IOZ3 CC
leakage
-12
-6.5
-2.2
-1
12
6.5
2
V
V
AGNDx = VAGND2
AGND<VSSMV;
;
;
;
;
TJ>150°C
V
V
AGNDx = VAGND2
AGND<VSSMV;
TJ≤150°C
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ>150°C
1
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ≤150°C
Resistance of the reference
input path
CSD resistance 9)
R
R
AREF CC
CSD CC
-
-
-
-
3
kOhm
kOhm
28
Data Sheet
189
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Resistance of the multiplexer
diagnostics pull-down device
R
MDD CC
25 + 3*VIN
-
40 +
12*VIN
kOhm 0 V ≤ VIN ≤ 1.667 V
0 + 18*VIN
-
-
0 + 18*VIN kOhm 1.667 V ≤ VIN ≤ VDDM
Resistance of the multiplexer
diagnostics pull-up device
R
R
MDU CC
60 -
12*VIN
120 -
kOhm 0 V ≤ VIN ≤ 1.667 V
kOhm 1.667 V ≤ VIN ≤ VDDM
kOhm
30*VIN
55 - 9*VIN
-
-
95 -
15*VIN
Resistance of the pull-down
test device 10)
PDD CC
-
0.9
CSD voltage accuracy 11) 12)
dVCSD CC -
WU CC
-
-
10
12
%
Wakeup time
t
-
µs
1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor
1/k. VAREF must be decoupled with an external capacitor.
2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx
.
3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual.
4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 500 ms.
5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.
6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
7) This parameter is valid for soldered devices and requires careful analog board design.
8) Value is defined for one sigma Gauss distribution.
9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS
.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad
itself adds another 200-Ohm series resistance, when measuring through the pin.
11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.
12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current
of max. VAREF / 45 kOhm.
A/D Converter
RSource
RAIN, On
VAIN
-
CExt
CAINT CAINS
CAINS
MCS05570
Figure 3-1 Equivalent Circuitry for Analog Inputs
Data Sheet
190
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationDSADC Parameters
3.10
DSADC Parameters
The following DSADC parameter are valid for VDDM = 4.5 V to 5.5 V.
Table 3-29 DSADC
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
5
Analog input voltage range 1)
V
DSIN SR
0
0
-
-
V
V
single ended
10
differential;VDSxP -
VDSxN
Reference load current
I
REF SR
-
4.5
6.3
µA
per twin-modulator (1
or 2 channels)
Modulator clock frequency 2)
Gain error
f
MOD SR
10
-
-
-
-
20
1 3)
3.5 4)
0.2 5)
MHz
%
EDGAIN CC -1
-3.5 4)
-0.2
Calibrated once
Uncalibrated
%
%
calibrated; GAIN = 1;
MODCFG.INCFGx=01
DC offset error
EDOFF CC -5
-
5 5)
50
100 4)
mV
mV
mV
calibrated
-50
-100 4)
-
calibrated once
gain = 1; uncalibrated
04)
500
130
Common Mode Rejection Ratio EDCM CC
Input impedance 6)
200
-
R
DAIN CC
100
170
kOhm Exact value (±1%)
available in UCB
Signal-Noise Ratio 7) 8) 9) 10)
SNR CC
80
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
kHz
fPB = 30 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
78
-
fPB = 50 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
70
-
fPB = 100 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
74
-
fPB = 100 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
76
-
fPB = 30 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
74
-
fPB = 50 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
Pass band
f
PB CC
10 11)
100
Output data rate fD =
f
PB * 3
Pass band ripple 8)
dfPB CC
fD CC
-1
-
-
1
%
Output sampling rate
30
330
kHz
Data Sheet
191
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationDSADC Parameters
Table 3-29 DSADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-3
Max.
DC compensation factor
DCF CC
-
-
-
dB
µA
10-5 fD
Positive reference VAREF1 pin
I
OZ5 CC
-2
2
all ADCs disabled
leakage
Negative reference VAGND1 pin IOZ6 CC
-2
-
2
µA
all ADCs disabled
leakage
Stop band attenuation 8)
SBA CC
40
45
50
55
60
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
V
0.5 ... 1 fD
1 ... 1.5 fD
1.5 ... 2 fD
2 ... 2.5 fD
2.5 ... OSR/2 fD
Reference ground voltage
Positive reference voltage
V
V
AGND SR VSSM
-
VSSM
0.05
+
+
0.05
AREF SR
V
DDMnom * -
VDDM
V
0.9
0.05
Common mode voltage
accuracy
dVCM CC
-100
-
-
100
200
mV
mV
from selected voltage
Common mode hold voltage
deviation 12)
dVCMH CC -200
From common mode
voltage
Analog filter settling time
Modulator recovery time
t
t
AFSET CC
MREC CC
-
-
2
4
µs
µs
If enabled
3.5
5.5
After leaving overdrive
state
Modulator settling time 13)
t
MSET CC
-
1
-
-
-
µs
After switching on,
voltage regulator
already running
Spurious Free Dynamic Range SFDR CC 60
dB
V
CM = 2.2 V, DC
7)14)
coupled; VDDM = ±10%
1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external
common mode voltage. In this case the Amplitude is limited to VCM * 2.
2) All modulators must run on the same frequency.
3) The calibration sequence must be executed once after an Application Reset
4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF
5) Recalibration needed in case of a temperature change > 20ºC
6) The variation of the impedance between different channels is < 1.5%.
7) Derating factors:
-2 dB in standard-performance mode.
-3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
8) CIC3, FIR0, FIR1 filters enabled.
9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM
(GAIN = 2).
10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM
.
11) 10 kHz only reachable with 10 MHz modulator clock frequency.
12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM
.
13) The modulator needs to settle after being switched on and after leaving the overdrive state.
14) SFDR = 20 * log(INL / 2N); N = amount of bits
Data Sheet
192
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationDSADC Parameters
The following DSADC parameter are valid for VDDM = 2.97 V to 3.63 V.
Table 3-30 DSADC_33V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
3.3
Analog input voltage range 1)
V
DSIN SR
0
0
-
-
V
V
single ended
6.6
differential;VDSxP -
VDSxN
Reference load current
I
REF SR
-
4.5
5.8
µA
per twin-modulator (1
or 2 channels)
Modulator clock frequency 2)
Gain error
f
MOD SR
10
-
-
-
-
20
MHz
%
EDGAIN CC -1.5
-10 4)
-0.3
1.5 3)
10 4)
0.3 5)
Calibrated once
Uncalibrated
%
%
calibrated; GAIN = 1;
MODCFG.INCFGx=01
DC offset error
EDOFF CC -5
-
5 5)
50
100 4)
mV
mV
mV
mV
calibrated
-50
-100 4)
-
calibrated once
gain = 1; uncalibrated
-
04)
-
-
gain = 1; uncalibrated;
uncalibrated
Common Mode Rejection Ratio EDCM CC
200
100
500
130
-
Input impedance 6)
R
DAIN CC
170
kOhm Exact value (±1%)
available in UCB
Signal-Noise Ratio 7) 8) 9) 10)
SNR CC
45
60
60
69
55
65
63
69
68
74
66
72
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
fPB = 100kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
f
PB = 100kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
f
PB = 30kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
f
PB = 30kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
f
PB = 50kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
f
PB = 50kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
Pass band
f
PB CC
10 11)
-1
-
-
100
1
kHz
%
Output data rate fD =
f
PB * 3
Pass band ripple 8)
dfPB CC
Data Sheet
193
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationDSADC Parameters
Table 3-30 DSADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
30
Max.
Output sampling rate
fD CC
-
-
-
330
kHz
dB
DC compensation factor
DCF CC
-3
-
10-5 fD
Positive reference VAREF1 pin
I
OZ5 CC
-2
2
µA
leakage
Negative reference VAGND1 pin IOZ6 CC
-2
-
2
µA
leakage
Stop band attenuation 8)
SBA CC
40
45
50
55
60
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
V
0.5 ... 1 fD
1 ... 1.5 fD
1.5 ... 2 fD
2 ... 2.5 fD
2.5 ... OSR/2 fD
Reference ground voltage
Positive reference voltage
V
V
AGND SR VSSM
-
VSSM
0.05
+
+
0.05
AREF SR
V
DDMnom * -
VDDM
V
0.9
0.05
Common mode voltage
accuracy
dVCM CC
-100
-
-
100
200
mV
mV
from selected voltage
Common mode hold voltage
deviation 12)
dVCMH CC -200
From common mode
voltage
Analog filter settling time
Modulator recovery time
t
t
AFSET CC
MREC CC
-
-
2
4
-
µs
µs
If enabled
3.5
After leaving overdrive
state
Modulator settling time 13)
t
MSET CC
-
1
-
µs
After switching on,
voltage regulator
already running
Spurious Free Dynamic Range SFDR CC 52
-
-
-
-
dB
dB
V
CM = 2.2 V, DC
coupled; VDDM = ±10%
CM = 2.2 V, DC
coupled; VDDM = ±5%
7)14)
60
V
1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external
common mode voltage. In this case the Amplitude is limited to VCM * 2.
2) All modulators must run on the same frequency.
3) The calibration sequence must be executed once after an Application Reset
4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF
5) Recalibration needed in case of a temperature change > 20ºC.
6) The variation of the impedance between different channels is < 1.5%.
7) Derating factors:
-2 dB in standard-performance mode.
-3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
8) CIC3, FIR0, FIR1 filters enabled.
9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM
(GAIN = 2).
10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM
.
Data Sheet
194
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationDSADC Parameters
11) 10 kHz bandwidth only with 10Mhz modulator clock frequency reachable
12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM
.
13) The modulator needs to settle after being switched on and after leaving the overdrive state.
14) SFDR = 20 * log(INL / 2N); N = amount of bits
VCM
Gain
VOFFSET
130 kΩ
130 kΩ
=
Modu-
lator
Gain
MC_DSADC_MODULATORBLOCK
Figure 3-2 DSADC Analog Inputs
Data Sheet
195
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMHz Oscillator
3.11
MHz Oscillator
OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 8 MHz to 40 MHz crystals external
outside of the device. Support of ceramic resonators is also provided.
Table 3-31 OSC_XTAL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-25
4
Max.
25
Input current at XTAL1
Oscillator frequency
I
IX1 CC
-
-
µA
VIN>0V ; VIN<VDDP3V
f
OSC SR
40
MHz
Direct Input Mode
selected
8
-
40
MHz
External Crystal Mode
selected
Oscillator start-up time 1)
t
OSCS CC
-
-
-
5 2)
ms
V
Input high voltage at XTAL1
V
IHBX SR
0.8
VDDP3
+
If shaper is bypassed
If shaper is bypassed
0.5
Input low voltage at XTAL1
Input voltage at XTAL1
V
ILBX SR
-0.5
-0.5
-
-
0.4
V
V
VIX SR
VDDP3
0.5
+
+
If shaper is not
bypassed
Input amplitude (peak to peak) VPPX SR
at XTAL1
0.3 *
VDDP3
-
-
VDDP3
1.0
V
V
If shaper is not
bypassed; fOSC
>
25MHz
0.4 *
VDDP3
VDDP3
1.0
+
If shaper is not
bypassed; fOSC
25MHz
≤
Internal load capacitor
Internal load capacitor
Internal load capacitor
Internal load capacitor
CL0 CC
CL1 CC
CL2 CC
CL3 CC
2
2.35
2.35
3.5
2.7
2.7
4
pF
pF
pF
pF
2
3
5.1
5.9
6.6
1) tOSCS is defined from the moment when VDDP3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDP3
.
The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended
and specified by crystal suppliers.
2) This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.
Note:It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
Data Sheet
196
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationBack-up Clock
3.12
Back-up Clock
The back-up clock provides an alternative clock source.
Table 3-32 Back-up Clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Back-up clock before trimming fBACKUT CC 75
Back-up clock after trimming BACKT CC 97.5
Max.
125
100
100
MHz
MHz
V
V
EXT≥2.97V
EXT≥2.97V
f
102.5
Data Sheet
197
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationTemperature Sensor
3.13
Temperature Sensor
Table 3-33 DTS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
100
1
Measurement time
tM CC
-
-
-
µs
°C
Calibration reference accuracy TCALACC CC -1
calibration points @
TJ=-40°C and
TJ=127°C
Non-linearity accuracy over
temperature range
T
T
NL CC
SR SR
-2
-
2
°C
Temperature sensor range
-40
-
-
-
170
20
°C
µs
Start-up time after resets
inactive
tTSST SR
The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the
DTSSTAT register.
(3.1)
DTSSTATRESULT – (607)
Tj = ---------------------------------------------------------------------------
2, 13
Data Sheet
198
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower Supply Current
3.14
Power Supply Current
The total power supply current defined below consists of leakage and switching component.
Application relevant values are typically lower than those given in the following table and depend on the customer's
system operating conditions (e.g. thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
The real (realisic) power pattern defines the following conditions:
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
SRI = fMAX = fCPU0 = 200 MHz
SPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 40 MHz
V
V
V
DD = 1.326 V
DDP3 = 3.366 V
EXT / FLEX = VDDM = 5.1 V
all cores are active including one lockstep core
the following peripherals are inactive: HSM, HSCT, Ethernet, PSI5, I2C, FCE, MTU, and 50% of the DSADC
channels
The max power pattern defines the following conditions:
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
SRI = fMAX = fCPU0 = 200 MHz
SPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 100 MHz
V
V
V
DD = 1.43 V
DDP3 = 3.63 V
EXT / FLEX = VDDM = 5.5 V
all cores and lockstep cores are active
all peripherals are active
Table 3-34 Power Supply
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
550
350
80
∑ Sum of IDD 1.3 V core and
peripheral supply currents
I
DD CC
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
max power pattern
real power pattern
TJ=125°C
I
DD core current during active IDDPORST
power-on reset (PORST held CC
low)
160
215
36
TJ=150°C
TJ=165°C
I
DD core current of CPU0
lockstep core active
DD core current of CPU1 main IDDC10 CC
I
DDC01 CC
real power pattern
I
-
-
43
mA
real power pattern
core with CPU1 lockstep core
inactive
I
DD core current of CPU1 main IDDC11 CC
core with lockstep core active
DD core current of CPU2 main IDDC20 CC
-
-
-
-
IDDC10
36
+
mA
mA
real power pattern
real power pattern
I
37
core
Data Sheet
199
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DD core current added by HSM IDDHSM CC
-
-
20
mA
mA
HSM running at
100MHz.
∑ Sum of 3.3 V supply currents IDDx3RAIL CC -
-
57
real power pattern
without pad activity
I
DDFL3 Flash memory current
I
DDFL3 CC
-
-
-
-
42 1)
42 2)
mA
mA
flash read current
flash read current
while programming
Dflash
I
DDP3 supply current without
I
DDP3 CC
-
-
-
-
15 1)
37 3)
mA
mA
real power pattern;
incl. OSC current &
flash read current
pad activity
incl. OSC current and
flash 3.3V
programming current
when using external
5V supply
-
-
-
39 2)
mA
incl. OSC current and
flash programming
current at 3.3V
I
DDP3 supply current for LVDSH IDDP3LVDSH
-
-
16
62
mA
mA
pads in LVDS mode
CC
Σ Sum of external and ADC
I
EXTRAIL CC -
real power pattern
supply currents (incl.
I
EXTFLEX+IDDM+IEXTLVDSM)
Sum of IEXT and IFLEX supply
current without pad activity
I
EXT/FLEX CC -
-
-
4
mA
mA
real power pattern;
PORST output
inactive.
I
EXT supply current for LVDSM IEXTLVDSM
-
14 4)
real power pattern
pads in LVDS mode CC
Data Sheet
200
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DDM supply current
I
DDM CC
-
-
44
mA
real power pattern;
sum of currents of
DSADC and VADC
modules
-
-
30
mA
current for DSADC
module only; 50%
DSADC channels
active.
-
-
-
-
14
mA
mA
real pattern; current for
VADC only
59 5)
max power pattern; All
DSADC channels
active 100% time.
-
-
17 6)
mA
max power pattern; All
VADC converters are
active 100% time
Σ Sum of all currents (incl.
EXTRAIL+IDDx3RAIL+IDD)
Σ Sum of all currents with DC- IDDTOTDC3
I
DDTOT CC
-
-
-
-
-
-
-
-
469
mA
mA
mA
µA
real power pattern
I
302
real power pattern;
7)
DC EVR13 regulator active
CC
V
EXT = 3.3V
real power pattern;
EXT = 5V
Σ Sum of all currents with DC- IDDTOTDC5
240
7)
DC EVR13 regulator active
CC
V
∑ Sum of all currents
(STANDBY mode)
I
I
EVRSB CC
150 8)
Standby RAM is
active. Power to
remaining domains
switched off. TJ =
25°C; VEVRSB = 5V
∑ Sum of all currents (SLEEP
SLEEP CC
-
-
15
mA
All CPUs in idle, All
peripherals in sleep,
mode)
f
SRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C
Maximum power dissipation
PD CC
-
-
-
-
1480
1014
mW
mW
max power pattern
real power pattern
1) Realistic Pflash read pattern with 70% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common
decoupling capacitor of atleast 100nF for (VDDFL3+VDDP3) is used. Dflash read current is also included. Flash read current
is predominantly drawn from VDDFL3 pin and a minor part drawn from the neighbouring VDDP3 pin.
2) Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Erase currents
of the corresponding flash modules are less than the respective programming currents at VDDP3 pin. Programming and
erasing flash may generate transient current spikes of up to x mA for maximum x us which is handled by the decoupling
and buffer capacitors. This parameter is relevant for external power supply dimensioning and not for thermal
considerations.
3) In addition to the current specified, upto 4 mA is additionally drawn at VEXT supply in burst programming mode with 5V
external supply. Erase currents of the corresponding flash modules are less than the respective programming currents at
V
DDP3 supply. This parameter is relevant for external power supply dimensioning and not for thermal considerations.
Data Sheet
201
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower Supply Current
4) The current consumption is for 2 pairs of LVDSM differential pads (8 pins). A single pair of LVDSM differential pads (4 pins)
consumes 7 mA.
5) The current consumption is for 6 DS channels with standard performance (MCFG=11b). A single DS channel instance
consumes 6-8 mA.
6) A single converter instance of VADC unit consumes 2 mA.
7) The total current drawn from external regulator is estimated with 72% EVR13 SMPS regulator Efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and
IDDM
.
8) Current at VEVRSB supply pin during normal RUN mode is less than 5 mA at Tj =150 degC. The transition between RUN
mode to STANDBY mode has a duration of less than 100us during which the current is higher but is less than 8 mA at Tj
=150 degC. Once STANDBY mode is entered with only Standby RAM active the current is less than 5mA at Tj = 150 degC.
It is recommended to have atleast 100 nF decoupling capacitor at this pin.
3.14.1
Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts:
•
•
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic current consumption
depends of the configured clocking frequencies and the software application executed. These two parts needs to
be added in order to get the rail current consumption.
(3.2)
mA
0, 02689 × T
--------
C
I
= 1, 135
= 3, 264
× e
[C]
J
0
(3.3)
mA
--------
0, 0259 × T
I
× e
[C]
J
0
C
Function 2 defines the typical static current consumption and Function 3 defines the maximum static current
consumption. Both functions are valid for VDD = 1.326 V.
Data Sheet
202
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
3.15
Power-up and Power-down
External Supply Mode
3.15.1
5 V & 1.3 V supplies are externally supplied. 3.3V is generated internally by EVR33.
•
External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Voltage Ramp-up from a residual threshold (Eg : up to 1 V) should also lead to a normal
startup of the device.
•
The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-3 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supplies
ramp up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR33 regulator is initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR33 regulator
has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge.
Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset
thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
203
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
4
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
VDD (externally supplied )
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDDP3 (internally generated
by EVR33)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
Basic Supply & Clock
Infrastructure
EVR33 Ramp-up Phase
Firmware Execution
User Code Execution
fCPU=100MHz default
on firmware exit
Power Ramp-down phase
Startup_Diag_1 v 0.1
Figure 3-3 External Supply Mode - 5 V and 1.3 V externally supplied
Data Sheet
204
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
3.15.2
Single Supply Mode
5 V single supply mode. 1.3 V & 3.3 V are generated internally by EVR13 & EVR33.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-4 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR13 and EVR33 regulators are initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 and EVR33
regulators have ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST
rising edge. Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset
thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
205
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
4
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDD
(internally generated
by EVR13)
1. 33 V
1.30
V
1. 17 V
Primary Reset Threshold
0 V
VDDP3
(internally generated
by EVR33)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
EVR13 & EVR 33 Ramp-up
Basic Supply & Clock
Infrastructure
User Code Execution
fCPU=100MHz default
on firmware exit
Firmware Execution
Power Ramp-down phase
Phase
Startup_Diag_2 v 0.1
Figure 3-4 Single Supply Mode - 5 V single supply
Data Sheet
206
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
3.15.3
External Supply Mode
All supplies, namely 5 V, 3.3 V & 1.3 V, are externally supplied.
•
•
External supplies VEXT ,, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s).
The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-5 is enumerated below
–
T1 refers to the point in time when all supplies are above their primary reset thresholds and basic clock
infrastructure is available. The supply mode is evaluated based on the HWCFG [0:2] pins. PORST (output)
is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated.
–
–
T2 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T3 refers to the point in time during the Ramp-down phase when atleast one of the externally provided
supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
207
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
VDD (externally supplied )
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
VDDP3
(externally supplied)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
T0
T1
T2
T3
Basic Supply & Clock
Infrastructure
User Code Execution
fCPU=100 MHz default
on firmware exit
Firmware Execution
Power Ramp-down phase
Startup_Diag_3 v 0.1
Figure 3-5 External Supply Mode - 5 V, 3.3 V & 1.3 V externally supplied
Data Sheet
208
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
3.15.4
Single Supply Mode
3.3 V single supply mode. 1.3 V is generated internally by EVR13.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V or 3.3 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-6 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR13 regulator is initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 regulator
has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge.
Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V or 3.3 V) drop below their respective primary under-voltage reset thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
209
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPower-up and Power-down
VEXT
0
1
2
3
4
(externally supplied )
&
VDDP3 (externally
supplied )
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDD (internally generated
by EVR 13)
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
Basic Supply & Clock
Infrastructure
User Code Execution
fCPU=100MHz default
on firmware exit
EVR13 Ramp-up Phase
Firmware Execution
Power Ramp-down phase
Startup_Diag_4 v 0.1
Figure 3-6 Single Supply Mode - 3.3 V single supply
Data Sheet
210
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationReset Timing
3.16
Reset Timing
Table 3-35 Reset Timings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Application Reset Boot Time 1) tB CC
-
-
350 2)
µs
operating with max.
frequencies.
System Reset Boot Time
Power on Reset Boot Time 3)
t
t
BS CC
BP CC
-
-
-
-
1
ms
ms
2.5 2)
dV/dT=1V/ms.
including EVR ramp-
up and Firmware
execution time
-
-
-
1.11 2)
ms
µs
Firmware execution
time; without EVR
operation (external
supply only)
Minimum PORST hold time
incase of power fail event
issued by EVR primary monitor
t
EVRPOR CC 10
-
EVR start-up or ramp-up time tEVRstartup
-
-
-
1
-
ms
ms
dV/dT=1V/ms. EVR13
and EVR33 active
CC
Minimum PORST active hold
time after power supplies are
stable at operating levels 4)
t
POA CC
1
Configurable PORST digital
filter delay in addition to analog
pad filter delay
t
PORSTDF CC 600
-
1200
ns
HWCFG pins hold time from
ESR0 rising edge
t
t
HDH CC
HDS CC
16 / fSPB
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
HWCFG pins setup time to
ESR0 rising edge
0
-
Ports inactive after ESR0 reset tPI CC
active
-
8/fSPB
Ports inactive after PORST
reset active 5)
t
t
t
PIP CC
POH SR
POS SR
-
150
Hold time from PORST rising
edge
150
0
-
-
Setup time to PORST rising
edge
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when
the first user instruction has entered the CPU pipeline and its processing starts.
2) The timing values assumes programmed BMI with ESR0CNT inactive.
3) The duration of the boot time is defined by all external supply voltages are inside there operation condictions and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
Data Sheet
211
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationReset Timing
4) The regulator that supplies VEXT should ensure that VEXT is in the operational region before PORST is externally released
by the regulator. Incase of 5V nominal supply, it should be ensured that VEXT > 4V before PORST is released. Incase of
3.3V nominal supply , it should be ensured that VEXT > 3V before PORST is released. The additional minimum PORST hold
time is required as an additional mechanism to avoid consecutive PORST toggling owing to slow supply slopes or residual
supply ramp-ups. It is also required to activate external PORST atleast 100us before power-fail is recognised to avoid
consecutive PORST toggling on a power fail event.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
VDDPPA
VDDPPA
VDDP
VDD
VDDPR
tPOA
tPOA
Warm
PORST
ESR0
Cold
t PI
tPI
tPIP
Tristate Z / pullup H
Programmed
Z / H
Programmed
Z / H
Programmed
Pads
Pad-
state
undefined
Pad-
state
undefined
tPOS
tPOS
tPOH
tPOH
TRST
TESTMODE
tHDH
tHDH
tHDA
tHDH
config
tHDA
HWCFG
power -on config
config
reset_beh_aurix
Figure 3-7 Power, Pad and Reset Timing
Data Sheet
212
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEVR
3.17
EVR
Table 3-36 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
4
Max.
5.50
3.63
Input voltage range 1)
VIN SR
-
V
V
pass device=on chip
pass device=on chip
Output voltage operational
range including load/line
regulation and aging incase of
LDO regulator
V
V
OUT CC
2.97
3.3
Output VDDx3 static voltage
accuracy after trimming and
aging without dynamic load/line
Regulation incase of LDO
regulator.
OUTT CC
3.225
3.3
3.375
V
pass device=on chip
Output buffer capacitance on
VOUT
C
OUT CC
-
-
1
-
-
µF
V
pass device=on chip
2)
Primary Undervoltage Reset
V
RST33 CC
3.0
by reset release before
EVR trimming on
supply ramp-up.
3)
threshold for VDDx3
Startup time
t
STR CC
-
-
-
1000
50
µs
Only EVR33 active. ;
pass device=on chip
External VIN supply ramp 4)
Load step response
dVin/dT
SR
1
-
V/ms pass device=on chip
dVout/dIout -
CC
240
mV
mV
mV
dI=-70mA/20ns;
Tsettle=20us; pass
device=on chip
-240
-
-
-
dI=50mA/20ns;
Tsettle=100us; pass
device=on chip
Line step response
dVout/dVin -20
20
dV/dT=1V/ms; pass
CC
device=on chip
1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device
operation.
2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the
resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
3) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold.
This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to
voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated
internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher
voltage of 3.0V at the VDDP3 pin.
4) EVR robust against residual voltage ramp-up starting between 0-1 V.
Data Sheet
213
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEVR
Table 3-37 1.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2.97
1.17
Max.
5.5
Input voltage range 1)
VIN SR
-
V
V
pass device=off chip
pass device=off chip
Output voltage operational
range including load/line
regulation and aging incase of
LDO regulator
V
V
OUT CC
1.3
1.43
Output VDD static voltage
accuracy after trimming without
dynamic load/line regulation
with aging incase of LDO
regulator.
OUTT CC
1.275
1.3
1.325
V
pass device=off chip
pass device=off chip
Output buffer capacitance on
COUT CC
3
-
4.7
-
6.3
µF
V
2)
VOUT
Primary undervoltage reset
threshold for VDD
V
RST13 CC
1.17
by reset release before
EVR trimming on
3)
supply ramp-up. pass
device=off chip
Startup time
t
STR CC
-
-
-
1000
50
µs
pass device=off chip.
Only EVR13 active.
External VIN supply ramp 4)
Load step response
dVin/dT
SR
1
-
V/ms pass device=off chip
dVout/dIout -
CC
100
mV
mV
mV
dI=-150mA;
Tsettle=20µs; pass
device=off chip
-100
-
-
-
dI=100mA;
Tsettle=20µs; pass
device=off chip
Line step response
dVout/dVin -10
10
dV/dT=1V/ms; pass
CC
device=off chip
1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device
operation.
2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the
resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
3) The reset release on supply ramp-up is delayed by a time duration 30-60 µs after reaching undervoltage reset threshold.
This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to
voltage drop/current jumps when reset is released.
4) EVR robust against residual voltage ramp-up starting between 0-1 V.
Data Sheet
214
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEVR
Table 3-38 Supply Monitoring
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
EXT primary undervoltage
VEXTPRIUV
SR
2.86
2.92
2.90
1.15
5.0
2.97
V
V
EXT = Undervoltage
monitor accuracy after
trimming 1)
Reset Threshold
VDDP3 primary undervoltage
VDDP3PRIUV 2.86
SR
2.97
1.17
5.1
V
V
V
DDP3 = Undervoltage
monitor accuracy after
trimming
Reset Threshold
1)
VDD primary undervoltage
VDDPRIUV
SR
1.13
VDD = Undervoltage
Reset Threshold
monitor accuracy after
trimming
1)
VEXT secondary supply monitor VEXTMON CC 4.9
V
SWDxxVAL VEXT
monitoring
accuracy
threshold=5V=DBh
V
DDP3 secondary supply
VDDP3MON
CC
3.23
3.30
1.30
-
3.37
1.33
1.8
V
EVR33xxVAL VDDP3
monitoring
threshold=3.3V=91h
monitor accuracy
VDD secondary supply monitor VDDMON CC 1.27
V
EVR13xxVAL VDD
monitoring
threshold=1.3V=E4h
accuracy
EVR primary and secondary
monitor measurement latency
for a new supply value
t
EVRMON CC -
µs
after trimming
1) The monitor tolerances constitute the inherent variation of the bandgap and ADC over process, voltage and temperature
operational ranges. The xxxPRIUV parameters are device individually tested in production with ±1% tolerance about the
min and max xxxPRIUV limits.
Table 3-39 EVR13 SMPS External components
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
29.7
13.5
50
External output capacitor value COUTDC SR 15.4
22
10
-
µF
µF
I
I
DDDC=1A
1)
6.5
DDDC=400mA
External output capacitor ESR CDC_ESR SR -
mOhm f≥0.5MHz ; f≤10MHz
-
-
100
13.5
9.18
50
Ohm
µF
f=10Hz
External input capacitor value 1) CIN SR
6.5
4.42
-
10
6.8
-
I
I
DDDC=1A
µF
DDDC=400mA
External input capacitor ESR
External inductor value 2)
External inductor ESR
C
IN_ESR SR
mOhm f≥0.5MHz ; f≤10MHz
-
-
100
4.29
6.11
0.2
Ohm
µH
f=100Hz
L
DC SR
2.31
3.29
3.3
4.7
-
f
f
DCDC=1.5MHz
DCDC=1MHz
µH
L
DC_ESR SR -
LL SR
Ohm
V
P + N-channel MOSFET logic
level
V
-
-
2.5
Data Sheet
215
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEVR
Table 3-39 EVR13 SMPS External components (cont’d)
Parameter Symbol Values
Typ.
Unit
Note / Test Condition
Min.
Max.
P + N-channel MOSFET drain |VBR_DS| SR -
-
7
V
source breakdown voltage
P + N-channel MOSFET drain RON SR
source ON-state resistance
-
-
150
mOhm IDDDC=1A;VGS=2.5V ;
TA=25°C
-
-
200
mOhm IDDDC=400mA;VGS=2.5
V ; TA=25°C
P + N-channel MOSFET Gate Qac SR
Charge
-
4
-
nC
nC
ns
V
I
DDDC=1A; MOS-
VGS=5V
IDDDC=400mA; MOS-
-
8
-
VGS=5V
External MOSFET
commutation time
tc SR
RDN SR
10
-
30
0.8
40
-
configurable
N-channel MOSFET reverse
diode forward voltage
V
1) Capacitor min-max range represent typical ±35% tolerance including DC bias effect. The trace resistance from the
capacitor to the supply or ground rail should be limited to 25 mOhm.
2) External inductor min-max range represent typical ±30% tolerance at a DC bias current of 100mA.
Table 3-40 EVR13 SMPS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2.97
1.17
Max.
5.5
Input VEXT Voltage range
VIN SR
-
-
V
V
SMPS regulator output voltage VDDDC CC
range including load/line
regulation and aging 1)
1.43
V
DD≥2.97V ; VDD≤5.5V
; IDDDC≥1mA ;
DDDC≤1A
DD≥2.97V ; VDD≤5.5V
; IDDDC≥1mA ;
DDDC≤1A
I
SMPS regulator static voltage
output accuracy after trimming
without dynamic load/line
Regulation with aging. 2)
V
DDDCT CC 1.275
1.3
1.325
V
V
I
Programmable switching
frequency
f
DCDC CC
0.4
-
-
-
2.0
2%
15
MHz
MHz
mV
Switching frequency
modulation spread
∆fDCSPR CC -
Maximum ripple at IMAX (peak- ∆VDDDC CC -
V
DD≥2.97V ; VDD≤5.5V
; IDDDC≥300mA ;
DDDC≤1A
DCDC=1MHz
to-peak) 3)
I
No load current consumption of IDCNL CC
-
5
10
mA
f
SMPS regulator
Data Sheet
216
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEVR
Table 3-40 EVR13 SMPS (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
SMPS regulator load transient dVout/dIout -25
response CC
Max.
-
25
mV
dI < 200mA ;
f
DCDC=1MHz; tr=0.1µs;
tf=0.1µs; VDDDC=1.3V
-65
-
65
130
1
mV
mV
A
dI < 400mA ;
f
DCDC=1MHz; tr=0.1µs;
tf=0.1µs; VDDDC=1.3V
-130
-
dI < 700mA ;
f
DCDC=1MHz; tr=0.1µs;
tf=0.1µs; VDDDC=1.3V
Maximum output current of the IMAX SR
regulator
-
-
-
limited by thermal
constraints and
component choice
SMPS regulator efficiency
n
DC CC
85
-
%
VIN=3.3V;
I
f
DDDC=300mA;
DCDC=1MHz
VIN=5V; IDDDC=400mA;
DCDC=1.5MHz
VIN=5V; IDDDC=400mA;
DCDC=1MHz
-
-
75
80
-
-
%
%
f
f
1) Incase of SMPS mode, It shall be ensured that the VDD output pin shall be connected on PCB level to all other VDD Input
pins.
2) Incase of fSRI running with max frequency, it shall be ensured that the VDD operating range is limited to 1.235V upto 1.430V.
The DCDC may be configured in this case with a nominal voltage of 1.33V±7.5%. The static accuracy and regulation
parameter ranges remain also valid for this case.
3) If frequency spreading (SDFREQSPRD = 1) is activated, an additional ripple of 1% need to be considered.
Data Sheet
217
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPhase Locked Loop (PLL)
3.18
Phase Locked Loop (PLL)
Table 3-41 PLL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
PLLBASE CC 80
Max.
360
800
24
PLL base frequency
VCO frequency range
VCO Input frequency range
Modulation Amplitude
Peak Period jitter
f
f
f
150
MHz
MHz
MHz
%
VCO SR
REF CC
400
8
-
-
-
-
-
-
MA CC
DP CC
0
2
-200
-5
200
5
ps
Peak Accumulated Jitter
Total long term jitter
DPP CC
ns
without modulation
JTOT CC
-
11.5
ns
including modulation;
MA ≤ 1%
System frequency deviation
f
SYSD CC
-
-
0.01
5.4
%
with active modulation
Modulation variation frequency fMV CC
PLL lock-in time tL CC
2
3.6
-
MHz
µs
11.5
200
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
218
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationERAY Phase Locked Loop (ERAY_PLL)
3.19
ERAY Phase Locked Loop (ERAY_PLL)
Table 3-42 PLL_ERAY
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
PLL Base Frequency of the
ERAY PLL
fPLLBASE_ERA 50
Y CC
200
320
MHz
MHz
MHz
VCO frequency range of the
ERAY PLL
fVCO_ERAY
400
-
-
480
24
SR
VCO input frequency of the
ERAY PLL
f
REF SR
16
Accumulated_Jitter
DP CC
DPP CC
-0.5
-0.8
-
-
0.5
0.8
ns
ns
Accumulated jitter at SYSCLK
pin
PLL lock-in time
tL CC
5.6
-
200
µs
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
219
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationAC Specifications
3.20
AC Specifications
All AC parameters are specified for the complette operating range defined in Chapter 3.4 unless otherwise noted
in colum Note / test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FLEX / VDDP3
90%
90%
10%
10%
VSS
tr
tf
rise_fall
Figure 3-8 Definition of rise / fall times
VEXT/FLEX / VDDP3
Timing
Reference
Points
VEXT/FLEX /VDDP3
V
EXT /FLEX / VDDP3
2
2
VSS
timing_reference
Figure 3-9 Time Reference Point Definition
Data Sheet
220
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationJTAG Parameters
3.21
JTAG Parameters
The following parameters are applicable for communication through the JTAG debug interface. The JTAG module
is fully compliant with IEEE1149.1-2000.
Table 3-43 JTAG
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
25
10
10
-
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
TCK low time
-
TCK clock rise time
TCK clock fall time
4
4
-
-
TDI/TMS setup to TCK rising
edge
6.0
TDI/TMS hold after TCK rising t7 SR
6.0
-
-
ns
edge
TDO valid after TCK falling
edge (propagation delay) 1)
t8 CC
3.0
-
-
-
-
-
ns
ns
ns
CL≤20pF
CL≤50pF
16
-
TDO hold after TCK falling
edge 1)
t
18 CC
2
TDO high impedance to valid t9 CC
-
-
-
-
17.5
17
ns
ns
CL≤50pF
CL≤50pF
from TCK falling edge 1)2)
TDO valid output to high
impedance from TCK falling
edge 1)
t10 CC
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
t1
0.9 VDDP
0.1 VDDP
0.5 VDDP
t5
t4
t2
t3
MC_JTAG_TCK
Figure 3-10 Test Clock Timing (TCK)
Data Sheet
221
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationJTAG Parameters
TCK
TMS
TDI
t6
t7
t6
t7
t9
t8
t10
TDO
t18
MC_JTAG
Figure 3-11 JTAG Timing
Data Sheet
222
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationDAP Parameters
3.22
DAP Parameters
The following parameters are applicable for communication through the DAP debug interface.
Table 3-44 DAP
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DAP0 clock period
DAP0 high time
t
t
t
t
11 SR
12 SR
13 SR
14 SR
6.25
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
2
2
-
-
DAP0 low time
-
DAP0 clock rise time
1
2
1
2
-
f=160MHz
f=80MHz
f=160MHz
f=80MHz
-
DAP0 clock fall time
t
15 SR
-
-
DAP1 setup to DAP0 rising
edge
t
t
t
16 SR
17 SR
19 CC
4
DAP1 hold after DAP0 rising
edge
2
-
-
ns
DAP1 valid per DAP0 clock
period 1)
3
-
-
-
-
-
-
ns
ns
ns
CL=20pF ; f=160MHz
CL=20pF ; f=80MHz
CL=50pF ; f=40MHz
8
10
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VDDP
0.1 VDDP
0.5 VDDP
t15
t14
t12
t13
MC_DAP0
Figure 3-12 Test Clock Timing (DAP0)
DAP0
t16
t17
DAP1
MC_DAP1_RX
Figure 3-13 DAP Timing Host to Device
Data Sheet
223
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationDAP Parameters
t11
DAP1
t19
MC_DAP1_TX
Figure 3-14 DAP Timing Device to Host (DAP1 and DAP2 pins)
Note:The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
Data Sheet
224
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
3.23
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC270 / TC275 / TC277, for 5V power supply.
Note:Pad asymmetry is already included in the following timings.
Table 3-45 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-3
3
0 < CL < 50pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-7
5
-
-
-
-
6
35
-
ns
ns
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
CL=25pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
28
-6
CL=25pF
MRST hold from ASCLKO
latching edge
-
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-46 Master Mode MP+sm/MPRsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
-2
3+0.01 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-10
5
-
-
-
-
10
35
-
ns
ns
ns
ns
CL=50pF
ASLSOn delay from the first
ASCLKO edge
CL=50pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
50
-10
CL=50pF
MRST hold from ASCLKO
latching edge
-
CL=50pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
225
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-47 Master Mode MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-2
3.5+0.035 ns
0 < CL < 200pF
2)
* CL
MTSR delay from ASCLKO
shifting edge
t
t
t
51 CC
510 CC
52 SR
-7
-7
-
-
6
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
6
CL=25pF
MRST setup to ASCLKO
latching edge
30
33 3)
-
-
-
-
ns
ns
CL=25pF, else
CL=25pF, for P14.2,
P14.4, and P15.1
MRST hold from ASCLKO
latching edge
t
53 SR
-5
-
-
ns
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
3) Please note that these pins didn't support the hystereses inactive feature.
Table 3-48 Master Mode MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
4+0.04 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-11
-11
60
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-10
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
226
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-49 Master Mode medium output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-8
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
4+0.04 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-20
-20
70
-
-
-
-
15
20
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-10
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-50 Master Mode weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
1000
-30
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
30+0.15 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-75
-65
510
-50
-
-
-
-
75
65
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
227
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
t50
ASCLKO
MTSR
t51
t51
t500
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-15 ASCLIN SPI Master Timing
Data Sheet
228
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
3.24
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC270 / TC275 / TC277, for 3.3V power supply, Medium
Performance pads, strong sharp edge (MPss), CL=25pF.
Note:Pad asymmetry is already included in the following timings.
Table 3-51 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-5
5
0 < CL < 50pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-12
0
-
-
-
-
12
60
-
ns
ns
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
CL=25pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
50
-5
CL=25pF
MRST hold from ASCLKO
latching edge
-
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-52 Master Mode MP+sm/MPRsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
7
0 < CL < 200pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-17
0
-
-
-
-
17
60
-
ns
ns
ns
ns
CL=50pF
ASLSOn delay from the first
ASCLKO edge
CL=50pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
85
-5
CL=50pF
MRST hold from ASCLKO
latching edge
-
CL=50pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
229
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-53 Master Mode MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-5
7+0.07 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-12
-12
50
-5
-
-
-
-
12
12
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-54 Master Mode MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-5
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
9+0.06 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-19
-19
100
-13
-
-
-
-
17
17
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-55 Master Mode medium output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ASCLKO clock period 1)
t
50 CC
400
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
-6-0.07 *
CL
6+0.07 * ns
CL
0 < CL < 200pF
2)
Data Sheet
230
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-55 Master Mode medium output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-33
-
-
-
-
25
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
-35
120
-13
35
-
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-56 Master Mode weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2000
-110
Max.
-
ASCLKO clock period 1)
t
50 CC
-
-
ns
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
150
0 < CL < 200pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-170
-170
510
-40
-
-
-
-
170
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
170
MRST setup to ASCLKO
latching edge
-
-
MRST hold from ASCLKO
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-57 Master Mode A2ss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
-3
3
2)
MTSR delay from ASCLKO
shifting edge
t
t
51 CC
-4
-5
-
-
4
4
ns
ns
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
510 CC
Data Sheet
231
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-57 Master Mode A2ss output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to ASCLKO
latching edge
t
t
52 SR
53 SR
17
-
-
ns
ns
CL=50pF
CL=50pF
MRST hold from ASCLKO
latching edge
0
-
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-58 Master Mode A2sm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
-4
4
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-8
-8
26
0
-
-
-
-
6
9
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
t50
ASCLKO
t51
t51
t500
MTSR
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-16 ASCLIN SPI Master Timing
Data Sheet
232
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
3.25
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC270 / TC275 / TC277, for 5V pad power supply.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
•
•
LVDSM output pads,LVDSH input pad, master mode, CL=25pF
Medium Performance Plus Pads (MP+):
–
–
–
–
strong sharp edge (MP+ss), CL=25pF
strong medium edge (MP+sm), CL=50pF
medium edge (MP+m), CL=50pF
weak edge (MP+w), CL=50pF
•
•
Medium Performance Pads (MP):
–
–
strong sharp edge (MPss), CL=25pF
strong medium edge (MPsm), CL=50pF
Medium and Low Performance Pads (MP/LP), the identical output strength settings:
–
–
medium edge (LP/MPm), CL=50pF
weak edge (MPw), CL=50pF
Note:Pad asymmetry is already included in the following timings.
Table 3-59 Master Mode Timing, LVDSM output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20 2)
-1
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 3) 4)
500 CC
1
MTSR delay from SCLKO
shifting edge
t
51 CC
-3
-
3
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
0
-
-
-
-
-
30
7
ns
ns
ns
ns
ns
CL=25pF; MPsm
CL=25pF; MPss
MP+ss; CL=25pF
MP+sm; CL=25pF
-5
-4
7
-1
19 5)
15
-
MRST setup to SCLK latching
edge 5)
t
52 SR
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR
edge
-6 5)
-
-
ns
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
4) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
5) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Data Sheet
233
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-60 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-3
3
0 < CL < 50pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-7
-
-
-
-
6
6
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-7
MRST setup to SCLK latching
edge 4)
t
52 SR
27 4)5)
-6 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-61 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
3+0.01 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-10
-
10
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-10
-13
0
-
-
-
10
1
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
40
MP+m, MPm, LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
-10 4)5)
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
234
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-62 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
4+0.04 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-11
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-11
MRST setup to SCLK latching
edge 4)
t
52 SR
60 4)5)
-10 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-63 Master Mode timing MPRm/MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-10
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
10+0.04 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-15
-
-
-
-
19
20
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-20
MRST setup to SCLK latching
edge 4)
t
52 SR
70 4)5)
-10 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
235
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-64 Master Mode Weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
1000
-30
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
30+0.15 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-65
-
-
-
-
65
65
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-70
MRST setup to SCLK latching
edge 4)
t
52 SR
300 4)5)
-40 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-65 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
4 x TMAX
40
Max.
SCLK clock period
SCLK duty cycle
t
t
t
54 SR
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
%
55/t54 SR
56 SR
60
-
MTSR setup to SCLK latching
edge
4 1)
5 1)
5 1)
3 1)
6 1)
9 1)
5 1)
4 1)
8 1)
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hystheresis Inactive
Input Level AL
-
-
Input Level TTL
Hystheresis Inactive
Input Level AL
MTSR hold from SCLK latching t57 SR
edge
-
-
-
Input Level TTL
Hystheresis Inactive
Input Level AL
SLSI setup to first SCLK shift
edge
t
58 SR
-
-
-
Input Level TTL
Only for pin 15.1, AL
-
Data Sheet
236
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-65 Slave mode timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
3 1)
4 1)
8 1)
10
Max.
SLSI hold from last SCLK
latching edge
t
t
59 SR
60 CC
-
-
-
-
-
ns
ns
ns
ns
Hystheresis Inactive
Input Level AL
-
-
Input Level TTL
MRST delay from SCLK shift
edge
70
MP+m/MPRm;
CL=50pF
10
5
-
-
-
50
ns
ns
ns
MP+sm/MPRsm;
CL=50pF
30
MP+ss/MPRss;
CL=25pF
40
300
MP+w/MPRw;
CL=50pF
10
10
5
-
-
-
-
-
70
55
30
300
5
ns
ns
ns
ns
ns
MPm/LPm; CL=50pF
MPsm; CL=50pF
MPss; CL=25pF
40
-
MPw/LPw; CL=50pF
SLSI to valid data on MRST
1) Except pin P15.1.
t
61 SR
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-17 Master Mode Timing
Data Sheet
237
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-18 Slave Mode Timing
3.26
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC270 / TC275 / TC277, for 3.3V pad power supply.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
•
•
LVDSM output pads, LVDSH input pad, master mode, CL=25pF
Medium Performance Plus Pads (MP+):
–
–
–
–
strong sharp edge (MP+ss), CL=25pF
strong medium edge (MP+sm), CL=50pF
medium edge (MP+m), CL=50pF
weak edge (MP+w), CL=50pF
•
•
Medium Performance Pads (MP):
–
–
strong sharp edge (MPss), CL=25pF
strong medium edge (MPsm), CL=50pF
Medium and Low Performance Pads (MP/LP), the identical output strength settings:
–
–
medium edge (LP/MPm), CL=50pF
weak edge (MPw), CL=50pF
Note:Pad asymmetry is already included in the following timings.
Table 3-66 Master Mode Timing, LVDSM output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
2
MTSR delay from SCLKO
shifting edge
t
51 CC
-5
-
5
ns
CL=25pF
Data Sheet
238
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-66 Master Mode Timing, LVDSM output pads for data and clock (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-2
Max.
55
12
12
26
-
SLSOn deviation from the ideal t510 CC
programmed position
-
-
-
-
-
ns
ns
ns
ns
ns
CL=25pF; MPsm
CL=25pF; MPss
MP+ss; CL=25pF
MP+sm; CL=25pF
-9
-7
-2
MRST setup to SCLK latching
edge 4)
t
52 SR
20
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR
edge
-6
-
-
ns
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Table 3-67 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-5
5
0 < CL < 50pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-12
-
-
-
-
12
12
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-12
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-6 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Data Sheet
239
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-68 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
7
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-17
-
17
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-17
-22
0
-
-
-
17
2
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
70
MP+m; MPm; LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
85 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
-10 4)5)
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-69 Master Mode timing MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-5
7+0.07 * ns
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-10
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-10
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-6 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
240
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-70 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-5
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
9+0.06 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-19
-
-
-
-
19
17
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-19
MRST setup to SCLK latching
edge 4)
t
52 SR
100 4)5)
-13 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-71 Master Mode timing MPRm/MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SCLKO clock period 1)
t
t
50 CC
400
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-6-0.07 *
CL
6+0.07 * ns
CL
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-25
-
-
-
-
33
35
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-35
MRST setup to SCLK latching
edge 4)
t
52 SR
120 4)5)
-13 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
241
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-72 Master Mode Weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2000
-110
Max.
-
SCLKO clock period 1)
t
t
50 CC
-
-
ns
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
110
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-170
-
-
-
-
170
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-170
170
MRST setup to SCLK latching
edge 4)
t
52 SR
510 4)5)
-40 4)5)
-
-
MRST hold from SCLK latching t53 SR
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-73 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
4 x TMAX
40
7 1)
9 1)
7 1)
5 1)
11 1)
16 1)
7 1)
Max.
SCLK clock period
SCLK duty cycle
t
t
t
54 SR
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
%
55/t54 SR
56 SR
60
-
MTSR setup to SCLK latching
edge
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hystheresis inactive
Input Level AL
-
-
Input Level TTL
MTSR hold from SCLK latching t57 SR
edge
-
Hystheresis inactive
Input Level AL
-
-
Input Level TTL
SLSI setup to first SCLK shift
edge
t
58 SR
-
Hystheresis inactive
Input Level AL
7 1)
14 1)
-
-
Input Level TTL
11
-
Only for pin P15.1, AL
Data Sheet
242
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-73 Slave mode timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
5 1)
7 1)
Max.
SLSI hold from last SCLK
latching edge
t
t
59 SR
60 CC
-
-
-
-
-
ns
ns
ns
ns
Hystheresis inactive
Input Level AL
-
14 1)
-
Input Level TTL
MRST delay from SCLK shift
edge
13
120
MP+m/MPRm;
CL=50pF
13
6
-
-
-
85
ns
ns
ns
MP+sm/MPRsm;
CL=50pF
50
MP+ss/MPRss;
CL=25pF
70
500
MP+w/MPRw;
CL=50pF
13
13
6
-
-
-
-
-
120
100
52
ns
ns
ns
ns
ns
MPm/LPm; CL=50pF
MPsm; CL=50pF
MPss; CL=25pF
70
-
500
9
MPw/LPw; CL=50pF
SLSI to valid data on MRST
1) Except pin P15.1
t
61 SR
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-19 Master Mode Timing
Data Sheet
243
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-20 Slave Mode Timing
Data Sheet
244
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 5 V Operation
3.27
MSC Timing 5 V Operation
The following section defines the timings for 5V pad power supply.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Table 3-74 LVDS clock/data (LVDS pads in LVDS mode)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-1
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
ns
LVDSM; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
1
LVDSM; 0 < CL < 50pF
4) 5)
SOPx output delay 6)
t
t
44 CC
-3
-4
-4
-3
-3
-
-
-
-
-
4
ns
ns
ns
ns
ns
LVDSM; CL=50pF;
option EN01
4.5
5
LVDSM; CL=50pF;
option EN01D
ENx output delay 6)
45 CC
MP+ss/MPRss; option
EN01; CL=25pF
7
MP+ss/MPRss; option
EN01; CL=50pF
11
MP+sm/MPRsm;
option EN01D;
CL=50pF
-2
-2
-3
-7
-5
-4
-7
-
-
-
-
-
-
-
9
ns
ns
ns
ns
ns
ns
ns
MP+ss/MPRss; option
EN23; CL=25pF
11
11
2
MP+ss/MPRss; option
EN23; CL=50pF
MPss; option EN01;
CL=50pF
MP+ss/MPRss; option
EN01; CL=0pF
3
MP+sm/MPRsm;
option EN01D; CL=0pF
5
MP+ss/MPRss; option
EN23; CL=0pF
4
MPss; option EN01;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
Data Sheet
245
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 5 V Operation
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Data Sheet
246
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 5 V Operation
Timing Options for t45
The wiring shown in the Figure 3-21 provides three useful timing options for t45. depending on the signals selected
with the alternate output lines (ALT1 to ALT7) in the ports:
•
•
•
EN01 - FCLN, SON, EN0, EN1
EN01D - FCLND, SOND, EN0, EN1 - t45 window shifted to the left
EN23 - FCLN, SON, EN2, EN3 - t45 window shifted to the right
- t45 reference timing
The timings corresponding to EN01, EN01D, and EN23 are defined in the LVDS. In order to use the EN23 timings,
the application should use the EN2 and EN3 outputs of the MSC module.
ALT1
FCLN ALTx
ALTy
LVDSM
FCLP
FCLN
FCLND
ALT7
PAD
ALT1
SON ALTx
ALTy
LVDSM
SOP
SON
SOND
ALT7
PAD
ALT1
ALTx
ALTy
EN0
EN1
CMOS
ALT7
PAD
EN2
EN3
ALT1
ALTx
ALTy
CMOS
MSC
ALT7
PAD
_DoublePath_4a.vsd
Figure 3-21 Timing Options for t45
Table 3-75 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
MPss; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
6+0.035 * ns
MPss; 0 < CL < 100pF
4) 5)
CL
SOPx output delay 6)
t
44 CC
-4
-
7
ns
MPss; CL=50pF
Data Sheet
247
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 5 V Operation
Table 3-75 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ENx output delay 6)
t
45 CC
-5
-
7
ns
ns
MP+ss/MPRss;
CL=50pF
-2
-
15
MP+sm/MPRsm;
CL=50pF
-4
0
-
-
10
30
ns
ns
MPss; CL=50pF
MPsm; CL=50pF;
except pin P13.0
0
-
-
-
-
31
45
2
ns
ns
ns
ns
MPsm; CL=50pF; pin
P13.0
6
MPm/MP+m/MPRm;
CL=50pF
-11
-4
MP+ss/MPRss;
CL=0pF
7
MP+sm/MPRsm;
CL=0pF
-10
-1
-
-
-
2
ns
ns
ns
MPss; CL=0pF
MPsm; CL=0pF
16
18
-2
MP+m/MPm/MPRm;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) FCLP signal high and low can be minimum 1 * TMSC
.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Table 3-76 MP+sm/MPRsm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
-
-
ns
MP+sm/MPRsm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-2
-5
3+0.01 * ns
CL
MP+sm/MPRsm; 0 <
CL < 200pF
2) 3)
SOPx output delay 4)
Data Sheet
t
44 CC
7
ns
MP+sm; CL=50pF
248
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 5 V Operation
Table 3-76 MP+sm/MPRsm clock/data (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-13
-5
Max.
2 5)
ENx output delay 4)
t
45 CC
-
-
ns
ns
MPss; CL=50pF
11
MP+sm/MPRsm;
CL=50pF
1
4
-
-
24
37
ns
ns
MPsm; CL=50pF
MP+m/MPm/MPRm;
CL=50pF
-19
-13
-5
-
-
-
-
-1
2
ns
ns
ns
ns
MPss; CL=0pF
MP+sm; CL=0pF
MPsm; CL=0pF
8
-5
10
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
5) If EN1 is configured to P13.0 the max limt is increased by 0.5ns to 2.5ns.
Table 3-77 MPm/MP+m/MPRm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
MPm/MP+m/MPRm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-8
-
15+0.04 * ns
CL
MPm/MP+m; 0 < CL <
200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-11
-15
-
-
9
ns
ns
MPm/MP+m; CL=50pF
11
MPm/MP+m/MPRm;
CL=50pF
-33
-
-4
ns
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
Data Sheet
249
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TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
t40
t400
FCLP
SOP
t44
t44
t45
t45
0.5 VEXT/FLEX
EN
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-22 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
3.28
MSC Timing 3.3 V Operation
The following section defines the timings for 3.3V pad power supply.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Mapping A, Combo Pads in LVDS Mode or CMOS Mode
The timing applies for the LVDS pads in LVDS operating mode:
•
•
The LVDSM output pads for clock and data signals set in LVDS mode
The CMOS MP pads for enable signals, with strong driver sharp edge (MPss) or strong driver medium edge
(MPsm).
Table 3-78 LVDS clock/data (LVDS pads in LVDS mode)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
ns
LVDSM; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
2
LVDSM; 0 < CL < 50pF
4) 5)
SOPx output delay 6)
t
44 CC
-5
-7
-
-
5
7
ns
ns
LVDSM; CL=50pF;
option EN01
LVDSM; CL=50pF;
option EN01D
Data Sheet
250
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-78 LVDS clock/data (LVDS pads in LVDS mode) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ENx output delay 6)
t
45 CC
-7
-
-
-
10
ns
ns
ns
MP+ss/MPRss; option
EN01; CL=25pF
-5
-5
13
26
MP+ss/MPRss; option
EN01; CL=50pF
MP+sm/MPRsm;
option EN01D;
CL=50pF
-4
-
-
-
-
-
-
-
16
17
19
4
ns
ns
ns
ns
ns
ns
ns
MP+ss/MPRss; option
EN23; CL=25pF
-4
MP+ss/MPRss; option
EN23; CL=50pF
-5
MPss; option EN01;
CL=50pF
-12
-9
MP+ss/MPRss; option
EN01; CL=0pF
11
9
MP+sm/MPRsm;
option EN01D; CL=0pF
-7
MP+ss/MPRss; option
EN23; CL=0pF
-12
7
MPss; option EN01;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Table 3-79 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-5
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
MPss; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
7+0.07 * ns
MPss; 0 < CL < 100pF
4) 5)
CL
Data Sheet
251
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-79 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-7
Max.
12
SOPx output delay 6)
ENx output delay 6)
t
t
44 CC
45 CC
-
-
ns
ns
MPss; CL=50pF
-9
12
MP+ss/MPRss;
CL=50pF
-4
-
26
ns
MP+sm/MPRsm;
CL=50pF
-7
0
-
-
17
54
ns
ns
MPss; CL=50pF
MPsm; CL=50pF;
except pin P13.0
0
-
-
-
-
58
77
4
ns
ns
ns
ns
MPsm; CL=50pF; pin
P13.0
4
MPm/MP+m/MPRm;
CL=50pF
-19
-7
MP+ss/MPRss;
CL=0pF
12
MP+sm/MPRsm;
CL=0pF
-17
-2
-
-
-
4
ns
ns
ns
MPss; CL=0pF
MPsm; CL=0pF
28
31
-4
MP+m/MPm/MPRm;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) FCLP signal high and low can be minimum 1 * TMSC
.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Mapping B, CMOS MP Pads
This timing applies for the dedicated CMOS pads, pin Mapping B:
•
•
MP strong sharp (MPss) output pads for the clock and the data signals
MP strong sharp or strong medium (MPss or MPsm) output pads for enable signals
Data Sheet
252
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-80 MP+sm/MPRsm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
ns
MP+sm/MPRsm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-3
-
7
MP+sm/MPRsm; 0 <
CL < 200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-9
-
-
-
12
4
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
-20
-9
19
MP+sm/MPRsm;
CL=50pF
0
0
-
-
44
63
ns
ns
MPsm; CL=50pF
MP+m/MPm/MPRm;
CL=50pF
-33
-23
-
-
0
4
ns
ns
MPss; CL=0pF
MP+sm/MPRsm;
CL=0pF
-9
-9
-
-
14
17
ns
ns
MPsm; CL=0pF
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
Table 3-81 MPm/MP+m/MPRm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
MPm/MP+m/MPRm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-6-0.07 *
CL
-
6+0.07 * ns
CL
MPm/MP+m/MPRm; 0
< CL < 200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-19
-19
-
-
17
20
ns
ns
MPm/MP+m; CL=50pF
MPm/MP+m/MPRm;
CL=50pF
-57
-
0
ns
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
253
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
4) From FCLP rising edge.
t40
t400
FCLP
t44
t44
SOP
EN
t45
t45
0.5 VEXT/FLEX
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-23 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
Data Sheet
254
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29
Ethernet Interface (ETH) Characteristics
3.29.1
ETH Measurement Reference Points
ETH Clock
ETH I/O
1.4
2.0
V
1.4 V
V
2.0
V
0.8
V
0.8
V
tR
tF
ETH_Testpoints.vsd
Figure 3-24 ETH Measurement Reference Points
Data Sheet
255
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29.2
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 3-82 ETH Management Signal Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
400
160
160
10
Max.
ETH_MDC period
ETH_MDC high time
ETH_MDC low time
t1 CC
t2 CC
t3 CC
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
-
-
ETH_MDIO setup time (output) t4 CC
ETH_MDIO hold time (output) t5 CC
ETH_MDIO data valid (input) t6 SR
-
10
-
0
300
t1
t3
t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4
t5
ETH_MDIO
(output )
Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input )
Valid Data
ETH_Timing-Mgmt.vsd
Figure 3-25 ETH Management Signal Timing
Data Sheet
256
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29.3
ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.
Table 3-83 ETH MII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Clock period
t7 SR
40
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF;
baudrate=100Mbps
400
14
-
CL=25pF;
baudrate=10Mbps
Clock high time
Clock low time
t8 SR
t9 SR
26
CL=25pF;
baudrate=100Mbps
140 1)
14
260 2)
26
CL=25pF;
baudrate=10Mbps
CL=25pF;
baudrate=100Mbps
140 1)
260 2)
CL=25pF;
baudrate=10Mbps
Input setup time
Input hold time
t
t
t
10 SR
11 SR
12 CC
10
10
0
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
-
Output valid time
25
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t7
t9
t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t10
t11
ETH_MII_RXD[3:0]
ETH_MII_RX_DV
ETH_MII_RX_ER
(sourced by PHY )
Valid Data
ETH_MII_TX_CLK
t12
ETH_MII_TXD[3:0]
ETH_MII_TXEN
Valid Data
(sourced by controller )
ETH_Timing-MII.vsd
Figure 3-26 ETH MII Signal Timing
Data Sheet
257
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29.4
ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.
Table 3-84 ETH RMII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ETH_RMII_REF_CL clock
period
t
13 CC
20
-
-
-
-
-
ns
ns
ns
ns
CL=25pF; 50ppm
CL=25pF
ETH_RMII_REF_CL clock high t14 CC
time
7 1)
7 1)
4
13 2)
13 2)
-
ETH_RMII_REF_CL clock low t15 CC
time
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV,
ETHRXER; setup time
t
t
16 CC
17 CC
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV,
ETHRXER; hold time
2
-
-
ns
CL=25pF
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t13
t15
t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t16
t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0],
ETHCRSDV,
ETHRXER
Valid Data
ETH_Timing-RMII.vsd
Figure 3-27 ETH RMII Signal Timing
Data Sheet
258
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationE-Ray Parameters
3.30
E-Ray Parameters
The timings of this section are valid for the strong driver and either sharp edge settings of the output drivers with
CL = 25 pF. For the inputs the hysteresis has to be configured to inactive.
Table 3-85 Transmit Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise time of TxEN
Fall time of TxEN
tdCCTxENRise2
5 CC
-
-
-
-
9
ns
ns
ns
CL=25pF
tdCCTxENFall25
CC
-
-
9
9
CL=25pF
Sum of rise and fall time
tdCCTxRise25+
20% - 80%; CL=25pF
dCCTxFall25
CC
Sum of delay between TP1_FF tdCCTxEN01
-
-
-
-
25
25
ns
ns
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxEN
CC
Sum of delay between TP1_FF tdCCTxEN10
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxEN
CC
Asymmetry of sending
t
tx_asym CC -2.45
-
-
2.45
25
ns
ns
CL=25pF
Sum of delay between TP1_FF tdCCTxD01
-
-
-
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxD
CC
Sum of delay between TP1_FF tdCCTxD10
-
-
25
9
ns
ns
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxD
CC
TxD signal sum of rise and fall ttxd_sum CC
time at TP1_BD
Table 3-86 Receive Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -30.5
ept25 SR
-
43.0
ns
ns
%
%
CL=25pF
CL=15pF
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -31.5
ept15 SR
-
-
-
44.0
70
Threshold for detecting logical TuCCLogic1
high SR
Threshold for detecting logical TuCCLogic0
35
30
65
low
SR
Data Sheet
259
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationE-Ray Parameters
Table 3-86 Receive Parameters (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sum of delay between TP4_CC tdCCRxD01
-
-
10
ns
and TP4_FF and delays
derived from TP4_FFi, rising
edge of RxD
CC
Sum of delay between TP1_CC tdCCRxD10
-
-
10
ns
and TP1_CC and delays
derived from TP4_FFi, falling
edge of RxD
CC
Data Sheet
260
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationHSCT Parameters
3.31
HSCT Parameters
Table 3-87 HSCT - Rx/Tx setup timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
60
RX o/p duty cycle
Bias startup time
DCrx CC
-
%
t
bias CC
5
10
µs
Bias distributor waking
up from power down
and provide stable
Bias.
RX startup time
TX startup time
trxi CC
ttx CC
-
-
5
5
-
-
µs
µs
Wake-up RX from
power down.
Wake-up TX from
power down.
Table 3-88 HSCT - Rx parasitics and loads
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Capacitance total budget
Ctotal CC
-
3.5
5
pF
Total Budget for
complete receiver
including silicon,
package, pins and
bond wire
Parasitic inductance budget
Htotal CC
-
5
-
nH
Table 3-89 LVDSH - Reduced TX and RX (RED)
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Output differential voltage
V
OD CC
150
200
285
mV
Rt = 100 Ohm ±20%
@2pF
Output voltage high
Output voltage low
V
V
OH CC
OL CC
-
-
1463
-
mV
mV
V
Rt = 100 Ohm ±20%
Rt = 100 Ohm ±20%
937
1.08
-
Output offset (Common mode) VOS CC
voltage
1.2
1.32
Rt = 100 Ohm ±20%
@2pF
Input voltage range
VI SR
-
-
-
-
1.6
-
V
Absolute max = 1.6 V +
(285mV/2) = 1.743
0.15
-100
V
Absolute min = 0.15 V -
(285 mV /2) = 0 V
Input differential threshold
Data frequency
V
idth SR
100
mV
100 mV for 55% of bit
period; Note Absolute
Value (Vidth - Vidthl)
DR CC
5
-
320
Mbps
Data Sheet
261
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationHSCT Parameters
Table 3-89 LVDSH - Reduced TX and RX (RED) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
90
80
-
Max.
110
120
2
Receiver differential input
impedance
Rin CC
100
Ohm
Ohm
V/ns
mV
0 V < VI < 1.6V
100
1.6 V < VI < 2.0V
Slew rate
SRtx CC
-
-
Change in VOS between 0 and dVOS CC
1
-
50
Peak to peak
(including DC
transients).
Change in Vod between 0 and dVod CC
1
-
-
50
mV
Peak to peak
(including DC
transients)
Fall time 1)
Rise time 1)
t
t
fall CC
rise CC
0.26
0.26
-
-
1.2
1.2
ns
ns
Rt = 100 Ohm ±20%
@2pF
Rt = 100 Ohm ±20%
@2pF
1) Rise / fall times are defined for 10% - 90% of VOD
Table 3-90 HSCT PLL
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
12.5
10
-
Typ.
Max.
320
PLL frequency range
PLL input frequency
PLL lock-in time
f
f
t
PLL CC
REF CC
LOCK CC
320
MHz
MHz
µs
-
-
-
20
50
Bit Error Rate based on 10 MHz BER10 CC
reference clock at Slave PLL
side
-
10EXP-9
-
Bit Error Rate based
on Slave interface
reference clock at 10
MHz
Bit Error Rate based on 20 MHz BER20 CC
reference clock at Slave PLL
side
-
-
-
-
10EXP-
12
-
Bit Error Rate based
on Slave interface
reference clock at 20
MHz
Absolute RMS Jitter (TX out)
JABS10 CC
-125
-85
125
85
ps
ps
Measured at link TX
out; valid for
Reference frequency
at 10 MHz
Absolute RMS Jitter (TX out)
JABS20 CC
Measured at link TX
out; valid for
Reference frequency
at 20 MHz
Data Sheet
262
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationHSCT Parameters
Table 3-90 HSCT PLL (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Accumulated RMS Jitter (RX
side)
J
ACC10 CC
-
-
-
-
145
ps
Measured at link RX
input, based on 5000
measures, each 300
clock cycles; valid for
Reference frequency
at 10 MHz
Accumulated RMS Jitter (link
RX side)
JACC20 CC
-
-
115
ps
Measured at link RX
input, based on 5000
measures, each 300
clock cycles; valid for
Reference frequency
at 20 MHz
Total Jitter peak to peak
TJpp CC
2083
ps
Total Jitter as sum of
deterministic jitter and
random jitter
Table 3-91 HSCT Sysclk
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
20
1
Frequency
f
SYSCLK CC 10
-
-
-
-
-
-
MHz
%
Frequency error
Duty Cycle
dfERR CC -1
DCsys CC 45
55
-
%
Load impedance
Load capacitance
Integrated phase noise
R
LOAD CC
LOAD CC
PN CC
10
-
kOhm
pF
C
10
-58
I
-
dB
single sideband phase
noise in 10 kHz to 10
Mhz at 20 MHz SysClk
Data Sheet
263
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
3.32
Inter-IC (I2C) Interface Timing
This section defines the timings for I2C in the TC270 / TC275 / TC277.
All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-92 I2C Standard Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
-
-
300
ns
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
4.7
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
-
-
-
-
-
-
-
1000
ns
µs
ns
µs
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data hold time
t3
t4
t5
t6
t7
0
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
250
4.7
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Hold time for the (repeated)
START condition
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
264
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
Table 3-92 I2C Standard Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Set-up time for (repeated)
START condition
t8
4.7
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
4
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Table 3-93 I2C Fast Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
20+0.1*C -
300
ns
Measured with a pull-
up resistor of 4.7
b
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
1.3
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
20+0.1*C -
300
ns
µs
ns
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
b
Data hold time
t3
t4
t5
t6
0
-
-
-
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
100
1.3
0.6
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
265
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
Table 3-93 I2C Fast Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Hold time for the (repeated)
START condition
t7
0.6
-
-
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for (repeated)
START condition
t8
0.6
0.6
-
-
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
266
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationFlash Target Parameters
3.33
Flash Target Parameters
Program Flash program and erase operation is only allowed up the TJ = 150°C.
Table 3-94 FLASH
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program Flash Erase Time per tERP CC
logical sector
-
-
-
1
-
s
s
cycle count < 1000
0.207 +
0.003 * (S
[KByte]) /
(fFSI
cycle count < 1000, for
sector of size S
[MHz])1)
Program Flash Erase Time per tMERP CC
Multi-Sector Command
-
-
-
1
-
s
s
Forconsecutivelogical
sectors in a physical
sector, cycle count <
1000
0.207 +
0.003 * (S
[KByte]) /
(fFSI
Forconsecutivelogical
sector range of size S
in a physical sector,
cycle count < 1000
[MHz])1)
Program Flash program time
per page in 5 V mode
t
t
t
t
PRP5 CC
PRP3 CC
PRPB5 CC
PRPB3 CC
-
-
-
-
-
-
-
-
-
-
50 +
3000/(fFSI
[MHz])
µs
µs
µs
µs
s
32 Byte
32 Byte
256 Byte
256 Byte
Program Flash program time
per page in 3.3 V mode
81 +
3400/(fFSI
[MHz])
Program Flash program time
per burst in 5 V mode
125 +
9500/(fFSI
[MHz])
Program Flash program time
per burst in 3.3 V mode
410 +
12000/(fF
SI [MHz])
Program Flash program time
for 1 MByte with burst
programming in 3 V mode
excluding communication
tPRPB3_1MB
CC
2.2
0.9
3.6
Derived value for
documentation
purpose, valid for fFSI
=
=
=
100MHz
Program Flash program time
for 1 MByte with burst
programming in 5 V mode
excluding communication
tPRPB5_1MB
CC
-
-
-
-
s
s
Derived value for
documentation
purpose, valid for fFSI
100MHz
Program Flash program time
for complete PFlash with burst CC
programming in 5 V mode
excluding communication
tPRPB5_PF
Derived value for
documentation
purpose, valid for fFSI
100MHz
Data Sheet
267
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationFlash Target Parameters
Table 3-94 FLASH (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Write Page Once adder
t
ADD CC
-
-
15 +
500/(fFSI
[MHz])
µs
Adder to Program
Time when using Write
Page Once
Program Flash suspend to read tSPNDP CC
latency
-
-
12000/(fF µs
SI [MHz])
For Write Burst, Verify
Erased and for multi-
(logical) sector erase
commands
Data Flash Erase Time per
Sector 2)
t
t
ERD CC
-
-
-
0.12 +
0.08/(fFSI
[MHz])1)
-
s
s
s
cycle count < 1000
0.57 +
0.928 +
cycle count < 125000
0.15/(fFSI 0.15/(fFSI
[MHz])1)
[MHz])
Data Flash Erase Time per
Multi-Sector Command 2)
MERD CC
0.12 +
-
Forconsecutivelogical
sector range of size S,
cycle count < 1000
0.01 * (S
[KByte]) /
(fFSI
[MHz])1)
-
0.57 +
0.019 * (S 0.019 * (S
[KByte]) / [KByte]) /
0.928 +
s
Forconsecutivelogical
sector range of size S,
cycle count < 125000
(fFSI
(fFSI
[MHz])
[MHz])1)
Data Flash erase disturb limit
N
DFD CC
-
-
-
-
50
cycles
µs
Program time data flash per
page 3)
t
PRD CC
50 +
2500/(fFSI
[MHz]) 3)
8 Byte
Complete Device Flash Erase
Time PFlash and DFlash 4)
t
ER_Dev CC
-
-
-
-
9
s
Derived value for
documentation
purpose (excl. UCBs
and HSMs), valid for
f
FSI = 100MHz
Data Flash program time per
burst 3)
t
t
PRDB CC
96 +
4400/(fFSI
[MHz]) 3)
µs
32 Bytes
Data Flash suspend to read
latency
SPNDD CC
-
-
-
-
-
12000/(fF µs
SI [MHz])
Wait time after margin change tFL_MarginDel
-
10
-
µs
CC
Program Flash Retention Time, tRET CC
Sector
20
years
Max. 1000
erase/program cycles
Data Flash Endurance per
EEPROMx sector 5)
NE_EEP10
CC
125000
-
cycles Max. data retention
time 10 years
Data Sheet
268
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationFlash Target Parameters
Table 3-94 FLASH (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
E_HSM CC 125000
Max.
Data Flash Endurance per
HSMx sector 5)
N
-
-
cycles Max. data retention
time 10 years
UCB Retention Time
t
RTU CC
20
-
-
years
Max. 100
erase/program cycles
per UCB, max 400
erase/program cycles
in total
Data Flash access delay
Data Flash ECC Delay
t
t
t
t
DF CC
-
-
-
-
-
-
-
-
100
20
ns
ns
ns
ns
see
PMU_FCON.WSDFLA
SH
DFECC CC
see
PMU_FCON.WSECD
F
Program Flash access delay
Program Flash ECC delay
PF CC
30
see
PMU_FCON.WSPFLA
SH
PFECC CC
10
see
PMU_FCON.WSECP
F
Number of erase operations on NERD0 CC
DF0 over lifetime
-
-
-
-
-
-
750000
500000
150
cycles
cycles
°C
Number of erase operations on NERD1 CC
DF1 over lifetime
Junction temperature limit for
PFlash program/erase
operations
TJPFlash SR
1) All typical values were characterised, but are not tested. Typical values are safe median values at room temperature
2) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase
processes may be increased by up to 50%.
3) Time is not dependent on program mode (5V or 3.3V).
4) Using 512 KByte erase commands.
5) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
Data Sheet
269
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPackage Outline
3.34
Package Outline
Figure 3-28 Package Outlines PG-LQFP-176-22
Table 3-95 Exposed Pad Dimensions
Ax (nominal EPad size)
7.9 mm ± 50 µm
7.9 mm ± 50 µm
8.7 mm ± 50 µm
8.7 mm ± 50 µm
Ay (nominal EPad size)
Ex (solder able EPad size)
Ey (solder able EPad size)
292 x
M
0.5 ±0 .0 5
1.7 MAX
0.15
0.08
C
C
A B
17 ±0.1
M
B
A
20
19
18
0.1 C
17
16
15
14
13
12
11
10
9
CODE
8
7
292x
0.15
6
5
4
3
COPLANARITY
2
1
Y W V U T R P N M L
K J HG F E D C B A
INDEX
INDEX MARKING
(LASERED )
0.8
MARKING
19 x 0.8 = 15.2
C
0.33 MIN
STANDOFF
Figure 3-29 Package Outlines LF-BGA-292-6
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
Data Sheet
270
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPackage Outline
3.34.1
Package Parameters
Table 3-96 Thermal Characteristics of the Package
Device
Package
RQJCT1)
RQJCB1) RQJA
Unit
Note
TC275
PG-LQFP-176-22
9,6
1,25
14,72)
K/W
with soldered
exposed pad
TC277
LF-BGA-292-6
5,1
7,2
15,83)
K/W
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the
thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal
resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT
,
R
TCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA * PD, where the RTJA is the total
thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from
the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
2) Value is defined in accordance with JEDEC JESD51-3, JESD51-5, and JESD51-7.
3) Value is defined in accordance with JEDEC JESD51-1.
3.34.2
TC270 Carrier Tape
Figure 3-30 Carrier Tape Dimenions
Data Sheet
271
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationPackage Outline
Table 3-97 TC270 Chip Dimenions
Device
A
B
T
TC270
7,590 mm
6,930 mm
0,3 mm
Data Sheet
272
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
Electrical SpecificationQuality Declarations
3.35
Quality Declarations
Table 3-98 Quality Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
24500
2000
Operation Lifetime
tOP
-
-
-
-
hour
V
ESD susceptibility according to VHBM
Conforming to
Human Body Model (HBM)
JESD22-A114-B
ESD susceptibility of the LVDS VHBM1
pins
-
-
-
-
500
500
V
V
ESD susceptibility according to VCDM
for all other balls/pins;
conforming to
Charged Device Model (CDM)
JESD22-C101-C
-
-
-
-
750
3
V
for corner balls/pins;
conforming to
JESD22-C101-C
Moisture Sensitivity Level
MSL
Conforming to Jedec
J-STD--020C for 240C
Data Sheet
273
V 1.0 2017-01
TC270 / TC275 / TC277 DC-Step
HistoryChanges from TC27xDB_v10 to 1.0
4
History
4.1
Changes from TC27xDB_v10 to 1.0
•
•
Replace PG-LQFP-176-18 with correct package LF-BGA-292-6 in table 1
VADC
–
–
–
Add parameter tWU
Add parameter RMDU
Add parameter RMDD
Data Sheet
274
V 1.0 2017-01
w w w . i n f i n e o n . c o m
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