SAK-TC364DP-64F300W AA [INFINEON]
SAK-TC364DP-64F300W AA belongs to the AURIX™ TC36xDP family. AURIX™ second generation (TC3xx) comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive and industrial trends and challenges. In terms of performance, T36xDP offers 2 cores running at 300 MHz and up to 672 KBytes embedded RAM, 4MB of flash and consuming below 2W.;
| 型号： | SAK-TC364DP-64F300W AA |
| 厂家： | 
Infineon |
| 描述： | SAK-TC364DP-64F300W AA belongs to the AURIX™ TC36xDP family. AURIX™ second generation (TC3xx) comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive and industrial trends and challenges. In terms of performance, T36xDP offers 2 cores running at 300 MHz and up to 672 KBytes embedded RAM, 4MB of flash and consuming below 2W. |
| 文件： | 总480页 (文件大小：18716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Bit
Microcontroller
TC36x
32-Bit Single-Chip Microcontroller
AA-Step
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1, 2021-03
Microcontrollers
OPEN MARKET VERSION
Edition 2021-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2021 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
OPEN MARKET VERSION
TC36x AA-Step
Revision History
Page or Item
Subjects (major changes since previous revision)
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
V 0.4, 2018-08
V 0.6, 2019-02
V 0.7, 2019-11
V 1.0, 2020-04
V 1.1, 2021-03
Data Sheet
3
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
4
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
TC36x Pin Definition and Functions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LFBGA-292 Package Variant Pin Configuration of TC36x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LFBGA-180 Package Variant Pin Configuration of TC36x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP-176 Package Variant Pin Configuration of TC36x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
LQFP-144 Package Variant Pin Configuration of TC36x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
TQFP-144 Package Variant Pin Configuration of TC36x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Sequence of Pads in Pad Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
High performance LVDS Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Power Supply Infrastructure and Supply Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Supply Ramp-up and Ramp-down Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Single Supply mode (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Single Supply mode (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
External Supply mode (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
External Supply mode (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
System Phase Locked Loop (SYS_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Peripheral Phase Locked Loop (PER_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 448
ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
ETH RGMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
3.8
3.9
3.10
3.11
3.12
3.13
3.13.1
3.13.1.1
3.13.1.2
3.13.1.3
3.13.1.4
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.24.1
3.24.2
3.24.3
3.24.4
3.24.5
3.25
3.26
3.27
3.28
Data Sheet
5
V 1.1 2021-03
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TC36x AA-Step
3.29
3.30
3.30.1
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
4
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Changes from Version 0.4 to Version 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Changes from Version 0.6 to Version 0.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Changes from Version 0.7 to Version 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Changes from Version 1.0 to Version 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
4.1
4.2
4.3
4.4
Data Sheet
6
V 1.1 2021-03
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TC36x AA-Step
Summary of Features
1
Summary of Features
The TC36x product family has the following features:
•
•
High Performance Microcontroller with two CPU cores
Two 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features:
–
–
–
–
–
–
–
–
–
–
–
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Multiply-accumulate unit able to sustain 2 MAC operations per cycle
Fully pipelined Floating point unit (FPU)
up to 300 MHz operation at full temperature range
up to 192 Kbyte Data Scratch-Pad RAM (DSPR)
up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
up to 64 Kbyte Data RAM (DLMU)
32 Kbyte Instruction Cache (ICACHE)
16 Kbyte Data Cache (DCACHE)
•
•
Lockstepped shadow cores for all TC1.6.2P
Multiple on-chip memories
–
–
–
–
All embedded NVM and SRAM are ECC protected
up to 4 Mbyte Program Flash Memory (PFLASH)
up to 128 kbyte Data Flash Memory (DFLASH 0) usable for EEPROM emulation
BootROM (BROM)
•
•
•
64-Channel DMA Controller with safe data transfer
Sophisticated interrupt system (ECC protected)
High performance on-chip bus structure
–
–
–
64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
SRI to SPB bus bridges (SFI Bridge)
•
•
•
•
•
Optional Hardware Security Module (HSM) on some variants
Safety Management Unit (SMU) handling safety monitor alarms
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
Hardware I/O Monitor (IOM) for checking of digital I/O
Versatile On-chip Peripheral Units
–
12 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
–
–
–
–
–
–
–
4 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
1 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
1 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
2 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering
10 Single Edge Nibble Transmission (SENT) channels for connection to sensors
1 FlexRayTM module with 2 channels (E-Ray) supporting V2.1
One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management
Data Sheet
7
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TC36x AA-Step
Summary of Features
–
–
–
–
–
–
One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
One General Purpose 12 Timer Unit (GPT120)
2 channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
1 Peripheral Sensor Interface with Serial PHY (PSI5-S)
1 Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
1 IEEE802.3 Ethernet MAC with RGMII, RMII and MII interfaces (ETH)
•
•
Versatile Successive Approximation ADC (VADC)
–
–
Cluster of 8 independent ADC kernels
Input voltage range from 0 V to 5.5V (ADC supply)
Delta-Sigma ADC (DSADC)
4 channels
–
•
•
•
•
•
•
•
•
Digital programmable I/O ports
On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
Power Management System and on-chip regulators
Clock Generation Unit with System PLL and Peripheral PLL
Embedded Voltage Regulator
Qualified for automotive application according to AEC-Q100 (only applicable after delivery release of the
corresponding sales codes)
•
ISO 26262 Safety Element out of Context for safety requirements up to ASIL D (only applicable for sales codes
listed within a released Safety Package Release Note from IFX)
Data Sheet
8
V 1.1, 2021-03
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TC36x AA-Step
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply voltage
The package and the type of delivery.
Table 1-1 Platform Feature Overview
Feature
TC36x
CPUs
Type
TC1.6.2
Cores / Checker Cores
Max. Freq.
Program
2 / 2
300 MHz
Cache per CPU
SRAM per CPU
32 KB
Data
16 KB
PSPR
32 KB
DSPR
192 KB
DLMU
64 KB
Program Flash
Size
4 MB
Banks
2 x 2 MB
Data Flash
DMA
Size (single-ended)
Channels
128 kB (DF0) + 128 KB (DF1)
64
CONVCTRL
EVADC
Modules
1
Primary Groups/Channels
Secondary Groups/Channels
Fast Compare Channels
Channels
4 / 32
2 / 32
2
EDSADC
GTM
4
Clusters
4 @ 200MHz
TIM (8 ch)
3
TOM (16 ch)
ATOM (8 ch)
MCS (8 ch)
CMU / ICM
PSM
2
4
3
1 / 1
1
TBU channels1)
4 (TBU0-3)
SPE
2
CMP / MON
BRC / DPLL
CDTM modules
DTM modules
GPT12
1 / 1
1 / 1
4
12 (4 on TOM, 8 on ATOM)
Timer
1
1
2
CCU6
STM
Modules
Data Sheet
9
V 1.1, 2021-03
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TC36x AA-Step
Summary of Features
Table 1-1 Platform Feature Overview (cont’d)
Feature
TC36x
FlexRay
Modules
1
Channels
2
CAN
Modules
2
Nodes
2 x 4
1
of which support TT-CAN
Modules
QSPI
4
HSCI Channels
Modules
0
ASCLIN
12
1
I2C
Interfaces
SENT
Channels
10
2
PSI5
Modules
PSI5-S
Modules
1
HSSL
Channels
1
MSC
Channels
1
EBU
External Bus
eMMC/SD Interface
Modules
0
SDMMC
0
Ethernet (10/100Mbit/1Gbit)
1
FCE
Modules
SMU
1
Safety Support
yes
yes
0
IOM
SPU
Modules
Modules
Modules
HSM+
RIF
0
HSPDM
Security
Debug
0
1
OCDS
yes
no
no
-
MCDS
miniMCDS
miniMCDS TRAM
AGBT
no
Low Power Features
Packages
Standby RAM
SCR
2 (DLMU0 + DLMU1)
yes
LFBGA-292 / LFBGA-180 /
LQFP-176 /LQFP-144 / TQFP-
144
Type
I/O
Type
5 V CMOS / 3.3 V CMOS / LVDS
−40 … +150°C
Tambient
Range
1) TBU3 has special purpose as angle clock.
Data Sheet
10
V 1.1, 2021-03
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TC36x AA-Step
TC36x Pin Definition and Functions:
2
TC36x Pin Definition and Functions:
The following figures are showing the TC36x Logic Symbols for the package variants:
•
•
•
•
•
LFBGA-292 (Figure 2-1)
LFBGA-180 (Figure 2-2)
LQFP-176 (Figure 2-3)
LQFP-144 (Figure 2-4)
TQFP-144 (Figure 2-5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
NC1
VEXT
P10.7
P10.6
P10.2
P10.3
P10.0
P11.11
P11.9
P11.2
P13.3
P13.1
P14.8
P14.5
P14.1
P15.6
P15.4
P15.1
VDDP3
VSS
A
B
C
D
E
F
P02.0
P02.2
P02.4
P02.6
P02.8
P00.0
P00.2
P00.4
P00.7
VSS
VEXT
P10.8
P10.5
P10.4
P10.1
P11.12
P11.10
P11.3
P13.2
P13.0
P14.6
P14.3
P14.4
P14.0
P15.3
VDDP3
VSS
P15.0
P02.1
P02.3
P02.5
P02.7
P00.1
P00.3
P00.5
P00.9
P15.2
P20.14
VSS
NC
VFLEX P11.15
P11.14
P11.8
P11.5
P11.7
P11.6
P11.1
P11.4
P11.0
P14.10
P12.1
P14.9
P12.0
P14.7
P14.2
P15.8
P15.5
P15.7
VDD
VDD
VSS
VSS
P20.9
P20.6
PORST
P20.12 P20.13
P20.10 P20.11
VSS
NC
P11.13
NC
ESR0
ESR1
P20.7
P20.1
P20.2
P21.3
P21.2
TRST
XTAL2
VDD
P20.8
P20.3
P20.0
P21.5
P21.4
VSS
G
H
J
NC
NC
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
G
H
J
P21.7 / P21.6 /
TDO
NC
NC
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VSS
NC
TDI
P00.6
P00.8
AN43
AN41
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TCK
P21.1
K
L
P00.10
AN42
AN40
VSS
VSS
VSS
VSS
TMS
NC
P21.0
NC
K
L
P00.11 P00.12
VSS
VSS
VDD
M
N
P
R
T
AN46
AN44
AN47
AN45
NC
NC
XTAL1
VEXT
P22.0
P22.2
P23.4
P23.2
P23.0
VEXT
M
N
P
R
T
AN36 /
P40.6
AN38 /
P40.8
VSS
VSS
VSS
VSS
NC
NC
AN39 /
P40.9
AN37 /
P40.7
AN32 /
P40.4
AN34
AN23
AN22
AN17
VDD
VDD
NC
NC
P22.1
P22.3
P23.3
P23.1
VEXT
VSS
AN33 /
P40.5
AN35
NC
AN31
AN30
NC1
NC
NC
VEVRS
B
NC
AN15
AN14
AN12
AN9
AN6
AN7
AN4
AN3
AN0
AN1
NC
NC
NC
NC
NC
NC
NC
NC
VSS
NC
P23.5
VSS
U
V
W
Y
AN29
AN28
NC
U
V
W
Y
AN27 /
P40.3
AN26 /
P40.2
P32.1 /
AN25 /
P40.1
AN24 /
P40.0
AN19
AN18
AN16
AN13
AN11
AN8
AN2
P33.0
P33.2
P33.4
P33.6
P33.8
P33.10 P33.12 VGATE
1P
P32.4
P32.0 /
P33.11 P33.13 VGATE
1N
VAREF VAGND
1
NC1
AN21
AN20
VSSM
VDDM
AN10
AN5
P33.1
P33.3
P33.5
P33.7
P33.9
P32.2
P32.3
VSS
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TC36xpd - (top view)
Figure 2-1 TC36x Logic Symbol for the package variant LFBGA-292
Data Sheet
11
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
NC
P10.3
P10.2
P11.12
P11.9
P11.2
P13.0
P13.2
P14.0
P15.3
P15.6
P15.1
P15.0
NC
A
B
C
D
E
F
P02.0
P02.1
P02.5
P02.6
P00.4
P00.8
P00.12
VSS
P10.1
VSS
P10.4
P10.0
VSS
P11.10
P11.11
VFLEX
VSS
P11.3
P11.6
P11.8
P13.1
P14.8
P15.8
P13.3
P14.10
P15.7
P14.5
P14.6
P14.2
P14.1
P14.4
P15.5
VSS
P15.4
P14.3
VSS
P15.2
VSS
VSS
P20.14
P02.2
P02.4
P02.7
P00.3
P00.7
P00.9
P20.13 P20.10
P20.12 P20.11
P02.3
P02.8
P00.2
P00.6
P00.5
P20.9
P20.7
P20.8
P20.3
P21.0
P22.3
TRST
P22.1
P10.6
P10.5
P00.0
P00.1
ESR1
P20.6
TMS
PORST
ESR0
P21.6 / P21.7 /
TDI
VEXT
VEXT
VDD
VDDP3
VSS
VEXT
VSS
VSS
VDD
VDD
VDD
TDO
TCK
G
H
J
P20.2
G
H
J
VEVRS
B
VSS
P22.2
P22.0
P23.3
VSS
P20.0
P21.4
P21.2
XTAL2
VDD
P21.5
P21.3
VSS
AN36 /
P40.6
AN37 /
P40.7
AN38 /
P40.8
AN39 /
P40.9
VSS
VDD
VEXT
AN32 /
P40.4
AN33 /
P40.5
K
L
AN34
NC
AN35
AN14
AN10
AN11
VSS
AN5
AN6
AN8
VSS
K
L
AN24 /
P40.0
AN25 /
P40.1
AN2
AN3
AN4
AN0
NC
P33.4
P33.1
P33.3
P33.8
P33.0
P33.5
P33.7
XTAL1
VEXT
P23.1
M
N
P
AN16
AN15
AN17
AN13
AN12
AN9
P33.12 P33.13
VSS
M
N
P
P32.1 /
NC
P33.11 P33.10 VGATE
1P
VSS
VSSM /
VAGND
1
P32.0 /
VAREF
1
NC
VDDM
AN7
AN1
NC
P33.2
P33.6
P33.9
VEXT VGATE
1N
P32.4
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TC36xpd - (top view)
Figure 2-2 TC36x Logic Symbol for the package variant LFBGA-180
Data Sheet
12
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions:
P02.0
P02.1
P02.2
P02.3
P02.4
P02.5
P02.6
P02.7
P02.8
VDD
P00.0
P00.1
P00.2
P00.3
P00.4
P00.5
P00.6
P00.7
P00.8
P00.9
P00.10
P00.11
P00.12
VDD
VEXT
AN43
AN42
AN47
AN46
AN45
1
2
3
4
5
6
7
8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
P20.14
P20.13
P20.12
P20.11
P20.10
P20.9
P20.8
P20.7
P20.6
VDD
ESR0
PORST
ESR1
P20.3
P20.2
P20.1
P20.0
TCK
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TRST
P21.7 / TDO
TMS
P21.6 / TDI
P21.5
P21.4
P21.3
P21.2
P21.1
P21.0
VEXT
XTAL2
XTAL1
VSS
TC36xpd
(Top View)
AN44
AN39 / P40.9
AN38 / P40.8
AN37 / P40.7
AN36 / P40.6
AN35
AN33 / P40.5
AN32 / P40.4
AN29
VDD
VEXT
P22.3
P22.2
P22.1
P22.0
P23.5
P23.4
P23.3
P23.2
P23.1
P23.0
98
97
96
95
94
93
92
91
AN28
AN27 / P40.3
AN26 / P40.2
AN25 / P40.1
AN24 / P40.0
90
89
Figure 2-3 TC36x Logic Symbol for the package variant LQFP-176
Data Sheet
13
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions:
P02.0
P02.1
P02.2
P02.3
P02.4
P02.5
P02.6
P02.7
P02.8
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
P20.14
P20.13
P20.12
P20.11
P20.10
P20.9
P20.8
P20.7
P20.6
VDD
9
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P00.0
P00.1
P00.2
P00.3
P00.4
P00.5
P00.6
P00.7
P00.8
P00.9
P00.12
VDD
VEXT
AN43
AN42
AN47
AN46
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
ESR0
PORST
ESR1
P20.3
P20.2
P20.0
TCK
TRST
P21.7 / TDO
TMS
P21.6 / TDI
P21.5
P21.4
P21.3
P21.2
VEXT
XTAL2
XTAL1
VSS
TC36xpd
(Top View)
AN45
AN44
AN39 / P40.9
AN38 / P40.8
AN37 / P40.7
AN36 / P40.6
AN35
VDD
VEXT
P22.3
P22.2
P22.1
P22.0
P23.1
AN25 / P40.1
AN24 / P40.0
74
73
Figure 2-4 TC36x Logic Symbol for the package variant LQFP-144
Data Sheet
14
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions:
P02.0
P02.1
P02.2
P02.3
P02.4
P02.5
P02.6
P02.7
P02.8
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
P20.14
P20.13
P20.12
P20.11
P20.10
P20.9
P20.8
P20.7
P20.6
VDD
9
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P00.0
P00.1
P00.2
P00.3
P00.4
P00.5
P00.6
P00.7
P00.8
P00.9
P00.12
VDD
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
ESR0
PORST
ESR1
P20.3
P20.2
P20.0
TCK
TRST
P21.7 / TDO
TMS
P21.6 / TDI
P21.5
P21.4
P21.3
P21.2
VEXT
XTAL2
XTAL1
VSS
TC36xpd
(Top View)
VEXT
AN39 / P40.9
AN38 / P40.8
AN37 / P40.7
AN36 / P40.6
AN35
AN34
AN33 / P40.5
AN32 / P40.4
AN28
AN27 / P40.3
AN26 / P40.2
AN25 / P40.1
AN24 / P40.0
VDD
VEXT
P22.3
P22.2
P22.1
P22.0
P23.1
74
73
Figure 2-5 TC36x Logic Symbol for the package variant TQFP-144
Data Sheet
15
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
2.1
LFBGA-292 Package Variant Pin Configuration of TC36x
Table 2-1 Port 00 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
G1
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Trap input capture
External timer start 12
Injection signal from port
MDIO Input
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Shift clock output
Transmit output
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
MDIO Output
O
Data Sheet
16
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
G2
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
T12 capture input 60
Receive input
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
CAN10_RXDA
PSI5_RX0A
CCU61_CC60INA
SENT_SENT0B
EVADC_G9CH11
P00.1
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
Receive input channel 0
Analog input channel 11, group 9
General-purpose output
GTM muxed output
Reference input 0
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
SENT_SPC0
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
17
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H1
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 2
Receive input channel 1
Analog input channel 10, group 9
General-purpose output
GTM muxed output
GTM_TIM2_IN1_2
SENT_SENT1B
EVADC_G9CH10
P00.2
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
—
Reference input 0
O2
O3
O4
Shift clock output
Reserved
PSI5_TX0
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
18
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H2
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 2
T12 capture input 61
Modulator clock input, channel 3
RXD inputs (receive data) channel 1
CAN receive input node 3
RX data input
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
PSI5_RX1A
CAN03_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
EVADC_G9CH9
P00.3
Receive input channel 2
T12 capture input 61
Analog input channel 9, group 9
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Reserved
EDSADC_DSCOUT3
—
Modulator clock output
Reserved
SENT_SPC2
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
19
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
J1
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
EVADC_G9CH8
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
AI
Analog input channel 8, group 9
General-purpose output
GTM muxed output
Reference input 0
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
O2
O3
O4
TX data output
CAN11_TXD
PSI5_TX1
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
20
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
J2
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 4 of TIM module 2
T12 capture input 62
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Modulator clock input, channel 2
T12 capture input 62
Receive input channel 4
CAN receive input node 1
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
P00.6
T12 PWM channel 62
Monitor input 1
Reference input 1
J4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 5 of TIM module 2
Digital datastream input, channel 2
Receive input channel 5
Receive input
GTM_TIM2_IN5_1
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
EVADC_G9CH6
P00.6
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
O5
O6
O7
Positive carrier generator output
Reserved
—
Reserved
EVADC_EMUX10
SENT_SPC5
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
21
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
K1
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 6 of TIM module 2
T12 capture input 60
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
P00.7
Receive input channel 6
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
—
Transmit output
Reserved
—
Reserved
EVADC_EMUX11
SENT_SPC6
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
P00.8
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
K4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 2
T12 capture input 61
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
P00.8
Receive input channel 7
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
22
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
K2
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
EVADC_G9CH3
P00.9
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
Analog input channel 3, group 9
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
P00.10
T12 PWM channel 62
Monitor input 1
Reference input 1
K5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input channel 9
Digital datastream input, channel 1
Analog input channel 2, group 9
General-purpose output
GTM muxed output
GTM_TIM1_IN1_1
GTM_TIM0_IN1_1
SENT_SENT9B
EDSADC_DSDIN1A
EVADC_G9CH2
P00.10
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT19
ASCLIN4_ASCLK
—
Shift clock output
Reserved
—
Reserved
—
Reserved
SENT_SPC9
Transmit output
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
23
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
L1
P00.11
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trap input capture
GTM_TIM1_IN2_1
GTM_TIM0_IN2_1
CCU60_CTRAPA
EDSADC_DSCIN0A
CCU61_T12HRE
EVADC_G9CH1
P00.11
Modulator clock input, channel 0
External timer start 12
Analog input channel 1, group 9
General-purpose output
GTM muxed output
Slave select signal output
Reserved
AI
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT20
ASCLIN4_ASLSO
—
EDSADC_DSCOUT0
—
Modulator clock output
Reserved
—
Reserved
—
Reserved
L2
P00.12
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
EVADC_G9CH0
P00.12
Digital datastream input, channel 0
Receive input
AI
Analog input channel 0, group 9
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
24
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
B1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
25
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
C2
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Reserved
GTM_TOUT1
IOM_REF0_1
—
O2
O3
O4
O5
O6
O7
QSPI3_SLSO2
EDSADC_CGPWMP
—
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
26
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
C1
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
27
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D2
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive Channel B2
CAN receive input node 2
Receive input
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
PSI5_RX0B
P02.3
RXD inputs (receive data) channel 0
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
28
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D1
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
P02.4
CAN receive input node 1
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
29
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E2
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
I2C0_SCLA
PSI5_RX1B
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
RXD inputs (receive data) channel 1
RX data input
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
I2C0_SCL
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
30
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E1
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
31
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F2
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
GPT120_T3EUDA
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Receive input channel 1
Modulator clock input, channel 3
Count direction control input of core timer T3
Hall capture input 1
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
—
Reference input 0
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
32
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-2 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F1
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
QSPI3_SLSO5
ASCLIN8_ASCLK
—
Reference input 0
O2
O3
O4
O5
O6
O7
Master slave select output
Shift clock output
Reserved
EVADC_EMUX02
GETH_MDC
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
33
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-3 Port 10 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
A7
P10.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of core timer T6
Receive input
GTM_TIM1_IN4_2
GTM_TIM0_IN4_2
GPT120_T6EUDB
ASCLIN11_ARXA
GETH_RXERC
P10.0
Receive Error MII
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT102
ASCLIN11_ATX
QSPI1_SLSO10
—
Transmit output
Master slave select output
Reserved
—
Reserved
—
Reserved
—
Reserved
B7
P10.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
EVADC_FC1BFLOUT
—
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Chip Select
Boundary flag output, FC channel 1
Reserved
—
Reserved
Data Sheet
34
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-3 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A5
P10.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P10.2
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
I
Reserved
QSPI1_SCLK
MSC0_EN0
—
Master SPI clock output
Chip Select
Reserved
—
Reserved
—
Reserved
A6
P10.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
Reserved
O7
Data Sheet
35
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-3 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B6
P10.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
P10.4
Trigger/gate input of core timer T3
Receive input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT106
IOM_MON2_11
—
Monitor input 2
O2
O3
O4
O5
O6
O7
I
Reserved
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
Master slave select output
Master SPI data output
Chip Select
—
Reserved
—
Reserved
B5
P10.5
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
MSC0_INJ1
Injection signal from port
General-purpose output
GTM muxed output
P10.5
O0
O1
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
Reference input 2
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
—
O6
O7
Slave select signal output
Reserved
Data Sheet
36
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-3 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A4
P10.6
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
P10.6
Slave SPI data input
HWCFG5 pin input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
—
O5
O6
Reserved
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
Slave SPI data output
Monitor input 2
Reference input 2
O7
I
Reserved
A3
P10.7
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Count direction control input of core timer T3
Clear to send input
GTM_TIM1_IN0_3
GTM_TIM0_IN0_3
GPT120_T3EUDB
ASCLIN2_ACTSA
QSPI3_MRSTB
SCU_E_REQ0_2
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS1C
P10.7
Hall capture input 1
General-purpose output
GTM muxed output
Reference input 2
Reserved
O0
O1
GTM_TOUT109
IOM_REF2_11
—
O2
O3
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
Data Sheet
37
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-3 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B4
P10.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN5_2
GTM_TIM0_IN5_2
CAN12_RXDB
GPT120_T4INB
QSPI3_SCLKB
SCU_E_REQ1_2
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 2
Trigger/gate input of timer T4
Slave SPI clock inputs
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS2C
Hall capture input 2
General-purpose output
GTM muxed output
Ready to send output
Master SPI clock output
Reserved
P10.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT110
ASCLIN2_ARTS
QSPI3_SCLK
—
—
—
—
Reserved
Reserved
Reserved
Table 2-4 Port 11 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
E10
P11.0
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN0_7
ASCLIN3_ARXB
GTM_DTMA2_1
P11.0
Mux input channel 0 of TIM module 2
Receive input
CDTM2_DTM4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT119
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
CAN11_TXD
GETH_TXD3
—
CAN transmit output node 1
Transmit Data
Reserved
Data Sheet
38
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-4 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E9
P11.1
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN1_6
P11.1
Mux input channel 1 of TIM module 2
O0
O1
O2
O3
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Monitor input 2
GTM_TOUT120
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 2
Reserved
O4
O5
O6
O7
I
CAN12_TXD
GETH_TXD2
—
CAN transmit output node 2
Transmit Data
Reserved
A10
P11.2
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
39
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-4 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B10
P11.3
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
Transmit Channel A
Reserved
O4
O5
O6
O7
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
P11.4
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
D10
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN2_6
GETH_RXCLKB
P11.4
Mux input channel 2 of TIM module 2
Receive Clock MII
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Shift clock output
GTM_TOUT121
ASCLIN3_ASCLK
—
Reserved
—
Reserved
CAN13_TXD
GETH_TXER
GETH_TXCLK
CAN transmit output node 3
Transmit Error MII
Transmit Clock Output for RGMII
Data Sheet
40
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-4 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D8
P11.5
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM2_IN3_8
GETH_TXCLKA
GETH_GREFCLK
Mux input channel 3 of TIM module 2
Transmit Clock Input for MII
Gigabit Reference Clock input for RGMII (125 MHz high
precission)
P11.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT122
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
D9
P11.6
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM muxed output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
Monitor input 1
Reference input 1
Data Sheet
41
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-4 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E8
P11.7
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM2_IN4_7
GETH_RXD3A
Mux input channel 4 of TIM module 2
Receive Data 3 MII and RGMII (RGMII can use RXD3A
only)
CAN11_RXDD
CAN receive input node 1
General-purpose output
GTM muxed output
Reserved
P11.7
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT123
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
E7
P11.8
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
Mux input channel 5 of TIM module 2
GTM_TIM2_IN5_8
GETH_RXD2A
Receive Data 2 MII and RGMII (RGMII can use RXD2A
only)
CAN12_RXDD
CAN receive input node 2
General-purpose output
GTM muxed output
Reserved
P11.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT124
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
42
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-4 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A9
P11.9
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT98
—
Reserved
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P11.10
T12 PWM channel 60
Monitor input 1
Reference input 1
B9
I
FAST /
General-purpose input
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
43
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-4 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A8
P11.11
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
Reserved
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
Master slave select output
Master slave select output
Chip Select
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P11.12
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
B8
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
44
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-4 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E6
P11.13
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 6 of TIM module 2
Receive Error MII
CAN receive input node 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN6_7
GETH_RXERA
CAN13_RXDD
P11.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT125
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
D7
P11.14
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN7_8
GETH_CRSDVB
GETH_RXDVB
GETH_CRSA
P11.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT126
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
D6
P11.15
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 0
Collision MII
GTM_TIM0_IN7_8
GETH_COLA
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT127
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
45
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-5 Port 12 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
E12
P12.0
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
CAN receive input node 0
Receive Clock MII
General-purpose output
GTM muxed output
Reserved
CAN00_RXDC
GETH_RXCLKC
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT128
—
—
Reserved
—
Reserved
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
E11
P12.1
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
MDIO Input
GETH_MDIOC
P12.1
O0
O1
O2
O3
O4
O5
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT129
ASCLIN3_ASLSO
—
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
O
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
46
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-6 Port 13 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B12
P13.0
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN5_3
ASCLIN10_ARXC
P13.0
Mux input channel 5 of TIM module 2
PU1 /
VEXT /
ES6
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
MSC0_FCLN
—
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
P13.1
CAN transmit output node 0
A12
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 2
PU1 /
VEXT /
ES6
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
Shift-clock direct part of the differential signal
Serial Clock Output
Reserved
—
B11
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 2
PU1 /
VEXT /
ES6
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
P13.2
Serial Data Input 1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
—
Reserved
Data Sheet
47
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-6 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A11
P13.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN0_3
Mux input channel 0 of TIM module 2
PU1 /
VEXT /
ES6
P13.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT94
ASCLIN10_ASLSO
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
QSPI2_MTSRP
—
MSC0_SOP
Data output - direct part of the differential signal
Reserved
—
—
Reserved
Table 2-7 Port 14 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B16
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
48
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-7 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A15
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
E13
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
49
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-7 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B14
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
B15
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
50
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-7 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A14
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
CDTM2_DTM4
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT85
—
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
—
Transmit Channel B
Reserved
B13
P14.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
—
Transmit Enable Channel B
Reserved
Data Sheet
51
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-7 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D13
P14.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive Channel B0
CAN receive input node 0
CAN receive input node 3
Receive input
GTM_TIM1_IN0_5
GTM_TIM0_IN0_5
ERAY0_RXDB0
CAN10_RXDB
CAN13_RXDA
ASCLIN9_ARXC
P14.7
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
Transmit output
GTM_TOUT87
ASCLIN0_ARTS
QSPI2_SLSO4
ASCLIN9_ATX
—
Reserved
—
Reserved
—
Reserved
A13
P14.8
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Receive Channel A0
CAN receive input node 2
Receive input
GTM_TIM2_IN2_3
ERAY0_RXDA0
CAN02_RXDD
ASCLIN1_ARXD
P14.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Slave select signal output
Slave select signal output
Reserved
GTM_TOUT88
ASCLIN5_ASLSO
ASCLIN7_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
Data Sheet
52
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-7 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D12
P14.9
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM2_IN3_3
ASCLIN0_ACTSA
QSPI2_MRSTFN
ASCLIN9_ARXD
P14.9
Mux input channel 3 of TIM module 2
PU1 /
VEXT /
ES
Clear to send input
Master SPI data input (LVDS N line)
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT89
—
MSC0_EN1
CAN10_TXD
ERAY0_TXENB
ERAY0_TXENA
—
Chip Select
CAN transmit output node 0
Transmit Enable Channel B
Transmit Enable Channel A
Reserved
D11
P14.10
LVDS_R General-purpose input
X / FAST /
GTM_TIM2_IN4_3
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 2
PU1 /
VEXT /
ES
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT90
—
MSC0_EN0
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
—
Chip Select
Transmit output
Monitor input 2
Reference input 2
CAN transmit output node 2
Monitor input 2
O5
Reference input 2
Transmit Channel A
Reserved
O6
O7
Data Sheet
53
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-8 Port 15 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
B20
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
A18
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
54
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-8 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
C19
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
Slave select input
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN5_4
QSPI2_SLSIA
QSPI2_MRSTE
P15.2
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
Shift clock output
Reserved
O6
O7
I
B17
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
Master SPI clock output
Reserved
O3
O4
O5
O6
O7
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
55
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-8 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A17
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
56
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-8 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E14
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
A16
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
P15.6
O0
O1
O2
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
57
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-8 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D15
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
P15.7
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
D14
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
58
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-9 Port 20 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
H20
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Shift clock output
Reserved
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
Trigger output
G19
P20.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
Trigger input
GTM_TIM2_IN3_5
CBS_TGI1
GTM_DTMA1_1
CDTM1_DTM4
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT60
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CBS_TGO1
P20.2
Trigger output
H19
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
Testmode Enable Input
Data Sheet
59
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-9 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
G20
P20.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
F17
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
Master slave select output
Reserved
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
—
Reserved
—
Reserved
Data Sheet
60
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-9 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F19
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
CAN receive input node 0
Clear to send input
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
F20
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
61
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-9 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E17
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
E19
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
62
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-9 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E20
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
D19
I
FAST /
PU1 /
VEXT /
ES
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O4
O5
O6
O7
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
63
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-9 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D20
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
C20
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
Enter destructive debug mode
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
DMU_FDEST
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
64
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-10 Port 21 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
K17
P21.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_6
ASCLIN11_ARXC
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
Reserved
GTM_TOUT51
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM1
Pin Output Value
General-purpose input
Mux input channel 5 of TIM module 2
Receive input
J17
P21.1
I
FAST /
PU1 /
VEXT /
ES
GTM_TIM2_IN5_6
ASCLIN11_ARXD
P21.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT52
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM2
Pin Output Value
Data Sheet
65
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-10 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K19
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
J19
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
P21.3
Mux input channel 1 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Reserved
GTM_TOUT54
ASCLIN11_ASCLK
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
66
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-10 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K20
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN2_6
Mux input channel 2 of TIM module 1
PU1 /
VEXT /
ES6
GTM_TIM0_IN2_6
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT55
ASCLIN11_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
J20
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
67
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-10 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H17
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ.
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
68
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-10 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H16
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Data Sheet
69
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-11 Port 22 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
P20
P22.0
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
ASCLIN6_ARXE
QSPI3_MTSRD
P22.0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT47
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MTSR
—
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
—
Reserved
ASCLIN6_ATX
P22.1
Transmit output
P19
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive input
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
ASCLIN7_ARXE
QSPI3_MRSTD
P22.1
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT48
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Monitor input 2
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
—
Reserved
ASCLIN7_ATX
Transmit output
Data Sheet
70
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-11 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
R20
P22.2
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
P22.2
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT49
ASCLIN5_ATX
QSPI3_SLSO12
Master slave select output
Reserved
—
—
Reserved
—
Reserved
—
Reserved
R19
P22.3
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
ASCLIN5_ARXC
QSPI3_SCLKD
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
P22.3
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT50
—
QSPI3_SCLK
Master SPI clock output
Reserved
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
71
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-12 Port 23 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
V20
P23.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_4
GTM_TIM0_IN5_4
CAN10_RXDC
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT41
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
U19
P23.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Ready to send output
Reserved
GTM_TOUT42
ASCLIN1_ARTS
—
GTM_CLK0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
P23.2
CGM generated clock
CAN transmit output node 0
External Clock 0
Shift clock output
U20
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_5
GTM_TIM0_IN6_5
ASCLIN7_ARXC
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT43
—
—
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
—
Reserved
Data Sheet
72
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-12 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
T19
P23.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
Receive input
GTM_TIM1_IN7_4
GTM_TIM0_IN7_4
ASCLIN6_ARXA
CAN12_RXDC
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
P23.3
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT44
ASCLIN7_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
T20
P23.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TIM1_IN7_5
GTM_TIM0_IN7_5
P23.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT45
ASCLIN6_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
T17
P23.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN2_7
GTM_TIM0_IN2_7
P23.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT46
ASCLIN6_ATX
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
73
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-13 Port 32 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
Y17
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM2_IN2_5
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
W17
P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT37
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Y18
P32.2
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 3
Receive input
GTM_TIM1_IN3_8
GTM_TIM0_IN3_8
CAN03_RXDB
ASCLIN3_ARXD
P32.2
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT38
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
Data Sheet
74
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-13 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
Y19
P32.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN4_5
GTM_TIM0_IN4_5
P32.3
O0
O1
O2
GTM_TOUT39
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN3_ASCLK
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Shift clock output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
W18
P32.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_5
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT40
—
—
Reserved
GTM_CLK1
—
CGM generated clock
Reserved
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
PMS_DCDCSYNCO
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
O
DC-DC synchronization output
Data Sheet
75
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
W10
P33.0
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
IOM_PIN_0
GTM_DTMT1_2
P33.0
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Y10
P33.1
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
Receive input
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
P33.1
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
O2
O3
O4
O5
O6
O7
—
Reserved
Data Sheet
76
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
W11
P33.2
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
Digital datastream input, channel 2
GPIO pad input to FPC
P33.2
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
—
Reference input 1
O5
O6
O7
I
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Y11
P33.3
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
SENT_SENT7C
EDSADC_DSCIN1B
IOM_PIN_3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
Modulator clock input, channel 1
GPIO pad input to FPC
P33.3
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
ASCLIN5_ASCLK
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT1
EVADC_EMUX00
—
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
77
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
W12
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
IOM_PIN_4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
GPIO pad input to FPC
P33.4
O0
O1
General-purpose output
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
Monitor input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
78
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
Y12
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
Clear to send input
Hall capture input 2
Receive input channel 5
CAN receive input node 3
GPIO pad input to FPC
P33.5
O0
O1
General-purpose output
GTM_TOUT27
IOM_MON0_5
IOM_GTM_5
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
—
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Reserved
ASCLIN5_ASLSO
Slave select signal output
Data Sheet
79
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
W13
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
P33.6
O0
O1
General-purpose output
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
Reserved
ASCLIN2_ASLSO
QSPI2_SLSO11
—
O2
O3
O4
O5
O6
O7
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
80
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
Y13
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
IOM_PIN_7
P33.7
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
—
GTM-provided inputs to EXOR combiner
Shift clock output
Reserved
O2
O3
O4
O5
O6
O7
ASCLIN8_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
Data Sheet
81
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
W14
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
FSP[1..0] Output Signals - Generated by SMU_core
O
Data Sheet
82
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
Y14
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN2_ASCLK
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Shift clock output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
83
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
W15
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
CAN receive input node 1
Receive input
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
P33.10
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
—
Monitor input 0
O2
O3
O4
O5
Master slave select output
Reserved
ASCLIN1_ASLSO
PSI5S_CLK
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Y15
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
84
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-14 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
W16
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 2
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN0_6
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
ASCLIN1_ASCLK
—
Shift clock output
Reserved
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P33.13
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
Reference input 1
Y16
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
P33.13
Carrier sign signal input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
85
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-15 Analog Inputs
Ball
Symbol
Ctrl. Buffer
Type
Function
T10
AN0
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
D / HighZ Analog Input 1
U10
W9
U9
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
AN3
Analog input channel 2, group 0
Positive analog input channel 0, pin A
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
T9
Y9
T8
U8
W8
U7
Y8
W7
T7
I
I
I
I
I
I
I
I
I
D / HighZ Analog Input 4
/ VDDM
EVADC_G0CH4
AN5
Analog input channel 4, group 0
D / HighZ Analog Input 5
/ VDDM
EVADC_G0CH5
AN6
Analog input channel 5, group 0
D / HighZ Analog Input 6
/ VDDM
EVADC_G0CH6
AN7
Analog input channel 6, group 0
D / HighZ Analog Input 7
/ VDDM
EVADC_G0CH7
AN8
Analog input channel 7, group 0
D / HighZ Analog Input 8
/ VDDM
EVADC_G1CH0
AN9
Analog input channel 0, group 1
D / HighZ Analog Input 9
/ VDDM
EVADC_G1CH1
AN10
Analog input channel 1, group 1
D / HighZ Analog Input 10
/ VDDM
EVADC_G1CH2
AN11
Analog input channel 2, group 1
D / HighZ Analog Input 11
/ VDDM
EVADC_G1CH3
AN12
Analog input channel 3, group 1
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
EDSADC_EDS0PB
AN13
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
W6
U6
I
I
/ VDDM
EVADC_G1CH5
EDSADC_EDS0NB
AN14
Analog input channel 5, group 1
Negative analog input channel 0, pin B
D / HighZ Analog Input 14
/ VDDM
EVADC_G1CH6
EDSADC_EDS3PB
Analog input channel 6, group 1
Positive analog input channel 3, pin B
Data Sheet
86
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-15 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T6
AN15
I
I
I
D / HighZ Analog Input 15
/ VDDM
EVADC_G1CH7
EDSADC_EDS3NB
AN16
Analog input channel 7, group 1
Negative analog input channel 3, pin N
D / HighZ Analog Input 16
W5
U5
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
AN17
Analog input channel 0, group 2
Analog input FC channel 0
D / HighZ Analog Input 17
/ VDDM
EVADC_G2CH1
EVADC_FC1CH0
AN18
Analog input channel 1, group 2
Analog input FC channel 1
D / HighZ Analog Input 18
/ VDDM
W4
W3
Y3
I
I
I
EVADC_G2CH2
AN19
Analog input channel 2, group 2
D / HighZ Analog Input 19
/ VDDM
EVADC_G2CH3
AN20
Analog input channel 3, group 2
D / HighZ Analog Input 20
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
Y2
I
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
AN22
Analog input channel 5, group 2
Negative analog input channel 2, pin A
T5
I
I
I
D / HighZ Analog Input 22
/ VDDM
EVADC_G2CH6
AN23
Analog input channel 6, group 2
R5
W2
D / HighZ Analog Input 23
/ VDDM
EVADC_G2CH7
AN24/P40.0
Analog input channel 7, group 2
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
W1
V2
I
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN26/P40.2
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
S / HighZ Analog Input 26
/ VDDM
SENT_SENT2A
EVADC_G3CH2
CCU60_CCPOS1D
Receive input channel 2
Analog input channel 2, group 3
Hall capture input 1
Data Sheet
87
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-15 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
V1
AN27/P40.3
I
S / HighZ Analog Input 27
/ VDDM
SENT_SENT3A
EVADC_G3CH3
CCU60_CCPOS2B
AN28
Receive input channel 3
Analog input channel 3, group 3
Hall capture input 2
U2
U1
T4
R4
P4
I
I
I
I
I
D / HighZ Analog Input 28
/ VDDM
EVADC_G3CH4
AN29
Analog input channel 4, group 3
D / HighZ Analog Input 29
/ VDDM
EVADC_G3CH5
AN30
Analog input channel 5, group 3
D / HighZ Analog Input 30
/ VDDM
EVADC_G3CH6
AN31
Analog input channel 6, group 3
D / HighZ Analog Input 31
/ VDDM
EVADC_G3CH7
AN32/P40.4
Analog input channel 7, group 3
S / HighZ Analog Input 32
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
AN33/P40.5
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
R1
I
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
AN34
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
P5
R2
N4
I
I
I
D / HighZ Analog Input 34
/ VDDM
EVADC_G8CH2
AN35
Analog input channel 2, group 8
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
AN36/P40.6
Analog input channel 3, group 8
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
AN37/P40.7
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
P2
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
Data Sheet
88
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-15 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N5
AN38/P40.8
I
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
P1
I
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
AN40
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
M5
M4
L5
I
I
I
I
I
D / HighZ Analog Input 40
/ VDDM
EVADC_G8CH8
AN41
Analog input channel 8, group 8
D / HighZ Analog Input 41
/ VDDM
EVADC_G8CH9
AN42
Analog input channel 9, group 8
D / HighZ Analog Input 42
/ VDDM
EVADC_G8CH10
AN43
Analog input channel 10, group 8
L4
D / HighZ Analog Input 43
/ VDDM
EVADC_G8CH11
AN44
Analog input channel 11, group 8
N1
D / HighZ Analog Input 44
/ VDDM
EVADC_G8CH12
EDSADC_EDS1PC
AN45
Analog input channel 12, group 8
Positive analog input channel 1, pin C
D / HighZ Analog Input 45
N2
M1
M2
I
I
I
/ VDDM
EVADC_G8CH13
EDSADC_EDS1NC
AN46
Analog input channel 13, group 8
Negative analog input channel 1, pin C
D / HighZ Analog Input 46
/ VDDM
EVADC_G8CH14
EDSADC_EDS1PD
AN47
Analog input channel 14, group 8
Positive analog input channel 1, pin D
D / HighZ Analog Input 47
/ VDDM
EVADC_G8CH15
EDSADC_EDS1ND
Analog input channel 15, group 8
Negative analog input channel 1, pin D
Data Sheet
89
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
1. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
2. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-16 System I/O
Ball
Symbol
Ctrl. Buffer
Type
Function
Y17
VGATE1N
O
—
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
W17
M20
M19
K16
VGATE1P
XTAL1
O
I
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
XTAL2
O
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
TMS
I
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
DAP: DAP1 Data I/O
DAP1
I/O
L19
J16
G16
TRST
I
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
TCK
I
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
DAP: DAP0 Clock Input
DAP0
ESR1
I/O
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
PORST
I
ESR1 pin input
G17
I/O
PORST / PORST pin
PD /
VEXT
Power On Reset Input. Additional strong PD in case of
power fail.
Data Sheet
90
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-16 System I/O (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F16
ESR0
I/O
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
Table 2-17 Supply
Ball
Symbol
Ctrl. Buffer
Type
Function
Y5
D5
VDDM
VFLEX
I
I
I
—
—
—
ADC Analog Power Supply (5V / 3.3V)
Digital Power Supply for Flex Port Pads (5V / 3.3V)
Digital Core Power Supply (1.25V)
P8, P13, N7, VDD
N14, E15,
H14, D16,
G13, G8, H7
A2, B3, V19, VEXT
W20
I
—
External Power Supply (5V / 3.3V)
B18, A19
VDDP3
I
I
—
—
Flash Power Supply (3.3V)
Digital Ground
B2, D4, E5, VSS
T16, U17,
W19, Y20,
E16, D17,
B19, A20
Y4
VSSM
I
—
Analog Ground for VDDM
Data Sheet
91
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-292 Package Variant Pin
Table 2-17 Supply (cont’d)
Ball Symbol
Ctrl. Buffer
Function
Type
P9, P12, N9, VSS
N10, N11,
N12, M7,
I
—
Digital Ground
M8, M10,
M11, M13,
M14, L8, L9,
L10, L11,
L12, L13,
K8, K9, K10,
K11, K12,
K13, J7, J8,
J10, J11,
J13, J14, H9,
H10, H11,
H12, G9,
G10, G11,
G12, L14,
P10, P11,
K7, L7
L20
Y6
VSS
I
I
I
I
—
—
—
—
Oscillator Ground
VAREF1
VAGND1
Positive Analog Reference Voltage 1
Negative Analog Reference Voltage 1
Y7
E4, F4, F5, NC
G4, G5, H4,
H5, J5, K14,
L16, L17,
Not connected. These pins are reserved for future
extensions and shall not be connected externally
M16, M17,
N16, N17,
P16, P17,
R16, R17,
T1, T2, T12,
T13, T14,
T15, U11,
U12, U13,
U14, U15,
U16
A1, Y1, U4
NC1
I
I
—
—
Not connected. These pins are not connected on
package level and will not be used for future
extensions
T11
VEVRSB
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
N19
N20
VDD
I
I
—
—
Digital Power Supply for Oscillator (1.25V)
VEXT
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT)
Data Sheet
92
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
2.2
LFBGA-180 Package Variant Pin Configuration of TC36x
Table 2-18 Port 00 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
G4
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Trap input capture
External timer start 12
Injection signal from port
MDIO Input
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Shift clock output
Transmit output
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
MDIO Output
O
Data Sheet
93
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H4
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
T12 capture input 60
Receive input
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
CAN10_RXDA
PSI5_RX0A
CCU61_CC60INA
SENT_SENT0B
EVADC_G9CH11
P00.1
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
Receive input channel 0
Analog input channel 11, group 9
General-purpose output
GTM muxed output
Reference input 0
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
SENT_SPC0
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
94
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F3
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 2
Receive input channel 1
Analog input channel 10, group 9
General-purpose output
GTM muxed output
GTM_TIM2_IN1_2
SENT_SENT1B
EVADC_G9CH10
P00.2
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
—
Reference input 0
O2
O3
O4
Shift clock output
Reserved
PSI5_TX0
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
95
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F2
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 2
T12 capture input 61
Modulator clock input, channel 3
RXD inputs (receive data) channel 1
CAN receive input node 3
RX data input
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
PSI5_RX1A
CAN03_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
EVADC_G9CH9
P00.3
Receive input channel 2
T12 capture input 61
Analog input channel 9, group 9
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Reserved
EDSADC_DSCOUT3
—
Modulator clock output
Reserved
SENT_SPC2
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
96
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F1
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
EVADC_G9CH8
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
AI
Analog input channel 8, group 9
General-purpose output
GTM muxed output
Reference input 0
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
O2
O3
O4
TX data output
CAN11_TXD
PSI5_TX1
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
97
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H3
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 4 of TIM module 2
T12 capture input 62
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Modulator clock input, channel 2
T12 capture input 62
Receive input channel 4
CAN receive input node 1
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
P00.6
T12 PWM channel 62
Monitor input 1
Reference input 1
G3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 5 of TIM module 2
Digital datastream input, channel 2
Receive input channel 5
Receive input
GTM_TIM2_IN5_1
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
EVADC_G9CH6
P00.6
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
O5
O6
O7
Positive carrier generator output
Reserved
—
Reserved
EVADC_EMUX10
SENT_SPC5
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
98
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
G2
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 6 of TIM module 2
T12 capture input 60
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
P00.7
Receive input channel 6
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
—
Transmit output
Reserved
—
Reserved
EVADC_EMUX11
SENT_SPC6
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
P00.8
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
G1
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 2
T12 capture input 61
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
P00.8
Receive input channel 7
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
99
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H2
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
EVADC_G9CH3
P00.9
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
AI
Analog input channel 3, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
100
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-18 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H1
P00.12
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
Digital datastream input, channel 0
Receive input
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
EVADC_G9CH0
P00.12
AI
Analog input channel 0, group 9
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
101
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
B1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
102
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
C1
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Reserved
GTM_TOUT1
IOM_REF0_1
—
O2
O3
O4
O5
O6
O7
QSPI3_SLSO2
EDSADC_CGPWMP
—
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
103
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
C2
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
104
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D3
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive Channel B2
CAN receive input node 2
Receive input
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
PSI5_RX0B
P02.3
RXD inputs (receive data) channel 0
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
105
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D2
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
P02.4
CAN receive input node 1
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
106
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D1
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
I2C0_SCLA
PSI5_RX1B
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
RXD inputs (receive data) channel 1
RX data input
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
I2C0_SCL
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
107
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E1
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
108
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E2
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
GPT120_T3EUDA
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Receive input channel 1
Modulator clock input, channel 3
Count direction control input of core timer T3
Hall capture input 1
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
—
Reference input 0
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
109
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-19 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E3
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
QSPI3_SLSO5
ASCLIN8_ASCLK
—
Reference input 0
O2
O3
O4
O5
O6
O7
Master slave select output
Shift clock output
Reserved
EVADC_EMUX02
GETH_MDC
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
110
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-20 Port 10 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
C4
P10.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of core timer T6
Receive input
GTM_TIM1_IN4_2
GTM_TIM0_IN4_2
GPT120_T6EUDB
ASCLIN11_ARXA
GETH_RXERC
P10.0
Receive Error MII
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT102
ASCLIN11_ATX
QSPI1_SLSO10
—
Transmit output
Master slave select output
Reserved
—
Reserved
—
Reserved
—
Reserved
B3
P10.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
EVADC_FC1BFLOUT
—
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Chip Select
Boundary flag output, FC channel 1
Reserved
—
Reserved
Data Sheet
111
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-20 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A3
P10.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P10.2
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
I
Reserved
QSPI1_SCLK
MSC0_EN0
—
Master SPI clock output
Chip Select
Reserved
—
Reserved
—
Reserved
A2
P10.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
Reserved
O7
Data Sheet
112
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-20 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B4
P10.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
P10.4
Trigger/gate input of core timer T3
Receive input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT106
IOM_MON2_11
—
Monitor input 2
O2
O3
O4
O5
O6
O7
I
Reserved
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
Master slave select output
Master SPI data output
Chip Select
—
Reserved
—
Reserved
F4
P10.5
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
MSC0_INJ1
Injection signal from port
General-purpose output
GTM muxed output
P10.5
O0
O1
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
Reference input 2
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
—
O6
O7
Slave select signal output
Reserved
Data Sheet
113
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-20 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E4
P10.6
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
P10.6
Slave SPI data input
HWCFG5 pin input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
—
O5
O6
Reserved
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O7
Table 2-21 Port 11 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
A6
P11.2
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
114
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-21 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B6
P11.3
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
Transmit Channel A
Reserved
O4
O5
O6
O7
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
P11.6
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
C6
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM muxed output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
Monitor input 1
Reference input 1
Data Sheet
115
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-21 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D6
P11.8
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM2_IN5_8
GETH_RXD2A
Mux input channel 5 of TIM module 2
Receive Data 2 MII and RGMII (RGMII can use RXD2A
only)
CAN12_RXDD
CAN receive input node 2
General-purpose output
GTM muxed output
Reserved
P11.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT124
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
A5
P11.9
FAST /
General-purpose input
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT98
—
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
116
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-21 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B5
P11.10
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
P11.11
T12 PWM channel 62
Monitor input 1
Reference input 1
C5
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Master slave select output
Master slave select output
Chip Select
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
117
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-21 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A4
P11.12
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
CAN transmit output node 3
Monitor input 2
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Table 2-22 Port 13 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
A7
P13.0
I
LVDS_TX General-purpose input
/ FAST /
PU1 /
VEXT /
ES6
GTM_TIM2_IN5_3
ASCLIN10_ARXC
P13.0
Mux input channel 5 of TIM module 2
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
MSC0_FCLN
—
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
CAN transmit output node 0
Data Sheet
118
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-22 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B7
P13.1
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 2
PU1 /
VEXT /
ES6
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
—
Shift-clock direct part of the differential signal
Serial Clock Output
Reserved
A8
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 2
PU1 /
VEXT /
ES6
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
P13.2
Serial Data Input 1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
—
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
Reserved
B8
P13.3
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN0_3
P13.3
Mux input channel 0 of TIM module 2
PU1 /
VEXT /
ES6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT94
ASCLIN10_ASLSO
QSPI2_MTSRP
—
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
—
Reserved
Data Sheet
119
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-23 Port 14 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
A9
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
120
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-23 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B10
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
D9
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
121
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-23 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
C11
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
C10
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
122
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-23 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B9
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
CDTM2_DTM4
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT85
—
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
—
Transmit Channel B
Reserved
C9
P14.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT86
—
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
—
Transmit Enable Channel B
Reserved
C7
P14.8
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Receive Channel A0
CAN receive input node 2
Receive input
GTM_TIM2_IN2_3
ERAY0_RXDA0
CAN02_RXDD
ASCLIN1_ARXD
P14.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Slave select signal output
Slave select signal output
Reserved
GTM_TOUT88
ASCLIN5_ASLSO
ASCLIN7_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
Data Sheet
123
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-23 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C8
P14.10
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM2_IN4_3
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 2
PU1 /
VEXT /
ES
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT90
—
MSC0_EN0
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
—
Chip Select
Transmit output
Monitor input 2
Reference input 2
CAN transmit output node 2
Monitor input 2
O5
Reference input 2
Transmit Channel A
Reserved
O6
O7
Table 2-24 Port 15 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
A13
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Shift clock output
Reserved
Data Sheet
124
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-24 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A12
P15.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
—
Reserved
—
Reserved
B12
P15.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
Slave select input
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN5_4
QSPI2_SLSIA
QSPI2_MRSTE
P15.2
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
Shift clock output
Reserved
O6
O7
Data Sheet
125
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-24 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
A10
P15.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
I
Master SPI clock output
Reserved
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
B11
P15.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Serial Clock Input 2
Master SPI data input
GTM_TIM2_IN7_4
I2C0_SCLC
QSPI2_MRSTA
SCU_E_REQ0_0
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
126
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-24 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D10
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
A11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
P15.6
O0
O1
O2
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
127
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-24 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D8
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
P15.7
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
D7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
128
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-25 Port 20 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
H13
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
Shift clock output
Reserved
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
P20.2
Trigger output
G13
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
Testmode Enable Input
Data Sheet
129
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-25 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
G12
P20.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
F11
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
Master slave select output
Reserved
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
—
Reserved
—
Reserved
Data Sheet
130
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-25 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
E12
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
CAN receive input node 0
Clear to send input
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
F12
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
131
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-25 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D12
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
C14
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
132
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-25 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
D14
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
D13
I
FAST /
PU1 /
VEXT /
ES
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O4
O5
O6
O7
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
133
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-25 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
C13
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
B14
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
Enter destructive debug mode
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
DMU_FDEST
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
134
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-26 Port 21 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
H12
P21.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_6
ASCLIN11_ARXC
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
Reserved
GTM_TOUT51
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM1
P21.2
Pin Output Value
K13
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
Data Sheet
135
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-26 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J14
P21.3
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN1_6
Mux input channel 1 of TIM module 1
PU1 /
VEXT /
ES
GTM_TIM0_IN1_6
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
Rx data
P21.3
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Reserved
GTM_TOUT54
ASCLIN11_ASCLK
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
J13
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN2_6
Mux input channel 2 of TIM module 1
PU1 /
VEXT /
ES6
GTM_TIM0_IN2_6
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT55
ASCLIN11_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
Tx data
Data Sheet
136
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-26 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H14
P21.5
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
P21.6/TDI
Tx data
F13
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ.
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
137
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-26 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
F14
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Data Sheet
138
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-27 Port 22 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
J11
P22.0
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
ASCLIN6_ARXE
QSPI3_MTSRD
P22.0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT47
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MTSR
—
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
—
Reserved
ASCLIN6_ATX
P22.1
Transmit output
L12
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive input
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
ASCLIN7_ARXE
QSPI3_MRSTD
P22.1
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT48
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Monitor input 2
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
—
Reserved
ASCLIN7_ATX
Transmit output
Data Sheet
139
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-27 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
H11
P22.2
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
P22.2
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT49
ASCLIN5_ATX
QSPI3_SLSO12
Master slave select output
Reserved
—
—
Reserved
—
Reserved
—
Reserved
J12
P22.3
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
ASCLIN5_ARXC
QSPI3_SCLKD
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
P22.3
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT50
—
QSPI3_SCLK
Master SPI clock output
Reserved
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
140
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-28 Port 23 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
N14
P23.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Ready to send output
Reserved
GTM_TOUT42
ASCLIN1_ARTS
—
GTM_CLK0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
P23.3
CGM generated clock
CAN transmit output node 0
External Clock 0
Shift clock output
K11
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
Receive input
GTM_TIM1_IN7_4
GTM_TIM0_IN7_4
ASCLIN6_ARXA
CAN12_RXDC
P23.3
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT44
ASCLIN7_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
141
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-29 Port 32 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
P12
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM2_IN2_5
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
N12
P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT37
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
P13
P32.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_5
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT40
—
—
Reserved
GTM_CLK1
—
CGM generated clock
Reserved
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
PMS_DCDCSYNCO
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
DC-DC synchronization output
O
Data Sheet
142
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions
Ball
Symbol
Ctrl. Buffer
Function
Type
M9
P33.0
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
IOM_PIN_0
GTM_DTMT1_2
P33.0
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
M8
P33.1
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
Receive input
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
P33.1
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
O2
O3
O4
O5
O6
O7
—
Reserved
Data Sheet
143
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
P8
P33.2
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
Digital datastream input, channel 2
GPIO pad input to FPC
P33.2
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
—
Reference input 1
O5
O6
O7
I
Control of external analog multiplexer interface 0
Reserved
—
Reserved
N8
P33.3
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
SENT_SENT7C
EDSADC_DSCIN1B
IOM_PIN_3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
Modulator clock input, channel 1
GPIO pad input to FPC
P33.3
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
ASCLIN5_ASCLK
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT1
EVADC_EMUX00
—
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
144
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
L8
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
IOM_PIN_4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
GPIO pad input to FPC
P33.4
O0
O1
General-purpose output
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
Monitor input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
145
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
N9
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
Clear to send input
Hall capture input 2
Receive input channel 5
CAN receive input node 3
GPIO pad input to FPC
P33.5
O0
O1
General-purpose output
GTM_TOUT27
IOM_MON0_5
IOM_GTM_5
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
—
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Reserved
ASCLIN5_ASLSO
Slave select signal output
Data Sheet
146
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
P9
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
P33.6
O0
O1
General-purpose output
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
Reserved
ASCLIN2_ASLSO
QSPI2_SLSO11
—
O2
O3
O4
O5
O6
O7
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
147
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
L10
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
IOM_PIN_7
P33.7
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
—
GTM-provided inputs to EXOR combiner
Shift clock output
Reserved
O2
O3
O4
O5
O6
O7
ASCLIN8_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
Data Sheet
148
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
L9
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
FSP[1..0] Output Signals - Generated by SMU_core
O
Data Sheet
149
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
P10
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN2_ASCLK
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Shift clock output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
150
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
N11
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
CAN receive input node 1
Receive input
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
P33.10
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
—
Monitor input 0
O2
O3
O4
O5
Master slave select output
Reserved
ASCLIN1_ASLSO
PSI5S_CLK
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
N10
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
151
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-30 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
M10
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 2
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN0_6
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
ASCLIN1_ASCLK
—
Shift clock output
Reserved
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P33.13
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
Reference input 1
M11
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
P33.13
Carrier sign signal input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
152
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-31 Analog Inputs
Ball
Symbol
Ctrl. Buffer
Type
Function
L7
AN0
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
D / HighZ Analog Input 1
P6
L6
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
AN3
Analog input channel 2, group 0
Positive analog input channel 0, pin A
D / HighZ Analog Input 3
M6
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
N6
L5
I
I
I
I
I
I
I
I
I
D / HighZ Analog Input 4
/ VDDM
EVADC_G0CH4
AN5
Analog input channel 4, group 0
D / HighZ Analog Input 5
/ VDDM
EVADC_G0CH5
AN6
Analog input channel 5, group 0
M5
P5
N5
N3
M4
N4
M3
D / HighZ Analog Input 6
/ VDDM
EVADC_G0CH6
AN7
Analog input channel 6, group 0
D / HighZ Analog Input 7
/ VDDM
EVADC_G0CH7
AN8
Analog input channel 7, group 0
D / HighZ Analog Input 8
/ VDDM
EVADC_G1CH0
AN9
Analog input channel 0, group 1
D / HighZ Analog Input 9
/ VDDM
EVADC_G1CH1
AN10
Analog input channel 1, group 1
D / HighZ Analog Input 10
/ VDDM
EVADC_G1CH2
AN11
Analog input channel 2, group 1
D / HighZ Analog Input 11
/ VDDM
EVADC_G1CH3
AN12
Analog input channel 3, group 1
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
EDSADC_EDS0PB
AN13
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
N2
L4
I
I
/ VDDM
EVADC_G1CH5
EDSADC_EDS0NB
AN14
Analog input channel 5, group 1
Negative analog input channel 0, pin B
D / HighZ Analog Input 14
/ VDDM
EVADC_G1CH6
EDSADC_EDS3PB
Analog input channel 6, group 1
Positive analog input channel 3, pin B
Data Sheet
153
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-31 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N1
AN15
I
I
I
I
D / HighZ Analog Input 15
/ VDDM
EVADC_G1CH7
EDSADC_EDS3NB
AN16
Analog input channel 7, group 1
Negative analog input channel 3, pin N
D / HighZ Analog Input 16
M1
M2
L1
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
AN17
Analog input channel 0, group 2
Analog input FC channel 0
D / HighZ Analog Input 17
/ VDDM
EVADC_G2CH1
EVADC_FC1CH0
AN24/P40.0
Analog input channel 1, group 2
Analog input FC channel 1
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
L2
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN32/P40.4
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
K1
K2
I
I
S / HighZ Analog Input 32
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
AN33/P40.5
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
AN34
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
K3
K4
J1
I
I
I
D / HighZ Analog Input 34
/ VDDM
EVADC_G8CH2
AN35
Analog input channel 2, group 8
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
AN36/P40.6
Analog input channel 3, group 8
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
Data Sheet
154
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-31 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J2
AN37/P40.7
I
I
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
AN38/P40.8
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
J3
J4
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
3. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
4. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-32 System I/O
Ball
Symbol
Ctrl. Buffer
Type
Function
P12
VGATE1N
O
—
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
N12
L14
L13
G11
VGATE1P
XTAL1
O
I
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
XTAL2
O
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
TMS
I
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
DAP: DAP1 Data I/O
DAP1
I/O
Data Sheet
155
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-32 System I/O (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
K12
TRST
I
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
G14
E11
TCK
I
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
DAP: DAP0 Clock Input
DAP0
ESR1
I/O
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
PORST
I
ESR1 pin input
E13
E14
I/O
PORST / PORST pin
PD /
VEXT
Power On Reset Input. Additional strong PD in case of
power fail.
ESR0
I/O
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
Table 2-33 Supply
Ball
Symbol
Ctrl. Buffer
Type
Function
P3
D5
VDDM
VFLEX
I
I
I
—
—
—
ADC Analog Power Supply (5V / 3.3V)
Digital Power Supply for Flex Port Pads (5V / 3.3V)
Digital Core Power Supply (1.25V)
F9, G9, H6, VDD
J7, J8
F6, F8, G6, VEXT
J9, P11
I
—
External Power Supply (5V / 3.3V)
F7
VDDP3
I
I
—
—
Flash Power Supply (3.3V)
Digital Ground
B2, C3, D4, VSS
E5, K10,
L11, M12,
N13
Data Sheet
156
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TC36x AA-Step
TC36x Pin Definition and Functions: LFBGA-180 Package Variant Pin
Table 2-33 Supply (cont’d)
Ball
Symbol
Ctrl. Buffer
Function
Type
B13, C12,
D11, E10,
G7, G8, H7,
H8, J6, K5
VSS
I
—
Digital Ground
K14
P4
VSS
I
I
I
—
—
—
Oscillator Ground
VAREF1
Positive Analog Reference Voltage 1
A1, A14, L3, NC
M7, N7, P1,
P7, P14
Not connected. These pins are reserved for future
extensions and shall not be connected externally
H9
VEVRSB
I
—
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
M13
M14
VDD
I
I
—
—
Digital Power Supply for Oscillator (1.25V)
VEXT
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT)
P2
VSSM/VAGND1
I
—
Analog Ground for VDDM / Negative Analog Reference
Voltage 1
Data Sheet
157
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
2.3
LQFP-176 Package Variant Pin Configuration of TC36x
Note:In the following QFP package the VFLEX supply is internally connected to VEXT supply and thus does not
show up in the corresponding package drawings neither supply tables as a dedicated pin.
Table 2-34 Port 00 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
11
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Trap input capture
External timer start 12
Injection signal from port
MDIO Input
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Shift clock output
Transmit output
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
MDIO Output
O
Data Sheet
158
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
12
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
T12 capture input 60
Receive input
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
CAN10_RXDA
PSI5_RX0A
CCU61_CC60INA
SENT_SENT0B
EVADC_G9CH11
P00.1
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
Receive input channel 0
Analog input channel 11, group 9
General-purpose output
GTM muxed output
Reference input 0
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
SENT_SPC0
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
159
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
13
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 2
Receive input channel 1
Analog input channel 10, group 9
General-purpose output
GTM muxed output
GTM_TIM2_IN1_2
SENT_SENT1B
EVADC_G9CH10
P00.2
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
—
Reference input 0
O2
O3
O4
Shift clock output
Reserved
PSI5_TX0
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
160
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
14
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 2
T12 capture input 61
Modulator clock input, channel 3
RXD inputs (receive data) channel 1
CAN receive input node 3
RX data input
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
PSI5_RX1A
CAN03_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
EVADC_G9CH9
P00.3
Receive input channel 2
T12 capture input 61
Analog input channel 9, group 9
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Reserved
EDSADC_DSCOUT3
—
Modulator clock output
Reserved
SENT_SPC2
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
161
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
15
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
EVADC_G9CH8
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
AI
Analog input channel 8, group 9
General-purpose output
GTM muxed output
Reference input 0
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
O2
O3
O4
TX data output
CAN11_TXD
PSI5_TX1
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
162
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
16
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 4 of TIM module 2
T12 capture input 62
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Modulator clock input, channel 2
T12 capture input 62
Receive input channel 4
CAN receive input node 1
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
P00.6
T12 PWM channel 62
Monitor input 1
Reference input 1
17
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 5 of TIM module 2
Digital datastream input, channel 2
Receive input channel 5
Receive input
GTM_TIM2_IN5_1
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
EVADC_G9CH6
P00.6
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
O5
O6
O7
Positive carrier generator output
Reserved
—
Reserved
EVADC_EMUX10
SENT_SPC5
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
163
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
18
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 6 of TIM module 2
T12 capture input 60
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
P00.7
Receive input channel 6
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
—
Transmit output
Reserved
—
Reserved
EVADC_EMUX11
SENT_SPC6
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
P00.8
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
19
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 2
T12 capture input 61
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
P00.8
Receive input channel 7
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
164
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
20
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
EVADC_G9CH3
P00.9
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
Analog input channel 3, group 9
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
P00.10
T12 PWM channel 62
Monitor input 1
Reference input 1
21
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input channel 9
Digital datastream input, channel 1
Analog input channel 2, group 9
General-purpose output
GTM muxed output
GTM_TIM1_IN1_1
GTM_TIM0_IN1_1
SENT_SENT9B
EDSADC_DSDIN1A
EVADC_G9CH2
P00.10
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT19
ASCLIN4_ASCLK
—
Shift clock output
Reserved
—
Reserved
—
Reserved
SENT_SPC9
Transmit output
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
165
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-34 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
22
P00.11
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trap input capture
GTM_TIM1_IN2_1
GTM_TIM0_IN2_1
CCU60_CTRAPA
EDSADC_DSCIN0A
CCU61_T12HRE
EVADC_G9CH1
P00.11
Modulator clock input, channel 0
External timer start 12
Analog input channel 1, group 9
General-purpose output
GTM muxed output
Slave select signal output
Reserved
AI
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT20
ASCLIN4_ASLSO
—
EDSADC_DSCOUT0
—
Modulator clock output
Reserved
—
Reserved
—
Reserved
23
P00.12
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
EVADC_G9CH0
P00.12
Digital datastream input, channel 0
Receive input
AI
Analog input channel 0, group 9
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
166
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
167
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
2
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Reserved
GTM_TOUT1
IOM_REF0_1
—
O2
O3
O4
O5
O6
O7
QSPI3_SLSO2
EDSADC_CGPWMP
—
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
168
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
3
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
169
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
4
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive Channel B2
CAN receive input node 2
Receive input
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
PSI5_RX0B
P02.3
RXD inputs (receive data) channel 0
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
170
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
5
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
P02.4
CAN receive input node 1
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
171
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
6
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
I2C0_SCLA
PSI5_RX1B
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
RXD inputs (receive data) channel 1
RX data input
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
I2C0_SCL
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
172
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
7
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
173
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
8
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
GPT120_T3EUDA
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Receive input channel 1
Modulator clock input, channel 3
Count direction control input of core timer T3
Hall capture input 1
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
—
Reference input 0
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
174
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-35 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
9
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
QSPI3_SLSO5
ASCLIN8_ASCLK
—
Reference input 0
O2
O3
O4
O5
O6
O7
Master slave select output
Shift clock output
Reserved
EVADC_EMUX02
GETH_MDC
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
175
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-36 Port 10 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
168
P10.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of core timer T6
Receive input
GTM_TIM1_IN4_2
GTM_TIM0_IN4_2
GPT120_T6EUDB
ASCLIN11_ARXA
GETH_RXERC
P10.0
Receive Error MII
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT102
ASCLIN11_ATX
QSPI1_SLSO10
—
Transmit output
Master slave select output
Reserved
—
Reserved
—
Reserved
—
Reserved
169
P10.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
EVADC_FC1BFLOUT
—
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Chip Select
Boundary flag output, FC channel 1
Reserved
—
Reserved
Data Sheet
176
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-36 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
170
P10.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P10.2
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
I
Reserved
QSPI1_SCLK
MSC0_EN0
—
Master SPI clock output
Chip Select
Reserved
—
Reserved
—
Reserved
171
P10.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
Reserved
O7
Data Sheet
177
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-36 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
172
P10.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
P10.4
Trigger/gate input of core timer T3
Receive input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT106
IOM_MON2_11
—
Monitor input 2
O2
O3
O4
O5
O6
O7
I
Reserved
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
Master slave select output
Master SPI data output
Chip Select
—
Reserved
—
Reserved
173
P10.5
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
MSC0_INJ1
Injection signal from port
General-purpose output
GTM muxed output
P10.5
O0
O1
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
Reference input 2
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
—
O6
O7
Slave select signal output
Reserved
Data Sheet
178
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-36 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
174
P10.6
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
P10.6
Slave SPI data input
HWCFG5 pin input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
—
O5
O6
Reserved
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
Slave SPI data output
Monitor input 2
Reference input 2
O7
I
Reserved
175
P10.7
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Count direction control input of core timer T3
Clear to send input
GTM_TIM1_IN0_3
GTM_TIM0_IN0_3
GPT120_T3EUDB
ASCLIN2_ACTSA
QSPI3_MRSTB
SCU_E_REQ0_2
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS1C
P10.7
Hall capture input 1
General-purpose output
GTM muxed output
Reference input 2
Reserved
O0
O1
GTM_TOUT109
IOM_REF2_11
—
O2
O3
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
Data Sheet
179
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-36 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
176
P10.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN5_2
GTM_TIM0_IN5_2
CAN12_RXDB
GPT120_T4INB
QSPI3_SCLKB
SCU_E_REQ1_2
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 2
Trigger/gate input of timer T4
Slave SPI clock inputs
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS2C
Hall capture input 2
General-purpose output
GTM muxed output
Ready to send output
Master SPI clock output
Reserved
P10.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT110
ASCLIN2_ARTS
QSPI3_SCLK
—
—
—
—
Reserved
Reserved
Reserved
Table 2-37 Port 11 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
160
P11.2
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
180
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-37 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
161
P11.3
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
Transmit Channel A
Reserved
O4
O5
O6
O7
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
P11.6
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
162
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM muxed output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
Monitor input 1
Reference input 1
Data Sheet
181
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-37 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
163
P11.9
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT98
—
Reserved
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P11.10
T12 PWM channel 60
Monitor input 1
Reference input 1
165
I
FAST /
General-purpose input
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
182
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-37 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
166
P11.11
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
Reserved
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
Master slave select output
Master slave select output
Chip Select
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P11.12
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
167
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
183
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-38 Port 13 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
156
P13.0
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN5_3
ASCLIN10_ARXC
P13.0
Mux input channel 5 of TIM module 2
PU1 /
VEXT /
ES6
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
MSC0_FCLN
—
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
P13.1
CAN transmit output node 0
157
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 2
PU1 /
VEXT /
ES6
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
Shift-clock direct part of the differential signal
Serial Clock Output
Reserved
—
158
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 2
PU1 /
VEXT /
ES6
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
P13.2
Serial Data Input 1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
—
Reserved
Data Sheet
184
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-38 Port 13 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
159
P13.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN0_3
Mux input channel 0 of TIM module 2
PU1 /
VEXT /
ES6
P13.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT94
ASCLIN10_ASLSO
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
QSPI2_MTSRP
—
MSC0_SOP
Data output - direct part of the differential signal
Reserved
—
—
Reserved
Table 2-39 Port 14 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
142
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
185
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-39 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
143
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
144
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
186
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-39 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
145
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
146
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
187
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-39 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
147
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
CDTM2_DTM4
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT85
—
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
—
Transmit Channel B
Reserved
148
P14.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
—
Transmit Enable Channel B
Reserved
Data Sheet
188
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-39 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
149
P14.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive Channel B0
CAN receive input node 0
CAN receive input node 3
Receive input
GTM_TIM1_IN0_5
GTM_TIM0_IN0_5
ERAY0_RXDB0
CAN10_RXDB
CAN13_RXDA
ASCLIN9_ARXC
P14.7
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
Transmit output
GTM_TOUT87
ASCLIN0_ARTS
QSPI2_SLSO4
ASCLIN9_ATX
—
Reserved
—
Reserved
—
Reserved
150
P14.8
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Receive Channel A0
CAN receive input node 2
Receive input
GTM_TIM2_IN2_3
ERAY0_RXDA0
CAN02_RXDD
ASCLIN1_ARXD
P14.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Slave select signal output
Slave select signal output
Reserved
GTM_TOUT88
ASCLIN5_ASLSO
ASCLIN7_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
Data Sheet
189
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-39 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
151
P14.9
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM2_IN3_3
ASCLIN0_ACTSA
QSPI2_MRSTFN
ASCLIN9_ARXD
P14.9
Mux input channel 3 of TIM module 2
PU1 /
VEXT /
ES
Clear to send input
Master SPI data input (LVDS N line)
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT89
—
MSC0_EN1
CAN10_TXD
ERAY0_TXENB
ERAY0_TXENA
—
Chip Select
CAN transmit output node 0
Transmit Enable Channel B
Transmit Enable Channel A
Reserved
152
P14.10
LVDS_R General-purpose input
X / FAST /
GTM_TIM2_IN4_3
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 2
PU1 /
VEXT /
ES
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT90
—
MSC0_EN0
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
—
Chip Select
Transmit output
Monitor input 2
Reference input 2
CAN transmit output node 2
Monitor input 2
O5
Reference input 2
Transmit Channel A
Reserved
O6
O7
Data Sheet
190
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-40 Port 15 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
133
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
134
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
191
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-40 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
135
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
Slave select input
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN5_4
QSPI2_SLSIA
QSPI2_MRSTE
P15.2
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
Shift clock output
Reserved
O6
O7
I
136
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
Master SPI clock output
Reserved
O3
O4
O5
O6
O7
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
192
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-40 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
137
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
193
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-40 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
138
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
139
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
P15.6
O0
O1
O2
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
194
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-40 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
140
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
P15.7
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
141
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
195
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-41 Port 20 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
116
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Shift clock output
Reserved
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
Trigger output
117
P20.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
Trigger input
GTM_TIM2_IN3_5
CBS_TGI1
GTM_DTMA1_1
CDTM1_DTM4
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT60
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CBS_TGO1
P20.2
Trigger output
118
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
Testmode Enable Input
Data Sheet
196
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-41 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
119
P20.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
124
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
Master slave select output
Reserved
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
—
Reserved
—
Reserved
Data Sheet
197
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-41 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
125
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
CAN receive input node 0
Clear to send input
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
126
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
198
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-41 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
127
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
128
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
199
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-41 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
129
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
130
I
FAST /
PU1 /
VEXT /
ES
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O4
O5
O6
O7
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
200
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-41 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
131
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
132
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
Enter destructive debug mode
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
DMU_FDEST
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
201
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-42 Port 21 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
105
P21.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_6
ASCLIN11_ARXC
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
Reserved
GTM_TOUT51
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM1
Pin Output Value
General-purpose input
Mux input channel 5 of TIM module 2
Receive input
106
P21.1
I
FAST /
PU1 /
VEXT /
ES
GTM_TIM2_IN5_6
ASCLIN11_ARXD
P21.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT52
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM2
Pin Output Value
Data Sheet
202
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-42 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
107
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
108
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
P21.3
Mux input channel 1 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Reserved
GTM_TOUT54
ASCLIN11_ASCLK
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
203
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-42 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
109
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN2_6
Mux input channel 2 of TIM module 1
PU1 /
VEXT /
ES6
GTM_TIM0_IN2_6
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT55
ASCLIN11_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
110
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
204
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-42 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
111
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ.
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
205
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-42 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
113
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Data Sheet
206
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-43 Port 22 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
95
P22.0
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
ASCLIN6_ARXE
QSPI3_MTSRD
P22.0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT47
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MTSR
—
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
—
Reserved
ASCLIN6_ATX
P22.1
Transmit output
96
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive input
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
ASCLIN7_ARXE
QSPI3_MRSTD
P22.1
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT48
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Monitor input 2
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
—
Reserved
ASCLIN7_ATX
Transmit output
Data Sheet
207
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-43 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
97
P22.2
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
P22.2
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT49
ASCLIN5_ATX
QSPI3_SLSO12
Master slave select output
Reserved
—
—
Reserved
—
Reserved
—
Reserved
98
P22.3
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
ASCLIN5_ARXC
QSPI3_SCLKD
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
P22.3
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT50
—
QSPI3_SCLK
Master SPI clock output
Reserved
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
208
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-44 Port 23 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
89
P23.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_4
GTM_TIM0_IN5_4
CAN10_RXDC
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT41
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
90
P23.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Ready to send output
Reserved
GTM_TOUT42
ASCLIN1_ARTS
—
GTM_CLK0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
P23.2
CGM generated clock
CAN transmit output node 0
External Clock 0
Shift clock output
91
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_5
GTM_TIM0_IN6_5
ASCLIN7_ARXC
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT43
—
—
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
—
Reserved
Data Sheet
209
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-44 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
92
P23.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
Receive input
GTM_TIM1_IN7_4
GTM_TIM0_IN7_4
ASCLIN6_ARXA
CAN12_RXDC
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
P23.3
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT44
ASCLIN7_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
93
P23.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TIM1_IN7_5
GTM_TIM0_IN7_5
P23.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT45
ASCLIN6_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
94
P23.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN2_7
GTM_TIM0_IN2_7
P23.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT46
ASCLIN6_ATX
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
210
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-45 Port 32 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
84
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM2_IN2_5
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
85
P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT37
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
86
P32.2
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 3
Receive input
GTM_TIM1_IN3_8
GTM_TIM0_IN3_8
CAN03_RXDB
ASCLIN3_ARXD
P32.2
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT38
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
Data Sheet
211
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-45 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
87
P32.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN4_5
GTM_TIM0_IN4_5
P32.3
O0
O1
O2
GTM_TOUT39
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN3_ASCLK
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Shift clock output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
88
P32.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_5
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT40
—
—
Reserved
GTM_CLK1
—
CGM generated clock
Reserved
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
PMS_DCDCSYNCO
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
O
DC-DC synchronization output
Data Sheet
212
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
70
P33.0
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
IOM_PIN_0
GTM_DTMT1_2
P33.0
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
71
P33.1
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
Receive input
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
P33.1
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
O2
O3
O4
O5
O6
O7
—
Reserved
Data Sheet
213
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
72
P33.2
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
Digital datastream input, channel 2
GPIO pad input to FPC
P33.2
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
—
Reference input 1
O5
O6
O7
I
Control of external analog multiplexer interface 0
Reserved
—
Reserved
73
P33.3
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
SENT_SENT7C
EDSADC_DSCIN1B
IOM_PIN_3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
Modulator clock input, channel 1
GPIO pad input to FPC
P33.3
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
ASCLIN5_ASCLK
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT1
EVADC_EMUX00
—
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
214
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
74
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
IOM_PIN_4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
GPIO pad input to FPC
P33.4
O0
O1
General-purpose output
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
Monitor input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
215
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
75
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
Clear to send input
Hall capture input 2
Receive input channel 5
CAN receive input node 3
GPIO pad input to FPC
P33.5
O0
O1
General-purpose output
GTM_TOUT27
IOM_MON0_5
IOM_GTM_5
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
—
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Reserved
ASCLIN5_ASLSO
Slave select signal output
Data Sheet
216
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
76
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
P33.6
O0
O1
General-purpose output
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
Reserved
ASCLIN2_ASLSO
QSPI2_SLSO11
—
O2
O3
O4
O5
O6
O7
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
217
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
77
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
IOM_PIN_7
P33.7
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
—
GTM-provided inputs to EXOR combiner
Shift clock output
Reserved
O2
O3
O4
O5
O6
O7
ASCLIN8_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
Data Sheet
218
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
78
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
FSP[1..0] Output Signals - Generated by SMU_core
O
Data Sheet
219
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
79
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN2_ASCLK
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Shift clock output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
220
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
80
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
CAN receive input node 1
Receive input
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
P33.10
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
—
Monitor input 0
O2
O3
O4
O5
Master slave select output
Reserved
ASCLIN1_ASLSO
PSI5S_CLK
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
81
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
221
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
82
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 2
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN0_6
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
ASCLIN1_ASCLK
—
Shift clock output
Reserved
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P33.13
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
Reference input 1
83
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
P33.13
Carrier sign signal input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
222
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-47 Analog Inputs
Pin
Symbol
Ctrl. Buffer
Type
Function
67
AN0
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
D / HighZ Analog Input 1
66
65
64
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
AN3
Analog input channel 2, group 0
Positive analog input channel 0, pin A
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
63
62
61
60
59
58
57
56
I
I
I
I
I
I
I
I
D / HighZ Analog Input 4
/ VDDM
EVADC_G0CH4
AN5
Analog input channel 4, group 0
D / HighZ Analog Input 5
/ VDDM
EVADC_G0CH5
AN6
Analog input channel 5, group 0
D / HighZ Analog Input 6
/ VDDM
EVADC_G0CH6
AN7
Analog input channel 6, group 0
D / HighZ Analog Input 7
/ VDDM
EVADC_G0CH7
AN8
Analog input channel 7, group 0
D / HighZ Analog Input 8
/ VDDM
EVADC_G1CH0
AN10
Analog input channel 0, group 1
D / HighZ Analog Input 10
/ VDDM
EVADC_G1CH2
AN11
Analog input channel 2, group 1
D / HighZ Analog Input 11
/ VDDM
EVADC_G1CH3
AN12
Analog input channel 3, group 1
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
EDSADC_EDS0PB
AN13
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
55
50
I
I
/ VDDM
EVADC_G1CH5
EDSADC_EDS0NB
AN16
Analog input channel 5, group 1
Negative analog input channel 0, pin B
D / HighZ Analog Input 16
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
Analog input channel 0, group 2
Analog input FC channel 0
Data Sheet
223
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-47 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
49
AN17
I
D / HighZ Analog Input 17
/ VDDM
EVADC_G2CH1
EVADC_FC1CH0
AN18
Analog input channel 1, group 2
Analog input FC channel 1
D / HighZ Analog Input 18
/ VDDM
48
47
46
I
I
I
EVADC_G2CH2
AN19
Analog input channel 2, group 2
D / HighZ Analog Input 19
/ VDDM
EVADC_G2CH3
AN20
Analog input channel 3, group 2
D / HighZ Analog Input 20
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
45
44
I
I
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
AN24/P40.0
Analog input channel 5, group 2
Negative analog input channel 2, pin A
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
43
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN26/P40.2
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
42
41
I
I
S / HighZ Analog Input 26
/ VDDM
SENT_SENT2A
EVADC_G3CH2
CCU60_CCPOS1D
AN27/P40.3
Receive input channel 2
Analog input channel 2, group 3
Hall capture input 1
S / HighZ Analog Input 27
/ VDDM
SENT_SENT3A
EVADC_G3CH3
CCU60_CCPOS2B
AN28
Receive input channel 3
Analog input channel 3, group 3
Hall capture input 2
40
39
I
I
D / HighZ Analog Input 28
/ VDDM
EVADC_G3CH4
AN29
Analog input channel 4, group 3
D / HighZ Analog Input 29
/ VDDM
EVADC_G3CH5
Analog input channel 5, group 3
Data Sheet
224
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-47 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
38
AN32/P40.4
I
S / HighZ Analog Input 32
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
AN33/P40.5
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
37
I
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
AN35
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
36
35
I
I
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
AN36/P40.6
Analog input channel 3, group 8
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
AN37/P40.7
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
34
33
32
I
I
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
AN38/P40.8
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
AN42
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
27
26
31
I
I
I
D / HighZ Analog Input 42
/ VDDM
EVADC_G8CH10
AN43
Analog input channel 10, group 8
D / HighZ Analog Input 43
/ VDDM
EVADC_G8CH11
AN44
Analog input channel 11, group 8
D / HighZ Analog Input 44
/ VDDM
EVADC_G8CH12
EDSADC_EDS1PC
Analog input channel 12, group 8
Positive analog input channel 1, pin C
Data Sheet
225
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-47 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
30
AN45
I
I
I
D / HighZ Analog Input 45
/ VDDM
EVADC_G8CH13
EDSADC_EDS1NC
AN46
Analog input channel 13, group 8
Negative analog input channel 1, pin C
D / HighZ Analog Input 46
29
28
/ VDDM
EVADC_G8CH14
EDSADC_EDS1PD
AN47
Analog input channel 14, group 8
Positive analog input channel 1, pin D
D / HighZ Analog Input 47
/ VDDM
EVADC_G8CH15
EDSADC_EDS1ND
Analog input channel 15, group 8
Negative analog input channel 1, pin D
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
5. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
6. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-48 System I/O
Pin
Symbol
Ctrl. Buffer
Type
Function
84
VGATE1N
O
—
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
85
VGATE1P
XTAL1
O
I
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
102
103
112
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
XTAL2
O
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
TMS
I
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
DAP: DAP1 Data I/O
DAP1
I/O
114
115
TRST
I
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
TCK
I
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
DAP: DAP0 Clock Input
DAP0
Data Sheet
226
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-48 System I/O (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
120
ESR1
I/O
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
PORST
I
ESR1 pin input
121
122
I/O
PORST / PORST pin
PD /
VEXT
Power On Reset Input. Additional strong PD in case of
power fail.
ESR0
I/O
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
Table 2-49 Supply
Pin
Symbol
Ctrl. Buffer
Type
Function
54
VDDM
I
I
I
I
I
—
—
—
—
—
ADC Analog Power Supply (5V / 3.3V)
Digital Power Supply for Flex Port Pads (5V / 3.3V)
Flash Power Supply (3.3V)
164
154
52
VFLEX
VDDP3
VAREF1
VEVRSB
Positive Analog Reference Voltage 1
69
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
155
10
VDD
VDD
VDD
VDD
VDD
VDD
VEXT
VEXT
VEXT
VSS
I
I
I
I
I
I
I
I
I
I
—
—
—
—
—
—
—
—
—
—
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
Digital Ground (Exposed PAD), VSS
24
68
100
123
153
25
99
E-PAD
Data Sheet
227
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-176 Package Variant Pin
Table 2-49 Supply (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
53
VSSM
VAGND1
VSS
I
I
I
I
—
Analog Ground for VDDM
51
—
Negative Analog Reference Voltage 1
Oscillator Ground, VSS(OSC)
101
104
—
VEXT
—
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT), VEXT(OSC)
Data Sheet
228
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
2.4
LQFP-144 Package Variant Pin Configuration of TC36x
Note:In the following QFP package the VFLEX supply is internally connected to VEXT supply and thus does not
show up in the corresponding package drawings neither supply tables as a dedicated pin.
Table 2-50 Port 00 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
11
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Trap input capture
External timer start 12
Injection signal from port
MDIO Input
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Shift clock output
Transmit output
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
MDIO Output
O
Data Sheet
229
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
12
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
T12 capture input 60
Receive input
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
CAN10_RXDA
PSI5_RX0A
CCU61_CC60INA
SENT_SENT0B
EVADC_G9CH11
P00.1
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
Receive input channel 0
Analog input channel 11, group 9
General-purpose output
GTM muxed output
Reference input 0
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
SENT_SPC0
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
230
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
13
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 2
Receive input channel 1
Analog input channel 10, group 9
General-purpose output
GTM muxed output
GTM_TIM2_IN1_2
SENT_SENT1B
EVADC_G9CH10
P00.2
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
—
Reference input 0
O2
O3
O4
Shift clock output
Reserved
PSI5_TX0
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
231
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
14
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 2
T12 capture input 61
Modulator clock input, channel 3
RXD inputs (receive data) channel 1
CAN receive input node 3
RX data input
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
PSI5_RX1A
CAN03_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
EVADC_G9CH9
P00.3
Receive input channel 2
T12 capture input 61
Analog input channel 9, group 9
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Reserved
EDSADC_DSCOUT3
—
Modulator clock output
Reserved
SENT_SPC2
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
232
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
15
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
EVADC_G9CH8
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
AI
Analog input channel 8, group 9
General-purpose output
GTM muxed output
Reference input 0
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
O2
O3
O4
TX data output
CAN11_TXD
PSI5_TX1
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
233
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
16
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 4 of TIM module 2
T12 capture input 62
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Modulator clock input, channel 2
T12 capture input 62
Receive input channel 4
CAN receive input node 1
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
P00.6
T12 PWM channel 62
Monitor input 1
Reference input 1
17
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 5 of TIM module 2
Digital datastream input, channel 2
Receive input channel 5
Receive input
GTM_TIM2_IN5_1
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
EVADC_G9CH6
P00.6
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
O5
O6
O7
Positive carrier generator output
Reserved
—
Reserved
EVADC_EMUX10
SENT_SPC5
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
234
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
18
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 6 of TIM module 2
T12 capture input 60
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
P00.7
Receive input channel 6
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
—
Transmit output
Reserved
—
Reserved
EVADC_EMUX11
SENT_SPC6
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
P00.8
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
19
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 2
T12 capture input 61
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
P00.8
Receive input channel 7
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
235
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
20
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
EVADC_G9CH3
P00.9
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
AI
Analog input channel 3, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
236
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-50 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
21
P00.12
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
Digital datastream input, channel 0
Receive input
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
EVADC_G9CH0
P00.12
AI
Analog input channel 0, group 9
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
237
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
238
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
2
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Reserved
GTM_TOUT1
IOM_REF0_1
—
O2
O3
O4
O5
O6
O7
QSPI3_SLSO2
EDSADC_CGPWMP
—
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
239
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
3
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
240
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
4
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive Channel B2
CAN receive input node 2
Receive input
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
PSI5_RX0B
P02.3
RXD inputs (receive data) channel 0
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
241
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
5
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
P02.4
CAN receive input node 1
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
242
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
6
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
I2C0_SCLA
PSI5_RX1B
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
RXD inputs (receive data) channel 1
RX data input
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
I2C0_SCL
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
243
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
7
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
244
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
8
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
GPT120_T3EUDA
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Receive input channel 1
Modulator clock input, channel 3
Count direction control input of core timer T3
Hall capture input 1
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
—
Reference input 0
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
245
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-51 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
9
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
QSPI3_SLSO5
ASCLIN8_ASCLK
—
Reference input 0
O2
O3
O4
O5
O6
O7
Master slave select output
Shift clock output
Reserved
EVADC_EMUX02
GETH_MDC
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
246
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-52 Port 10 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
140
P10.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Chip Select
EVADC_FC1BFLOUT
—
Boundary flag output, FC channel 1
Reserved
—
Reserved
141
P10.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P10.2
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
Reserved
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
QSPI1_SCLK
Master SPI clock output
Chip Select
MSC0_EN0
—
—
—
Reserved
Reserved
Reserved
Data Sheet
247
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-52 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
142
P10.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
143
P10.5
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
MSC0_INJ1
P10.5
Injection signal from port
General-purpose output
GTM muxed output
Reference input 2
O0
O1
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
—
O6
O7
Slave select signal output
Reserved
Data Sheet
248
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-52 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
144
P10.6
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
P10.6
Slave SPI data input
HWCFG5 pin input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
—
O5
O6
Reserved
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O7
Table 2-53 Port 11 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
132
P11.2
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
249
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-53 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
133
P11.3
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
Transmit Channel A
Reserved
O4
O5
O6
O7
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
P11.6
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
134
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM muxed output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
Monitor input 1
Reference input 1
Data Sheet
250
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-53 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
135
P11.9
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT98
—
Reserved
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P11.10
T12 PWM channel 60
Monitor input 1
Reference input 1
137
I
FAST /
General-purpose input
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
251
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-53 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
138
P11.11
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
Reserved
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
Master slave select output
Master slave select output
Chip Select
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P11.12
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
139
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
252
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-54 Port 13 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
128
P13.0
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN5_3
ASCLIN10_ARXC
P13.0
Mux input channel 5 of TIM module 2
PU1 /
VEXT /
ES6
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
MSC0_FCLN
—
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
P13.1
CAN transmit output node 0
129
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 2
PU1 /
VEXT /
ES6
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
Shift-clock direct part of the differential signal
Serial Clock Output
Reserved
—
130
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 2
PU1 /
VEXT /
ES6
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
P13.2
Serial Data Input 1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
—
Reserved
Data Sheet
253
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-54 Port 13 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
131
P13.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN0_3
Mux input channel 0 of TIM module 2
PU1 /
VEXT /
ES6
P13.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT94
ASCLIN10_ASLSO
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
QSPI2_MTSRP
—
MSC0_SOP
Data output - direct part of the differential signal
Reserved
—
—
Reserved
Table 2-55 Port 14 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
118
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
254
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-55 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
119
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
120
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
255
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-55 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
121
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
122
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
256
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-55 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
123
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
CDTM2_DTM4
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT85
—
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
—
Transmit Channel B
Reserved
124
P14.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
—
Transmit Enable Channel B
Reserved
Data Sheet
257
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-56 Port 15 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
109
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
110
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
258
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-56 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
111
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
Slave select input
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN5_4
QSPI2_SLSIA
QSPI2_MRSTE
P15.2
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
Shift clock output
Reserved
O6
O7
I
112
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
Master SPI clock output
Reserved
O3
O4
O5
O6
O7
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
259
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-56 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
113
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
260
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-56 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
114
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
115
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
P15.6
O0
O1
O2
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
261
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-56 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
116
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
P15.7
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
117
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
262
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-57 Port 20 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
93
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
Shift clock output
Reserved
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
P20.2
Trigger output
94
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
Testmode Enable Input
Data Sheet
263
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-57 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
95
P20.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
100
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
Master slave select output
Reserved
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
—
Reserved
—
Reserved
Data Sheet
264
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-57 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
101
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
CAN receive input node 0
Clear to send input
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
102
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
265
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-57 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
103
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
104
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
266
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-57 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
105
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
106
I
FAST /
PU1 /
VEXT /
ES
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O4
O5
O6
O7
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
267
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-57 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
107
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
108
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
Enter destructive debug mode
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
DMU_FDEST
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
268
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-58 Port 21 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
84
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
85
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
P21.3
Mux input channel 1 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Reserved
GTM_TOUT54
ASCLIN11_ASCLK
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
269
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-58 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
86
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN2_6
Mux input channel 2 of TIM module 1
PU1 /
VEXT /
ES6
GTM_TIM0_IN2_6
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT55
ASCLIN11_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
87
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
270
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-58 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
88
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ.
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
271
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-58 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
90
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Data Sheet
272
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-59 Port 22 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
74
P22.0
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
ASCLIN6_ARXE
QSPI3_MTSRD
P22.0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT47
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MTSR
—
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
—
Reserved
ASCLIN6_ATX
P22.1
Transmit output
75
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive input
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
ASCLIN7_ARXE
QSPI3_MRSTD
P22.1
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT48
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Monitor input 2
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
—
Reserved
ASCLIN7_ATX
Transmit output
Data Sheet
273
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-59 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
76
P22.2
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
P22.2
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT49
ASCLIN5_ATX
QSPI3_SLSO12
Master slave select output
Reserved
—
—
Reserved
—
Reserved
—
Reserved
77
P22.3
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
ASCLIN5_ARXC
QSPI3_SCLKD
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
P22.3
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT50
—
QSPI3_SCLK
Master SPI clock output
Reserved
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
274
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-60 Port 23 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
73
P23.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT42
ASCLIN1_ARTS
—
Ready to send output
Reserved
GTM_CLK0
CGM generated clock
CAN transmit output node 0
External Clock 0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
Shift clock output
Table 2-61 Port 32 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
70
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM2_IN2_5
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
71
P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT37
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
275
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-61 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
72
P32.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_5
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT40
—
—
Reserved
GTM_CLK1
—
CGM generated clock
Reserved
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
PMS_DCDCSYNCO
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
O
DC-DC synchronization output
Data Sheet
276
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
60
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
IOM_PIN_4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
GPIO pad input to FPC
P33.4
O0
O1
General-purpose output
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
Monitor input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
277
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
61
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
Clear to send input
Hall capture input 2
Receive input channel 5
CAN receive input node 3
GPIO pad input to FPC
P33.5
O0
O1
General-purpose output
GTM_TOUT27
IOM_MON0_5
IOM_GTM_5
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
—
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Reserved
ASCLIN5_ASLSO
Slave select signal output
Data Sheet
278
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
62
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
P33.6
O0
O1
General-purpose output
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
Reserved
ASCLIN2_ASLSO
QSPI2_SLSO11
—
O2
O3
O4
O5
O6
O7
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
279
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
63
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
IOM_PIN_7
P33.7
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
—
GTM-provided inputs to EXOR combiner
Shift clock output
Reserved
O2
O3
O4
O5
O6
O7
ASCLIN8_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
Data Sheet
280
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
64
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
FSP[1..0] Output Signals - Generated by SMU_core
O
Data Sheet
281
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
65
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN2_ASCLK
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Shift clock output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
282
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
66
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
CAN receive input node 1
Receive input
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
P33.10
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
—
Monitor input 0
O2
O3
O4
O5
Master slave select output
Reserved
ASCLIN1_ASLSO
PSI5S_CLK
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
67
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
283
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-62 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
68
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 2
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN0_6
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
ASCLIN1_ASCLK
—
Shift clock output
Reserved
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P33.13
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
Reference input 1
69
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
P33.13
Carrier sign signal input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
284
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-63 Analog Inputs
Pin
Symbol
Ctrl. Buffer
Type
Function
57
AN0
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
D / HighZ Analog Input 1
56
55
54
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
AN3
Analog input channel 2, group 0
Positive analog input channel 0, pin A
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
53
52
51
50
49
48
47
46
I
I
I
I
I
I
I
I
D / HighZ Analog Input 4
/ VDDM
EVADC_G0CH4
AN5
Analog input channel 4, group 0
D / HighZ Analog Input 5
/ VDDM
EVADC_G0CH5
AN6
Analog input channel 5, group 0
D / HighZ Analog Input 6
/ VDDM
EVADC_G0CH6
AN7
Analog input channel 6, group 0
D / HighZ Analog Input 7
/ VDDM
EVADC_G0CH7
AN8
Analog input channel 7, group 0
D / HighZ Analog Input 8
/ VDDM
EVADC_G1CH0
AN10
Analog input channel 0, group 1
D / HighZ Analog Input 10
/ VDDM
EVADC_G1CH2
AN11
Analog input channel 2, group 1
D / HighZ Analog Input 11
/ VDDM
EVADC_G1CH3
AN12
Analog input channel 3, group 1
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
EDSADC_EDS0PB
AN13
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
45
40
I
I
/ VDDM
EVADC_G1CH5
EDSADC_EDS0NB
AN16
Analog input channel 5, group 1
Negative analog input channel 0, pin B
D / HighZ Analog Input 16
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
Analog input channel 0, group 2
Analog input FC channel 0
Data Sheet
285
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-63 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
39
AN17
I
I
I
I
D / HighZ Analog Input 17
/ VDDM
EVADC_G2CH1
EVADC_FC1CH0
AN20
Analog input channel 1, group 2
Analog input FC channel 1
D / HighZ Analog Input 20
38
37
36
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
AN24/P40.0
Analog input channel 5, group 2
Negative analog input channel 2, pin A
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
35
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN35
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
34
33
I
I
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
AN36/P40.6
Analog input channel 3, group 8
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
AN37/P40.7
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
32
31
I
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
AN38/P40.8
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
Data Sheet
286
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-63 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
30
AN39/P40.9
I
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
AN42
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
25
24
29
I
I
I
D / HighZ Analog Input 42
/ VDDM
EVADC_G8CH10
AN43
Analog input channel 10, group 8
D / HighZ Analog Input 43
/ VDDM
EVADC_G8CH11
AN44
Analog input channel 11, group 8
D / HighZ Analog Input 44
/ VDDM
EVADC_G8CH12
EDSADC_EDS1PC
AN45
Analog input channel 12, group 8
Positive analog input channel 1, pin C
D / HighZ Analog Input 45
28
27
26
I
I
I
/ VDDM
EVADC_G8CH13
EDSADC_EDS1NC
AN46
Analog input channel 13, group 8
Negative analog input channel 1, pin C
D / HighZ Analog Input 46
/ VDDM
EVADC_G8CH14
EDSADC_EDS1PD
AN47
Analog input channel 14, group 8
Positive analog input channel 1, pin D
D / HighZ Analog Input 47
/ VDDM
EVADC_G8CH15
EDSADC_EDS1ND
Analog input channel 15, group 8
Negative analog input channel 1, pin D
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
7. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
8. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-64 System I/O
Pin
Symbol
Ctrl. Buffer
Type
Function
70
VGATE1N
O
—
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
71
81
VGATE1P
XTAL1
O
I
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
Data Sheet
287
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-64 System I/O (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
82
XTAL2
O
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
89
TMS
I
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
DAP: DAP1 Data I/O
DAP1
I/O
91
92
96
TRST
I
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
TCK
I
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
DAP: DAP0 Clock Input
DAP0
ESR1
I/O
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
PORST
I
ESR1 pin input
97
98
I/O
PORST / PORST pin
PD /
VEXT
Power On Reset Input. Additional strong PD in case of
power fail.
ESR0
I/O
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
Table 2-65 Supply
Pin
Symbol
Ctrl. Buffer
Type
Function
44
VDDM
I
I
I
I
I
—
—
—
—
—
ADC Analog Power Supply (5V / 3.3V)
Digital Power Supply for Flex Port Pads (5V / 3.3V)
Flash Power Supply (3.3V)
136
126
42
VFLEX
VDDP3
VAREF1
VEVRSB
Positive Analog Reference Voltage 1
59
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
Data Sheet
288
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TC36x AA-Step
TC36x Pin Definition and Functions: LQFP-144 Package Variant Pin
Table 2-65 Supply (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
VDD
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Digital Core Power Supply (1.25V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Ground (Exposed PAD), VSS
Analog Ground for VDDM
125
23
VEXT
VEXT
VEXT
VDD
78
127
22
VDD
58
VDD
79
VDD
99
VDD
E-PAD
43
VSS
VSSM
VAGND1
VSS
41
Negative Analog Reference Voltage 1
Oscillator Ground, VSS(OSC)
80
83
VEXT
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT), VEXT(OSC)
Data Sheet
289
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
2.5
TQFP-144 Package Variant Pin Configuration of TC36x
Note:In the following QFP package the VFLEX supply is internally connected to VEXT supply and thus does not
show up in the corresponding package drawings neither supply tables as a dedicated pin.
Table 2-66 Port 00 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
11
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Trap input capture
External timer start 12
Injection signal from port
MDIO Input
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Shift clock output
Transmit output
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
MDIO Output
O
Data Sheet
290
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
12
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
T12 capture input 60
Receive input
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
CAN10_RXDA
PSI5_RX0A
CCU61_CC60INA
SENT_SENT0B
EVADC_G9CH11
P00.1
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
Receive input channel 0
Analog input channel 11, group 9
General-purpose output
GTM muxed output
Reference input 0
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
SENT_SPC0
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
291
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
13
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 2
Receive input channel 1
Analog input channel 10, group 9
General-purpose output
GTM muxed output
GTM_TIM2_IN1_2
SENT_SENT1B
EVADC_G9CH10
P00.2
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
—
Reference input 0
O2
O3
O4
Shift clock output
Reserved
PSI5_TX0
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
292
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
14
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 2
T12 capture input 61
Modulator clock input, channel 3
RXD inputs (receive data) channel 1
CAN receive input node 3
RX data input
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
PSI5_RX1A
CAN03_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
EVADC_G9CH9
P00.3
Receive input channel 2
T12 capture input 61
Analog input channel 9, group 9
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Reserved
EDSADC_DSCOUT3
—
Modulator clock output
Reserved
SENT_SPC2
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
293
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
15
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
EVADC_G9CH8
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
AI
Analog input channel 8, group 9
General-purpose output
GTM muxed output
Reference input 0
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
O2
O3
O4
TX data output
CAN11_TXD
PSI5_TX1
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
294
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
16
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 4 of TIM module 2
T12 capture input 62
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Modulator clock input, channel 2
T12 capture input 62
Receive input channel 4
CAN receive input node 1
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
P00.6
T12 PWM channel 62
Monitor input 1
Reference input 1
17
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 5 of TIM module 2
Digital datastream input, channel 2
Receive input channel 5
Receive input
GTM_TIM2_IN5_1
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
EVADC_G9CH6
P00.6
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
O5
O6
O7
Positive carrier generator output
Reserved
—
Reserved
EVADC_EMUX10
SENT_SPC5
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
295
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
18
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 6 of TIM module 2
T12 capture input 60
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
P00.7
Receive input channel 6
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
—
Transmit output
Reserved
—
Reserved
EVADC_EMUX11
SENT_SPC6
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
P00.8
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 60
Monitor input 1
Reference input 1
19
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 2
T12 capture input 61
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
P00.8
Receive input channel 7
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Control of external analog multiplexer interface 1
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
296
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
20
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
EVADC_G9CH3
P00.9
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
AI
Analog input channel 3, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
297
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-66 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
21
P00.12
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
Digital datastream input, channel 0
Receive input
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
EVADC_G9CH0
P00.12
AI
Analog input channel 0, group 9
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
298
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
299
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
2
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
Reserved
GTM_TOUT1
IOM_REF0_1
—
O2
O3
O4
O5
O6
O7
QSPI3_SLSO2
EDSADC_CGPWMP
—
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
300
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
3
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
301
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
4
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive Channel B2
CAN receive input node 2
Receive input
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
PSI5_RX0B
P02.3
RXD inputs (receive data) channel 0
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
302
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
5
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
P02.4
CAN receive input node 1
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
303
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
6
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
I2C0_SCLA
PSI5_RX1B
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
RXD inputs (receive data) channel 1
RX data input
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
I2C0_SCL
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
304
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
7
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
305
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
8
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
GPT120_T3EUDA
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Receive input channel 1
Modulator clock input, channel 3
Count direction control input of core timer T3
Hall capture input 1
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
—
Reference input 0
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
306
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-67 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
9
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
QSPI3_SLSO5
ASCLIN8_ASCLK
—
Reference input 0
O2
O3
O4
O5
O6
O7
Master slave select output
Shift clock output
Reserved
EVADC_EMUX02
GETH_MDC
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
307
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-68 Port 10 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
140
P10.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Chip Select
EVADC_FC1BFLOUT
—
Boundary flag output, FC channel 1
Reserved
—
Reserved
141
P10.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P10.2
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
Reserved
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
QSPI1_SCLK
Master SPI clock output
Chip Select
MSC0_EN0
—
—
—
Reserved
Reserved
Reserved
Data Sheet
308
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-68 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
142
P10.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
143
P10.5
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
MSC0_INJ1
P10.5
Injection signal from port
General-purpose output
GTM muxed output
Reference input 2
O0
O1
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
—
O6
O7
Slave select signal output
Reserved
Data Sheet
309
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-68 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
144
P10.6
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
P10.6
Slave SPI data input
HWCFG5 pin input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
—
O5
O6
Reserved
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O7
Table 2-69 Port 11 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
132
P11.2
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
310
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-69 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
133
P11.3
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
Transmit Channel A
Reserved
O4
O5
O6
O7
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
P11.6
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
134
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM muxed output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
Monitor input 1
Reference input 1
Data Sheet
311
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-69 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
136
P11.8
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM2_IN5_8
GETH_RXD2A
Mux input channel 5 of TIM module 2
Receive Data 2 MII and RGMII (RGMII can use RXD2A
only)
CAN12_RXDD
CAN receive input node 2
General-purpose output
GTM muxed output
Reserved
P11.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT124
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
135
P11.9
FAST /
General-purpose input
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT98
—
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
312
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-69 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
137
P11.10
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
P11.11
T12 PWM channel 62
Monitor input 1
Reference input 1
138
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Master slave select output
Master slave select output
Chip Select
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
313
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-69 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
139
P11.12
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
CAN transmit output node 3
Monitor input 2
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Table 2-70 Port 13 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
128
P13.0
I
LVDS_TX General-purpose input
/ FAST /
PU1 /
VEXT /
ES6
GTM_TIM2_IN5_3
ASCLIN10_ARXC
P13.0
Mux input channel 5 of TIM module 2
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
MSC0_FCLN
—
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
CAN transmit output node 0
Data Sheet
314
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-70 Port 13 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
129
P13.1
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 2
PU1 /
VEXT /
ES6
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
—
Shift-clock direct part of the differential signal
Serial Clock Output
Reserved
130
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 2
PU1 /
VEXT /
ES6
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
P13.2
Serial Data Input 1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
—
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
Reserved
131
P13.3
LVDS_TX General-purpose input
/ FAST /
GTM_TIM2_IN0_3
P13.3
Mux input channel 0 of TIM module 2
PU1 /
VEXT /
ES6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT94
ASCLIN10_ASLSO
QSPI2_MTSRP
—
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
—
Reserved
Data Sheet
315
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-71 Port 14 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
118
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
316
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-71 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
119
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
120
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
317
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-71 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
121
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
122
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
318
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-71 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
123
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
CDTM2_DTM4
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT85
—
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
—
Transmit Channel B
Reserved
124
P14.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
—
Transmit Enable Channel B
Reserved
Data Sheet
319
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-72 Port 15 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
109
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
110
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
320
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-72 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
111
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
Slave select input
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN5_4
QSPI2_SLSIA
QSPI2_MRSTE
P15.2
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
Shift clock output
Reserved
O6
O7
I
112
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
Master SPI clock output
Reserved
O3
O4
O5
O6
O7
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
321
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-72 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
113
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
322
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-72 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
114
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
115
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
P15.6
O0
O1
O2
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
323
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-72 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
116
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
P15.7
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
117
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
324
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-73 Port 20 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
93
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
Shift clock output
Reserved
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
P20.2
Trigger output
94
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
Testmode Enable Input
Data Sheet
325
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-73 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
95
P20.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
100
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
Master slave select output
Reserved
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
—
Reserved
—
Reserved
Data Sheet
326
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-73 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
101
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
CAN receive input node 0
Clear to send input
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
102
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
327
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-73 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
103
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
104
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
328
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-73 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
105
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
106
I
FAST /
PU1 /
VEXT /
ES
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O4
O5
O6
O7
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
329
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-73 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
107
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
108
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
Enter destructive debug mode
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
DMU_FDEST
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
330
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-74 Port 21 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
84
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
85
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
P21.3
Mux input channel 1 of TIM module 1
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Reserved
GTM_TOUT54
ASCLIN11_ASCLK
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
331
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-74 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
86
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN2_6
Mux input channel 2 of TIM module 1
PU1 /
VEXT /
ES6
GTM_TIM0_IN2_6
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT55
ASCLIN11_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
87
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
332
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-74 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
88
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ.
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
333
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-74 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
90
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Data Sheet
334
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-75 Port 22 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
74
P22.0
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
ASCLIN6_ARXE
QSPI3_MTSRD
P22.0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT47
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MTSR
—
Monitor input 2
Reference input 2
Master SPI data output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
—
Reserved
ASCLIN6_ATX
P22.1
Transmit output
75
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive input
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
ASCLIN7_ARXE
QSPI3_MRSTD
P22.1
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT48
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Monitor input 2
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
—
Reserved
ASCLIN7_ATX
Transmit output
Data Sheet
335
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-75 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
76
P22.2
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
P22.2
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT49
ASCLIN5_ATX
QSPI3_SLSO12
Master slave select output
Reserved
—
—
Reserved
—
Reserved
—
Reserved
77
P22.3
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
ASCLIN5_ARXC
QSPI3_SCLKD
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
P22.3
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT50
—
QSPI3_SCLK
Master SPI clock output
Reserved
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
336
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-76 Port 23 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
73
P23.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT42
ASCLIN1_ARTS
—
Ready to send output
Reserved
GTM_CLK0
CGM generated clock
CAN transmit output node 0
External Clock 0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
Shift clock output
Table 2-77 Port 32 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
70
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM2_IN2_5
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
71
P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT37
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
337
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions
Pin
Symbol
Ctrl. Buffer
Function
Type
56
P33.0
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
IOM_PIN_0
GTM_DTMT1_2
P33.0
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
57
P33.1
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
Receive input
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
P33.1
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
O2
O3
O4
O5
O6
O7
—
Reserved
Data Sheet
338
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
58
P33.2
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
Digital datastream input, channel 2
GPIO pad input to FPC
P33.2
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
—
Reference input 1
O5
O6
O7
I
Control of external analog multiplexer interface 0
Reserved
—
Reserved
59
P33.3
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
SENT_SENT7C
EDSADC_DSCIN1B
IOM_PIN_3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
Modulator clock input, channel 1
GPIO pad input to FPC
P33.3
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
ASCLIN5_ASCLK
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT1
EVADC_EMUX00
—
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
60
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
IOM_PIN_4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
GPIO pad input to FPC
P33.4
O0
O1
General-purpose output
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
Monitor input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
340
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
61
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
Clear to send input
Hall capture input 2
Receive input channel 5
CAN receive input node 3
GPIO pad input to FPC
P33.5
O0
O1
General-purpose output
GTM_TOUT27
IOM_MON0_5
IOM_GTM_5
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
—
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Reserved
ASCLIN5_ASLSO
Slave select signal output
Data Sheet
341
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
62
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
P33.6
O0
O1
General-purpose output
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
Reserved
ASCLIN2_ASLSO
QSPI2_SLSO11
—
O2
O3
O4
O5
O6
O7
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
342
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
63
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
IOM_PIN_7
P33.7
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
—
GTM-provided inputs to EXOR combiner
Shift clock output
Reserved
O2
O3
O4
O5
O6
O7
ASCLIN8_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
Data Sheet
343
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
64
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
FSP[1..0] Output Signals - Generated by SMU_core
O
Data Sheet
344
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
65
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN2_ASCLK
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Shift clock output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
345
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
66
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
CAN receive input node 1
Receive input
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
P33.10
GPIO pad input to FPC
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
—
Monitor input 0
O2
O3
O4
O5
Master slave select output
Reserved
ASCLIN1_ASLSO
PSI5S_CLK
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
67
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
346
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-78 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
68
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 2
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM2_IN0_6
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
ASCLIN1_ASCLK
—
Shift clock output
Reserved
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
Reference input 1
Table 2-79 Analog Inputs
Pin
Symbol
Ctrl. Buffer
Type
Function
51
AN0
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
50
49
48
D / HighZ Analog Input 1
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
AN3
Analog input channel 2, group 0
Positive analog input channel 0, pin A
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
D / HighZ Analog Input 4
/ VDDM
47
46
I
I
EVADC_G0CH4
AN5
Analog input channel 4, group 0
D / HighZ Analog Input 5
/ VDDM
EVADC_G0CH5
Analog input channel 5, group 0
Data Sheet
347
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-79 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
45
AN11
I
D / HighZ Analog Input 11
/ VDDM
EVADC_G1CH3
AN16
Analog input channel 3, group 1
40
39
38
37
36
I
D / HighZ Analog Input 16
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
AN17
Analog input channel 0, group 2
Analog input FC channel 0
D / HighZ Analog Input 17
I
I
I
I
/ VDDM
EVADC_G2CH1
EVADC_FC1CH0
AN20
Analog input channel 1, group 2
Analog input FC channel 1
D / HighZ Analog Input 20
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
AN24/P40.0
Analog input channel 5, group 2
Negative analog input channel 2, pin A
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
35
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN26/P40.2
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
34
33
I
I
S / HighZ Analog Input 26
/ VDDM
SENT_SENT2A
EVADC_G3CH2
CCU60_CCPOS1D
AN27/P40.3
Receive input channel 2
Analog input channel 2, group 3
Hall capture input 1
S / HighZ Analog Input 27
/ VDDM
SENT_SENT3A
EVADC_G3CH3
CCU60_CCPOS2B
AN28
Receive input channel 3
Analog input channel 3, group 3
Hall capture input 2
32
31
I
I
D / HighZ Analog Input 28
/ VDDM
EVADC_G3CH4
AN32/P40.4
Analog input channel 4, group 3
S / HighZ Analog Input 32
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
Data Sheet
348
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-79 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
30
AN33/P40.5
I
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
AN34
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
29
28
27
I
I
I
D / HighZ Analog Input 34
/ VDDM
EVADC_G8CH2
AN35
Analog input channel 2, group 8
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
AN36/P40.6
Analog input channel 3, group 8
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
AN37/P40.7
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
26
25
24
I
I
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
AN38/P40.8
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
Data Sheet
349
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
9. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
10. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-80 System I/O
Pin
Symbol
Ctrl. Buffer
Type
Function
70
VGATE1N
O
—
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
71
81
82
89
VGATE1P
XTAL1
O
I
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
XTAL2
O
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
TMS
I
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
DAP: DAP1 Data I/O
DAP1
I/O
91
92
96
TRST
I
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
TCK
I
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
DAP: DAP0 Clock Input
DAP0
ESR1
I/O
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
PORST
I
ESR1 pin input
97
I/O
PORST / PORST pin
PD /
VEXT
Power On Reset Input. Additional strong PD in case of
power fail.
Data Sheet
350
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TC36x AA-Step
TC36x Pin Definition and Functions: TQFP-144 Package Variant Pin
Table 2-80 System I/O (cont’d)
Pin
Symbol
Ctrl. Buffer
Function
Type
98
ESR0
I/O
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
Table 2-81 Supply
Pin
Symbol
Ctrl. Buffer
Type
Function
44
VDDM
VDDP3
VAREF1
NC
I
I
I
I
—
—
—
—
ADC Analog Power Supply (5V / 3.3V)
Flash Power Supply (3.3V)
126
42
Positive Analog Reference Voltage 1
53, 54, 55
Not connected. These pins are reserved for future
extensions and shall not be connected externally
52
VEVRSB
I
—
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
10
VDD
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Digital Core Power Supply (1.25V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Ground (Exposed PAD), VSS
Analog Ground for VDDM
125
23
VEXT
VEXT
VEXT
VEXT
VDD
78
69
127
22
VDD
79
VDD
99
VDD
72
VDD
E-PAD
43
VSS
VSSM
VAGND1
VSS
41
Negative Analog Reference Voltage 1
Oscillator Ground, VSS(OSC)
80
83
VEXT
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT), VEXT(OSC)
Data Sheet
351
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TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
2.6
Sequence of Pads in Pad Frame
Table 2-82 Pad List
Number
Pad Name
Pad Type
X
Y
Comment
1
P15.0
P15.1
P15.2
P15.3
P15.4
P15.5
FAST / PU1 / 291978
VEXT / ES
185148
General-purpose I/O
2
3
4
5
6
FAST / PU1 / 392976
VEXT / ES
185148
185148
362646
185148
362646
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 495972
VEXT / ES
FAST / PU1 / 600930
VEXT / ES
FAST / PU1 / 650934
VEXT / ES
FAST / PU1 / 700938
VEXT / ES
7
8
9
VSS
Vx
Vx
750942
802980
185148
362646
185148
Supply Voltage
VEXT
P15.6
Supply Voltage
FAST / PU1 / 852984
VEXT / ES
General-purpose I/O
10
P15.7
FAST / PU1 / 902988
VEXT / ES
362646
General-purpose I/O
11
12
13
VSS
Vx
Vx
978948
185148
362646
185148
Supply Voltage
VDD
P15.8
1054494
Supply Voltage
FAST / PU1 / 1106532
VEXT / ES
General-purpose I/O
14
15
VDDP3
P14.0
Vx
1158570
362646
185148
Supply Voltage
FAST / PU1 / 1210608
VEXT / ES2
General-purpose I/O
16
17
18
19
20
21
22
P14.1
P14.2
P14.3
P14.4
P14.5
P14.6
P14.7
FAST / PU1 / 1262646
VEXT / ES2
362646
185148
362646
185148
362646
185148
362646
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU2 / 1314684
VEXT / ES
SLOW / PU2 / 1366722
VEXT / ES
SLOW / PU2 / 1418760
VEXT / ES
FAST / PU2 / 1470798
VEXT / ES
FAST / PU1 / 1522836
VEXT / ES
SLOW / PU1 / 1572840
VEXT / ES
Data Sheet
352
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
23
P14.8
SLOW / PU1 / 1624293
VEXT / ES
185148
General-purpose I/O
24
25
P14.9
LVDS_RX /
FAST / PU1 /
VEXT / ES
1694340
362646
362646
General-purpose I/O
General-purpose I/O
P14.10
LVDS_RX /
FAST / PU1 /
VEXT / ES
1793340
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
1868391
1924389
1976427
2028465
2080503
2262501
2312505
2362509
2442267
2516445
2586627
2654505
2720385
2778876
2878884
185148
362646
185148
362646
185148
185148
362646
185148
362646
185148
362646
185148
362646
185148
185148
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VEXT
VSS
VEXT
VEXT
VDDP3
VDDP3
VDDP3
VDD
VSS
VDD
VSS
VDD
VSS
P13.0
LVDS_TX /
FAST / PU1 /
VEXT / ES6
41
42
43
P13.1
P13.2
P13.3
LVDS_TX /
FAST / PU1 /
VEXT / ES6
2977884
3148884
3247884
185148
362646
362646
General-purpose I/O
General-purpose I/O
General-purpose I/O
LVDS_TX /
FAST / PU1 /
VEXT / ES6
LVDS_TX /
FAST / PU1 /
VEXT / ES6
44
45
46
47
P12.0
SLOW / PU1 / 3381597
VFLEX / ES
179145
348147
179145
348147
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
P12.1
SLOW / PU1 / 3428595
VFLEX / ES
P11.14
P11.13
SLOW / PU1 / 3531933
VFLEX / ES
SLOW / PU1 / 3580191
VFLEX / ES
Data Sheet
353
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
48
P11.15
SLOW / PU1 / 3627189
VFLEX / ES
179145
General-purpose I/O
49
P11.0
RFAST / PU1 / 3700593
VFLEX / ES
356643
General-purpose I/O
50
51
VFLEX
P11.1
Vx
3749391
185148
356643
Supply Voltage
RFAST / PU1 / 3822795
VFLEX / ES
General-purpose I/O
52
53
VSS
Vx
3871593
185148
362646
Supply Voltage
P11.2
RFAST / PU1 / 3944997
VFLEX / ES
General-purpose I/O
54
55
VDD
Vx
3993795
185148
348147
Supply Voltage
P11.4
RFAST / PU1 / 4109499
VFLEX / ES
General-purpose I/O
56
57
VSS
Vx
4196997
185148
362646
Supply Voltage
P11.3
RFAST / PU1 / 4270401
VFLEX / ES
General-purpose I/O
58
59
VFLEX
P11.6
Vx
4319199
185148
362646
Supply Voltage
RFAST / PU1 / 4390803
VFLEX / ES
General-purpose I/O
60
61
VSS
Vx
4441401
4491099
185148
356643
Supply Voltage
P11.5
SLOW /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
62
63
P11.7
P11.9
SLOW /
4554387
4602285
179145
362646
General-purpose I/O
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
FAST /
RGMII_Input /
PU1 / VFLEX /
ES
64
65
VFLEX
P11.8
Vx
4652883
4702581
185148
362646
Supply Voltage
SLOW /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
66
P11.10
FAST /
4753179
185148
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
Data Sheet
354
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
67
P11.11
FAST /
4803777
362646
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
68
69
VSS
Vx
4854375
4903173
185148
362646
Supply Voltage
P11.12
FAST /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
70
71
72
73
P10.0
P10.1
P10.2
P10.3
SLOW / PU1 / 4979187
VEXT / ES
185148
362646
185148
362646
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 5029191
VEXT / ES
FAST / PU1 / 5079195
VEXT / ES
FAST / PU1 / 5129199
VEXT / ES
74
75
76
VSS
Vx
Vx
5179203
5231241
185148
362646
185148
Supply Voltage
VEXT
P10.4
Supply Voltage
FAST / PU1 / 5281245
VEXT / ES
General-purpose I/O
77
78
VDD
Vx
5331249
362646
185148
Supply Voltage
P10.5
SLOW / PU2 / 5383287
VEXT / ES
General-purpose I/O
79
P10.7
SLOW / PU1 / 5435325
VEXT / ES
362646
General-purpose I/O
80
81
VSS
Vx
5494005
185148
185148
Supply Voltage
P10.6
SLOW / PU2 / 5595003
VEXT / ES
General-purpose I/O
82
83
84
85
86
87
88
P10.8
P02.0
P02.1
P02.2
P02.3
P02.4
VSS
SLOW / PU1 / 5697999
VEXT / ES
185148
291978
392976
495972
600966
700974
800982
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
Supply Voltage
FAST / PU1 / 5801292
VEXT / ES
SLOW / PU1 / 5801292
VEXT / ES
FAST / PU1 / 5801292
VEXT / ES
SLOW / PU1 / 5801292
VEXT / ES
FAST / PU1 / 5801292
VEXT / ES
Vx
5801292
Data Sheet
355
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
89
P02.5
FAST / PU1 / 5801292
VEXT / ES
900990
General-purpose I/O
90
91
92
P02.6
P02.7
P02.8
FAST / PU1 / 5801292
VEXT / ES
1000998
1101006
1201014
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 5801292
VEXT / ES
SLOW / PU1 / 5801292
VEXT / ES
93
VEXT
VSS
VDD
VDD
VSS
VDD
VSS
VSS
VDD
P00.0
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
5801292
5801292
5801292
5801292
5801292
5801292
5801292
5801292
5623794
1301022
1401030
1501038
1601046
1701054
1801062
1902060
2005056
2108052
2165049
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
94
95
96
97
98
99
100
101
102
FAST / PU1 / 5801292
VEXT / ES
103
104
105
106
107
108
109
110
111
112
113
P00.1
P00.2
P00.3
P00.4
P00.5
P00.6
P00.7
P00.8
P00.9
P00.10
P00.11
SLOW / PU1 / 5801292
VEXT / ES
2273540
2328538
2383538
2438536
2493536
2548534
2603534
2658532
2713532
2768530
2823530
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 5623794
VEXT / ES1
SLOW / PU1 / 5801292
VEXT / ES1
SLOW / PU1 / 5623794
VEXT / ES1
SLOW / PU1 / 5801292
VEXT / ES1
SLOW / PU1 / 5623794
VEXT / ES1
SLOW / PU1 / 5801292
VEXT / ES1
SLOW / PU1 / 5623794
VEXT / ES1
SLOW / PU1 / 5801292
VEXT / ES1
SLOW / PU1 / 5623794
VEXT / ES1
SLOW / PU1 / 5801292
VEXT / ES1
Data Sheet
356
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
114
P00.12
SLOW / PU1 / 5623794
VEXT / ES1
2878528
General-purpose I/O
115
116
117
118
119
120
121
VSS
Vx
Vx
Vx
Vx
Vx
Vx
5801292
5801292
5801292
5623794
5801292
5623794
5801292
2933528
3032626
3131726
3186724
3285824
3340822
3439922
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Analog Input 43
VSS
VDD
VDD
VEXT
VEXT
AN43
D / HighZ /
VDDM
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
AN42
D / HighZ /
VDDM
5623794
5801292
5623794
5801292
5623794
5801292
5623794
5801292
5623794
5801292
5623794
5801292
5623794
5801292
5623794
5801292
3494920
3549920
3604918
3659918
3714916
3879914
3934912
3989912
4044910
4099910
4154908
4209908
4264906
4319906
4374904
4429904
Analog Input 42
Analog Input 47
Analog Input 46
Analog Input 45
Analog Input 44
Analog Input 39
Analog Input 38
Analog Input 37
Analog Input 36
Analog Input 35
Analog Input 34
Analog Input 33
Analog Input 32
Analog Input 29
Analog Input 28
Analog Input 27
AN47
D / HighZ /
VDDM
AN46
D / HighZ /
VDDM
AN45
D / HighZ /
VDDM
AN44
D / HighZ /
VDDM
AN39/P40.9
AN38/P40.8
AN37/P40.7
AN36/P40.6
AN35
S / HighZ /
VDDM
S / HighZ /
VDDM
S / HighZ /
VDDM
S / HighZ /
VDDM
D / HighZ /
VDDM
AN34
D / HighZ /
VDDM
AN33/P40.5
AN32/P40.4
AN29
S / HighZ /
VDDM
S / HighZ /
VDDM
D / HighZ /
VDDM
AN28
D / HighZ /
VDDM
AN27/P40.3
S / HighZ /
VDDM
Data Sheet
357
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
138
AN26/P40.2
S / HighZ /
VDDM
5623794
4484902
Analog Input 26
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
AN25/P40.1
AN24/P40.0
AN23
S / HighZ /
VDDM
5801292
5801292
5716440
5593140
5538141
5483142
5428143
5373144
5318145
5263146
5208147
5153148
5098149
5043150
4988151
4539902
4663300
4748292
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
Analog Input 25
Analog Input 24
Analog Input 23
Analog Input 22
Analog Input 41
Analog Input 21
Analog Input 40
Analog Input 20
Analog Input 31
Analog Input 19
Analog Input 30
Analog Input 18
Analog Input 17
Analog Input 16
Analog Input 15
S / HighZ /
VDDM
D / HighZ /
VDDM
AN22
D / HighZ /
VDDM
AN41
D / HighZ /
VDDM
AN21
D / HighZ /
VDDM
AN40
D / HighZ /
VDDM
AN20
D / HighZ /
VDDM
AN31
D / HighZ /
VDDM
AN19
D / HighZ /
VDDM
AN30
D / HighZ /
VDDM
AN18
D / HighZ /
VDDM
AN17
D / HighZ /
VDDM
AN16
D / HighZ /
VDDM
AN15
D / HighZ /
VDDM
154
155
156
157
158
159
160
161
162
163
VAGND1
VAREF1
VAGND0
VAREF0
VSSM
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
4933152
4878153
4823154
4768155
4713156
4658157
4603158
4548159
4369514
4314514
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
VDDM
VSSM
VDDM
VSSM
VDDM
Data Sheet
358
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
164
AN14
D / HighZ /
VDDM
4259516
4748292
Analog Input 14
165
166
167
168
169
170
171
172
173
174
175
176
177
178
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
D / HighZ /
VDDM
4204516
4149518
4094518
4039520
3984520
3929522
3874522
3819524
3764524
3709526
3654526
3599528
3544528
3489530
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
Analog Input 13
Analog Input 12
Analog Input 11
Analog Input 10
Analog Input 9
Analog Input 8
Analog Input 7
Analog Input 6
Analog Input 5
Analog Input 4
Analog Input 3
Analog Input 2
Analog Input 1
Analog Input 0
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
179
180
181
182
183
184
185
186
187
188
VSS
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
3371427
3293469
3219507
3141549
3067587
2991789
2910159
2858121
2806083
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4570794
4748292
4748292
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
VSS
VDD
VSS
VDD
VEVRSB
VEVRSB
VSS
P33.0
SLOW / PU1 / 2683107
VEVRSB /
ES5
Data Sheet
359
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
189
P33.1
SLOW / PU1 / 2627109
4570794
General-purpose I/O
VEVRSB /
ES5
190
191
192
193
P33.2
P33.3
P33.4
P33.5
SLOW / PU1 / 2577105
VEVRSB /
ES5
4748292
4570794
4748292
4570794
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 2527101
VEVRSB /
ES5
SLOW / PU1 / 2477097
VEVRSB /
ES5
SLOW / PU1 / 2422107
VEVRSB /
ES5
194
195
196
VSS
Vx
Vx
2334015
2258217
4748292
4570794
4748292
Supply Voltage
VDD
P33.6
Supply Voltage
SLOW / PU1 / 2208519
General-purpose I/O
VEVRSB /
ES5
197
198
P33.8
P33.7
FAST / HighZ / 2158515
VEVRSB
4570794
4748292
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 2108511
VEVRSB /
ES5
199
200
201
VDD
Vx
Vx
2059173
2009475
4570794
4748292
4570794
Supply Voltage
VSS
Supply Voltage
P33.10
FAST / PU1 / 1954179
General-purpose I/O
VEVRSB /
ES5
202
203
204
P33.9
SLOW / PU1 / 1903185
VEVRSB /
ES5
4748292
4570794
4748292
General-purpose I/O
General-purpose I/O
General-purpose I/O
P33.11
P33.12
FAST / PU1 / 1853181
VEVRSB /
ES5
FAST / PU1 / 1803177
VEVRSB /
ES5
205
206
207
208
VDD
Vx
Vx
Vx
Vx
1752309
1684044
1584036
1484028
4570794
4748292
4748292
4748292
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
VSS
VEVRSB
VSS
Data Sheet
360
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
209
P33.13
FAST / PU1 / 1379034
4748292
General-purpose I/O
VEVRSB /
ES5
210
211
212
213
VSS
Vx
Vx
Vx
1278036
1178028
1078020
4748292
4748292
4748292
4748292
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
VEXT
P32.0
SLOW / PU1 / 978012
VEXT / ES
214
215
216
VGATE1N
P32.1
Vx
878004
4748292
4748292
4748292
DCDC N ch. MOSFET gate
driver output
SLOW / PU1 / 777996
VEXT / ES
General-purpose I/O
VGATE1P
Vx
677988
DCDC P ch. MOSFET gate
driver output
217
218
VSS
Vx
577980
4748292
4748292
Supply Voltage
P32.2
SLOW / PU1 / 477972
VEXT / ES
General-purpose I/O
219
220
221
222
P32.3
P32.4
P23.0
P23.1
SLOW / PU1 / 372978
VEXT / ES
4748292
4748292
4596759
4493763
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 269982
VEXT / ES
SLOW / PU1 / 185148
VEXT / ES
FAST / PU1 / 185148
VEXT / ES
223
224
VEXT
P23.3
Vx
362646
4441725
4364199
Supply Voltage
SLOW / PU1 / 185148
VEXT / ES
General-purpose I/O
225
226
227
228
229
230
231
P23.2
P23.5
P23.4
P22.0
P22.1
P22.2
P22.3
SLOW / PU1 / 362646
VEXT / ES
4312161
4260123
4208085
4156047
4104009
4048011
3995973
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 185148
VEXT / ES
FAST / PU1 / 362646
VEXT / ES
FAST / PU1 / 185148
VEXT / ES6
FAST / PU1 / 362646
VEXT / ES6
FAST / PU1 / 185148
VEXT / ES6
FAST / PU1 / 362646
VEXT / ES6
Data Sheet
361
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OPEN MARKET VERSION
TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
232
233
234
235
236
237
238
239
240
241
242
243
Pad Name
RESERVED
VEXT
VSS
Pad Type
Vx
X
Y
Comment
185148
362646
185148
362646
185148
362646
185148
362646
185148
362646
185148
3943935
3891897
3839859
3787821
3735783
3683745
3604815
3523887
3446955
3356172
3306762
3149613
Must be bonded to VSS
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Vx
Vx
VEXT
VSS
Vx
Vx
VDD
Vx
VSS
Vx
VDD
Vx
VSS
Vx
VDD
Vx
VSS
Vx
XTAL1
XTAL / VEXT 185148
XTAL pad1
XTAL1. Main
Oscillator/PLL/Clock
Generator Input.
244
XTAL2
XTAL / VEXT 185148
3050613
XTAL pad2
XTAL2. Main
Oscillator/PLL/Clock
Generator OUTPUT
245
246
247
248
249
VSS
Vx
Vx
Vx
Vx
185148
362646
362646
185148
2893464
2844054
2709414
2659374
2605338
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VEXT
VEXT
VSS
P21.0
FAST / PU1 / 362646
VEXT / ES
250
251
P21.1
P21.2
FAST / PU1 / 185148
VEXT / ES
2551338
2476287
General-purpose I/O
General-purpose I/O
LVDS_RX /
FAST / PU1 /
VEXT / ES
362646
362646
362646
362646
252
253
254
P21.3
P21.4
P21.5
LVDS_RX /
FAST / PU1 /
VEXT / ES
2377287
2247741
2148741
General-purpose I/O
General-purpose I/O
General-purpose I/O
LVDS_TX /
FAST / PU1 /
VEXT / ES6
LVDS_TX /
FAST / PU1 /
VEXT / ES6
Data Sheet
362
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TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
255
P21.6/TDI
FAST / PD /
PU2 / VEXT /
ES3
185148
2037240
General-purpose I/O
PD during Reset and in
DAP/DAPE or JTAG mode.
After Reset release and when
not in DAP/DAPE or JTAG
mode: PU. In Standby mode:
HighZ.
256
257
258
259
260
TMS
FAST / PD2 / 362646
VEXT
1987236
1937232
1887228
1837224
1787220
JTAG Module State Machine
Control Input
P21.7/TDO
TRST
TCK
FAST / PU2 / 185148
VEXT / ES4
General-purpose I/O
FAST / PU2 / 362646
VEXT
JTAG Module Reset/Enable
Input
FAST / PD2 / 185148
VEXT
JTAG Module Clock Input
P20.0
FAST / PU1 / 362646
VEXT / ES
General-purpose I/O
261
262
263
VSS
Vx
Vx
185148
362646
1737216
1685178
1635174
Supply Voltage
VEXT
P20.1
Supply Voltage
SLOW / PU1 / 185148
VEXT / ES
General-purpose I/O
264
P20.2
S / PU / VEXT 362646
1585170
General-purpose I/O
This pin is latched at power
on reset release to enter test
mode.
265
266
P20.3
ESR1
SLOW / PU1 / 185148
VEXT / ES
1535166
1485162
General-purpose I/O
FAST / PU1 / 362646
VEXT
ESR1 Port Pin input - can be
used to trigger a reset or an
NMI
ESR1: External System
Request Reset 1. Default NMI
function. See also SCU
chapter for details. Default
after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
267
PORST
PORST / PD / 185148
VEXT
1435158
PORST pin
Power On Reset Input.
Additional strong PD in case
of power fail.
Data Sheet
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TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
268
ESR0
FAST / OD /
VEXT
362646
1385154
ESR0 Port Pin input - can be
used to trigger a reset or an
NMI
ESR0: External System
Request Reset 0. Default
configuration during and after
reset is open-drain driver.
The driver drives low during
power-on reset. This is valid
additionally after deactivation
of PORST_N until the internal
reset phase has finished. See
also SCU chapter for details.
Default after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
269
270
271
272
273
274
275
VSS
VDD
VSS
VDD
VSS
VDD
P20.6
Vx
Vx
Vx
Vx
Vx
Vx
185148
362646
185148
362646
185148
362646
1312974
1240794
1168614
1096434
1024254
952074
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
SLOW / PU1 / 185148
VEXT / ES
900036
276
277
278
P20.7
P20.8
P20.9
FAST / PU1 / 362646
VEXT / ES
847998
797994
747990
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 185148
VEXT / ES
FAST / PU1 / 362646
VEXT / ES
279
280
VEXT
Vx
185148
697986
647982
Supply Voltage
P20.10
FAST / PU1 / 362646
VEXT / ES
General-purpose I/O
281
282
VSS
Vx
185148
597978
547974
Supply Voltage
P20.12
FAST / PU1 / 362646
VEXT / ES
General-purpose I/O
283
P20.11
FAST / PU1 / 185148
VEXT / ES
497970
General-purpose I/O
Data Sheet
364
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TC36x AA-Step
TC36x Pin Definition and Functions: Sequence of Pads in Pad Frame
Table 2-82 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
284
P20.13
FAST / PU1 / 185148
VEXT / ES
392976
General-purpose I/O
285
P20.14
FAST / PU1 / 185148
VEXT / ES
289980
General-purpose I/O
Whenever in table of section 3 ’Electrical Specification’ the term ‘neighbor pads’ is used, the detailed definition is
provided by Figure 2-82. This statement is also valid for next/nearest neighbor pads.
In order to find out who is affecting operation on a target pad (interfering) a number of active close-neighbor pads
(ACNP) has to be defined.
Finding close-neighbor pads.
The Pad Ring has four edges: bottom, left, top, right. Each edge is limited, i.e. it has two ends.
Each pad has two direct (first) neighbors unless it is located at the end of the edge. In that case it only has one
neighbor. Similarly, each pad has two indirect (second) neighbors unless it or its first neighbor is located at the
end of the edge. These first and second neighbors we will collectively call Close-Neighbor pads. Therefore each
pad has 2 to 4 close-neighbor pads.
Finding close-neighbors can be done with the following sequence:
1.) Choose a target pad and lookup its “X” and “Y” coordinates in table Figure 2-82.
2.) Find first and second neighbors by calculating “X” and “Y” distance from the selected pad. Figure 2-82 is sorted
by “Y” coordinate, which might help locate the 4 close-neighbor candidates (if the pad is near the edge, it might
end up with less than 4 close-neighbors).
Defining active pads:
Pad is active if it is currently in use and if it doesn’t have “Vxx” in the name.
Figuring out number of active close-neighbor pads follow next rules:
- If the first neighbor is active, then we count it and also check if second neighbor (on the same side of selected
pad) is active.
- If the first neighbor is not active, then we do not check the second on the same side.
Data Sheet
365
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TC36x AA-Step
TC36x Pin Definition and Functions: Legend
2.7
Legend
The data in this chapter 2 match with the file TC36xpd_IO_Spirit_v1.0.0.1.12.xml.
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field Selection PCx = 0XXXB)
O = Output (for GPIO port lines the ´O´ represents in most cases the port HWOUT function)
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Buffer Type”:
FAST = Pad class FAST (5V/3.3V)
RFAST = Pad class RFAST (5V/3.3V)
SLOW = Pad class SLOW (5V/3.3V)
LVDS_TX = Pad class LVDS Transmit
LVDS_RX = Pad class LVDS Receive
RGMII_Input = Pad implemented with controllable RGMII input buffer. Chapter -> ´General Purpose Ports and I/O´
S = Pad class S (Analog Input overlayed with General Purpose Input)
D = Pad class D (Analog Input)
Porst = Porst input Pad
XTAL1 = XTAL1 input Pad
XTAL2 = XTAL2 input Pad
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1)
PU2 = with pull-up device connected during reset and startup, HighZ in Standby mode
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1)
PD2 = with pull-down device connected during reset and startup, HighZ in Standby mode
OD = open drain during reset (PORST = 0)
ES = Supports Emergency Stop
ES1 = ES. ES can be overruled by VADC, control via P00_PCSR
ES2 = ES. ES can be overruled by DXCPL - DAP over CAN physical layer, No overruling for DXCM - Debug over
CAN message
ES3 = ES. ES can be overruled by JTAG mode if this pin is used as TDI
ES4 = ES. ES can be overruled by JTAG or Three Pin DAP mode
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG6 (P14.4). Pls. see also chapter
PMS, HWCFG[6].
Data Sheet
366
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TC36x AA-Step
TC36x Pin Definition and Functions: Legend
ES5 = ES. ES can be overruled by the Standby Controller - SCR - if implemented. Overruling can be disabled via
the control register P33_PCSR and P34_PCSR
ES6 = ES. On LVDS TX pads the ES affects the pads only in CMOS mode, not in LVDS mode. Thus, only when
LPCRx.TX_EN selects the CMOS Mode, the output is switched off in the ES event.
Data Sheet
367
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TC36x AA-Step
Electrical Specification Parameter Interpretation
3
Electrical Specification
3.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC36x and partly its requirements
on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with
an two-letter abbreviation in column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of the TC36x and must be
regarded for a system design.
•
SR
Such parameters indicate System Requirements which must be provided by the microcontroller system in
which the TC36x designed in.
Data Sheet
368
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TC36x AA-Step
Electrical Specification Absolute Maximum Ratings
3.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3-1 Absolute Maximum Ratings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
150
Storage Temperature
T
ST SR
-65
-
-
-
-
°C
V
upto 65h @ TJ = 150°C
upto 2.8h
Voltage at VDD power supply
pins with respect to VSS
V
DD SR
-
-
-
1.65
1.45
4.43
1) 2)
V
upto 72h
Voltage at VDDP3 power supply
pins with respect to VSS
V
DDP3 SR
V
Voltage at VDDM, VEXT, VFLEX and VDDM SR
EVRSB power supply pins with
respect to VSS
-
-
-
-
6.75
5.6
V
V
upto 2.8h
upto 72h
V
Voltage on all other input pins
with respect to VSS
VIN SR
-0.7
-0.7
-
-
6.75
6.75
V
V
3)
Voltage on all analog and class VIN SR
S input pins with respect to VSS
3)
Input current on any pin during IIN SR
overload condition
-10
-
-
10
mA
mA
4) 5)
Absolute maximum sum of all
input circuit currents during
overload condition. 4)
ΣIIN SR
-100
100
1) Valid for cumulated for up to 2.8h and pulse forms followed a power supply switch on phase, where the rise
and fall times are related to the system capacities and coils.
2) Due to EVRC output voltage oscillation during switch off phase VDD can drop down to -0.72V. For VDD an input level down to
-0.72V during switch off phase will not cause any damage or reliability problem.
3) Voltages below VINmin have no Impact to the device reliability as Long as the times and currents defined in section Pin Reliability
in Overload for the affected pad(s) are not violated.
4) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may
damage the device.
5) The specified min. and max. values represent the current limits, which have to be maintained, in case of a short circuit condition
on the output of any Fast, RFast, Slow and Class S pad, not being used during operation.
This covers also output currents due to switching in operation for CL=200pF.
Data Sheet
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TC36x AA-Step
Electrical Specification Pin Reliability in Overload
3.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience overload currents and
voltages that go beyond their own IO power supplies specification.
The following table defines overload conditions that will not cause any negative reliability impact if all the following
conditions are met:
•
allowed time interval (defined in Note column) for overload condition is not exceeded. If no time limit is defined
the allowed time includes both ‘Operation Lifetime hours’ and ‘Inactive Lifetime hours’. The number of hours
in Table 3-66 and Table 3-67 are examples only and the applicable numbers are defined by the customer
profiles accepted by Infineon.
•
Operating Conditions are met for
–
–
pad supply levels
temperature
If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters
functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still
possible in most cases but with relaxed parameters.
Table 3-2 Overload Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-5
-15 1)
Max.
5
15 1)
Input current on any digital pin IIN
during overload condition
-
-
mA
mA
except LVDS pins
except LVDS pins;
limited to max. 20
pulses with 1ms pulse
length
Input current on LVDS pin
during overload condition
IINLVDS
-3
-
3
mA
Input current on analog input pin IINANA
during overload condition
-3
-5
-
-
3
5
mA
mA
limited to 60h over
lifetime
Absolute sum of all analog input IINSA
currents for analog inputs during
overload condition
-20
-
-
20
mA
mA
Absolute maximum sum of all
input circuit currents during
overload condition (digital and
analog combined)
ΣIINS
-100
100
Signal voltage over/undershoot VOUS
at GPIOs
V
SS - 2
-
VEXT/FLEX
+ 2
V
limited to 60h over
lifetime; Valid for non
LVDS and analoge
pads
Sum of all inactive device pin
currents
IIDS
-100
-
-
-
100
2.5
5
mA
mA
mA
Static pin output current
I
OUT CC
-
-
100% duty cycle;
output driver = medium
100% duty cycle;
output driver = strong
Data Sheet
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TC36x AA-Step
Electrical Specification Pin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
digital inputs, negative
K
OVDN CC
-
-
3*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
fast pads; -5mA < IIN <
0mA
-
-
-
2*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
slow pads VGASTE1N
and VGATE1P; -5mA <
IIN < 0mA
-
1*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
slow pads; -5mA < IIN <
0mA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
0.5
Overload injected on
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for
digital inputs, positive
K
OVDP CC
1.5*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
GPIO non LVDS pads
1
Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
5*10-3
1*10-4
1*10-5
Overload injected on
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for
analog inputs, negative 2)
K
OVAN CC
Analog inputs overlaid
with slow pads or pull
down diagnostics; -
5mA < IIN < 0mA
else; -5mA < IIN < 0mA
Data Sheet
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TC36x AA-Step
Electrical Specification Pin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
analog inputs, positive 2)
K
OVAP CC
-
-
2*10-4
Analoge inputs overlaid
with slow pads or pull
down diagnostics; 0mA
< IIN < 5mA
-
-
2*10-5
else; 0mA < IIN < 5mA
1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters.
2) Overload coupling on analog inputs is caused by parasitic effects between pads, input multiplexers and surrounding structures.
The given parameters have been verified for all permutations of channels. Also watch multiple connections of a pin to several
channels.
Data Sheet
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TC36x AA-Step
Electrical Specification Operating Conditions
3.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the
TC36x. All parameters specified in the following tables refer to these operating conditions, unless otherwise
noticed.
Digital supply voltages applied to the TC36x must be static regulated voltages.
All parameters specified in the following tables refer to these operating conditions (see table below), unless
otherwise noticed in the Note / Test Condition column.
Table 3-3 Operating Conditions
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
300
300
300
100
300
100
200
100
-
SRI frequency
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SRI SR
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CPU Frequency (All CPUs)
PLL0 output frequency
SPB frequency
CPUx SR
PLL0 SR
SPB SR
FSI2 SR
FSI SR
-
-
20
-
-
-
FSI2 frequency
-
-
FSI frequency
20
-
-
GTM frequency
GTM SR
STM SR
ERAY SR
BBB SR
ADC SR
ASCLINx SR
CAN SR
I2C SR
-
STM frequency
-
-
ERAY frequency
BBB frequency
-
80
-
-
150
160
200
80
VADC frequency
ASCLIN Operating Frequency
CAN frequency
-
-
-
-
-
-
I2C frequency
-
-
100
200
320
Operating MSC Frequency
MSC SR
PLL1 SR
-
-
PLL1 output frequency from
PER PLL
20
-
PLL2 output frequency from
PER PLL
f
PLL2 SR
20
-
200
MHz
QSPI Frequency
f
f
f
QSPI SR
-
-
-
-
-
200
100
150
125
MHz
MHz
MHz
°C
MCANH frequency
GETH frequency
MCANH CC
GETH CC
-
100
-40
Ambient Temperature
TA SR
valid for all SAK
products
-40
-40
-
-
150
170
°C
°C
valid for all SAL
products with package
valid for all SAL
products without
package
Data Sheet
373
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TC36x AA-Step
Electrical Specification Operating Conditions
Table 3-3 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Junction Temperature
TJ SR
-40
-
150
°C
°C
valid for all SAK
products
-40
-
170
valid for all SAL
products
Core Supply Voltage
V
V
V
DD SR
1.125 1)
2.97
1.25
5.0
1.375 2)
5.5 3)
5.5 3)
V
V
V
ADC analog supply voltage
DDM SR
EXT SR
Digital external supply voltage
for pads and EVR
4.5
5.0
Nominal 5V Pad / Port
Pin supply range. 5V
pad parameters are
valid.
2.97
3.6
3.3
3.63
4.5
V
V
Nominal 3.3V Pad /
Port Pin supply range
with VDDP3 supplied
externally and EVR33
inactive. 3.3V pad
parameters are valid.
-
Flash configured in
cranking mode; Flash
read operation with
reduced performance.
EVR33 active in low
voltage mode. 3.3V pad
parameters are valid.
2.97
-
3.6
V
Incase EVR33 is active,
Flash configured in
sleep mode and
execution switched to
RAM. 3.3V pad
parameters are valid.
Digital supply voltage for Flex
port
V
V
FLEX SR
2.97
4.5
-
4.0
V
V
3.3V pad parameters
are valid
5.0
5.5 3)
5V pad parameters are
valid
Digital supply voltage for Flash
DDP3 SR
2.97
2.6
3.3
-
3.63 4)
3.63
V
V
Flash configured in
cranking mode; Flash
read operation with
reduced performance.
Digital ground voltage
V
V
SS SR
0
-
-
V
V
Analog ground voltage for VDDM
SSM CC
-0.1
0
0.1
Data Sheet
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TC36x AA-Step
Electrical Specification Operating Conditions
Table 3-3 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
EVRSB SR 2.97 5)
Max.
Digital external supply voltage
for EVR and during Standby
mode
V
V
-
5.5
V
Voltage to ensure defined pad
states
DDPPA CC 1.3 6)
-
-
V
1) For VDD 1.08V ≤ VDD < 1.125V operation is still possible but with relaxed parameters.
2) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
3) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
4) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
5) VEVRSB supply voltage can drop down upto 2.6V during Standby mode. It is required to have a capictor of 100nF on VEVRSB
supply pin.
6) HWCFG[6] pin is latched and pull-up or tristate is activated at Port pins when VEXT has reached this level.
Limitation of Supply Voltage over Time
The maximum operation voltage for VEXT/FLEX/DDM supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-4 Example Voltage Profile
VEXT/FLEX/DDM
=
Duration [h]
5.4 V < VEXT/FLEX/DDM ≤ 5.5 V
5.15 V < VEXT/FLEX/DDM ≤ 5.4 V
4.85 V < VEXT/FLEX/DDM ≤ 5.15 V
4.6 V < VEXT/FLEX/DDM ≤ 4.85 V
4.5 V < VEXT/FLEX/DDM ≤ 4.6 V
≤ 5% of lifetime
≤ 15% of lifetime
≤ 60% of lifetime
≤ 15% of lifetime
≤ 5% of lifetime
The maximum operation voltage for VDD supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-5 Example Voltage Profile
VDD=
Duration [h]
1.325 V < VDD ≤ 1.375 V
1.275 V < VDD ≤ 1.325 V
1.225 V < VDD ≤ 1.275 V
1.175 V < VDD ≤ 1.225 V
1.125 V < VDD ≤ 1.175V
≤ 5% of lifetime
≤ 15% of lifetime
≤ 60% of lifetime
≤ 15% of lifetime
≤ 5% of lifetime
Data Sheet
375
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
3.5
5 V / 3.3 V switchable Pads
Pad classes slow GPIO and fast GPIO support both Automotive Level (AL) or TTL level (TTL) operation.
Parameters are defined for AL operation and degrade in TTL operation.
Table 3-6 PORST Pad
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
PORST pad Output current
I
PORST CC
13
-
-
-
-
mA
ns
VEXT = 2.97V; VPORST =
0.9V
Spike filter always blocked pulse tSF1 CC
duration
-
80
-
Spike filter pass-through
blocked pulse duration
t
SF2 CC
260
ns
without additional
PORST Digtial Filter
active (PORSTDF = 0).
Input hysteresis 1)
HYS CC
0.055 *
VEXT
-
-
V
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
Pull-down current 2)
I
I
PDL CC
-
-
-
-
|130|
-
µA
µA
nA
VIH; TTL (degraded,
used for CIF)
|15|
-450
VIL; TTL (degraded,
used for CIF)
Input leakage current
OZ CC
450
TJ≤150°C ; (0.1 * VEXT
)
)
< VIN < (0.9 * VEXT
)
-500
-900
-
-
500
900
nA
nA
TJ≤150°C ;else
TJ≤170°C ; (0.1 * VEXT
< VIN < (0.9 * VEXT
)
-950
1.4
-
-
950
-
nA
V
TJ≤170°C ; else
Input high voltage level
Input low voltage level
Pin capacitance
VIH SR
VIL SR
CIO CC
TTL (degraded, used
for CIF); VEXT = 2.97V
2.0
-
-
-
-
V
V
TTL; VEXT = 4.5V
0.5
TTL (degraded, used
for CIF); VEXT = 2.97V
-
-
-
0.8
3
V
TTL; VEXT = 4.5V
2
pF
in addition 2.5pF from
package to be added
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
2) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Data Sheet
376
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-7 Fast 5V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL =
2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
3.2
CL = 25pF; driver =
strong sharp edge;
from 0.2 *
VEXT/FLEX/EVRSB to 0.8 *
VEXT/FLEX/EVRSB
4+0.55*CL 4+0.75*CL 12+1.0*CL ns
driver = medium;
CL≤200pF
1.0+0.18* 2.5+0.27* 5.0+0.35* ns
driver = strong edge =
CL
CL
CL
medium; CL≤200pF
0.5+0.08* 0.5+0.11* 1.0+0.17* ns
driver = strong edge =
CL
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.09 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/E
VRSB
0.075 *
VEXT/FLEX/E
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
VRSB
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
Pull-down current 5)
-
|130|
|30|
|28|
-
-
VIL; TTL
Data Sheet
377
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-7 Fast 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input leakage current
I
OZ CC
-1100
-
1100
nA
TJ ≤ 150°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-2500
-
2500
nA
TJ ≤ 150°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-6000
-3200
-
-
6000
3200
nA
nA
TJ ≤ 150°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 150°C ; LVDS_TX
/ Fast pad type ; else
-1500
-2000
-
-
1500
2000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-4000
-
4000
nA
TJ ≤ 170°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-13500
-5100
-2500
-
-
13500
5100
nA
nA
TJ ≤ 170°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 170°C ; LVDS_TX
/ Fast pad type ; else
-
-
2500
-
nA
V
TJ ≤ 170°C ; else
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 *
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
V
V
TTL
AL
-
0.44 *
VEXT/FLEX/E
VRSB
-
-
-
0.8
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
-50
50
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
constant; AL
=
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
Data Sheet
378
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-8 Fast 3.3V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL =
2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
4.5
CL = 25pF; driver =
strong sharp edge;
from 0.2 *
VEXT/FLEX/EVRSB to 0.8 *
VEXT/FLEX/EVRSB
-
-
5
ns
CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
2+0.57*CL 5.5+0.75* 10+1.25* ns
CL CL
1.5+0.18* 1.5+0.28* 8+0.4*CL ns
CL CL
driver = medium;
CL≤200pF
driver = strong edge =
medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns
driver = strong edge =
*CL
*CL
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.055 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/E
VRSB
0.09 *
VEXT/FLEX/E
-
-
-
-
V
V
non of the neighbor
pads are used as
output; TTL
VRSB
0.055 *
VEXT/FLEX/E
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
VRSB
125
-
-
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet
379
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-8 Fast 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull-up current 4)
I
PUH CC
|17|
-
-
µA
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
VIH; TTL
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF)
Pull-down current 5)
I
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
I
OZ CC
-1100
-2500
-
-
1100
2500
nA
nA
TJ ≤ 150°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
TJ ≤ 150°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-6000
-3200
-
-
6000
3200
nA
nA
TJ ≤ 150°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 150°C ; LVDS_TX
/ Fast pad type ; else
-1500
-2000
-
-
1500
2000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-4000
-
4000
nA
TJ ≤ 170°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-13500
-5100
-2500
-
-
-
13500
5100
2500
nA
nA
nA
TJ ≤ 170°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 170°C ; LVDS_TX
/ Fast pad type ; else
TJ ≤ 170°C ; else
Data Sheet
380
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-8 Fast 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage level
VIH SR
0.7 *
-
-
V
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
-
V
V
TTL
1.4
TTL (degraded, used
for CIF)
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VEXT/FLEX/E
VRSB
-
-
-
-
0.8
V
V
TTL
0.5
1.9
33
TTL (degraded, used
for CIF)
Input low/high voltage level
Input low threshold variation
V
V
ILH SR
ILD SR
1.0
-33
-
-
V
RGMII; no hysteresis
available
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-9 Slow 5V GPIO
Parameter
Symbol
Values
Typ.
225
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
Rise / Fall time 1) 2)
R
DSON CC
125
320
Ohm
medium driver; IOH / OL =
2mA
t
RF CC
4+0.55*CL 4+0.75*CL 12+1*CL ns
1.5+0.25* 2.5+0.40* 7+0.55*CL ns
driver = medium edge =
medium ; CL≤200pF
driver = medium edge =
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Data Sheet
fIN CC
-
-
160
MHz
381
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-9 Slow 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 3)
HYS CC
0.09 *
VEXT/FLEX/E
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
VRSB
0.075 *
VEXT/FLEX/E
-
-
V
non of the neighbor
pads are used as
output; TTL
VRSB
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
PUH CC
|30|
-
-
-
-
µA
µA
VIH;AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
|130|
VIL; AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
Pull-down current 5)
Input leakage current
I
I
PDL CC
-
-
-
-
-
|130|
µA
µA
µA
nA
VIH; AL or TTL
VIL; AL
|30|
|28|
-300
-
-
VIL; TTL
OZ CC
300
TJ ≤ 150°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-400
-600
-
-
400
600
nA
nA
TJ ≤ 150°C; else
TJ ≤ 170°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-750
-
-
750
nA
nA
TJ ≤ 170°C; else
-18000
18000
P32.0 and
P32.1;TJ≤150°C
-38000
-
-
38000
-
nA
V
P32.0 and
P32.1;TJ≤170°C
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 *
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
V
V
TTL
AL
-
0.44 *
VEXT/FLEX/E
VRSB
-
-
0.8
V
TTL
Data Sheet
382
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-9 Slow 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low threshold variation
V
ILD SR
-50
-
50
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-10 Slow 3.3V GPIO
Parameter
Symbol
Values
Typ.
225
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
Rise / Fall time 1) 2)
R
DSON CC
125
320
Ohm
medium driver; IOH / OL =
2mA
t
RF CC
2+0.57*CL 5.5+0.75* 10+1.25* ns
CL CL
driver = medium edge =
medium ; CL≤200pF
2+0.30*CL 3.5+0.50* 5+0.70*CL ns
driver = medium edge =
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.055 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/E
VRSB
0.09 *
VEXT/FLEX/E
-
-
-
-
V
V
non of the neighbor
pads are used as
output; TTL
VRSB
0.055 *
VEXT/FLEX/E
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
VRSB
125
-
-
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet
383
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-10 Slow 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull-up current 4)
I
PUH CC
|17|
-
-
µA
VIH; AL and TTL
(degraded, used for
CIF); exept VGATE1P;
except VGATE1N and
TJ > 150°C
|11|
-
-
-
-
µA
µA
VIH; TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF); exept
VGATE1P; except
VGATE1N and TJ >
150°C
Pull-down current 5)
I
I
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
OZ CC
-300
-
300
nA
TJ ≤ 150°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-400
-600
-
-
400
600
nA
nA
TJ ≤ 150°C; else
TJ ≤ 170°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-750
-
-
750
nA
nA
TJ ≤ 170°C; else
-18000
18000
P32.0 and
P32.1;TJ≤150°C
-38000
-
-
38000
-
nA
V
P32.0 and
P32.1;TJ≤170°C
Input high voltage level
VIH SR
0.7 *
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
-
V
V
TTL
1.4
TTL (degraded, used
for CIF)
Data Sheet
384
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-10 Slow 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VEXT/FLEX/E
VRSB
-
-
-
-
0.8
V
V
TTL
0.5
1.9
33
TTL (degraded, used
for CIF)
Input low/high voltage level
Input low threshold variation
V
V
ILH SR
ILD SR
1.0
-33
-
-
V
RGMII; no hysteresis
available
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-11 RFast 5V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL =
2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
3.2
CL = 25pF; driver =
strong sharp edge;
from 0.2 * VFLEX to 0.8 *
VFLEX
4+0.55*CL 4+0.75*CL 12+1.0*CL ns
driver = medium;
CL≤200pF
1.0+0.18* 2.5+0.27* 5.0+0.35* ns
driver = strong edge =
CL
CL
CL
medium; CL≤200pF
0.5+0.08* 0.5+0.11* 1.0+0.17* ns
driver = strong edge =
CL
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
Data Sheet
t
TX_ASYM CC -0.5
-
0.5
ns
valid for all data rates
excluding clock
tolerance
385
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TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-11 RFast 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
MHz
V
HYS CC
0.09 *
VFLEX
non of the neighbor
pads are used as
output; AL
0.075 *
VFLEX
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
nA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
|130|
-
Pull-down current 5)
-
|30|
|28|
-1700
-
VIL; TTL
Input leakage current
I
OZ CC
1700
TJ ≤ 150°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-2100
-3000
-
-
2100
3000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-4000
-
-
-
-
4000
nA
V
TJ ≤ 170°C ; else
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7*VFLEX
-
-
AL
2.0
-
V
TTL
AL
0.44 *
V
VFLEX
-
-
-
0.8
50
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-50
mV
max. variation of 1ms;
V
FLEX = constant; AL
-
-
2
-
3.5
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
Data Sheet
386
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TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-12 RFast 3.3V pad
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
8
20
30
Ohm
Ohm
Ohm
Driver = RGMII; IOH / OL
= 8mA
125
31
225
55
320
80
medium driver; IOH / OL =
2mA
strong driver; IOH / OL
=
8mA
Input Duty Cycle
Rise / Fall time 1) 2)
fD SR
tRF CC
47.5
1.6
50
-
52.5
4.5
ns
ns
ns
CL = 25pF; driver =
strong sharp edge;
from 0.2 * VFLEX to 0.8 *
VFLEX
-
-
-
-
5
1
CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
Driver = RGMII; from
20%V to 80%V;
CL=15pF
2+0.57*CL 5.5+0.75* 10+1.25* ns
CL CL
1.5+0.18* 1.5+0.28* 8+0.4*CL ns
CL CL
driver = medium;
CL≤200pF
driver = strong edge =
medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns
driver = strong edge =
*CL
*CL
CL
sharp ; CL≤200pF
Asymmetry of sending
Input frequency
t
TX_ASYM CC -0.4
-
0.4
ns
valid for all data rates
excluding clock
tolerance
fIN CC
-
-
160
MHz
Data Sheet
387
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TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-12 RFast 3.3V pad (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 3)
HYS CC
0.055 *
VFLEX
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
0.09 *
VFLEX
-
-
V
V
non of the neighbor
pads are used as
output; TTL
0.055 *
VFLEX
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
125
|17|
-
-
-
-
mV
µA
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
VIH; TTL
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF)
Pull-down current 5)
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
I
OZ CC
-1700
-
1700
nA
TJ ≤ 150°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-2100
-3000
-
-
2100
3000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-4000
0.7*VFLEX
2.0
-
-
-
-
4000
nA
V
TJ ≤ 170°C ; else
Input high voltage level
VIH SR
-
-
-
AL
V
TTL
1.4
V
TTL (degraded, used
for CIF)
Data Sheet
388
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TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-12 RFast 3.3V pad (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VFLEX
-
-
-
-
0.8
0.5
V
V
TTL
TTL (degraded, used
for CIF)
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-33
-
33
mV
pF
ns
max. variation of 1ms;
VFLEX = constant; AL
-
-
2
-
3.5
100
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-13 Class S 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input hysteresis 1)
fIN CC
-
-
-
MHz
V
HYS CC
0.09 *
VDDM
non of the neighbor
pads are used as
output; AL
0.075 *
VDDM
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 2)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
Pull-down current 3)
-
|130|
|30|
|28|
-
-
VIL; TTL
Data Sheet
389
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TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-13 Class S 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-150
-300
Max.
150
Input leakage current
I
OZ CC
-
-
nA
nA
TJ ≤ 150°C; else
300
TJ ≤ 150°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected
-300
-600
-
-
300
600
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 * VDDM
-
-
-
-
-
V
V
V
AL
2.0
-
TTL
AL
0.44 *
VDDM
-
-
-
0.8
50
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-50
mV
max. variation of 1ms;
V
DDM = constant; AL
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
3) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Data Sheet
390
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-14 Class D
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
150
300 1)
Input leakage current
I
OZ CC
-150
-300 1)
-
-
nA
nA
TJ ≤ 150°C; else
TJ ≤ 150°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected
-300
-600 2)
-
-
300
600 2)
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected
Pin capacitance
CIO CC
-
2
3
pF
in addition 2.5pF from
package to be added
1) For AN11, 100 nA need to be added.
2) For AN11, 200 nA need to be added .
Table 3-15 ADC Reference Pads
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Input leakage current for VAREF
I
OZ2 CC
-1
-
1
µA
µA
µA
TJ ≤ 150°C; VAREF <
VDDM; used for EVADC
-2
-
-
2
TJ ≤ 170°C; VAREF <
VDDM; used for EVADC
-3.5
3.5
TJ ≤ 150°C; VAREF
≤
VDDM+50mV; used for
EVADC
-7
-
-
-
-
-
7
µA
µA
µA
µA
µA
TJ ≤ 170°C; VAREF
≤
VDDM+50mV; used for
EVADC
-2
2
TJ ≤ 150°C; VAREF
<
<
≤
VDDM; used for
EDSADC
-4
4
TJ ≤ 170°C; VAREF
VDDM; used for
EDSADC
-6
6
TJ ≤ 150°C; VAREF
VDDM+50mV; used for
EDSADC
-12
12
TJ ≤ 170°C; VAREF ≤
VDDM+50mV; used for
EDSADC
Data Sheet
391
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TC36x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-16 Driver Mode Selection for Slow Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Driver Setting
X
X
X
X
0
1
Speed grade 1
Speed grade 2
medium sharp edge (sm)
medium medium edge (m)
Table 3-17 Driver Mode Selection for Fast Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Strong sharp edge (ss)
Strong medium edge (sm)
medium (m)
Reserved, do not use this combination
Table 3-18 Driver Mode Selection for RFast Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Strong sharp edge (ss)
Strong medium edge (sm)
medium (m)
RGMII function is active
Data Sheet
392
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification High performance LVDS Pads
3.6
High performance LVDS Pads
This LVDS pad type is used for the high speed chip to chip communication interface of the new TC36x. It compose
out of a LVDS pad and a fast pad.
CL = 2.5 pF for all LVDS parameters.
Table 3-19 LVDS - IEEE standard LVDS general purpose link (GPL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
0.75 1)
Output impedance
R0 CC
-
-
Ohm
ns
Vcm = 1.0 V and 1.4 V
Rise time (20% - 80%)
t
rise20 CC
ZL = 100 Ohm ±20%
@2pF external load
Output differential voltage 2)
V
OD CC
240
280
320
380
-
-
-
-
330
370
410
500
mV
mV
mV
mV
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=00
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=01
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=10
RT = 100 Ohm ± 1%;
LPCRx.VDIFFADJ=11;
Multi slave operation
Output voltage high
Output voltage low
V
V
V
OH CC
OL CC
OS CC
-
-
-
-
-
-
-
1475
1500
-
mV
mV
mV
mV
mV
mV
RT = 100 Ohm +/- 1%
VDIFFADJ=00 and 01
-
RT = 100 Ohm ± 1%
VDIFFADJ=10 and 11
925
900
1125
0
RT = 100 Ohm ± 1%
VDIFFADJ=00 and 01
-
RT = 100 Ohm +/- 1%
VDIFFADJ=10 and 11
Output offset (Common mode)
voltage
1275
1600
RT = 100 Ohm ± 1%
Input voltage range
VI SR
Driver ground potential
difference < 925 mV; RT
= 100 Ohm ±10%
0
-
-
-
-
2400
100
-
mV
Driver ground potential
difference < 925 mV; RT
= 100 Ohm ±20%
Input differential threshold
V
idth SR
-100
-100
80
mV
Driver ground potential
difference < 900 mV;
VDIFFADJ=10 and 11
mV
Driver ground potential
difference < 925 mV;
VDIFFADJ=00 and 01
Receiver differential input
impedance
Rin CC
120
Ohm
VI ≤ 2400 mV
Data Sheet
393
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification High performance LVDS Pads
Table 3-19 LVDS - IEEE standard LVDS general purpose link (GPL) (cont’d)
Parameter Symbol Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Output differential voltage Sleep VODSM CC
-5
-
20
mV
RT = 100 Ohm ± 20%;
LPCRx.VDIFFADJ=xx
Mode 3)
Delta output impedance
dR0 SR
-
-
-
-
10
25
%
Vcm = 1.0 V and 1.4 V
Change in VOS between 0 and dVOS CC
mV
RT = 100 Ohm ±1%
1
Change in Vod between 0 and 1 dVod CC
-
-
-
25
13
mV
µs
RT = 100 Ohm ±1%
Pad set-up time
tSET_LVDS
10
CC
Duty cycle
t
duty CC
45
-
55
%
1) trise20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load.
2) Potential violations of the IEEE Std 1596.3 are intended for the new multislave support feature. To be compliant to IEEE Std
1596.3 LPCRx.VDIFFADJ has to be configured to 01.
3) Common Mode voltage of Tx is maintained.
Note:Driver ground potential difference is defined as driver-receiver potentital difference, that can result in a
voltage shift when comparing driver output voltage level and receiver input voltage level of a transmitted
signal.
Note:RT in table ‘LVDS - IEEE standard LVDS general purpose Link (GPL)’ is as termination resistor of the
receiver according to figure 3-5 in IEEE Std 1596.3-1996 and is represent in Figure 3-1 either by Rin or by
RT=100Ohm but not both. If RT is mentioned in column Note / Test Condition always the internal resistor Rin
in Figure 3-1 is the selected one.
default after start-up = CMOS function
Data Sheet
394
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification High performance LVDS Pads
P
Htotal=5nH
Ctotal=3.5pF
LVDS
Cext=2pF
Rin
IN
RT=100Ohm
N
Htotal=5nH
Ctotal=3.5pF
Cext=2pF
LVDS_Input_Pad_Model.vsd
Figure 3-1 LVDS pad Input model
Data Sheet
395
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification VADC Parameters
3.7
VADC Parameters
The accuracy of the converter results depends on the reference voltage range. The parameters in the table below
are valid for a reference voltage range of (VAREF - VAGND) >= 4.5 V. If the reference voltage range is below 4.5 V
by a factor of k (e.g. 3.3 V), the accuracy parameters increase by a factor of 1.1/k (e.g. 1.1 × 4.5 / 3.3 = 1.5).
Noise on supply voltage VDDM influences the conversion. The accuracy (error) parameters are defined for a supply
voltage ripple of below 20 mVpp up to 10 MHz (below 5 mVpp above 10 MHz).
Digital functions overlapping analog inputs influence accuracy.
The total unadjusted error (TUE) is defined without noise. The overall deviation depends on TUE and ENRMS
(depending on the noise distribution). Example: For a noise distribution of 4 sigma and ENRMS = 1.0 the additional
peak-peak noise error is ±(4 × 1.0) = 8 LSB12.
Fast compare operations are executed with 10-bit values.
The noise reduction feature improves the result by adding additional conversion steps. The conversion times,
therefore, increase accordingly (4 × tADCI + 3 × tADC for each of 1, 3, or 7 steps).
Table 3-20 VADC 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
EVADC IVR output voltage
V
DDK CC
1.15
-
1.35
V
%
V
V
V
V
Measured at low
temperature.
Deviation of IVR output voltage dVDDK CC
VDDK
Analog reference voltage 1)
-2
-
2
Based on device-
specific value
V
AREF SR
4.5
5.0
3.3
VSSM
-
VDDM
0.05
+
+
4.5 V ≤ VDDM ≤ 5.5 V
2.97
VSSM
VAGND
VDDM
0.05
2.97 V ≤ VDDM < 4.5 V
Analog reference ground
Analog input voltage range
V
V
AGND SR
AIN SR
VSSM
V
SSM and VAGND are
connected together
AIN is limited by the
VAREF
V
respective pad supply
voltage; see pin
configuration (buffer
type)
Converter reference clock
Total Unadjusted Error 2) 3)
f
ADCI SR
16
16
-4
40
20
-
53.33
26.67
4
MHz
MHz
LSB
4.5 V ≤ VDDM ≤ 5.5 V
2.97 V ≤ VDDM < 4.5 V
TUE CC
12-bit resolution for
primary/secondary
groups, 10-bit
resolution for fast
compare channels
INL Error 2)
DNL error 2)4)
Gain Error 2)
Offset Error 2)3)
RMS Noise 2)5) 6)
EAINL CC
EADNL CC
-3
-1
-
3
LSB
LSB
LSB
LSB
LSB
LSB
-
3
EAGAIN CC -3.5
-
3.5
4
EAOFF CC
ENRMS CC
-4
-
-
0.5
0.5
0.8
1.0
Noise reduction level 3
Standard conversion
-
Data Sheet
396
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TC36x AA-Step
Electrical Specification VADC Parameters
Table 3-20 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Reference input charge
Q
CONV CC
-
-
20
pC
pC
V
AIN = 0 V (worst case),
precharging disabled
AIN = 0 V (worst case),
precharging enabled,
consumption per conversion
7) 8) 9)
(from VAREF
)
-
-
10
V
VDDM - 5% < VAREF <
VDDM + 50 mV
Switched capacitance of an
analog input
C
AINS CC
AINS CC
-
-
2.5
-
3.4
3.5
pF
pC
Input buffer disabled
Analog input charge
consumption 10)
Q
Primary groups and
fast compare channels;
VAIN = VAREF; VDDM = 5.0
V; input buffer enabled;
TJ ≤ 150°C
-
-
3.8
pC
Primary groups and
fast compare channels;
VAIN = VAREF; VDDM = 5.0
V; input buffer enabled;
TJ > 150°C
-
-
-
-
4.4
4.8
pC
pC
Secondarygroups;VAIN
= VAREF; VDDM = 5.0 V;
input buffer enabled; TJ
≤ 150 °C
Secondarygroups;VAIN
= VAREF; VDDM = 5.0 V;
input buffer enabled; TJ
> 150°C
Data Sheet
397
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification VADC Parameters
Table 3-20 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sampling time
tS SR
100
-
-
ns
Primary group or fast
compare channel, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer disabled
300
-
-
ns
Primary group or fast
compare channel, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer enabled
500
700
200
-
-
-
-
-
-
ns
ns
ns
Secondary group, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer disabled
Secondary group, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer enabled
Primary Group or fast
compare channel, 2.97
V ≤ VDDM < 4.5 V; input
buffer disabled
400
-
-
ns
Primary group or fast
compare channel, 2.97
V ≤ VDDM < 4.5 V; input
buffer enabled
1000
1200
-
-
-
-
ns
ns
Secondary group, 2.97
V ≤ VDDM < 4.5 V; input
buffer disabled
Secondary group, 2.97
V ≤ VDDM < 4.5 V; input
buffer enabled
Sampling time for calibration
t
SCAL SR
50
-
-
ns
ns
µs
µs
µs
4.5 V ≤ VDDM ≤ 5.5 V
2.97 V ≤ VDDM < 4.5 V
100
-
-
Input buffer switch-on time
Wakeup time
t
t
BUF CC
WU CC
-
-
-
-
0.4
0.1
1.6
100
1
0.2
3
-
Fast standby mode
Slow standby mode
Broken wire detection delay
against VAREF
t
t
BWR CC
cycles Result above 80% of
full scale range, analog
input buffer disabled
Broken wire detection delay
against VAGND
BWG CC
-
100
-
cycles Result below 10% of full
scale range, analog
input buffer disabled
Converter diagnostics unit
resistance 11)
R
CSD CC
45
-
-
75
10
kOhm
Converter diagnostics voltage
accuracy
dVCSD CC
-10
%
Percentage refers to
VDDM
Data Sheet
398
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TC36x AA-Step
Electrical Specification VADC Parameters
Table 3-20 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Resistance of the multiplexer
diagnostics pull-up device
R
MDU CC
30
-
-
-
-
-
42
kOhm 0 V ≤ VIN ≤ 0.9* VDDM
,
,
Automotive Levels
56
43
18
-
78
58
25
0.3
kOhm 0 V ≤ VIN ≤ 0.9* VDDM
TTL Levels
Resistance of the multiplexer
diagnostics pull-down device
R
MDD CC
kOhm 0.1*VDDM ≤ VIN ≤ VDDM
,
Automotive level
kOhm 0.1*VDDM ≤ VIN ≤ VDDM
,
TTL level
Resistance of the pull-down test RPDD CC
kOhm Measured at pad input
device
voltage VIN = VDDM / 2.
1) These limits apply to the standard reference input as well as to the alternate reference input.
2) Parameter depends on reference voltage range and supply ripple, see introduction.
Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
Tests are done with postcalibration disabled, after completing the startup calibration.
3) Analog inputs mapped to pads of the type SLOW influence accuracy. The values for this parameter increase by 3 LSB12.
4) Monotonic characteristic, no missing codes when calibrated.
5) Parameter ENRMS refers to a 1 sigma distribution.
6) Analog inputs mapped to pads of the type SLOW the RMS noise (ENRMS) can be up to 2 LSB 12 (soft switching for DC/DC
enabled).
7) For reduced reference voltages VAREF < 3.375V, the consumed charge QCONV is reduced by the factor of k2 = VAREF [V]
/ 3.375. For reduced reference voltages 4.5V < VAREF ≤ 3.375V, QCONV is not reduced.
8) Maximum charge increases by 15 pC when BWD (Broken Wire Detection) is active.
9) Fast compare channels only consume 1/3 of the charge for a primary/secondary group.
10) For analog inputs with overlaid digital GPIOs or with PDD function this value increases by 1 pC.
11) Use a sample time of at least 1.1 µs to enable proper settling of the test voltage.
Figure 3-2 Equivalent Circuitry for Analog Inputs
Data Sheet
399
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification DSADC Parameters
3.8
DSADC Parameters
The DSADC parameters are valid only for voltage range 4.5 V <= VDDM <= 5.5 V.
These parameters describe the product properties and do not include external circuitry. The values are valid for
junction temperatures TJ <= 150°C if not defined explicitly.
Calibration is specified for gain factors 1 and 2, calibrated values refer to these settings.
The signal-noise ratio (SNR) is specified for differential inputs. For single ended operation the resulting signal-
noise ratio is reduced by 6 dB. For quasi-differential mode (i.e. using VCM) it is reduced by 6 dB for gain = 1 and
by 3 dB for gain= 2.
Table 3-21 DSADC 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Common mode voltage bias
resistance
R
V
V
BIAS CC
AREF SR
AGND SR
105
130
155
kOhm On-chip variation ≤
±2.5%.
Positive reference voltage
Reference ground voltage
Reference load current
4.5
-
-
VDDM
0.05
+
V
VSSM
VSSM
V
VSSM and VAGND are
connected together
I
REF CC
-
-
10
-
12
14
µA
µA
Per modulator
Per modulator,
TJ>150°C
Common mode voltage
accuracy 1)
dVCM CC
DSIN SR
-100
-
-
100
mV
V
Deviation from selected
voltage
Analog input voltage range
V
VSSM
2 * VDDM
Differential;VDSxP -
VDSxN
VSSM
-
VDDM
V
Single ended
Input current 2)
I
RMS CC
7
10
13
µA
Exact value (±1%)
available in UCB; valid
for gain = 1 and fMOD
=
26.7 MHz
On-chip modulator clock
frequency
Gain error 3) 4)
f
MOD SR
16
-
40
MHz
%
EDGAIN CC -0.2 5)
±0.15)
0.2 5)
TJ≤150°C; Target,
calibrated, VAREF
constant after
calibration; fMOD
=
26.67 MHz
-
±0.25
-
%
TJ>150°C; VAREF
constant after
calibration; fMOD
=
26.67 MHz
-1
-
-
1
%
%
Calibrated once; fMOD =
26.67 MHz
-2.5
2.5
Uncalibrated; fMOD =
26.67 MHz
Data Sheet
400
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification DSADC Parameters
Table 3-21 DSADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DC offset error 3)
EDOFF CC -5 5)
-
-
-
-
-
-
-
5 5)
mV
mV
mV
dB
dB
dB
dB
Calibrated; fMOD =
26.67 MHz
-10
-30
10
30
-
Calibrated once; fMOD =
26.67 MHz
Uncalibrated; fMOD
26.67 MHz
=
Signal-Noise Ratio for
differential input signals 2)6) 7)
SNR CC
80
78
74
-
TJ≤150°C; fPB = 30 kHz;
MOD = 26.67 MHz
TJ≤150°C; fPB = 50 kHz;
MOD = 26.67 MHz
f
-
f
-
TJ≤150°C; fPB = 100
kHz; fMOD = 26.67 MHz
Signal-Noise Ratio degradation DSNR CC
Spurious-free dynamic range 3) SFDR CC
3
TJ>150°C; Resulting
Signal-Noise Ratio
value is SNR - DSNR
60
-
-
-
dB
fMOD = 26.67 MHz
Output sampling rate
fD CC
3.906
300
kHz
16 MHz / 4096, without
integrator
Pass band
f
PB CC
1.302
1.302
-
-
100
10
kHz
kHz
Output data rate: fD =
fPB * 3; without
integrator
Output data rate: fD =
fPB * 6; without
integrator
Pass band ripple
dfPB CC
SBA CC
-0.08
40
-
-
-
-
-
-
-
0.08
dB
dB
dB
dB
dB
dB
dB
FIR filters enabled
0.5 fD ... 1.0 fD
1.0 fD ... 1.5 fD
1.5 fD ... 2.0 fD
2.0 fD ... 2.5 fD
2.5 fD ... OSR/2 fD
10-5 fD, offset
compensation filter
enabled
Stop band attenuation
-
-
-
-
-
-
45
50
55
60
DC compensation factor
Modulator settling time
DCF CC
-3
(FCFGMx.OCEN =
001B)
t
MSET CC
-
-
20
µs
After switching on,
voltage regulator
already running
1) On pins with overlaid GPIO function the max. limit increases by up to 25 mV due to leakage current for TJ > 150°C.
2) For detailed information, refer to the User Manual chapter.
3) This parameter is valid within the defined range of fMOD
.
4) Gain mismatch error between the different EDSADC channels is within ±0.5% if they have the same calibration strategy
Data Sheet
401
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TC36x AA-Step
Electrical Specification DSADC Parameters
5) Recalibration needed in case of a temperature change >20ºC
6) These values are valid for an analog gain factor of 1. Subtract 3 dB for each higher gain factor.
7) For single ended input signals and gain1, the SNR is reduced by 6 dB.
Data Sheet
402
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TC36x AA-Step
Electrical Specification MHz Oscillator
3.9
MHz Oscillator
OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 16 MHz to 40 MHz crystals external
outside of the device. Support of ceramic resonators is also provided.
Table 3-22 OSC_XTAL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-70
4
Max.
70
Input current at XTAL1
Oscillator frequency
I
IX1 CC
-
-
µA
VIN>0V ; VIN<VEXT
f
OSC SR
40
MHz
Direct Input Mode
selected, if shaper is
not bypassed
16
-
-
-
-
40
MHz
ms
External Crystal Mode
selected
Oscillator start-up time
t
OSCS CC
-
3 1)
20MHz ≤ fOSC and 8pF
load capacitance
Input voltage at XTAL1 2)
VIX SR
PPX SR
-0.7
V
EXT + 0.5 V
EXT + 1.0 V
If shaper is not
bypassed
Input amplitude (peak to peak)
at XTAL1
V
0.3*VEXT
V
If shaper is not
bypassed; fOSC
25MHz
>
≤
0.35*VEXT
-
VEXT + 1.0 V
If shaper is not
bypassed; fOSC
25MHz
Internal load capacitor
Internal load capacitor
Internal load capacitor
Internal load capacitor
C
C
C
C
C
C
L0 CC
1.30
3.05
7.85
12.05
1.15
-
1.40
3.35
8.70
13.35
1.20
2.5
1.55
3.70
9.55
14.65
1.25
4
pF
pF
pF
pF
pF
pF
enabled via bit
OSCCON.CAP0EN
L1 CC
enabled via bit
OSCCON.CAP1EN
L2 CC
enabled via bit
OSCCON.CAP2EN
L3 CC
enabled via bit
OSCCON.CAP3EN
Internal load stray capacitor
between XTAL1 and XTAL2
XINTS CC
XTAL1 CC
Internal load stray capacitor
between XTAL1 and ground
Duty cycle at XTAL1 3)
Absolute RMS jitter at XTAL1 3)
Slew rate at XTAL1 3)
DCX1 SR
ABSX1 SR
35
-
-
-
-
65
28
-
%
VXTAL1 = 0.5*VPPX
J
ps
10 KHz to fOSC/2
SRXTAL1 SR 0.3
V/ns
Maximum 30%
difference between
rising and falling slew
rate
1) tOSCS is defined from the moment when the Oscillator Mode is set to External Crystal Mode until the oscillations reach an
amplitude at XTAL1 of 0.3 * VEXT.
This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.
2) For Supply (VEXT < 5.3V VIX) min could be down to -0.9V. For XTAL1 an input level down to -0.9V will not cause a damage or
a reliability problem operating with an external crystal.
Data Sheet
403
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification MHz Oscillator
3) Square wave input signal for XTAL1.
Note:It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
Data Sheet
404
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TC36x AA-Step
Electrical Specification Back-up Clock
3.10
Back-up Clock
The back-up clock provides an alternative clock source.
Table 3-23 Back-up Clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
BACKUT CC 70
Max.
Back-up clock accuracy before
trimming
f
f
f
100
100
70
130
MHz
MHz
kHz
VEXT≥2.97V
VEXT≥2.97V
VEXT≥2.97V
Back-up clock accuracy after
trimming 1)
BACKT CC
98
102
Standby clock
SB CC
25
110
1) A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for
temperature and voltage drifts up to temperatures of 125 celcius
Data Sheet
405
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Temperature Sensor
3.11
Temperature Sensor
Table 3-24 DTS PMS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Measurement time for each
conversion 1)
tM CC
-
-
2.7
ms
°C
Measured from cold
power-on reset release
Calibration reference accuracy
T
CALACC CC -1
-
1
calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature
range
T
T
NL CC
SR SR
-2
-
-
2
°C
°C
TCALACC has to be
added in addition
DTS temperature range
-40
170
1) After warm reset tM is not restarted and is measured from last conversion.
Table 3-25 DTS Core
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Measurement time for each
conversion 1)
tM CC
-
-
2.7
ms
°C
Measured from cold
power-on reset release
Temperature difference
between on chip temperature
sensors
ΔT CC
-3
-
3
2
Calibration reference accuracy
T
CALACC CC -2
-
°C
calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature
range
T
T
NL CC
SR SR
-2
-
-
2
°C
°C
T
CALACC has to be
added in addition
DTS temperature range
-40
170
1) After warm reset tM is not restarted and is measured from last conversion.
Data Sheet
406
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TC36x AA-Step
Electrical Specification Power Supply Current
3.12
Power Supply Current
The total power supply current defined below consists of leakage and switching component.
Application relevant values are typically lower than those given in the following table and depend on the customer's
system operating conditions (e.g. thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
The real (realistic) power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
SRI = fCPUx = 300 MHz
GTM = 200 MHz
SPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz
V
V
V
DD = 1.275 V
DDP3 / FLEX = 3.366 V
EXT / EVRSB = VDDM = 5.1 V
all cores are active including two lockstep cores at IPC = 0.6
the following peripherals are inactive: HSM, Ethernet, PSI5, I2C, FCE, and MTU
The max (maximum) power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
SRI = fCPUx = 300 MHz
GTM = 200 MHz
SPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz
V
V
V
DD = 1.375 V
DDP3 / FLEX = 3.63 V
EXT / EVRSB = VDDM = 5.5 V
all cores are active including two lockstep cores at IPC = 1.2
the following peripherals are inactive: GETH, FCE, and MTU
Table 3-26 Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
650
∑ Sum of IDD core and
peripheral supply currents (incl.
I
I
DDRAIL CC
-
-
-
-
mA
mA
max power pattern
real power pattern
500
I
I
DDPORST+ ∑ IDDCx0+ ∑ IDDCxx
DDGTM+IDDSB
DD core current during active
+
)
I
DDPORST CC -
-
-
-
95
mA
mA
mA
V
DD = 1.275V;
TJ=125°C
DD = 1.275V;
TJ=150°C
DD = 1.275V;
TJ=165°C
power-on reset (PORST pin
held low). Leakage current of
core domain. 1)
-
-
166
230
V
V
Data Sheet
407
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TC36x AA-Step
Electrical Specification Power Supply Current
Table 3-26 Current Consumption (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
DDP3RAIL CC -
Max.
∑ Sum of IDDP3 3.3 V supply
currents
I
-
45
mA
max power pattern incl.
Flash read current and
Dflash programming
current.
-
-
36 2)
mA
real power pattern incl.
Flash read current and
Dflash programming
current.
∑ Sum of external IEXT supply
currents (incl.
I
I
I
EXTRAIL CC
-
-
-
-
44
34
mA
mA
max power pattern
real power pattern
I
EXTFLEX+IEVRSB+IEXTLVDS)
I
EXT and IFLEX supply current
EXTFLEX CC -
-
18 3)
mA
real power pattern with
port activity absent;
PORST output inactive.
I
EVRSB supply current 1)
EVRSB CC
-
-
8.5
mA
real power pattern;
PMS/EVR module
current considered
without SCR and
Standby RAM during
RUN mode.
∑ Sum of external IDDM supply
currents (incl.
I
I
DDM CC
-
-
27
mA
real power pattern; sum
of currents of EDSADC
and EVADC modules
I
DDMEVADC+IDDMEDSADC
∑ Sum of all currents (incl.
EXTRAIL+IDDMRAIL+IDDx3RAIL+IDD)
∑ Sum of all currents with DC- IDDTOTDC3
)
DDTOT CC
-
-
-
-
597
380
mA
mA
real power pattern;
TJ=150°C
I
real power pattern;
EVRC reset settings
with 72% efficiency;
4)
DC EVRC regulator active
CC
VEXT = 3.3V
∑ Sum of all currents with DC- IDDTOTDC5
-
-
-
-
280
25
mA
mA
real power pattern;
EVRC reset settings
with 72% efficiency;
4)
DC EVRC regulator active
CC
VEXT = 5V
∑ Sum of all currents (SLEEP
mode) 1)
I
I
SLEEP CC
All CPUs in idle, All
peripherals in sleep,
fSRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C
∑ Sum of all currents
STANDBY CC -
-
130 6)
µA
32 kB Standby RAM
block active. SCR
inactive. Power to
(STANDBY mode) drawn at
V
EVRSB supply pin 5)
remaining domains
switched off. TJ = 25°C;
VEVRSB = 5V
Data Sheet
408
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Current
Table 3-26 Current Consumption (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
1495
1080
Maximum power dissipation 7)
PD SR
-
-
-
-
mW
mW
max power pattern
real power pattern
1) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
2) Realistic Pflash read pattern with 50% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common
decoupling capacitor of atleast 100nF for (VDDP3) is used. Continuous Dflash programming in burst mode with 3.3 V supply and
realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective
programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to 45 mA / 20
ns
which are handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply dimensioning
and not for thermal considerations.
3) The current consumption includes only minimal port activity.
4) The total current drawn from external regulator is estimated with 72% EVRC SMPS regulator efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and
IDDM.
5) The same current limits apply also for the other power pattern.
6) ∑ Sum of all currents during RUN mode at VEVRSB supply pin is less than (IEVRSB + 4 mA Standby RAM current + ISCRSB
if SCR active). ∑ It is recommended to have atleast 100 nF decoupling capacitor at this pin. 32kB of Standby SRAM
contributes less than 10uA to ISTANDBY current.
7) The values are only valid if all supplies are applied from external and do not contain the power losses of EVR33 and EVRC.
Table 3-27 Module Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DDP3 supply current for
IDDP3PROG
CC
-
-
-
-
-
25
mA
Pflash 3.3V
programming of a Pflash or
Dflash bank 1)
programming current
adder when using
external 3.3V supply.
-
9 2)
mA
mA
mA
Pflash 3.3V
programming current
adder when using
external 5V supply.
I
EXT supply current added by
I
EXTLVDS CC -
3
real power pattern; 2
pairs of LVDS pins
active with receive
function
LVDS pads in LVDS mode 1)
-
12
real power pattern; 3
pairs of LVDS pins
active with transmit
function
Data Sheet
409
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Current
Table 3-27 Module Current Consumption (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of external IDDM supply
currents (incl.
I
DDM CC
-
-
14
mA
real power pattern;
current for EDSADC
modules only and
EVADC modules are
inactive; 4 EDSADC
channels active
I
DDMEVADC+IDDMEDSADC)
continuously.
-
-
22 3)
mA
max power pattern;
current for EDSADC
modules only and
EVADC modules are
inactive; all EDSADC
channels active
continuously.
-
-
-
-
13
mA
mA
real power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; 6 EVADC
modules active.
15 4)
max power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; all EVADC
modules active.
I
DDP3 supply current for erasing IDDP3ERASE
-
-
-
-
25
mA
mA
Pflash 3.3V erasing
current adder when
using external 3.3V
supply.
of a Pflash or Dflash bank
CC
SCR 8-bit Standby Controller
current incl. PMS in STANDBY
Mode drawn at VEVRSB supply
pin
I
SCRSB CC
7.5
SCR power pattern incl.
PMS current
consumption with fback
clock active; fSYS_SCR
20MHz; TJ=150°C
=
-
-
0.150
-
mA
mA
SCR power pattern incl.
PMS current
consumption with fback
inactive; fSYS_SCR =
70kHz; TJ=25°C
SCR 8-bit Standby Controller
CPU in IDLE mode 5)
I
SCRIDLE CC
-
3.5
real power pattern.
CPU set into idle mode.
1) The same current limits apply also for the other power pattern.
2) During Pflash programming at 5V, additional 2 mA is drawn at VEXT supply rail.
3) A single DS channel instance consumes 4 mA.
Data Sheet
410
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
4) A single VADC unit consumes 1.3 mA.
5) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
Table 3-28 Module Core Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DD core current of CPUx main
I
I
DDCx0 CC
-
-
-
-
-
70
mA
mA
mA
mA
max power pattern;
IPC=1.2
core with CPUx lockstep core
inactive
-
-
-
45
real power pattern;
IPC=0.6
I
DD core current of CPUx main
DDCxx CC
IDDCx0
50
+
+
max power pattern;
IPC=1.2
core with CPUx lockstep core
active
IDDCx0
40
real power pattern;
IPC=0.6
I
DD core current added by GTM IDDGTM CC
-
-
-
-
90
75
mA
mA
max power pattern
real power pattern;
TIMx, TOMx, ATOMx ,
MCSx active. 2 clusters
at 200 MHz.
-
-
-
50
mA
mA
TIMx, TOMx active at
100MHz. ATOMx ,
MCSx, DPLL inactive. 2
clusters at 100 MHz.
I
I
DD core current added by HSM IDDHSM CC
DD core dynamic current added IDDLBIST CC
-
-
20 1)
max power pattern;
HSM running at
100MHz.
-
-
200 2)
200
mA
mA
LBIST Configuration A;
1.2V ≤ VDD
by LBIST
DD core dynamic current added IDDMBIST CC -
by MBIST
I
fMBIST = 300MHz;
tMBIST < 6ms. MTU
Ganging procedure for
SRAM test and
initialization; VDD =
1.375V.
1) The current consumption includes basic HSM activity incl. AES module.
2) LBIST is executed either during start-up phase or can be triggered by application software. Secondary voltage monitors are
inactive during the LBIST execution time (tLBIST).
During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static
accuracy.
If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit.
3.13
Power Supply Infrastructure and Supply Start-up
Data Sheet
411
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1
Supply Ramp-up and Ramp-down Behavior
Start-up slew rates for supply rails shall comply to SR (see Table 3-32 Supply Ramp).
3.13.1.1 Single Supply mode (a)
VEXT (externally supplied)
0
1
2
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDD
(internally generated
by EVRC)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
EVRC_tSTR
0 V
VDDP3
(internally generated
by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVR33_tSTR
0 V
tBP (incl. tEVRstartup)
T3
T0
T1
T2
T4
User Code Execution
fCPU0=100MHz default
T5
EVRC & EVR33 Ramp-up
Phase
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_2 v 0.3
on firmware exit
Figure 3-3 Single Supply mode (a) - VEXT (5 V) single supply
Data Sheet
412
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal
regulators.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited during the basic
infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling
time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the
maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the
specification.
•
Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware
start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-3 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after
LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal
pre-regulator VDDPD voltage has reached VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated.
PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate
the respective voltages though PORST is asserted and the device is in reset state. The generated voltage
follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up.
PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU.
Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet
parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
413
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.2 Single Supply mode (e)
0
1
2
3
4
5
VEXT/VDDP3
(externally supplied)
LVD Reset release
HWCFG[1,2] latch
3.63 V
3.30 V
VRST5/
VRST33 Primary cold PORST Reset Threshold
VLVDRST5
LVD Reset Threshold
VDDPPA
HWCFG[6] latch
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDD (internally generated
by EVRC)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVRC is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVRC_tSTR
0 V
tBP (incl. tEVRstartup)
T3
T0
T2
T4
User Code Execution
fCPU0=100MHz default
on firmware exit
T5
T1
EVRC Ramp-up
Phase
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_4 v 0.3
Figure 3-4 Single Supply mode (e) - (VEXT & VDDP3) 3.3 V single supply
VEXT = VDDP3 = 3.3 V single supply mode. VDD is generated internally by the EVRC regulator.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet
parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual
waveform may not represent the specification.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA
(dIDD) is expected.
Data Sheet
414
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
•
The power sequence as shown in Figure 3-4 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after
LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal
pre-regulator VDDPD voltage has reached VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVRC regulator is initiated. PORST (input)
does not have any affect on EVRC output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC regulator has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
415
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.3 External Supply mode (d)
VEXT (externally supplied)
0
1
2
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDDP3 (internally generated
by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVR33_tSTR
0 V
tBP (incl. tEVRstartup)
T1
T0
T3
T2
T4
User Code Execution
fCPU0=100MHz default
on firmware exit
T5
Basic Supply & Clock
Infrastructure
EVR33 Ramp-up Phase
Firmware Execution
Power Ramp-down phase
Startup_Diag_1 v 0.3
Figure 3-5 External Supply mode (d) - VEXT and VDD externally supplied
VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator.
•
External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is
defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. In case VDD
Data Sheet
416
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
voltage rail is ramped up before VEXT; VDD supply overshoots during start-up shall be limited within the
operational voltage range.
•
The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds. The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-5 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after
LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal
pre-regulator VDDPD voltage has reached VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVR33 regulator is initiated. PORST (input)
does not have any affect on EVR33 output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVR33 regulators has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
417
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.4 External Supply mode (h)
VEXT (externally supplied)
0
1
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
VDDP3
(externally supplied)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
tPOA time to ensure adequate time between reset releases
PORST (input driven by external regulator)
PORST (output driven by PMS)
tBP
T3
T0
T1
T4
T5
User Code Execution
fCPU0=100MHz default
on firmware exit
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_3 v 0.4
Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied
All supplies, namely VEXT, VDDP3 & VDD are externally supplied.
•
External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards to
start, rise and fall time(s). Start-up slew rates for supply rails shall comply to (datasheet parameter) SR. The
slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails. In
case smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall
be limited within the operational voltage ranges of the respective rails.
Data Sheet
418
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
•
The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-6 is enumerated below
–
T1 up to T3 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. These events are initiated after
LVD reset release at T1 after VEXT ad VEVRSB supply rails have reached VLVDRST5 level and internal
pre-regulator VDDPD voltage has reached VLVDRSTC level.
–
–
–
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. PORST (output) is de-asserted and HWCFG[3:5] pins are
latched on PORST rising edge by SCU. Firmware execution is initiated.
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided
supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds.
Data Sheet
419
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Reset Timing
3.14
Reset Timing
Table 3-29 Reset
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Application Reset Boot Time
System Reset Boot Time
tB CC
-
-
400
µs
operating with max.
frequencies, with valid
BMI header
t
BS CC
-
-
-
1.1
3.1
ms
ms
RAM initialization and
HSM boot time are not
included, with valid BMI
header
Cold Power on Reset Boot Time tBP CC
-
dVEXT/dT=1V/ms.
VEXT>VLVDRST5.
Boot time after Cold
PORST including EVR
ramp-up and Firmware
execution time; RAM
initialization and HSM
boot time are not
1)
included.
-
-
-
1.6
ms
Firmware execution
time after PORST
release without EVR
ramp-up; RAM
initialization and HSM
boot time is not
included
Minimum cold PORST reset
hold time in case of power fail
event issued by EVR primary
monitors
t
EVRPOR CC 10 2)
-
µs
PMS Infrastructure, EVRC and tEVRstartup
EVR33 overall start-up time till CC
cold PORST reset release
-
-
-
1
-
ms
ms
dV/dT=1V/ms. EVRC
and EVR33 active
Minimum PORST active hold
time externally after power
supplies are stable at operating
levels after start-up
t
POA SR
1 3)
Configurable PORST digital
filter delay in addition to analog
pad filter delay
t
PORSTDF CC 600
-
1200
ns
Warm Reset Sequencing Delay tWARMRSTSEQ
-
-
-
180
-
µs
ns
CC
HWCFG pins hold time from
ESR0 rising edge
t
HDH CC
16 / fSPB
Data Sheet
420
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Reset Timing
Table 3-29 Reset (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
HWCFG pins setup time to
ESR0 rising edge
t
HDS CC
0
-
-
-
-
-
-
-
-
ns
s
Ports inactive after ESR0 reset tPI CC
active
8000/fBAC
18000/fBA
KT
CKT
Ports inactive after PORST
reset active
t
t
t
t
PIP CC
POH SR
POS SR
BWP CC
-
160
ns
ns
ns
ms
ms
Hold time from PORST rising
edge
150
-
Setup time to PORST rising
edge
0
-
-
Warm PORST reset boot time
1.5
6
without RAM
initalization
LBIST execution time extending tLBIST CC
-
LBIST Configuration A;
the boot time
1.2V ≤ VDD
SCR reset boot time
t
SCR CC
-
-
-
-
5
µs
µs
µs
User Mode 0
User Mode 1
-
16
-
13.3
WDT double bit ECC,
soft reset
Minimum external supplies hold tSUPHOLD CC -
-
250
µs
external supplies are
time after warm reset assertion
VEVRSB, VEXT, VFLEX
,
VDDM, VDDP3 and VDD
1) RAM initialization add 500µs in addition.
2) Cold PORST reset is driven by uC and maintained in an extended voltage range between VDDPPA limit and absolute
maximum rating voltage limits.
3) The reset release on supply ramp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above
the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple consecutive
cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released.
Data Sheet
421
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Reset Timing
VDDPPA
VDDPPA
VDDP
VDD
VDDPR
t
POA
t
POA
Warm
PORST
ESR0
Cold
t PI
Programmed
tPI
tPIP
Tristate Z / pullup H
Programmed
Z / H
Z / H
Programmed
Pads
Pad-
state
undefined
Pad-
state
undefined
tPOS
tPOS
tPOH
tPOH
TRST
TESTMODE
tHDH
tHDH
config
tHDA
tHDH
config
tHDA
HWCFG
power -on config
reset_beh_aurix
Figure 3-7 Power, Pad and Reset Timing
Data Sheet
422
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
3.15
EVR
Table 3-30 EVR33 LDO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
5.50
5.50
Input voltage range
VIN SR
3.60 1)
2.97 2)
-
-
V
V
Normal RUN mode
Low voltage cranking
mode
Output voltage operational
range including load/line
regulation and aging 3)
V
V
OUT CC
2.97
2.60
3.3
3.3
3.63
3.63
V
V
Normal RUN mode
Low voltage cranking
mode; IDDP3=50mA
Output VDDx3 static voltage
accuracy after trimming and
aging without dynamic load/line
regulation.
OUTT CC
3.225
2.78
3.3
3.3
3.375
3.375
V
V
Normal RUN mode
Low voltage cranking
mode; IDDP3=50mA
Output buffer capacitance on
VOUT
C
C
OUT SR
1.45
2.2
3
µF
Output buffer capacitor ESR
OUTESR SR -
60 5)
-
-
100 4)
-
mOhm f > 0.5MHz; f < 10MHz
Maximum output current of the
regulator
I
MAX CC
mA
Normal RUN mode
Startup time
External VIN supply ramp 6)
t
STR CC
-
500
1000
-
µs
Normal RUN mode
dVin/dt SR -
ΔVOUTTC CC -
1
-
V/ms
mV
Ripple on Output Voltage
33
V
EXT ≥ 2.97V ; VEXT
5.5V ; IOUTTC ≥ 10mA ;
OUTTC ≤ 60mA;
≤
I
ΔVOUTTC = (peak to
peak ripple / 2)
Load step response 7)
dVout/dIout -165
CC
-
-
-
-
-
mV
mV
mV
mV
Normal RUN mode;
dI=10 to 60mA;
dt=20ns; Tsettle=20us
-
165
-
Normal RUN mode;
dI=60 to 10mA;
dt=20ns; Tsettle=20us
-180
-
Low voltage cranking
mode; dI=10 to 50 mA;
dt=20ns; Tsettle=20us
180
Low voltage cranking
mode; dI=50 to 10mA;
dt=20ns; Tsettle=20us
Data Sheet
423
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
Table 3-30 EVR33 LDO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Line step response
dVout/dVin
CC
-
-
-
-
-
40
mV
mV
mV
mV
dVin/dT=1V/ms; dV=
3.6 to 5V; IMAX=60mA
-40
-
-
dVin/dT=1V/ms; dV= 5
to 3.6V; IMAX=60mA
280
-
dVin/dT=50V/ms; dV=
3.6 to 5V; IMAX=60mA
-165
dVin/dT=50V/ms; dV=
5 to 3.6V; IMAX=60mA
1) A maximum pass device dropout voltage of 300mV is included in the minimum input voltage to ensure optimal pass device
performance during normal operation.
2) VEXT Input voltage drop up to 2.97V leading to VDDP3 output voltage drop upto 2.6V can be tolerated if Flash is switched
before to low performance mode.
3) No external inductive load permissible if EVR33 is used.
4) It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
An additional decoupling capacitor of 100nF shall be located close to the pin before Cout.
5) IMAX is limited to 40 mA incase of Low voltage mode (cranking case) with on chip pass devices. In case EVR33 is not used,
Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during power
sequencing 3.3V is supplied before 5V by external regulator.
6) EVR is robust against residual voltage ramp-up starting between 0 - 2.97 V. A VEXT voltage ramp range between 0.5V/min
upto 120V/ms is covered in robustness validation. The generated voltage itself follows a soft ramp-up over the tSTR time to
avoid overshoots.
7) Settling time is defined until output voltage is within +-1% of the mean(VOUTT) of the individual device.
Table 3-31 Supply Monitors
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Primary Undervoltage Reset
threshold for VDDP3 before
trimming 1)
V
V
RST33 CC
-
-
3.00
V
by reset release before
EVR trimming on
supply ramp-up
Primary undervoltage reset
threshold for VDD before
trimming
RSTC CC
-
-
1.138
V
by reset release before
trimming on supply
ramp-up including 2
LSB voltage Hysteresis
V
EXT primary undervoltage
VEXTPRIUV
2.86
2.92
2.90
1.105
2.97
2.97
1.125
V
V
V
VEXT = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after trimming CC
2)
VDDP3 primary undervoltage
VDDP3PRIUV 2.86 3)
VDDP3 = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after trimming CC
2)
VDD primary undervoltage
V
DDPRIUV CC 1.08 3)
VDD = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after trimming
2)
Data Sheet
424
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
Table 3-31 Supply Monitors (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
EVR primary monitor
measurement latency for a new
supply value
t
PRIUV CC
-
-
300
ns
The supply ramp / line
jump slope is limited to
50V/ms for VEXT, VDDP3
and VDD rails.
Data Sheet
425
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
Table 3-31 Supply Monitors (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
EXT, VDDM & VEVRSB secondary VEXTMON CC 3.2
3.3
3.3
4.6
4.6
5.4
5.4
5.0
3.4
V
SWDxxVAL,
supply monitor accuracy after
trimming 4) 5)
VDDMxxVAL &
SBxxVAL monitoring
threshold=3.3V=90h(O
V,UV). For BGA
packages:
EVRMONFILT.SWDFI
L=1.
3.2
4.5
4.5
5.3
5.3
4.9
3.4
4.7
4.7
5.5
5.5
5.1
V
V
V
V
V
V
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=3.3V=90h(O
V,UV). For QFP
packages:
EVRMONFILT.SWDFI
L=2
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=4.6V=C8h(U
V)/C9h(OV). For BGA
packages:
EVRMONFILT.SWDFI
L=1
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=4.6V=C8h(U
V)/C9h(OV). For QFP
packages:
EVRMONFILT.SWDFI
L=2
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5.4V=EAh(U
V)/ECh(OV). For BGA
packages:
EVRMONFILT.SWDFI
L=1
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5.4V=EAh(U
V)/ECh(OV). For QFP
packages:
EVRMONFILT.SWDFI
L=2
Data Sheet
426
V 1.1, 2021-03
SWDx
OPEN MARKET VERSION
VDDMxxVAL &
TC36x AA-Step
Electrical Specification EVR
Table 3-31 Supply Monitors (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
DDP3 secondary supply monitor VDDP3MON
2.97
3.035
3.30
3.565
1.15
1.25
1.35
3.1
V
EVR33xxVAL
monitoring
threshold=3.035V=CBh
(UV)/CCh(OV).
EVRMONFILT.EVR33
FIL = 3.
accuracy after trimming 5)
CC
3.235
3.365
3.63
V
V
V
V
V
EVR33xxVAL
monitoring
threshold=3.3V=DDh(
OV,UV).
EVRMONFILT.EVR33
FIL = 3.
3.5
EVR33xxVAL
monitoring
threshold=3.565V=EEh
(UV)/EFh(OV).
EVRMONFILT.EVR33
FIL = 3.
VDD & VDDPD secondary supply
V
DDMON CC 1.125
1.175
1.275
1.375
EVRCxxVAL &
monitor accuracy after trimming
PRExxVAL monitoring
threshold=1.15V=C7h(
UV)/C8h(OV).
EVRMONFILT.EVRCFI
L = 1.
5)
1.225
EVRCxxVAL &
PRExxVAL monitoring
threshold=1.25V=D9h(
OV,UV).
EVRMONFILT.EVRCFI
L = 1.
1.325
EVRCxxVAL &
PRExxVAL monitoring
threshold=1.35V=EAh(
UV)/EBh(OV).
EVRMONFILT.EVRCFI
L = 1.
V
EXT LVD Primary undervoltage VLVDRST5 CC 2.3
-
-
-
-
2.72
2.75
2.47
2.5
V
V
V
V
Power-down
Power-up
reset Monitor threshold
2.4
VEVRSB LVD Primary
VLVDRSTSB
CC
2.18
2.21
Power-down
Power-up
undervoltage reset Monitor
threshold
VEXT and VEVRSB PBIST primary VPBIST5 CC 5.63
-
-
V
overvoltage Monitor threshold
Data Sheet
427
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
Table 3-31 Supply Monitors (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Primary undervoltage reset
threshold for VEXT before
trimming
V
RST5 CC
-
-
3.0
V
by last cold PORST
release on supply
ramp-up including
voltage hysteresis.
EVR secondary monitor
measurement latency for all 6
supply rails
t
MON CC
-
-
3.2
µs
HPOSC and SHPBG
bandgap trimmed.
Filter inactive.
1) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold and
by a voltage hysteresis of 1.5% above the undervoltage reset limit. These mechanisms serve as hysteresis to avoid multiple
consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. The
reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply is provided
externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin.
2) The monitor tolerances constitute the inherent variation of the band gap and ADC over process, voltage and temperature
operational ranges. The VxxPRIUV parameters are device individually tested in production with +-1% tolerance about the
VxxPRIUV limits. All voltages are measured on pins.
3) VRSTxx parameters are relevant only for the first cold PORST release. Later the reset levels are trimmed by the Firmware and
reflected as VxxPRIUV parameters before device is used with full performance. The cold PORST is released with a voltage
hysteresis on all the primary monitors to avoid consecutive PORST toggling behavior.
4) In case the application is using 3.3V single supply (Single Supply mode (e), i.e. VEXT and VDDP3 are shorted together), it is
recommended to use secondary supply monitoring on channel VDDP3, because of the better accuracy of parameter
VDDP3MON.
5) To monitor voltage level not provided in conditions the values for OV and UV thresholds can be generated by a linear
interpolation or extrapolation based on the given points.
Table 3-32 Supply Ramp
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
External VEXT & VEVRSB supply dVEXT/dt
8.3E-6
1
100
V/ms
ramp-up and ramp-down slope SR
1) 2) 3)
External VDDP3 supply ramp-up dVDDP3/dt 8.3E-6
1
1
1
100
100
100
V/ms
V/ms
V/ms
and ramp-down slope 1)3)
SR
External VDD supply ramp-up
dVDD/dt
SR
8.3E-6
and ramp-down slope 1)3)
External VDDM supply ramp-up dVDDM/dt 8.3E-6
and ramp-down slope 1)3)
SR
1) The device is robust against residual voltage ramp-up starting between 0 - 2.97 V for VEXT, VEVRSB, VDDP3 and VDDM
and 0-1 V for VDD. A voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation.
2) Also valid in case EVR33 or EVRC is used. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid
overshoots.
3) The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent
the specification.
Up to 1,000,000 power cycles, matching the limits defined in table ‘Supply Ramp’, are allowed for TC36x without
any restriction to reliability.
Data Sheet
428
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
Table 3-33 EVRC SMPS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input VEXT Voltage range
VIN SR
2.97
-
5.5
V
V
Start-up VEXT voltage
> 2.6 V
SMPS regulator output voltage
range including load/line
regulation and aging
V
DDDC CC
1.125
-
1.375
1.275
2.0
V
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 1mA ;
DDDC ≤ 500mA ;
untrimmed
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 1mA ;
DDDC ≤ 500mA
≤
I
SMPS regulator static voltage
output accuracy after trimming
without dynamic load/line
regulation.
V
DDDCT CC 1.225
1.25
1.82
V
V
≤
I
Programmable switching
frequency
f
DCDC SR
1.6
MHz
Start-up frequency
switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation.
-
0.8
-
MHz
Start-up frequency
switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation. 0.8
MHz to be set in SW.
Startup time
t
STRDC CC
-
-
900
µs
SMPS Start-up Mode. It
is is defined beween
VEXTPRIUV reset
threshold till PORST
release, on condition
that all other PORST
requirements were
released before. ISTART
< 350mA.
Switching frequency modulation ΔfDCSPR CC -
spread
1.8%
-
-
MHz
mV
Maximum ripple at IMAX
ΔVDDDC CC
-
16
V
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 300mA ;
DDDC ≤ 500mA ;
≤
I
ΔVDDDC = (Peak to
Peak ripple / 2)
No load current consumption of IDCNL CC
SMPS regulator
-
-
15
5
19
-
mA
mA
f
I
DCDC=1.82MHz;
DDDC=ISLEEP; VEXT
>
>
2.97 V; TJ=25°C
LPM mode;
IDDDC=ISLEEP; VEXT
2.97 V; TJ=25°C
Data Sheet
429
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
Table 3-33 EVRC SMPS (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SMPS regulator load transient dVDDDCT
/
-50
-
75
mV
dI < -250mA ;
response
dlOUT CC
I
DDDC=280-500mA;
tr=0.1us; tf=0.1us;
DDDC=1.25V;
settle=100 us
V
T
-26
-
26
mV
dI < 100mA ; IDDDC=50-
500mA; tr=0.1us;
tf=0.1us; VDDDC=1.25V;
Tsettle=20us;
Maximum output current
I
MAX CC
100
500
-75
-12.5
-
-
-
mA
mA
mV
mV
%
LPM mode. Typical
current in LPM Mode =
ISLEEP
-
-
limited by thermal
constraints and
component choice
SMPS regulator line transient
response
dVDDDCT
dVIN CC
/
-
75
dV/dT=120V/ms; dV <
2.97 - 5.5V ; IDDDC=50-
500mA;
-
12.5
dV/dT=1V/ms; dV <
2.97 - 5.5V ; IDDDC=50-
500mA;
SMPS regulator efficiency
n
DC CC
80
75
-
-
VIN=3.3V;
I
f
DDDC=500mA;
DCDC=1.82MHz
VIN=5V; IDDDC=500mA;
-
%
fDCDC=1.82MHz
fDCDC =1.82MHz
fDCDC=0.8MHz
InputSynchronisationfrequency fDCDCSYNC
1.6
1.82
0.8
2.0
MHz
MHz
SR
0.66
0.94
Table 3-34 EVRC SMPS External components
Parameter Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
External output capacitor value COUT SR
13
20
27
µF
I
DDDC=500 mA; fDDDC
0.8MHz
DDDC=500mA; fDDDC
1.82MHz
mOhm f≥0.5MHz ; f≤10MHz
=
1)
9.6
14.7
19.8
µF
I
=
External output capacitor ESR COUT_ESR
-
-
50
SR
-
-
100
9.18
50
Ohm
µF
f=10Hz
IDDDC=500mA
External input capacitor value 1) CIN SR
4.42
6.8
External input capacitor ESR
C
IN_ESR SR
-
-
-
-
mOhm f≥0.5MHz ; f≤10MHz
Ohm f=100Hz
100
Data Sheet
430
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification EVR
Table 3-34 EVRC SMPS External components (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
3.29
2.31
Max.
6.11
4.29
0.2
External inductor value
L
L
DC SR
4.7
3.3
-
fDCDC=0.8MHz
DCDC=1.82MHz
µH
Ohm
V
f
External inductor DCR
DC_DCR SR -
LL SR
P + N-channel MOSFET logic
level
V
-
-
2.5
P + N-channel MOSFET drain |VBR_DS| SR +7
-
-
V
V
NMOS - VGS = 0.
PMOS - VGS = 0.
source breakdown voltage
-
-
-7
-
P + N-channel MOSFET drain
source ON-state resistance
R
ON SR
-
-
200
mOhm IDDDC=500mA;
|VGS|=2.5V ; TA=25°C
DDDC=500mA; NMOS-
P + N-channel MOSFET Gate QG SR
-
-
-
4
-
nC
nC
mA
I
Charge
|VGS|=5V; 0.5A pulsed
drain current
-4
IDDDC=500mA; PMOS-
|VGS|=5V; 0.5A pulsed
drain current
External Inductor Saturation
Current Margin
ΔISAT SR
400
-
The saturation current
of the coil must be
larger than IDDDC
ΔISAT
+
P + N-channel MOSFET Gate
threshold voltage
V
V
GSTH SR
-
-
-
1
-
-
-
V
V
V
NMOS
PMOS
-1
0.8
N-channel MOSFET reverse
diode forward voltage
RDN SR
1) Capacitor min-max range represent typical +-35% tolerance including DC bias effect. The trace resistance from the capacitor
to the supply or ground rail should be limited to 25 mOhm.
Data Sheet
431
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification System Phase Locked Loop (SYS_PLL)
3.16
System Phase Locked Loop (SYS_PLL)
Table 3-35 PLL System
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10
Max.
40
DCO Input frequency range
Modulation Amplitude
Peak Period jitter
f
REF CC
-
-
-
MHz
%
MA CC
DP CC
0
2
-200
200
ps
without modulation
(PLL output frequency)
Peak Accumulated Jitter
Total long term jitter
D
PP CC
-5
-
-
-
5
ns
ns
without modulation
J
TOT CC
11.5
including modulation;
MA 1.25%; fREF 20MHz
System frequency deviation
DCO frequency range
PLL lock-in time
f
f
SYSD CC
DCO CC
-
-
-
-
0.01
800
100
%
with active modulation
400
4
MHz
µs
tL CC
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
432
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Peripheral Phase Locked Loop (PER_PLL)
3.17
Peripheral Phase Locked Loop (PER_PLL)
Table 3-36 PLL Peripheral
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Peak Accumulated jitter at
SYSCLK pin
D
PP CC
-1000
-
1000
ps
Peak only
Peak accumulated jitter
RMS Accumulated jitter
D
D
PPI CC
-700
-100
-
-
700
100
ps
ps
Peak only
RMS CC
measured over 1 µs;
fREF = 20 MHz and fDCO
= 640 MHz or fREF = 25
MHz and fDCO = 800
MHz
Peak Period jitter
DP CC
-200
-125
-85
-
-
-
-
200
125
85
ps
ps
ps
ps
f
DCO = 640 MHz or fDCO
= 800 MHz
REF = 10 MHz; fDCO
640 MHz
REF = 20 MHz; fDCO
640 MHz
REF = 25 MHz; fDCO
800 MHz
Absolute RMS jitter (PLL out)
Absolute RMS jitter (PLL out)
Absolute RMS jitter (PLL out)
J
J
J
ABS10 CC
ABS20 CC
ABS25 CC
f
=
=
=
f
-85
85
f
DCO frequency range
DCO input frequency range
PLL lock-in time
f
f
DCO CC
REF CC
400
10
4
-
-
-
800
40
MHz
MHz
µs
tL CC
100
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
433
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification AC Specifications
3.18
AC Specifications
All AC parameters are specified for the complete operating range defined in Chapter 3.4 unless otherwise noted
in column Note / Test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FLEX / VDDP3
90%
90%
10%
10%
VSS
tr
tf
rise_fall
Figure 3-8 Definition of rise / fall times
VEXT/FLEX/ VDDP3
Timing
Reference
Points
VEXT/FLEX /VDDP3
VEXT /FLEX / VDDP3
2
2
VSS
timing_reference
Figure 3-9 Time Reference Point Definition
Data Sheet
434
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification JTAG Parameters
3.19
JTAG Parameters
The following parameters are applicable for communication through the JTAG debug interface. The JTAG module
is fully compliant with IEEE1149.1-2000.
Table 3-37 JTAG
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
10
10
-
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
TCK low time
-
TCK clock rise time
TCK clock fall time
4
4
-
-
TDI/TMS setup to TCK rising
edge
6.0
TDI/TMS hold after TCK rising t7 SR
6.0
-
-
ns
edge
TDO valid after TCK falling edge t8 CC
(propagation delay)
3.0
-
-
-
-
-
ns
ns
ns
ns
CL≤20pF
CL≤50pF
-
25
-
TDO hold after TCK falling edge t18 CC
2
-
TDO high impedance to valid
from TCK falling edge
t9 CC
25
CL≤50pF
CL≤50pF
TDO valid output to high
impedance from TCK falling
edge
t
10 CC
-
-
25
ns
t1
0.9 VEXT
0.1 VEXT
0.5 VEXT
t5
t4
t2
t3
MC_JTAG_TCK
Figure 3-10 Test Clock Timing (TCK)
Data Sheet
435
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TC36x AA-Step
Electrical Specification JTAG Parameters
TCK
TMS
TDI
t6
t7
t6
t7
t9
t8
t10
TDO
t18
MC_JTAG
Figure 3-11 JTAG Timing
Data Sheet
436
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TC36x AA-Step
Electrical Specification DAP Parameters
3.20
DAP Parameters
The following parameters are applicable for communication through the DAP debug interface.
Table 3-38 DAP
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DAP0 clock rise time
t
t
14 SR
15 SR
-
-
-
-
-
-
-
-
-
-
1
4
2
1
4
2
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
f=160MHz
f=40MHz
f=80MHz
f=160MHz
f=40MHz
f=80MHz
-
-
DAP0 clock fall time
-
-
-
DAP1 setup to DAP0 rising edge t16 SR
4
5
2
-
f=40MHz
DAP1 hold after DAP0 rising
edge
t
t
17 SR
19 CC
-
DAP1 valid per DAP0 clock
period
4
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=20pF ; f=160MHz
CL=20pF ; f=80MHz
CL=50pF ; f=40MHz
8
10
2
DAP0 high time
DAP0 low time
t
t
t
12 SR
13 SR
11 SR
2
DAP0 clock period
6.25
Table 3-39 SCR DAP
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
-
Typ.
Max.
DAP0 clock rise time
DAP0 clock fall time
t
t
14 SR
15 SR
-
-
-
-
8
8
-
ns
ns
ns
ns
f=20MHz
f=20MHz
-
DAP1 setup to DAP0 rising edge t16 SR
10
10
DAP1 hold after DAP0 rising
edge
t
17 SR
-
DAP1 valid per DAP0 clock
period
t
19 CC
30
-
-
ns
CL=20pF ; f=20MHz
DAP0 high time
DAP0 low time
t
t
t
12 SR
13 SR
11 SR
15
15
50
-
-
-
-
-
-
ns
ns
ns
DAP0 clock period
Data Sheet
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TC36x AA-Step
Electrical Specification DAP Parameters
t11
t15
t14
t13
t12
0.9 VEXT
0.1 VEXT
0.5 VEXT
DAP0
t16
t17
DAP1
(Host to Device)
t11
DAP11),2)
(Device to Host)
t19
1) The DAP1 and DAP2 device to host timing is individual for both pins.
There is no guaranteed max. signal skew.
2) No explicite setup and hold times are given for DAP1 for the direction Device to Host.
Only t11 and t19 are guaranteed and the tool may set the sample point freely.
Figure 3-12 DAP Timing
Note:The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
Data Sheet
438
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TC36x AA-Step
Electrical Specification ASCLIN SPI Master Timing
3.21
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC36x.
Note:Pad asymmetry is already included in the following timings.
Table 3-40 Master Mode strong sharp (ss) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period
t
t
t
50 CC
500 CC
51 CC
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
Deviation from ideal duty cycle
-2
2
MTSR delay from ASCLKO
shifting edge
-3.5
3.5
ASLSOn delay from the first
ASCLKO edge
t
t
t
510 CC
52 SR
53 SR
-3
25
-2
-
-
-
3.5
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
MRST setup to ASCLKO
latching edge
-
-
MRST hold from ASCLKO
latching edge
Table 3-41 Master Mode strong medium (sm) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
ASCLKO clock period
t
t
t
50 CC
500 CC
51 CC
-
-
-
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
-5
5
7
MTSR delay from ASCLKO
shifting edge
-7
ASLSOn delay from the first
ASCLKO edge
t
t
t
510 CC
52 SR
53 SR
-7
35
-5
-
-
-
7
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
Table 3-42 Master Mode medium (m) output pads
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
160
-10
Typ.
Max.
-
ASCLKO clock period
t
t
t
50 CC
500 CC
51 CC
-
-
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
10
20
MTSR delay from ASCLKO
shifting edge
-20
ASLSOn delay from the first
ASCLKO edge
t
510 CC
-20
-
20
ns
CL=50pF
Data Sheet
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TC36x AA-Step
Electrical Specification ASCLIN SPI Master Timing
Table 3-42 Master Mode medium (m) output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to ASCLKO
latching edge
t
t
52 SR
53 SR
80
-
-
ns
ns
CL=50pF
CL=50pF
MRST hold from ASCLKO
latching edge
-15
-
-
t50
ASCLKO
MTSR
t51
t51
t500
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-13 ASCLIN SPI Master Timing
Data Sheet
440
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TC36x AA-Step
Electrical Specification QSPI Timings, Master and Slave Mode
3.22
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC36x.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
Note:Pad asymmetry is already included in the following timings.
Table 3-43 Master Mode Timing, LVDS output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20 1)
-1 1)
Max.
-
1 1)
SCLKO clock period
t
t
50 CC
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle
500 CC
MTSR delay from SCLKO
shifting edge
t
51 CC
-3 1)
-
-
-
-
-
4 1)
ns
ns
ns
ns
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-4 1)
5.5 1)
10 1)
30 1)
-
CL=25pF, driver
strength ss
-10 1)
-30 1)
18 1)
CL=25pF, driver
strength sm
CL=25pF, driver
strength m
MRST setup to SCLK latching
edge
t
52 SR
CL=25pF; valid for
LVDS Input pads of
QSPI2 only
MRST hold from SCLK latching t53 SR
-1 1)
-
-
ns
CL=25pF; valid for
edge
LVDS Input pads only
1) The load (CL=25pF) defined in the condition list is a load definition for the single end signal SLSO and does not intend to add
an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the
signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-44 Master Mode Strong Sharp (ss) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle
500 CC
-2
2
MTSR delay from SCLKO
shifting edge
t
51 CC
-4
-
-
-
-
5
5
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-4
MRST setup to SCLK latching
edge
t
52 SR
25 1) 2)
-2 1)2)
MRST hold from SCLK latching t53 SR
-
edge
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Data Sheet
441
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TC36x AA-Step
Electrical Specification QSPI Timings, Master and Slave Mode
Table 3-45 Master Mode Strong Medium (sm) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period
t
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle
500 CC
-5
5
MTSR delay from SCLKO
shifting edge
t
51 CC
-7
-
-
-
-
7
7
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-7
MRST setup to SCLK latching
edge
t
52 SR
35 1) 2)
-5 1)2)
MRST hold from SCLK latching t53 SR
-
edge
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-46 Master Mode Medium (m) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
160
-10
Max.
-
SCLKO clock period
t
t
50 CC
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle
500 CC
10
MTSR delay from SCLKO
shifting edge
t
51 CC
-20
-
-
-
20
20
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-20
MRST setup to SCLK latching
edge
t
52 SR
80 1) 2)
MRST hold from SCLK latching t53 SR
edge
-15 1)2)
-13 1)2)
-
-
-
-
ns
ns
CL=50pF
CL=50pF; SCR SSC
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-47 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SCLK clock period
SCLK duty cycle
t
t
t
54 SR
4 x TMAX
-
-
-
-
-
ns
%
55/t54 SR
56 SR
40
6
60
-
MTSR setup to SCLK latching
edge
ns
ns
Input Level AL
Input Level TTL
6
-
Data Sheet
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TC36x AA-Step
Electrical Specification QSPI Timings, Master and Slave Mode
Table 3-47 Slave mode timing (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MTSR hold from SCLK latching t57 SR
edge
4
6
4
6
3
6
5
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
-
SLSI setup to first SCLK shift
edge
t
t
t
58 SR
59 SR
60 CC
-
-
SLSI hold from last SCLK
latching edge
-
-
MRST delay from SCLK shift
edge
35
driver = strong edge =
medium ; CL=50pF
2
-
-
-
24
80
-
ns
ns
ns
driver = strong edge =
sharp ; CL=50pF
15
14
medium driver ;
CL=50pF
medium driver ;
CL=50pF; SCR SSC
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-14 Master Mode Timing
Data Sheet
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TC36x AA-Step
Electrical Specification QSPI Timings, Master and Slave Mode
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-15 Slave Mode Timing
Data Sheet
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TC36x AA-Step
Electrical Specification MSC Timing 5 V Operation
3.23
MSC Timing 5 V Operation
The following section defines the timings.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Table 3-48 LVDS clock/data (LVDS pads in LVDS mode) valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
1) 2)
FCLPx clock period
t
40 CC
2 * TA
-
-
ns
LVDS; CL=50pF
3)
Deviation from ideal duty cycle
SOPx output delay
t
t
t
400 CC
44 CC
45 CC
-1 3)
-3 3)
-4 3)
-
-
-
1 3)
3 3)
5 3)
ns
ns
ns
LVDS; 0 < CL < 50pF
CL=50pF
ENx output delay
ss; CL=50pF; ABRA
block bypassed
-4 3)
-
4 3)
ns
ss; CL=50pF; ABRA
block used
-2 3)
-30 3)
-
-
10 3)
30 3)
ns
ns
sm; CL=50pF
m; CL=50pF
1) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The load (CL=50pF) defined in the condition list is a load definition for the single end signal EN and does not intend to add an
additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal
on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-49 Strong sharp (ss) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
-
FCLPx clock period
t
t
t
t
40 CC
400 CC
44 CC
45 CC
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
SOPx output delay
2
-4
3.5
3.5
ENx output delay
-4
Table 3-50 Strong medium (sm) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-5
Max.
FCLPx clock period
t
t
t
t
40 CC
400 CC
44 CC
45 CC
-
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
SOPx output delay
5
7
7
-7
ENx output delay
-7
Data Sheet
445
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TC36x AA-Step
Electrical Specification MSC Timing 5 V Operation
Table 3-51 Medium (m) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-10
Max.
-
FCLPx clock period
t
t
t
t
40 CC
400 CC
44 CC
45 CC
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
SOPx output delay
10
20
20
-20
ENx output delay
-20
Table 3-52 Upstream Interface
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
-
SDI bit time
SDI rise time
SDI fall time
t
t
t
46 SR
48 SR
49 SR
8 * tMSC
-
-
-
ns
ns
ns
-
-
200
200
t40
t400
FCLP
SOP
t44
t44
t45
t45
0.5 VEXT/FLEX
EN
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-16 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
Data Sheet
446
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TC36x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24
Ethernet Interface (ETH) Characteristics
3.24.1
ETH Measurement Reference Points
ETH Clock
ETH I/O
1.4
2.0
V
1.4 V
V
2.0
V
0.8
V
0.8
V
tR
tF
ETH_Testpoints.vsd
Figure 3-17 ETH Measurement Reference Points
Data Sheet
447
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TC36x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.2
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 3-53 ETH Management Signal Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
400
160
160
10
Max.
ETH_MDC period
ETH_MDC high time
ETH_MDC low time
t1 CC
t2 CC
t3 CC
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
-
-
ETH_MDIO setup time (output) t4 CC
-
ETH_MDIO hold time (output)
ETH_MDIO data valid (input)
t5 CC
t6 SR
10
-
0
300
t1
t3
t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4
t5
ETH_MDIO
(output )
Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input )
Valid Data
ETH_Timing-Mgmt.vsd
Figure 3-18 ETH Management Signal Timing
Data Sheet
448
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TC36x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.3
ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.
Table 3-54 ETH MII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Clock period
t7 SR
-
40
-
ns
ns
ns
ns
ns
ns
CL=25pF ;
baudrate=100Mbps
-
400
-
CL=25pF ;
baudrate=10Mbps
Clock high time
Clock low time
t8 SR
t9 SR
14
-
-
-
-
26
CL=25pF ;
baudrate=100Mbps
140 1)
14
260 2)
26
CL=25pF ;
baudrate=10Mbps
CL=25pF ;
baudrate=100Mbps
140 1)
260 2)
CL=25pF ;
baudrate=10Mbps
Input setup time
Input hold time
t
t
t
10 SR
11 SR
12 CC
10
10
0
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
-
Output valid time
25
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t7
t9
t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t10
t11
ETH_MII_RXD[3:0]
ETH_MII_RX_DV
ETH_MII_RX_ER
(sourced by PHY )
Valid Data
ETH_MII_TX_CLK
t12
ETH_MII_TXD[3:0]
ETH_MII_TXEN
Valid Data
(sourced by controller )
ETH_Timing-MII.vsd
Figure 3-19 ETH MII Signal Timing
Data Sheet
449
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TC36x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.4
ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.
Table 3-55 ETH RMII Signal Timing Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ETH_RMII_REF_CL clock
period
t
13 SR
-
20
-
ns
ns
ns
ns
50ppm ; CL=25pF
CL=25pF
ETH_RMII_REF_CL clock high t14 SR
time
7 1)
7 1)
4
-
13 2)
13 2)
-
ETH_RMII_REF_CL clock low
time
t
t
15 SR
16 CC
-
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV;
setup time 3)
-
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV;
hold time 3)
t
17 CC
2
-
-
ns
CL=25pF
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
3) For ETHRXD and ETHCRSDV signals this parameter is a SR.
t13
t15
t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t16
t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0],
ETHCRSDV,
ETHRXER
Valid Data
ETH_Timing-RMII.vsd
Figure 3-20 ETH RMII Signal Timing
Data Sheet
450
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.5
ETH RGMII Parameters
In the following, the parameters of the RGMII are described.
Table 3-56 ETH RGMII Signal Timing Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
36
Max.
44
TX Clock period
t
19 CC
40
400
8
ns
ns
ns
ps
ns
100Mbps
10Mbps
Gigabit
360
7.2
-500
1
440
8.8
Data to Clock Output skew
t
t
20 CC
21 SR
0
500
2.6
Data to Clock input skew (at
receiver)
1.8
Clock duty cycle
t
duty CC
40
50
50
-
60
%
%
%
%
10/100Mbps
Gigabit
45
55
GREFCLK duty cycle
t
duty_in SR
45
55
GREFCLK Input accuracy
ACC SR
-0.005
-
0.005
t
19
TXCLK
at transmiter
t20
TXD[3:0],TXCTL
Figure 3-21 ETH RGMII TX Signal Timing (Delay on Destination (DoD))
t19
t
21
RXCLK
at receiver
RXD[3:0],RXCTL
Figure 3-22 ETH RGMII RX Signal Timing (Delay on Source (DoS))
Data Sheet
451
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification E-Ray Parameters
3.25
E-Ray Parameters
The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL =
25 pF.
Table 3-57 Transmit Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise time of TxEN
Fall time of TxEN
tdCCTxENRise2
5 CC
-
-
-
-
-
9
ns
ns
ns
ns
CL=25pF
tdCCTxENFall25
CC
-
-
-
9
CL=25pF
Sum of rise and fall time
tdCCTxRise25+d
CCTxFall25 CC
9
20% - 80% ; CL=25pF
Sum of delay between TP1_FF tdCCTxEN01
25
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxEN
CC
Sum of delay between TP1_FF tdCCTxEN10
-
-
25
ns
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxEN
CC
Asymmetry of sending
t
tx_asym CC -2.45
-
-
2.45
25
ns
ns
CL=25pF
Sum of delay between TP1_FF tdCCTxD01 CC -
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxD
Sum of delay between TP1_FF tdCCTxD10 CC -
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxD
-
-
25
9
ns
ns
TxD signal sum of rise and fall
time at TP1_BD
t
txd_sum CC
-
Table 3-58 Receive Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -30.5
ept25 SR
-
43.0
ns
ns
%
%
CL=25pF
CL=15pF
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -31.5
ept15 SR
-
-
-
44.0
70
Threshold for detecting logical TuCCLogic1
high SR
Threshold for detecting logical TuCCLogic0
35
30
65
low
SR
Data Sheet
452
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification E-Ray Parameters
Table 3-58 Receive Parameters (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sum of delay between TP4_CC tdCCRxD01 CC -
and TP4_FF and delays derived
from TP4_FFi, rising edge of
RxD
-
10
ns
Sum of delay between TP4_CC tdCCRxD10 CC -
and TP4_FF and delays derived
from TP4_FFi, falling edge of
RxD
-
10
ns
Data Sheet
453
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification HSCT Parameters
3.26
HSCT Parameters
Table 3-59 HSCT - Rx parasitics and loads
Parameter
Symbol
Values
Typ.
3.5
Unit
Note / Test Condition
Min.
Max.
Capacitance total budget
C
total CC
-
5
pF
Total Budget for
complete receiver
including silicon,
package, pins and
bond wire
Parasitic inductance budget
Htotal CC
-
5
-
nH
Table 3-60 HSCT - Rx/Tx setup timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
60
RX o/p duty cycle
DCrx CC
40
-
-
-
-
-
-
%
Disable time of the LVDS pad
Enable time of the LVDS pad
t
t
LVDSDIS CC
LVDSEN CC
20
ns
ns
ns
ns
-
400
250
0.2
Wakeup time from Sleep Mode tSWU CC
-
Maximum length of a wake-up
glitch that does not wake-up the
receiver
t
WUP CC
-
Bias startup time
t
bias CC
-
5
10
µs
Bias distributor waking
up from power down
and provide stable
Bias.
RX startup time
TX startup time
trxi CC
ttx CC
-
-
-
-
600
280
ns
ns
Wake-up RX from
power down.
Wake-up TX from
power down.
Data Sheet
454
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Inter-IC (I2C) Interface Timing
3.27
Inter-IC (I2C) Interface Timing
All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-61 I2C Standard Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
-
-
300
ns
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Capacitive load for each bus line Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
4.7
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
and ATART condition
Rise time of both SDA and SCL t2
-
-
-
-
-
-
-
-
-
1000
ns
µs
ns
µs
µs
µs
µs
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data hold time
t3
t4
t5
t6
t7
t8
0
-
-
-
-
-
-
-
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data set-up time
250
4.7
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Hold time for the (repeated)
START condition
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for (repeated)
START condition
4.7
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data Sheet
455
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Inter-IC (I2C) Interface Timing
Table 3-62 I2C Fast Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
20+0.1*Cb
-
300
ns
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Capacitive load for each bus line Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
1.3
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
and ATART condition
Rise time of both SDA and SCL t2
20+0.1*Cb
-
-
-
-
-
-
-
-
300
ns
µs
ns
µs
µs
µs
µs
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data hold time
t3
t4
t5
t6
t7
t8
0
-
-
-
-
-
-
-
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data set-up time
100
1.3
0.6
0.6
0.6
0.6
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Hold time for the (repeated)
START condition
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for (repeated)
START condition
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data Sheet
456
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Inter-IC (I2C) Interface Timing
Table 3-63 I2C High Speed Mode Timing
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
400
40 1)
80 1)
40 1)
80 1)
70 1)
-
Capacitive load for each bus line Cb SR
-
-
-
-
-
-
-
-
-
-
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fall time of SCL
t11
t12
t13
t14
t3
10 1)
10 1)
10 1)
10 1)
0 1)
10 1)
160 1)
60 1)
160 1)
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
Fall time of SDA
Rise time of SCL
Rise time of SDA
Data hold time
Data set-up time
t4
Low period of SCL clock
High period of SCL clock
t5
-
t6
-
Hold time for the (repeated)
START condition
t7
-
Set-up time for (repeated)
START condition
t8
160 1)
160 1)
-
-
-
-
ns
ns
bus line load of 100pF
bus line load of 100pF
Set-up time for STOP condition t9
1) Values are defined for Cb = 100pF, for the Timing of Cb = 400pF see the I2C Standard.
t1
t2
t4
70%
30%
SDA
SCL
t1
t3
t2
t6
9th
clock
t7
t5
t10
S
SDA
SCL
t8
t7
t9
9th
clock
Sr
P
S
Figure 3-23 I2C Standard and Fast Mode Timing
Data Sheet
457
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Flash Target Parameters
3.28
Flash Target Parameters
Table 3-64 Flash
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program Flash Erase Time per
logical sector 1)
t
t
ERP CC
-
-
0.5
s
s
cycle count < 1000
Program Flash Erase Time per
Multi-Sector Command 1)
MERP CC
-
-
0.5
For consecutive logical
sectors in a physical
sector with total range ≤
512 kByte; cycle count
< 1000
Program Flash program time
per page in 5 V mode 1)
t
t
t
t
PRP5 CC
PRP3 CC
PRPB5 CC
PRPB3 CC
-
-
-
-
-
-
-
-
-
-
80
µs
µs
µs
µs
s
32 Byte
32 Byte
256 Byte
256 Byte
Program Flash program time
per page in 3.3 V mode 1)
115
220
530
2.2
Program Flash program time
per burst in 5 V mode 1)
Program Flash program time
per burst in 3.3 V mode 1)
Program Flash program time for tPRPB3_1MB
1 MByte with burst programming CC
in 3.3 V mode excluding
communication 1)
Derived value for
documentation purpose
Program Flash program time for tPRPB5_1MB
1 MByte with burst programming CC
in 5 V mode excluding
-
-
-
-
1
4
s
s
Derived value for
documentation purpose
communication 1)
Program Flash program time for tPRPB5_PF
Derived value for
complete PFlash with burst
programming in 5 V mode
excluding communication 1)
CC
documentation purpose
Write Page Once adder 1)
t
ADD CC
-
-
-
-
20
µs
µs
Adder to Program Time
when using Write Page
Once
Program Flash suspend to read tSPNDP CC
120
For Write Burst, Verify
Erased and for multi-
(logical) sector erase
commands
latency 1)
Data Flash Erase Disturb Limit
(single ended sensing mode)
N
N
N
DFD CC
-
-
-
-
-
-
50
cycles
cycles
cycles
Data Flash Erase Disturb Limit
(complement sensing mode)
DFDC CC
UCBD CC
500
500
UCB Erase Disturb Limit
Data Sheet
458
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Flash Target Parameters
Table 3-64 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program time data flash per
page 1)2)
t
t
PRD CC
-
-
75
µs
s
8 Byte
Complete Device Flash Erase
Time PFlash and DFlash 1)3) 4) 5)
ER_Dev CC
-
3
5
Valid for less than 1000
cycles, w/o UCB.
Derived value for
documentation
purpose.
Data Flash program time per
burst 1)2)
t
t
PRDB CC
-
-
-
-
-
-
-
-
140
120
2
µs
µs
µs
32 Byte
Data Flash suspend to read
latency 1)
SPNDD CC
Wait time after margin change tFL_MarginDel
CC
Program Flash Endurance per
Logical Sector
N
E_P CC
1000
cycles Replace logical sector
commandshall beused
if a sector fails during
erase or program
Number of erase operations per NERP CC
physical sector in program flash
-
-
-
-
16000
cycles
Program Flash Retention Time, tRET CC
Sector
20
20
-
-
years Max. 1000
erase/program cycles
UCB Retention Time
t
RTU CC
years Max. 100
erase/program cycles
per UCB, max 500
erase/program cycles
for all UCBs together
Data Flash access delay
Data Flash ECC Delay
t
t
t
t
DF CC
-
-
-
-
-
-
-
-
100
20
ns
ns
ns
ns
see RFLASH of DMU
register HF_DWAIT
DFECC CC
PF CC
see RECC of DMU
register HF_DWAIT
Program Flash access delay
Program Flash ECC delay
30
see RFLASH of DMU
register HF_PWAIT
PFECC CC
10
see RECC and CECC
of DMU register
HF_PWAIT
Number of erase operations on NERD0C CC
DF0 over lifetime (complement
sensing mode) 6)
-
-
-
-
4000000 cycles
Number of erase operations on NERD0S CC
DF0 over lifetime (single ended
sensing mode) 7)
750000
cycles
Data Sheet
459
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Flash Target Parameters
Table 3-64 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
2000000 cycles
Number of erase operations on NERD1C CC
DF1 over lifetime (complement
sensing mode) 6)
-
-
-
-
-
Number of erase operations on NERD1S CC
DF1 over lifetime (single ended
sensing mode) 7)
-
-
-
500000
500000
125000
cycles
Data Flash Endurance per
EEPROMx sector (complement CC
sensing mode) 8)
NE_EEP10C
cycles Max. data retention
time 10 years
DataFlash Endurance per
EEPROMx sector (single ended CC
sensing mode) 8)
NE_EEP10S
cycles Retention time and Tj
according below
example temperature
profile
-
-
-
-
-
125000
125000
250000
cycles max data retention time
20y, Tj=110°C
cycles max data retention time
8.2y, Tj=125°C
Data Flash Endurance per
HSMx sector (complement
sensing mode) 8)
N
N
E_HSMC CC -
cycles Max. data retention
time 10 years
Data Flash Endurance per
HSMx sector (single ended
sensing mode) 8)
E_HSMS CC -
-
125000
cycles Retention time and Tj
according below
example temperature
profile
-
-
-
-
-
125000
125000
150
cycles max data retention time
20y, Tj=110°C
cycles max data retention time
8.2y, Tj=125°C
Junction temperature limit for
PFlash program/erase
operations
T
JPFlash SR
-
°C
Data Flash Erase Time per
Sector 1)3)5)
t
t
ERD1 CC
ERDM CC
-
-
-
-
0.5
1.5
s
s
Max. 1000
erase/program cycles
Data Flash Erase Time per
Max allowed cycles,
see NE_EEP10 and
NE_HSM parameters
1)3)5)
Sector
DataFlash Adder on Erase Time tER_ADDC32C
-
-
50
ms
Adder per 32 kByte on
erase time; applicable
only when using
per 32kByte erase size when
using complement sensing
mode 1)
CC
complement mode
Data Sheet
460
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Flash Target Parameters
Table 3-64 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Data Flash Erase Time per
Multi-Sector Command 1)3)5)
t
t
MERD1 CC
-
-
0.5
s
Max 1000
erase/program cycles;
For consecutive logical
sectors ≤ 256KBytes
Data Flash Erase Time per
Multi-Sector Command 1)3)5)
MERDM CC
-
-
1.5
s
Max allowed cycles,
see NE_EEP10x and
NE_HSMxParameters;
For consecutive logical
sectors ≤ 256 kByte
Program Flash Access Delay at tPF_low_VDDP3
reduced VDDP3 voltage supply CC
during cranking
-
-
-
-
-
-
-
-
-
-
60
10
10
10
200
ns
µs
µs
µs
µs
see register
DMU_HF_PWAIT.CFL
ASH
Data Flash Erase Verify time per tVER_PAGE_DC
Time per 8 Byte page
for Verify Erased Page
command
page (Complement Sensing) 2) CC
Data Flash Erase Verify time per tVER_PAGE_DS
Time per 8 Byte page
for Verify Erased Page
command
page (Single Ended Sensing) 1) CC
Program Flash Erase Verify
time per page 1)
tVER_PAGE_P
CC
Time per 32 Byte page
for Verify Erased Page
command
Data Flash Erase Verify time per tVER_SEC_DC
Time per 2 KB sector
for Verify Erased
Logical Sector Range
command
sector (Complement Sensing) 1) CC
Data Flash Erase Verify time per tVER_SEC_DS
-
-
-
-
360
360
µs
µs
Time per 4 KB sector
for Verify Erased
Logical Sector Range
command
sector (Single Ended Sensing) 1) CC
Program Flash Erase Verify
time per sector 1)
tVER_SEC_P
CC
Time per 16KB sector
for Verify Erased
Logical Sector Range
command
Data Flash Erase Verify time per tVER_WL_DC
-
-
-
-
-
-
30
50
30
µs
µs
µs
wordline (ComplementSensing) CC
1)
Data Flash Erase Verify time per tVER_WL_DS
wordline (Single Ended
Sensing) 1)
CC
Program Flash Erase Verify
time per wordline 1)
tVER_WL_P
CC
1) Only vaild for fFSI = 100MHz.
2) Time is not dependent on program mode (5V or 3.3V).
Data Sheet
461
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Flash Target Parameters
3) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase processes
may be increased by up to 50%.
4) Using 512 kByte / 256 kByte erase commands (PFlash / DFlash).
5) If the DataFlash is operated in Complement Sensing Mode the erase time is increased by erase_size / 32kByte x
tER_ADDC32C
6) Allows segmentation of addressable memory into 8 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD
7) Allows segmentation of addressable memory into 6 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD
8) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
.
.
Data Sheet
462
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Quality Declarations
3.29
Quality Declarations
Table 3-65 Quality Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Moisture Sensitivity Level
MSL CC
-
-
3
Conforming to Jedec J-
STD--020C for 240C
ESD susceptibility according to VCDM SR
Charged Device Model (CDM)
-
-
-
500
750
V
V
for all other balls/pins;
conforming to JESD22-
C101-C
-
for corner balls/pins;
conforming to JESD22-
C101-C
ESD susceptibility according to VHBM SR
Human Body Model (HBM)
-
-
-
-
2000
2000
V
V
Conforming to
JESD22-A114-B
ESD susceptibility of the LVDS
pins according to Human Body
Model (HBM)
VHBM1 SR
Operation Lifetime
t
OP CC
-
-
24500
hour
see below temperature
profile as an example
Example Temperature Profile
The following temperature profile is an example. Application specific temperature profiles need to be aligned and
approved by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-66 Example Temperature Profile
TJ=
Duration [h]
≤ 30
Comment
≤ 170°C
≤ 160°C
≤ 150°C
≤ 140°C
≤ 130°C
≤ 120°C
≤ 110°C
≤ 100°C
≤ 90°C
≤ 80°C
≤ 70°C
≤ 120
≤ 220
≤ 350
≤ 780
≤ 1600
≤ 3000
≤ 7000
≤ 8000
≤ 2400
≤ 1000
≤ 24500
total time
Data Sheet
463
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Quality Declarations
Table 3-67 Example Inactive Lifetime Temperature Profile
TJ=
Duration [h]
Comment
≤ 55°C
≤ 150700
Data Sheet
464
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Package Outline
3.30
Package Outline
Figure 3-24 Package Outlines LFBGA-292
Figure 3-25 Package Outlines LFBGA-180
Data Sheet
465
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OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Package Outline
Figure 3-26 Package Outlines LQFP-176
Figure 3-27 Package Outlines LQFP-144
Data Sheet
466
V 1.1, 2021-03
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TC36x AA-Step
Electrical Specification Package Outline
Figure 3-28 Package Outlines TQFP-144
Table 3-68 Exposed Pad Dimensions for LQFP-144 and LQFP-176
LQFP-144 (0.5 mm) and
LQFP-176 (0.5 mm)
Ex; nominal EPad size
Ey; nominal EPad size
Ax; solderable EPad size
Ay; solderable EPad size
7.5 mm ± 50 μm
7.5 mm ± 50 μm
6.7 mm ± 50 μm
6.7 mm ± 50 μm
Table 3-69 Exposed Pad Dimensions for TQFP-144
TQFP-144 (0.4 mm) Ex; nominal EPad size
8.7 mm ± 50 μm
8.7 mm ± 50 μm
7.9 mm ± 50 μm
7.9 mm ± 50 μm
Ey; nominal EPad size
Ax; solderable EPad size
Ay; solderable EPad size
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
Data Sheet
467
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
Electrical Specification Package Outline
3.30.1
Package Parameters
Table 3-70 Package Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
22
23
18
17
4.5
4.5
2
Thermal resistance (junction to RTH_JA
ambient) 1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
LFBGA-180
LFBGA-292
QFP-144
CC
QFP-176
Thermal resistance (junction to RTH_JCB
case bottom) 1)
CC
LFBGA-180
LFBGA-292
QFP-144
2
QFP-176
Thermal resistance (junction to RTH_JCT
case top) 1)
CC
6
LFBGA-180
LFBGA-292
QFP-144
5
10
10
QFP-176
1) The top and bottom thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) are to be combined
with the thermal resistances between the junction and the case given above (RTH_JCT, RTH_JCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTH_JA). The thermal resistances between the case
and the ambient (RTH_CTA, RTH_CBA) depend on the external system (PCB, case) characteristics and are under user
responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTH_JA * PD, where the RTH_JA is
the total thermal resistance between the junction and the ambient.
Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1).
Data Sheet
468
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.4 to Version 0.6
4
History
Version 0.4 is the first version of this document.
4.1
Changes from Version 0.4 to Version 0.6
•
•
Changes in chapter Summary of Features, table Platform Feature Overview
–
–
–
Corrected spelling “HSPDM”
Changed spelling for packages
Added packages
Changes in chapter “Pin Definition and Function”
–
–
–
–
–
–
Changed package wording from BGA292 to LFBGA-292
Changed package wording from BGA180 to LFBGA-180
Changed package wording from QFP176 to LQFP-176
Changed package wording from QFP144 to LQFP-144
Added pinning for package LFBGA-180
Separated pinnings for package LQFP-144 and TQFP-144
•
Changes in chapter 'LFBGA-292 Package Variant Pin Configuration of TC36x'
–
Changes in 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.9, P00.10,
P00.11, P00.12
–
–
–
–
–
–
–
–
–
–
–
–
Changes in Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4, P02.5, P02.7, P02.8
Changes in 'Port 10 Functions' table; P10.2, P10.3, P10.7, P10.8
Changes in 'Port 11 Functions' table; P11.0, P11.1, P11.4, P11.5, P11.7, P11.8, P11.10, P11.12, P11.13
Changes in 'Port 12 Functions' table; P12.0, P12.1
Changes in 'Port 13 Functions' table; P13.0, P13.1, P13.2
Changes in 'Port 14 Functions' table; P14.0, P14.1, P14.6, P14.7, P14.8, P14.9, P14.10
Changes in 'Port 15 Functions' table; P15.0, P15.1, P15.2, P15.3, P15.4, P15.5
Changes in 'Port 20 Functions' table; P20.0, P20.3, P20.6, P20.7, P20.8, P20.9, P20.10, P20.14
Changes in 'Port 21 Functions' table; P21.0, P21.1, P21.2, P21.3, P21.4, P21.5, P21.6, P21.7
Changes in 'Port 23 Functions' table; P23.0, P23.1, P23.2, P23.3
Changes in 'Port 32 Functions' table; P32.2, P32.3, P32.4
Changes in 'Port 33 Functions' table; P33.0, P33.1, P33.2, P33.3, P33.4, P33.5, P33.6, P33.7, P33.8,
P33.9, P33.10, P33.12, P33.13
–
–
Changes in table “Analog Inputs” - Changed function for ball W5; Changed function for ball U5
Changes in table “System I/O” - Removed symbol and function for ball L19; Changed I/O for symbol ESR1,
ball G16; Changed I/O for symbol ESR0, ball F16
•
•
Added chapter 'LFBGA-180 Package Variant Pin Configuration of TC36x'
Changes in chapter 'LQFP-176 Package Variant Pin Configuration of TC36x'
Data Sheet
469
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.4 to Version 0.6
–
Changes in 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.9, P00.10,
P00.11, P00.12
–
–
–
–
–
–
–
–
–
–
–
Changes in 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4, P02.5, P02.7, P02.8
Changes in 'Port 10 Functions' table; P10.2, P10.3, P10.7, P10.8
Changes in 'Port 11 Functions' table; P11.10, P11.12
Changes in 'Port 13 Functions' table; P13.0, P13.1, P13.2
Changes in 'Port 14 Functions' table; P14.0, P14.1, P14.6, P14.7, P14.8, P14.9, P14.10
Changes in 'Port 15 Functions' table; P15.0, P15.1, P15.2, P15.3, P15.4, P15.5
Changes in 'Port 20 Functions' table; P20.0, P20.3, P20.6, P20.7, P20.8, P20.9, P20.10, P20.14
Changes in 'Port 21 Functions' table; P21.0, P21.1, P21.2, P21.3, P21.4, P21.5, P21.6, P21.7
Changes in 'Port 23 Functions' table; P23.0, P23.1, P23.2, P23.3
Changes in 'Port 32 Functions' table; P32.2, P32.3, P32.4
Changes in 'Port 33 Functions' table; P33.0, P33.1, P33.2, P33.3, P33.4, P33.5, P33.6, P33.7, P33.8,
P33.9, P33.10, P33.12, P33.13
–
–
Changes in table “Analog Inputs” - Changed function for pin 50; Changed function for pin 49
Changes in table “System I/O” - Removed symbol and function for pin 114; Changed I/O for symbol ESR1,
pin 120; Changed I/O for symbol ESR0, pin 122
–
Changes in table “Supply” - Changed symbol and function for pin 164; Changed symbol and function for
pin 54; Changed pin 177 to E-PAD
•
Changes in chapter 'LQFP-144 Package Variant Pin Configuration of TC36x'
–
–
–
–
–
–
–
–
–
–
–
–
–
Changes in 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.9, P00.12
Changes in 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4, P02.5, P02.7, P02.8
Changes in 'Port 10 Functions' table; P10.2, P10.3
Changes in 'Port 11 Functions' table; P11.10, P11.12
Changes in 'Port 13 Functions' table; P13.0, P13.1, P13.2
Changes in 'Port 14 Functions' table; P14.0, P14.1, P14.6
Changes in 'Port 15 Functions' table; P15.0, P15.1, P15.2, P15.3, P15.4, P15.5
Changes in 'Port 20 Functions' table; P20.0, P20.3, P20.6, P20.7, P20.8, P20.9, P20.10, P20.14
Changes in 'Port 21 Functions' table; P21.2, P21.3, P21.4, P21.5, P21.6, P21.7
Changes in 'Port 23 Functions' table; P23.1
Changes in 'Port 32 Functions' table; P32.4
Changes in 'Port 33 Functions' table; P33.4, P33.5, P33.6, P33.7, P33.8, P33.9, P33.10, P33.12, P33.13
Changes in table “Analog Inputs” - Changed function for pin 40, symbol EVADC_FC0CH0; Changed
function for pin 39, symbol EVADC_FC1CH0
–
–
Changes in table “System I/O” - Removed symbol and function for pin 91; Changed I/O for symbol ESR1,
ball 96; Changed I/O for symbol ESR0, ball 98
Changes in table “Supply” - Changed symbol and function for pin 136; Changed symbol and function for
pin 44; Changed pin 145 to E-PAD
•
•
Added chapter 'TQFP-144 Package Variant Pin Configuration of TC36x'
Changes in chapter “Bare Die Variant Pin Configuration of TC36x”
Data Sheet
470
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.4 to Version 0.6
–
Changes in table “Pad List” for different positions (Pad Names, Pad Types, X and Y values, and comments)
•
•
•
Changes in chapter “Legend”
Changes in chapter “Electrical Specification”
Changes in table “Absolute Maximum Ratings”
–
–
–
–
–
–
Added footnote of parameter VDDM
Changed footnote number of parameter VIN
Changed footnote number of parameter IIN
Changed footnote number of parameter ∑IIN
Added footnote 2)
Changed order of footnotes
•
Changes in table “Overload Parameters”
–
–
–
–
–
Changed note for parameter KOVAN
Changed footnote number of parameter KOVAN
Changed note for parameter KOVAP
Changed footnote number of parameter KOVAP
Added footnote 2)
•
Changes in table “Operating Conditions”
–
–
–
–
–
–
–
–
–
–
Deleted parameter fEBU
Added footnote number of parameter VDD
Changed footnote number of parameter VDDM
Changed footnote number of parameter VEXT
Changed footnote number of parameter VFLEX
Changed footnote number of parameter VDDP3
Changed footnote number of parameter VEVRSB
Changed footnote number of parameter VDDPPA
Added footnote 1)
Changed order of footnotes
•
•
Changes in table “PORST Pad”
–
–
–
–
Added footnote number of parameter IPDL
Added values and notes for parameter VIH
Added values and notes for parameter VIL
Added footnote 2)
Changes in table “Fast 5V GPIO”
–
–
Added footnote number of parameter IPUH
Added footnote number of parameter IPDL
Data Sheet
471
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
Changed and deleted values of parameter IOZ
Added footnotes 4) and 5)
•
•
Changes in table “Fast 3.3V GPIO”
–
–
–
–
Added footnote number of parameter IPUH
Added footnote number of parameter IPDL
Changed and deleted values of parameter IOZ
Added footnotes 4) and 5)
Changes in table “Slow 5V GPIO”
–
–
–
–
–
Added footnote number of parameter IPUH
Added footnote number of parameter IPDL
Changed and deleted values of parameter IOZ
Deleted footnote 4)
Added footnotes 4) and 5)
•
Changes in table “Slow 3.3V GPIO”
–
–
–
–
–
Added footnote number of parameter IPUH
Added footnote number of parameter IPDL
Changed and deleted values of parameter IOZ
Deleted footnote 4)
Added footnotes 4) and 5)
•
•
•
•
Changes in table “RFast 5V GPIO”
–
–
–
Added footnote number of parameter IPUH
Added footnote number of parameter IPDL
Added footnotes 4) and 5)
Changes in table “RFast 3.3V GPIO pad”
–
–
–
Added footnote number of parameter IPUH
Added footnote number of parameter IPDL
Added footnotes 4) and 5)
Changes in table “Class S 5V”
–
–
–
Added footnote number of parameter IPUH
Added footnote number of parameter IPDL
Added footnotes 2) and 3)
Changes in table “LVDS - IEEE standard LVDS general purpose link (GPL)”
–
–
–
Added footnote for parameter trise20
Added footnote for parameter tfall20
Changed footnote number of parameter VOD
Data Sheet
472
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
–
–
–
–
–
Changed value for parameter VI
Changed test conditions for parameter Vidth
Added values and test conditions for parameter Vidth
Changed test conditions for parameter Rin
Changed footnote number of parameter VODSM
Added footnotes 1) and 2)
Changed order of footnotes
•
Changes in table “VADC 5V”
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Added and changed values of parameter VAREF
Added footnote number of parameter VAREF
Added note for parameter VAIN
Changed footnote numbers of parameter TUE
Changed footnote number of parameter EAINL
Changed footnote numbers of parameter EADNL
Changed footnote number of parameter EAGAIN
Added footnote number of parameter EAOFF
Added and changed footnote numbers of parameter ENRMS
Added footnote number of parameter QCONV
Changed footnote number of parameter QAINS
Changed footnote number of parameter RCSD
Added footnote 1)
Changed order of footnotes
•
Changes in table “DSADC 5V”
–
–
–
–
–
–
–
–
Changed value of parameter VAREF
Added value of parameter IREF
Added value of parameter IRMS
Added and changed footnote numbers of parameter EDGAIN
Changed footnote number of parameter EDOFF
Changed footnote number of parameter SNR
Added footnote 4)
Changed order of footnotes
•
•
Changes in table “OSC_XTAL”
–
–
–
–
Added values for parameter DCX1
Added values for parameter JABSX1
Added values for parameter SRXTAL1
Added footnote 3)
Changes in table “Back-up Clock”
Changes in footnote 1)
–
Data Sheet
473
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.4 to Version 0.6
•
•
•
•
Changes in table “DTS PMS”
Added note for parameter TNL
–
Changes in table “DTS Core”
Added note for parameter TNL
–
Changes in chapter “Power Supply Current”
Changed chapter description
–
Changes in table “Current Consumption”
–
–
–
–
–
–
–
–
–
–
–
–
Changed values of parameter IDDPORST
Changed value for parameter IEXTRAIL
Changed value for parameter IEXTFLEX
Changed value for parameter IDDTOT
Added value for parameter IDDTOTDC3
Changed test condition for parameter IDDTOTDC3
Added value for parameter IDDTOTDC5
Changed test condition for parameter IDDTOTDC5
Changed values for parameter PD
Deleted footnote number of parameter IEXTFLEX
Deleted footnote number of parameter IDDP3RAIL
Changed footnotes 1) and 3)
•
Changes in table “Module Current Consumption”
–
–
–
Changed value of parameter of IEXTLVDS
Changed value of parameter of ISCRSB
Changed footnote 5)
•
•
Changes in table “Module Core Current Consumption”
–
–
Added values of parameter of IDDGTM
Changed footnote 1)
Changes in chapter “Power Supply Infrastructure and Supply Start-up”
–
–
–
–
–
–
Changed wording in descriptions for sub chapter “Supply Ramp-up and Ramp-down Behavior”
Changed numbers for HWCFG pins
Changed figure for 'Single Supply Mode (a)'
Changed figure for 'Single Supply Mode (e)'
Changed figure for 'External Supply Mode (d)'
Changed figure for 'External Supply Mode (h)'
•
Changes in table “Reset”
Data Sheet
474
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
–
Added values for parameter tWARMRSTSEQ
Changed value for parameter tBWP
Changed/ added values for parameter tSCR
•
•
Changes in table “EVR33 LDO”
–
–
Added footnote number of parameter dVOUT / dIOUT
Added footnote 7)
Changes in table “Supply Monitors”
–
–
–
–
–
–
–
–
–
–
Changed note for parameter VRST33
Added value for parameter VRSTC
Changed note for parameter VRSTC
Changed values of parameter VEXTMON
Added footnote number of parameter VEXTMON
Added footnote number of parameter VDDP3MON
Added footnote number of parameter VDDMON
Changed footnote 2)
Changed footnote 3)
Added footnote 5)
•
Changes in table “EVRC SMPS”
–
–
–
–
–
–
–
–
–
Changed values of parameter VDDDC
Changed values of parameter VDDDCT
Added/ changed values of parameter fDCDC
Changed value of parameter tSTRDC
Changed value of parameter ∆VDDDC
Deleted/ changed values of parameter dVDDDCT / dIOUT
Changed value for parameter IMAX
Deleted/ changed values of parameter dVDDDCT / dVIN
Changed values of parameter nDC
•
Changes in table “EVRC SMPS External components”
–
–
–
–
–
Deleted values of parameter COUT
Deleted values of parameter CIN
Added values of parameter LDC
Deleted values of parameter RON
Deleted values of parameter QG
•
•
Changes in table “PLL System”
Deleted values of parameter fMV
–
Changes in table “Master Mode Timing, LVDS output pads for data and clock”
Data Sheet
475
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.6 to Version 0.7
–
–
Added footnote numbers for all parameter values
Added footnote 1)
•
•
•
Changes in table “LVDS clock/data (LVDS pads in LVDS mode) valid for 5V”
–
–
Added footnote numbers for all parameter values
Added footnote 3)
Changes in subchapter “ETH RGMII Parameters”
–
–
Added figure for “ETH RGMII TX Signal Timing (Delay on Destination (DoD))”
Added figure for “ETH RGMII RX Signal Timing (Delay on Source (DoS))”
Changes in table “Flash”
–
–
–
Changed value for parameter tRTU
Changed description and note for parameter tVER-PAGE_DC
Changed description for parameter tVER-PAGE_DS
•
Changes in table “Package Parameters”
–
Added values for all parameters
4.2
Changes from Version 0.6 to Version 0.7
•
Changes in chapter “Bare Die Variant Pin Configuration of TC36x”
Added comment to “Pad List” concerning “neighbor pads”
–
•
Changes in chapter “Legend”
Added refering IO_Spirit_file version
–
Changes in chapter “Electrical Specification”
•
Changes in table “Absolute Maximum Ratings”
–
–
–
–
Changed description of parameter VIN
Changed description of parameter ∑IIN
Added footnote number to parameter IIN
Added footnote 5)
•
Changes in table “Slow 3.3V GPIO”
–
–
Added value and note for parameter RDSON
Changed notes of parameter IOZ
•
•
•
Changes in table “LVDS - IEEE standard LVDS general purpose link (GPL)”
Added notes to table “LVDS - IEEE standard LVDS general purpose link (GPL)”
Changes in table “OSC_XTAL”
Changed spelling in footnote 2)
Changes in table “Current Consumption”
Changed wording in footnote 6)
–
–
–
Data Sheet
476
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 0.7 to Version 1.0
•
Changes in table “Module Current Consumption”
–
–
Changed value and note of parameter TEXTLVDS
Added value and note of parameter TEXTLVDS
•
•
•
Changes in table “Reset”
Changed value for parameter tPIP
Changes in table “EVR33 LDO”
Added parameter dVOUTTC
Changes in table “Supply Monitors”
–
–
–
–
Changed notes for all values of parameter VEXTMON
Added values to parameter VEXTMON
•
Changes in table “EVRC SMPS”
–
–
–
Changed Controller Characteristics (CC) to System Requirements (SR) for parameter ∆fDCSPR
Changed Controller Characteristics (CC) to System Requirements (SR) for parameter nDC
Added values to parameter fDCDCSYNC
•
•
Changes in table “PLL System”
Changed value of parameter fREF
Changes in table “Flash”
–
–
–
Changed value of parameter tPRPB5_PF
Changed value of parameter tER-DEV
•
Changes in table “Package Parameters”
–
Changed value of parameter VHBM1
4.3
Changes from Version 0.7 to Version 1.0
Changes in chapter “Summary of Features”
Changed spelling in table "Platform Feature Overview"
Removed “ASIL” value from table “Platform Feature Overview”
Changes in chapter “TC36x Pin Definition and Functions”
Changes in sub-chapter "Bare Die Variant Pin Configuration of TC36x"
Deleted redundant sentence in explanation following table “Pad List” regarding neighbor pads
Changes in chapter “Electrical Specification”
•
–
•
–
•
Changes in sub-chapter “Absolute Maximum Ratings”
–
–
Changed wording for parameter VIN
Changed spelling in footnote 3)
•
•
Changes in sub-chapter “Pin Reliability in Overload”
Changed spelling for parameter IINSA in table “Overload Parameters”
Changes in sub-chapter “Operating Conditions”
–
–
–
Deleted parameter fADAS in table "Operating Conditions"
Changed values for parameter fGETH in table "Operating Conditions"
•
Changes in sub-chapter “5V / 3.3V switchable Pads”
–
–
Deleted value for parameter RDSON in table "Slow 5V GPIO"
Deleted value for parameter RDSON in table "Slow 3.3V GPIO"
Data Sheet
477
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 1.0 to Version 1.1
•
•
Changes in sub-chapter “High performance LVDS Pads”
–
–
–
Deleted value for parameter tfall20 in table "LVDS - IEEE standard LVDS general purpose link (GPL)"
Deleted footnote 2) for table "LVDS - IEEE standard LVDS general purpose link (GPL)"
Changed order of footnotes for table "LVDS - IEEE standard LVDS general purpose link (GPL)"
Changes in sub-chapter “VADC Parameters”
–
–
–
–
–
Deleted footnote 9) for parameter QCONV in table "VADC 5V"
Changed spelling for parameter dVCSD in table "VADC 5V"
Changed wording for footnote 7) for table "VADC 5V"
Changed footnote numbering for table "VADC 5V"
Changed figure "Equivalent Circuitry for Analog Inputs" for table "VADC 5V"
•
•
Changes in sub-chapter “MHz Oscillator”
Changed wording of footnote 1) for table "OSC_XTAL"
Changes in sub-chapter “Power Supply Current”
–
–
–
–
Changed value for parameter TEXTRAIL in table "Current Consumption"
Changed value for parameter TEVRSB in table "Current Consumption"
Changed value for parameter ISRCSB in table "Module Current Consumption"
•
•
Changes in sub-chapter “Reset Timing”
–
–
Changed spelling for parameter tEVRPOR in table "Reset"
Changed values for parameter tPI in table "Reset"
Changes in sub-chapter “EVR”
–
–
–
–
–
–
Changed Test Conditions for parameter VDDP3MON in table "Supply Monitors"
Changed Test Conditions for parameter VDDMON in table "Supply Monitors"
Changed Test Conditions for parameter tMON in table "Supply Monitors"
Changed spelling of footnote 2) for table "Supply Ramp"
Added description at table "Supply Ramp" regarding power cycles
Added values for parameter COUT in table "EVRC SMPS External components"
•
•
Changes in sub-chapter “ETH RGMII Parameters”
Deleted note for parameter t21 in table "ETH RGMII Signal Timing Parameters valid for 3.3V"
Changes in sub-chapter “Package Parameters”
–
–
Changed notes spelling in table "Package Parameters"
4.4
Changes from Version 1.0 to Version 1.1
•
Changes in chapter “Summary of Features”
–
–
–
–
–
–
Changed wording for “DFLASH”
Added description for “AEC-Q100”
Added description for “ISO 26262 Safety Element”
Added description for Data Flash in table “Platform Feature Overview”
Changed wording for Low Power Features in table “Platform Feature Overview”
•
Changes in chapter “TC36x Pin Definition and Functions”
Added notes to table “System I/O” for “LFBGA-292 Package Variant”
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Data Sheet
478
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 1.0 to Version 1.1
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Added notes to table “System I/O” for “LFBGA-180 Package Variant”
Added note to sub-chapter “LQFP-176 Package Variant”
Added notes to table “System I/O” for “LQFP-176 Package Variant”
Added note to sub-chapter “LQFP-144 Package Variant”
Added notes to table “System I/O” for “LQFP-144 Package Variant”
Added note to sub-chapter “TQFP-144 Package Variant”
Added notes to table “System I/O” for “TQFP-144 Package Variant”
Changed sub-chapter title from “Bare Die Variant Pin Configuration of TC36x” to “Sequence of Pads in Pad
Frame”
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Changes in chapter “Legend”
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Changed version number of “TC36xpd_IO_Spirit” file
Changes in chapter “Electrical Specification”
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Typos corrected in footnotes for sub-chapter “Absolute Maximum Ratings”
Changed note for parameter tTX_ASYM in table “Fast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Fast 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Slow 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Slow 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “RFast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “RFast 3.3V pad” of sub-chapter “5V/3.3V switchable Pads”
Typos corrected in footnote 2) for table “LVDS – IEEE standard LVDS general purpose link (GPL)” in sub-
chapter “High performance LVDS Pads”
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Added footnote content for table “LVDS – IEEE standard LVDS general purpose link (GPL)” in sub-chapter
“High performance LVDS Pads”
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Changed footnotes 3) and 6) for table “VADC 5V” in sub-chapter “VADC Parameters”
Changed value of parameter IRMS in table “DSADC 5V” in sub-chapter “DSADC Parameters”
Changed footnote 4) in sub-chapter “DSADC Parameters”
Added footnote 7) for parameter PD in table “Current Consumption” in sub-chapter “Power Supply Current”
Changed footnote 2) for table “Current Consumption” in sub-chapter “Power Supply Current”
Added footnote 7) for table “Current Consumption” in sub-chapter “Power Supply Current”
Added sentence to sub-chapter “Supply Ramp-up and Ramp-down Behavior”
Deleted value for parameter t52 in table “Master Mode Timing, LVDS output pads for data and clock” in sub-
chapter “QSPI Timings, Master and Slave Mode”
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Changed values (from Min. to Typ.) for parameter t7 in table “ETH MII Signal Timing Parameters” for sub-
chapter “ETH MII Parameters”
Changed symbols for parameters t13, t14, t15 in table “ETH RMII Signal Timing Parameters valid for 3.3V” in
sub-chapter “ETH RMII Parameters”
Changed value (from Min. to Typ.) for parameter t13 in table “ETH RMII Signal Timing Parameters valid for
3.3V” in sub-chapter “ETH RMII Parameters”
Added footnote 3) for parameters t16, t17 in table “ETH RMII Signal Timing Parameters valid for 3.3V” in
sub-chapter “ETH RMII Parameters”
Data Sheet
479
V 1.1, 2021-03
OPEN MARKET VERSION
TC36x AA-Step
History Changes from Version 1.0 to Version 1.1
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Added footnote 3) for table “ETH RMII Signal Timing Parameters valid for 3.3V” in sub-chapter “ETH RMII
Parameters”
Added tables for “Exposed Pad Dimensions” to sub-chapter “Package Outlines”
Data Sheet
480
V 1.1, 2021-03
OPEN MARKET VERSION
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