SAK-XC886CLM-6FFA3V3AC [INFINEON]
Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PQFP48,;
| 型号： | SAK-XC886CLM-6FFA3V3AC |
| 厂家： | 
Infineon |
| 描述： | Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PQFP48, 时钟 微控制器 |
| 文件： | 总144页 (文件大小：1455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit
XC886/888CLM
8-Bit Single Chip Microcontroller
Data Sheet
V1.2 2009-07
Microcontrollers
Edition 2009-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
8-Bit
XC886/888CLM
8-Bit Single Chip Microcontroller
Data Sheet
V1.2 2009-07
Microcontrollers
XC886/888CLM
XC886/888 Data Sheet
Revision History: V1.2 2009-07
Previous Versions: V1.0, V1.1
Page
Subjects (major changes since last revision)
Changes from V1.1 2009-01 to V1.2 2009-07
89
Note on LIN baud rate detection is added.
92
RXD slave line in SSC block diagram is updated.
108
Electrical parameters are now valid for all variants, previous note on
exclusion of ROM variants is removed.
116
120
128
Symbol for ADC error parameters are updated.
Power supply current parameters for ROM variants are updated.
Test condition for the on-chip oscillator short term deviation is updated.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet
V1.2, 2009-07
XC886/888CLM
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
XC886/888 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Parallel Read Access of P-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash Programming Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.1
3.2
3.2.1
3.2.1.1
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.3.1
3.2.4
3.2.4.1
3.2.4.2
3.2.4.3
3.2.4.4
3.2.4.5
3.2.4.6
3.2.4.7
3.2.4.8
3.2.4.9
3.2.4.10
3.2.4.11
3.2.4.12
3.2.4.13
3.2.4.14
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
Data Sheet
I-1
V1.2, 2009-07
XC886/888CLM
Table of Contents
3.6
Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . 68
Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 75
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 88
LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 91
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.7
3.7.1
3.7.2
3.8
3.8.1
3.8.2
3.9
3.10
3.11
3.12
3.13
3.13.1
3.13.2
3.14
3.15
3.15.1
3.16
3.17
3.18
3.19
3.20
3.21
3.21.1
3.21.2
3.22
3.22.1
3.23
4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.1
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.2.3
4.2.3.1
4.2.4
4.3
4.3.1
4.3.2
Data Sheet
I-2
V1.2, 2009-07
XC886/888CLM
Table of Contents
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5
Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.1
5.2
5.3
Data Sheet
I-3
V1.2, 2009-07
8-Bit Single Chip Microcontroller
XC886/888CLM
1
Summary of Features
The XC886/888 has the following features:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 12 Kbytes of Boot ROM
– 256 bytes of RAM
– 1.5 Kbytes of XRAM
– 24/32 Kbytes of Flash; or
24/32 Kbytes of ROM, with additional 4 Kbytes of Flash
(includes memory protection strategy)
• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)
(more features on next page)
Flash or ROM1)
On-Chip Debug Support
XC800 Core
UART
SSC
Port 0
Port 1
Port 2
Port 3
Port 4
8-bit Digital I/O
8-bit Digital I/O
24K/32K x 8
Boot ROM
12K x 8
Capture/Compare Unit
16-bit
.
XRAM
Compare Unit
16-bit
8-bit Digital/
Analog Input
1.5K x 8
ADC
Watchdog
10-bit
RAM
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
8-bit Digital I/O
8-bit Digital I/O
256 x 8
Timer
8-channel
Timer 21
16-bit
MDU
CORDIC
MultiCAN
UART1
Port 5
8-bit Digital I/O
1) All ROM devices come with an additional 4K x 8 Flash
Figure 1
XC886/888 Functional Units
Data Sheet
1
V1.2, 2009-07
XC886/888CLM
Summary of Features
Features: (continued)
• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Six ports
– Up to 48 pins as digital I/O
– 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Four 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 and Timer 21 (T2 and T21)
• Multiplication/Division Unit for arithmetic operations (MDU)
• Software libraries to support floating point and MDU calculations
• CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear
functions
• MultiCAN with 2 nodes, 32 message objects
• Capture/compare unit for PWM signal generation (CCU6)
• Two full-duplex serial interfaces (UART and UART1)
• Synchronous serial channel (SSC)
• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM)
– 64 bytes of monitor RAM
• Packages:
– PG-TQFP-48
– PG-TQFP-64
• Temperature range TA:
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
Data Sheet
2
V1.2, 2009-07
XC886/888CLM
Summary of Features
XC886/888 Variant Devices
The XC886/888 product family features devices with different configurations, program
memory sizes, package options, power supply voltage, temperature and quality profiles
(Automotive or Industrial), to offer cost-effective solutions for different application
requirements.
The list of XC886/888 device configurations are summarized in Table 1. For each
configuration, 2 types of packages are available:
• PG-TQFP-48, which is denoted by XC886 and;
• PG-TQFP-64, which is denoted by XC888.
Table 1
Device Configuration
Device Name
CAN
LIN BSL
Support
MDU
Module
Module
XC886/888
No
No
No
XC886/888C
XC886/888CM
XC886/888LM
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
XC886/888CLM
Yes
Note: For variants with LIN BSL support, only LIN BSL is available regardless of the
availability of the CAN module.
From these 10 different combinations of configuration and package type, each are
further made available in many sales types, which are grouped according to device type,
program memory sizes, power supply voltage, temperature and quality profile
(Automotive or Industrial), as shown in Table 2.
Table 2
Device Profile
Sales Type
Device Program Power Temp-
Type Memory Supply erature
(Kbytes) (V) (°C)
Quality
Profile
SAK-XC886*/888*-8FFA 5V Flash 32
SAK-XC886*/888*-6FFA 5V Flash 24
SAF-XC886*/888*-8FFA 5V Flash 32
SAF-XC886*/888*-6FFA 5V Flash 24
5.0
5.0
5.0
5.0
5.0
5.0
-40 to 125 Automotive
-40 to 125 Automotive
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Automotive
Automotive
Industrial
SAF-XC886*/888*-8FFI 5V
SAF-XC886*/888*-6FFI 5V
Flash 32
Flash 24
Industrial
Data Sheet
3
V1.2, 2009-07
XC886/888CLM
Summary of Features
Table 2
Device Profile (cont’d)
Sales Type
Device Program Power Temp-
Quality
Profile
Type
Memory Supply erature
(Kbytes) (V) (°C)
SAK-XC886*/888*-8FFA 3V3 Flash 32
SAK-XC886*/888*-6FFA 3V3 Flash 24
SAF-XC886*/888*-8FFA 3V3 Flash 32
SAF-XC886*/888*-6FFA 3V3 Flash 24
SAF-XC886*/888*-8FFI 3V3 Flash 32
SAF-XC886*/888*-6FFI 3V3 Flash 24
3.3
3.3
3.3
3.3
3.3
3.3
-40 to 125 Automotive
-40 to 125 Automotive
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Automotive
Automotive
Industrial
Industrial
Note: The asterisk (*) above denotes the device configuration letters from Table 1.
Corresponding ROM derivatives will be available on request.
Note: For variants with LIN BSL support, only LIN BSL is available regardless of the
availability of the CAN module.
As this document refers to all the derivatives, some description may not apply to a
specific product. For simplicity, all versions are referred to by the term XC886/888
throughout this document.
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
• The package and the type of delivery
For the available ordering codes for the XC886/888, please refer to your responsible
sales representative or your local distributor.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
4
V1.2, 2009-07
XC886/888CLM
General Device Information
2
General Device Information
Chapter 2 contains the block diagram, pin configurations, definitions and functions of the
XC886/888.
2.1
Block Diagram
The block diagram of the XC886/888 is shown in Figure 2.
XC886/888
Internal Bus
12-Kbyte
Boot ROM1)
XC800 Core
P0.0 - P0.7
P1.0 - P1.7
P2.0 - P2.7
256-byte RAM
+
T0 & T1
UART
64-byte monitor
RAM
TMS
MBC
RESET
VDDP
CORDIC
MDU
UART1
SSC
1.5-Kbyte XRAM
VSSP
VDDC
VSSC
24/32-Kbyte
Flash or ROM2)
WDT
Timer 2
Timer 21
CCU6
VAREF
VAGND
ADC
Clock Generator
XTAL1
XTAL2
OCDS
9.6 MHz
On-chip OSC
P3.0 - P3.7
P4.0 - P4.7
P5.0 - P5.7
PLL
MultiCAN
1) Includes 1-Kbyte monitor ROM
2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash
Figure 2
XC886/888 Block Diagram
Data Sheet
5
V1.2, 2009-07
XC886/888CLM
General Device Information
2.2
Logic Symbol
The logic symbols of the XC886/888 are shown in Figure 3.
VDDP
VSSP
VDDP
VSSP
Port 0 8-Bit
Port 1 8-Bit
Port 2 8-Bit
Port 3 8-Bit
Port 4 8-Bit
Port 5 8-Bit
VAREF
VAGND
VAREF
VAGND
Port 0 7-Bit
Port 1 8-Bit
Port 2 8-Bit
Port 3 8-Bit
Port 4 3-Bit
RESET
MBC
RESET
MBC
XC886
XC888
TMS
TMS
XTAL1
XTAL2
XTAL1
XTAL2
VDDC
VSSC
VDDC
VSSC
Figure 3
XC886/888 Logic Symbol
Data Sheet
6
V1.2, 2009-07
XC886/888CLM
General Device Information
2.3
Pin Configuration
The pin configuration of the XC886, which is based on the PG-TQFP-48 package, is
shown in Figure 4, while that of the XC888, which is based on the PG-TQFP-64
package, is shown in Figure 5.
36 35 34 33 32 31 30 29 28 27 26 25
P3.2
P3.3
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VAREF
VAGND
P2.6
P3.4
P3.5
P2.5
RESET
VSSP
VDDP
MBC
P4.0
P2.4
P2.3
XC886
VSSP
VDDP
P2.2
P2.
P4.1
1
P0.7
P2.0
P0.1
P0.3
1
2
3
4 5
6
7
8
9 10 11 12
Figure 4
XC886 Pin Configuration, PG-TQFP-48 Package (top view)
Data Sheet
7
V1.2, 2009-07
XC886/888CLM
General Device Information
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P3.2
P3.3
P3.4
P3.5
RESET
VSSP
VDDP
NC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VAREF
VAGND
P2.6
P2.5
P2.4
P2.3
VSSP
VDDP
P2.2
XC888
NC
P2.
MBC
P4.0
P4.1
P4.2
P0.7
P0.3
P0.4
1
P2.0
P0.1
P5.7
P5.6
P0.2
P0.0
1
2
3
4 5
6
7
8
9 10 11 12 13 14 15 16
Note: The pins shaded in blue are not available in the PG-TQFP-48 package.
Figure 5
XC888 Pin Configuration, PG-TQFP-64 Package (top view)
Data Sheet
8
V1.2, 2009-07
XC886/888CLM
General Device Information
2.4
Pin Definitions and Functions
The functions and default states of the XC886/888 external pins are provided in Table 3.
Table 3 Pin Definitions and Functions
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P0
I/O
Port 0
Port 0 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, UART1, Timer 2,
Timer 21, MultiCAN and SSC.
P0.0
11/17
Hi-Z
TCK_0
JTAG Clock Input
CCU6 Timer 12 Hardware Run
Input
T12HR_1
CC61_1
Input/Output of
Capture/Compare channel 1
CLKOUT_0 Clock Output
RXDO_1
UART Transmit Data Output
P0.1
13/21
Hi-Z
TDI_0
JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
T13HR_1
RXD_1
RXDC1_0
UART Receive Data Input
MultiCAN Node 1 Receiver Input
COUT61_1 Output of Capture/Compare
channel 1
EXF2_1
Timer 2 External Flag Output
P0.2
P0.3
12/18
48/63
PU
CTRAP_2
TDO_0
CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Data
Output/Clock Output
MultiCAN Node 1 Transmitter
Output
TXD_1
TXDC1_0
Hi-Z
SCK_1
SSC Clock Input/Output
COUT63_1 Output of Capture/Compare
channel 3
RXDO1_0
UART1 Transmit Data Output
Data Sheet
9
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P0.4
1/64
Hi-Z
MTSR_1
CC62_1
TXD1_0
SSC Master Transmit Output/
Slave Receive Input
Input/Output of
Capture/Compare channel 2
UART1 Transmit Data
Output/Clock Output
P0.5
2/1
Hi-Z
MRST_1
SSC Master Receive Input/Slave
Transmit Output
EXINT0_0 External Interrupt Input 0
T2EX1_1
RXD1_0
Timer 21 External Trigger Input
UART1 Receive Data Input
COUT62_1 Output of Capture/Compare
channel 2
P0.6
P0.7
–/2
47/62
PU
PU
GPIO
CLKOUT_1 Clock Output
Data Sheet
10
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P1
I/O
Port 1
Port 1 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, Timer 0, Timer 1,
Timer 2, Timer 21, MultiCAN and SSC.
P1.0
P1.1
26/34
27/35
PU
PU
RXD_0
T2EX
UART Receive Data Input
Timer 2 External Trigger Input
MultiCAN Node 0 Receiver Input
RXDC0_0
EXINT3
T0_1
TDO_1
TXD_0
External Interrupt Input 3
Timer 0 Input
JTAG Serial Data Output
UART Transmit Data
Output/Clock Output
MultiCAN Node 0 Transmitter
Output
TXDC0_0
P1.2
P1.3
28/36
29/37
PU
PU
SCK_0
MTSR_0
SSC Clock Input/Output
SSC Master Transmit
Output/Slave Receive Input
MultiCAN Node 1 Transmitter
Output
SSC Master Receive Input/
Slave Transmit Output
TXDC1_3
MRST_0
P1.4
P1.5
30/38
31/39
PU
PU
EXINT0_1 External Interrupt Input 0
RXDC1_3
CCPOS0_1 CCU6 Hall Input 0
EXINT5
T1_1
EXF2_0
RXDO_0
MultiCAN Node 1 Receiver Input
External Interrupt Input 5
Timer 1 Input
Timer 2 External Flag Output
UART Transmit Data Output
Data Sheet
11
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P1.6
8/10
PU
CCPOS1_1 CCU6 Hall Input 1
T12HR_0
CCU6 Timer 12 Hardware Run
Input
EXINT6_0 External Interrupt Input 6
RXDC0_2
T21_1
MultiCAN Node 0 Receiver Input
Timer 21 Input
P1.7
9/11
PU
CCPOS2_1 CCU6 Hall Input 2
T13HR_0
CCU6 Timer 13 Hardware Run
Input
Timer 2 Input
T2_1
TXDC0_2
MultiCAN Node 0 Transmitter
Output
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
Data Sheet
12
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P2
I
Port 2
Port 2 is an 8-bit general purpose input-only
port. It can be used as alternate functions for
the digital inputs of the JTAG and CCU6. It is
also used as the analog inputs for the ADC.
P2.0
14/22
Hi-Z
CCPOS0_0 CCU6 Hall Input 0
EXINT1_0 External Interrupt Input 1
T12HR_2
CCU6 Timer 12 Hardware Run
Input
JTAG Clock Input
Input of Capture/Compare
channel 1
TCK_1
CC61_3
AN0
Analog Input 0
P2.1
P2.2
15/23
16/24
Hi-Z
Hi-Z
CCPOS1_0 CCU6 Hall Input 1
EXINT2_0 External Interrupt Input 2
T13HR_2
CCU6 Timer 13 Hardware Run
Input
TDI_1
CC62_3
JTAG Serial Data Input
Input of Capture/Compare
channel 2
AN1
Analog Input 1
CCPOS2_0 CCU6 Hall Input 2
CTRAP_1
CC60_3
CCU6 Trap Input
Input of Capture/Compare
channel 0
AN2
AN3
AN4
AN5
AN6
AN7
Analog Input 2
P2.3
P2.4
P2.5
P2.6
P2.7
19/27
20/28
21/29
22/30
25/33
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Analog Input 3
Analog Input 4
Analog Input 5
Analog Input 6
Analog Input 7
Data Sheet
13
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P3
I/O
Port 3
Port 3 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, UART1, Timer 21 and MultiCAN.
P3.0
P3.1
35/43
36/44
Hi-Z
Hi-Z
CCPOS1_2 CCU6 Hall Input 1
CC60_0
Input/Output of
Capture/Compare channel 0
UART1 Transmit Data Output
RXDO1_1
CCPOS0_2 CCU6 Hall Input 0
CC61_2
Input/Output of
Capture/Compare channel 1
COUT60_0 Output of Capture/Compare
channel 0
TXD1_1
UART1 Transmit Data
Output/Clock Output
P3.2
37/49
Hi-Z
CCPOS2_2 CCU6 Hall Input 2
RXDC1_1
RXD1_1
CC61_0
MultiCAN Node 1 Receiver Input
UART1 Receive Data Input
Input/Output of
Capture/Compare channel 1
P3.3
P3.4
P3.5
38/50
39/51
40/52
Hi-Z
Hi-Z
Hi-Z
COUT61_0 Output of Capture/Compare
channel 1
TXDC1_1
MultiCAN Node 1 Transmitter
Output
CC62_0
Input/Output of
Capture/Compare channel 2
MultiCAN Node 0 Receiver Input
Timer 21 External Trigger Input
RXDC0_1
T2EX1_0
COUT62_0 Output of Capture/Compare
channel 2
EXF21_0
TXDC0_1
Timer 21 External Flag Output
MultiCAN Node 0 Transmitter
Output
P3.6
33/41
PD
CTRAP_0
14
CCU6 Trap Input
Data Sheet
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P3.7
34/42
Hi-Z
EXINT4
External Interrupt Input 4
COUT63_0 Output of Capture/Compare
channel 3
Data Sheet
15
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P4
I/O
Port 4
Port 4 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, Timer 0, Timer 1, Timer 21 and
MultiCAN.
P4.0
P4.1
45/59
46/60
Hi-Z
Hi-Z
RXDC0_3
CC60_1
MultiCAN Node 0 Receiver Input
Output of Capture/Compare
channel 0
MultiCAN Node 0 Transmitter
Output
TXDC0_3
COUT60_1 Output of Capture/Compare
channel 0
P4.2
P4.3
–/61
PU
EXINT6_1 External Interrupt Input 6
T21_0
Timer 21 Input
32/40
Hi-Z
EXF21_1
Timer 21 External Flag Output
COUT63_2 Output of Capture/Compare
channel 3
P4.4
P4.5
P4.6
P4.7
–/45
–/46
–/47
–/48
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CCPOS0_3 CCU6 Hall Input 0
T0_0
Timer 0 Input
CC61_4
Output of Capture/Compare
channel 1
CCPOS1_3 CCU6 Hall Input 1
T1_0
Timer 1 Input
COUT61_2 Output of Capture/Compare
channel 1
CCPOS2_3 CCU6 Hall Input 2
T2_0
CC62_2
Timer 2 Input
Output of Capture/Compare
channel 2
CTRAP_3
CCU6 Trap Input
COUT62_2 Output of Capture/Compare
channel 2
Data Sheet
16
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P5
I/O
Port 5
Port 5 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART, UART1 and JTAG.
P5.0
P5.1
P5.2
P5.3
–/8
–/9
–/12
–/13
PU
PU
PU
PU
EXINT1_1 External Interrupt Input 1
EXINT2_1 External Interrupt Input 2
RXD_2
TXD_2
UART Receive Data Input
UART Transmit Data
Output/Clock Output
P5.4
P5.5
–/14
–/15
PU
PU
RXDO_2
TDO_2
TXD1_2
UART Transmit Data Output
JTAG Serial Data Output
UART1 Transmit Data Output/
Clock Output
P5.6
P5.7
–/19
–/20
PU
PU
TCK_2
JTAG Clock Input
RXDO1_2
UART1 Transmit Data Output
TDI_2
RXD1_2
JTAG Serial Data Input
UART1 Receive Data Input
Data Sheet
17
V1.2, 2009-07
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
VDDP
7, 17, 43/
7, 25, 55
–
–
I/O Port Supply (3.3 or 5.0 V)
Also used by EVR and analog modules. All
pins must be connected.
VSSP
18, 42/26, 54 –
–
I/O Port Ground
All pins must be connected.
VDDC
VSSC
VAREF
VAGND
6/6
5/5
24/32
23/31
–
–
–
–
I
–
–
–
–
Core Supply Monitor (2.5 V)
Core Supply Ground
ADC Reference Voltage
ADC Reference Ground
XTAL1 4/4
Hi-Z
External Oscillator Input
(backup for on-chip OSC, normally NC)
XTAL2 3/3
O
Hi-Z
External Oscillator Output
(backup for on-chip OSC, normally NC)
TMS
10/16
I
I
I
–
PD
PU
PU
–
Test Mode Select
Reset Input
Monitor & BootStrap Loader Control
No Connection
RESET 41/53
MBC1) 44/58
NC
–/56, 57
1) An external pull-up device in the range of 4.7 kΩ to 100 kΩ. is required to enter user mode. Alternatively MBC
can be tied to high if alternate functions (for debugging) of the pin are not utilized.
Data Sheet
18
V1.2, 2009-07
XC886/888CLM
Functional Description
3
Functional Description
Chapter 3 provides an overview of the XC886/888 functional description.
3.1
Processor Architecture
The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU)
that is compatible with the standard 8051 processor. While the standard 8051 processor
is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock
machine cycle. This allows fast access to ROM or RAM memories without wait state.
Access to the Flash memory, however, requires an additional wait state (one machine
cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte
instructions.
The XC886/888 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and Special Function Registers (SFRs).
Figure 6 shows the CPU functional blocks.
Internal Data
Memory
Core SFRs
Register Interface
External Data
Memory
External SFRs
16-bit Registers &
Memory Interface
ALU
Program Memory
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
UART
fCCLK
Memory Wait
Reset
State Machine &
Power Saving
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Interrupt
Controller
Non-Maskable Interrupt
Figure 6
CPU Block Diagram
Data Sheet
19
V1.2, 2009-07
XC886/888CLM
Functional Description
3.2
Memory Organization
The XC886/888 CPU operates in the following five address spaces:
• 12 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 1.5 Kbytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
• A 128-byte Special Function Register area
• 24/32 Kbytes of Flash program memory (Flash devices); or
24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash
(ROM devices)
Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the
24-Kbyte Flash devices, the shaded banks are not available.
FFFFH
F600H
FFFFH
F600H
1)
In 24-Kbyte Flash devices, the upper 2-
Kbyte of Banks 4 and 5 are not available.
XRAM
XRAM
1.5 Kbytes
1.5 Kbytes
F000H
F000H
Boot ROM
12 Kbytes
C000H
B000H
A000H
D-Flash Bank 1
4 Kbytes
D-Flash Bank 0
4 Kbytes
8000
H
D-Flash Bank 0
4 Kbytes
7000
H
D-Flash Bank 1
4 Kbytes
6000
H
Indirect
Direct
P-Flash Banks 4 and 5
2 x 4 Kbytes1)
Address
Address
5000
H
FFH
4000
H
Special Function
Registers
Internal RAM
P-Flash Banks 2 and 3
2 x 4 Kbytes
80H
2000
H
7FH
00H
P-Flash Banks 0 and 1
2 x 4 Kbytes
Internal RAM
0000
0000H
H
Program Space
External Data Space
Internal Data Space
Figure 7
Memory Map of XC886/888 Flash Device
For both 24-Kbyte and 32-Kbyte ROM devices, the last four bytes of the ROM from
7FFCH to 7FFFH are reserved for the ROM signature and cannot be used to store user
Data Sheet
20
V1.2, 2009-07
XC886/888CLM
Functional Description
code or data. Therefore, even though the ROM device contains either a 24-Kbyte or 32-
Kbyte ROM, the maximum size of code that can be placed in the ROM is the given size
less four bytes.
3.2.1
Memory Protection Strategy
The XC886/888 memory protection strategy includes:
• Read-out protection: The user is able to protect the contents in the Flash (for Flash
devices) and ROM (for ROM devices) memory from being read
– Flash protection is enabled by programming a valid password (8-bit non-zero
value) via BSL mode 6.
– ROM protection is fixed with the ROM mask and is always enabled.
• Flash program and erase protection: This feature is available only for Flash devices.
3.2.1.1 Flash Memory Protection
As long as a valid password is available, all external access to the device, including the
Flash, will be blocked.
For additional security, the Flash hardware protection can be enabled to implement a
second layer of read-out protection, as well as to enable program and erase protection.
Flash hardware protection is available only for Flash devices and comes in two modes:
• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 4.
Table 4
Flash Protection Modes
Flash Protection Without hardware
With hardware protection
protection
Hardware
-
0
1
Protection Mode
Activation
Selection
Program a valid password via BSL mode 6
Bit 4 of password = 0 Bit 4 of password = 1 Bit 4 of password = 1
MSB of password = 0 MSB of password = 1
P-Flash
Read instructions in Read instructions in Read instructions in
contents can be any program memory the P-Flash
the P-Flash or D-
Flash
read by
External access Not possible
Not possible
Not possible
to P-Flash
Data Sheet
21
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 4
Flash Protection Modes (cont’d)
Flash Protection Without hardware
With hardware protection
protection
P-Flashprogram Possible
Not possible Not possible
and erase
D-Flash
Read instructions in Read instructions in Read instructions in
contents can be any program memory any program memory the P-Flash or D-
read by
Flash
External access Not possible
Not possible
Possible
Not possible
to D-Flash
D-Flash
Possible
Possible
Not possible
Not possible
program
D-Flash erase
Possible, on
condition that bit
DFLASHEN in
register MISC_CON
is set to 1 prior to
each erase operation
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. A
password match triggers an automatic erase of the protected P-Flash and D-Flash
contents, including the programmed password. The Flash protection is then disabled
upon the next reset.
For the ROM device, the ROM is protected at all times and BSL mode 6 is used only to
block external access to the device. However, unlike the Flash device, it is not possible
to disable the memory protection of the ROM device. Here, entering BSL mode 6 will
result in a protection error.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Although no protection scheme can be considered infallible, the XC886/888 memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Data Sheet
22
V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.2
Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
• Mapping
• Paging
3.2.2.1 Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number of
addressable SFRs to 256. The extended address range is not directly controlled by the
CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
Data Sheet
23
V1.2, 2009-07
XC886/888CLM
Functional Description
Standard Area (RMAP = 0)
FFH
Module 1 SFRs
SYSCON0.RMAP
Module 2 SFRs
rw
Module n SFRs
80H
FFH
SFR Data
(to/from CPU)
Mapped Area (RMAP = 1)
Module (n+1) SFRs
Module (n+2) SFRs
Module m SFRs
80H
Direct
Internal Data
Memory Address
Figure 8
Address Extension by Mapping
Data Sheet
24
V1.2, 2009-07
XC886/888CLM
Functional Description
SYSCON0
System Control Register 0
Reset Value: 04H
7
6
5
4
3
2
1
0
0
IMODE
0
1
0
RMAP
r
rw
r
r
r
rw
Field
Bits
Type Description
RMAP
0
rw
Interrupt Node XINTR0 Enable
0
The access to the standard SFR area is
enabled
1
The access to the mapped SFR area is
enabled
1
0
2
r
r
Reserved
Returns 1 if read; should be written with 1.
[7:5],
3,1
Reserved
Returns 0 if read; should be written with 0.
Note: The RMAP bit should be cleared/set by ANL or ORL instructions.
3.2.2.2 Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC886/888 has a 256-SFR address range. However, this is
still less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 9.
Data Sheet
25
V1.2, 2009-07
XC886/888CLM
Functional Description
SFR Address
(from CPU)
PAGE 0
MOD_PAGE.PAGE
SFR0
SFR1
rw
SFRx
PAGE 1
SFR0
SFR1
SFR Data
(to/from CPU)
SFRy
PAGE q
SFR0
SFR1
SFRz
Module
Figure 9
Address Extension by Paging
In order to access a register located in a page different from the actual one, the current
page must be exited. This is done by reprogramming the bit field PAGE in the page
register. Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and the old page setting
restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore
action of the current page setting. By indicating which storage bit field should be used in
parallel with the new page value, a single write operation can:
• Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
Data Sheet
26
V1.2, 2009-07
XC886/888CLM
Functional Description
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written
to the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
PAGE
value update
from CPU
Figure 10
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC886/888 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers
Data Sheet
27
V1.2, 2009-07
XC886/888CLM
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
Reset Value: 00H
7
6
5
4
3
2
1
0
OP
STNR
0
PAGE
w
w
r
rw
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
Data Sheet
28
V1.2, 2009-07
XC886/888CLM
Functional Description
Field
OP
Bits
[7:6]
Type Description
w Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
3.2.3
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the
bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit
field PASS closes access to writing of all protected bits. In both cases, the value of the
bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can
only be changed when bit field PASS is written with 11000B, for example, writing D0H to
PASSWD register disables the bit protection scheme.
Note that access is opened for maximum 32 CCLKs if the “close access” password is not
written. If “open access” password is written again before the end of 32 CCLK cycles,
there will be a recount of 32 CCLK cycles. The protected bits include the N- and K-
Divider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the power-
down and slow-down enable bits, PD and SD.
Data Sheet
29
V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.3.1 Password Register
PASSWD
Password Register
Reset Value: 07H
7
6
5
4
3
2
1
0
PROTECT
_S
PASS
MODE
wh
rh
rw
Field
Bits
Type Description
MODE
[1:0]
rw
Bit Protection Scheme Control Bits
00
Scheme disabled - direct access to the
protected bits is allowed.
11
Scheme enabled - the bit field PASS has to be
written with the passwords to open and close
the access to protected bits. (default)
Others:Scheme Enabled.
These two bits cannot be written directly. To change
the value between 11B and 00B, the bit field PASS
must be written with 11000B; only then, will the
MODE[1:0] be registered.
PROTECT_S
PASS
2
rh
Bit Protection Signal Status Bit
This bit shows the status of the protection.
0
1
Software is able to write to all protected bits.
Software is unable to write to any protected
bits.
[7:3]
wh
Password Bits
The Bit Protection Scheme only recognizes three
patterns.
11000B Enables writing of the bit field MODE.
10011B Opens access to writing of all protected bits.
10101B Closes access to writing of all protected bits
Data Sheet
30
V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.4
XC886/888 Register Overview
The SFRs of the XC886/888 are organized into groups according to their functional units.
The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.14.
Note: The addresses of the bitaddressable SFRs appear in bold typeface.
3.2.4.1 CPU Registers
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 5
CPU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
81
82
83
87
88
89
SP
Reset: 07
Bit Field
Type
SP
rw
H
H
H
H
H
H
H
H
H
H
H
H
Stack Pointer Register
DPL
Reset: 00
Bit Field
Type
DPL7
rw
DPL6
rw
DPL5
rw
DPL4
rw
DPL3
rw
DPL2
rw
DPL1
rw
DPL0
rw
Data Pointer Register Low
DPH
Reset: 00
Bit Field DPH7
Type rw
Bit Field SMOD
DPH6
rw
DPH5
rw
DPH4
rw
DPH3
rw
DPH2
rw
DPH1
rw
DPH0
rw
Data Pointer Register High
PCON
Reset: 00
0
GF1
rw
GF0
rw
0
IDLE
rw
Power Control Register
Type
rw
r
r
TCON
Reset: 00
Bit Field
Type
TF1
rwh
TR1
rw
TF0
rwh
TR0
rw
IE1
IT1
IE0
rwh
IT0
Timer Control Register
rwh
rw
rw
TMOD
Reset: 00
Bit Field GATE
1
T1S
T1M
rw
GATE
0
T0S
T0M
rw
Timer Mode Register
Type
rw
rw
rw
rw
8A
8B
TL0
Reset: 00
Bit Field
Type
VAL
rwh
VAL
rwh
VAL
rwh
VAL
rwh
H
H
H
H
H
H
Timer 0 Register Low
TL1
Reset: 00
Bit Field
Type
H
Timer 1 Register Low
8C
8D
98
TH0
Reset: 00
Bit Field
Type
H
Timer 0 Register High
TH1
Reset: 00
Bit Field
Type
H
Timer 1 Register High
SCON
Reset: 00
Bit Field
Type
SM0
rw
SM1
rw
SM2
rw
REN
rw
TB8
rw
RB8
rwh
TI
RI
H
Serial Channel Control Register
rwh
rwh
99
SBUF
Reset: 00
Bit Field
Type
VAL
rwh
H
H
H
Serial Data Buffer Register
A2
EO
Reset: 00
Bit Field
0
r
TRAP_
EN
0
r
DPSE
L0
H
Extended Operation Register
Type
rw
rw
Data Sheet
31
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 5
CPU Register Overview (cont’d)
Addr Register Name
Bit
Bit Field
7
EA
6
0
r
5
ET2
rw
4
ES
3
ET1
rw
2
EX1
rw
1
ET0
rw
0
EX0
rw
A8
B8
B9
IEN0
Reset: 00
H
H
H
H
H
Interrupt Enable Register 0
Type
rw
rw
IP
Reset: 00
Bit Field
Type
0
r
PT2
rw
PS
PT1
rw
PX1
rw
PT0
rw
PX0
rw
Interrupt Priority Register
rw
IPH
Reset: 00
Bit Field
Type
0
r
PT2H
rw
PSH
rw
PT1H
rw
PX1H
rw
PT0H
rw
PX0H
rw
H
Interrupt Priority High Register
D0
PSW
Reset: 00
Bit Field
Type
CY
AC
rwh
F0
RS1
rw
RS0
rw
OV
F1
P
H
H
H
H
Program Status Word Register
rwh
rw
rwh
ACC2
rw
rw
rh
E0
E8
ACC
Reset: 00
Bit Field ACC7
Type rw
ACC6
rw
ACC5
rw
ACC4
rw
ACC3
rw
ACC1
rw
ACC0
rw
H
H
Accumulator Register
IEN1
Reset: 00
Bit Field ECCIP ECCIP ECCIP ECCIP
EXM
EX2
ESSC
EADC
Interrupt Enable Register 1
3
2
1
0
Type
rw
B7
rw
rw
B6
rw
rw
B5
rw
rw
B4
rw
rw
B3
rw
B2
rw
B1
rw
B0
F0
B
Reset: 00
Reset: 00
Bit Field
Type
H
H
H
B Register
rw
rw
rw
rw
F8
IP1
Bit Field PCCIP PCCIP PCCIP PCCIP
PXM
PX2
PSSC
PADC
H
Interrupt Priority 1 Register
3
2
1
0
Type
rw
rw
rw
rw
rw
rw
rw
rw
F9
IPH1
Reset: 00
Bit Field PCCIP PCCIP PCCIP PCCIP PXMH
PX2H
PSSC
H
PADC
H
H
H
Interrupt Priority 1 High Register
3H
rw
2H
rw
1H
rw
0H
rw
Type
rw
rw
rw
rw
3.2.4.2 MDU Registers
The MDU SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6 MDU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
B0
MDUSTAT
Reset: 00
Bit Field
Type
0
r
BSY
rh
IERR
rwh
IRDY
rwh
H
H
MDU Status Register
B1
MDUCON
Reset: 00
Bit Field
IE
IR
rw
RSEL
STAR
T
OPCODE
H
H
MDU Control Register
Type
rw
rw
rwh
rw
B2
B2
B3
MD0
Reset: 00
Bit Field
Type
DATA
H
H
H
H
H
H
MDU Operand Register 0
rw
DATA
rh
MR0
Reset: 00
Bit Field
Type
MDU Result Register 0
MD1
Reset: 00
Bit Field
Type
DATA
rw
MDU Operand Register 1
Data Sheet
32
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 6
MDU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
B3
B4
B4
B5
B5
B6
B6
B7
B7
MR1
Reset: 00
Bit Field
DATA
rh
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
MDU Result Register 1
Type
MD2
Reset: 00
Bit Field
Type
DATA
rw
MDU Operand Register 2
MR2
Reset: 00
Bit Field
Type
DATA
rh
MDU Result Register 2
MD3
Reset: 00
Bit Field
Type
DATA
rw
MDU Operand Register 3
MR3
Reset: 00
Bit Field
Type
DATA
rh
MDU Result Register 3
MD4
Reset: 00
Bit Field
Type
DATA
rw
MDU Operand Register 4
MR4
Reset: 00
Bit Field
Type
DATA
rh
MDU Result Register 4
MD5
Reset: 00
Bit Field
Type
DATA
rw
MDU Operand Register 5
MR5
Reset: 00
Bit Field
Type
DATA
rh
MDU Result Register 5
3.2.4.3 CORDIC Registers
The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 7 CORDIC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
9A
CD_CORDXL
Reset: 00
Bit Field
Type
DATAL
rw
H
H
H
H
H
H
H
H
CORDIC X Data Low Byte
9B
CD_CORDXH
Reset: 00
Bit Field
Type
DATAH
rw
CORDIC X Data High Byte
9C
9D
9E
CD_CORDYL
Reset: 00
Bit Field
Type
DATAL
rw
H
H
CORDIC Y Data Low Byte
CD_CORDYH
Reset: 00
Bit Field
Type
DATAH
rw
CORDIC Y Data High Byte
CD_CORDZL
Reset: 00
Bit Field
Type
DATAL
rw
H
H
CORDIC Z Data Low Byte
9F
CD_CORDZH
Reset: 00
Bit Field
Type
DATAH
rw
CORDIC Z Data High Byte
Data Sheet
33
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 7
CORDIC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
A0
CD_STATC
Reset: 00
Bit Field KEEP
KEEP
KEEP DMAP INT_E
EOC
ERRO
BSY
H
H
CORDIC Status and Data
Control Register
Z
Y
X
N
R
Type
rw
rw
rw
rw
rw
rwh
rh
rh
A1
CD_CON
Reset: 00
Bit Field
MPS
rw
X_USI ST_M
ROTV
EC
MODE
ST
H
H
CORDIC Control Register
GN
rw
ODE
rw
Type
rw
rw
rwh
3.2.4.4 System Control Registers
The system control SFRs can be accessed in the mapped memory area (RMAP = 0).
Table 8 SCU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
8F
SYSCON0
Reset: 04
Bit Field
Type
0
r
IMOD
E
0
r
1
r
0
r
RMAP
rw
H
H
System Control Register 0
rw
RMAP = 0
BF SCU_PAGE
Reset: 00
Reset: 00
Bit Field
Type
OP
w
STNR
0
r
PAGE
rw
H
H
Page Register
w
RMAP = 0, PAGE 0
B3
B4
B5
B6
B7
MODPISEL
Bit Field
0
URRIS JTAGT JTAGT EXINT EXINT EXINT URRIS
H
H
H
H
H
H
Peripheral Input Select Register
H
DIS
rw
CKS
rw
2IS
rw
1IS
rw
0IS
rw
Type
r
rw
rw
IRCON0
Reset: 00
Bit Field
0
EXINT EXINT EXINT EXINT EXINT EXINT EXINT
H
H
H
Interrupt Request Register 0
6
5
4
3
2
1
0
Type
r
rwh
rwh
rwh
rwh
rwh
RIR
rwh
TIR
rwh
EIR
IRCON1
Reset: 00
Bit Field
0
CANS CANS ADCS ADCS
Interrupt Request Register 1
RC2
rwh
0
RC1
rwh
R1
R0
Type
r
rwh
rwh
rwh
0
rwh
rwh
IRCON2
Reset: 00
Bit Field
CANS
RC3
CANS
RC0
Interrupt Request Register 2
Type
r
rwh
r
rwh
EXICON0
Reset: F0
Bit Field
Type
EXINT3
EXINT2
EXINT1
EXINT0
H
H
H
External Interrupt Control
Register 0
rw
rw
rw
rw
BA
EXICON1
Reset: 3F
Bit Field
Type
0
r
EXINT6
rw
EXINT5
rw
EXINT4
rw
H
H
External Interrupt Control
Register 1
BB
NMICON
Reset: 00
Bit Field
Type
0
r
NMI
NMI
NMI
NMI
NMI
NMI
NMI
NMI Control Register
ECC
VDDP
rw
VDD
OCDS FLASH
PLL
rw
WDT
rw
rw
rw rw
rw
Data Sheet
34
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 8
SCU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
BC
NMISR
Reset: 00
Bit Field
0
FNMI
FNMI
FNMI
FNMI
FNMI
FNMI
FNMI
H
H
NMI Status Register
ECC
VDDP
VDD
OCDS FLASH
PLL
WDT
Type
r
rwh
rwh
rwh
BRDIS
rw
rwh
rwh
BRPRE
rw
rwh
rwh
R
BD
BE
BCON
Reset: 00
Bit Field
Type
BGSEL
rw
0
r
H
H
Baud Rate Control Register
rw
BG
Reset: 00
Bit Field
Type
BR_VALUE
rwh
H
H
Baud Rate Timer/Reload
Register
E9
FDCON
Reset: 00
Bit Field
BGS
rw
SYNE ERRS
EOFS
BRK
NDOV
rwh
FDM
rw
FDEN
rw
H
H
Fractional Divider Control
Register
N
YN
YN
Type
rw
rwh
rwh
rwh
EA
EB
FDSTEP
Reset: 00
Bit Field
Type
STEP
rw
H
H
Fractional Divider Reload
Register
FDRES
Reset: 00
Bit Field
Type
RESULT
rh
H
H
Fractional Divider Result
Register
RMAP = 0, PAGE 1
B3
ID
Reset: UU
Bit Field
Type
PRODID
r
VERID
r
H
H
Identity Register
B4
PMCON0
Reset: 00
Bit Field
0
WDT
RST
WKRS
WK
SD
rw
PD
WS
H
H
Power Mode Control Register 0
SEL
rw
Type
r
rwh
rwh
rwh
rw
B5
B6
B7
PMCON1
Reset: 00
Bit Field
0
CDC_
DIS
CAN_
DIS
MDU_
DIS
T2_
DIS
CCU_
DIS
SSC_
DIS
ADC_
DIS
H
H
H
H
Power Mode Control Register 1
Type
r
rw
0
rw
rw
rw
rw
rw
rw
OSC_CON
Reset: 08
Bit Field
OSC
PD
XPD
OSC
SS
ORD
RES
OSCR
H
H
H
H
OSC Control Register
Type
r
rw
rw
rw
rwh
rh
PLL_CON
Reset: 90
Bit Field
NDIV
rw
VCO
BYP
OSC
RESL
D
LOCK
PLL Control Register
DISC
Type
rw
rw
rwh
rh
BA
CMCON
Reset: 10
Bit Field
VCO
SEL
KDIV
0
FCCF
G
CLKREL
H
H
Clock Control Register
Type
rw
rw
r
rw
rw
BB
PASSWD
Reset: 07
Bit Field
PASS
PROT
MODE
rw
Password Register
ECT_S
Type
wh
rh
BC
BD
FEAL
Reset: 00
Bit Field
Type
ECCERRADDR
rh
H
H
H
Flash Error Address Register
Low
FEAH
Reset: 00
Bit Field
Type
ECCERRADDR
rh
H
Flash Error Address Register
High
Data Sheet
35
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 8
SCU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
BE
COCON
Reset: 00
Bit Field
0
r
TLEN
COUT
COREL
rw
H
H
Clock Output Control Register
S
Type
rw
rw
0
E9
MISC_CON
Reset: 00
Bit Field
DFLAS
HEN
H
H
Miscellaneous Control Register
Type
r
rwh
RMAP = 0, PAGE 3
B3
XADDRH
Reset: F0
Bit Field
Type
ADDRH
rw
H
H
On-chip XRAM Address Higher
Order
B4
IRCON3
Reset: 00
Bit Field
0
CANS
RC5
CCU6
SR1
0
CANS
RC4
CCU6
SR0
H
H
H
H
Interrupt Request Register 3
Type
r
rwh
rwh
r
rwh
rwh
B5
B7
IRCON4
Reset: 00
Bit Field
0
CANS
RC7
CCU6
SR3
0
CANS
RC6
CCU6
SR2
H
Interrupt Request Register 4
Type
r
rwh
rwh
r
rwh
rwh
MODPISEL1
Reset: 00
Bit Field EXINT
6IS
0
UR1RIS
T21EX JTAGT JTAGT
H
Peripheral Input Select Register
1
IS
rw
DIS1
rw
CKS1
rw
Type
rw
r
0
r
rw
BA
BB
MODPISEL2
Reset: 00
Bit Field
Type
T21IS
rw
T2IS
rw
T1IS
rw
T0IS
rw
H
H
Peripheral Input Select Register
2
PMCON2
Reset: 00
Bit Field
0
r
UART T21_D
H
H
Power Mode Control Register 2
1_DIS
rw
IS
Type
rw
BD
MODSUSP
Reset: 01
Bit Field
0
r
T21SU T2SUS T13SU T12SU WDTS
H
H
Module Suspend Control
Register
SP
rw
P
SP
rw
SP
rw
USP
rw
Type
rw
3.2.4.5 WDT Registers
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 9 WDT Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
BB
WDTCON
Reset: 00
Bit Field
0
r
WINB WDTP
0
r
WDTE WDTR WDTI
H
H
Watchdog Timer Control
Register
EN
rw
R
N
S
N
Type
rh
rw
rwh
rw
BC
BD
WDTREL
Reset: 00
Bit Field
Type
WDTREL
H
H
Watchdog Timer Reload
Register
rw
WDTWINB
Reset: 00
Bit Field
Type
WDTWINB
rw
H
H
Watchdog Window-Boundary
Count Register
Data Sheet
36
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 9
WDT Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
BE
WDTL
Reset: 00
Bit Field
WDT
rh
H
H
Watchdog Timer Register Low
Type
BF
WDTH
Reset: 00
Bit Field
Type
WDT
rh
H
H
Watchdog Timer Register High
3.2.4.6 Port Registers
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10 Port Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
B2
PORT_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
Page Register
RMAP = 0, PAGE 0
80
86
90
91
92
93
P0_DATA
Reset: 00
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
P0 Data Register
P0_DIR
Bit Field
Type
P0 Direction Register
P1_DATA
Reset: 00
Bit Field
Type
P1 Data Register
P1_DIR
Reset: 00
Bit Field
Type
P1 Direction Register
P5_DATA
Reset: 00
Bit Field
Type
P5 Data Register
P5_DIR
Reset: 00
Bit Field
Type
P5 Direction Register
A0
P2_DATA
Reset: 00
Bit Field
Type
H
P2 Data Register
A1
P2_DIR
Reset: 00
Bit Field
Type
H
P2 Direction Register
B0
P3_DATA
Reset: 00
Bit Field
Type
H
P3 Data Register
B1
P3_DIR
Reset: 00
Bit Field
Type
H
P3 Direction Register
C8
P4_DATA
Reset: 00
Bit Field
Type
H
P4 Data Register
C9
P4_DIR
Reset: 00
Bit Field
Type
H
P4 Direction Register
Data Sheet
37
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0, PAGE 1
80
86
90
91
92
93
P0_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
H
H
H
H
H
P0 Pull-Up/Pull-Down Select
Register
P0_PUDEN
Reset: C4
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
H
H
H
H
H
P0 Pull-Up/Pull-Down Enable
Register
P1_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P1 Pull-Up/Pull-Down Select
Register
P1_PUDEN
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P1 Pull-Up/Pull-Down Enable
Register
P5_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P5 Pull-Up/Pull-Down Select
Register
P5_PUDEN
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P5 Pull-Up/Pull-Down Enable
Register
A0
P2_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
P2 Pull-Up/Pull-Down Select
Register
A1
P2_PUDEN
Reset: 00
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
P2 Pull-Up/Pull-Down Enable
Register
B0
P3_PUDSEL
Reset: BF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P3 Pull-Up/Pull-Down Select
Register
B1
P3_PUDEN
Reset: 40
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P3 Pull-Up/Pull-Down Enable
Register
C8
P4_PUDSEL
Reset: FF
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P4 Pull-Up/Pull-Down Select
Register
C9
P4_PUDEN
Reset: 04
Bit Field
Type
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
H
H
P4 Pull-Up/Pull-Down Enable
Register
RMAP = 0, PAGE 2
80
86
90
91
92
P0_ALTSEL0
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
P0 Alternate Select 0 Register
P0_ALTSEL1
Reset: 00
Bit Field
Type
H
P0 Alternate Select 1 Register
P1_ALTSEL0
Reset: 00
Bit Field
Type
H
P1 Alternate Select 0 Register
P1_ALTSEL1
Reset: 00
Bit Field
Type
H
P1 Alternate Select 1 Register
P5_ALTSEL0
Reset: 00
Bit Field
Type
H
P5 Alternate Select 0 Register
Data Sheet
38
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
93
P5_ALTSEL1
Reset: 00
Bit Field
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
P5 Alternate Select 1 Register
Type
B0
P3_ALTSEL0
Reset: 00
Bit Field
Type
H
H
P3 Alternate Select 0 Register
B1
P3_ALTSEL1
Reset: 00
Bit Field
Type
H
H
P3 Alternate Select 1 Register
C8
P4_ALTSEL0
Reset: 00
Bit Field
Type
H
H
P4 Alternate Select 0 Register
C9
P4_ALTSEL1
Reset: 00
Bit Field
Type
H
H
P4 Alternate Select 1 Register
RMAP = 0, PAGE 3
80
90
92
P0_OD
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
P0 Open Drain Control Register
P1_OD
Reset: 00
Bit Field
Type
H
P1 Open Drain Control Register
P5_OD
Reset: 00
Bit Field
Type
H
P5 Open Drain Control Register
B0
C8
P3_OD
Reset: 00
Bit Field
Type
H
H
H
P3 Open Drain Control Register
P4_OD
Reset: 00
Bit Field
Type
H
P4 Open Drain Control Register
3.2.4.7 ADC Registers
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11 ADC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D1
ADC_PAGE
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
Page Register
RMAP = 0, PAGE 0
CA
ADC_GLOBCTR Reset: 30
Bit Field ANON
DW
rw
CTC
rw
0
r
H
H
Global Control Register
Type
rw
CB
ADC_GLOBSTR Reset: 00
Bit Field
0
r
CHNR
0
r
SAMP BUSY
LE
H
H
Global Status Register
Type
rh
rh
rh
CC
ADC_PRAR
Reset: 00
Bit Field ASEN
1
ASEN
0
0
r
ARBM CSM1 PRIO1 CSM0 PRIO0
H
H
Priority and Arbitration Register
Type
rw
rw
rw rw rw rw rw
Data Sheet
39
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
CD
ADC_LCBR
Reset: B7
Bit Field
BOUND1
BOUND0
H
H
Limit Check Boundary Register
Type
rw
rw
CE
ADC_INPCR0
Reset: 00
Bit Field
Type
STC
rw
H
H
H
H
Input Class 0 Register
CF
ADC_ETRCR
Reset: 00
Bit Field SYNE
N1
SYNE
N0
ETRSEL1
ETRSEL0
rw
External Trigger Control
Register
Type
rw
rw
rw
RMAP = 0, PAGE 1
CA
ADC_CHCTR0
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
H
H
H
H
H
H
H
H
Channel Control Register 0
CB
ADC_CHCTR1
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 1
CC
CD
CE
ADC_CHCTR2
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 2
ADC_CHCTR3
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 3
ADC_CHCTR4
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 4
CF
D2
ADC_CHCTR5
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 5
ADC_CHCTR6
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 6
D3
ADC_CHCTR7
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 7
RMAP = 0, PAGE 2
CA
ADC_RESR0L
Reset: 00
Bit Field
Type
RESULT
0
r
VF
rh
DRC
rh
CHNR
H
H
H
H
H
H
H
H
Result Register 0 Low
rh
rh
CB
ADC_RESR0H
Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 0 High
CC
CD
CE
ADC_RESR1L
Reset: 00
Bit Field
Type
RESULT
rh
0
r
VF
rh
DRC
rh
CHNR
rh
H
Result Register 1 Low
ADC_RESR1H
Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 1 High
ADC_RESR2L
Reset: 00
Bit Field
Type
RESULT
rh
0
r
VF
rh
DRC
rh
CHNR
rh
H
Result Register 2 Low
CF
ADC_RESR2H
Reset: 00
Bit Field
Type
RESULT
rh
H
Result Register 2 High
D2
ADC_RESR3L
Reset: 00
Bit Field
Type
RESULT
rh
0
r
VF
rh
DRC
rh
CHNR
rh
H
Result Register 3 Low
Data Sheet
40
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
D3
ADC_RESR3H
Reset: 00
Bit Field
RESULT
H
H
Result Register 3 High
Type
rh
RMAP = 0, PAGE 3
CA
ADC_RESRA0L Reset: 00
Bit Field
Type
RESULT
rh
VF
rh
DRC
rh
CHNR
rh
H
H
Result Register 0, View A Low
CB
ADC_RESRA0H Reset: 00
Bit Field
Type
RESULT
rh
H
H
Result Register 0, View A High
CC
CD
CE
ADC_RESRA1L Reset: 00
H
Bit Field
Type
RESULT
rh
VF
rh
DRC
rh
CHNR
rh
H
Result Register 1, View A Low
ADC_RESRA1H Reset: 00
H
Bit Field
Type
RESULT
rh
H
Result Register 1, View A High
ADC_RESRA2L Reset: 00
H
Bit Field
Type
RESULT
rh
VF
rh
DRC
rh
CHNR
rh
H
Result Register 2, View A Low
CF
D2
ADC_RESRA2H Reset: 00
H
Bit Field
Type
RESULT
rh
H
Result Register 2, View A High
ADC_RESRA3L Reset: 00
H
Bit Field
Type
RESULT
rh
VF
rh
DRC
rh
CHNR
rh
H
Result Register 3, View A Low
D3
ADC_RESRA3H Reset: 00
H
Bit Field
Type
RESULT
rh
H
Result Register 3, View A High
RMAP = 0, PAGE 4
CA
ADC_RCR0
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
H
H
H
H
H
Result Control Register 0
Type
rw
rw
r
rw
r
rw
CB
ADC_RCR1
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
Result Control Register 1
Type
rw
rw
r
rw
r
rw
CC
CD
CE
ADC_RCR2
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
Result Control Register 2
Type
rw
rw
r
rw
r
rw
ADC_RCR3
Reset: 00
Bit Field VFCT
R
WFR
0
IEN
0
DRCT
R
H
Result Control Register 3
Type
rw
rw
r
rw
r
VFC2
w
rw
VFC0
w
ADC_VFCR
Reset: 00
Bit Field
Type
0
VFC3
w
VFC1
w
H
Valid Flag Clear Register
r
RMAP = 0, PAGE 5
CA
ADC_CHINFR
Reset: 00
Bit Field CHINF CHINF CHINF CHINF CHINF CHINF CHINF CHINF
H
H
Channel Interrupt Flag Register
7
6
5
4
3
2
1
0
Type
rh
rh
rh
rh
rh
rh
rh
rh
CB
ADC_CHINCR
Reset: 00
Bit Field CHINC CHINC CHINC CHINC CHINC CHINC CHINC CHINC
H
H
Channel Interrupt Clear Register
7
6
5
4
3
2
1
0
Type
w
w
w
w
w
w
w
w
Data Sheet
41
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
CC
CD
CE
ADC_CHINSR
Reset: 00
Bit Field CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS
H
H
Channel Interrupt Set Register
7
6
5
4
3
2
1
0
Type
w
w
w
w
w
w
w
w
ADC_CHINPR
Reset: 00
Bit Field CHINP CHINP CHINP CHINP CHINP CHINP CHINP CHINP
H
H
Channel Interrupt Node Pointer
Register
7
6
5
4
3
2
1
0
Type
rw
rw
rw
rw
rw
rw
rw
rw
ADC_EVINFR
Reset: 00
Bit Field EVINF EVINF EVINF EVINF
0
EVINF EVINF
H
H
H
H
Event Interrupt Flag Register
7
6
5
4
1
0
Type
rh
rh
rh
rh
r
rh
rh
CF
D2
ADC_EVINCR
Reset: 00
Bit Field EVINC EVINC EVINC EVINC
0
EVINC EVINC
H
Event Interrupt Clear Flag
Register
7
6
5
4
1
0
Type
w
w
w
w
r
w
w
ADC_EVINSR
Reset: 00
Bit Field EVINS EVINS EVINS EVINS
0
EVINS EVINS
H
Event Interrupt Set Flag Register
7
6
5
4
1
0
Type
w
w
w
w
r
w
w
D3
ADC_EVINPR
Reset: 00
Bit Field EVINP EVINP EVINP EVINP
0
EVINP EVINP
H
H
Event Interrupt Node Pointer
Register
7
6
5
4
1
0
Type
rw
rw
rw
rw
r
rw
rw
RMAP = 0, PAGE 6
CA
ADC_CRCR1
Reset: 00
Conversion Request Control
Register 1
Bit Field
Type
CH7
rwh
CH6
rwh
CH5
rwh
CH4
rwh
0
r
H
H
H
CB
ADC_CRPR1
Reset: 00
Bit Field CHP7
CHP6
rwh
CHP5
rwh
CHP4
rwh
0
r
H
Conversion Request Pending
Register 1
Type
rwh
Rsv
CC
CD
CE
ADC_CRMR1
Reset: 00
Bit Field
LDEV
CLRP
ND
SCAN
ENSI
ENTR
0
ENGT
H
H
H
H
Conversion Request Mode
Register 1
Type
r
w
w
rw
rw
0
rw
r
rw
ADC_QMR0
Reset: 00
Bit Field
CEV
TREV
FLUS
H
CLRV
ENTR
0
ENGT
H
Queue Mode Register 0
Type
w
w
0
w
w
r
rw
r
rw
ADC_QSR0
Reset: 20
Bit Field
Rsv
EMPT
Y
EV
0
r
FILL
rh
H
Queue Status Register 0
Type
r
r
rh
RF
rh
rh
V
CF
D2
ADC_Q0R0
Reset: 00
Bit Field EXTR
Type rh
Bit Field EXTR
Type rh
Bit Field EXTR
Type
ENSI
rh
0
r
REQCHNR
H
H
H
H
Queue 0 Register 0
rh
V
rh
REQCHNR
rh
ADC_QBUR0
Reset: 00
ENSI
rh
RF
rh
0
r
H
Queue Backup Register 0
rh
D2
ADC_QINR0
Reset: 00
ENSI
w
RF
w
0
r
REQCHNR
w
H
Queue Input Register 0
w
Data Sheet
42
V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.4.8 Timer 2 Registers
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 12 T2 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
C0
T2_T2CON
Reset: 00
Bit Field
TF2
rwh
EXF2
rwh
0
r
EXEN
2
TR2
C/T2
rw
CP/
H
H
H
Timer 2 Control Register
RL2
Type
rw
rwh
rw
C1
T2_T2MOD
Reset: 00
Bit Field
T2RE
GS
T2RH
EN
EDGE PREN
SEL
T2PRE
DCEN
H
Timer 2 Mode Register
Type
rw
rw
rw
rw
rw
rw
rw
rw
C2
C3
T2_RC2L
Reset: 00
Bit Field
Type
RC2
H
H
H
Timer 2 Reload/Capture
Register Low
rwh
T2_RC2H
Reset: 00
Bit Field
Type
RC2
rwh
H
Timer 2 Reload/Capture
Register High
C4
C5
T2_T2L
Reset: 00
Bit Field
Type
THL2
rwh
H
H
H
Timer 2 Register Low
T2_T2H
Reset: 00
Bit Field
Type
THL2
rwh
H
Timer 2 Register High
3.2.4.9 Timer 21 Registers
The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 13 T21 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
C0
T21_T2CON
Reset: 00
Bit Field
TF2
rwh
EXF2
rwh
0
r
EXEN
2
TR2
C/T2
rw
CP/
H
H
Timer 2 Control Register
RL2
Type
rw
rwh
rw
C1
T21_T2MOD
Reset: 00
Bit Field
T2RE
GS
T2RH
EN
EDGE PREN
SEL
T2PRE
DCEN
H
H
Timer 2 Mode Register
Type
rw
rw
rw
rw
rw
rw
rw
rw
C2
C3
C4
T21_RC2L
Reset: 00
Bit Field
Type
RC2
H
H
H
H
H
H
Timer 2 Reload/Capture
Register Low
rwh
T21_RC2H
Reset: 00
Bit Field
Type
RC2
rwh
Timer 2 Reload/Capture
Register High
T21_T2L
Reset: 00
Bit Field
Type
THL2
rwh
Timer 2 Register Low
Data Sheet
43
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 13
T21 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
C5
T21_T2H
Reset: 00
Bit Field
THL2
rwh
H
H
Timer 2 Register High
Type
3.2.4.10 CCU6 Registers
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 14 CCU6 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A3
CCU6_PAGE
Reset: 00
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
Page Register
RMAP = 0, PAGE 0
9A
CCU6_CC63SRL
Bit Field
Type
CC63SL
H
H
Capture/Compare Shadow Register
for Channel CC63 Low
rw
9B
CCU6_CC63SRH
Reset: 00
Bit Field
Type
CC63SH
rw
H
H
Capture/Compare Shadow Register
for Channel CC63 High
9C
9D
9E
CCU6_TCTR4L
Reset: 00
Bit Field
T12
T12
0
r
DT
T12
T12R
S
T12R
R
H
H
H
H
Timer Control Register 4 Low
STD
STR
RES
w
RES
Type
w
w
w
w
w
CCU6_TCTR4H
Reset: 00
Bit Field
T13
T13
0
r
T13
T13R
S
T13R
R
H
Timer Control Register 4 High
STD
STR
RES
Type
w
w
0
w
w
w
CCU6_MCMOUTSL
Reset: 00
Bit Field STRM
CM
MCMPS
H
Multi-Channel Mode Output Shadow
Register Low
Type
w
r
rw
9F
CCU6_MCMOUTSH
Reset: 00
Bit Field STRH
P
0
CURHS
rw
EXPHS
rw
H
H
Multi-Channel Mode Output Shadow
Register High
Type
w
r
A4
A5
A6
A7
CCU6_ISRL
Reset: 00
Bit Field RT12
PM
RT12 RCC6 RCC6 RCC6 RCC6 RCC6 RCC6
H
H
H
H
H
H
H
Capture/Compare Interrupt Status
Reset Register Low
OM
w
2F
w
2R
w
1F
w
1R
w
0F
w
0R
w
Type
w
CCU6_ISRH
Reset: 00
Bit Field RSTR RIDLE RWH RCHE
E
0
RTRP RT13
RT13
CM
Capture/Compare Interrupt Status
Reset Register High
F
PM
w
Type
w
0
w
w
w
0
r
w
w
CCU6_CMPMODIFL
Reset: 00
Bit Field
MCC6
3S
MCC6 MCC6 MCC6
Compare State Modification Register
Low
2S
w
1S
w
0S
w
Type
r
w
r
CCU6_CMPMODIFH Reset: 00
H
Bit Field
0
MCC6
3R
0
MCC6 MCC6 MCC6
Compare State Modification Register
High
2R
w
1R
w
0R
w
Type
r
w
r
Data Sheet
44
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
FA
CCU6_CC60SRL
Reset: 00
Bit Field
CC60SL
H
H
Capture/Compare Shadow Register
for Channel CC60 Low
Type
rwh
FB
CCU6_CC60SRH
Reset: 00
Bit Field
Type
CC60SH
rwh
H
H
Capture/Compare Shadow Register
for Channel CC60 High
FC
FD
FE
CCU6_CC61SRL
Reset: 00
Bit Field
Type
CC61SL
rwh
H
H
Capture/Compare Shadow Register
for Channel CC61 Low
CCU6_CC61SRH
Reset: 00
Bit Field
Type
CC61SH
rwh
H
H
Capture/Compare Shadow Register
for Channel CC61 High
CCU6_CC62SRL
Reset: 00
Bit Field
Type
CC62SL
rwh
H
H
Capture/Compare Shadow Register
for Channel CC62 Low
FF
CCU6_CC62SRH
Reset: 00
Bit Field
Type
CC62SH
rwh
H
H
Capture/Compare Shadow Register
for Channel CC62 High
RMAP = 0, PAGE 1
9A
CCU6_CC63RL
Reset: 00
Bit Field
Type
CC63VL
rh
H
H
H
Capture/Compare Register for
Channel CC63 Low
9B
CCU6_CC63RH
Reset: 00
Bit Field
Type
CC63VH
rh
H
Capture/Compare Register for
Channel CC63 High
9C
9D
9E
CCU6_T12PRL
Reset: 00
Bit Field
Type
T12PVL
rwh
H
H
H
H
H
H
Timer T12 Period Register Low
CCU6_T12PRH
Reset: 00
Bit Field
Type
T12PVH
rwh
H
Timer T12 Period Register High
CCU6_T13PRL
Reset: 00
Bit Field
Type
T13PVL
rwh
H
Timer T13 Period Register Low
9F
CCU6_T13PRH
Reset: 00
Bit Field
Type
T13PVH
rwh
H
Timer T13 Period Register High
A4
A5
A6
CCU6_T12DTCL
Reset: 00
Bit Field
Type
DTM
H
H
H
Dead-Time Control Register for
Timer T12 Low
rw
CCU6_T12DTCH
Reset: 00
Bit Field
Type
0
r
DTR2 DTR1 DTR0
0
r
DTE2 DTE1 DTE0
H
H
Dead-Time Control Register for
Timer T12 High
rh
rh
rh
rw
rw
rw
CCU6_TCTR0L
Reset: 00
Bit Field CTM
CDIR
STE1
2
T12R
T12
T12CLK
Timer Control Register 0 Low
PRE
Type
rw
rh
rh
rh
rw
rw
A7
CCU6_TCTR0H
Reset: 00
Bit Field
0
r
STE1
3
T13R
T13
T13CLK
H
H
H
Timer Control Register 0 High
PRE
Type
rh
rh
rw
rw
FA
CCU6_CC60RL
Reset: 00
Bit Field
Type
CC60VL
rh
H
Capture/Compare Register for
Channel CC60 Low
Data Sheet
45
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
FB
CCU6_CC60RH
Reset: 00
Bit Field
CC60VH
H
H
H
H
H
H
Capture/Compare Register for
Channel CC60 High
Type
rh
FC
FD
FE
CCU6_CC61RL
Reset: 00
Bit Field
Type
CC61VL
rh
H
H
Capture/Compare Register for
Channel CC61 Low
CCU6_CC61RH
Reset: 00
Bit Field
Type
CC61VH
rh
Capture/Compare Register for
Channel CC61 High
CCU6_CC62RL
Reset: 00
Bit Field
Type
CC62VL
rh
H
Capture/Compare Register for
Channel CC62 Low
FF
CCU6_CC62RH
Reset: 00
Bit Field
Type
CC62VH
rh
H
Capture/Compare Register for
Channel CC62 High
RMAP = 0, PAGE 2
9A
CCU6_T12MSELL
Reset: 00
Bit Field
Type
MSEL61
rw
HSYNC
rw
MSEL60
H
H
T12 Capture/Compare Mode Select
Register Low
rw
9B
CCU6_T12MSELH
Reset: 00
Bit Field DBYP
Type rw
MSEL62
rw
H
H
T12 Capture/Compare Mode Select
Register High
9C
CCU6_IENL
Reset: 00
Bit Field ENT1 ENT1 ENCC ENCC ENCC ENCC ENCC ENCC
H
H
Capture/Compare Interrupt Enable
Register Low
2
2
62F
62R
61F
61R
60F
60R
PM
OM
Type
rw
rw
rw
rw
rw
0
rw
rw
rw
9D
9E
CCU6_IENH
Reset: 00
Bit Field
EN
EN
EN
EN
EN
ENT1 ENT1
H
H
Capture/Compare Interrupt Enable
Register High
STR
IDLE
WHE
CHE
TRPF
3PM
rw
3CM
rw
Type
rw
rw
rw
rw
r
rw
CCU6_INPL
Reset: 40
Bit Field
Type
INPCHE
INPCC62
INPCC61
INPCC60
H
H
H
H
Capture/Compare Interrupt Node
Pointer Register Low
rw
rw
rw
rw
9F
CCU6_INPH
Reset: 39
Bit Field
Type
0
r
INPT13
rw
INPT12
rw
INPERR
rw
H
Capture/Compare Interrupt Node
Pointer Register High
A4
CCU6_ISSL
Reset: 00
Bit Field ST12
PM
ST12 SCC6 SCC6 SCC6 SCC6 SCC6 SCC6
H
H
Capture/Compare Interrupt Status
Set Register Low
OM
w
2F
w
2R
w
1F
w
1R
w
0F
w
0R
w
Type
w
A5
CCU6_ISSH
Reset: 00
Bit Field SSTR SIDLE SWHE SCHE SWH
C
STRP ST13
ST13
CM
H
Capture/Compare Interrupt Status
Set Register High
F
PM
w
Type
w
w
0
r
w
w
w
w
w
A6
A7
CCU6_PSLR
Reset: 00
Bit Field PSL63
PSL
rwh
H
H
Passive State Level Register
Type
rwh
CCU6_MCMCTR
Reset: 00
Bit Field
Type
0
r
SWSYN
rw
0
r
SWSEL
rw
H
H
Multi-Channel Mode Control Register
FA
CCU6_TCTR2L
Reset: 00
Bit Field
0
r
T13TED
rw
T13TEC
T13
T12
H
H
Timer Control Register 2 Low
SSC
SSC
Type
rw
rw
rw
Data Sheet
46
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
FB
CCU6_TCTR2H
Reset: 00
Bit Field
0
r
T13RSEL
T12RSEL
H
H
H
Timer Control Register 2 High
Type
rw
rw
FC
FD
FE
CCU6_MODCTRL
Reset: 00
Bit Field MCM
EN
0
T12MODEN
H
Modulation Control Register Low
Type
rw
r
rw
CCU6_MODCTRH
Reset: 00
Bit Field ECT1
3O
0
T13MODEN
H
H
H
H
Modulation Control Register High
Type
rw
r
rw
CCU6_TRPCTRL
Reset: 00
Bit Field
0
r
TRPM TRPM TRPM
H
Trap Control Register Low
2
1
0
Type
rw
rw
rw
FF
CCU6_TRPCTRH
Reset: 00
Bit Field TRPP TRPE
TRPEN
H
Trap Control Register High
EN
rw
N13
rw
Type
rw
RMAP = 0, PAGE 3
9A
CCU6_MCMOUTL
Reset: 00
Bit Field
Type
0
r
R
MCMP
rh
H
H
Multi-Channel Mode Output Register
Low
rh
9B
CCU6_MCMOUTH
Reset: 00
Bit Field
Type
0
r
CURH
rh
EXPH
rh
H
H
Multi-Channel Mode Output Register
High
9C
9D
9E
CCU6_ISL
Reset: 00
Bit Field
T12
PM
T12
OM
ICC62 ICC62 ICC61 ICC61 ICC60 ICC60
H
H
Capture/Compare Interrupt Status
Register Low
F
rh
R
rh
F
R
F
R
Type
rh
rh
rh
rh
rh
rh
CCU6_ISH
Reset: 00
Bit Field
STR
IDLE
WHE
CHE
TRPS TRPF
T13
PM
T13
CM
H
H
Capture/Compare Interrupt Status
Register High
Type
rh
rh
rh
rh
rh
rh
rh
rh
CCU6_PISEL0L
Reset: 00
Bit Field
Type
ISTRP
rw
ISCC62
ISCC61
ISCC60
H
H
H
H
H
H
H
H
Port Input Select Register 0 Low
rw
rw
ISPOS1
rw
rw
ISPOS0
rw
9F
CCU6_PISEL0H
Reset: 00
Bit Field
Type
IST12HR
rw
ISPOS2
H
Port Input Select Register 0 High
rw
0
A4
CCU6_PISEL2
Reset: 00
Bit Field
Type
IST13HR
rw
H
Port Input Select Register 2
r
FA
FB
CCU6_T12L
Reset: 00
Bit Field
Type
T12CVL
rwh
H
H
Timer T12 Counter Register Low
CCU6_T12H
Reset: 00
Bit Field
Type
T12CVH
rwh
Timer T12 Counter Register High
FC
CCU6_T13L
Reset: 00
Bit Field
Type
T13CVL
rwh
H
H
Timer T13 Counter Register Low
FD
CCU6_T13H
Reset: 00
Bit Field
Type
T13CVH
rwh
Timer T13 Counter Register High
Data Sheet
47
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
FE
CCU6_CMPSTATL
Reset: 00
Bit Field
0
CC63
CC
CC
CC
CC62 CC61 CC60
H
H
H
Compare State Register Low
ST
POS2 POS1 POS0
ST
rh
ST
rh
ST
rh
Type
r
rh
rh
rh
rh
FF
CCU6_CMPSTATH
Reset: 00
Bit Field T13IM COUT COUT CC62 COUT CC61 COUT CC60
H
Compare State Register High
63PS
rwh
62PS
rwh
PS
61PS
rwh
PS
60PS
rwh
PS
Type
rwh
rwh
rwh
rwh
3.2.4.11 UART1 Registers
The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 15 UART1 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
C8
SCON
Reset: 00
Bit Field
Type
SM0
rw
SM1
rw
SM2
rw
REN
rw
TB8
rw
RB8
rwh
TI
RI
H
H
Serial Channel Control Register
rwh
rwh
C9
SBUF
Reset: 00
Bit Field
Type
VAL
rwh
H
H
H
H
Serial Data Buffer Register
CA
CB
BCON
Reset: 00
Bit Field
Type
0
r
BRPRE
rw
R
H
H
Baud Rate Control Register
rw
BG
Reset: 00
Bit Field
Type
BR_VALUE
rwh
Baud Rate Timer/Reload
Register
CC
CD
CE
FDCON
Reset: 00
Bit Field
Type
0
r
NDOV
rwh
FDM
rw
FDEN
rw
H
H
H
H
Fractional Divider Control
Register
FDSTEP
Reset: 00
Bit Field
Type
STEP
rw
H
Fractional Divider Reload
Register
FDRES
Reset: 00
Bit Field
Type
RESULT
rh
H
Fractional Divider Result
Register
Data Sheet
48
V1.2, 2009-07
XC886/888CLM
Functional Description
3.2.4.12 SSC Registers
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 16 SSC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A9
SSC_PISEL
Reset: 00
Bit Field
Type
0
r
CIS
rw
SIS
rw
MIS
rw
H
H
Port Input Select Register
AA
AA
AB
AB
SSC_CONL
Reset: 00
Bit Field
Type
LB
rw
PO
rw
PH
rw
HB
rw
BM
rw
H
H
H
H
H
Control Register Low
Programming Mode
SSC_CONL
Reset: 00
Bit Field
Type
0
r
BC
rh
H
H
H
H
Control Register Low
Operating Mode
SSC_CONH
Reset: 00
Bit Field
Type
EN
rw
MS
rw
0
r
AREN
rw
BEN
rw
PEN
rw
REN
rw
TEN
rw
Control Register High
Programming Mode
SSC_CONH
Reset: 00
Bit Field
Type
EN
rw
MS
rw
0
r
BSY
rh
BE
PE
RE
TE
Control Register High
Operating Mode
rwh
rwh
rwh
rwh
AC
AD
AE
SSC_TBL
Reset: 00
Bit Field
Type
TB_VALUE
H
Transmitter Buffer Register Low
rw
RB_VALUE
rh
SSC_RBL
Reset: 00
Bit Field
Type
H
H
Receiver Buffer Register Low
SSC_BRL
Reset: 00
Bit Field
Type
BR_VALUE
rw
H
H
H
Baud Rate Timer Reload
Register Low
AF
SSC_BRH
Reset: 00
Bit Field
Type
BR_VALUE
rw
H
Baud Rate Timer Reload
Register High
3.2.4.13 MultiCAN Registers
The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).
Table 17 CAN Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D8
ADCON
Reset: 00
Bit Field
Type
V3
rw
V2
rw
V1
rw
V0
rw
AUAD
rw
BSY
rh
RWEN
rw
H
H
CAN Address/Data Control
Register
D9
ADL
Reset: 00
Bit Field
Type
CA9
rwh
CA8
rwh
CA7
rwh
CA6
rwh
CA5
rwh
CA4
rwh
CA3
rwh
CA2
rwh
H
H
H
CAN Address Register Low
DA
ADH
Reset: 00
Bit Field
Type
0
r
CA13
rwh
CA12
rwh
CA11
rwh
CA10
rwh
H
CAN Address Register High
Data Sheet
49
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 17
CAN Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
DB
DATA0
Reset: 00
Bit Field
CD
rwh
CD
rwh
CD
rwh
CD
rwh
H
H
H
H
H
CAN Data Register 0
Type
DC
DD
DE
DATA1
Reset: 00
Bit Field
Type
H
H
CAN Data Register 1
DATA2
Reset: 00
Bit Field
Type
CAN Data Register 2
DATA3
Reset: 00
Bit Field
Type
H
CAN Data Register 3
3.2.4.14 OCDS Registers
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 18 OCDS Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
E9
MMCR2
Reset: 1U
Bit Field STMO EXBC DSUS MBCO ALTDI MMEP MMOD JENA
H
H
Monitor Mode Control 2
Register
DE
rw
P
rw
0
N
E
rh
Type
rw
rwh
rw
rwh
rh
F1
MMCR
Reset: 00
Bit Field MEXIT MEXIT
_P
MSTE MRAM MRAM
TRF
RRF
H
H
H
H
H
H
Monitor Mode Control Register
P
S_P
w
S
Type
w
rwh
r
rw
rwh
rh
rh
F2
F3
F4
F5
MMSR
Reset: 00
Bit Field MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWB0
H
Monitor Mode Status Register
M
F
F
F
F
Type
rw
rwh
rwh
rwh
rwh
rwh
rwh
rwh
MMBPCR
Reset: 00
Bit Field SWBC
HWB3C
HWB2C
HWB1
C
HWB0C
H
H
Breakpoints Control Register
Type rw
rw
rw
rw
rw
MMICR
Reset: 00
Bit Field DVEC DRET COMR MSTS
MMUI
E_P
MMUI RRIE_
RRIE
rw
Monitor Mode Interrupt Control
Register
T
R
ST
EL
rh
E
P
w
Type
rwh
rwh
rwh
w
rw
MMDR
Reset: 00
Bit Field
Type
MMRR
rh
H
H
Monitor Mode Data Transfer
Register
Receive
F6
F7
HWBPSR
Reset: 00
Bit Field
0
r
BPSEL
_P
BPSEL
rw
H
H
Hardware Breakpoints Select
Register
Type
w
HWBPDR
Reset: 00
Bit Field
Type
HWBPxx
H
H
Hardware Breakpoints Data
Register
rw
EB
MMWR1
Reset: 00
Bit Field
Type
MMWR1
rw
H
Monitor Work Register 1
Data Sheet
50
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 18
OCDS Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
EC
MMWR2
Reset: 00
Bit Field
MMWR2
H
H
Monitor Work Register 2
Type
rw
Data Sheet
51
V1.2, 2009-07
XC886/888CLM
Functional Description
3.3
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The sectorization of the Flash memory allows each
sector to be erased independently.
Features
• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program and erase operations for CPU load minimization
• Support for aborting erase operation
• Minimum program width1) of 32-byte for D-Flash and 64-byte for P-Flash
• 1-sector minimum erase width
• 1-byte read access
• Flash is delivered in erased state (read all zeros)
• Operating supply voltage: 2.5 V ± 7.5 %
• Read access time: 3 × tCCLK = 125 ns2)
• Program time: 248256 / fSYS = 2.6 ms3)
• Erase time: 9807360 / fSYS = 102 ms3)
1) P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed.
D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.
2) Values shown here are typical values. fsys = 96 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the maximum
frequency range for Flash read access.
3) Values shown here are typical values. fsys = 96 MHz ± 7.5% is the only frequency range for Flash
programming and erasing. fsysmin is used for obtaining the worst case timing.
Data Sheet
52
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 19 shows the Flash data retention and endurance targets.
Table 19
Retention
Program Flash
20 years
20 years
Data Flash
20 years
5 years
Flash Data Retention and Endurance (Operating Conditions apply)
Endurance1)
Size
Remarks
1,000 cycles
1,000 cycles
up to 32 Kbytes2)
up to 24 Kbytes2)
for 32-Kbyte Variant
for 24-Kbyte Variant
1,000 cycles
4 Kbytes
1 Kbyte
512 bytes
128 bytes
10,000 cycles
70,000 cycles
100,000 cycles
2 years
2 years
1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance
data specified in Table 19 is valid only if the following conditions are fulfilled:
- the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles.
- the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles.
- the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles.
2) If no Flash is used for data, the Program Flash size can be up to the maximum Flash size available in the
device variant. Having more Data Flash will mean less Flash is available for Program Flash.
3.3.1
Flash Bank Sectorization
The XC886/888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes
of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash)
and Data Flash (D-Flash) bank(s) with different sectorization shown in Figure 11. Both
types can be used for code and data storage. The label “Data” neither implies that the
D-Flash is mapped to the data memory region, nor that it can only be used for data
storage. It is used to distinguish the different Flash bank sectorizations.
The 32-Kbyte Flash device consists of 6 P-Flash and 2 D-Flash banks, while the 24-
Kbyte Flash device consists of also of 6 P-Flash banks but with the upper 2 banks only
2 Kbytes each, and only 1 D-Flash bank. The XC886/888 ROM devices offer a single 4-
Kbyte D-Flash bank.
The P-Flash banks are always grouped in pairs. As such, the P-Flash banks are also
sometimes referred to as P-Flash bank pair. Each sector in a P-Flash bank is grouped
with the corresponding sector from the other bank within a bank pair to form a P-Flash
bank pair sector.
Data Sheet
53
V1.2, 2009-07
XC886/888CLM
Functional Description
Sector 2: 128-byte
Sector 1: 128-byte
Sector 9: 128-byte
Sector 8: 128-byte
Sector 7: 128-byte
Sector 6: 128-byte
Sector 5: 256-byte
Sector 4: 256-byte
Sector 3: 512-byte
Sector 2: 512-byte
Sector 0: 3.75-Kbyte
Sector 1: 1-Kbyte
Sector 0: 1-Kbyte
P-Flash
D-Flash
Figure 11
Flash Bank Sectorization
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
3.3.2
Parallel Read Access of P-Flash
To enhance system performance, the P-Flash banks are configured for parallel read to
allow two bytes of linear code to be read in 4 x CCLK cycles, compared to 6 x CCLK
cycles if serial read is performed. This is achieved by reading two bytes in parallel from
a P-Flash bank pair within the 3 x CCLK cycles access time and storing them in a cache.
Subsequent read from the cache by the CPU does not require a wait state and can be
completed within 1 x CCLK cycle. The result is the average instruction fetch time from
the P-Flash banks is reduced and thus, the MIPS (Mega Instruction Per Second) of the
system is increased.
However, if the parallel read feature is not desired due to certain timing constraints, it can
be disabled by calling the parallel read disable subroutine.
Data Sheet
54
V1.2, 2009-07
XC886/888CLM
Functional Description
3.3.3
Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be
reprogrammed as the Flash cells can only withstand one gate disturb. This means that
the entire sector containing the WL must be erased since it is impossible to erase a
single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required
as the Flash cells are able to withstand two gate disturbs. This means if the number of
data bytes that needs to be written is smaller than the 32-byte minimum programming
width, the user can opt to program this number of data bytes (x; where x can be any
integer from 1 to 31) first and program the remaining bytes (32 - x) later. Hence, it is
possible to program the same WL, for example, with 16 bytes of data two times (see
Figure 12)
32 bytes (1 WL)
0000 ….. 0000 H
16 bytes
16 bytes
Program 1
0000 ….. 0000 H
1111 ….. 1111 H
1111 ….. 1111 H
0000 ….. 0000 H
1111 ….. 1111H
Program 2
0000 ….. 0000 H
1111 ….. 0000 H
1111 ….. 0000 H
0000 ….. 0000H
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
Flash memory cells
32-byte write buffers
Figure 12
D-Flash Programming
Note: When programming a D-Flash WL the second time, the previously programmed
Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain
its original contents and to prevent “over-programming”.
Data Sheet
55
V1.2, 2009-07
XC886/888CLM
Functional Description
3.4
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC886/888 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1
Interrupt Source
Figure 13 to Figure 17 give a general overview of the interrupt sources and nodes, and
their corresponding control and status flags.
WDT Overflow
FNMIWDT
NMIISR.0
NMIWDT
NMICON.0
PLL Loss of Lock
FNMIPLL
NMIISR.1
NMIPLL
NMICON.1
Flash Operation
Complete
FNMIFLASH
NMIISR.2
NMIFLASH
>=1
Non
Maskable
Interrupt
0073
FNMIVDD
NMIISR.4
H
VDD Pre-Warning
VDDP Pre-Warning
Flash ECC Error
NMIVDD
NMICON.4
FNMIVDDP
NMIISR.5
NMIVDDP
NMICON.5
FNMIECC
NMIISR.6
NMIECC
NMICON.6
Figure 13
Non-Maskable Interrupt Request Sources
Data Sheet
56
V1.2, 2009-07
XC886/888CLM
Functional Description
Highest
Timer 0
TF0
Lowest
Overflow
Priority Level
TCON.5
000B
001B
ET0
H
H
IP.1/
IPH.1
IEN0.1
Timer 1
TF1
Overflow
P
o
l
TCON.7
ET1
IP.3/
IPH.3
IEN0.3
l
i
n
g
UART
Receive
RI
SCON.0
>=1
UART
S
e
q
u
e
n
c
0023
0003
TI
ES
IEN0.4
H
H
Transmit
IP.4/
IPH.4
SCON.1
IE0
TCON.1
EINT0
e
EX0
IT0
IP.0/
IPH.0
IEN0.0
TCON.0
EXINT0
EXICON0.0/1
IE1
EINT1
TCON.3
0013
EX1
H
IT1
IP.2/
IPH.2
IEN0.2
TCON.2
EXINT1
EA
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 14
Interrupt Request Sources (Part 1)
Data Sheet
57
V1.2, 2009-07
XC886/888CLM
Functional Description
Highest
Timer 2
Overflow
TF2
Lowest
T2_T2CON.7
Priority Level
>=1
T2EX
EXF2
T2_T2CON.6
EXEN2
T2_T2CON.3
EDGES
EL
T2_T2MOD.5
Normal Divider
Overflow
NDOV
>=1
FDCON.2
End of
002B
EOFSYN
FDCON.4
ET2
IEN0.5
P
H
Synch Byte
IP.5/
IPH.5
>=1
o
Synch Byte
Error
l
ERRSYN
FDCON.5
SYNEN
l
i
MultiCAN_0
CANSRC0
IRCON2.0
n
g
S
e
q
u
e
n
c
ADC_0
ADC_1
ADCSR0
IRCON1.3
ADCSR1
IRCON1.4
>=1
MultiCAN_1
MultiCAN_2
CANSRC1
IRCON1.5
0033
EADC
IEN1.0
H
IP1.0/
e
IPH1.0
CANSRC2
IRCON1.6
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 15
Interrupt Request Sources (Part 2)
Data Sheet
58
V1.2, 2009-07
XC886/888CLM
Functional Description
Highest
Lowest
Priority Level
SSC_EIR
SSC_TIR
SSC_RIR
EIR
IRCON1.0
>=1
TIR
IRCON1.1
003B
ESSC
IEN1.1
H
IP1.1/
RIR
IRCON1.2
IPH1.1
P
o
l
EXINT2
EINT2
IRCON0.2
l
i
EXINT2
EXICON0.4/5
n
g
RI
S
e
q
u
e
n
c
UART1_SCON.0
>=1
>=1
UART1
TI
UART1_SCON.1
Timer 21
Overflow
TF2
>=1
0043
EX2
IEN1.2
H
T21_T2CON.7
e
IP1.2/
IPH1.2
T21EX
EXF2
T21_T2CON.6
EXEN2
T21_T2CON.3
EDGES
EL
T21_T2MOD.5
Normal Divider
Overflow
NDOV
UART1_FDCON.2
Cordic
EOC
CDSTATC.2
MDU_0
MDU_1
IRDY
MDUSTAT.0
IERR
EA
MDUSTAT.1
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 16
Interrupt Request Sources (Part 3)
Data Sheet
59
V1.2, 2009-07
XC886/888CLM
Functional Description
Highest
Lowest
EXINT3
Priority Level
EINT3
EINT4
IRCON0.3
EXINT3
EXICON0.6/7
EXINT4
P
o
l
IRCON0.4
EXINT3
l
i
EXICON1.0/1
n
g
>=1
EXINT5
EINT5
004B
EXM
H
IRCON0.5
S
e
q
u
e
n
c
IP1.3/
IPH1.3
IEN1.3
EXINT5
EXICON1.2/3
EXINT6
EINT6
e
IRCON0.6
EXINT6
EXICON1.4/5
MultiCAN_3
CANSRC3
IRCON2.4
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 17
Interrupt Request Sources (Part 4)
Data Sheet
60
V1.2, 2009-07
XC886/888CLM
Functional Description
Highest
Lowest
Priority Level
CCU6 interrupt node 0
MultiCAN_4
CCU6SR0
IRCON3.0
>=1
>=1
CANSRC4
IRCON3.1
P
o
l
0053
005B
0063
H
H
ECCIP0
IEN1.4
IP1.4/
IPH1.4
l
i
CCU6 interrupt node 1
MultiCAN_5
CCU6SR1
IRCON3.4
n
g
CANSRC5
IRCON3.5
ECCIP1
IEN1.5
IP1.5/
S
e
q
u
e
n
c
IPH1.5
CCU6 interrupt node 2
MutliCAN_6
CCU6SR2
IRCON4.0
>=1
>=1
H
H
ECCIP2
IEN1.6
CANSRC6
IRCON4.1
IP1.6/
IPH1.6
e
CCU6 interrupt node 3
MultiCAN_7
CCU6SRC3
IRCON4.4
006B
CANSRC7
IRCON4.5
ECCIP3
IEN1.7
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 18
Interrupt Request Sources (Part 5)
Data Sheet
61
V1.2, 2009-07
XC886/888CLM
Functional Description
3.4.2
Interrupt Source and Vector
Each interrupt event source has an associated interrupt vector address for the interrupt
node it belongs to. This vector is accessed to service the corresponding interrupt node
request. The interrupt service of each interrupt source can be individually enabled or
disabled via an enable bit. The assignment of the XC886/888 interrupt sources to the
interrupt vector address and the corresponding interrupt node enable bits are
summarized in Table 20.
Table 20
Interrupt Vector Addresses
Interrupt
Vector
Assignment for
Enable Bit
SFR
Source
Address
XC886/888
NMI
0073H
Watchdog Timer NMI
PLL NMI
Flash NMI
VDDC Prewarning NMI
VDDP Prewarning NMI
Flash ECC NMI
External Interrupt 0
Timer 0
NMIWDT
NMIPLL
NMIFLASH
NMIVDD
NMIVDDP
NMIECC
EX0
ET0
EX1
ET1
ES
NMICON
XINTR0
XINTR1
XINTR2
XINTR3
XINTR4
XINTR5
0003H
000BH
0013H
001BH
0023H
002BH
IEN0
External Interrupt 1
Timer 1
UART
T2
ET2
UART Fractional Divider
(Normal Divider Overflow)
MultiCAN Node 0
LIN
Data Sheet
62
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 20
Interrupt Vector Addresses (cont’d)
Interrupt
Vector
Assignment for
Enable Bit
SFR
Source
Address
XC886/888
XINTR6
0033H
MultiCAN Nodes 1 and 2
EADC
IEN1
ADC[1:0]
SSC
External Interrupt 2
T21
XINTR7
XINTR8
003BH
0043H
ESSC
EX2
CORDIC
UART1
UART1 Fractional Divider
(Normal Divider Overflow)
MDU[1:0]
XINTR9
004BH
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
MultiCAN Node 3
CCU6 INP0
MultiCAN Node 4
CCU6 INP1
MultiCAN Node 5
CCU6 INP2
EXM
XINTR10
XINTR11
XINTR12
XINTR13
0053H
005BH
0063H
006BH
ECCIP0
ECCIP1
ECCIP2
ECCIP3
MultiCAN Node 6
CCU6 INP3
MultiCAN Node 7
Data Sheet
63
V1.2, 2009-07
XC886/888CLM
Functional Description
3.4.3
Interrupt Priority
An interrupt that is currently being serviced can only be interrupted by a higher-priority
interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of
the highest priority cannot be interrupted by any other interrupt request.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 21.
Table 21
Source
Priority Structure within Interrupt Level
Level
Non-Maskable Interrupt (NMI)
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
UART Interrupt
Timer 2,UART Normal Divider Overflow,
MultiCAN, LIN Interrupt
(highest)
1
2
3
4
5
6
ADC, MultiCAN Interrupt
SSC Interrupt
External Interrupt 2, Timer 21, UART1, UART1
Normal Divider Overflow, MDU, CORDIC Interrupt
7
8
9
External Interrupt [6:3], MultiCAN Interrupt
10
CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11
CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12
CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13
CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14
Data Sheet
64
V1.2, 2009-07
XC886/888CLM
Functional Description
3.5
Parallel Ports
The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4),
while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 5
(P5). Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1, P3, P4 and P5 are bidirectional and can be used as
general purpose input/output (GPIO) or to perform alternate input/output functions for the
on-chip peripherals. When configured as an output, the open drain mode can be
selected. Port P2 is an input-only port, providing general purpose input functions,
alternate input functions for the on-chip peripherals, and also analog inputs for the
Analog-to-Digital Converter (ADC).
Bidirectional Port Features
• Configurable pin direction
• Configurable pull-up/pull-down devices
• Configurable open drain mode
• Transfer of data through digital inputs and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals
Input Port Features
• Configurable input driver
• Configurable pull-up/pull-down devices
• Receive of data through digital input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module
Data Sheet
65
V1.2, 2009-07
XC886/888CLM
Functional Description
Figure 19 shows the structure of a bidirectional port pin.
Px_PUDSEL
Pull-up/Pull-down
Select Register
Internal Bus
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_OD
Open Drain
Control Register
Px_DIR
Direction Register
Px_ALTSEL0
Alternate Select
Register 0
VDDP
Px_ALTSEL1
Alternate Select
Register 1
Pull
Up
enable
Device
AltDataOut 3
AltDataOut 2
AltDataOut1
enable
11
Output
Driver
10
01
00
Pin
enable
Out
In
Input
Px_Data
Driver
Data Register
Schmitt Trigger
AltDataIn
Pull
enable
Down
Device
Pad
Figure 19
General Structure of Bidirectional Port
Data Sheet
66
V1.2, 2009-07
XC886/888CLM
Functional Description
Figure 20 shows the structure of an input-only port pin.
Internal Bus
Px_PUDSEL
Pull-up/Pull-down
Select Register
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_DIR
Direction Register
VDDP
Pull
Up
enable
Device
enable
Input
In
Driver
Px_DATA
Pin
Data Register
Schmitt Trigger
AltDataIn
AnalogIn
Pull
enable
Down
Device
Pad
Figure 20
General Structure of Input Port
Data Sheet
67
V1.2, 2009-07
XC886/888CLM
Functional Description
3.6
Power Supply System with Embedded Voltage Regulator
The XC886/888 microcontroller requires two different levels of power supply:
• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 21 shows the XC886/888 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps to reduce the power consumption of the
whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
On-chip
OSC
Peripheral
logic
Memory
ADC
FLASH
PLL
VDDC (2.5V)
XTAL1&
XTAL2
GPIO Ports
(P0-P5)
EVR
VDDP (3.3V/5.0V)
VSSP
Figure 21
XC886/888 Power Supply System
EVR Features
• Input voltage (VDDP): 3.3 V/5.0 V
• Output voltage (VDDC): 2.5 V ± 7.5%
• Low power voltage regulator provided in power-down mode
• VDDC and VDDP prewarning detection
• VDDC brownout detection
Data Sheet
68
V1.2, 2009-07
XC886/888CLM
Functional Description
3.7
Reset Control
The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC886/888 is first powered up, the status of certain pins (see Table 23) must
be defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external
capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches
0.4 V, but not before VDDC reaches 0.9* VDDC.
A typical application example is shown in Figure 22. The VDDP capacitor value is 100 nF
while the VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is
100 nF.
Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50 µs once VDDP reaches
2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than
500 µs, the RESET pin should be held low for 500 µs typically. See Figure 23.
3.3 / 5V
100nF
VIN
VR
220nF
VDDP
VDDC
VSSC
VSSP
typ.
100nF
RESET
EVR
30k
XC886/888
Figure 22
Reset Circuitry
Data Sheet
69
V1.2, 2009-07
XC886/888CLM
Functional Description
Voltage
5V
VDDP
VDDC
2.5V
2.3V
0.9*VDDC
Time
Voltage
5V
RESET with
capacitor
< 0.4V
0V
Time
typ. < 50µs
Figure 23
VDDP,
VDDC and VRESET during Power-on Reset
The second type of reset in XC886/888 is the hardware reset. This reset function can be
used during normal operation or when the chip is in power-down mode. A reset input pin
RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
Data Sheet
70
V1.2, 2009-07
XC886/888CLM
Functional Description
3.7.1
Module Reset Behavior
Table 22 lists the functions of the XC886/888 and the various reset types that affect
these functions. The symbol “■” signifies that the particular function is reset to its default
state.
Table 22
Effect of Reset on Device Functions
Module/
Wake-Up
Watchdog Hardware
Power-On
Reset
■
Brownout
Reset
■
Function
Reset
Reset
■
Reset
■
CPU Core
Peripherals
■
■
■
■
■
■
On-Chip
Not affected, Not affected, Not affected, Affected, un- Affected, un-
Static RAM
Reliable
Reliable
Reliable
reliable
reliable
Oscillator,
■
Not affected ■
■
■
PLL
Port Pins
EVR
■
■
■
■
■
■
■
The voltage Not affected ■
regulator is
switched on
FLASH
NMI
■
■
■
■
■
■
■
■
Disabled
Disabled
3.7.2
Booting Scheme
When the XC886/888 is reset, it must identify the type of configuration with which to start
the different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 23
shows the available boot options in the XC886/888.
Table 23
XC886/888 Boot Selection
MBC TMS P0.0 Type of Mode
PC Start Value
User Mode1); on-chip OSC/PLL non-bypassed 0000H
BSL Mode; on-chip OSC/PLL non-bypassed2) 0000H
1
0
0
0
0
1
X
X
0
OCDS Mode; on-chip OSC/PLL non-
bypassed
0000H
1
1
0
User (JTAG) Mode3); on-chip OSC/PLL non- 0000H
bypassed (normal)
Data Sheet
71
V1.2, 2009-07
XC886/888CLM
Functional Description
1) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals
zero.
2) OSC is bypassed in MultiCAN BSL mode
3) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Note: The boot options are valid only with the default set of UART and JTAG pins.
3.8
Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC886/888. The power consumption is indirectly proportional to the frequency, whereas
the performance of the microcontroller is directly proportional to the frequency. During
user program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features
• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support
The CGU consists of an oscillator circuit and a PLL. In the XC886/888, the oscillator can
be from either of these two sources: the on-chip oscillator (9.6 MHz) or the external
oscillator (4 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip
oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip
oscillator will be used by default.The external oscillator can be selected via software. In
addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock
detection. This allows emergency routines to be executed for system recovery or to
perform system shut down.
Data Sheet
72
V1.2, 2009-07
XC886/888CLM
Functional Description
osc fail
detect
OSCR
LOCK
lock
detect
OSC
P:1
fsys
PLL
core
fvco
fosc
K:1
fp
fn
N:1
PLLBYP
OSCDISC
VCOBYP
NDIV
Figure 24
CGU Block Diagram
PLL Base Mode
When the oscillator is disconnected from the PLL, the system clock is derived from the
VCO base (free running) frequency clock (Table 25) divided by the K factor.
1
---
K
f
= f
×
SYS
VCObase
(3.1)
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided
by the P and K factors.
1
-------------
f
= f
×
SYS
OSC
P × K
(3.2)
Data Sheet
73
V1.2, 2009-07
XC886/888CLM
Functional Description
PLL Mode
The system clock is derived from the oscillator clock, multiplied by the N factor, and
divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for
this PLL mode. The PLL mode is used during normal system operation.
N
-------------
f
= f
×
SYS
OSC
P × K
(3.3)
System Frequency Selection
For the XC886/888, the value of P is fixed to 1. In order to obtain the required fsys, the
value of N and K can be selected by bits NDIV and KDIV respectively for different
oscillator inputs. The output frequency must always be configured for 96 MHz. Table 24
provides examples on how fsys = 96 MHz can be obtained for the different oscillator
sources.
Table 24
Oscillator
On-chip
System frequency (fsys = 96 MHz)
Fosc
N
P
1
1
1
1
K
2
2
2
2
Fsys
9.6 MHz
8 MHz
6 MHz
4 MHz
20
24
32
48
96 MHz
96 MHz
96 MHz
96 MHz
External
Data Sheet
74
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 25 shows the VCO range for the XC886/888.
Table 25
fVCOmin
150
VCO Range
fVCOmax
200
fVCOFREEmin
20
10
fVCOFREEmax
80
80
Unit
MHz
MHz
100
150
3.8.1
Recommended External Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz
to 12 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and
depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1
and CX2 values shown in Figure 25 can be used as starting points for the negative
resistance evaluation and for non-productive systems. The exact values and related
operating range are dependent on the crystal frequency and have to be determined and
optimized together with the crystal vendor using the negative resistance method.
Oscillation measurement with the final target system is strongly recommended to verify
the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin
negative resistance) for the oscillator-crystal system.
When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is
left open (unconnected).
The oscillator can also be used in combination with a ceramic resonator. The final
circuitry must also be verified by the resonator vendor. Figure 25 shows the
recommended external oscillator circuitries for both operating modes, external crystal
mode and external input clock mode.
Data Sheet
75
V1.2, 2009-07
XC886/888CLM
Functional Description
fOSC
fOSC
External Clock
Signal
XTAL1
XC886/888
XTAL1
4 - 12
MHz
XC886/888
Oscillator
Oscillator
RQ
RX2
CX2
XTAL2
XTAL2
CX1
Fundamental
Mode Crystal
VSS
VSS
1)
1)
RX2
Crystal Frequency CX1, CX2
4 MHz
33 pF
18 pF
15 pF
12 pF
0
0
0
0
8 MHz
10 MHz
12 MHz
Clock_EXOSC
1) Note that these are evaluation start values!
Figure 25
External Oscillator Circuitry
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
Data Sheet
76
V1.2, 2009-07
XC886/888CLM
Functional Description
3.8.2
Clock Management
The CGU generates all clock signals required within the microcontroller from a single
clock, fsys. During normal system operation, the typical frequencies of the different
modules are as follow:
• CPU clock: CCLK, SCLK = 24 MHz
• Fast clock (used by MultiCAN): FCLK = 24 or 48 MHz
• Peripheral clock: PCLK = 24 MHz
• Flash Interface clock: CCLK2 = 48 MHz and CCLK = 24 MHz
In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The
clock output frequency, which is derived from the clock output divider (bit COREL), can
further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output
frequency has a 50% duty cycle. Figure 26 shows the clock distribution of the
XC886/888.
FCCFG
FCLK
CLKREL
MultiCAN
SD
PCLK
Peripherals
CORE
1
0
SCLK
CCLK
fsys=
/2
96MHz
fosc
OSC
PLL
/2
FLASH
CCLK2
Interface
COREL
N,P,K
TLEN
Toggle
Latch
CLKOUT
COUTS
Figure 26
Clock Generation from fsys
Data Sheet
77
V1.2, 2009-07
XC886/888CLM
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 26.
Table 26
System frequency (fsys = 96 MHz)
Power Saving Mode Action
Idle
Clock to the CPU is disabled.
Slow-down
Clocks to the CPU and all the peripherals are divided by a
common programmable factor defined by bit field
CMCON.CLKREL.
Power-down
Oscillator and PLL are switched off.
Data Sheet
78
V1.2, 2009-07
XC886/888CLM
Functional Description
3.9
Power Saving Modes
The power saving modes of the XC886/888 provide flexible power consumption through
a combination of techniques, including:
• Stopping the CPU clock
• Stopping the clocks of individual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 27) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode
ACTIVE
any interrupt
& SD=0
EXINT0/RXD pin
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
clear SD
bit
POWER-DOWN
IDLE
set IDLE
bit
set PD
bit
any interrupt
& SD=1
EXINT0/RXD pin
& SD=1
SLOW-DOWN
Figure 27
Transition between Power Saving Modes
Data Sheet
79
V1.2, 2009-07
XC886/888CLM
Functional Description
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC886/888 system reset. Hence, routine service of the WDT
confirms that the system is functioning properly. This ensures that an accidental
malfunction of the XC886/888 will be aborted in a user-specified time period.
In debug mode, the WDT is default suspended and stops counting. Therefore, there is
no need to refresh the WDT during debugging.
Features
• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of fPCLK/2 or fPCLK/128
• Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit
timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be
preset to a user-programmable value via a watchdog service access in order to modify
the watchdog expire time period. The lower 8 bits are reset on each service access.
Figure 28 shows the block diagram of the WDT unit.
WDT
WDTREL
Control
Clear
WDT Low Byte
1:2
MUX
WDT High Byte
fPCLK
1:128
Overflow/Time-out Control &
Window-boundary control
FNMIWDT
WDTRST
.
WDTIN
ENWDT
Logic
ENWDT_P
WDTWINB
Figure 28
WDT Block Diagram
Data Sheet
80
V1.2, 2009-07
XC886/888CLM
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is
entered. The prewarning period lasts for 30H count, after which the system is reset
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000H to the value obtained from the concatenation of WDTWINB and
00H.
After being serviced, the WDT continues counting up from the value (<WDTREL> * 28).
The time period for an overflow of the WDT is programmable in two ways:
• The input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128
• The reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
The period, PWDT, between servicing the WDT and the next overflow can be determined
by the following formula:
(1 + WDTIN × 6)
16
8
2
× (2 – WDTREL × 2 )
P
= ---------------------------------------------------------------------------------------------------------
WDT
f
PCLK
(3.4)
If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 29. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be
smaller than WDTREL.
Data Sheet
81
V1.2, 2009-07
XC886/888CLM
Functional Description
Count
FFFFH
WDTWINB
WDTREL
time
No refresh
allowed
Refresh allowed
Figure 29
WDT Timing Diagram
Table 27 lists the possible watchdog time ranges that can be achieved using a certain
module clock. Some numbers are rounded to 3 significant digits.
Table 27
Reload value
In WDTREL
Watchdog Time Ranges
Prescaler for fPCLK
2 (WDTIN = 0)
24 MHz
128 (WDTIN = 1)
24 MHz
FFH
7FH
00H
21.3 µs
2.75 ms
5.46 ms
1.37 ms
176 ms
350 ms
Data Sheet
82
V1.2, 2009-07
XC886/888CLM
Functional Description
3.11
Multiplication/Division Unit
The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and
32-bit division as well as shift and normalize features. It has been integrated to support
the XC886/888 Core in real-time control applications, which require fast mathematical
computations.
Features
• Fast signed/unsigned 16-bit multiplication
• Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations
• 32-bit unsigned normalize operation
• 32-bit arithmetic/logical shift operations
Table 28 specifies the number of clock cycles used for calculation in various operations.
Table 28
MDU Operation Characteristics
Operation
Result
Remainder
No. of Clock Cycles
used for calculation
Signed 32-bit/16-bit
Signed 16-bit/16bit
Signed 16-bit x 16-bit
Unsigned 32-bit/16-bit
Unsigned 16-bit/16-bit
Unsigned 16-bit x 16-bit 32-bit
32-bit normalize
32-bit shift L/R
32-bit
16-bit
32-bit
32-bit
16-bit
16-bit
16-bit
-
16-bit
16-bit
-
-
-
33
17
16
32
16
16
-
-
No. of shifts + 1 (Max. 32)
No. of shifts + 1 (Max. 32)
Data Sheet
83
V1.2, 2009-07
XC886/888CLM
Functional Description
3.12
CORDIC Coprocessor
The CORDIC Coprocessor provides CPU with hardware support for the solving of
circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions.
Features
• Modes of operation
– Supports all CORDIC operating modes for solving circular (trigonometric), linear
(multiply-add, divide-add) and hyperbolic functions
– Integrated look-up tables (LUTs) for all operating modes
• Circular vectoring mode: Extended support for values of initial X and Y data up to full
range of [-215,(215-1)] for solving angle and magnitude
• Circular rotation mode: Extended support for values of initial Z data up to full range
of [-215,(215-1)], representing angles in the range [-π,((215-1)/215)π] for solving
trigonometry
• Implementation-dependent operational frequency of up to 80 MHz
• Gated clock input to support disabling of module
• 16-bit accessible data width
– 24-bit kernel data width plus 2 overflow bits for X and Y each
– 20-bit kernel data width plus 1 overflow bit for Z
– With KEEP bit to retain the last value in the kernel register for a new calculation
• 16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start
(ST) bit to set of end-of-calculation flag, excluding time taken for write and read
access of data bytes.
• Twos complement data processing
– Only exception: X result data with user selectable option for unsigned result
• X and Y data generally accepted as integer or rational number; X and Y must be of
the same data form
• Entries of LUTs are 20-bit signed integers
– Entries of atan and atanh LUTs are integer representations (S19) of angles with
the scaling such that [-215,(215-1)] represents the range [-π,((215-1)/215)π]
– Accessible Z result data for circular and hyperbolic functions is integer in data form
of S15
• Emulated LUT for linear function
– Data form is 1 integer bit and 15-bit fractional part (1.15)
– Accessible Z result data for linear function is rational number with fixed data form
of S4.11 (signed 4Q16)
• Truncation Error
– The result of a CORDIC calculation may return an approximation due to truncation
of LSBs
– Good accuracy of the CORDIC calculated result data, especially in circular mode
• Interrupt
– On completion of a calculation
Data Sheet
84
V1.2, 2009-07
XC886/888CLM
Functional Description
– Interrupt enabling and corresponding flag
3.13
UART and UART1
The XC886/888 provides two Universal Asynchronous Receiver/Transmitter (UART and
UART1) modules for full-duplex asynchronous reception/transmission. Both are also
receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– Fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception
The UART modules can operate in the four modes shown in Table 29.
Table 29
UART Modes
Operating Mode
Baud Rate
PCLK/2
Variable
PCLK/32 or fPCLK/641)
Variable
Mode 0: 8-bit shift register
Mode 1: 8-bit shift UART
Mode 2: 9-bit shift UART
Mode 3: 9-bit shift UART
f
f
1) For UART1 module, the baud rate is fixed at fPCLK/64.
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
f
PCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock
and can be configured to eitherfPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is
available. The variable baud rate is set by the underflow rate on the dedicated baud-rate
generator. For UART module, the variable baud rate alternatively can be set by the
overflow rate on Timer 1.
3.13.1
Baud-Rate Generator
Both UART modules have their own dedicated baud-rate generator, which is based on
a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and
Data Sheet
85
V1.2, 2009-07
XC886/888CLM
Functional Description
fractional divider) for generating a wide range of baud rates based on its input clock fPCLK
see Figure 30.
,
Fractional Divider
8-Bit Reload Value
FDSTEP
1
FDEN&FDM
FDM
1
0
Adder
fDIV
00
01
0
1
fBR
8-Bit Baud Rate Timer
0
11
10
fMOD
FDRES
(overflow)
FDEN
R
fDIV
fPCLK
Prescaler
clk
11
10
NDOV
01
00
‘0’
Figure 30
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the
output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14.
The baud rate (fBR) value is dependent on the following parameters:
• Input clock fPCLK
• Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional
divider mode)
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
Data Sheet
86
V1.2, 2009-07
XC886/888CLM
Functional Description
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
f
BRPRE
PCLK
------------------------------------------------------------------------------------
baud rate =
where 2
× (BR_VALUE + 1) > 1
BRPRE
16 × 2
× (BR_VALUE + 1)
(3.5)
(3.6)
f
STEP
PCLK
------------------------------------------------------------------------------------ --------------
baud rate =
×
BRPRE
256
16 × 2
× (BR_VALUE + 1)
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20 kHz to 115.2 kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 30 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 30
Typical Baud rates for UART with Fractional Divider disabled
Baud rate
Prescaling Factor Reload Value
Deviation Error
(2BRPRE)
(BR_VALUE + 1)
78 (4EH)
19.2 kBaud
9600 Baud
4800 Baud
2400 Baud
1 (BRPRE=000B)
1 (BRPRE=000B)
2 (BRPRE=001B)
4 (BRPRE=010B)
0.17 %
0.17 %
0.17 %
0.17 %
156 (9CH)
156 (9CH)
156 (9CH)
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 31 lists the resulting deviation errors from generating a baud rate of
115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
87
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 31
Deviation Error for UART with Fractional Divider enabled
fPCLK
Prescaling Factor Reload Value
STEP
Deviation
(2BRPRE)
(BR_VALUE + 1)
10 (AH)
Error
24 MHz
12 MHz
8 MHz
6 MHz
1
1
1
1
197 (C5H)
236 (ECH)
236 (ECH)
236 (ECH)
+0.20 %
+0.03 %
+0.03 %
+0.03 %
6 (6H)
4 (4H)
3 (3H)
3.13.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
SMOD
2
× f
PCLK
Mode 1, 3 baud rate= ----------------------------------------------------
32 × 2 × (256 – TH1)
(3.7)
3.14
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 30). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.
The output frequency in normal divider mode is derived as follows:
1
-----------------------------
256 – STEP
f
= f
×
MOD
DIV
(3.8)
Data Sheet
88
V1.2, 2009-07
XC886/888CLM
Functional Description
3.15
LIN Protocol
The UART module can be used to support the Local Interconnect Network (LIN) protocol
for both master and slave operations. The LIN baud rate detection feature, which
consists of the hardware logic for Break and Synch Byte detection, provides the
capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART
to be synchronized to the LIN baud rate for data transmission and reception.
Note: The LIN baud rate detection feature is available for use only with UART. To use
UART1 for LIN communication, software has to be implemented to detect the
Break and Synch Byte.
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multiple-
slave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 31. The frame consists of the:
• Header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field
• Response time
• Data bytes (according to UART protocol)
• Checksum
Frame slot
Frame
Response
space
Header
Response
Checksum
Data 2 Data N
Protected
identifier
Data 1
Synch
Figure 31
3.15.1
Structure of LIN Frame
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
Data Sheet
89
V1.2, 2009-07
XC886/888CLM
Functional Description
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet
90
V1.2, 2009-07
XC886/888CLM
Functional Description
3.16
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 32 shows the block diagram of the SSC.
Data Sheet
91
V1.2, 2009-07
XC886/888CLM
Functional Description
PCLK
SS_CLK
MS_CLK
Baud-rate
Generator
Clock
Control
Shift
Clock
RIR
TIR
EIR
Receive Int. Request
Transmit Int. Request
Error Int. Request
SSC Control Block
Register CON
Status
Control
TXD(Master)
RXD(Slave)
Pin
Control
16-Bit Shift
Register
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 32
SSC Block Diagram
Data Sheet
92
V1.2, 2009-07
XC886/888CLM
Functional Description
3.17
Timer 0 and Timer 1
Timer 0 and Timer 1 can function as both timers or counters. When functioning as a
timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input
clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are
incremented in response to a 1-to-0 transition (falling edge) at their respective external
input pins, T0 or T1.
Timer 0 and 1 are fully compatible and can be configured in four different operating
modes for use in a variety of applications, see Table 32. In modes 0, 1 and 2, the two
timers operate independently, but in mode 3, their functions are specialized.
Table 32
Mode
0
Timer 0 and Timer 1 Modes
Operation
13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
1
2
3
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet
93
V1.2, 2009-07
XC886/888CLM
Functional Description
3.18
Timer 2 and Timer 21
Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible
and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel
capture mode, see Table 33. As a timer, the timers count with an input clock of PCLK/12
(if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the
counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is
disabled).
Table 33
Mode
Timer 2 Modes
Description
Auto-reload Up/Down Count Disabled
• Count up only
• Start counting from 16-bit reload value, overflow at FFFFH
• Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event
Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up
– Start counting from 16-bit reload value, overflow at FFFFH
– Reload event triggered by overflow condition
– Programmble reload value in register RC2
• Count down
– Start counting from FFFFH, underflow at value defined in register
RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFFH
Channel
capture
• Count up only
• Start counting from 0000H, overflow at FFFFH
• Reload event triggered by overflow condition
• Reload value fixed at 0000H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value stored in register RC2
• Interrupt is generated with reload or capture event
Data Sheet
94
V1.2, 2009-07
XC886/888CLM
Functional Description
3.19
Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which
can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor
control. The CCU6 also supports special control modes for block commutation and
multi-phase machines.
The timer T12 can function in capture and/or compare mode for its three channels. The
timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
Timer T12 Features
• Three capture/compare channels, each channel can be used either as a capture or
as a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for
highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode
Timer T13 Features
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at period-match and compare-match
• Supports single-shot mode
Additional Features
• Implements block commutation for Brushless DC-drives
• Position detection via Hall-sensor pattern
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP)
• Control modes for multi-channel AC-drives
• Output levels can be selected and adapted to the power stage
The block diagram of the CCU6 module is shown in Figure 33.
Data Sheet
95
V1.2, 2009-07
XC886/888CLM
Functional Description
module kernel
compare
channel 0
channel 1
channel 2
address
decoder
1
1
1
dead-
time
multi-
trap
T12
channel
control
control
control
clock
control
start
T13
channel 3
compare
interrupt
control
1
3
2
2
2
3
1
input / output control
port control
CCU6_block_diagram
Figure 33
CCU6 Block Diagram
Data Sheet
96
V1.2, 2009-07
XC886/888CLM
Functional Description
3.20
Controller Area Network (MultiCAN)
The MultiCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN
node can receive and transmit standard frames with 11-bit identifiers as well as extended
frames with 29-bit identifiers.
Both CAN nodes share a common set of message objects, where each message object
may be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects may be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double chained lists, where each CAN node has
it’s own list of message objects. A CAN node stores frames only into message objects
that are allocated to the list of the CAN node. It only transmits messages from objects of
this list. A powerful, command driven list controller performs all list operations.
The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are
programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects
each CAN node to a bus transceiver.
MultiCANModule Kernel
CANSRC[7:0]
Interrupt
Controller
TXDC1
Message
Object
Buffer
CAN
fCAN
Clock
Node 1
Linked
List
Control
RXDC1
TXDC0
RXDC0
Port
Control
Control
CAN
32
Node 0
Objects
A[13: 2]
D[31:0]
Address
Decoder &
Data
control
CAN Control
AccessMediator
MultiCAN_XC8_overview
Figure 34
Features
Overview of the MultiCAN
• Compliant to ISO 11898.
Data Sheet
97
V1.2, 2009-07
XC886/888CLM
Functional Description
• CAN functionality according to CAN specification V2.0 B active.
• Dedicated control registers are provided for each CAN node.
• A data transfer rate up to 1 MBaud is supported.
• Flexible and powerful message transfer control and error handling capabilities are
implemented.
• Advanced CAN bus bit timing analysis and baud rate detection can be performed for
each CAN node via the frame counter.
• Full-CAN functionality: A set of 32 message objects can be individually
– allocated (assigned) to any CAN node
– configured as transmit or receive object
– setup to handle frames with 11-bit or 29-bit identifier
– counted or assigned a timestamp via a frame counter
– configured to remote monitoring mode
• Advanced Acceptance Filtering:
– Each message object provides an individual acceptance mask to filter incoming
frames.
– A message object can be configured to accept only standard or only extended
frames or to accept both standard and extended frames.
– Message objects can be grouped into 4 priority classes.
– The selection of the message to be transmitted first can be performed on the basis
of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.
• Advanced Message Object Functionality:
– Message Objects can be combined to build FIFO message buffers of arbitrary
size, which is only limited by the total number of message objects.
– Message objects can be linked to form a gateway to automatically transfer frames
between 2 different CAN buses. A single gateway can link any two CAN nodes. An
arbitrary number of gateways may be defined.
• Advanced Data Management:
– The Message objects are organized in double chained lists.
– List reorganizations may be performed any time, even during full operation of the
CAN nodes.
– A powerful, command driven list controller manages the organization of the list
structure and ensures consistency of the list.
– Message FIFOs are based on the list structure and can easily be scaled in size
during CAN operation.
– Static Allocation Commands offer compatibility with TwinCAN applications, which
are not list based.
• Advanced Interrupt Handling:
– Up to 8 interrupt output lines are available. Most interrupt requests can be
individually routed to one of the 8 interrupt output lines.
– Message postprocessing notifications can be flexibly aggregated into a dedicated
register field of 64 notification bits.
Data Sheet
98
V1.2, 2009-07
XC886/888CLM
Functional Description
3.21
Analog-to-Digital Converter
The XC886/888 includes a high-performance 10-bit Analog-to-Digital Converter (ADC)
with eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at Port 2.
Features
• Successive approximation
• 8-bit or 10-bit resolution
(TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access
(wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter
(accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes
3.21.1
ADC Clocking Scheme
A common module clock fADC generates the various clock signals used by the analog and
digital parts of the ADC module:
• fADCA is input clock for the analog part.
• fADCI is internal clock for the analog part (defines the time base for conversion length
and the sample time). This clock is generated internally in the analog part, based on
the input clock fADCA to generate a correct duty cycle for the analog components.
• fADCD is input clock for the digital part.
The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz.
Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI
does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register
Data Sheet
99
V1.2, 2009-07
XC886/888CLM
Functional Description
GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of
the ADC is not required.
fADC = fPCLK
fADCD
arbiter
registers
interrupts
digital part
fADCA
CTC
MUX
÷32
÷ 4
÷3
fADCI
analog
components
÷ 2
clock prescaler
analog part
1
fADCI
Condition: f ADCI 10 MHz, where t ADCI =
≤
Figure 35
ADC Clocking Scheme
For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as
shown in Table 34.
Table 34
fADCI Frequency Selection
Module Clock fADC
CTC
Prescaling Ratio Analog Clock fADCI
24 MHz
00B
÷ 2
12 MHz (N.A)
01B
10B
11B (default)
÷ 3
÷ 4
÷ 32
8 MHz
6 MHz
750 kHz
As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is
24 MHz. During slow-down mode where fADC may be reduced to 12 MHz, 6 MHz etc.,
CTC can be set to 00B as long as the divided analog clock fADCI does not exceed 10 MHz.
Data Sheet
100
V1.2, 2009-07
XC886/888CLM
Functional Description
However, it is important to note that the conversion error could increase due to loss of
charges on the capacitors, if fADC becomes too low during slow-down mode.
3.21.2
ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
• Synchronization phase (tSYN
)
• Sample phase (tS)
• Conversion phase
• Write result phase (tWR)
conversion start
trigger
Source
Channel
interrupt
Result
interrupt
interrupt
Sample Phase
Conversion Phase
fADCI
BUSY Bit
SAMPLE Bit
tSYN
tS
Write Result Phase
tWR
tCONV
Figure 36
ADC Conversion Timing
Data Sheet
101
V1.2, 2009-07
XC886/888CLM
Functional Description
3.22
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
• Use the built-in debug functionality of the XC800 Core
• Add a minimum of hardware overhead
• Provide support for most of the operations by a Monitor Program
• Use standard interfaces to communicate with the Host (a Debugger)
Features
• Set breakpoints on instruction address and on address range within the Program
Memory
• Set breakpoints on internal RAM address range
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks via JTAG and upon activating a dedicated pin
• Step through the program code
The OCDS functional blocks are shown in Figure 37. The Monitor Mode Control (MMC)
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals.
After processing memory address and control signals from the core, the MMC provides
proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and
a Monitor RAM (for work-data and Monitor-stack).
The OCDS system is accessed through the JTAG1), which is an interface dedicated
exclusively for testing and debugging activities and is not normally used in an
application. The dedicated MBC pin is used for external configuration and debugging
control.
Note: All the debug functionality described here can normally be used only after
XC886/888 has been started in OCDS mode.
1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports
(Ports 1 and 2/Port 5).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet
102
V1.2, 2009-07
XC886/888CLM
Functional Description
JTAG Module
Memory
Control
Unit
TMS
TCK
TDI
TCK
TDI
Debug
JTAG
Interface
User
Boot/
TDO
TDO
Program Monitor
Control
Memory
ROM
Reset
Monitor Mode Control
MBC
Monitor &
Bootstrap loader
Control line
User
Internal
RAM
Monitor
RAM
Suspend
Control
System
Control
Unit
Reset
Clock
Reset Clock Debug PROG PROG Memory
Interface & IRAM Data Control
Addresses
- parts of
OCDS
XC800 Core
OCDS_XC886C-Block_Diagram-UM-v0.2
Figure 37
3.22.1
OCDS Block Diagram
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is
also true immediately after reset.
The JTAG ID register contents for the XC886/888 Flash devices are given in Table 35.
Table 35
Device Type
Flash
JTAG ID Summary
Device Name
JTAG ID
XC886/888*-8FF
XC886/888*-6FF
XC886/888*-8RF
XC886/888*-6RF
1012 0083H
1012 5083H
1013 C083H
1013 D083H
ROM
Note: The asterisk (*) above denotes all possible device configurations.
Data Sheet
103
V1.2, 2009-07
XC886/888CLM
Functional Description
3.23
Chip Identification Number
The XC886/888 identity (ID) register is located at Page 1 of address B3H. The value of
ID register is 09H for Flash devices and 22H for ROM devices. However, for easy
identification of product variants, the Chip Identification Number, which is an unique
number assigned to each product variant, is available. The differentiation is based on the
product, variant type and device step information.
Two methods are provided to read a device’s chip identification number:
• In-application subroutine, GET_CHIP_INFO
• Bootstrap loader (BSL) mode A
Table 36 lists the chip identification numbers of available XC886/888 Flash and ROM
device variants.
Table 36
Chip Identification Number
Product Variant
Chip Identification Number
AA-Step
AB-Step
AC-Step
Flash Devices
XC886CLM-8FFA 3V3
XC888CLM-8FFA 3V3
XC886LM-8FFA 3V3
XC888LM-8FFA 3V3
XC886CLM-6FFA 3V3
XC888CLM-6FFA 3V3
XC886LM-6FFA 3V3
XC888LM-6FFA 3V3
XC886CM-8FFA 3V3
XC888CM-8FFA 3V3
XC886C-8FFA 3V3
XC888C-8FFA 3V3
XC886-8FFA 3V3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
09500102H
09500103H
09500122H
09500123H
09551502H
09551503H
09551522H
09551523H
09580102H
09580103H
09580142H
09580143H
09580162H
09580163H
095D1502H
095D1503H
095D1542H
095D1543H
0B500102H
0B500103H
0B500122H
0B500123H
0B551502H
0B551503H
0B551522H
0B551523H
0B580102H
0B580103H
0B580142H
0B580143H
0B580162H
0B580163H
0B5D1502H
0B5D1503H
0B5D1542H
0B5D1543H
XC888-8FFA 3V3
XC886CM-6FFA 3V3
XC888CM-6FFA 3V3
XC886C-6FFA 3V3
XC888C-6FFA 3V3
Data Sheet
104
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 36
Chip Identification Number (cont’d)
Product Variant
Chip Identification Number
AA-Step
AB-Step
AC-Step
XC886-6FFA 3V3
XC888-6FFA 3V3
XC886CLM-8FFA 5V
XC888CLM-8FFA 5V
XC886LM-8FFA 5V
XC888LM-8FFA 5V
XC886CLM-6FFA 5V
XC888CLM-6FFA 5V
XC886LM-6FFA 5V
XC888LM-6FFA 5V
XC886CM-8FFA 5V
XC888CM-8FFA 5V
XC886C-8FFA 5V
XC888C-8FFA 5V
XC886-8FFA 5V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
095D1562H
095D1563H
09900102H
09900103H
09900122H
09900123H
09951502H
09951503H
09951522H
09951523H
09980102H
09980103H
09980142H
09980143H
09980162H
09980163H
099D1502H
099D1503H
099D1542H
099D1543H
099D1562H
099D1563H
0B5D1562H
0B5D1563H
0B900102H
0B900103H
0B900122H
0B900123H
0B951502H
0B951503H
0B951522H
0B951523H
0B980102H
0B980103H
0B980142H
0B980143H
0B980162H
0B980163H
0B9D1502H
0B9D1503H
0B9D1542H
0B9D1543H
0B9D1562H
0B9D1563H
XC888-8FFA 5V
XC886CM-6FFA 5V
XC888CM-6FFA 5V
XC886C-6FFA 5V
XC888C-6FFA 5V
XC886-6FFA 5V
XC888-6FFA 5V
ROM Devices
XC886CLM-8RFA 3V3
XC888CLM-8RFA 3V3
XC886LM-8RFA 3V3
XC888LM-8RFA 3V3
XC886CLM-6RFA 3V3
XC888CLM-6RFA 3V3
22400502H
22400503H
22400522H
22400523H
22411502H
22411503H
-
-
-
-
-
-
-
-
-
-
-
-
Data Sheet
105
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 36
Chip Identification Number (cont’d)
Product Variant
Chip Identification Number
AA-Step
AB-Step
AC-Step
XC886LM-6RFA 3V3
XC888LM-6RFA 3V3
XC886CM-8RFA 3V3
XC888CM-8RFA 3V3
XC886C-8RFA 3V3
XC888C-8RFA 3V3
XC886-8RFA 3V3
22411522H
22411523H
22480502H
22480503H
22480542H
22480543H
22480562H
22480563H
22491502H
22491503H
22491542H
22491543H
22491562H
22491563H
22800502H
22800503H
22800522H
22800523H
22811502H
22811503H
22811522H
22811523H
22880502H
22880503H
22880542H
22880543H
22880562H
22880563H
22891502H
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
XC888-8RFA 3V3
XC886CM-6RFA 3V3
XC888CM-6RFA 3V3
XC886C-6RFA 3V3
XC888C-6RFA 3V3
XC886-6RFA 3V3
XC888-6RFA 3V3
XC886CLM-8RFA 5V
XC888CLM-8RFA 5V
XC886LM-8RFA 5V
XC888LM-8RFA 5V
XC886CLM-6RFA 5V
XC888CLM-6RFA 5V
XC886LM-6RFA 5V
XC888LM-6RFA 5V
XC886CM-8RFA 5V
XC888CM-8RFA 5V
XC886C-8RFA 5V
XC888C-8RFA 5V
XC886-8RFA 5V
XC888-8RFA 5V
XC886CM-6RFA 5V
Data Sheet
106
V1.2, 2009-07
XC886/888CLM
Functional Description
Table 36
Chip Identification Number (cont’d)
Product Variant
Chip Identification Number
AA-Step
AB-Step
AC-Step
XC888CM-6RFA 5V
XC886C-6RFA 5V
XC888C-6RFA 5V
XC886-6RFA 5V
XC888-6RFA 5V
22891503H
22891542H
22891543H
22891562H
22891563H
-
-
-
-
-
-
-
-
-
-
Data Sheet
107
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4
Electrical Parameters
Chapter 4 provides the characteristics of the electrical parameters which are
implementation-specific for the XC886/888.
4.1
General Parameters
The general parameters are described here to aid the users in interpreting the
parameters mainly in Section 4.2 and Section 4.3.
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the
XC886/888 and partly its requirements on the system. To aid interpreting the parameters
easily when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
• CC
These parameters indicate Controller Characteristics, which are distinctive features
of the XC886/888 and must be regarded for a system design.
• SR
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC886/888 is designed in.
Data Sheet
108
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC886/888 can be subjected to
without permanent damage.
Table 4-1
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
min.
-40
-65
-40
-0.5
max.
125
150
150
6
Ambient temperature
Storage temperature
Junction temperature
TA
TST
TJ
°C
°C
°C
V
under bias
1)
under bias1)
1)
Voltage on power supply pin with VDDP
respect to VSS
Voltage on any pin with respect VIN
to VSS
-0.5
VDDP
+
V
whichever is
lower1)
0.5 or
max. 6
1)
Input current on any pin during
overload condition
IIN
-10
–
10
50
mA
mA
1)
Absolute sum of all input currents Σ|IIN|
during overload condition
1) Not subjected to production test, verified by design/characterization.
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pin with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
109
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.1.3
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC886/888. All parameters mentioned in the following table refer to
these operating conditions, unless otherwise noted.
Table 37
Parameter
Operating Condition Parameters
Symbol Limit Values
Unit Notes/
Conditions
min.
4.5
3.0
0
max.
5.5
3.6
Digital power supply voltage VDDP
Digital power supply voltage VDDP
V
5V Device
V
3.3V Device
Digital ground voltage
Digital core supply voltage
System Clock Frequency1)
Ambient temperature
VSS
VDDC
fSYS
TA
V
2.3
88.8
-40
2.7
103.2
85
V
MHz
°C
SAF-
XC886/888...
-40
125
°C
SAK-
XC886/888...
1) fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 4. Please refer to Figure 26
for detailed description.
Data Sheet
110
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.2
DC Parameters
The electrical characteristics of the DC Parameters are detailed in this section.
4.2.1
Input/Output Characteristics
Table 38 provides the characteristics of the input/output pins of the XC886/888.
Table 38
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
V
DDP = 5 V Range
Output low voltage
VOL
CC –
1.0
1.0
V
V
IOL = 15 mA
–
–
IOL = 5 mA, current into
all pins > 60 mA
0.4
V
V
V
V
V
IOL = 5 mA, current into
all pins ≤ 60 mA
Output high voltage
VOH
CC VDDP - –
IOH = -15 mA
1.0
V
DDP - –
I
OH = -5 mA, current
1.0
from all pins > 60 mA
V
DDP - –
IOH = -5 mA, current
0.4
from all pins ≤ 60 mA
Input low voltage on
port pins
(all except P0.0 & P0.1)
VILP
SR –
0.3 ×
VDDP
CMOS Mode
Input low voltage on
P0.0 & P0.1
Input low voltage on
RESET pin
Input low voltage on
TMS pin
Input high voltage on
port pins
(all except P0.0 & P0.1)
VILP0 SR -0.2
0.3 ×
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode
CMOS Mode
VDDP
VILR
VILT
VIHP
SR –
SR –
0.3 ×
VDDP
0.3 ×
VDDP
SR 0.7 ×
–
VDDP
Input high voltage on
P0.0 & P0.1
VIHP0 SR 0.7 × VDDP
V
CMOS Mode
VDDP
Data Sheet
111
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 38
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
Input high voltage on
RESET pin
Input high voltage on
TMS pin
VIHR
VIHT
SR 0.7 ×
–
V
V
V
V
V
CMOS Mode
CMOS Mode
VDDP
SR 0.75 × –
VDDP
Input Hysteresis on port HYSP CC 0.07 × –
CMOS Mode1)
pins
VDDP
1)
Input Hysteresis on
XTAL1
Input low voltage at
XTAL1
Input high voltage at
XTAL1
Pull-up current
HYSX CC 0.07 × –
VDDC
VILX
VIHX
IPU
SR VSS - 0.3 ×
0.5
VDDC
VDDC + V
SR 0.7 ×
VDDC 0.5
SR –
-150
SR –
150
CC -1
-10
–
10
–
1
µA VIHP,min
µA VILP,max
µA VILP,max
µA VIHP,min
Pull-down current
Input leakage current
IPD
IOZ1
µA 0 < VIN < VDDP
,
TA ≤ 125°C2)
Input current at XTAL1 IILX
CC -10
SR -5
10
5
µA
mA
Overloadcurrentonany IOV
pin
3)
Absolute sum of
overload currents
Voltage on any pin
during VDDP power off
Maximum current per
pin (excluding VDDP and
VSS)
Maximum current for all Σ|IM|
pins (excluding VDDP
and VSS)
Σ|IOV| SR –
SR –
IM SR SR –
25
0.3
15
mA
4)
VPO
V
mA
mA
SR –
90
3)
Maximum current into
VDDP
IMVDDP SR –
120
mA
Data Sheet
112
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 38
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
120
3)
Maximum current out of IMVSS SR –
mA
VSS
V
DDP = 3.3 V Range
Output low voltage
VOL
VOH
CC –
–
1.0
0.4
V
V
V
IOL = 8 mA
IOL = 2.5 mA
Output high voltage
CC VDDP - –
IOH = -8 mA
1.0
V
DDP - –
0.4
SR –
V
V
I
OH = -2.5 mA
Input low voltage on
port pins
(all except P0.0 & P0.1)
VILP
0.3 ×
VDDP
CMOS Mode
Input low voltage on
P0.0 & P0.1
Input low voltage on
RESET pin
Input low voltage on
TMS pin
Input high voltage on
port pins
(all except P0.0 & P0.1)
VILP0 SR -0.2
0.3 ×
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode
CMOS Mode
VDDP
VILR
VILT
VIHP
SR –
SR –
0.3 ×
VDDP
0.3 ×
VDDP
SR 0.7 ×
–
VDDP
Input high voltage on
P0.0 & P0.1
Input high voltage on
RESET pin
Input high voltage on
TMS pin
Input Hysteresis
VIHP0 SR 0.7 × VDDP
V
V
V
V
V
V
CMOS Mode
CMOS Mode
CMOS Mode
VDDP
VIHR
VIHT
HYS
SR 0.7 ×
–
VDDP
SR 0.75 × –
VDDP
CC 0.03 × –
CMOS Mode1)
VDDP
1)
Input Hysteresis on
XTAL1
Input low voltage at
XTAL1
HYSX CC 0.07 × –
VDDC
VILX
SR VSS - 0.3 ×
0.5
VDDC
Data Sheet
113
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 38
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
VDDC + V
Input high voltage at
XTAL1
Pull-up current
VIHX
IPU
SR 0.7 ×
VDDC 0.5
SR –
-50
SR –
50
CC -1
-5
–
5
–
µA VIHP,min
µA VILP,max
µA VILP,max
µA VIHP,min
Pull-down current
Input leakage current
IPD
IOZ1
1
µA 0 < VIN < VDDP
,
TA ≤ 125°C2)
Input current at XTAL1 IILX
CC - 10
SR -5
10
5
µA
mA
Overloadcurrentonany IOV
pin
3)
Absolute sum of
overload currents
Voltage on any pin
during VDDP power off
Maximum current per
pin (excluding VDDP and
VSS)
Maximum current for all Σ|IM|
pins (excluding VDDP
and VSS)
Σ|IOV| SR –
25
0.3
15
mA
4)
VPO
SR –
V
IM SR SR –
mA
mA
SR –
90
3)
Maximum current into
VDDP
IMVDDP SR –
120
120
mA
3)
Maximum current out of IMVSS SR –
mA
VSS
1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses
switching due to external system noise.
2) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and
RESET pin have internal pull devices and are not included in the input leakage current characteristic.
3) Not subjected to production test, verified by design/characterization.
4) Not subjected to production test, verified by design/characterization. However, for applications with strict low
power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin
when VDDP is powered off.
Data Sheet
114
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.2.2
Supply Threshold Characteristics
Table 39 provides the characteristics of the supply threshold in the XC886/888.
5.0V
VDDPPW
VDDP
2.5V
VDDCPW
VDDCBO
VDDCRDR
VDDCBOPD
VDDC
VDDCPOR
Figure 38
Supply Threshold Parameters
Table 39
Supply Threshold Parameters (Operating Conditions apply)
Parameters
Symbol
Limit Values
Unit
min.
CC 2.2
CC 2.0
typ.
2.3
2.1
max.
2.4
2.2
V
V
DDC prewarning voltage1)
DDC brownout voltage in
VDDCPW
VDDCBO
V
V
active mode1)
RAM data retention voltage
VDDCRDR CC 0.9
VDDCBOPD CC 1.3
1.0
1.5
1.1
1.7
V
V
V
DDC brownout voltage in
power-down mode2)
DDP prewarning voltage3)
Power-on reset voltage2)4)
V
VDDPPW
CC 3.4
4.0
1.5
4.6
1.7
V
V
VDDCPOR CC 1.3
1) Detection is disabled in power-down mode.
2) Detection is enabled in both active and power-down mode.
3) Detection is enabled for external power supply of 5.0V.
Detection must be disabled for external power supply of 3.3V.
4) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
Data Sheet
115
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.2.3
ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (VSS) must be
externally connected to one single star point in the system. The voltage difference
between the ground pins must not exceed 200mV.
Table 40
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Parameter
Symbol
Limit Values
min. typ . max.
Unit Test Conditions/
Remarks
1)
Analog reference
voltage
Analog reference
ground
Analog input
voltage range
ADC clocks
VAREF
VAGND
VAIN
SR VAGND VDDP VDDP
V
+ 1
+ 0.05
1)
SR VSS - VSS VAREF
V
0.05
- 1
SR VAGND
–
VAREF
V
fADC
fADCI
–
–
24
–
25.8
10
MHz module clock1)
MHz internal analog clock1)
See Figure 35
1)
Sample time
tS
CC (2 + INPCR0.STC) × µs
tADCI
1)
Conversion time
Total unadjusted
error
tC
|TUE|
CC See Section 4.2.3.1 µs
CC –
–
–
–
1
1
2
–
LSB 8-bit conversion2)
LSB 10-bit conversion2)
LSB 10-bit conversion1)
Differential
Nonlinearity
Integral
Nonlinearity
Offset
Gain
Overload current
coupling factor for
analog inputs
|EADNL| CC –
|EAINL| CC –
1
–
LSB 10-bit conversion1)
|EAOFF| CC –
|EAGAIN| CC –
KOVA
1
1
–
–
–
LSB 10-bit conversion1)
LSB 10-bit conversion1)
CC –
1.0 x
–
I
OV > 01)3)
10-4
–
–
1.5 x
10-3
–
I
OV < 01)3)
Data Sheet
116
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 40
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Parameter
Symbol
Limit Values
min. typ . max.
Unit Test Conditions/
Remarks
Overload current
coupling factor for
digital I/O pins
KOVD
CC –
–
5.0 x
–
I
OV > 01)3)
OV < 01)3)
10-3
–
–
1.0 x
10-2
–
I
1)4)
Switched
CAREFSW CC –
10
20
pF
capacitance at the
reference voltage
input
1)5)
Switched
CAINSW CC –
5
7
pF
capacitance at the
analog voltage
inputs
1)
1)
Input resistance of RAREF
CC –
CC –
1
1
2
kΩ
kΩ
the reference input
Input resistance of RAIN
theselectedanalog
channel
1.5
1) Not subjected to production test, verified by design/characterization
2) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDDP = 5.0 V.
3) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ1
|
+ (|IOV| × KOV). The additional error current may distort the input voltage on analog inputs.
4) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
5) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.
Data Sheet
117
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Analog Input Circuitry
REXT
RAIN, On
ANx
VAIN
CEXT
CAINSW
VAGNDx
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFSW
VAGNDx
Figure 39
ADC Input Circuits
Data Sheet
118
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.2.3.1 ADC Conversion Timing
Conversion time, tC = tADC × ( 1 + r × (3 + n + STC) ) , where
r = CTC + 2 for CTC = 00B, 01B or 10B,
r = 32 for CTC = 11B,
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
tADC = 1 / fADC
Data Sheet
119
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.2.4
Power Supply Current
Table 41, Table 42, Table 43 and Table 44 provide the characteristics of the power
supply current in the XC886/888.
Table 41
Power Supply Current Parameters (Operating Conditions apply;
DDP = 5V range)
V
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
V
DDP = 5V Range
Active Mode
IDDP
IDDP
IDDP
IDDP
27.2
24.3
21.1
18.2
14.1
11.9
11.7
9.7
32.8
29.8
25.3
21.6
17.0
14.3
15.0
11.9
mA Flash Device3)
mA ROM Device3)
mA Flash Device4)
mA ROM Device4)
mA Flash Device5)
mA ROM Device5)
mA Flash Device6)
mA ROM Device6)
Idle Mode
Active Mode with slow-down
enabled
Idle Mode with slow-down
enabled
1) The typical IDDP values are periodically measured at TA = + 25 °C and VDDP = 5.0 V.
2) The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 5.5 V).
3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by
on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP, no load on ports.
4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz, RESET = VDDP, no load on ports.
5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP, no load on ports.
6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP
,
no load on ports.
Data Sheet
120
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 42
Power Down Current (Operating Conditions apply; VDDP = 5V range)
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
V
DDP = 5V Range
Power-Down Mode
IPDP
1
-
10
30
µA TA = + 25 °C3)4)
µA TA = + 85 °C4)5)
1) The typical IPDP values are measured at VDDP = 5.0 V.
2) The maximum IPDP values are measured at VDDP = 5.5 V.
3) IPDP has a maximum value of 200 µA at TA = + 125 °C.
4) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be
input with either internal pull devices enabled or driven externally to ensure no floating inputs.
5) Not subjected to production test, verified by design/characterization.
Data Sheet
121
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 43
Power Supply Current Parameters (Operating Conditions apply;
V
DDP = 3.3V range)
Parameter
Symbol
Limit Values Unit Test Condition
typ.1)
max.2)
V
DDP = 3.3V Range
Active Mode
IDDP
IDDP
IDDP
IDDP
25.6
23.4
19.9
17.5
13.3
11.5
11.1
9.3
31.0
28.6
24.7
20.7
16.2
13.7
14.4
11.4
mA Flash Device3)
mA ROM Device3)
mA Flash Device4)
mA ROM Device4)
mA Flash Device5)
mA ROM Device5)
mA Flash Device6)
mA ROM Device6)
Idle Mode
Active Mode with slow-down
enabled
Idle Mode with slow-down
enabled
1) The typical IDDP values are periodically measured at TA = + 25 °C and VDDP = 3.3 V.
2) The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 3.6 V).
3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by
on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP, no load on ports.
4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz, RESET = VDDP, no load on ports.
5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP, no load on ports.
6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110B,,
RESET = VDDP, no load on ports.
Data Sheet
122
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 44
Power Down Current (Operating Conditions apply; VDDP = 3.3V
range)
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
V
DDP = 3.3V Range
Power-Down Mode
IPDP
1
-
10
30
µA TA = + 25 °C3)4)
µA TA = + 85 °C4)5)
1) The typical IPDP values are measured at VDDP = 3.3 V.
2) The maximum IPDP values are measured at VDDP = 3.6 V.
3) IPDP has a maximum value of 200 µA at TA = + 125 °C.
4) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be
input with either internal pull devices enabled or driven externally to ensure no floating inputs.
5) Not subjected to production test, verified by design/characterization.
Data Sheet
123
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.3
AC Parameters
The electrical characteristics of the AC Parameters are detailed in this section.
4.3.1
Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 40, Figure 41 and Figure 42.
VDDP
90%
90%
10%
10%
VSS
tF
tR
Figure 40
Rise/Fall Time Parameters
VDDP
VDDE / 2
VDDE / 2
Test Points
VSS
Figure 41
Testing Waveform, Output Delay
VLoad + 0.1 V
VLoad - 0.1 V
VOH - 0.1 V
VOL - 0.1 V
Timing
Reference
Points
Figure 42
Testing Waveform, Output High Impedance
Data Sheet
124
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.3.2
Output Rise/Fall Times
Table 45 provides the characteristics of the output rise/fall times in the XC886/888.
Table 45
Output Rise/Fall Times Parameters (Operating Conditions apply)
Parameter
Symbol
Limit
Unit Test Conditions
Values
min. max.
V
DDP = 5V Range
Rise/fall times
DDP = 3.3V Range
Rise/fall times
tR, tF
tR, tF
–
10
ns
ns
20 pF.1)2)3)
20 pF.1)2)4)
V
–
10
1) Rise/Fall time measurements are taken with 10% - 90% of pad supply.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF.
4) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF.
V
DDP
90%
90%
10%
10%
V
SS
tF
tR
Figure 43
Rise/Fall Times Parameters
Data Sheet
125
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.3.3
Power-on Reset and PLL Timing
Table 49 provides the characteristics of the power-on reset and PLL timing in the
XC886/888.
Table 46
Power-On Reset and PLL Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
1)
Pad operating voltage VPAD
CC 2.3
CC –
–
–
–
500
V
ns
1)
On-Chip Oscillator
start-up time
tOSCST
1)
Flash initialization time tFINIT
CC –
SR –
160 –
500 –
µs
µs
RESET hold time
tRST
VDDP rise time
(10% – 90%) ≤
500µs1)2)
1)
PLL lock-in in time
tLOCK
CC –
–
–
–
200
0.7
µs
ns
1)3)
PLL accumulated jitter DP
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
2) RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5 V).
3) PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.
Data Sheet
126
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
VDDP
VDDC
VPAD
tOSCST
OSC
PLL
PLL unlock
tLOCK
PLL lock
Flash State
Reset
Initialization
tFINIT
Ready to Read
tRST
RESET
Pads
3)
1)Pad state undefined 2)ENPS control 3)As Programmed
2)
1)
III) until Flash go IV) CPU reset is released; Boot
to Ready-to-Read ROM software begin execution
I)until EVR is stable II)until PLL is locked
Figure 44
Power-on Reset Timing
Data Sheet
127
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.3.4
On-Chip Oscillator Characteristics
Table 47 provides the characteristics of the on-chip oscillator in the XC886/888.
Table 47
On-chip Oscillator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Nominal frequency
fNOM CC 9.36 9.6 9.84 MHz under nominal
conditions1)
Long term frequency ∆fLT CC -5.0 –
5.0
0
%
%
%
with respect to fNOM, over
lifetime and temperature
(-10°C to 125°C), for one
given device after
deviation
trimming
-6.0 –
with respect to fNOM, over
lifetime and temperature
(-40°C to
-10°C), for one given
device after trimming
within one LIN message
(<10 ms .... 100 ms)
Short term frequency ∆fST CC -1.0 –
1.0
deviation
1) Nominal condition: VDDC = 2.5 V, TA = + 25°C.
Data Sheet
128
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.3.5
External Clock Drive XTAL1
Table 48 shows the parameters that define the external clock supply for XC886/888.
These timing parameters are based on the direct XTAL1 drive of clock input signals.
They are not applicable if an external crystal or ceramic resonator is considered.
Table 48
External Clock Drive Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min.
Max.
250
-
-
20
20
1)2)
Oscillator period
High time
tosc
t1
SR 83.3
SR 25
SR 25
SR -
ns
ns
ns
ns
2)3)
2)3)
Low time
t2
2)3)
Rise time
t3
2)3)
Fall time
t4
SR -
ns
1) The clock input signals with 45-55% duty cycle are used.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3) The clock input signal must reach the defined levels VILX and VIHX
.
t1
t3
t4
VIHX
VILX
0.5 VDDC
t2
tOSC
External Clock Drive XTAL1
Figure 45
Data Sheet
129
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.3.6
JTAG Timing
Table 49 provides the characteristics of the JTAG timing in the XC886/888.
Table 49
TCK Clock Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min max
Unit Test Conditions
1)
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
tTCK SR
50
20
20
-
-
−
ns
ns
ns
ns
1)
t1
t2
t3
t4
SR
SR
SR
SR
1)
-
4
4
1)
1)
-
ns
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
0.9 V DDP
0.5 V DDP
0.1 V DDP
TCK
t1
t2
t4
t3
tTCK
Figure 46
TCK Clock Timing
Table 50
Parameter
JTAG Timing (Operating Conditions apply; CL = 50 pF)
Symbol Limits Unit Test
Conditions
min max
1)
1)
1)
1)
TMS setup to TCK
t1
t2
t1
t2
t3
SR
SR
SR
SR
CC
8
-
-
-
-
ns
ns
ns
ns
TMS hold to TCK
24
11
24
TDI setup to TCK
TDI hold to TCK
TDO valid output from TCK
-
-
21
28
ns
ns
5V Device1)
3.3V Device1)
Data Sheet
130
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
Table 50
JTAG Timing (Operating Conditions apply; CL = 50 pF) (cont’d)
Parameter
Symbol
Limits
min max
Unit Test
Conditions
TDO high impedance to valid
output from TCK
t4
t5
CC
CC
-
-
-
-
27
36
22
28
ns
ns
ns
ns
5V Device1)
3.3V Device1)
5V Device1)
3.3V Device1)
TDO valid output to high
impedance from TCK
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
TCK
t2
t1
TMS
TDI
t2
t1
t4
t3
t5
TDO
Figure 47
JTAG Timing
Data Sheet
131
V1.2, 2009-07
XC886/888CLM
Electrical Parameters
4.3.7
SSC Master Mode Timing
Table 51 provides the characteristics of the SSC timing in the XC886/888.
Table 51
Parameter
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
Symbol Limit Values Unit Test
Conditions
min.
max.
1)2)
SCLK clock period
MTSR delay from SCLK t1
t0
CC
2*TSSC
0
–
8
ns
ns
2)
CC
SR
SR
2)
2)
MRST setup to SCLK
MRST hold from SCLK
t2
t3
24
0
–
–
ns
ns
1) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3ns. TCPU is the CPU clock period.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
MRST1)
valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 52
SSC Master Mode Timing
Data Sheet
132
V1.2, 2009-07
XC886/888CLM
Package and Quality Declaration
5
Package and Quality Declaration
Chapter 5 provides the information of the XC886/888 package and reliability section.
5.1
Package Parameters
Table 1 provides the thermal characteristics of the package used in XC886 and XC888.
Table 1
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Max.
Unit
Notes
Min.
PG-TQFP-48 (XC886)
1)2)
Thermalresistancejunction RTJC CC -
13
K/W
K/W
case
1)2)
Thermalresistancejunction RTJL CC -
32.5
-
lead
PG-TQFP-64 (XC888)
1)2)
1)2)
Thermalresistancejunction RTJC CC -
12.6
33.4
K/W
K/W
case
Thermalresistancejunction RTJL CC -
lead
1) The thermal resistances between the case and the ambient (RTCA) , the lead and the ambient (RTLA) are to be
combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead
(RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient
(RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA
)
depend on the external system (PCB, case) characteristics, and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ=TA+RTJA × PD, where the RTJA is
the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA
can be obtained from the upper four partial thermal resistances, by
a) simply adding only the two thermal resistances (junction lead and lead ambient), or
b) by taking all four resistances into account, depending on the precision needed.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Data Sheet
133
V1.2, 2009-07
XC886/888CLM
Package and Quality Declaration
5.2
Package Outline
Figure 48 shows the package outlines of the XC886.
H
±0.15
0.5
0.6
C
5.5
0.08
2)
±0.05
0.22
M
0.08 A-B D C 48x
9
71)
0.2 A-B D 48x
0.2 A-B D H 4x
D
A
B
48
Index Marking
1
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
GPP09237
Figure 48
PG-TQFP-48 Package Outline
Data Sheet
134
V1.2, 2009-07
XC886/888CLM
Package and Quality Declaration
Figure 49 shows the package outlines of the XC888.
Figure 49
PG-TQFP-64 Package Outline
Data Sheet
135
V1.2, 2009-07
XC886/888CLM
Package and Quality Declaration
5.3
Quality Declaration
Table 2 shows the characteristics of the quality parameters in the XC886/888.
Table 2
Parameter
Quality Parameters
Symbol Limit Values
Unit Notes
Min.
Max.
ESD susceptibility
according to Human Body
Model (HBM)
ESD susceptibility
according to Charged
Device Model (CDM) pins
VHBM
-
2000
V
V
Conforming to
EIA/JESD22-
A114-B1)
VCDM
-
500
Conforming to
JESD22-C101-C1)
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Data Sheet
136
V1.2, 2009-07
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
©2020 ICPDF网 联系我们和版权申明