SAL-TC389QP-160F300S AD [INFINEON]
SAL-TC389QP-160F300S AD belongs to the AURIX™ TC38xQP family . AURIX™ second generation ( TC3xx ) comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive and industrial trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontroller. In terms of performance, T38x offers 4 cores running at 300 MHz and up to 1.5 MBytes embedded RAM, and consuming below 2 W. Its mirrored embedded flash banks offers A/B swap capabilities.;
| 型号： | SAL-TC389QP-160F300S AD |
| 厂家： | 
Infineon |
| 描述： | SAL-TC389QP-160F300S AD belongs to the AURIX™ TC38xQP family . AURIX™ second generation ( TC3xx ) comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive and industrial trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontroller. In terms of performance, T38x offers 4 cores running at 300 MHz and up to 1.5 MBytes embedded RAM, and consuming below 2 W. Its mirrored embedded flash banks offers A/B swap capabilities. |
| 文件： | 总416页 (文件大小：16446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Bit
Microcontroller
TC38x
32-Bit Single-Chip Microcontroller
AD/AE-Step
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.2, 2021-03
Microcontroller
OPEN MARKET VERSION
Edition 2021-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2021 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
OPEN MARKET VERSION
TC38x AD/AE-Step
Revision History
Page or Item
Subjects (major changes since previous revision)
Version 0.4 is the first version of this document
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
V 0.4, 2017-02
V 0.6, 2017-06
V 0.7, 2018-05
V 0.71, 2018-07
V 1.0, 2018-09
V 1.1, 2019-09
V 1.2, 2021-03
Data Sheet
3
V 1.2 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
4
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TC38x AD/AE-Step
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BGA516 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BGA292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Sequence of Pads in Pad Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
2.1
2.2
2.3
2.4
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
High performance LVDS Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Calculating the 1.25 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Power Supply Infrastructure and Supply Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Supply Ramp-up and Ramp-down Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Single Supply mode (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Single Supply mode (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
External Supply mode (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
External Supply mode (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
PMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
System Phase Locked Loop (SYS_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Peripheral Phase Locked Loop (PER_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 368
ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
ETH RGMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
FSP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
3.8
3.9
3.10
3.11
3.12
3.12.1
3.13
3.13.1
3.13.1.1
3.13.1.2
3.13.1.3
3.13.1.4
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.24.1
3.24.2
3.24.3
3.24.4
3.24.5
3.25
3.26
3.27
3.28
3.29
3.30
Data Sheet
5
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TC38x AD/AE-Step
3.31
3.31.1
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
4
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Changes from Version 0.4 to Version 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Changes from Version 0.6 to Version 0.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Changes from Version 0.7 to Version 0.71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Changes from Version 0.71 to Version 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Changes from Version 1.0 to Version 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Changes from Version 1.1 to Version 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
4.1
4.2
4.3
4.4
4.5
4.6
Data Sheet
6
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TC38x AD/AE-Step
Summary of Features
1
Summary of Features
The TC38x product family has the following features:
•
•
High Performance Microcontroller with four CPU cores
Four 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features:
–
–
–
–
–
–
–
–
–
–
–
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Multiply-accumulate unit able to sustain 2 MAC operations per cycle
Fully pipelined Floating point unit (FPU)
up to 300 MHz operation at full temperature range
up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR)
up to 64 Kbyte Instruction Scratch-Pad RAM (PSPR)
up to 64 Kbyte Data RAM (DLMU)
32 Kbyte Instruction Cache (ICACHE)
16 Kbyte Data Cache (DCACHE)
•
•
Lockstepped shadow cores for two TC1.6.2P
Multiple on-chip memories
–
–
–
–
–
All embedded NVM and SRAM are ECC protected
up to 10 Mbyte Program Flash Memory (PFLASH)
up to 512 Kbyte Data Flash Memory (DFLASH 0) usable for EEPROM emulation
128 Kbyte Memory (LMU)
BootROM (BROM)
•
•
•
128-Channel DMA Controller with safe data transfer
Sophisticated interrupt system (ECC protected)
High performance on-chip bus structure
–
–
–
64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
SRI to SPB bus bridges (SFI Bridge)
•
•
•
•
•
Optional Hardware Security Module (HSM) on some variants
Safety Management Unit (SMU) handling safety monitor alarms
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
Hardware I/O Monitor (IOM) for checking of digital I/O
Versatile On-chip Peripheral Units
–
24 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
–
–
–
–
–
–
5 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
1 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
3 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
3 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering
25 Single Edge Nibble Transmission (SENT) channels for connection to sensors
2 FlexRayTM module with 2 channels (E-Ray) supporting V2.1
Data Sheet
7
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TC38x AD/AE-Step
Summary of Features
–
One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management
–
–
–
–
–
–
One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
One General Purpose 12 Timer Unit (GPT120)
4 channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
1 Peripheral Sensor Interface with Serial PHY (PSI5-S)
2 Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
1 IEEE802.3 Ethernet MAC with RGMII, RMII and MII interfaces (ETH)
•
•
Versatile Successive Approximation ADC (VADC)
–
–
Cluster of 16 independent ADC kernels
Input voltage range from 0 V to 5.5V (ADC supply)
Delta-Sigma ADC (DSADC)
10 channels
–
•
•
•
•
•
•
•
•
Digital programmable I/O ports
On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
Power Management System and on-chip regulators
Clock Generation Unit with System PLL and Peripheral PLL
Embedded Voltage Regulator
Qualified for automotive application according to AEC-Q100 (only applicable after delivery release of the
corresponding sales codes)
•
ISO 26262 Safety Element out of Context for safety requirements up to ASIL D (only applicable for sales codes
listed within a released Safety Package Release Note from IFX)
Data Sheet
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TC38x AD/AE-Step
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply voltage
The package and the type of delivery.
Table 1-1 Platform Feature Overview
Feature
TC38x
CPUs
Type
TC1.6.2
Cores / Checker Cores
4 / 2
Max. Freq.
300 MHz
Cache per CPU
SRAM per CPU
Program
32 KB
Data
16 KB
PSPR
64 KB
DSPR
240 KB for CPU0,1 / 96 KB else
DLMU
64 KB
SRAM global
LMU
128 KB
DAM
64 KB
Extension Memory
TCM
- MB
- MB
XCM
- KB
XTM
Program Flash
Size
10 MB
Banks
3 x 3 MB, 1 x 1 MB
Data Flash
DMA
Size (single-ended)
Channels
512 KB (DF0) + 128 KB (DF1)
128
1
CONVCTRL
EVADC
Modules
Primary Groups/Channels
Secondary Groups/Channels
Fast Compare Channels
Channels
8 / 64
4 / 64
4
EDSADC
10
Data Sheet
9
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TC38x AD/AE-Step
Summary of Features
Table 1-1 Platform Feature Overview (cont’d)
Feature
TC38x
GTM
Clusters
9 (5 @ 200MHz, 4 @ 100MHz)
TIM (8 ch)
TOM (16 ch)
ATOM (8 ch)
MCS (8 ch)
CMU / ICM
PSM
7
5
9
7
1 / 1
2
TBU channels1)
4 (TBU0-3)
SPE
4
CMP / MON
BRC / DPLL
CDTM modules
DTM modules
GPT12
1 / 1
1 / 1
6
20 (8 on TOM, 12 on ATOM)
Timer
1
CCU6
1
STM
Modules
4
FlexRay
Modules
2
Channels
2
CAN
Modules
3
Nodes
3 x 4
1
of which support TT-CAN
Modules
QSPI
5
HSCI Channels
Modules
-
ASCLIN
24
2
I2C
Interfaces
Channels
SENT
25
4
PSI5
Modules
PSI5-S
Modules
1
HSSL
Channels
1
MSC
Channels
3
SDMMC
eMMC/SD Interface
Modules
0
Ethernet (10/100Mbit/1Gbit)
1
FCE
Modules
SMU
1
Safety Support
yes
IOM
yes
SPU
Modules
Modules
Modules
-
-
-
RIF
HSPDM
Data Sheet
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TC38x AD/AE-Step
Summary of Features
Table 1-1 Platform Feature Overview (cont’d)
Feature
TC38x
1
Security
Debug
HSM+
OCDS
yes
no
MCDS
miniMCDS
miniMCDS TRAM
AGBT
yes
8 KB
No
Low Power Features
Standby RAM
SCR
2
yes
FBGA-516 / LFBGA-292
5 V CMOS / 3.3 V CMOS / LVDS
−40 … +150°C
Packages
I/O
Type
Type
Tambient
Range
1) TBU3 has special purpose as angle clock.
Data Sheet
11
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions
2
Pin Definition and Functions
The following figures are showing the Logic Symbols for the package variants:
•
•
BGA516 (Figure 2-1)
BGA292 (Figure 2-2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
B
NC1
VEXT
NC
NC
P10.15 P10.13 P10.11
NC
NC
NC
P13.15 P13.13 P13.11
P13.14 P13.12 P13.10
P13.9
P13.7
P13.5
NC
P14.15 P14.13 P14.11
NC
P15.15 P15.13 P15.11
P15.14 P15.12 P15.10
NC
NC
NC
NC
VDDP3
VSS
A
B
NC
NC
NC
NC
VSS
NC
NC
NC
VEXT
NC
P10.14
NC
P10.10
P10.9
NC
NC
NC
P13.6
P13.4
NC
P14.14 P14.12
NC
NC
NC
NC
NC
VDDP3
VSS
NC
VSS
NC
C
C
D
NC
NC
D
E
NC
NC
E
F
P02.13 P02.12
P02.15 P02.14
NC1
VEXT
VSS
P10.7
VEXT
P10.6
P10.8
P10.2
P10.5
P10.3
P10.4
P10.0
P10.1
P11.11
P11.12
P11.9
P11.2
P11.3
P13.3
P13.2
P13.1
P13.0
P14.8
P14.6
P14.5
P14.3
P14.1
P14.4
P15.6
P14.0
P15.4
P15.3
P15.1
VDDP3
VSS
VSS
P15.0
P20.14
NC
NC
F
G
P02.0
P02.2
P02.4
P02.6
P02.8
P00.0
P00.2
P00.4
P00.7
P11.10
VDDP3
NC
NC
G
H
NC
NC
NC
P02.1
P02.3
P02.5
P02.7
P00.1
P00.3
P00.5
P00.9
P15.2
VSS
VEXT
VSS
VEXT
H
J
P01.0
P01.2
P01.9
VSS
VFLEX P11.15
P11.14
P11.8
P11.5
P11.7
P11.6
P11.1
P11.4
P11.0
P14.10
P12.1
P14.9
P12.0
P14.7
P14.2
P15.8
P15.5
P15.7
VDD
VDD
VSS
VSS
P20.9
P20.6
PORST
P20.12 P20.13
P20.10 P20.11
J
K
P01.1
P01.8
P02.9
VSS
P11.13
P24.14 P24.15
P24.12 P24.13
P24.10 P24.11
K
L
P02.11 P02.10
ESR0
ESR1
P20.7
P20.1
P20.2
P21.3
P21.2
TRST
XTAL2
VDD
P20.8
P20.3
P20.0
P21.5
P21.4
VSS
L
M
P01.11 P01.10
P01.13 P01.12
P01.15 P01.14
P01.4
P01.6
P00.6
P00.8
AN43
AN41
P01.3
P01.5
P01.7
P00.10
AN42
AN40
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
M
P21.7 / P21.6 /
TDO
N
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VSS
NC
P24.8
P24.6
P24.4
P24.2
P24.0
NC1
P24.9
P24.7
P24.5
P24.3
P24.1
NC1
N
TDI
P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TCK
P21.1
P
R
NC
NC
NC
VSS
VSS
VSS
VSS
TMS
P21.0
R
T
P00.13
P00.11 P00.12
VSS
VSS
VDD
P22.10 P22.11
T
U
P00.15 P00.14
AN46
AN44
AN47
AN45
P22.8
P22.6
P22.4
P23.7
VSS
P22.9
P22.7
P22.5
P23.6
P23.5
VSS
XTAL1
VEXT
P22.0
P22.2
P23.4
P23.2
P23.0
VEXT
VSS
U
AN36 /
P40.6
AN38 /
P40.8
V
NC
NC
VSS
VSS
VSS
VSS
V
AN70 /
P41.2
AN71 /
P41.3
AN39 /
P40.9
AN37 /
P40.7
AN32 /
P40.4
W
Y
AN34
AN23
AN22
VDD
VDD
P22.1
P22.3
P23.3
P23.1
VEXT
VSS
P25.6
NC
W
Y
AN68 /
P41.0
AN69 /
P41.1
AN33 /
P40.5
AN35
AN31
AN30
NC1
P25.14 P25.15
P25.12 P25.13
P25.10 P25.11
AN67 /
P40.15
VAREF VAGND
2
VEVRS
B
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AN66
AN15
AN14
AN12
AN9
AN6
AN7
AN4
AN3
AN0
AN1
P34.2
P34.3
P34.4
P34.5
P33.14
P33.15
P32.5
P32.6
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
2
AN64 /
P41.8
AN29 /
P40.14 P40.13
AN28 /
AN17 /
P40.10
AN65
P34.1
P32.7
AN63 /
P41.7
AN62 /
P41.6
AN27 /
P40.3
AN26 /
P40.2
P25.8
P25.7
P25.4
P25.2
P26.0
VEXT
VSS
P25.9
P25.5
P25.3
P25.1
P25.0
VEXT
VEXT
P32.1 /
AN25 /
P40.1
AN24 /
P40.0
AN19 /
P40.12 P40.11
AN18 /
AN60
AN59
AN56
AN61
AN58
AN57
AN16
AN13
AN11
AN8
AN2
AN5
P33.0
P33.1
P33.2
P33.3
P33.4
P33.5
P33.6
P33.7
P33.8
P33.9
P33.10 P33.12 VGATE
1P
P32.4
P32.2
P32.0 /
P33.11 P33.13 VGATE
1N
VAREF VAGND
1
NC1
AN21
AN20
VSSM
VDDM
AN10
P32.3
1
VAREF VAGND
3
3
NC
NC
AN54 /
P41.4
NC
NC
NC
AN52
AN50
AN49
VSSM
VDDM
VSS
VEXT
P31.0
P31.2
P31.4
P31.6
P31.8
P31.10 P31.12 P31.14
P31.11 P31.13 P31.15
NC
P30.0
P30.2
P30.4
P30.6
P30.8
P30.10 P30.12 P30.14
P30.11 P30.13 P30.15
AN55 /
P41.5
NC1
NC
NC
AN53
AN51
AN48
VSSM
VDDM
VSS
VEXT
P31.1
P31.3
P31.5
P31.7
P31.9
VEXT
P30.1
P30.3
P30.5
P30.7
P30.9
VEXT
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TC38xpd - (top view)
Figure 2-1 Logic Symbol for the package variant BGA516
Data Sheet
12
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
NC1
VEXT
P10.7
P10.6
P10.2
P10.3
P10.0
P11.11
P11.9
P11.2
P13.3
P13.1
P14.8
P14.5
P14.1
P15.6
P15.4
P15.1
VDDP3
VSS
A
B
C
D
E
F
P02.0
P02.2
P02.4
P02.6
P02.8
P00.0
P00.2
P00.4
P00.7
VSS
VEXT
P10.8
P10.5
P10.4
P10.1
P11.12
P11.10
P11.3
P13.2
P13.0
P14.6
P14.3
P14.4
P14.0
P15.3
VDDP3
VSS
P15.0
P02.1
P02.3
P02.5
P02.7
P00.1
P00.3
P00.5
P00.9
P15.2
P20.14
VSS
VFLEX P11.15
P11.14
P11.8
P11.5
P11.7
P11.6
P11.1
P11.4
P11.0
P14.10
P12.1
P14.9
P12.0
P14.7
P14.2
P15.8
P15.5
P15.7
VDD
VDD
VSS
VSS
P20.9
P20.6
PORST
P20.12 P20.13
P20.10 P20.11
P02.9
VSS
P11.13
P02.11 P02.10
ESR0
ESR1
P20.7
P20.1
P20.2
P21.3
P21.2
TRST
XTAL2
VDD
P20.8
P20.3
P20.0
P21.5
P21.4
VSS
G
H
J
P01.4
P01.6
P00.6
P00.8
AN43
AN41
P01.3
P01.5
P01.7
P00.10
AN42
AN40
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
G
H
J
P21.7 / P21.6 /
TDO
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VSS
NC
TDI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TCK
P21.1
K
L
VSS
VSS
VSS
VSS
TMS
P21.0
K
L
P00.11 P00.12
VSS
VSS
VDD
P22.10 P22.11
M
N
P
R
T
AN46
AN44
AN47
AN45
P22.8
P22.6
P22.4
P23.7
VSS
P22.9
P22.7
P22.5
P23.6
P23.5
VSS
XTAL1
VEXT
P22.0
P22.2
P23.4
P23.2
P23.0
VEXT
M
N
P
R
T
AN36 /
P40.6
AN38 /
P40.8
VSS
VSS
VSS
VSS
AN39 /
P40.9
AN37 /
P40.7
AN32 /
P40.4
AN34
AN23
AN22
VDD
VDD
P22.1
P22.3
P23.3
P23.1
VEXT
VSS
AN33 /
P40.5
AN35
AN31
AN30
NC1
VAREF VAGND
2
VEVRS
B
AN15
AN14
AN12
AN9
AN6
AN7
AN4
AN3
AN0
AN1
P34.2
P34.3
P34.4
P34.5
P33.14
P33.15
P32.5
P32.6
2
AN29 /
P40.14 P40.13
AN28 /
AN17 /
P40.10
U
V
W
Y
P34.1
P32.7
U
V
W
Y
AN27 /
P40.3
AN26 /
P40.2
P32.1 /
AN25 /
P40.1
AN24 /
P40.0
AN19 /
P40.12 P40.11
AN18 /
AN16
AN13
AN11
AN8
AN2
P33.0
P33.2
P33.4
P33.6
P33.8
P33.10 P33.12 VGATE
1P
P32.4
P32.0 /
P33.11 P33.13 VGATE
1N
VAREF VAGND
1
NC1
AN21
AN20
VSSM
VDDM
AN10
AN5
P33.1
P33.3
P33.5
P33.7
P33.9
P32.2
P32.3
VSS
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TC38xpd - (top view)
Figure 2-2 Logic Symbol for the package variant BGA292
Data Sheet
13
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
2.1
BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
M6
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Trap input capture
GTM_TIM5_IN4_10
GTM_TIM3_IN0_1
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
External timer start 12
Injection signal from port
MDIO Input
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Shift clock output
Transmit output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
O
MDIO Output
Data Sheet
14
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
M7
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
T12 capture input 60
GTM_TIM5_IN5_11
GTM_TIM3_IN1_1
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
EDSADC_DSCIN5A
CAN10_RXDA
PSI5_RX0A
Receive input
Modulator clock input, channel 5
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
CCU61_CC60INA
SENT_SENT0B
EDSADC_DSCIN7B
EVADC_G9CH11
EDSADC_EDS5NA
P00.1
Receive input channel 0
Modulator clock input, channel 7
Analog input channel 11, group 9
Negative analog input channel 5, pin A
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT5
EDSADC_DSCOUT7
SENT_SPC0
Modulator clock output
Modulator clock output
Transmit output
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
15
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N6
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM5_IN6_11
GTM_TIM3_IN1_2
GTM_TIM2_IN1_2
EDSADC_DSDIN7B
EDSADC_DSDIN5A
SENT_SENT1B
EVADC_G9CH10
EDSADC_EDS5PA
P00.2
Mux input channel 6 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Digital datastream input, channel 7
Digital datastream input, channel 5
Receive input channel 1
Analog input channel 10, group 9
Positive analog input channel 5, pin A
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
CAN21_TXD
Reference input 0
O2
O3
O4
Shift clock output
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
PSI5_TX0
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
IOM_MON2_8
IOM_REF2_8
Reference input 2
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
16
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N7
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
T12 capture input 61
GTM_TIM5_IN7_10
GTM_TIM3_IN2_1
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
EDSADC_ITR5F
PSI5_RX1A
Modulator clock input, channel 3
Trigger/Gate input, channel 5
RXD inputs (receive data) channel 1
CAN receive input node 3
CAN receive input node 1
RX data input
CAN03_RXDA
CAN21_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
ASCLIN12_ARXA
EVADC_G9CH9
EDSADC_EDS5NB
P00.3
Receive input channel 2
T12 capture input 61
Receive input
AI
Analog input channel 9, group 9
Negative analog input channel 5, pin B
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
ASCLIN12_ATX
EDSADC_DSCOUT3
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Transmit output
Modulator clock output
Reserved
SENT_SPC2
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
17
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P6
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM6_IN4_1
GTM_TIM3_IN3_1
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 4 of TIM module 6
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
GTM_DTMA5_0
GTM_DTMT3_0
EVADC_G9CH8
EDSADC_EDS5PB
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
CDTM5_DTM4
CDTM3_DTM0
AI
Analog input channel 8, group 9
Positive analog input channel 5, pin B
General-purpose output
GTM muxed output
Reference input 0
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
O2
O3
O4
TX data output
CAN11_TXD
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
PSI5_TX1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
18
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P7
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN4_1
GTM_TIM3_IN0_11
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
PSI5_RX2A
Mux input channel 4 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 2
T12 capture input 62
Modulator clock input, channel 2
RXD inputs (receive data) channel 2
T12 capture input 62
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
ASCLIN12_ARXB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Receive input channel 4
CAN receive input node 1
Receive input
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
19
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P9
P00.6
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 5 of TIM module 3
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 2
Trigger/Gate input, channel 4
Digital datastream input, channel 2
Receive input channel 5
Receive input
GTM_TIM3_IN5_1
GTM_TIM3_IN1_14
GTM_TIM2_IN5_1
EDSADC_ITR4F
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
GTM_DTMT3_1
EVADC_G9CH6
P00.6
CDTM3_DTM0
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
Positive carrier generator output
Reserved
PSI5_TX2
TXD outputs (send data)
Reference input 1
IOM_REF1_15
EVADC_EMUX10
SENT_SPC5
O5
O6
O7
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
20
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R6
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN6_1
GTM_TIM3_IN2_11
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
EDSADC_DSCIN4A
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
EDSADC_EDS4NA
P00.7
Mux input channel 6 of TIM module 3
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 2
T12 capture input 60
Receive input channel 6
Modulator clock input, channel 4
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
Negative analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
EVADC_FC2BFLOUT
EDSADC_DSCOUT4
EVADC_EMUX11
SENT_SPC6
Transmit output
Boundary flag output, FC channel 2
Modulator clock output
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC60
T12 PWM channel 60
IOM_MON1_8
Monitor input 1
IOM_REF1_13
Reference input 1
Data Sheet
21
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R9
P00.8
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN7_1
GTM_TIM3_IN3_11
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
EDSADC_DSDIN4A
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
EDSADC_EDS4PA
P00.8
Mux input channel 7 of TIM module 3
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 2
T12 capture input 61
Receive input channel 7
Digital datastream input, channel 4
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
Positive analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
22
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R7
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM4_IN0_7
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
ASCLIN13_ARXA
EVADC_G9CH3
EDSADC_EDS4NB
P00.9
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
Receive input
AI
Analog input channel 3, group 9
Negative analog input channel 4, pin B
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
23
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R10
P00.10
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input channel 9
Digital datastream input, channel 1
Analog input channel 2, group 9
Positive analog input channel 4, pin B
General-purpose output
GTM muxed output
GTM_TIM4_IN1_11
GTM_TIM1_IN1_1
GTM_TIM0_IN1_1
SENT_SENT9B
EDSADC_DSDIN1A
EVADC_G9CH2
EDSADC_EDS4PB
P00.10
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT19
ASCLIN4_ASCLK
ASCLIN13_ATX
—
Shift clock output
Transmit output
Reserved
—
Reserved
SENT_SPC9
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P00.11
Transmit output
T13 PWM channel 63
Monitor input 1
Reference input 1
T6
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trap input capture
GTM_TIM4_IN2_11
GTM_TIM1_IN2_1
GTM_TIM0_IN2_1
CCU60_CTRAPA
EDSADC_DSCIN0A
CCU61_T12HRE
SENT_SENT10B
ASCLIN13_ARXB
EVADC_G9CH1
EVADC_FC3CH0
P00.11
Modulator clock input, channel 0
External timer start 12
Receive input channel 10
Receive input
AI
Analog input channel 1, group 9
Analog input FC channel 3
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT20
ASCLIN4_ASLSO
ASCLIN13_ATX
EDSADC_DSCOUT0
—
Slave select signal output
Transmit output
Modulator clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
24
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T7
P00.12
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
GTM_TIM4_IN3_11
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
SENT_SENT11B
EVADC_G9CH0
EVADC_FC2CH0
P00.12
Digital datastream input, channel 0
Receive input
Receive input channel 11
Analog input channel 0, group 9
Analog input FC channel 2
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P00.13
T13 PWM channel 63
Monitor input 1
Reference input 1
T2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 0 of TIM module 5
Mux input channel 0 of TIM module 4
Digital datastream input, channel 6
General-purpose output
GTM muxed output
GTM_TIM6_IN5_2
GTM_TIM5_IN0_1
GTM_TIM4_IN0_1
EDSADC_DSDIN6A
P00.13
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT167
—
Reserved
—
Reserved
CCU_EXTCLK1
—
External Clock 1
Reserved
—
Reserved
—
Reserved
Data Sheet
25
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U2
P00.14
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 4
Modulator clock input, channel 6
General-purpose output
GTM muxed output
GTM_TIM6_IN6_2
GTM_TIM5_IN7_1
GTM_TIM4_IN7_1
EDSADC_DSCIN6A
P00.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT166
—
Reserved
—
Reserved
EDSADC_DSCOUT6
Modulator clock output
Reserved
—
—
Reserved
—
Reserved
U1
P00.15
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 1 of TIM module 5
Mux input channel 1 of TIM module 4
Trigger/Gate input, channel 6
General-purpose output
GTM muxed output
GTM_TIM6_IN7_2
GTM_TIM5_IN1_1
GTM_TIM4_IN1_1
EDSADC_ITR6F
P00.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT168
—
Reserved
—
Reserved
CCU_EXTCLK0
External Clock 0
—
—
—
Reserved
Reserved
Reserved
Data Sheet
26
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
J2
P01.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 4 of TIM module 4
Mux input channel 6 of TIM module 2
CAN receive input node 1
Trigger/Gate input, channel 6
CAN receive input node 3
Receive input
GTM_TIM5_IN4_1
GTM_TIM4_IN4_1
GTM_TIM2_IN6_13
CAN21_RXDE
EDSADC_ITR6E
CAN03_RXDF
ASCLIN6_ARXB
P01.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT155
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
K1
P01.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 1 of TIM module 4
Trigger/Gate input, channel 8
Receive Channel A1
Receive input channel 15
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN1_2
GTM_TIM4_IN1_2
EDSADC_ITR8E
ERAY1_RXDA1
SENT_SENT15B
P01.1
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT159
—
—
Reserved
ASCLIN6_ATX
Transmit output
—
—
—
Reserved
Reserved
Reserved
Data Sheet
27
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K2
P01.2
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 5 of TIM module 4
Modulator clock input, channel 7
General-purpose output
GTM muxed output
GTM_TIM5_IN5_1
GTM_TIM4_IN5_1
EDSADC_DSCIN7A
P01.2
O0
O1
O2
O3
GTM_TOUT156
—
Reserved
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
CAN transmit output node 3
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Reserved
CAN21_TXD
EDSADC_DSCOUT7
—
CAN transmit output node 1
Modulator clock output
Reserved
M10
P01.3
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 0 of TIM module 2
Mux input channel 5 of TIM module 0
Slave select input
GTM_TIM4_IN5_2
GTM_TIM2_IN0_14
GTM_TIM0_IN5_8
QSPI3_SLSIB
EDSADC_ITR7F
EVADC_G9CH14
P01.3
Trigger/Gate input, channel 7
Analog input channel 14, group 9
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
GTM_TOUT111
—
Reserved
—
Reserved
QSPI3_SLSO9
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
—
Master slave select output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
Reserved
—
Reserved
Data Sheet
28
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
M9
P01.4
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 1 of TIM module 2
Mux input channel 6 of TIM module 0
CAN receive input node 1
Trigger/Gate input, channel 7
Analog input channel 13, group 9
General-purpose output
GTM muxed output
GTM_TIM4_IN6_2
GTM_TIM2_IN1_14
GTM_TIM0_IN6_8
CAN01_RXDC
EDSADC_ITR7E
EVADC_G9CH13
P01.4
AI
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT112
—
Reserved
ASCLIN9_ASLSO
QSPI3_SLSO10
—
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
N10
P01.5
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 2
Mux input channel 2 of TIM module 2
Master SPI data input
Modulator clock input, channel 8
Receive input
GTM_TIM5_IN3_2
GTM_TIM2_IN3_7
GTM_TIM2_IN2_7
QSPI3_MRSTC
EDSADC_DSCIN8A
ASCLIN9_ARXA
EVADC_G9CH12
P01.5
AI
Analog input channel 12, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
GTM_TOUT113
—
Reserved
—
Reserved
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
Reserved
EDSADC_DSCOUT8
—
Modulator clock output
Reserved
Data Sheet
29
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N9
P01.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 5 of TIM module 5
Mux input channel 5 of TIM module 2
Slave SPI data input
Digital datastream input, channel 8
General-purpose output
GTM muxed output
GTM_TIM5_IN6_2
GTM_TIM5_IN5_3
GTM_TIM2_IN5_7
QSPI3_MTSRC
EDSADC_DSDIN8A
P01.6
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT114
ASCLIN12_ATX
ASCLIN9_ASCLK
QSPI3_MTSR
—
Transmit output
Shift clock output
Master SPI data output
Reserved
—
Reserved
—
Reserved
P10
P01.7
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
Trigger/Gate input, channel 8
Receive input
GTM_TIM5_IN7_2
GTM_TIM2_IN7_7
QSPI3_SCLKC
EDSADC_ITR8F
ASCLIN9_ARXB
P01.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT115
—
Reserved
ASCLIN9_ATX
QSPI3_SCLK
—
Transmit output
Master SPI clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
30
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L1
P01.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 0 of TIM module 5
Mux input channel 4 of TIM module 4
CAN receive input node 0
Receive Channel B1
Digital datastream input, channel 9
Receive input channel 17
Receive input
GTM_TIM5_IN4_2
GTM_TIM5_IN0_10
GTM_TIM4_IN4_2
CAN00_RXDF
ERAY1_RXDB1
EDSADC_DSDIN9A
SENT_SENT17B
ASCLIN0_ARXC
CAN20_RXDE
ASCLIN7_ARXB
P01.8
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT162
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
L2
P01.9
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 5
Mux input channel 1 of TIM module 5
Mux input channel 2 of TIM module 4
Modulator clock input, channel 9
Receive input channel 16
General-purpose output
GTM muxed output
GTM_TIM5_IN2_1
GTM_TIM5_IN1_11
GTM_TIM4_IN2_1
EDSADC_DSCIN9A
SENT_SENT16B
P01.9
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT160
ASCLIN7_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
EDSADC_DSCOUT9
—
Modulator clock output
Reserved
Data Sheet
31
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
M2
P01.10
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 2 of TIM module 5
Mux input channel 5 of TIM module 4
Trigger/Gate input, channel 9
Receive input channel 18
CDTM3_DTM0
GTM_TIM5_IN5_2
GTM_TIM5_IN2_9
GTM_TIM4_IN5_3
EDSADC_ITR9F
SENT_SENT18B
GTM_DTMT3_2
P01.10
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Shift clock output
GTM_TOUT163
ASCLIN7_ASCLK
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
M1
P01.11
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 3 of TIM module 5
Mux input channel 7 of TIM module 4
Trigger/Gate input, channel 9
Receive input channel 19
CDTM5_DTM4
GTM_TIM5_IN7_3
GTM_TIM5_IN3_11
GTM_TIM4_IN7_2
EDSADC_ITR9E
SENT_SENT19B
GTM_DTMA5_1
P01.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT165
ASCLIN7_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
32
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N2
P01.12
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 0 of TIM module 5
Mux input channel 0 of TIM module 4
General-purpose output
GTM muxed output
GTM_TIM6_IN0_3
GTM_TIM5_IN0_2
GTM_TIM4_IN0_2
P01.12
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT158
ASCLIN7_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
ERAY1_TXDA
—
Transmit Channel A
Reserved
N1
P01.13
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 4
General-purpose output
GTM muxed output
GTM_TIM6_IN1_3
GTM_TIM5_IN3_1
GTM_TIM4_IN3_1
P01.13
O0
O1
O2
GTM_TOUT161
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
CAN20_TXD
ERAY1_TXDB
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O5
O6
O7
CAN transmit output node 0
Transmit Channel B
Reserved
Data Sheet
33
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P2
P01.14
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 6 of TIM module 5
Mux input channel 6 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN2_3
GTM_TIM5_IN6_3
GTM_TIM4_IN6_3
P01.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT164
—
—
Reserved
—
Reserved
—
Reserved
ERAY1_TXENA
Transmit Enable Channel A
Reserved
—
P1
P01.15
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 6 of TIM module 5
Mux input channel 6 of TIM module 4
Digital datastream input, channel 7
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN3_3
GTM_TIM5_IN6_1
GTM_TIM4_IN6_1
EDSADC_DSDIN7A
P01.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT157
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
34
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G6
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
35
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H7
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT1
IOM_REF0_1
QSPI4_SLSO7
QSPI3_SLSO2
EDSADC_CGPWMP
—
O2
O3
O4
O5
O6
O7
Master slave select output
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
36
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H6
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
Receive input channel 14
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
SENT_SENT14B
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
37
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J7
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Modulator clock input, channel 5
Receive Channel B2
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
EDSADC_DSCIN5B
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
MSC1_SDI1
CAN receive input node 2
Receive input
Upstream assynchronous input signal
RXD inputs (receive data) channel 0
Receive input channel 13
General-purpose output
GTM muxed output
PSI5_RX0B
SENT_SENT13B
P02.3
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
EDSADC_DSCOUT5
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Modulator clock output
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
38
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J6
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
EDSADC_DSDIN5B
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Digital datastream input, channel 5
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
SENT_SENT12B
P02.4
CAN receive input node 1
External CAN time trigger input
Receive input channel 12
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
39
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K7
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Modulator clock input, channel 4
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
EDSADC_DSCIN4B
I2C0_SCLA
PSI5_RX1B
RXD inputs (receive data) channel 1
RX data input
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
EDSADC_DSCOUT4
I2C0_SCL
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Modulator clock output
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
40
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K6
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM3_IN0_10
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
EDSADC_DSDIN4B
EDSADC_ITR5E
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Digital datastream input, channel 4
Trigger/Gate input, channel 5
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
41
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L7
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN1_10
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
EDSADC_ITR4E
GPT120_T3EUDA
PSI5_RX2B
Mux input channel 1 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
Receive input channel 1
Modulator clock input, channel 3
Trigger/Gate input, channel 4
Count direction control input of core timer T3
RXD inputs (receive data) channel 2
Hall capture input 1
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
—
Reference input 0
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
42
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L6
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM3_IN2_10
GTM_TIM3_IN0_2
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
Reference input 0
QSPI3_SLSO5
ASCLIN8_ASCLK
PSI5_TX2
O2
O3
O4
Master slave select output
Shift clock output
TXD outputs (send data)
Reference input 1
IOM_REF1_15
EVADC_EMUX02
GETH_MDC
O5
O6
O7
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
43
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K9
P02.9
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 3 of TIM module 3
Mux input channel 2 of TIM module 0
Receive input channel 20
Receive input
GTM_TIM4_IN2_2
GTM_TIM3_IN3_10
GTM_TIM0_IN2_10
SENT_SENT20B
ASCLIN8_ARXA
P02.9
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT116
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
ASCLIN8_ATX
—
Monitor input 2
Reference input 2
O3
O4
O5
Transmit output
Reserved
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
—
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
L10
P02.10
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM4_IN3_2
GTM_TIM3_IN4_11
GTM_TIM0_IN3_10
ASCLIN2_ARXC
CAN01_RXDE
SENT_SENT21B
ASCLIN8_ARXB
P02.10
CAN receive input node 1
Receive input channel 21
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT117
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
44
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L9
P02.11
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 5 of TIM module 3
Mux input channel 7 of TIM module 0
Receive input channel 22
Analog input channel 15, group 9
General-purpose output
GTM muxed output
GTM_TIM4_IN4_3
GTM_TIM3_IN5_12
GTM_TIM0_IN7_7
SENT_SENT22B
EVADC_G9CH15
P02.11
AI
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT118
—
Reserved
ASCLIN8_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
F2
P02.12
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 5
Mux input channel 0 of TIM module 4
Mux input channel 6 of TIM module 3
Receive input channel 23
General-purpose output
GTM muxed output
GTM_TIM5_IN0_3
GTM_TIM4_IN0_3
GTM_TIM3_IN6_12
SENT_SENT23B
P02.12
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT151
QSPI3_SLSO5
QSPI4_SLSO4
ASCLIN6_ASLSO
—
Master slave select output
Master slave select output
Slave select signal output
Reserved
—
Reserved
—
Reserved
Data Sheet
45
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F1
P02.13
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 5
Mux input channel 2 of TIM module 4
Mux input channel 7 of TIM module 3
Receive input channel 24
General-purpose output
GTM muxed output
GTM_TIM5_IN2_2
GTM_TIM4_IN2_3
GTM_TIM3_IN7_11
SENT_SENT24B
P02.13
O0
O1
O2
O3
O4
GTM_TOUT153
QSPI3_SLSO7
QSPI4_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
CAN20_TXD
—
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O5
O6
O7
I
CAN transmit output node 0
Reserved
—
Reserved
G2
P02.14
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 4
Mux input channel 4 of TIM module 2
CAN receive input node 0
CAN receive input node 0
General-purpose output
GTM muxed output
GTM_TIM5_IN3_3
GTM_TIM4_IN3_3
GTM_TIM2_IN4_14
CAN20_RXDD
CAN00_RXDH
P02.14
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT154
ASCLIN6_ASCLK
—
Shift clock output
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
46
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G1
P02.15
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 1 of TIM module 4
Mux input channel 5 of TIM module 2
General-purpose output
GTM muxed output
GTM_TIM5_IN1_3
GTM_TIM4_IN1_3
GTM_TIM2_IN5_14
P02.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT152
QSPI3_SLSO6
QSPI4_SLSO5
ASCLIN6_ATX
—
Master slave select output
Master slave select output
Transmit output
Reserved
ERAY1_TXENB
—
Transmit Enable Channel B
Reserved
Table 2-4 Port 10 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
F12
P10.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of core timer T6
Receive input
GTM_TIM4_IN0_12
GTM_TIM1_IN4_2
GTM_TIM0_IN4_2
GPT120_T6EUDB
ASCLIN11_ARXA
GETH_RXERC
GTM_DTMA5_2
P10.0
Receive Error MII
CDTM5_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT102
ASCLIN11_ATX
QSPI1_SLSO10
—
Transmit output
Master slave select output
Reserved
—
Reserved
ASCLIN22_ATX
—
Transmit output
Reserved
Data Sheet
47
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G12
P10.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN4_12
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
Mux input channel 4 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Chip Select
EVADC_FC1BFLOUT
—
Boundary flag output, FC channel 1
Reserved
—
Reserved
F10
P10.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN5_12
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 5 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMT2_2
P10.2
CDTM2_DTM0
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI1_SCLK
MSC0_EN0
EVADC_FC3BFLOUT
—
Master SPI clock output
Chip Select
Boundary flag output, FC channel 3
Reserved
—
Reserved
Data Sheet
48
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F11
P10.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN6_10
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
Mux input channel 6 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
G11
P10.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
Trigger/gate input of core timer T3
Receive input
GTM_TIM4_IN7_3
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
ASCLIN22_ARXA
P10.4
Receive input
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT106
IOM_MON2_11
ASCLIN22_ATX
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
—
O2
O3
O4
O5
O6
O7
Transmit output
Master slave select output
Master SPI data output
Chip Select
Reserved
—
Reserved
Data Sheet
49
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G10
P10.5
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM4_IN3_13
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
CAN20_RXDA
MSC0_INJ1
CAN receive input node 0
Injection signal from port
Receive input
ASCLIN22_ARXB
P10.5
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
Reference input 2
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
PSI5_TX3
O6
O7
Slave select signal output
TXD outputs (send data)
Data Sheet
50
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F9
P10.6
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
RXD inputs (receive data) channel 3
Receive input
GTM_TIM4_IN2_13
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
PSI5_RX3C
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
ASCLIN23_ARXA
P10.6
Slave SPI data input
HWCFG5 pin input
Receive input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
CAN20_TXD
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
O5
O6
CAN transmit output node 0
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O7
Data Sheet
51
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F8
P10.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_3
GTM_TIM0_IN0_3
GPT120_T3EUDB
ASCLIN2_ACTSA
QSPI3_MRSTB
SCU_E_REQ0_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Count direction control input of core timer T3
Clear to send input
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS1C
ASCLIN23_ARXB
P10.7
Hall capture input 1
Receive input
O0
O1
General-purpose output
GTM muxed output
Reference input 2
Transmit output
GTM_TOUT109
IOM_REF2_11
ASCLIN23_ATX
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
O2
O3
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN20_TXD
CAN12_TXD
—
CAN transmit output node 0
CAN transmit output node 2
Reserved
Data Sheet
52
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G9
P10.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN0_13
GTM_TIM1_IN5_2
GTM_TIM0_IN5_2
CAN12_RXDB
GPT120_T4INB
QSPI3_SCLKB
SCU_E_REQ1_2
Mux input channel 0 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 2
Trigger/gate input of timer T4
Slave SPI clock inputs
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS2C
Hall capture input 2
CAN receive input node 0
General-purpose output
GTM muxed output
Ready to send output
Master SPI clock output
Transmit output
CAN20_RXDB
P10.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT110
ASCLIN2_ARTS
QSPI3_SCLK
ASCLIN23_ATX
—
Reserved
—
Reserved
—
Reserved
B8
P10.9
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 0
Receive input channel 15
Receive input
GTM_TIM6_IN0_5
GTM_TIM4_IN1_4
GTM_TIM0_IN1_10
SENT_SENT15C
ASCLIN6_ARXD
P10.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT265
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
53
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B7
P10.10
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 0
Receive input channel 16
General-purpose output
GTM muxed output
Transmit output
GTM_TIM6_IN1_5
GTM_TIM4_IN2_4
GTM_TIM0_IN2_11
SENT_SENT16C
P10.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT266
ASCLIN6_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
A7
P10.11
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 5 of TIM module 4
Mux input channel 5 of TIM module 0
Receive input channel 19
General-purpose output
GTM muxed output
Shift clock output
GTM_TIM6_IN2_5
GTM_TIM4_IN5_4
GTM_TIM0_IN5_9
SENT_SENT19C
P10.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT269
ASCLIN6_ASCLK
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
54
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A6
P10.13
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 4 of TIM module 4
Mux input channel 4 of TIM module 0
Receive input channel 18
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TIM6_IN3_5
GTM_TIM4_IN4_4
GTM_TIM0_IN4_9
SENT_SENT18C
P10.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT268
ASCLIN6_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
B5
P10.14
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 0
Receive input channel 17
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN3_4
GTM_TIM0_IN3_11
SENT_SENT17C
P10.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT267
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
A5
P10.15
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 6 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN6_4
GTM_TIM0_IN6_9
P10.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT270
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
55
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
K15
P11.0
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN0_4
GTM_TIM2_IN0_7
ASCLIN3_ARXB
GTM_DTMA2_1
P11.0
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 2
Receive input
CDTM2_DTM4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT119
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 2
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
CAN11_TXD
GETH_TXD3
—
CAN transmit output node 1
Transmit Data
Reserved
K14
P11.1
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN1_5
GTM_TIM2_IN1_6
P11.1
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Shift clock output
Transmit output
O0
O1
O2
O3
GTM_TOUT120
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN12_TXD
GETH_TXD2
—
CAN transmit output node 2
Transmit Data
Reserved
Data Sheet
56
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F15
P11.2
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN1_3
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P11.3
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
G15
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN2_2
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Transmit Channel A
Reserved
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
57
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J15
P11.4
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN2_5
GTM_TIM2_IN2_6
GETH_RXCLKB
P11.4
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 2
Receive Clock MII
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT121
ASCLIN3_ASCLK
—
Shift clock output
Reserved
—
Reserved
CAN13_TXD
GETH_TXER
GETH_TXCLK
P11.5
CAN transmit output node 3
Transmit Error MII
Transmit Clock Output for RGMII
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 2
Transmit Clock Input for MII
J13
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM4_IN3_5
GTM_TIM2_IN3_8
GETH_TXCLKA
GETH_GREFCLK
Gigabit Reference Clock input for RGMII (125 MHz high
precission)
P11.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT122
—
—
Reserved
—
Reserved
CAN20_TXD
CAN transmit output node 0
Reserved
—
—
Reserved
Data Sheet
58
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J14
P11.6
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN3_2
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
P11.7
GTM muxed output
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
I
Monitor input 1
Reference input 1
K13
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM4_IN4_5
GTM_TIM2_IN4_7
GETH_RXD3A
Mux input channel 4 of TIM module 4
Mux input channel 4 of TIM module 2
Receive Data 3 MII and RGMII (RGMII can use RXD3A
only)
CAN11_RXDD
CAN receive input node 1
General-purpose output
GTM muxed output
Reserved
P11.7
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT123
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
59
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K12
P11.8
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM4_IN5_5
GTM_TIM2_IN5_8
GETH_RXD2A
Mux input channel 5 of TIM module 4
Mux input channel 5 of TIM module 2
Receive Data 2 MII and RGMII (RGMII can use RXD2A
only)
CAN12_RXDD
CAN receive input node 2
General-purpose output
GTM muxed output
Reserved
P11.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT124
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
F14
P11.9
FAST /
General-purpose input
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN4_2
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT98
—
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
60
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G14
P11.10
I
FAST /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM3_IN5_2
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
61
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F13
P11.11
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN6_2
GTM_TIM3_IN0_14
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
Reserved
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
Master slave select output
Master slave select output
Chip Select
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P11.12
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
G13
I
FAST /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
GTM_TIM3_IN7_2
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
62
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K11
P11.13
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 6 of TIM module 2
Receive Error MII
GTM_TIM4_IN6_5
GTM_TIM2_IN6_7
GETH_RXERA
I2C1_SDAA
CAN13_RXDD
P11.13
Serial Data Input 0
CAN receive input node 3
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT125
—
—
Reserved
—
Reserved
—
Reserved
I2C1_SDA
—
Serial Data Output
Reserved
J12
P11.14
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
GTM_TIM4_IN7_4
GTM_TIM2_IN7_8
GETH_CRSDVB
GETH_RXDVB
GETH_CRSA
I2C1_SCLA
CAN20_RXDF
P11.14
Serial Clock Input 0
CAN receive input node 0
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT126
—
—
Reserved
—
Reserved
—
Reserved
I2C1_SCL
—
Serial Clock Output
Reserved
Data Sheet
63
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J11
P11.15
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 0
Collision MII
GTM_TIM4_IN7_5
GTM_TIM0_IN7_8
GETH_COLA
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT127
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-6 Port 12 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
K17
P12.0
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 3
CAN receive input node 0
Receive Clock MII
CDTM4_DTM4
GTM_TIM4_IN0_5
GTM_TIM3_IN0_7
CAN00_RXDC
GETH_RXCLKC
GTM_DTMA4_0
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT128
—
—
Reserved
—
Reserved
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
Data Sheet
64
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-6 Port 12 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K16
P12.1
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 3
MDIO Input
GTM_TIM4_IN1_6
GTM_TIM3_IN1_6
GETH_MDIOC
P12.1
O0
O1
O2
O3
O4
O5
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT129
ASCLIN3_ASLSO
—
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
O
—
Reserved
GETH_MDIO
MDIO Output
Table 2-7 Port 13 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G17
P13.0
I
LVDS_TX General-purpose input
/ FAST /
PU1 /
VEXT /
ES6
GTM_TIM3_IN5_3
GTM_TIM2_IN5_3
ASCLIN10_ARXC
ASCLIN21_ARXA
P13.0
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Receive input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
MSC0_FCLN
—
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
CAN transmit output node 0
Data Sheet
65
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F17
P13.1
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN6_3
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 6 of TIM module 2
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
Shift-clock direct part of the differential signal
Serial Clock Output
—
Reserved
G16
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN7_3
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 7 of TIM module 2
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
Serial Data Input 1
P13.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
ASCLIN21_ATX
Transmit output
Data Sheet
66
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F16
P13.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN0_3
GTM_TIM2_IN0_3
ASCLIN21_ARXB
P13.3
Mux input channel 0 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 2
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT94
ASCLIN10_ASLSO
QSPI2_MTSRP
—
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
MSC0_SOP
ASCLIN21_ATX
—
Data output - direct part of the differential signal
Transmit output
Reserved
B16
P13.4
LVDS_TX General-purpose input
/ FAST /
GTM_TIM6_IN0_4
GTM_TIM5_IN3_4
GTM_TIM3_IN3_8
P13.4
Mux input channel 0 of TIM module 6
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT253
—
Reserved
—
Reserved
MSC2_EN0
MSC2_FCLN
—
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN23_TXD
P13.5
CAN transmit output node 3
A16
LVDS_TX General-purpose input
/ FAST /
GTM_TIM6_IN1_4
GTM_TIM5_IN4_4
GTM_TIM3_IN4_9
CAN23_RXDD
P13.5
Mux input channel 1 of TIM module 6
PU1 /
VEXT /
ES6
Mux input channel 4 of TIM module 5
Mux input channel 4 of TIM module 3
CAN receive input node 3
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT254
—
Reserved
—
Reserved
—
Reserved
MSC2_FCLP
—
Shift-clock direct part of the differential signal
Reserved
—
Reserved
Data Sheet
67
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B15
P13.6
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM6_IN2_4
Mux input channel 2 of TIM module 6
PU1 /
VEXT /
ES6
GTM_TIM5_IN5_4
Mux input channel 5 of TIM module 5
GTM_TIM3_IN5_10
Mux input channel 5 of TIM module 3
P13.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM_TOUT255
GTM muxed output
—
Reserved
—
Reserved
—
Reserved
MSC2_SON
Data output - inverted part of the differential signal
—
Reserved
Reserved
—
A15
P13.7
LVDS_TX General-purpose input
/ FAST /
GTM_TIM6_IN3_4
Mux input channel 3 of TIM module 6
PU1 /
VEXT /
ES6
GTM_TIM5_IN6_4
Mux input channel 6 of TIM module 5
GTM_TIM3_IN6_10
Mux input channel 6 of TIM module 3
P13.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT256
GTM muxed output
—
Reserved
—
Reserved
—
Reserved
MSC2_SOP
Data output - direct part of the differential signal
—
—
Reserved
Reserved
Data Sheet
68
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A14
P13.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 2
Serial Clock Input 1
General-purpose output
GTM muxed output
Transmit output
GTM_TIM6_IN4_4
GTM_TIM4_IN7_6
GTM_TIM2_IN7_12
I2C1_SCLB
P13.9
O0
O1
O2
GTM_TOUT248
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
CAN21_TXD
I2C1_SCL
—
CAN transmit output node 1
Serial Clock Output
Reserved
B13
P13.10
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 1 of TIM module 5
Mux input channel 1 of TIM module 3
RXD inputs (receive data) channel 3
General-purpose output
GTM muxed output
Transmit output
GTM_TIM6_IN5_4
GTM_TIM5_IN1_5
GTM_TIM3_IN1_8
PSI5_RX3A
P13.10
O0
O1
O2
GTM_TOUT251
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
69
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A13
P13.11
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 0 of TIM module 5
Mux input channel 0 of TIM module 3
Receive input
GTM_TIM6_IN6_4
GTM_TIM5_IN0_9
GTM_TIM3_IN0_9
ASCLIN0_ARXE
ASCLIN7_ARXD
P13.11
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT250
—
—
Reserved
PSI5_TX3
—
TXD outputs (send data)
Reserved
—
Reserved
—
Reserved
B12
P13.12
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 0
Receive input
GTM_TIM6_IN7_4
GTM_TIM4_IN0_6
GTM_TIM0_IN0_11
ASCLIN3_ARXH
I2C1_SDAB
CAN21_RXDB
P13.12
Serial Data Input 1
CAN receive input node 1
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT249
ASCLIN7_ATX
—
Reserved
—
Reserved
—
Reserved
I2C1_SDA
—
Serial Data Output
Reserved
Data Sheet
70
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A12
P13.13
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 5 of TIM module 3
Injection signal from port
RXD inputs (receive data) channel 3
General-purpose output
GTM muxed output
Shift clock output
GTM_TIM5_IN5_5
GTM_TIM3_IN5_9
MSC2_INJ0
PSI5_RX3B
P13.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT262
ASCLIN7_ASCLK
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
B11
P13.14
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 5
Mux input channel 2 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN2_4
GTM_TIM3_IN2_7
P13.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT252
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
A11
P13.15
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 3
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TIM5_IN7_4
GTM_TIM3_IN7_9
P13.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT264
ASCLIN7_ASLSO
—
PSI5_TX3
TXD outputs (send data)
Reserved
—
—
—
Reserved
Reserved
Data Sheet
71
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G21
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input channel 17
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
SENT_SENT17D
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
72
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F20
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
SENT_SENT18D
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive input channel 18
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
K18
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
73
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G19
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
G20
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
74
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F19
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
CDTM2_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT85
—
Reserved
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
ERAY1_TXDB
P14.6
Transmit Channel B
Transmit Channel B
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
G18
FAST /
PU1 /
VEXT /
ES
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
Reserved
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
ERAY1_TXENB
Transmit Enable Channel B
Transmit Enable Channel B
Data Sheet
75
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J18
P14.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive Channel B0
Receive Channel B0
CAN receive input node 0
CAN receive input node 3
Receive input
GTM_TIM4_IN7_10
GTM_TIM1_IN0_5
GTM_TIM0_IN0_5
ERAY0_RXDB0
ERAY1_RXDB0
CAN10_RXDB
CAN13_RXDA
ASCLIN9_ARXC
ASCLIN20_ARXA
P14.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT87
ASCLIN0_ARTS
QSPI2_SLSO4
ASCLIN9_ATX
—
Ready to send output
Master slave select output
Transmit output
Reserved
—
Reserved
ASCLIN20_ATX
P14.8
Transmit output
F18
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Receive Channel A0
CAN receive input node 2
Receive input
GTM_TIM3_IN2_3
GTM_TIM2_IN2_3
ERAY0_RXDA0
CAN02_RXDD
ASCLIN1_ARXD
ERAY1_RXDA0
P14.8
Receive Channel A0
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT88
ASCLIN5_ASLSO
ASCLIN7_ASLSO
—
Slave select signal output
Slave select signal output
Reserved
—
Reserved
—
Reserved
ASCLIN20_ATX
Transmit output
Data Sheet
76
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J17
P14.9
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN3_3
GTM_TIM2_IN3_3
ASCLIN0_ACTSA
QSPI2_MRSTFN
ASCLIN9_ARXD
ASCLIN20_ARXB
P14.9
Mux input channel 3 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 3 of TIM module 2
Clear to send input
Master SPI data input (LVDS N line)
Receive input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT89
CAN23_TXD
MSC0_EN1
CAN transmit output node 3
Chip Select
CAN10_TXD
ERAY0_TXENB
ERAY0_TXENA
ERAY1_TXENA
P14.10
CAN transmit output node 0
Transmit Enable Channel B
Transmit Enable Channel A
Transmit Enable Channel A
J16
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN4_3
GTM_TIM2_IN4_3
CAN23_RXDA
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 4 of TIM module 2
CAN receive input node 3
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT90
—
MSC0_EN0
Chip Select
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
ERAY1_TXDA
Transmit output
Monitor input 2
Reference input 2
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel A
Transmit Channel A
Data Sheet
77
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A20
P14.11
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 1 of TIM module 3
Upstream assynchronous input signal
General-purpose output
GTM muxed output
GTM_TIM5_IN1_4
GTM_TIM3_IN1_9
MSC2_SDI1
P14.11
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT258
—
Reserved
—
Reserved
MSC2_EN2
Chip Select
MSC2_SOP
Data output - direct part of the differential signal
Reserved
—
—
Reserved
B19
P14.12
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 4 of TIM module 5
Mux input channel 4 of TIM module 3
Upstream assynchronous input signal
General-purpose output
GTM muxed output
GTM_TIM6_IN4_3
GTM_TIM5_IN4_5
GTM_TIM3_IN4_8
MSC2_SDI0
P14.12
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT261
ASCLIN5_ASCLK
ASCLIN7_ASCLK
—
Shift clock output
Shift clock output
Reserved
—
Reserved
—
Reserved
—
Reserved
A19
P14.13
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
GTM_TIM6_IN5_3
GTM_TIM5_IN3_5
GTM_TIM3_IN3_6
P14.13
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT260
—
Reserved
—
Reserved
MSC2_EN1
CAN22_TXD
—
Chip Select
CAN transmit output node 2
Reserved
—
Reserved
Data Sheet
78
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B18
P14.14
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 2 of TIM module 5
Mux input channel 2 of TIM module 3
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM6_IN6_3
GTM_TIM5_IN2_3
GTM_TIM3_IN2_8
CAN22_RXDD
P14.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT259
ASCLIN5_ATX
ASCLIN7_ATX
MSC2_EN0
CAN23_TXD
—
Transmit output
Chip Select
CAN transmit output node 3
Reserved
—
Reserved
A18
P14.15
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 6 of TIM module 5
Mux input channel 6 of TIM module 3
Injection signal from port
Receive input
GTM_TIM6_IN7_3
GTM_TIM5_IN6_5
GTM_TIM3_IN6_9
MSC2_INJ1
ASCLIN5_ARXD
ASCLIN7_ARXA
CAN23_RXDC
P14.15
Receive input
CAN receive input node 3
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT263
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
79
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G25
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
GTM_TIM3_IN3_4
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
F23
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM3_IN4_4
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
80
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H24
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Slave select input
GTM_TIM3_IN5_4
GTM_TIM2_IN5_4
QSPI2_SLSIA
SENT_SENT10D
QSPI2_MRSTE
P15.2
Receive input channel 10
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
G22
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM3_IN6_4
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI clock output
Reserved
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
81
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F22
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN7_4
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT11D
P15.4
Receive input channel 11
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
ASCLIN19_ATX
—
Monitor input 2
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Transmit output
O4
O5
O6
O7
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
82
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K19
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM3_IN0_4
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
F21
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
Receive input
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
ASCLIN19_ARXA
P15.6
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
83
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J20
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
ASCLIN19_ARXB
P15.7
Master SPI data input
Receive input
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
ASCLIN19_ATX
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Transmit output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
J19
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
84
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B24
P15.10
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN1_7
GTM_TIM2_IN1_8
P15.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT242
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
A24
P15.11
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN2_6
GTM_TIM2_IN2_8
P15.11
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT243
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
B23
P15.12
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN3_6
GTM_TIM2_IN3_6
P15.12
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT244
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
85
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A23
P15.13
I
FAST /
PU1 /
VEXT /
ES6
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 4 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN4_6
GTM_TIM2_IN4_9
P15.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT245
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
B22
P15.14
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 5 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN5_6
GTM_TIM2_IN5_12
P15.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT246
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
A22
P15.15
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN6_6
GTM_TIM2_IN6_9
P15.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT247
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
86
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-10 Port 20 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
N25
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CAN21_RXDC
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
CAN receive input node 1
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
Shift clock output
Reserved
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
Trigger output
M24
P20.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Trigger input
GTM_TIM4_IN4_11
GTM_TIM3_IN3_5
GTM_TIM2_IN3_5
CBS_TGI1
GTM_DTMA1_1
CDTM1_DTM4
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT60
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CBS_TGO1
Trigger output
Data Sheet
87
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N24
P20.2
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
P20.3
Testmode Enable Input
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
M25
I
SLOW /
PU1 /
VEXT /
ES
GTM_TIM4_IN5_11
GTM_TIM3_IN4_5
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CAN21_TXD
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
CAN transmit output node 1
Reserved
L22
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM6_IN0_1
GTM_TIM3_IN6_5
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
Ready to send output
Master slave select output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
88
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L24
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
Mux input channel 1 of TIM module 6
CAN receive input node 0
Clear to send input
GTM_TIM3_IN7_5
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
GTM_TIM6_IN1_1
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
L25
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM6_IN2_1
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
89
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K22
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM6_IN3_1
GTM_TIM3_IN5_5
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Mux input channel 3 of TIM module 6
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
K24
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM3_IN6_6
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
90
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K25
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN7_6
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
J24
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN0_5
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Master SPI data output
Reserved
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
91
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J25
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM3_IN1_4
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
H25
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN2_4
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
92
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-11 Port 21 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
R22
P21.0
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN0_11
GTM_TIM3_IN4_6
GTM_TIM2_IN4_6
QSPI4_MRSTDN
DMU_FDEST
ASCLIN11_ARXC
ASCLIN17_ARXB
P21.0
Mux input channel 0 of TIM module 4
PU1 /
VEXT /
ES
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Master SPI data input (LVDS N line)
Enter destructive debug mode
Receive input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT51
ASCLIN11_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM1
P21.1
Pin Output Value
P22
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN1_13
GTM_TIM3_IN5_6
GTM_TIM2_IN5_6
QSPI4_MRSTDP
ASCLIN11_ARXD
ASCLIN18_ARXA
GTM_DTMA4_1
P21.1
Mux input channel 1 of TIM module 4
PU1 /
VEXT /
ES
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Master SPI data input (LVDS P line)
Receive input
Receive input
CDTM4_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT52
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM2
Pin Output Value
Data Sheet
93
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R24
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN4_11
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 4 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
QSPI4_MRSTCN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Master SPI data input (LVDS N line)
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
P24
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN5_12
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
QSPI4_MRSTCP
P21.3
Mux input channel 5 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Shift clock output
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT54
ASCLIN11_ASCLK
ASCLIN18_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
94
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R25
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN6_12
GTM_TIM1_IN2_6
GTM_TIM0_IN2_6
ASCLIN18_ARXB
P21.4
Mux input channel 6 of TIM module 5
PU1 /
VEXT /
ES6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Slave select signal output
Transmit output
GTM_TOUT55
ASCLIN11_ASLSO
ASCLIN18_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
P25
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN7_11
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 7 of TIM module 5
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
95
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N22
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ.
Mux input channel 2 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM4_IN2_12
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
96
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N21
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GTM_TIM4_IN3_12
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Table 2-12 Port 22 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
W25
P22.0
I
LVDS_TX General-purpose input
/ FAST /
PU1 /
VEXT /
ES6
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
QSPI4_MTSRB
ASCLIN6_ARXE
P22.0
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Slave SPI data input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT47
ASCLIN3_ATXN
QSPI4_MTSR
QSPI4_SCLKN
MSC1_FCLN
—
GTM muxed output
Differential Transmit output (low active)
Master SPI data output
Master SPI clock output (LVDS N line)
Shift-clock inverted part of the differential signal
Reserved
ASCLIN6_ATX
Transmit output
Data Sheet
97
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W24
P22.1
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
QSPI4_MRSTB
ASCLIN7_ARXE
P22.1
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 0
Master SPI data input
Receive input
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT48
ASCLIN3_ATXP
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI4_SCLKP
MSC1_FCLP
—
Differential Transmit output (high active)
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Master SPI clock output (LVDS P line)
Shift-clock direct part of the differential signal
Reserved
ASCLIN7_ATX
P22.2
Transmit output
Y25
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
QSPI4_SLSIB
P22.2
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Slave select input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT49
ASCLIN5_ATX
QSPI4_SLSO3
QSPI4_MTSRN
MSC1_SON
—
Transmit output
Master slave select output
Master SPI data output (LVDS N line)
Data output - inverted part of the differential signal
Reserved
—
Reserved
Data Sheet
98
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y24
P22.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
QSPI4_SCLKB
ASCLIN5_ARXC
P22.3
Mux input channel 4 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 4 of TIM module 0
Slave SPI clock inputs
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT50
—
QSPI4_SCLK
QSPI4_MTSRP
MSC1_SOP
—
Master SPI clock output
Master SPI data output (LVDS P line)
Data output - direct part of the differential signal
Reserved
—
Reserved
W21
P22.4
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Receive input
GTM_TIM3_IN0_8
ASCLIN7_ARXF
GTM_DTMA3_0
P22.4
CDTM3_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT130
ASCLIN4_ASLSO
—
QSPI0_SLSO12
—
Master slave select output
Reserved
CAN13_TXD
—
CAN transmit output node 3
Reserved
W22
P22.5
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 3
Slave SPI data input
CAN receive input node 3
General-purpose output
GTM muxed output
Transmit output
GTM_TIM3_IN1_7
QSPI0_MTSRC
CAN13_RXDC
P22.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT131
ASCLIN4_ATX
—
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
Data Sheet
99
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
V21
P22.6
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 2
Master SPI data input
Receive input
GTM_TIM3_IN2_6
GTM_TIM2_IN6_14
QSPI0_MRSTC
ASCLIN4_ARXC
P22.6
O0
O1
O2
O3
O4
General-purpose output
GTM muxed output
Reserved
GTM_TOUT132
—
—
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
CAN21_TXD
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
I
CAN transmit output node 1
Reserved
—
Reserved
V22
P22.7
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 3
Slave SPI clock inputs
CAN receive input node 1
General-purpose output
GTM muxed output
Shift clock output
GTM_TIM3_IN3_7
QSPI0_SCLKC
CAN21_RXDF
P22.7
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT133
ASCLIN4_ASCLK
ASCLIN17_ATX
QSPI0_SCLK
—
Transmit output
Master SPI clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
100
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U21
P22.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 5
Mux input channel 4 of TIM module 3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Shift clock output
GTM_TIM5_IN0_4
GTM_TIM3_IN4_7
QSPI0_SCLKB
P22.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT134
ASCLIN5_ASCLK
—
Reserved
QSPI0_SCLK
CAN22_TXD
—
Master SPI clock output
CAN transmit output node 2
Reserved
—
Reserved
U22
P22.9
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 5 of TIM module 3
Master SPI data input
Receive input
GTM_TIM5_IN1_10
GTM_TIM3_IN5_7
QSPI0_MRSTB
ASCLIN4_ARXD
CAN22_RXDE
GTM_DTMA3_1
P22.9
CAN receive input node 2
CDTM3_DTM4
O0
O1
O2
O3
O4
General-purpose output
GTM muxed output
Reserved
GTM_TOUT135
—
—
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
Reserved
—
Reserved
—
Reserved
Data Sheet
101
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T21
P22.10
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 5
Mux input channel 6 of TIM module 3
Slave SPI data input
General-purpose output
GTM muxed output
GTM_TIM5_IN2_8
GTM_TIM3_IN6_7
QSPI0_MTSRB
P22.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT136
ASCLIN4_ATX
—
Transmit output
Reserved
QSPI0_MTSR
CAN23_TXD
—
Master SPI data output
CAN transmit output node 3
Reserved
—
Reserved
T22
P22.11
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 7 of TIM module 3
CAN receive input node 3
Receive input
GTM_TIM5_IN3_10
GTM_TIM3_IN7_7
CAN23_RXDE
ASCLIN17_ARXA
P22.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT137
ASCLIN4_ASLSO
ASCLIN17_ATX
QSPI0_SLSO10
—
Slave select signal output
Transmit output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
102
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-13 Port 23 Functions
Ball Symbol
Ctrl. Buffer
Type
Function
AC25 P23.0
GTM_TIM6_IN7_1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 0
General-purpose output
GTM muxed output
GTM_TIM1_IN5_4
GTM_TIM0_IN5_4
CAN10_RXDC
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT41
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AB24 P23.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Upstream assynchronous input signal
Receive input
GTM_TIM6_IN6_1
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
MSC1_SDI0
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT42
ASCLIN1_ARTS
QSPI4_SLSO6
GTM_CLK0
Ready to send output
Master slave select output
CGM generated clock
CAN transmit output node 0
External Clock 0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
Shift clock output
Data Sheet
103
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-13 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AB25 P23.2
GTM_TIM6_IN5_1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_5
GTM_TIM0_IN6_5
ASCLIN7_ARXC
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT43
—
Reserved
—
Reserved
CAN23_TXD
CAN transmit output node 3
CAN transmit output node 2
Reserved
CAN12_TXD
—
—
Reserved
AA24 P23.3
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
Injection signal from port
Receive input
GTM_TIM6_IN4_2
GTM_TIM1_IN7_4
GTM_TIM0_IN7_4
MSC1_INJ0
ASCLIN6_ARXA
CAN12_RXDC
CAN23_RXDB
P23.3
CAN receive input node 2
CAN receive input node 3
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT44
ASCLIN7_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
104
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-13 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AA25 P23.4
GTM_TIM6_IN3_2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_5
GTM_TIM0_IN7_5
P23.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT45
ASCLIN6_ASLSO
QSPI4_SLSO5
—
Slave select signal output
Master slave select output
Reserved
MSC1_EN0
—
Chip Select
Reserved
—
Reserved
AA22 P23.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Receive input
GTM_TIM6_IN2_2
GTM_TIM1_IN2_7
GTM_TIM0_IN2_7
ASCLIN16_ARXA
P23.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT46
ASCLIN6_ATX
QSPI4_SLSO4
—
Transmit output
Master slave select output
Reserved
MSC1_EN1
CAN22_TXD
—
Chip Select
CAN transmit output node 2
Reserved
Y22
P23.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 1
CAN receive input node 2
General-purpose output
GTM muxed output
GTM_TIM6_IN1_2
GTM_TIM4_IN2_7
GTM_TIM1_IN2_10
CAN22_RXDC
P23.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT138
ASCLIN16_ATX
—
Transmit output
Reserved
QSPI0_SLSO11
CAN11_TXD
—
Master slave select output
CAN transmit output node 1
Reserved
—
Reserved
Data Sheet
105
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-13 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y21
P23.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 1
CAN receive input node 1
Receive input
GTM_TIM6_IN0_2
GTM_TIM4_IN3_7
GTM_TIM1_IN3_10
CAN11_RXDC
ASCLIN16_ARXB
P23.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT139
ASCLIN16_ATX
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-14 Port 24 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
U29
P24.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 0 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN0_6
GTM_TIM4_IN0_8
P24.0
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT222
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
106
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-14 Port 24 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U30
P24.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 1 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN1_6
GTM_TIM4_IN1_8
P24.1
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT223
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
T29
P24.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 2 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN2_6
GTM_TIM4_IN2_8
P24.2
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT224
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
T30
P24.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 3 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN3_6
GTM_TIM4_IN3_8
P24.3
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT225
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
107
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-14 Port 24 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R29
P24.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 4 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN4_5
GTM_TIM4_IN4_7
P24.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT226
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
R30
P24.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 5 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN5_5
GTM_TIM4_IN5_7
P24.5
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT227
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
P29
P24.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 6 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN6_5
GTM_TIM4_IN6_7
P24.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT228
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
108
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-14 Port 24 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P30
P24.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 7 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN7_5
GTM_TIM4_IN7_7
P24.7
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT229
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
N29
P24.8
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN0_5
P24.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT230
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
N30
P24.9
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN1_6
P24.9
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT231
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
109
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-14 Port 24 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
M29
P24.10
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN2_5
P24.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT232
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
M30
P24.11
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN3_6
P24.11
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT233
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
L29
P24.12
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN4_6
P24.12
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT234
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
110
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-14 Port 24 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L30
P24.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN5_6
P24.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT235
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
K29
P24.14
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN6_6
P24.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT236
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
K30
P24.15
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN7_5
P24.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT237
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
111
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-15 Port 25 Functions
Ball Symbol
Ctrl. Buffer
Type
Function
AG30 P25.0
GTM_TIM6_IN0_7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 0 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN0_12
P25.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT206
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AF30 P25.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 1 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN1_7
GTM_TIM3_IN1_11
P25.1
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT207
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AF29 P25.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 2 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN2_7
GTM_TIM3_IN2_9
P25.2
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT208
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
112
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-15 Port 25 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE30 P25.3
GTM_TIM6_IN3_7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN3_9
P25.3
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT209
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AE29 P25.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 4 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN4_6
GTM_TIM3_IN4_10
P25.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT210
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AD30 P25.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 5 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN5_6
GTM_TIM3_IN5_11
P25.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT211
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
113
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-15 Port 25 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W29
P25.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 6 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN6_6
GTM_TIM3_IN6_14
P25.6
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT212
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AD29 P25.7
GTM_TIM6_IN7_6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 7 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN7_10
P25.7
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT213
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AC29 P25.8
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN0_9
P25.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT214
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
114
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-15 Port 25 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AC30 P25.9
GTM_TIM4_IN1_9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 4
General-purpose output
GTM muxed output
Reserved
P25.9
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT215
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AB29 P25.10
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN2_9
P25.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT216
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AB30 P25.11
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN3_9
P25.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT217
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
115
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-15 Port 25 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AA29 P25.12
GTM_TIM4_IN4_8
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
General-purpose output
GTM muxed output
Reserved
P25.12
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT218
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AA30 P25.13
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN5_8
P25.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT219
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Y29
P25.14
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN6_8
P25.14
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT220
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
116
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-15 Port 25 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y30
P25.15
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN7_8
P25.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT221
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-16 Port 26 Functions
Ball Symbol
Ctrl. Buffer
Type
Function
AG29 P26.0
GTM_TIM6_IN6_9
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 6 of TIM module 3
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN6_11
P26.0
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT212
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
117
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-17 Port 30 Functions
Ball Symbol
Ctrl. Buffer
Type
Function
AJ21 P30.0
GTM_TIM4_IN0_10
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
General-purpose output
GTM muxed output
Reserved
P30.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT190
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK21 P30.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN1_10
P30.1
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT191
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ22 P30.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN2_10
P30.2
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT192
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
118
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-17 Port 30 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AK22 P30.3
GTM_TIM4_IN3_10
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
General-purpose output
GTM muxed output
Reserved
P30.3
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT193
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ23 P30.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN4_9
P30.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT194
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK23 P30.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN5_9
P30.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT195
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
119
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-17 Port 30 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AJ24 P30.6
GTM_TIM4_IN6_9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 4
General-purpose output
GTM muxed output
Reserved
P30.6
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT196
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK24 P30.7
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN7_9
P30.7
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT197
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ25 P30.8
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 0 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN0_8
GTM_TIM5_IN0_6
P30.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT198
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
120
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-17 Port 30 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AK25 P30.9
GTM_TIM6_IN1_8
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 1 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN1_7
P30.9
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT199
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ26 P30.10
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 2 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN2_8
GTM_TIM5_IN2_6
P30.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT200
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK26 P30.11
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 3 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN3_8
GTM_TIM5_IN3_7
P30.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT201
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
121
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-17 Port 30 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AJ27 P30.12
GTM_TIM6_IN4_7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 4 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN4_7
P30.12
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT202
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK27 P30.13
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 5 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN5_7
GTM_TIM5_IN5_7
P30.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT203
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ28 P30.14
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 6 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN6_7
GTM_TIM5_IN6_7
P30.14
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT204
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
122
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-17 Port 30 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AK28 P30.15
GTM_TIM6_IN7_7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 7 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN7_6
P30.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT205
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-18 Port 31 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
AJ12 P31.0
GTM_TIM2_IN0_13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P31.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT174
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK12 P31.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN1_9
P31.1
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT175
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
123
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-18 Port 31 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AJ13 P31.2
GTM_TIM2_IN2_9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P31.2
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT176
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK13 P31.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN3_14
P31.3
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT177
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ14 P31.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN4_12
P31.4
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT178
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
124
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-18 Port 31 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AK14 P31.5
GTM_TIM2_IN5_13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 2
General-purpose output
GTM muxed output
Reserved
P31.5
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT179
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ15 P31.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN6_12
P31.6
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT180
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK15 P31.7
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN7_14
P31.7
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT181
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
125
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-18 Port 31 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AJ16 P31.8
GTM_TIM6_IN0_9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 0 of TIM module 5
Receive input channel 20
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN0_7
SENT_SENT20C
P31.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT182
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK16 P31.9
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 1 of TIM module 5
Receive input channel 21
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN1_9
GTM_TIM5_IN1_8
SENT_SENT21C
P31.9
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT183
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ17 P31.10
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 2 of TIM module 5
Receive input channel 22
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN2_9
GTM_TIM5_IN2_7
SENT_SENT22C
P31.10
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT184
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
126
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-18 Port 31 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AK17 P31.11
GTM_TIM6_IN3_9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 3 of TIM module 5
Receive input channel 23
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN3_8
SENT_SENT23C
P31.11
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT185
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AJ18 P31.12
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 4 of TIM module 5
Receive input channel 24
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN4_8
GTM_TIM5_IN4_8
SENT_SENT24C
P31.12
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT186
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK18 P31.13
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 5 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN5_8
GTM_TIM5_IN5_8
P31.13
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT187
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
127
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-18 Port 31 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AJ19 P31.14
GTM_TIM6_IN6_8
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 6 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN6_8
P31.14
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT188
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AK19 P31.15
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 7 of TIM module 5
General-purpose output
GTM muxed output
Reserved
GTM_TIM6_IN7_8
GTM_TIM5_IN7_7
P31.15
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT189
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
128
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-19 Port 32 Functions
Ball Symbol
Ctrl. Buffer
Type
Function
AE22 P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM3_IN2_5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN2_5
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
AD22 P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
GTM_TIM3_IN3_15
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
Reserved
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT37
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
129
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-19 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE23 P32.2
GTM_TIM1_IN3_8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 3
Receive input
GTM_TIM0_IN3_8
CAN03_RXDB
ASCLIN3_ARXD
CAN21_RXDD
P32.2
CAN receive input node 1
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT38
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
AE24 P32.3
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN4_5
GTM_TIM0_IN4_5
P32.3
O0
O1
O2
GTM_TOUT39
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN3_ASCLK
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CAN21_TXD
—
Shift clock output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
CAN transmit output node 1
Reserved
Data Sheet
130
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-19 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD23 P32.4
GTM_TIM1_IN5_5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
MSC1_SDI2
Upstream assynchronous input signal
Receive input
ASCLIN15_ARXA
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT40
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
GTM_CLK1
CGM generated clock
Chip Select
MSC1_EN0
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
AA20 P32.5
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 1 of TIM module 4
Mux input channel 5 of TIM module 3
Receive input channel 10
General-purpose output
GTM muxed output
GTM_TIM5_IN5_9
GTM_TIM4_IN1_14
GTM_TIM3_IN5_8
SENT_SENT10C
P32.5
O0
O1
O2
GTM_TOUT140
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
Reserved
—
Reserved
—
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
Reserved
Data Sheet
131
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-19 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AB20 P32.6
GTM_TIM5_IN6_9
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 4 of TIM module 4
Mux input channel 6 of TIM module 3
CAN receive input node 2
Trigger input
GTM_TIM4_IN4_15
GTM_TIM3_IN6_8
CAN02_RXDC
CBS_TGI4
ASCLIN2_ARXF
ASCLIN6_ARXC
SENT_SENT11C
P32.6
Receive input
Receive input
Receive input channel 11
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT141
—
—
Reserved
QSPI2_SLSO12
CAN22_TXD
—
Master slave select output
CAN transmit output node 2
Reserved
—
Reserved
CBS_TGO4
Trigger output
AB21 P32.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 0 of TIM module 4
Mux input channel 7 of TIM module 3
Trigger input
GTM_TIM5_IN7_8
GTM_TIM4_IN0_15
GTM_TIM3_IN7_8
CBS_TGI5
CAN22_RXDB
SENT_SENT12C
ASCLIN15_ARXB
P32.7
CAN receive input node 2
Receive input channel 12
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT142
ASCLIN6_ATX
—
Reserved
ASCLIN15_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
CBS_TGO5
Trigger output
Data Sheet
132
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions
Ball Symbol
Ctrl. Buffer
Type
Function
AD15 P33.0
GTM_TIM3_IN0_13
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 13
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
SENT_SENT13C
IOM_PIN_0
GTM_DTMT1_2
EVADC_G10CH7
P33.0
AI
Analog input channel 7, group 10
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
Reserved
ASCLIN15_ATX
—
Transmit output
Reserved
EVADC_FC2BFLOUT
—
Boundary flag output, FC channel 2
Reserved
Data Sheet
133
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE15 P33.1
GTM_TIM3_IN1_15
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
Receive input
GPIO pad input to FPC
EVADC_G10CH6
P33.1
AI
Analog input channel 6, group 10
General-purpose output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
O2
O3
O4
O5
O6
O7
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
134
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD16 P33.2
GTM_TIM3_IN2_14
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Digital datastream input, channel 2
GPIO pad input to FPC
EVADC_G10CH5
P33.2
AI
Analog input channel 5, group 10
General-purpose output
O0
O1
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
EVADC_FC3BFLOUT
ASCLIN14_ATX
Monitor input 1
Reference input 1
O5
O6
O7
Control of external analog multiplexer interface 0
Boundary flag output, FC channel 3
Transmit output
Data Sheet
135
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE16 P33.3
GTM_TIM3_IN3_12
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
SENT_SENT7C
EDSADC_DSCIN1B
ASCLIN14_ARXA
IOM_PIN_3
Modulator clock input, channel 1
Receive input
GPIO pad input to FPC
EVADC_G10CH4
P33.3
AI
Analog input channel 4, group 10
General-purpose output
O0
O1
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
ASCLIN5_ASCLK
QSPI4_SLSO2
EDSADC_DSCOUT1
EVADC_EMUX00
—
O2
O3
O4
O5
O6
O7
Master slave select output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
ASCLIN14_ATX
Transmit output
Data Sheet
136
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD17 P33.4
GTM_TIM4_IN4_10
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
ASCLIN14_ARXB
IOM_PIN_4
Digital datastream input, channel 1
Trap input capture
Receive input
Receive input
GPIO pad input to FPC
GTM_DTMT2_0
EVADC_G10CH3
P33.4
CDTM2_DTM0
AI
Analog input channel 3, group 10
General-purpose output
O0
O1
GTM_TOUT26
IOM_MON0_4
GTM muxed output
Monitor input 0
IOM_GTM_4
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
137
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE17 P33.5
GTM_TIM4_IN5_10
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
ASCLIN2_ACTSB
CCU61_CCPOS2C
PSI5_RX2C
Clear to send input
Hall capture input 2
RXD inputs (receive data) channel 2
Receive input channel 5
SENT_SENT5C
CAN13_RXDB
CAN receive input node 3
IOM_PIN_5
GPIO pad input to FPC
EVADC_G10CH2
P33.5
AI
Analog input channel 2, group 10
General-purpose output
O0
O1
GTM_TOUT27
IOM_MON0_5
GTM muxed output
Monitor input 0
IOM_GTM_5
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
EVADC_FC2BFLOUT
ASCLIN5_ASLSO
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 2
Slave select signal output
Data Sheet
138
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD18 P33.6
GTM_TIM1_IN2_9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
GTM_DTMT2_1
EVADC_G10CH1
P33.6
CDTM2_DTM0
AI
Analog input channel 1, group 10
General-purpose output
O0
O1
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
TXD outputs (send data)
ASCLIN2_ASLSO
QSPI2_SLSO11
PSI5_TX2
O2
O3
O4
IOM_REF1_15
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Reference input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
139
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE18 P33.7
GTM_TIM1_IN3_9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT14C
IOM_PIN_7
Receive input channel 14
GPIO pad input to FPC
Analog input channel 0, group 10
General-purpose output
GTM muxed output
EVADC_G10CH0
P33.7
AI
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
QSPI4_SLSO7
ASCLIN8_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Master slave select output
Transmit output
Reserved
EVADC_FC3BFLOUT
—
Boundary flag output, FC channel 3
Reserved
Data Sheet
140
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD19 P33.8
GTM_TIM1_IN4_7
I
FAST /
HighZ /
VEVRSB
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
GTM_TIM0_IN4_7
ASCLIN2_ARXE
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO2
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
O
FSP[1..0] Output Signals - Generated by SMU_core
Data Sheet
141
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE19 P33.9
GTM_TIM1_IN1_9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO1
ASCLIN2_ASCLK
CAN01_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Shift clock output
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
142
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD20 P33.10
GTM_TIM4_IN4_14
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave select input
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
QSPI4_SLSIA
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
CAN receive input node 1
Receive input
GPIO pad input to FPC
P33.10
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
QSPI4_SLSO0
ASCLIN1_ASLSO
PSI5S_CLK
Monitor input 0
O2
O3
O4
O5
Master slave select output
Master slave select output
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GPIO pad input to FPC
General-purpose output
GTM muxed output
AE20 P33.11
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
QSPI4_SCLKA
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
QSPI4_SCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Master SPI clock output
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
143
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD21 P33.12
GTM_TIM3_IN0_6
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Slave SPI data input
GTM_TIM2_IN0_6
QSPI4_MTSRA
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MTSR
ASCLIN1_ASCLK
CAN22_TXD
Monitor input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Shift clock output
CAN transmit output node 2
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 1
Data Sheet
144
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AE21 P33.13
GTM_TIM3_IN1_5
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
QSPI4_MRSTA
MSC1_INJ1
Carrier sign signal input
Master SPI data input
Injection signal from port
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
CAN22_RXDA
P33.13
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
145
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-20 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AA19 P33.14
GTM_TIM5_IN0_8
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 5
Mux input channel 5 of TIM module 4
Mux input channel 0 of TIM module 2
Slave SPI clock inputs
Trigger input
GTM_TIM4_IN5_14
GTM_TIM2_IN0_8
QSPI2_SCLKD
CBS_TGI6
P33.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT143
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
CBS_TGO6
T12 PWM channel 62
Monitor input 1
Reference input 1
O
I
Trigger output
AB19 P33.15
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 6 of TIM module 4
Mux input channel 1 of TIM module 2
Trigger input
GTM_TIM5_IN1_9
GTM_TIM4_IN6_12
GTM_TIM2_IN1_7
CBS_TGI7
P33.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT144
—
QSPI2_SLSO11
—
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
CBS_TGO7
T12 PWM channel 62
Monitor input 1
Reference input 1
O
Trigger output
Data Sheet
146
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-21 Port 34 Functions
Ball Symbol
Ctrl. Buffer
Type
Function
AB16 P34.1
GTM_TIM5_IN3_9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 4 of TIM module 3
Mux input channel 3 of TIM module 2
Analog input channel 11, group 10
General-purpose output
GTM muxed output
GTM_TIM3_IN4_12
GTM_TIM2_IN3_9
EVADC_G10CH11
P34.1
AI
O0
O1
O2
O3
O4
GTM_TOUT146
ASCLIN4_ATX
—
Transmit output
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
CAN20_TXD
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O5
O6
O7
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
T13 PWM channel 63
Monitor input 1
Reference input 1
AA17 P34.2
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 5 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM5_IN4_9
GTM_TIM3_IN5_13
GTM_TIM2_IN4_8
ASCLIN4_ARXB
CAN00_RXDG
CAN20_RXDC
EVADC_G10CH10
P34.2
CAN receive input node 0
CAN receive input node 0
Analog input channel 10, group 10
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT147
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
147
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-21 Port 34 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AB17 P34.3
GTM_TIM5_IN5_10
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 6 of TIM module 3
Mux input channel 5 of TIM module 2
Analog input channel 9, group 10
General-purpose output
GTM muxed output
GTM_TIM3_IN6_13
GTM_TIM2_IN5_9
EVADC_G10CH9
P34.3
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT148
ASCLIN4_ASCLK
—
Shift clock output
Reserved
QSPI2_SLSO10
—
Master slave select output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
AA18 P34.4
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 7 of TIM module 3
Mux input channel 6 of TIM module 2
Master SPI data input
Analog input channel 8, group 10
General-purpose output
GTM muxed output
GTM_TIM5_IN6_10
GTM_TIM3_IN7_12
GTM_TIM2_IN6_8
QSPI2_MRSTD
EVADC_G10CH8
P34.4
AI
O0
O1
O2
O3
O4
GTM_TOUT149
ASCLIN4_ASLSO
—
Slave select signal output
Reserved
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
Reserved
—
Reserved
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
148
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-21 Port 34 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AB18 P34.5
GTM_TIM5_IN7_9
I
FAST /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 2
Slave SPI data input
Receive input
GTM_TIM4_IN7_12
GTM_TIM2_IN7_9
QSPI2_MTSRD
ASCLIN8_ARXE
P34.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT150
ASCLIN8_ATX
—
Reserved
QSPI2_MTSR
—
Master SPI data output
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Table 2-22 Analog Inputs
Ball
Symbol
Ctrl. Buffer
Type
Function
AA15 AN0
EVADC_G0CH0
EDSADC_EDS3PA
AB15 AN1
I
I
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
Analog input channel 0, group 0
Positive analog input channel 3, pin A
D / HighZ Analog Input 1
/ VDDM
EVADC_G0CH1
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
EDSADC_EDS3NA
AD14 AN2
/ VDDM
EVADC_G0CH2
Analog input channel 2, group 0
EDSADC_EDS0PA
Positive analog input channel 0, pin A
AB14 AN3
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
Analog input channel 3, group 0
Negative analog input channel 0, pin A
D / HighZ Analog Input 4
EDSADC_EDS0NA
AA14 AN4
/ VDDM
EVADC_G11CH0
EVADC_G0CH4
Analog input channel 0, group 11
Analog input channel 4, group 0
AE14 AN5
D / HighZ Analog Input 5
/ VDDM
EVADC_G11CH1
EVADC_G0CH5
Analog input channel 1, group 11
Analog input channel 5, group 0
Data Sheet
149
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-22 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AA13 AN6
EVADC_G11CH2
EVADC_G0CH6
AB13 AN7
I
I
I
I
I
I
I
I
I
I
I
I
D / HighZ Analog Input 6
/ VDDM
Analog input channel 2, group 11
Analog input channel 6, group 0
D / HighZ Analog Input 7
/ VDDM
EVADC_G11CH3
EVADC_G0CH7
Analog input channel 3, group 11
Analog input channel 7, group 0
AD13 AN8
D / HighZ Analog Input 8
/ VDDM
EVADC_G11CH4
EVADC_G1CH0
Analog input channel 4, group 11
Analog input channel 0, group 1
D / HighZ Analog Input 9
AB12 AN9
/ VDDM
EVADC_G11CH5
EVADC_G1CH1
Analog input channel 5, group 11
Analog input channel 1, group 1
AE13 AN10
D / HighZ Analog Input 10
/ VDDM
EVADC_G11CH6
EVADC_G1CH2
Analog input channel 6, group 11
Analog input channel 2, group 1
D / HighZ Analog Input 11
AD12 AN11
/ VDDM
EVADC_G11CH7
EVADC_G1CH3
Analog input channel 7, group 11
Analog input channel 3, group 1
AA12 AN12
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
EDSADC_EDS0PB
AD11 AN13
/ VDDM
EVADC_G1CH5
Analog input channel 5, group 1
EDSADC_EDS0NB
Negative analog input channel 0, pin B
AB11 AN14
D / HighZ Analog Input 14
/ VDDM
EVADC_G1CH6
Analog input channel 6, group 1
Positive analog input channel 3, pin B
D / HighZ Analog Input 15
EDSADC_EDS3PB
AA11 AN15
/ VDDM
EVADC_G1CH7
Analog input channel 7, group 1
EDSADC_EDS3NB
Negative analog input channel 3, pin N
AD10 AN16
D / HighZ Analog Input 16
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
AB10 AN17/P40.10
SENT_SENT10A
Analog input channel 0, group 2
Analog input FC channel 0
S / HighZ Analog Input 17
/ VDDM
Receive input channel 10
EVADC_G2CH1
Analog input channel 1, group 2
Analog input FC channel 1
EVADC_FC1CH0
Data Sheet
150
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-22 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD9
AN18/P40.11
I
S / HighZ Analog Input 18
/ VDDM
SENT_SENT11A
EVADC_G11CH8
EVADC_G2CH2
AN19/P40.12
Receive input channel 11
Analog input channel 8, group 11
Analog input channel 2, group 2
AD8
I
S / HighZ Analog Input 19
/ VDDM
SENT_SENT12A
EVADC_G11CH9
EVADC_G2CH3
AN20
Receive input channel 12
Analog input channel 9, group 11
Analog input channel 3, group 2
AE8
AE7
I
I
D / HighZ Analog Input 20
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
Analog input channel 5, group 2
Negative analog input channel 2, pin A
AA10 AN22
EVADC_G2CH6
AN23
I
I
I
D / HighZ Analog Input 22
/ VDDM
Analog input channel 6, group 2
Y10
AD7
D / HighZ Analog Input 23
/ VDDM
EVADC_G2CH7
AN24/P40.0
Analog input channel 7, group 2
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
AD6
AC7
AC6
I
I
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN26/P40.2
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
S / HighZ Analog Input 26
/ VDDM
SENT_SENT2A
EVADC_G3CH2
CCU60_CCPOS1D
EVADC_G11CH10
AN27/P40.3
Receive input channel 2
Analog input channel 2, group 3
Hall capture input 1
Analog input channel 10, group 11
S / HighZ Analog Input 27
/ VDDM
SENT_SENT3A
EVADC_G3CH3
CCU60_CCPOS2B
EVADC_G11CH11
Receive input channel 3
Analog input channel 3, group 3
Hall capture input 2
Analog input channel 11, group 11
Data Sheet
151
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-22 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AB7
AN28/P40.13
I
S / HighZ Analog Input 28
/ VDDM
SENT_SENT13A
EVADC_G3CH4
EVADC_G4CH4
AN29/P40.14
Receive input channel 13
Analog input channel 4, group 3
Analog input channel 4, group 4
AB6
I
S / HighZ Analog Input 29
/ VDDM
SENT_SENT14A
EVADC_G3CH5
EVADC_G4CH5
AN30
Receive input channel 14
Analog input channel 5, group 3
Analog input channel 5, group 4
AA9
Y9
I
I
I
D / HighZ Analog Input 30
/ VDDM
EVADC_G3CH6
EVADC_G4CH6
AN31
Analog input channel 6, group 3
Analog input channel 6, group 4
D / HighZ Analog Input 31
/ VDDM
EVADC_G3CH7
EVADC_G4CH7
AN32/P40.4
Analog input channel 7, group 3
Analog input channel 7, group 4
W9
S / HighZ Analog Input 32
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
EVADC_G11CH12
AN33/P40.5
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
Analog input channel 12, group 11
Y6
I
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
EVADC_G11CH13
AN34
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
Analog input channel 13, group 11
W10
Y7
I
I
I
D / HighZ Analog Input 34
/ VDDM
EVADC_G8CH2
EVADC_G11CH14
AN35
Analog input channel 2, group 8
Analog input channel 14, group 11
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
EVADC_G11CH15
AN36/P40.6
Analog input channel 3, group 8
Analog input channel 15, group 11
V9
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
Data Sheet
152
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-22 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W7
AN37/P40.7
I
I
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
AN38/P40.8
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
V10
W6
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
AN40
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
U10
U9
T10
T9
I
I
I
I
I
I
I
D / HighZ Analog Input 40
/ VDDM
EVADC_G8CH8
EVADC_G4CH0
AN41
Analog input channel 8, group 8
Analog input channel 0, group 4
D / HighZ Analog Input 41
/ VDDM
EVADC_G8CH9
EVADC_G4CH1
AN42
Analog input channel 9, group 8
Analog input channel 1, group 4
D / HighZ Analog Input 42
/ VDDM
EVADC_G8CH10
EVADC_G4CH2
AN43
Analog input channel 10, group 8
Analog input channel 2, group 4
D / HighZ Analog Input 43
/ VDDM
EVADC_G8CH11
EVADC_G4CH3
AN44
Analog input channel 11, group 8
Analog input channel 3, group 4
D / HighZ Analog Input 44
V6
/ VDDM
EVADC_G8CH12
EDSADC_EDS1PC
AN45
Analog input channel 12, group 8
Positive analog input channel 1, pin C
V7
D / HighZ Analog Input 45
/ VDDM
EVADC_G8CH13
EDSADC_EDS1NC
AN46
Analog input channel 13, group 8
Negative analog input channel 1, pin C
D / HighZ Analog Input 46
U6
/ VDDM
EVADC_G8CH14
EDSADC_EDS1PD
Analog input channel 14, group 8
Positive analog input channel 1, pin D
Data Sheet
153
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-22 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U7
AN47
I
D / HighZ Analog Input 47
/ VDDM
EVADC_G8CH15
EDSADC_EDS1ND
AN48
Analog input channel 15, group 8
Negative analog input channel 1, pin D
D / HighZ Analog Input 48
/ VDDM
AK7
AJ7
AJ6
I
I
I
EVADC_G5CH0
AN49
Analog input channel 0, group 5
D / HighZ Analog Input 49
/ VDDM
EVADC_G5CH1
AN50
Analog input channel 1, group 5
D / HighZ Analog Input 50
/ VDDM
EVADC_G5CH2
EDSADC_EDS9PA
AN51
Analog input channel 2, group 5
Positive analog input channel 9, pin A
D / HighZ Analog Input 51
AK6
AJ5
AK5
AJ4
I
I
I
I
/ VDDM
EVADC_G5CH3
EDSADC_EDS9NA
AN52
Analog input channel 3, group 5
Negative analog input channel 9, pin A
D / HighZ Analog Input 52
/ VDDM
EVADC_G5CH4
EDSADC_EDS6PA
AN53
Analog input channel 4, group 5
Positive analog input channel 6, pin A
D / HighZ Analog Input 53
/ VDDM
EVADC_G5CH5
EDSADC_EDS6NA
AN54/P41.4
Analog input channel 5, group 5
Negative analog input channel 6, pin A
S / HighZ Analog Input 54
/ VDDM
SENT_SENT20A
EVADC_G5CH6
EDSADC_EDS6PB
AN55/P41.5
Receive input channel 20
Analog input channel 6, group 5
Positive analog input channel 6, pin B
AK4
I
S / HighZ Analog Input 55
/ VDDM
SENT_SENT21A
EVADC_G5CH7
EDSADC_EDS6NB
AN56
Receive input channel 21
Analog input channel 7, group 5
Negative analog input channel 6, pin B
AF1
AF2
AE2
AE1
AD1
I
I
I
I
I
D / HighZ Analog Input 56
/ VDDM
EVADC_G6CH0
AN57
Analog input channel 0, group 6
D / HighZ Analog Input 57
/ VDDM
EVADC_G6CH1
AN58
Analog input channel 1, group 6
D / HighZ Analog Input 58
/ VDDM
EVADC_G6CH2
AN59
Analog input channel 2, group 6
D / HighZ Analog Input 59
/ VDDM
EVADC_G6CH3
AN60
Analog input channel 3, group 6
D / HighZ Analog Input 60
/ VDDM
EVADC_G6CH4
EDSADC_EDS7PA
Analog input channel 4, group 6
Positive analog input channel 7, pin A
Data Sheet
154
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TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-22 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
AD2
AN61
I
I
D / HighZ Analog Input 61
/ VDDM
EVADC_G6CH5
EDSADC_EDS7NA
AN62/P41.6
Analog input channel 5, group 6
Negative analog input channel 7, pin A
S / HighZ Analog Input 62
AC2
AC1
AB2
/ VDDM
SENT_SENT22A
EVADC_G6CH6
EDSADC_EDS7PB
AN63/P41.7
Receive input channel 22
Analog input channel 6, group 6
Positive analog input channel 7, pin B
I
I
S / HighZ Analog Input 63
/ VDDM
SENT_SENT23A
EVADC_G6CH7
EDSADC_EDS7NB
AN64/P41.8
Receive input channel 23
Analog input channel 7, group 6
Negative analog input channel 7, pin B
S / HighZ Analog Input 64
/ VDDM
SENT_SENT24A
EVADC_G7CH0
AN65
Receive input channel 24
Analog input channel 0, group 7
AB1
AA2
AA1
I
I
I
D / HighZ Analog Input 65
/ VDDM
EVADC_G7CH1
AN66
Analog input channel 1, group 7
D / HighZ Analog Input 66
/ VDDM
EVADC_G7CH2
AN67/P40.15
Analog input channel 2, group 7
S / HighZ Analog Input 67
/ VDDM
SENT_SENT15A
EVADC_G7CH3
AN68/P41.0
Receive input channel 15
Analog input channel 3, group 7
S / HighZ Analog Input 68
Y1
I
I
I
I
/ VDDM
SENT_SENT16A
EVADC_G7CH4
EDSADC_EDS8PA
AN69/P41.1
Receive input channel 16
Analog input channel 4, group 7
Positive analog input channel 8, pin A
Y2
S / HighZ Analog Input 69
/ VDDM
SENT_SENT17A
EVADC_G7CH5
EDSADC_EDS8NA
AN70/P41.2
Receive input channel 17
Analog input channel 5, group 7
Negative analog input channel 8, pin A
W1
W2
S / HighZ Analog Input 70
/ VDDM
SENT_SENT18A
EVADC_G7CH6
EDSADC_EDS9PB
AN71/P41.3
Receive input channel 18
Analog input channel 6, group 7
Positive analog input channel 9, pin B
S / HighZ Analog Input 71
/ VDDM
SENT_SENT19A
EVADC_G7CH7
EDSADC_EDS9NB
Receive input channel 19
Analog input channel 7, group 7
Negative analog input channel 9, pin B
Data Sheet
155
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TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
1. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
2. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-23 System I/O
Ball
Symbol
Ctrl. Buffer
Type
Function
M21
ESR1
I/O
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
ESR0
I
ESR1 pin input
L21
I/O
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
AD22 VGATE1P
O
—
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
AE22 VGATE1N
O
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
U25
U24
T24
XTAL1
XTAL2
TRST
I
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
O
I
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
P21
TCK
I
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
DAP: DAP0 Clock Input
DAP0
Data Sheet
156
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TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-23 System I/O (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R21
TMS
I
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
DAP: DAP1 Data I/O
DAP1
I/O
M22
PORST
I/O
PORST / PORST pin
PD /
Power On Reset Input. Additional strong PD in case of
VEXT
power fail.
Table 2-24 Supply
Ball
Symbol
Ctrl. Buffer
Type
Function
N19, V19,
M18, W18,
W13, V12,
J21, K20,
N12, M13
VDD
I
—
Digital Core Power Supply (1.25V)
AJ30, AH29, VEXT
AD25,AC24,
G8, F7, B3,
A2, J29, J30,
AH30,AK29,
AK20, AJ11,
AK11
I
—
External Power Supply (5V / 3.3V)
J10
VFLEX
I
I
—
—
Digital Power Supply for Flex Port Pads (5V / 3.3V)
ADC Analog Power Supply (5V / 3.3V)
AE10, AJ9, VDDM
AK9
A29, B28,
F24, G23
VDDP3
I
I
—
—
Flash Power Supply (3.3V)
Digital Ground
AK30, AJ29, VSS
AE25, AD24,
AB22, AA21,
K10, J9, G7,
B2, A30,
B30, B29,
F25, G24,
J22, K21,
H30, H29,
AJ10, AK10
AE9, AJ8,
AK8
VSSM
I
—
Analog Ground for VDDM
Data Sheet
157
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TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-24 Supply (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P19, U19,
P18, R18,
T18, U18,
M15, M16,
M17, N17,
R17, T17,
V17, W17,
N16, P16,
R16, T16,
U16, V16,
N15, P15,
R15, T15,
U15, V15,
M14, N14,
R14, T14,
V14, W14,
P13, R13,
T13, U13,
P12, U12,
T19, W15,
W16, R12,
T12
VSS
I
—
Digital Ground
T25
VSS
I
I
I
I
I
—
—
—
—
—
Oscillator Ground, VSS(OSC)
AE11
AE12
AA6
VAREF1
VAGND1
VAREF2
VAGND2
Positive Analog Reference Voltage 1
Negative Analog Reference Voltage 1
Positive Analog Reference Voltage 2
Negative Analog Reference Voltage 2
AA7
Data Sheet
158
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA516 Package Variant Pin Configuration
Table 2-24 Supply (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C30, D30,
E30, F30,
G30, W30,
C29, D29,
E29, F29,
G29, A28,
A27, B27,
A26, B26,
A25, A21,
AJ20, B21,
B20, A17,
B17, A10,
B10, A9, B9,
A8, A4, B4,
A3, AJ3,
NC
I
—
Not connected. These pins are reserved for future
extensions and shall not be connected externally
AK3, C2, D2,
E2, H2, R2,
AH2, AJ2,
AK2, B1, C1,
D1, E1, H1,
J1, R1, T1,
AH1, AJ1,
B6, B14,
B25, V1, V2,
R19
AB9, F6,
AE6, A1,
AK1, V30,
V29
NC1
I
I
—
—
Not connected. These pins are not connected on
package level and will not be used for future
extensions
AA16
VEVRSB
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
V24
V25
VDD
I
I
—
—
Digital Power Supply for Oscillator (1.25V), VDD(OSC)
VEXT
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT), VEXT(OSC)
AG1
AG2
VAREF3
VAGND3
I
I
—
—
Positive Analog Reference Voltage 3
Negative Analog Reference Voltage 3
Data Sheet
159
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
2.2
BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G1
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Trap input capture
GTM_TIM5_IN4_10
GTM_TIM3_IN0_1
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
External timer start 12
Injection signal from port
MDIO Input
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Shift clock output
Transmit output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
O
MDIO Output
Data Sheet
160
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G2
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
T12 capture input 60
GTM_TIM5_IN5_11
GTM_TIM3_IN1_1
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
EDSADC_DSCIN5A
CAN10_RXDA
PSI5_RX0A
Receive input
Modulator clock input, channel 5
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
CCU61_CC60INA
SENT_SENT0B
EDSADC_DSCIN7B
EVADC_G9CH11
EDSADC_EDS5NA
P00.1
Receive input channel 0
Modulator clock input, channel 7
Analog input channel 11, group 9
Negative analog input channel 5, pin A
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT5
EDSADC_DSCOUT7
SENT_SPC0
Modulator clock output
Modulator clock output
Transmit output
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
161
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H1
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM5_IN6_11
GTM_TIM3_IN1_2
GTM_TIM2_IN1_2
EDSADC_DSDIN7B
EDSADC_DSDIN5A
SENT_SENT1B
EVADC_G9CH10
EDSADC_EDS5PA
P00.2
Mux input channel 6 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Digital datastream input, channel 7
Digital datastream input, channel 5
Receive input channel 1
Analog input channel 10, group 9
Positive analog input channel 5, pin A
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
CAN21_TXD
Reference input 0
O2
O3
O4
Shift clock output
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
PSI5_TX0
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
IOM_MON2_8
IOM_REF2_8
Reference input 2
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
162
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H2
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
T12 capture input 61
GTM_TIM5_IN7_10
GTM_TIM3_IN2_1
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
EDSADC_ITR5F
PSI5_RX1A
Modulator clock input, channel 3
Trigger/Gate input, channel 5
RXD inputs (receive data) channel 1
CAN receive input node 3
CAN receive input node 1
RX data input
CAN03_RXDA
CAN21_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
ASCLIN12_ARXA
EVADC_G9CH9
EDSADC_EDS5NB
P00.3
Receive input channel 2
T12 capture input 61
Receive input
AI
Analog input channel 9, group 9
Negative analog input channel 5, pin B
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
ASCLIN12_ATX
EDSADC_DSCOUT3
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Transmit output
Modulator clock output
Reserved
SENT_SPC2
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
163
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J1
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM6_IN4_1
GTM_TIM3_IN3_1
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 4 of TIM module 6
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
GTM_DTMA5_0
GTM_DTMT3_0
EVADC_G9CH8
EDSADC_EDS5PB
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
CDTM5_DTM4
CDTM3_DTM0
AI
Analog input channel 8, group 9
Positive analog input channel 5, pin B
General-purpose output
GTM muxed output
Reference input 0
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
O2
O3
O4
TX data output
CAN11_TXD
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
PSI5_TX1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
164
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J2
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN4_1
GTM_TIM3_IN0_11
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
PSI5_RX2A
Mux input channel 4 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 2
T12 capture input 62
Modulator clock input, channel 2
RXD inputs (receive data) channel 2
T12 capture input 62
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
ASCLIN12_ARXB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Receive input channel 4
CAN receive input node 1
Receive input
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
165
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J4
P00.6
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 5 of TIM module 3
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 2
Trigger/Gate input, channel 4
Digital datastream input, channel 2
Receive input channel 5
Receive input
GTM_TIM3_IN5_1
GTM_TIM3_IN1_14
GTM_TIM2_IN5_1
EDSADC_ITR4F
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
GTM_DTMT3_1
EVADC_G9CH6
P00.6
CDTM3_DTM0
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
Positive carrier generator output
Reserved
PSI5_TX2
TXD outputs (send data)
Reference input 1
IOM_REF1_15
EVADC_EMUX10
SENT_SPC5
O5
O6
O7
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
166
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K1
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN6_1
GTM_TIM3_IN2_11
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
EDSADC_DSCIN4A
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
EDSADC_EDS4NA
P00.7
Mux input channel 6 of TIM module 3
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 2
T12 capture input 60
Receive input channel 6
Modulator clock input, channel 4
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
Negative analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
EVADC_FC2BFLOUT
EDSADC_DSCOUT4
EVADC_EMUX11
SENT_SPC6
Transmit output
Boundary flag output, FC channel 2
Modulator clock output
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC60
T12 PWM channel 60
IOM_MON1_8
Monitor input 1
IOM_REF1_13
Reference input 1
Data Sheet
167
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K4
P00.8
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN7_1
GTM_TIM3_IN3_11
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
EDSADC_DSDIN4A
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
EDSADC_EDS4PA
P00.8
Mux input channel 7 of TIM module 3
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 2
T12 capture input 61
Receive input channel 7
Digital datastream input, channel 4
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
Positive analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
168
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K2
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM4_IN0_7
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
ASCLIN13_ARXA
EVADC_G9CH3
EDSADC_EDS4NB
P00.9
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
Receive input
AI
Analog input channel 3, group 9
Negative analog input channel 4, pin B
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
169
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K5
P00.10
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input channel 9
Digital datastream input, channel 1
Analog input channel 2, group 9
Positive analog input channel 4, pin B
General-purpose output
GTM muxed output
GTM_TIM4_IN1_11
GTM_TIM1_IN1_1
GTM_TIM0_IN1_1
SENT_SENT9B
EDSADC_DSDIN1A
EVADC_G9CH2
EDSADC_EDS4PB
P00.10
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT19
ASCLIN4_ASCLK
ASCLIN13_ATX
—
Shift clock output
Transmit output
Reserved
—
Reserved
SENT_SPC9
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P00.11
Transmit output
T13 PWM channel 63
Monitor input 1
Reference input 1
L1
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trap input capture
GTM_TIM4_IN2_11
GTM_TIM1_IN2_1
GTM_TIM0_IN2_1
CCU60_CTRAPA
EDSADC_DSCIN0A
CCU61_T12HRE
SENT_SENT10B
ASCLIN13_ARXB
EVADC_G9CH1
EVADC_FC3CH0
P00.11
Modulator clock input, channel 0
External timer start 12
Receive input channel 10
Receive input
AI
Analog input channel 1, group 9
Analog input FC channel 3
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT20
ASCLIN4_ASLSO
ASCLIN13_ATX
EDSADC_DSCOUT0
—
Slave select signal output
Transmit output
Modulator clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
170
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-25 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L2
P00.12
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
GTM_TIM4_IN3_11
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
SENT_SENT11B
EVADC_G9CH0
EVADC_FC2CH0
P00.12
Digital datastream input, channel 0
Receive input
Receive input channel 11
Analog input channel 0, group 9
Analog input FC channel 2
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
171
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-26 Port 01 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G5
P01.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 0 of TIM module 2
Mux input channel 5 of TIM module 0
Slave select input
GTM_TIM4_IN5_2
GTM_TIM2_IN0_14
GTM_TIM0_IN5_8
QSPI3_SLSIB
EDSADC_ITR7F
EVADC_G9CH14
P01.3
Trigger/Gate input, channel 7
Analog input channel 14, group 9
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
GTM_TOUT111
—
Reserved
—
Reserved
QSPI3_SLSO9
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
—
Master slave select output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
G4
P01.4
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 1 of TIM module 2
Mux input channel 6 of TIM module 0
CAN receive input node 1
Trigger/Gate input, channel 7
Analog input channel 13, group 9
General-purpose output
GTM muxed output
GTM_TIM4_IN6_2
GTM_TIM2_IN1_14
GTM_TIM0_IN6_8
CAN01_RXDC
EDSADC_ITR7E
EVADC_G9CH13
P01.4
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT112
—
Reserved
ASCLIN9_ASLSO
QSPI3_SLSO10
—
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
172
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-26 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H5
P01.5
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 2
Mux input channel 2 of TIM module 2
Master SPI data input
Modulator clock input, channel 8
Receive input
GTM_TIM5_IN3_2
GTM_TIM2_IN3_7
GTM_TIM2_IN2_7
QSPI3_MRSTC
EDSADC_DSCIN8A
ASCLIN9_ARXA
EVADC_G9CH12
P01.5
AI
Analog input channel 12, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
GTM_TOUT113
—
Reserved
—
Reserved
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
I
Reserved
EDSADC_DSCOUT8
—
Modulator clock output
Reserved
H4
P01.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 5 of TIM module 5
Mux input channel 5 of TIM module 2
Slave SPI data input
GTM_TIM5_IN6_2
GTM_TIM5_IN5_3
GTM_TIM2_IN5_7
QSPI3_MTSRC
EDSADC_DSDIN8A
P01.6
Digital datastream input, channel 8
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT114
ASCLIN12_ATX
ASCLIN9_ASCLK
QSPI3_MTSR
—
Transmit output
Shift clock output
Master SPI data output
Reserved
—
Reserved
—
Reserved
Data Sheet
173
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-26 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J5
P01.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
Trigger/Gate input, channel 8
Receive input
GTM_TIM5_IN7_2
GTM_TIM2_IN7_7
QSPI3_SCLKC
EDSADC_ITR8F
ASCLIN9_ARXB
P01.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT115
—
ASCLIN9_ATX
QSPI3_SCLK
—
Transmit output
Master SPI clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
174
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
175
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C2
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT1
IOM_REF0_1
QSPI4_SLSO7
QSPI3_SLSO2
EDSADC_CGPWMP
—
O2
O3
O4
O5
O6
O7
Master slave select output
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
176
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C1
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
Receive input channel 14
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
SENT_SENT14B
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
177
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D2
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Modulator clock input, channel 5
Receive Channel B2
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
EDSADC_DSCIN5B
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
MSC1_SDI1
CAN receive input node 2
Receive input
Upstream assynchronous input signal
RXD inputs (receive data) channel 0
Receive input channel 13
General-purpose output
GTM muxed output
PSI5_RX0B
SENT_SENT13B
P02.3
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
EDSADC_DSCOUT5
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Modulator clock output
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
178
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D1
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
EDSADC_DSDIN5B
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Digital datastream input, channel 5
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
SENT_SENT12B
P02.4
CAN receive input node 1
External CAN time trigger input
Receive input channel 12
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
179
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E2
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Modulator clock input, channel 4
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
EDSADC_DSCIN4B
I2C0_SCLA
PSI5_RX1B
RXD inputs (receive data) channel 1
RX data input
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
EDSADC_DSCOUT4
I2C0_SCL
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Modulator clock output
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
180
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E1
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM3_IN0_10
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
EDSADC_DSDIN4B
EDSADC_ITR5E
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Digital datastream input, channel 4
Trigger/Gate input, channel 5
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
181
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F2
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN1_10
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
EDSADC_ITR4E
GPT120_T3EUDA
PSI5_RX2B
Mux input channel 1 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
Receive input channel 1
Modulator clock input, channel 3
Trigger/Gate input, channel 4
Count direction control input of core timer T3
RXD inputs (receive data) channel 2
Hall capture input 1
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
—
Reference input 0
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
182
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F1
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM3_IN2_10
GTM_TIM3_IN0_2
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
Reference input 0
QSPI3_SLSO5
ASCLIN8_ASCLK
PSI5_TX2
O2
O3
O4
Master slave select output
Shift clock output
TXD outputs (send data)
Reference input 1
IOM_REF1_15
EVADC_EMUX02
GETH_MDC
O5
O6
O7
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
183
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E4
P02.9
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 3 of TIM module 3
Mux input channel 2 of TIM module 0
Receive input channel 20
Receive input
GTM_TIM4_IN2_2
GTM_TIM3_IN3_10
GTM_TIM0_IN2_10
SENT_SENT20B
ASCLIN8_ARXA
P02.9
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT116
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
ASCLIN8_ATX
—
Monitor input 2
Reference input 2
O3
O4
O5
Transmit output
Reserved
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
—
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
F5
P02.10
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM4_IN3_2
GTM_TIM3_IN4_11
GTM_TIM0_IN3_10
ASCLIN2_ARXC
CAN01_RXDE
SENT_SENT21B
ASCLIN8_ARXB
P02.10
CAN receive input node 1
Receive input channel 21
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT117
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
184
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-27 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F4
P02.11
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 5 of TIM module 3
Mux input channel 7 of TIM module 0
Receive input channel 22
Analog input channel 15, group 9
General-purpose output
GTM muxed output
GTM_TIM4_IN4_3
GTM_TIM3_IN5_12
GTM_TIM0_IN7_7
SENT_SENT22B
EVADC_G9CH15
AI
P02.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT118
—
Reserved
ASCLIN8_ASLSO
Slave select signal output
Reserved
—
—
—
—
Reserved
Reserved
Reserved
Table 2-28 Port 10 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
A7
P10.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of core timer T6
Receive input
GTM_TIM4_IN0_12
GTM_TIM1_IN4_2
GTM_TIM0_IN4_2
GPT120_T6EUDB
ASCLIN11_ARXA
GETH_RXERC
GTM_DTMA5_2
P10.0
Receive Error MII
CDTM5_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT102
ASCLIN11_ATX
QSPI1_SLSO10
—
Transmit output
Master slave select output
Reserved
—
Reserved
ASCLIN22_ATX
—
Transmit output
Reserved
Data Sheet
185
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-28 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B7
P10.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN4_12
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
Mux input channel 4 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Chip Select
EVADC_FC1BFLOUT
—
Boundary flag output, FC channel 1
Reserved
—
Reserved
A5
P10.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN5_12
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 5 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMT2_2
P10.2
CDTM2_DTM0
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI1_SCLK
MSC0_EN0
EVADC_FC3BFLOUT
—
Master SPI clock output
Chip Select
Boundary flag output, FC channel 3
Reserved
—
Reserved
Data Sheet
186
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-28 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A6
P10.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN6_10
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
Mux input channel 6 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
B6
P10.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
Trigger/gate input of core timer T3
Receive input
GTM_TIM4_IN7_3
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
ASCLIN22_ARXA
P10.4
Receive input
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT106
IOM_MON2_11
ASCLIN22_ATX
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
—
O2
O3
O4
O5
O6
O7
Transmit output
Master slave select output
Master SPI data output
Chip Select
Reserved
—
Reserved
Data Sheet
187
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-28 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B5
P10.5
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM4_IN3_13
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
CAN20_RXDA
MSC0_INJ1
CAN receive input node 0
Injection signal from port
Receive input
ASCLIN22_ARXB
P10.5
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
Reference input 2
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
PSI5_TX3
O6
O7
Slave select signal output
TXD outputs (send data)
Data Sheet
188
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-28 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A4
P10.6
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
RXD inputs (receive data) channel 3
Receive input
GTM_TIM4_IN2_13
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
PSI5_RX3C
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
ASCLIN23_ARXA
P10.6
Slave SPI data input
HWCFG5 pin input
Receive input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
CAN20_TXD
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
O5
O6
CAN transmit output node 0
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O7
Data Sheet
189
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-28 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A3
P10.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_3
GTM_TIM0_IN0_3
GPT120_T3EUDB
ASCLIN2_ACTSA
QSPI3_MRSTB
SCU_E_REQ0_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Count direction control input of core timer T3
Clear to send input
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS1C
ASCLIN23_ARXB
P10.7
Hall capture input 1
Receive input
O0
O1
General-purpose output
GTM muxed output
Reference input 2
Transmit output
GTM_TOUT109
IOM_REF2_11
ASCLIN23_ATX
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
O2
O3
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN20_TXD
CAN12_TXD
—
CAN transmit output node 0
CAN transmit output node 2
Reserved
Data Sheet
190
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-28 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B4
P10.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN0_13
GTM_TIM1_IN5_2
GTM_TIM0_IN5_2
CAN12_RXDB
GPT120_T4INB
QSPI3_SCLKB
SCU_E_REQ1_2
Mux input channel 0 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 2
Trigger/gate input of timer T4
Slave SPI clock inputs
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS2C
CAN20_RXDB
P10.8
Hall capture input 2
CAN receive input node 0
General-purpose output
GTM muxed output
Ready to send output
Master SPI clock output
Transmit output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT110
ASCLIN2_ARTS
QSPI3_SCLK
ASCLIN23_ATX
—
Reserved
—
Reserved
—
Reserved
Table 2-29 Port 11 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
E10
P11.0
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN0_4
GTM_TIM2_IN0_7
ASCLIN3_ARXB
GTM_DTMA2_1
P11.0
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 2
Receive input
CDTM2_DTM4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT119
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
CAN11_TXD
GETH_TXD3
—
CAN transmit output node 1
Transmit Data
Reserved
Data Sheet
191
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E9
P11.1
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN1_5
GTM_TIM2_IN1_6
P11.1
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Shift clock output
Transmit output
O0
O1
O2
O3
GTM_TOUT120
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
I
CAN12_TXD
GETH_TXD2
—
CAN transmit output node 2
Transmit Data
Reserved
A10
P11.2
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN1_3
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
192
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B10
P11.3
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN2_2
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Transmit Channel A
Reserved
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
P11.4
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
D10
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN2_5
GTM_TIM2_IN2_6
GETH_RXCLKB
P11.4
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 2
Receive Clock MII
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT121
ASCLIN3_ASCLK
—
Shift clock output
Reserved
—
Reserved
CAN13_TXD
GETH_TXER
GETH_TXCLK
CAN transmit output node 3
Transmit Error MII
Transmit Clock Output for RGMII
Data Sheet
193
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D8
P11.5
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM4_IN3_5
GTM_TIM2_IN3_8
GETH_TXCLKA
GETH_GREFCLK
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 2
Transmit Clock Input for MII
Gigabit Reference Clock input for RGMII (125 MHz high
precission)
P11.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT122
—
—
Reserved
—
Reserved
CAN20_TXD
—
CAN transmit output node 0
Reserved
—
Reserved
D9
P11.6
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN3_2
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM muxed output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
Monitor input 1
Reference input 1
Data Sheet
194
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E8
P11.7
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM4_IN4_5
GTM_TIM2_IN4_7
GETH_RXD3A
Mux input channel 4 of TIM module 4
Mux input channel 4 of TIM module 2
Receive Data 3 MII and RGMII (RGMII can use RXD3A
only)
CAN11_RXDD
CAN receive input node 1
General-purpose output
GTM muxed output
Reserved
P11.7
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT123
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
E7
P11.8
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 5 of TIM module 2
GTM_TIM4_IN5_5
GTM_TIM2_IN5_8
GETH_RXD2A
Receive Data 2 MII and RGMII (RGMII can use RXD2A
only)
CAN12_RXDD
CAN receive input node 2
General-purpose output
GTM muxed output
Reserved
P11.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT124
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
195
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A9
P11.9
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN4_2
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT98
—
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
196
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B9
P11.10
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN5_2
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
197
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A8
P11.11
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN6_2
GTM_TIM3_IN0_14
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
Reserved
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
Master slave select output
Master slave select output
Chip Select
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P11.12
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
B8
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN7_2
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
198
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E6
P11.13
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 6 of TIM module 2
Receive Error MII
GTM_TIM4_IN6_5
GTM_TIM2_IN6_7
GETH_RXERA
I2C1_SDAA
CAN13_RXDD
P11.13
Serial Data Input 0
CAN receive input node 3
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT125
—
—
Reserved
—
Reserved
—
Reserved
I2C1_SDA
—
Serial Data Output
Reserved
D7
P11.14
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
GTM_TIM4_IN7_4
GTM_TIM2_IN7_8
GETH_CRSDVB
GETH_RXDVB
GETH_CRSA
I2C1_SCLA
CAN20_RXDF
P11.14
Serial Clock Input 0
CAN receive input node 0
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT126
—
—
Reserved
—
Reserved
—
Reserved
I2C1_SCL
—
Serial Clock Output
Reserved
Data Sheet
199
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-29 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D6
P11.15
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 0
Collision MII
GTM_TIM4_IN7_5
GTM_TIM0_IN7_8
GETH_COLA
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT127
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-30 Port 12 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
E12
P12.0
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 3
CAN receive input node 0
Receive Clock MII
CDTM4_DTM4
GTM_TIM4_IN0_5
GTM_TIM3_IN0_7
CAN00_RXDC
GETH_RXCLKC
GTM_DTMA4_0
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT128
—
—
Reserved
—
Reserved
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
Data Sheet
200
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-30 Port 12 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E11
P12.1
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 3
MDIO Input
GTM_TIM4_IN1_6
GTM_TIM3_IN1_6
GETH_MDIOC
P12.1
O0
O1
O2
O3
O4
O5
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT129
ASCLIN3_ASLSO
—
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
O
—
Reserved
GETH_MDIO
MDIO Output
Table 2-31 Port 13 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B12
P13.0
I
LVDS_TX General-purpose input
/ FAST /
PU1 /
VEXT /
ES6
GTM_TIM3_IN5_3
GTM_TIM2_IN5_3
ASCLIN10_ARXC
ASCLIN21_ARXA
P13.0
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Receive input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
MSC0_FCLN
—
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
CAN transmit output node 0
Data Sheet
201
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-31 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A12
P13.1
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN6_3
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 6 of TIM module 2
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
Shift-clock direct part of the differential signal
Serial Clock Output
—
Reserved
B11
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN7_3
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 7 of TIM module 2
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
Serial Data Input 1
P13.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
ASCLIN21_ATX
Transmit output
Data Sheet
202
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-31 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A11
P13.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN0_3
GTM_TIM2_IN0_3
ASCLIN21_ARXB
P13.3
Mux input channel 0 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 2
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT94
ASCLIN10_ASLSO
QSPI2_MTSRP
—
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
MSC0_SOP
ASCLIN21_ATX
—
Data output - direct part of the differential signal
Transmit output
Reserved
Table 2-32 Port 14 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B16
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input channel 17
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
SENT_SENT17D
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
203
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-32 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A15
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
SENT_SENT18D
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive input channel 18
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
E13
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
204
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-32 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B14
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
B15
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
205
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-32 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A14
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
CDTM2_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT85
—
Reserved
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
ERAY1_TXDB
P14.6
Transmit Channel B
Transmit Channel B
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
B13
FAST /
PU1 /
VEXT /
ES
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
Reserved
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
ERAY1_TXENB
Transmit Enable Channel B
Transmit Enable Channel B
Data Sheet
206
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-32 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D13
P14.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive Channel B0
Receive Channel B0
CAN receive input node 0
CAN receive input node 3
Receive input
GTM_TIM4_IN7_10
GTM_TIM1_IN0_5
GTM_TIM0_IN0_5
ERAY0_RXDB0
ERAY1_RXDB0
CAN10_RXDB
CAN13_RXDA
ASCLIN9_ARXC
ASCLIN20_ARXA
P14.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT87
ASCLIN0_ARTS
QSPI2_SLSO4
ASCLIN9_ATX
—
Ready to send output
Master slave select output
Transmit output
Reserved
—
Reserved
ASCLIN20_ATX
P14.8
Transmit output
A13
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Receive Channel A0
CAN receive input node 2
Receive input
GTM_TIM3_IN2_3
GTM_TIM2_IN2_3
ERAY0_RXDA0
CAN02_RXDD
ASCLIN1_ARXD
ERAY1_RXDA0
P14.8
Receive Channel A0
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT88
ASCLIN5_ASLSO
ASCLIN7_ASLSO
—
Slave select signal output
Slave select signal output
Reserved
—
Reserved
—
Reserved
ASCLIN20_ATX
Transmit output
Data Sheet
207
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-32 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D12
P14.9
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN3_3
GTM_TIM2_IN3_3
ASCLIN0_ACTSA
QSPI2_MRSTFN
ASCLIN9_ARXD
ASCLIN20_ARXB
P14.9
Mux input channel 3 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 3 of TIM module 2
Clear to send input
Master SPI data input (LVDS N line)
Receive input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT89
CAN23_TXD
MSC0_EN1
CAN transmit output node 3
Chip Select
CAN10_TXD
ERAY0_TXENB
ERAY0_TXENA
ERAY1_TXENA
P14.10
CAN transmit output node 0
Transmit Enable Channel B
Transmit Enable Channel A
Transmit Enable Channel A
D11
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN4_3
GTM_TIM2_IN4_3
CAN23_RXDA
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 4 of TIM module 2
CAN receive input node 3
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT90
—
MSC0_EN0
Chip Select
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
ERAY1_TXDA
Transmit output
Monitor input 2
Reference input 2
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel A
Transmit Channel A
Data Sheet
208
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-33 Port 15 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B20
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
GTM_TIM3_IN3_4
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
A18
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM3_IN4_4
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
209
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-33 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C19
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Slave select input
GTM_TIM3_IN5_4
GTM_TIM2_IN5_4
QSPI2_SLSIA
SENT_SENT10D
QSPI2_MRSTE
P15.2
Receive input channel 10
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
B17
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM3_IN6_4
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI clock output
Reserved
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
210
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-33 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A17
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN7_4
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT11D
P15.4
Receive input channel 11
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
ASCLIN19_ATX
—
Monitor input 2
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Transmit output
O4
O5
O6
O7
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
211
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-33 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E14
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM3_IN0_4
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
A16
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
Receive input
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
ASCLIN19_ARXA
P15.6
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
212
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-33 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D15
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
ASCLIN19_ARXB
P15.7
Master SPI data input
Receive input
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
ASCLIN19_ATX
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Transmit output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
D14
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
213
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-34 Port 20 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
H20
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CAN21_RXDC
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
CAN receive input node 1
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
Shift clock output
Reserved
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
Trigger output
G19
P20.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Trigger input
GTM_TIM4_IN4_11
GTM_TIM3_IN3_5
GTM_TIM2_IN3_5
CBS_TGI1
GTM_DTMA1_1
CDTM1_DTM4
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT60
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CBS_TGO1
Trigger output
Data Sheet
214
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-34 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H19
P20.2
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
P20.3
Testmode Enable Input
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
G20
I
SLOW /
PU1 /
VEXT /
ES
GTM_TIM4_IN5_11
GTM_TIM3_IN4_5
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CAN21_TXD
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
CAN transmit output node 1
Reserved
F17
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM6_IN0_1
GTM_TIM3_IN6_5
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
Ready to send output
Master slave select output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
215
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-34 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F19
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
Mux input channel 1 of TIM module 6
CAN receive input node 0
Clear to send input
GTM_TIM3_IN7_5
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
GTM_TIM6_IN1_1
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
F20
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM6_IN2_1
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
216
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-34 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E17
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM6_IN3_1
GTM_TIM3_IN5_5
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Mux input channel 3 of TIM module 6
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
E19
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM3_IN6_6
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
217
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-34 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E20
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN7_6
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
D19
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN0_5
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Master SPI data output
Reserved
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
218
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-34 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D20
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM3_IN1_4
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
C20
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN2_4
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
219
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-35 Port 21 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
K17
P21.0
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN0_11
GTM_TIM3_IN4_6
GTM_TIM2_IN4_6
QSPI4_MRSTDN
DMU_FDEST
ASCLIN11_ARXC
ASCLIN17_ARXB
P21.0
Mux input channel 0 of TIM module 4
PU1 /
VEXT /
ES
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Master SPI data input (LVDS N line)
Enter destructive debug mode
Receive input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT51
ASCLIN11_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM1
P21.1
Pin Output Value
J17
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN1_13
GTM_TIM3_IN5_6
GTM_TIM2_IN5_6
QSPI4_MRSTDP
ASCLIN11_ARXD
ASCLIN18_ARXA
GTM_DTMA4_1
P21.1
Mux input channel 1 of TIM module 4
PU1 /
VEXT /
ES
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Master SPI data input (LVDS P line)
Receive input
Receive input
CDTM4_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT52
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM2
Pin Output Value
Data Sheet
220
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-35 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K19
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN4_11
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 4 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
QSPI4_MRSTCN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Master SPI data input (LVDS N line)
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
J19
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN5_12
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
QSPI4_MRSTCP
P21.3
Mux input channel 5 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Shift clock output
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT54
ASCLIN11_ASCLK
ASCLIN18_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
221
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-35 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K20
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN6_12
GTM_TIM1_IN2_6
GTM_TIM0_IN2_6
ASCLIN18_ARXB
P21.4
Mux input channel 6 of TIM module 5
PU1 /
VEXT /
ES6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Slave select signal output
Transmit output
GTM_TOUT55
ASCLIN11_ASLSO
ASCLIN18_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
J20
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN7_11
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 7 of TIM module 5
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
222
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-35 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H17
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ.
Mux input channel 2 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM4_IN2_12
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
223
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-35 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H16
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GTM_TIM4_IN3_12
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Table 2-36 Port 22 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
P20
P22.0
I
LVDS_TX General-purpose input
/ FAST /
PU1 /
VEXT /
ES6
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
QSPI4_MTSRB
ASCLIN6_ARXE
P22.0
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Slave SPI data input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT47
ASCLIN3_ATXN
QSPI4_MTSR
QSPI4_SCLKN
MSC1_FCLN
—
GTM muxed output
Differential Transmit output (low active)
Master SPI data output
Master SPI clock output (LVDS N line)
Shift-clock inverted part of the differential signal
Reserved
ASCLIN6_ATX
Transmit output
Data Sheet
224
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-36 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P19
P22.1
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
QSPI4_MRSTB
ASCLIN7_ARXE
P22.1
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 0
Master SPI data input
Receive input
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT48
ASCLIN3_ATXP
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI4_SCLKP
MSC1_FCLP
—
Differential Transmit output (high active)
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Master SPI clock output (LVDS P line)
Shift-clock direct part of the differential signal
Reserved
ASCLIN7_ATX
P22.2
Transmit output
R20
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
QSPI4_SLSIB
P22.2
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Slave select input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT49
ASCLIN5_ATX
QSPI4_SLSO3
QSPI4_MTSRN
MSC1_SON
—
Transmit output
Master slave select output
Master SPI data output (LVDS N line)
Data output - inverted part of the differential signal
Reserved
—
Reserved
Data Sheet
225
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-36 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R19
P22.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
QSPI4_SCLKB
ASCLIN5_ARXC
P22.3
Mux input channel 4 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 4 of TIM module 0
Slave SPI clock inputs
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT50
—
QSPI4_SCLK
QSPI4_MTSRP
MSC1_SOP
—
Master SPI clock output
Master SPI data output (LVDS P line)
Data output - direct part of the differential signal
Reserved
—
Reserved
P16
P22.4
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Receive input
GTM_TIM3_IN0_8
ASCLIN7_ARXF
GTM_DTMA3_0
P22.4
CDTM3_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT130
ASCLIN4_ASLSO
—
QSPI0_SLSO12
—
Master slave select output
Reserved
CAN13_TXD
—
CAN transmit output node 3
Reserved
P17
P22.5
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 3
Slave SPI data input
CAN receive input node 3
General-purpose output
GTM muxed output
Transmit output
GTM_TIM3_IN1_7
QSPI0_MTSRC
CAN13_RXDC
P22.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT131
ASCLIN4_ATX
—
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
Data Sheet
226
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-36 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N16
P22.6
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 2
Master SPI data input
Receive input
GTM_TIM3_IN2_6
GTM_TIM2_IN6_14
QSPI0_MRSTC
ASCLIN4_ARXC
P22.6
O0
O1
O2
O3
O4
General-purpose output
GTM muxed output
Reserved
GTM_TOUT132
—
—
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
CAN21_TXD
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
I
CAN transmit output node 1
Reserved
—
Reserved
N17
P22.7
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 3
Slave SPI clock inputs
CAN receive input node 1
General-purpose output
GTM muxed output
Shift clock output
GTM_TIM3_IN3_7
QSPI0_SCLKC
CAN21_RXDF
P22.7
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT133
ASCLIN4_ASCLK
ASCLIN17_ATX
QSPI0_SCLK
—
Transmit output
Master SPI clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
227
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-36 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
M16
P22.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 5
Mux input channel 4 of TIM module 3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Shift clock output
GTM_TIM5_IN0_4
GTM_TIM3_IN4_7
QSPI0_SCLKB
P22.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT134
ASCLIN5_ASCLK
—
Reserved
QSPI0_SCLK
CAN22_TXD
—
Master SPI clock output
CAN transmit output node 2
Reserved
—
Reserved
M17
P22.9
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 5 of TIM module 3
Master SPI data input
Receive input
GTM_TIM5_IN1_10
GTM_TIM3_IN5_7
QSPI0_MRSTB
ASCLIN4_ARXD
CAN22_RXDE
GTM_DTMA3_1
P22.9
CAN receive input node 2
CDTM3_DTM4
O0
O1
O2
O3
O4
General-purpose output
GTM muxed output
Reserved
GTM_TOUT135
—
—
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
Reserved
—
Reserved
—
Reserved
Data Sheet
228
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-36 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L16
P22.10
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 5
Mux input channel 6 of TIM module 3
Slave SPI data input
General-purpose output
GTM muxed output
GTM_TIM5_IN2_8
GTM_TIM3_IN6_7
QSPI0_MTSRB
P22.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT136
ASCLIN4_ATX
—
Transmit output
Reserved
QSPI0_MTSR
CAN23_TXD
—
Master SPI data output
CAN transmit output node 3
Reserved
—
Reserved
L17
P22.11
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 7 of TIM module 3
CAN receive input node 3
Receive input
GTM_TIM5_IN3_10
GTM_TIM3_IN7_7
CAN23_RXDE
ASCLIN17_ARXA
P22.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT137
ASCLIN4_ASLSO
ASCLIN17_ATX
QSPI0_SLSO10
—
Slave select signal output
Transmit output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
229
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-37 Port 23 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
V20
P23.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 6
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 0
General-purpose output
GTM muxed output
GTM_TIM6_IN7_1
GTM_TIM1_IN5_4
GTM_TIM0_IN5_4
CAN10_RXDC
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT41
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
U19
P23.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 6
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Upstream assynchronous input signal
Receive input
GTM_TIM6_IN6_1
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
MSC1_SDI0
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT42
ASCLIN1_ARTS
QSPI4_SLSO6
GTM_CLK0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
Ready to send output
Master slave select output
CGM generated clock
CAN transmit output node 0
External Clock 0
Shift clock output
Data Sheet
230
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-37 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U20
P23.2
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 6
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM6_IN5_1
GTM_TIM1_IN6_5
GTM_TIM0_IN6_5
ASCLIN7_ARXC
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT43
—
Reserved
—
Reserved
CAN23_TXD
CAN12_TXD
—
CAN transmit output node 3
CAN transmit output node 2
Reserved
—
Reserved
T19
P23.3
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 6
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
Injection signal from port
Receive input
GTM_TIM6_IN4_2
GTM_TIM1_IN7_4
GTM_TIM0_IN7_4
MSC1_INJ0
ASCLIN6_ARXA
CAN12_RXDC
CAN23_RXDB
P23.3
CAN receive input node 2
CAN receive input node 3
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT44
ASCLIN7_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
231
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-37 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T20
P23.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 6
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM6_IN3_2
GTM_TIM1_IN7_5
GTM_TIM0_IN7_5
P23.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT45
ASCLIN6_ASLSO
QSPI4_SLSO5
—
Slave select signal output
Master slave select output
Reserved
MSC1_EN0
—
Chip Select
Reserved
—
Reserved
T17
P23.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Receive input
GTM_TIM6_IN2_2
GTM_TIM1_IN2_7
GTM_TIM0_IN2_7
ASCLIN16_ARXA
P23.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT46
ASCLIN6_ATX
QSPI4_SLSO4
—
Transmit output
Master slave select output
Reserved
MSC1_EN1
CAN22_TXD
—
Chip Select
CAN transmit output node 2
Reserved
R17
P23.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 6
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 1
CAN receive input node 2
General-purpose output
GTM muxed output
GTM_TIM6_IN1_2
GTM_TIM4_IN2_7
GTM_TIM1_IN2_10
CAN22_RXDC
P23.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT138
ASCLIN16_ATX
—
Transmit output
Reserved
QSPI0_SLSO11
CAN11_TXD
—
Master slave select output
CAN transmit output node 1
Reserved
—
Reserved
Data Sheet
232
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-37 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R16
P23.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 6
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 1
CAN receive input node 1
Receive input
GTM_TIM6_IN0_2
GTM_TIM4_IN3_7
GTM_TIM1_IN3_10
CAN11_RXDC
ASCLIN16_ARXB
P23.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT139
ASCLIN16_ATX
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-38 Port 32 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
Y17
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM3_IN2_5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN2_5
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT36
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
233
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-38 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W17
P32.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
GTM_TIM3_IN3_15
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
Reserved
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT37
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Y18
P32.2
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 3
Receive input
GTM_TIM1_IN3_8
GTM_TIM0_IN3_8
CAN03_RXDB
ASCLIN3_ARXD
CAN21_RXDD
P32.2
CAN receive input node 1
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT38
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
Data Sheet
234
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-38 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y19
P32.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN4_5
GTM_TIM0_IN4_5
P32.3
O0
O1
O2
GTM_TOUT39
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN3_ASCLK
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CAN21_TXD
—
Shift clock output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
CAN transmit output node 1
Reserved
W18
P32.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
GTM_TIM1_IN5_5
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
MSC1_SDI2
ASCLIN15_ARXA
P32.4
Upstream assynchronous input signal
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT40
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
GTM_CLK1
CGM generated clock
Chip Select
MSC1_EN0
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
235
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-38 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T15
P32.5
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 1 of TIM module 4
Mux input channel 5 of TIM module 3
Receive input channel 10
General-purpose output
GTM muxed output
Transmit output
GTM_TIM5_IN5_9
GTM_TIM4_IN1_14
GTM_TIM3_IN5_8
SENT_SENT10C
P32.5
O0
O1
O2
GTM_TOUT140
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
Reserved
—
Reserved
—
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
U15
P32.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 4 of TIM module 4
Mux input channel 6 of TIM module 3
CAN receive input node 2
Trigger input
GTM_TIM5_IN6_9
GTM_TIM4_IN4_15
GTM_TIM3_IN6_8
CAN02_RXDC
CBS_TGI4
ASCLIN2_ARXF
ASCLIN6_ARXC
SENT_SENT11C
P32.6
Receive input
Receive input
Receive input channel 11
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT141
—
—
Reserved
QSPI2_SLSO12
CAN22_TXD
—
Master slave select output
CAN transmit output node 2
Reserved
—
Reserved
CBS_TGO4
Trigger output
Data Sheet
236
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-38 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U16
P32.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 0 of TIM module 4
Mux input channel 7 of TIM module 3
Trigger input
GTM_TIM5_IN7_8
GTM_TIM4_IN0_15
GTM_TIM3_IN7_8
CBS_TGI5
CAN22_RXDB
SENT_SENT12C
ASCLIN15_ARXB
P32.7
CAN receive input node 2
Receive input channel 12
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT142
ASCLIN6_ATX
—
Reserved
ASCLIN15_ATX
—
Transmit output
Reserved
—
Reserved
—
Reserved
CBS_TGO5
Trigger output
Data Sheet
237
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
W10
P33.0
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 13
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM3_IN0_13
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
SENT_SENT13C
IOM_PIN_0
GTM_DTMT1_2
EVADC_G10CH7
P33.0
AI
Analog input channel 7, group 10
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
Reserved
ASCLIN15_ATX
—
Transmit output
Reserved
EVADC_FC2BFLOUT
—
Boundary flag output, FC channel 2
Reserved
Data Sheet
238
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y10
P33.1
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN1_15
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
Receive input
GPIO pad input to FPC
EVADC_G10CH6
P33.1
AI
Analog input channel 6, group 10
General-purpose output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
O2
O3
O4
O5
O6
O7
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
239
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W11
P33.2
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN2_14
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
Digital datastream input, channel 2
GPIO pad input to FPC
EVADC_G10CH5
P33.2
AI
Analog input channel 5, group 10
General-purpose output
O0
O1
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
EVADC_FC3BFLOUT
ASCLIN14_ATX
Monitor input 1
Reference input 1
O5
O6
O7
Control of external analog multiplexer interface 0
Boundary flag output, FC channel 3
Transmit output
Data Sheet
240
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y11
P33.3
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN3_12
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
SENT_SENT7C
EDSADC_DSCIN1B
ASCLIN14_ARXA
IOM_PIN_3
Modulator clock input, channel 1
Receive input
GPIO pad input to FPC
EVADC_G10CH4
P33.3
AI
Analog input channel 4, group 10
General-purpose output
O0
O1
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
ASCLIN5_ASCLK
QSPI4_SLSO2
EDSADC_DSCOUT1
EVADC_EMUX00
—
O2
O3
O4
O5
O6
O7
Master slave select output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
ASCLIN14_ATX
Transmit output
Data Sheet
241
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W12
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN4_10
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
ASCLIN14_ARXB
IOM_PIN_4
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
Receive input
GPIO pad input to FPC
GTM_DTMT2_0
EVADC_G10CH3
P33.4
CDTM2_DTM0
AI
Analog input channel 3, group 10
General-purpose output
O0
O1
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
242
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y12
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN5_10
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 5 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
PSI5_RX2C
Clear to send input
Hall capture input 2
RXD inputs (receive data) channel 2
Receive input channel 5
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
CAN receive input node 3
GPIO pad input to FPC
EVADC_G10CH2
P33.5
AI
Analog input channel 2, group 10
General-purpose output
O0
O1
GTM_TOUT27
IOM_MON0_5
GTM muxed output
Monitor input 0
IOM_GTM_5
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
EVADC_FC2BFLOUT
ASCLIN5_ASLSO
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 2
Slave select signal output
Data Sheet
243
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W13
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
GTM_DTMT2_1
EVADC_G10CH1
P33.6
CDTM2_DTM0
AI
Analog input channel 1, group 10
General-purpose output
O0
O1
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
TXD outputs (send data)
ASCLIN2_ASLSO
QSPI2_SLSO11
PSI5_TX2
O2
O3
O4
IOM_REF1_15
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Reference input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
244
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y13
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT14C
IOM_PIN_7
Receive input channel 14
GPIO pad input to FPC
Analog input channel 0, group 10
General-purpose output
GTM muxed output
EVADC_G10CH0
P33.7
AI
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
QSPI4_SLSO7
ASCLIN8_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Master slave select output
Transmit output
Reserved
EVADC_FC3BFLOUT
—
Boundary flag output, FC channel 3
Reserved
Data Sheet
245
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W14
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO2
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
O
FSP[1..0] Output Signals - Generated by SMU_core
Data Sheet
246
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y14
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO1
ASCLIN2_ASCLK
CAN01_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Shift clock output
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
247
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W15
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN4_14
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
QSPI4_SLSIA
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave select input
CAN receive input node 1
Receive input
GPIO pad input to FPC
P33.10
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
QSPI4_SLSO0
ASCLIN1_ASLSO
PSI5S_CLK
Monitor input 0
O2
O3
O4
O5
Master slave select output
Master slave select output
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GPIO pad input to FPC
General-purpose output
GTM muxed output
Y15
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
QSPI4_SCLKA
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
QSPI4_SCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Master SPI clock output
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
248
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W16
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Slave SPI data input
GTM_TIM3_IN0_6
GTM_TIM2_IN0_6
QSPI4_MTSRA
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MTSR
ASCLIN1_ASCLK
CAN22_TXD
Monitor input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Shift clock output
CAN transmit output node 2
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 1
Data Sheet
249
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y16
P33.13
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM3_IN1_5
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
QSPI4_MRSTA
MSC1_INJ1
Carrier sign signal input
Master SPI data input
Injection signal from port
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
CAN22_RXDA
P33.13
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
250
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-39 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T14
P33.14
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 5
Mux input channel 5 of TIM module 4
Mux input channel 0 of TIM module 2
Slave SPI clock inputs
Trigger input
GTM_TIM5_IN0_8
GTM_TIM4_IN5_14
GTM_TIM2_IN0_8
QSPI2_SCLKD
CBS_TGI6
P33.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT143
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
CBS_TGO6
P33.15
T12 PWM channel 62
Monitor input 1
Reference input 1
O
I
Trigger output
U14
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 6 of TIM module 4
Mux input channel 1 of TIM module 2
Trigger input
GTM_TIM5_IN1_9
GTM_TIM4_IN6_12
GTM_TIM2_IN1_7
CBS_TGI7
P33.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT144
—
QSPI2_SLSO11
—
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
CBS_TGO7
T12 PWM channel 62
Monitor input 1
Reference input 1
O
Trigger output
Data Sheet
251
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TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-40 Port 34 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
U11
P34.1
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 4 of TIM module 3
Mux input channel 3 of TIM module 2
Analog input channel 11, group 10
General-purpose output
GTM muxed output
GTM_TIM5_IN3_9
GTM_TIM3_IN4_12
GTM_TIM2_IN3_9
EVADC_G10CH11
P34.1
AI
O0
O1
O2
O3
O4
GTM_TOUT146
ASCLIN4_ATX
—
Transmit output
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
CAN20_TXD
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O5
O6
O7
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P34.2
T13 PWM channel 63
Monitor input 1
Reference input 1
T12
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 5 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM5_IN4_9
GTM_TIM3_IN5_13
GTM_TIM2_IN4_8
ASCLIN4_ARXB
CAN00_RXDG
CAN20_RXDC
EVADC_G10CH10
P34.2
CAN receive input node 0
CAN receive input node 0
Analog input channel 10, group 10
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT147
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
252
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-40 Port 34 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U12
P34.3
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 6 of TIM module 3
Mux input channel 5 of TIM module 2
Analog input channel 9, group 10
General-purpose output
GTM muxed output
GTM_TIM5_IN5_10
GTM_TIM3_IN6_13
GTM_TIM2_IN5_9
EVADC_G10CH9
P34.3
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT148
ASCLIN4_ASCLK
—
Shift clock output
Reserved
QSPI2_SLSO10
—
Master slave select output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P34.4
T12 PWM channel 60
Monitor input 1
Reference input 1
T13
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 7 of TIM module 3
Mux input channel 6 of TIM module 2
Master SPI data input
Analog input channel 8, group 10
General-purpose output
GTM muxed output
GTM_TIM5_IN6_10
GTM_TIM3_IN7_12
GTM_TIM2_IN6_8
QSPI2_MRSTD
EVADC_G10CH8
P34.4
AI
O0
O1
O2
O3
O4
GTM_TOUT149
ASCLIN4_ASLSO
—
Slave select signal output
Reserved
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
Reserved
—
Reserved
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
253
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-40 Port 34 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U13
P34.5
I
FAST /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 2
Slave SPI data input
Receive input
GTM_TIM5_IN7_9
GTM_TIM4_IN7_12
GTM_TIM2_IN7_9
QSPI2_MTSRD
ASCLIN8_ARXE
P34.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT150
ASCLIN8_ATX
—
Reserved
QSPI2_MTSR
—
Master SPI data output
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Table 2-41 Analog Inputs
Ball
Symbol
Ctrl. Buffer
Type
Function
T10
AN0
I
I
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
U10
W9
U9
T9
D / HighZ Analog Input 1
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
AN3
Analog input channel 2, group 0
Positive analog input channel 0, pin A
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
D / HighZ Analog Input 4
/ VDDM
EVADC_G11CH0
EVADC_G0CH4
AN5
Analog input channel 0, group 11
Analog input channel 4, group 0
Y9
D / HighZ Analog Input 5
/ VDDM
EVADC_G11CH1
EVADC_G0CH5
Analog input channel 1, group 11
Analog input channel 5, group 0
Data Sheet
254
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-41 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T8
AN6
I
I
I
I
I
I
I
I
I
I
I
I
D / HighZ Analog Input 6
/ VDDM
EVADC_G11CH2
EVADC_G0CH6
AN7
Analog input channel 2, group 11
Analog input channel 6, group 0
D / HighZ Analog Input 7
U8
W8
U7
Y8
W7
T7
/ VDDM
EVADC_G11CH3
EVADC_G0CH7
AN8
Analog input channel 3, group 11
Analog input channel 7, group 0
D / HighZ Analog Input 8
/ VDDM
EVADC_G11CH4
EVADC_G1CH0
AN9
Analog input channel 4, group 11
Analog input channel 0, group 1
D / HighZ Analog Input 9
/ VDDM
EVADC_G11CH5
EVADC_G1CH1
AN10
Analog input channel 5, group 11
Analog input channel 1, group 1
D / HighZ Analog Input 10
/ VDDM
EVADC_G11CH6
EVADC_G1CH2
AN11
Analog input channel 6, group 11
Analog input channel 2, group 1
D / HighZ Analog Input 11
/ VDDM
EVADC_G11CH7
EVADC_G1CH3
AN12
Analog input channel 7, group 11
Analog input channel 3, group 1
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
EDSADC_EDS0PB
AN13
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
W6
U6
T6
/ VDDM
EVADC_G1CH5
EDSADC_EDS0NB
AN14
Analog input channel 5, group 1
Negative analog input channel 0, pin B
D / HighZ Analog Input 14
/ VDDM
EVADC_G1CH6
EDSADC_EDS3PB
AN15
Analog input channel 6, group 1
Positive analog input channel 3, pin B
D / HighZ Analog Input 15
/ VDDM
EVADC_G1CH7
EDSADC_EDS3NB
AN16
Analog input channel 7, group 1
Negative analog input channel 3, pin N
W5
U5
D / HighZ Analog Input 16
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
AN17/P40.10
SENT_SENT10A
EVADC_G2CH1
EVADC_FC1CH0
Analog input channel 0, group 2
Analog input FC channel 0
S / HighZ Analog Input 17
/ VDDM
Receive input channel 10
Analog input channel 1, group 2
Analog input FC channel 1
Data Sheet
255
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TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-41 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W4
AN18/P40.11
I
S / HighZ Analog Input 18
/ VDDM
SENT_SENT11A
EVADC_G11CH8
EVADC_G2CH2
AN19/P40.12
Receive input channel 11
Analog input channel 8, group 11
Analog input channel 2, group 2
W3
I
S / HighZ Analog Input 19
/ VDDM
SENT_SENT12A
EVADC_G11CH9
EVADC_G2CH3
AN20
Receive input channel 12
Analog input channel 9, group 11
Analog input channel 3, group 2
Y3
Y2
I
I
D / HighZ Analog Input 20
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
AN22
Analog input channel 5, group 2
Negative analog input channel 2, pin A
T5
I
I
I
D / HighZ Analog Input 22
/ VDDM
EVADC_G2CH6
AN23
Analog input channel 6, group 2
R5
W2
D / HighZ Analog Input 23
/ VDDM
EVADC_G2CH7
AN24/P40.0
Analog input channel 7, group 2
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
W1
V2
V1
I
I
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN26/P40.2
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
S / HighZ Analog Input 26
/ VDDM
SENT_SENT2A
EVADC_G3CH2
CCU60_CCPOS1D
EVADC_G11CH10
AN27/P40.3
Receive input channel 2
Analog input channel 2, group 3
Hall capture input 1
Analog input channel 10, group 11
S / HighZ Analog Input 27
/ VDDM
SENT_SENT3A
EVADC_G3CH3
CCU60_CCPOS2B
EVADC_G11CH11
Receive input channel 3
Analog input channel 3, group 3
Hall capture input 2
Analog input channel 11, group 11
Data Sheet
256
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-41 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U2
AN28/P40.13
I
S / HighZ Analog Input 28
/ VDDM
SENT_SENT13A
EVADC_G3CH4
EVADC_G4CH4
AN29/P40.14
Receive input channel 13
Analog input channel 4, group 3
Analog input channel 4, group 4
U1
I
S / HighZ Analog Input 29
/ VDDM
SENT_SENT14A
EVADC_G3CH5
EVADC_G4CH5
AN30
Receive input channel 14
Analog input channel 5, group 3
Analog input channel 5, group 4
T4
R4
P4
I
I
I
D / HighZ Analog Input 30
/ VDDM
EVADC_G3CH6
EVADC_G4CH6
AN31
Analog input channel 6, group 3
Analog input channel 6, group 4
D / HighZ Analog Input 31
/ VDDM
EVADC_G3CH7
EVADC_G4CH7
AN32/P40.4
Analog input channel 7, group 3
Analog input channel 7, group 4
S / HighZ Analog Input 32
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
EVADC_G11CH12
AN33/P40.5
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
Analog input channel 12, group 11
R1
I
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
EVADC_G11CH13
AN34
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
Analog input channel 13, group 11
P5
R2
N4
I
I
I
D / HighZ Analog Input 34
/ VDDM
EVADC_G8CH2
EVADC_G11CH14
AN35
Analog input channel 2, group 8
Analog input channel 14, group 11
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
EVADC_G11CH15
AN36/P40.6
Analog input channel 3, group 8
Analog input channel 15, group 11
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
Data Sheet
257
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-41 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P2
AN37/P40.7
I
I
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
AN38/P40.8
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
N5
P1
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
AN40
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
M5
M4
L5
I
I
I
I
I
I
I
D / HighZ Analog Input 40
/ VDDM
EVADC_G8CH8
EVADC_G4CH0
AN41
Analog input channel 8, group 8
Analog input channel 0, group 4
D / HighZ Analog Input 41
/ VDDM
EVADC_G8CH9
EVADC_G4CH1
AN42
Analog input channel 9, group 8
Analog input channel 1, group 4
D / HighZ Analog Input 42
/ VDDM
EVADC_G8CH10
EVADC_G4CH2
AN43
Analog input channel 10, group 8
Analog input channel 2, group 4
L4
D / HighZ Analog Input 43
/ VDDM
EVADC_G8CH11
EVADC_G4CH3
AN44
Analog input channel 11, group 8
Analog input channel 3, group 4
D / HighZ Analog Input 44
N1
N2
M1
/ VDDM
EVADC_G8CH12
EDSADC_EDS1PC
AN45
Analog input channel 12, group 8
Positive analog input channel 1, pin C
D / HighZ Analog Input 45
/ VDDM
EVADC_G8CH13
EDSADC_EDS1NC
AN46
Analog input channel 13, group 8
Negative analog input channel 1, pin C
D / HighZ Analog Input 46
/ VDDM
EVADC_G8CH14
EDSADC_EDS1PD
Analog input channel 14, group 8
Positive analog input channel 1, pin D
Data Sheet
258
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-41 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
M2
AN47
I
D / HighZ Analog Input 47
/ VDDM
EVADC_G8CH15
EDSADC_EDS1ND
Analog input channel 15, group 8
Negative analog input channel 1, pin D
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
3. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
4. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-42 System I/O
Ball
Symbol
Ctrl. Buffer
Type
Function
G16
ESR1
I/O
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
ESR0
I
ESR1 pin input
F16
I/O
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
VGATE1P
I
ESR0 pin input
W17
Y17
O
—
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
VGATE1N
O
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
M20
M19
XTAL1
XTAL2
I
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
O
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
Data Sheet
259
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TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-42 System I/O (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L19
TRST
I
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
J16
K16
G17
TCK
I
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
DAP: DAP0 Clock Input
DAP0
TMS
I
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
DAP: DAP1 Data I/O
DAP1
I/O
PORST
I/O
PORST / PORST pin
PD /
Power On Reset Input. Additional strong PD in case of
VEXT
power fail.
Table 2-43 Supply
Ball
Symbol
Ctrl. Buffer
Type
Function
P8, P13, N7, VDD
N14, E15,
I
—
Digital Core Power Supply (1.25V)
H14, D16,
G13, G8, H7
A2, B3, V19, VEXT
W20
I
—
External Power Supply (5V / 3.3V)
D5
VFLEX
VDDM
VDDP3
I
I
I
I
—
—
—
—
Digital Power Supply for Flex Port Pads (5V / 3.3V)
ADC Analog Power Supply (5V / 3.3V)
Flash Power Supply (3.3V)
Y5
B18, A19
B2, D4, E5, VSS
T16, U17,
Digital Ground
W19, Y20,
E16, D17,
B19, A20
Y4
VSSM
I
—
Analog Ground for VDDM
Data Sheet
260
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TC38x AD/AE-Step
Pin Definition and Functions BGA292 Package Variant Pin Configuration
Table 2-43 Supply (cont’d)
Ball Symbol
Ctrl. Buffer
Type
Function
P9, P12, N9, VSS
N10, N11,
N12, M7,
I
—
Digital Ground
M8, M10,
M11, M13,
M14, L8, L9,
L10, L11,
L12, L13,
K8, K9, K10,
K11, K12,
K13, J7, J8,
J10, J11,
J13, J14, H9,
H10, H11,
H12, G9,
G10, G11,
G12, L14,
P10, P11,
K7, L7
L20
Y6
VSS
I
I
I
I
I
I
—
—
—
—
—
—
Oscillator Ground, VSS(OSC)
VAREF1
VAGND1
VAREF2
VAGND2
NC
Positive Analog Reference Voltage 1
Negative Analog Reference Voltage 1
Positive Analog Reference Voltage 2
Negative Analog Reference Voltage 2
Y7
T1
T2
K14
Not connected. These pins are reserved for future
extensions and shall not be connected externally
A1, Y1, U4
T11
NC1
I
I
—
—
Not connected. These pins are not connected on
package level and will not be used for future
extensions
VEVRSB
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
N19
N20
VDD
I
I
—
—
Digital Power Supply for Oscillator (1.25V), VDD(OSC)
VEXT
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT), VEXT(OSC)
Data Sheet
261
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
2.3
Sequence of Pads in Pad Frame
Table 2-44 Pad List
Number
Pad Name
ESR1
Pad Type
X
Y
Comment
1
FAST / PU1 / 263799
VEXT
179145
ESR1 Port Pin input - can be
used to trigger a reset or an
NMI
ESR1: External System
Request Reset 1. Default NMI
function. See also SCU
chapter for details. Default
after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
2
ESR0
FAST / OD /
VEXT
357795
179145
ESR0 Port Pin input - can be
used to trigger a reset or an
NMI
ESR0: External System
Request Reset 0. Default
configuration during and after
reset is open-drain driver.
The driver drives low during
power-on reset. This is valid
additionally after deactivation
of PORST_N until the internal
reset phase has finished. See
also SCU chapter for details.
Default after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
3
4
5
6
7
P20.9
P20.14
P15.0
P15.2
P15.4
FAST / PU1 / 409293
VEXT / ES
348147
179145
348147
179145
348147
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 456291
VEXT / ES
FAST / PU1 / 503289
VEXT / ES
FAST / PU1 / 550287
VEXT / ES
FAST / PU1 / 597285
VEXT / ES
Data Sheet
262
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
8
P15.1
FAST / PU1 / 644283
VEXT / ES
179145
General-purpose I/O
9
P15.3
P14.0
FAST / PU1 / 691281
VEXT / ES
348147
179145
General-purpose I/O
General-purpose I/O
10
FAST / PU1 / 738279
VEXT / ES2
11
12
VDDP3
P15.10
Vx
785277
348147
179145
Supply Voltage
FAST / PU1 / 832275
VEXT / ES6
General-purpose I/O
13
P15.11
FAST / PU1 / 926271
VEXT / ES6
179145
General-purpose I/O
14
15
16
VDD
Vx
Vx
973269
348147
179145
348147
Supply Voltage
VSS
1048869
Supply Voltage
P15.12
FAST / PU1 / 1124469
VEXT / ES6
General-purpose I/O
17
18
19
20
P15.6
FAST / PU1 / 1171467
VEXT / ES
179145
348147
179145
348147
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
P15.13
P15.7
FAST / PU1 / 1218465
VEXT / ES6
FAST / PU1 / 1265463
VEXT / ES
P15.14
FAST / PU1 / 1312461
VEXT / ES
21
22
VEXT
Vx
1359459
179145
348147
Supply Voltage
P15.15
FAST / PU1 / 1406457
VEXT / ES
General-purpose I/O
23
24
VSS
Vx
1453455
179145
348147
Supply Voltage
P14.4
SLOW / PU2 / 1500453
VEXT / ES
General-purpose I/O
25
26
27
28
29
30
31
P15.8
P14.1
P14.3
P14.5
P15.5
P14.11
VSS
FAST / PU1 / 1547451
VEXT / ES
179145
348147
179145
348147
179145
348147
179145
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
Supply Voltage
FAST / PU1 / 1594449
VEXT / ES2
SLOW / PU2 / 1641447
VEXT / ES
FAST / PU2 / 1688445
VEXT / ES
FAST / PU1 / 1735443
VEXT / ES
SLOW / PU1 / 1782441
VEXT / ES
Vx
1858041
Data Sheet
263
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
32
P14.12
SLOW / PU1 / 1933641
VEXT / ES
348147
General-purpose I/O
33
34
VDD
Vx
2009241
179145
348147
Supply Voltage
P14.13
FAST / PU1 / 2084841
VEXT / ES
General-purpose I/O
35
36
37
P14.7
P14.15
P14.6
SLOW / PU1 / 2131839
VEXT / ES
179145
348147
179145
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 2178837
VEXT / ES
FAST / PU1 / 2225835
VEXT / ES
38
39
VEXT
P14.9
Vx
2272833
2347884
348147
179145
Supply Voltage
LVDS_RX /
FAST / PU1 /
VEXT / ES
General-purpose I/O
40
P14.10
LVDS_RX /
FAST / PU1 /
VEXT / ES
2441880
179145
General-purpose I/O
41
42
43
P14.8
P14.2
P13.0
SLOW / PU1 / 2516931
VEXT / ES
348147
179145
348147
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU2 / 2563929
VEXT / ES
LVDS_TX /
FAST / PU1 /
VEXT / ES6
2675430
44
P13.1
LVDS_TX /
FAST / PU1 /
VEXT / ES6
2769426
348147
General-purpose I/O
45
46
47
VDD
VSS
Vx
Vx
2880927
2936925
3048426
348147
179145
348147
Supply Voltage
Supply Voltage
P13.2
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
48
P13.3
LVDS_TX /
FAST / PU1 /
VEXT / ES6
3142422
3253923
348147
General-purpose I/O
49
50
VDD
Vx
179145
348147
Supply Voltage
P13.9
FAST / PU1 / 3300921
VEXT / ES
General-purpose I/O
51
52
VSS
Vx
3347919
3459420
179145
348147
Supply Voltage
P13.4
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
Data Sheet
264
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
53
P13.5
LVDS_TX /
FAST / PU1 /
VEXT / ES6
3553416
348147
General-purpose I/O
54
55
P13.6
P13.7
LVDS_TX /
FAST / PU1 /
VEXT / ES6
3729420
3823416
348147
348147
General-purpose I/O
General-purpose I/O
LVDS_TX /
FAST / PU1 /
VEXT / ES6
56
57
58
VDD
Vx
Vx
3934917
3981915
348147
179145
348147
Supply Voltage
VSS
Supply Voltage
P13.10
SLOW / PU1 / 4085973
VEXT / ES
General-purpose I/O
59
60
VSS
Vx
4132971
179145
348147
Supply Voltage
P13.12
SLOW / PU1 / 4179969
VEXT / ES
General-purpose I/O
61
62
63
VEXT
Vx
Vx
4226967
4408965
179145
348147
179145
Supply Voltage
VDDP3
P13.13
Supply Voltage
SLOW / PU1 / 4455963
VEXT / ES
General-purpose I/O
64
65
VDDP3
P13.14
Vx
4502961
348147
179145
Supply Voltage
SLOW / PU1 / 4549959
VEXT / ES
General-purpose I/O
66
67
VDDP3
P13.11
Vx
4596957
348147
179145
Supply Voltage
SLOW / PU1 / 4643955
VEXT / ES
General-purpose I/O
68
69
70
71
72
P13.15
P14.14
P12.0
P12.1
P11.0
SLOW / PU1 / 4690953
VEXT / ES
348147
179145
179145
348147
348147
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 4737951
VEXT / ES
SLOW / PU1 / 4832019
VFLEX / ES
SLOW / PU1 / 4879017
VFLEX / ES
RFAST / PU1 / 4983021
VFLEX / ES
73
74
VFLEX
P11.1
Vx
5030019
179145
348147
Supply Voltage
RFAST / PU1 / 5105223
VFLEX / ES
General-purpose I/O
75
76
VSS
Vx
5152221
179145
348147
Supply Voltage
P11.2
RFAST / PU1 / 5227425
VFLEX / ES
General-purpose I/O
Data Sheet
265
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
77
Pad Name
VDD
Pad Type
X
Y
Comment
Vx
5274423
179145
348147
Supply Voltage
General-purpose I/O
78
P11.4
RFAST / PU1 / 5390127
VFLEX / ES
79
80
VSS
Vx
5477625
179145
348147
Supply Voltage
P11.3
RFAST / PU1 / 5552829
VFLEX / ES
General-purpose I/O
81
82
VFLEX
P11.6
Vx
5599827
179145
348147
Supply Voltage
RFAST / PU1 / 5675031
VFLEX / ES
General-purpose I/O
83
84
VSS
Vx
5722029
5769027
179145
348147
Supply Voltage
P11.5
SLOW /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
85
86
P11.7
P11.9
SLOW /
5821407
5872005
179145
348147
General-purpose I/O
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
FAST /
RGMII_Input /
PU1 / VFLEX /
ES
87
88
VFLEX
P11.8
Vx
5922603
5969601
179145
348147
Supply Voltage
SLOW /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
89
90
P11.10
P11.11
FAST /
6020199
6070797
179145
348147
General-purpose I/O
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
FAST /
RGMII_Input /
PU1 / VFLEX /
ES
91
92
VSS
Vx
6121395
6168393
179145
348147
Supply Voltage
P11.12
FAST /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
93
94
P11.14
P11.13
SLOW / PU1 / 6276357
VFLEX / ES
348147
179145
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 6323355
VFLEX / ES
Data Sheet
266
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
95
P11.15
SLOW / PU1 / 6370353
VFLEX / ES
348147
General-purpose I/O
96
97
98
VDD
VSS
Vx
Vx
6444567
6538563
179145
179145
348147
Supply Voltage
Supply Voltage
P10.0
SLOW / PU1 / 6614163
VEXT / ES
General-purpose I/O
99
VDD
Vx
6689763
179145
348147
Supply Voltage
100
P10.3
FAST / PU1 / 6765363
VEXT / ES
General-purpose I/O
101
102
VSS
Vx
6840963
179145
348147
Supply Voltage
P10.1
FAST / PU1 / 6916563
VEXT / ES
General-purpose I/O
103
104
VEXT
P10.9
Vx
6972561
179145
348147
Supply Voltage
SLOW / PU1 / 7089147
VEXT / ES
General-purpose I/O
105
106
VSS
Vx
7176645
179145
179145
Supply Voltage
P10.11
SLOW / PU1 / 7306641
VEXT / ES
General-purpose I/O
107
108
109
110
111
112
113
114
115
116
117
118
P10.4
P10.10
P10.15
P10.13
P10.2
P10.14
P10.6
P10.5
P10.8
P10.7
P02.0
P02.2
FAST / PU1 / 7391295
VEXT / ES
263799
357795
451791
545787
639783
733779
795888
842886
936882
983880
1030878
1077876
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 7391295
VEXT / ES
SLOW / PU1 / 7222293
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
FAST / PU1 / 7222293
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
SLOW / PU2 / 7222293
VEXT / ES
SLOW / PU2 / 7391295
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
SLOW / PU1 / 7222293
VEXT / ES
FAST / PU1 / 7391295
VEXT / ES
FAST / PU1 / 7222293
VEXT / ES
Data Sheet
267
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
119
P02.1
SLOW / PU1 / 7391295
VEXT / ES
1124874
General-purpose I/O
120
121
122
123
124
125
126
P02.5
FAST / PU1 / 7222293
VEXT / ES
1171872
1218870
1265868
1312866
1359864
1406862
1453860
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
P02.3
SLOW / PU1 / 7391295
VEXT / ES
P02.13
P02.11
P02.12
P02.4
SLOW / PU1 / 7222293
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
SLOW / PU1 / 7222293
VEXT / ES
FAST / PU1 / 7391295
VEXT / ES
P02.15
FAST / PU1 / 7222293
VEXT / ES
127
128
129
VDD
Vx
Vx
7391295
7391295
1529460
1623456
1699056
Supply Voltage
VSS
Supply Voltage
P02.14
SLOW / PU1 / 7222293
VEXT / ES
General-purpose I/O
130
131
132
133
134
135
136
137
P02.6
P01.0
P02.7
P01.1
P02.8
P01.2
P02.9
P01.8
FAST / PU1 / 7391295
VEXT / ES
1746054
1793052
1840050
1887048
1934046
1981044
2028042
2075040
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 7222293
VEXT / ES
FAST / PU1 / 7391295
VEXT / ES
SLOW / PU1 / 7222293
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
SLOW / PU1 / 7222293
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
SLOW / PU1 / 7222293
VEXT / ES
138
139
VEXT
P01.9
Vx
7391295
2122038
2169036
Supply Voltage
SLOW / PU1 / 7222293
VEXT / ES
General-purpose I/O
140
141
VSS
Vx
7391295
2216034
2263032
Supply Voltage
P01.11
SLOW / PU1 / 7222293
VEXT / ES
General-purpose I/O
Data Sheet
268
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
142
P02.10
SLOW / PU1 / 7391295
VEXT / ES
2310030
General-purpose I/O
143
P01.10
SLOW / PU1 / 7222293
VEXT / ES
2357028
General-purpose I/O
144
145
146
VSS
Vx
Vx
7391295
7391295
2432628
2526624
2620620
Supply Voltage
VDD
P00.0
Supply Voltage
FAST / PU1 / 7391295
VEXT / ES
General-purpose I/O
147
148
149
150
151
152
153
154
155
156
157
158
P01.13
P01.4
FAST / PU1 / 7222293
VEXT / ES
2667618
2714616
2761614
2808612
2855610
2902608
2949606
2996604
3043602
3090600
3137598
3184596
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 7391295
VEXT / ES
P01.12
P01.3
FAST / PU1 / 7222293
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
P01.15
P01.6
SLOW / PU1 / 7222293
VEXT / ES
FAST / PU1 / 7391295
VEXT / ES
P01.14
P01.5
FAST / PU1 / 7222293
VEXT / ES
SLOW / PU1 / 7391295
VEXT / ES
P00.15
P01.7
FAST / PU1 / 7222293
VEXT / ES
FAST / PU1 / 7391295
VEXT / ES
P00.13
RESERVED
FAST / PU1 / 7222293
VEXT / ES
Vx
7391295
PBIST_OFFMust be bonded
to VSS
159
160
RESERVED
P00.14
Vx
7391295
3278592
3325590
OTPMust be bonded to VSS
General-purpose I/O
SLOW / PU1 / 7222293
VEXT / ES
161
162
164
VSS
Vx
Vx
7391295
7391295
3401190
3495186
3572226
Supply Voltage
VDD
P00.1
Supply Voltage
SLOW / PU1 / 7222293
VEXT / ES
General-purpose I/O
165
P00.2
SLOW / PU1 / 7391295
VEXT / ES1
3619224
General-purpose I/O
Data Sheet
269
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
166
P00.3
SLOW / PU1 / 7222293
VEXT / ES1
3666222
General-purpose I/O
167
168
P00.4
P00.5
SLOW / PU1 / 7391295
VEXT / ES1
3713220
3760218
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 7222293
VEXT / ES1
169
170
VSS
Vx
7391295
3807216
3854214
Supply Voltage
P00.6
SLOW / PU1 / 7222293
VEXT / ES1
General-purpose I/O
171
172
VEXT
P00.7
Vx
7391295
3901212
3948210
Supply Voltage
SLOW / PU1 / 7222293
VEXT / ES1
General-purpose I/O
173
174
175
176
177
179
180
181
182
P00.8
P00.9
P00.10
P00.11
P00.12
AN47
AN46
AN45
AN44
SLOW / PU1 / 7391295
VEXT / ES1
3995208
4042206
4089204
4136202
4183200
4257414
4304412
4351410
4398408
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
Analog Input 47
SLOW / PU1 / 7222293
VEXT / ES1
SLOW / PU1 / 7391295
VEXT / ES1
SLOW / PU1 / 7222293
VEXT / ES1
SLOW / PU1 / 7391295
VEXT / ES1
D / HighZ /
VDDM
7222293
7391295
7222293
7391295
D / HighZ /
VDDM
Analog Input 46
D / HighZ /
VDDM
Analog Input 45
D / HighZ /
VDDM
Analog Input 44
183
184
185
186
187
188
189
VDDM
Vx
Vx
Vx
Vx
Vx
Vx
7222293
7391295
7222293
7391295
7222293
7391295
7222293
4445406
4492404
4539402
4586400
4633398
4680396
4727394
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Analog Input 43
VSSM
VAREF5
VAREF4
VAGND5
VAGND4
AN43
D / HighZ /
VDDM
190
191
AN42
AN41
D / HighZ /
VDDM
7391295
7222293
4774392
4821390
Analog Input 42
Analog Input 41
D / HighZ /
VDDM
Data Sheet
270
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
192
Pad Name
VSSM
Pad Type
X
Y
Comment
Vx
Vx
7391295
7222293
7391295
4868388
4915386
4962384
Supply Voltage
Supply Voltage
Analog Input 40
193
VDDM
194
AN40
D / HighZ /
VDDM
195
AN39/P40.9
S / HighZ /
VDDM
7222293
5009382
Analog Input 39
196
197
VSSM
Vx
7391295
7222293
5056380
5103378
Supply Voltage
Analog Input 38
AN38/P40.8
S / HighZ /
VDDM
198
199
VDDM
Vx
7391295
7222293
5150376
5197374
Supply Voltage
Analog Input 37
AN37/P40.7
S / HighZ /
VDDM
200
201
202
203
204
AN36/P40.6
AN35
S / HighZ /
VDDM
7391295
7222293
7391295
7222293
7391295
5244372
5291370
5338368
5385366
5432364
Analog Input 36
Analog Input 35
Analog Input 34
Analog Input 33
Analog Input 32
D / HighZ /
VDDM
AN34
D / HighZ /
VDDM
AN33/P40.5
AN32/P40.4
S / HighZ /
VDDM
S / HighZ /
VDDM
205
206
207
208
209
VAREF3
VAREF2
VAGND3
VAGND2
AN71/P41.3
Vx
Vx
Vx
Vx
7222293
7391295
7222293
7391295
7222293
5479362
5526360
5573358
5620356
5667354
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Analog Input 71
S / HighZ /
VDDM
210
211
212
213
214
215
216
AN70/P41.2
AN69/P41.1
AN68/P41.0
S / HighZ /
VDDM
7391295
7222293
7391295
7222293
7391295
7222293
7391295
5714352
5761350
5808348
5855346
5902344
5949342
5996340
Analog Input 70
Analog Input 69
Analog Input 68
Analog Input 67
Analog Input 66
Analog Input 65
Analog Input 64
S / HighZ /
VDDM
S / HighZ /
VDDM
AN67/P40.15 S / HighZ /
VDDM
AN66
D / HighZ /
VDDM
AN65
D / HighZ /
VDDM
AN64/P41.8
S / HighZ /
VDDM
Data Sheet
271
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
217
Pad Name
VDDM
Pad Type
X
Y
Comment
Vx
Vx
7222293
7391295
7222293
6043338
6090336
6137334
Supply Voltage
Supply Voltage
Analog Input 63
218
VSSM
219
AN63/P41.7
S / HighZ /
VDDM
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
AN62/P41.6
AN61
S / HighZ /
VDDM
7391295
7222293
7391295
7222293
7391295
7222293
7391295
7222293
7391295
7222293
7391295
7222293
7391295
7222293
7391295
7391295
7302141
7208145
7161147
6184332
6231330
6278328
6325326
6372324
6419322
6466320
6513318
6560316
6607314
6654312
6701310
6748308
6795306
6842304
6936300
7058295
7058295
6889293
Analog Input 62
Analog Input 61
Analog Input 60
Analog Input 59
Analog Input 58
Analog Input 57
Analog Input 56
Analog Input 55
Analog Input 54
Analog Input 53
Analog Input 52
Analog Input 51
Analog Input 50
Analog Input 49
Analog Input 48
Analog Input 31
Analog Input 30
Analog Input 29
Analog Input 28
D / HighZ /
VDDM
AN60
D / HighZ /
VDDM
AN59
D / HighZ /
VDDM
AN58
D / HighZ /
VDDM
AN57
D / HighZ /
VDDM
AN56
D / HighZ /
VDDM
AN55/P41.5
AN54/P41.4
AN53
S / HighZ /
VDDM
S / HighZ /
VDDM
D / HighZ /
VDDM
AN52
D / HighZ /
VDDM
AN51
D / HighZ /
VDDM
AN50
D / HighZ /
VDDM
AN49
D / HighZ /
VDDM
AN48
D / HighZ /
VDDM
AN31
D / HighZ /
VDDM
AN30
D / HighZ /
VDDM
AN29/P40.14 S / HighZ /
VDDM
AN28/P40.13 S / HighZ /
VDDM
Data Sheet
272
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
239
AN27/P40.3
S / HighZ /
VDDM
7114149
7058295
Analog Input 27
240
241
242
243
244
245
246
247
248
249
250
251
AN26/P40.2
AN25/P40.1
AN24/P40.0
AN23
S / HighZ /
VDDM
7067151
7020153
6973155
6926157
6879159
6832161
6785163
6738165
6691167
6644169
6597171
6550173
6889293
7058295
6889293
7058295
6889293
7058295
6889293
7058295
6889293
7058295
6889293
7058295
Analog Input 26
Analog Input 25
Analog Input 24
Analog Input 23
Analog Input 22
Analog Input 21
Analog Input 20
Analog Input 19
Analog Input 18
Analog Input 17
Analog Input 16
Analog Input 15
S / HighZ /
VDDM
S / HighZ /
VDDM
D / HighZ /
VDDM
AN22
D / HighZ /
VDDM
AN21
D / HighZ /
VDDM
AN20
D / HighZ /
VDDM
AN19/P40.12 S / HighZ /
VDDM
AN18/P40.11 S / HighZ /
VDDM
AN17/P40.10 S / HighZ /
VDDM
AN16
D / HighZ /
VDDM
AN15
D / HighZ /
VDDM
252
253
254
255
256
VAGND1
VAGND0
VAREF1
VAREF0
AN14
Vx
Vx
Vx
Vx
6503175
6456177
6409179
6362181
6315183
6889293
7058295
6889293
7058295
6889293
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Analog Input 14
D / HighZ /
VDDM
257
AN13
D / HighZ /
VDDM
6268185
7058295
Analog Input 13
258
259
260
VDDM
VSSM
AN12
Vx
Vx
6221187
6174189
6127191
6889293
7058295
6889293
Supply Voltage
Supply Voltage
Analog Input 12
D / HighZ /
VDDM
261
262
263
VSSM
VDDM
AN11
Vx
Vx
6080193
6033195
5986197
7058295
6889293
7058295
Supply Voltage
Supply Voltage
Analog Input 11
D / HighZ /
VDDM
Data Sheet
273
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
264
AN10
D / HighZ /
VDDM
5939199
6889293
Analog Input 10
265
266
267
268
269
270
271
272
273
274
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
D / HighZ /
VDDM
5892201
5845203
5798205
5751207
5704209
5657211
5610213
5563215
5516217
5469219
7058295
6889293
7058295
6889293
7058295
6889293
7058295
6889293
7058295
6889293
Analog Input 9
Analog Input 8
Analog Input 7
Analog Input 6
Analog Input 5
Analog Input 4
Analog Input 3
Analog Input 2
Analog Input 1
Analog Input 0
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
276
277
278
279
280
281
VSS
Vx
Vx
Vx
Vx
Vx
5386005
5310405
5234805
5140809
4961709
7058295
6889293
7058295
7058295
6889293
7058295
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
VDD
VSS
VEXT
P32.1
SLOW / PU1 / 4914711
VEXT / ES
282
VGATE1P
Vx
4867713
6889293
DCDC P ch. MOSFET gate
driver output
283
284
VSS
Vx
Vx
4802715
4737717
7058295
6889293
Supply Voltage
VGATE1N
DCDC N ch. MOSFET gate
driver output
285
P32.0
SLOW / PU1 / 4690719
VEXT / ES
7058295
General-purpose I/O
286
287
288
VEVRSB
VEVRSB
P33.1
Vx
Vx
4607505
4560507
6889293
7058295
6889293
Supply Voltage
Supply Voltage
SLOW / PU1 / 4513509
General-purpose I/O
VEVRSB /
ES5
289
VSS
Vx
4466511
274
7058295
Supply Voltage
V 1.2, 2021-03
Data Sheet
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
290
Pad Name
VSS
Pad Type
X
Y
Comment
—
—
4354515
4307517
7058295
6889293
7058295
Supply Voltage
Supply Voltage
General-purpose I/O
291
VDD
292
P33.0
SLOW / PU1 / 4260519
VEVRSB /
ES5
293
294
295
P33.3
P33.2
P33.5
SLOW / PU1 / 4213521
VEVRSB /
ES5
6889293
7058295
6889293
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 4166523
VEVRSB /
ES5
SLOW / PU1 / 4119525
VEVRSB /
ES5
296
297
298
VSS
Vx
Vx
4016925
3969927
7058295
6889293
7058295
Supply Voltage
VDD
P34.1
Supply Voltage
SLOW / PU1 / 3922929
General-purpose I/O
VEVRSB /
ES5
299
P33.4
SLOW / PU1 / 3875931
6889293
General-purpose I/O
VEVRSB /
ES5
300
301
P34.3
P33.7
SLOW / PU1 / 3828933
VEVRSB / ES
7058295
6889293
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 3781935
VEVRSB /
ES5
302
303
P34.2
P33.6
SLOW / PU1 / 3734937
VEVRSB / ES
7058295
6889293
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 3687939
VEVRSB /
ES5
304
305
P34.5
P33.9
FAST / PU1 / 3640941
VEVRSB / ES
7058295
6889293
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 3593943
VEVRSB /
ES5
306
307
VEVRSB
P33.8
Vx
3546945
7058295
6889293
Supply Voltage
FAST / HighZ / 3499947
VEVRSB
General-purpose I/O
308
P34.4
SLOW / PU1 / 3452949
VEVRSB / ES
7058295
General-purpose I/O
Data Sheet
275
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
309
P33.11
FAST / PU1 / 3405951
6889293
General-purpose I/O
VEVRSB /
ES5
310
311
312
313
VSS
Vx
Vx
Vx
3303153
3256155
3209157
7058295
6889293
7058295
6889293
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
VSS
P33.10
FAST / PU1 / 3162159
VEVRSB /
ES5
314
315
316
317
P33.15
P33.13
P33.14
P33.12
SLOW / PU1 / 3115161
VEVRSB /
ES5
7058295
6889293
7058295
6889293
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 3068163
VEVRSB /
ES5
FAST / PU1 / 3021165
VEVRSB /
ES5
FAST / PU1 / 2974167
VEVRSB /
ES5
318
319
320
VDD
VSS
—
—
2890953
2796957
7058295
7058295
6889293
Supply Voltage
Supply Voltage
P32.2
SLOW / PU1 / 2721357
VEXT / ES
General-purpose I/O
321
322
P32.5
P32.4
SLOW / PU1 / 2674359
VEXT / ES
7058295
6889293
General-purpose I/O
General-purpose I/O
FAST / PU1 / 2627361
VEXT / ES
323
324
325
VSS
Vx
Vx
2580363
2533365
7058295
6889293
7058295
Supply Voltage
VEXT
P32.3
Supply Voltage
SLOW / PU1 / 2486367
VEXT / ES
General-purpose I/O
326
P32.7
SLOW / PU1 / 2439369
VEXT / ES
6889293
General-purpose I/O
327
328
VSS
Vx
2363769
7058295
6889293
Supply Voltage
P32.6
SLOW / PU1 / 2288169
VEXT / ES
General-purpose I/O
329
330
VDD
Vx
2212569
7058295
6889293
Supply Voltage
P31.1
FAST / PU1 / 2136969
VEXT / ES
General-purpose I/O
331
P31.0
FAST / PU1 / 2089971
VEXT / ES
7058295
General-purpose I/O
Data Sheet
276
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
332
P31.3
FAST / PU1 / 2042973
VEXT / ES
6889293
General-purpose I/O
333
334
335
336
337
338
339
340
341
342
343
344
P31.2
P31.4
P31.5
P31.6
P31.7
P31.8
P31.10
P31.9
P31.12
P31.11
P31.14
P31.13
FAST / PU1 / 1995975
VEXT / ES
7058295
6889293
7058295
6889293
7058295
6889293
7058295
6889293
7058295
6889293
7058295
6889293
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 1948977
VEXT / ES
FAST / PU1 / 1901979
VEXT / ES
FAST / PU1 / 1854981
VEXT / ES
FAST / PU1 / 1807983
VEXT / ES
FAST / PU1 / 1760985
VEXT / ES
FAST / PU1 / 1713987
VEXT / ES
FAST / PU1 / 1666989
VEXT / ES
FAST / PU1 / 1619991
VEXT / ES
FAST / PU1 / 1572993
VEXT / ES
FAST / PU1 / 1525995
VEXT / ES
FAST / PU1 / 1478997
VEXT / ES
345
346
347
VDD
Vx
Vx
1403397
1309401
7058295
7058295
6889293
Supply Voltage
VSS
Supply Voltage
P31.15
FAST / PU1 / 1233801
VEXT / ES
General-purpose I/O
348
349
P30.2
P30.0
FAST / PU1 / 1186803
VEXT / ES
7058295
6889293
General-purpose I/O
General-purpose I/O
FAST / PU1 / 1139805
VEXT / ES
350
351
VSS
Vx
1092807
7058295
6889293
Supply Voltage
P30.1
FAST / PU1 / 1045809
VEXT / ES
General-purpose I/O
352
353
VEXT
P30.3
Vx
998811
7058295
6889293
Supply Voltage
FAST / PU1 / 951813
VEXT / ES
General-purpose I/O
354
P30.5
FAST / PU1 / 904815
VEXT / ES
7058295
General-purpose I/O
Data Sheet
277
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
355
P30.4
FAST / PU1 / 857817
VEXT / ES
6889293
General-purpose I/O
356
P30.8
FAST / PU1 / 810819
VEXT / ES
7058295
General-purpose I/O
357
358
359
360
361
VDD
VSS
VDD
VSS
P30.6
Vx
Vx
Vx
Vx
763821
716823
614223
538623
6889293
7058295
6889293
7058295
6889293
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
FAST / PU1 / 463023
VEXT / ES
362
363
369
370
371
372
373
374
375
376
377
378
379
380
381
382
P30.9
P30.7
P30.10
P30.11
P30.14
P30.15
P30.13
P30.12
P26.0
P25.0
P23.0
P23.1
P23.2
P25.2
P23.3
P25.1
FAST / PU1 / 357795
VEXT / ES
7058295
7058295
6973641
6879645
6828147
6781149
6734151
6687153
6640155
6593157
6546159
6499161
6443163
6396165
6349167
6302169
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 263799
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
SLOW / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
SLOW / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
SLOW / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
SLOW / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
Data Sheet
278
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
383
Pad Name
VEXT
Pad Type
X
Y
Comment
Vx
348147
6255171
6208173
Supply Voltage
General-purpose I/O
384
P25.4
FAST / PU1 / 179145
VEXT / ES
385
386
VSS
Vx
348147
6161175
6114177
Supply Voltage
P23.5
FAST / PU1 / 179145
VEXT / ES
General-purpose I/O
387
388
389
390
391
392
393
394
395
396
397
P23.6
P23.7
P25.3
P22.4
P25.7
P25.5
P25.8
P25.9
P25.10
P22.5
P25.11
SLOW / PU1 / 348147
VEXT / ES
6067179
6020181
5973183
5926185
5879187
5832189
5785191
5738193
5691195
5644197
5588199
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
398
399
400
VSS
Vx
Vx
179145
348147
5512599
5436999
5390001
Supply Voltage
VDD
Supply Voltage
P25.12
FAST / PU1 / 179145
VEXT / ES
General-purpose I/O
401
402
403
404
405
P23.4
FAST / PU1 / 348147
VEXT / ES
5343003
5296005
5249007
5202009
5155011
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
P25.14
P25.13
P25.15
P25.6
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
Data Sheet
279
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
406
P24.1
FAST / PU1 / 179145
VEXT / ES
5108013
General-purpose I/O
407
408
409
410
411
P24.0
P24.3
P24.2
P24.5
P24.4
FAST / PU1 / 348147
VEXT / ES
5061015
5014017
4967019
4920021
4873023
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
FAST / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
412
413
414
VEXT
VSS
Vx
Vx
179145
348147
4826025
4779027
4732029
Supply Voltage
Supply Voltage
P22.7
SLOW / PU1 / 179145
VEXT / ES
General-purpose I/O
415
416
417
418
419
P24.9
P22.6
P24.8
P22.8
P22.2
FAST / PU1 / 348147
VEXT / ES
4685031
4638033
4591035
4544037
4432536
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
LVDS_TX /
FAST / PU1 /
VEXT / ES6
348147
420
P22.3
LVDS_TX /
FAST / PU1 /
VEXT / ES6
348147
4338540
General-purpose I/O
421
422
VDD
Vx
179145
348147
4227039
4115538
Supply Voltage
P22.0
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
423
P22.1
LVDS_TX /
FAST / PU1 /
VEXT / ES6
348147
179145
4021542
General-purpose I/O
424
425
VSS
Vx
3910041
3834441
Supply Voltage
P24.6
FAST / PU1 / 348147
VEXT / ES
General-purpose I/O
426
P24.7
FAST / PU1 / 179145
VEXT / ES
3787443
General-purpose I/O
Data Sheet
280
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
427
P24.11
FAST / PU1 / 348147
VEXT / ES
3740445
General-purpose I/O
428
429
430
VSS
Vx
Vx
179145
348147
3664845
3570849
3495249
Supply Voltage
VDD
Supply Voltage
P24.10
FAST / PU1 / 179145
VEXT / ES
General-purpose I/O
432
433
434
VDD
Vx
Vx
348147
179145
3406041
3359043
3199392
Supply Voltage
Supply Voltage
VSS
XTAL1
XTAL / VEXT 179145
XTAL pad1
XTAL1. Main
Oscillator/PLL/Clock
Generator Input.
435
XTAL2
XTAL / VEXT 179145
3105396
XTAL pad2
XTAL2. Main
Oscillator/PLL/Clock
Generator OUTPUT
436
437
439
VSS
—
179145
348147
2945745
2898747
2764233
Supply Voltage
VEXT
P24.13
Vx
Supply Voltage
FAST / PU1 / 348147
VEXT / ES
General-purpose I/O
440
441
442
443
444
445
446
447
P22.11
P24.12
P22.10
P24.15
P22.9
SLOW / PU1 / 179145
VEXT / ES
2717235
2670237
2623239
2576241
2529243
2482245
2435247
2360196
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 348147
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
FAST / PU1 / 348147
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
P24.14
TRST
FAST / PU1 / 348147
VEXT / ES
FAST / PU2 / 179145
VEXT
JTAG Module Reset/Enable
Input
P21.0
LVDS_RX /
FAST / PU1 /
VEXT / ES
348147
348147
179145
General-purpose I/O
General-purpose I/O
Supply Voltage
448
449
P21.1
VDD
LVDS_RX /
FAST / PU1 /
VEXT / ES
2266200
2191149
Vx
Data Sheet
281
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
450
P21.2
LVDS_RX /
FAST / PU1 /
VEXT / ES
348147
2116098
General-purpose I/O
451
P21.3
LVDS_RX /
FAST / PU1 /
VEXT / ES
348147
2022102
General-purpose I/O
452
453
VSS
Vx
179145
348147
1947051
1835550
Supply Voltage
P21.4
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
454
P21.5
LVDS_TX /
FAST / PU1 /
VEXT / ES6
348147
1741554
General-purpose I/O
455
456
457
458
459
VDD
VSS
Vx
Vx
Vx
Vx
348147
179145
348147
179145
1630053
1554453
1460457
1413459
1366461
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VSS
VEXT
P20.0
FAST / PU1 / 348147
VEXT / ES
460
461
TCK
FAST / PD2 / 179145
VEXT
1319463
1272465
JTAG Module Clock Input
P20.2
S / PU / VEXT 348147
General-purpose I/O
This pin is latched at power
on reset release to enter test
mode.
462
463
464
465
TMS
FAST / PD2 / 179145
VEXT
1225467
1178469
1131471
1084473
JTAG Module State Machine
Control Input
P20.3
SLOW / PU1 / 348147
VEXT / ES
General-purpose I/O
General-purpose I/O
General-purpose I/O
P21.7/TDO
P20.1
FAST / PU2 / 179145
VEXT / ES4
SLOW / PU1 / 348147
VEXT / ES
466
467
VEXT
P20.8
Vx
179145
1037475
990477
Supply Voltage
FAST / PU1 / 348147
VEXT / ES
General-purpose I/O
468
469
VSS
Vx
179145
943479
896481
Supply Voltage
P20.7
FAST / PU1 / 348147
VEXT / ES
General-purpose I/O
470
471
VDD
Vx
179145
820881
745281
Supply Voltage
P20.11
FAST / PU1 / 348147
VEXT / ES
General-purpose I/O
Data Sheet
282
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TC38x AD/AE-Step
Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-44 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
472
P21.6/TDI
FAST / PD /
PU2 / VEXT /
ES3
179145
698283
General-purpose I/O
PD during Reset and in
DAP/DAPE or JTAG mode.
After Reset release and when
not in DAP/DAPE or JTAG
mode: PU. In Standby mode:
HighZ.
473
P20.10
FAST / PU1 / 348147
VEXT / ES
651285
General-purpose I/O
474
475
VSS
Vx
179145
575685
500085
Supply Voltage
P20.13
FAST / PU1 / 348147
VEXT / ES
General-purpose I/O
476
PORST
PORST / PD / 179145
VEXT
451791
PORST pin
Power On Reset Input.
Additional strong PD in case
of power fail.
477
478
P20.12
P20.6
FAST / PU1 / 179145
VEXT / ES
357795
263799
General-purpose I/O
SLOW / PU1 / 179145
VEXT / ES
General-purpose I/O
Whenever in table of section 3 ’Electrical Specification’ the term ‘neighbor pads’ is used, the detailed definition is
provided by Figure 2-44. This statement is also valid for next/nearest neighbor pads.
In order to find out who is affecting operation on a target pad (interfering) a number of active close-neighbor pads
(ACNP) has to be defined.
Finding close-neighbor pads.
The Pad Ring has four edges: bottom, left, top, right. Each edge is limited, i.e. it has two ends.
Each pad has two direct (first) neighbors unless it is located at the end of the edge. In that case it only has one
neighbor. Similarly, each pad has two indirect (second) neighbors unless it or its first neighbor is located at the
end of the edge. These first and second neighbors we will collectively call Close-Neighbor pads. Therefore each
pad has 2 to 4 close-neighbor pads.
Finding close-neighbors can be done with the following sequence:
1.) Choose a target pad and lookup its “X” and “Y” coordinates in table Figure 2-44.
2.) Find first and second neighbors by calculating “X” and “Y” distance from the selected pad. Figure 2-44 is sorted
by “Y” coordinate, which might help locate the 4 close-neighbor candidates (if the pad is near the edge, it might
end up with less than 4 close-neighbors).
Defining active pads:
Pad is active if it is currently in use and if it doesn’t have “Vxx” in the name.
Figuring out number of active close-neighbor pads follow next rules:
- If the first neighbor is active, then we count it and also check if second neighbor (on the same side of selected
pad) is active.
- If the first neighbor is not active, then we do not check the second on the same side.
Data Sheet
283
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TC38x AD/AE-Step
Pin Definition and Functions Legend
2.4
Legend
The data in this chapter 2 match with the file TC38xpd_IO_Spirit_v1.0.0.1.21.xml.
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field Selection PCx = 0XXXB)
O = Output (for GPIO port lines the ´O´ represents in most cases the port HWOUT function)
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Buffer Type”:
RFAST = Pad class RFAST (5V/3.3V)
FAST = Pad class FAST (5V/3.3V)
SLOW = Pad class SLOW (5V/3.3V)
LVDS_TX = Pad class LVDS Transmit
LVDS_RX = Pad class LVDS Receive
S = Pad class S (Analog Input overlayed with General Purpose Input)
D = Pad class D (Analog Input)
Porst = Porst input Pad
XTAL1 = XTAL1 input Pad
XTAL2 = XTAL2 input Pad
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1)
PU2 = with pull-up device connected during startup and reset, HighZ in Standby mode
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1)
PD2 = with pull-down device connected during startup and reset, HighZ in Standby mode
OD = open drain during reset (PORST = 0)
ES = Supports Emergency Stop
ES1 = ES. ES can be overruled by VADC, control via P00_PCSR
ES2 = ES. ES can be overruled by DXCPL - DAP over CAN physical layer, No overruling for DXCM - Debug over
CAN message
ES3 = ES. ES can be overruled by JTAG mode if this pin is used as TDI
ES4 = ES. ES can be overruled by JTAG or Three Pin DAP mode
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG6 (P14.4). Pls. see also chapter
PMS, HWCFG[6].
Data Sheet
284
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OPEN MARKET VERSION
TC38x AD/AE-Step
Pin Definition and Functions Legend
ES5 = ES. ES can be overruled by the Standby Controller - SCR - if implemented. Overruling can be disabled via
the control register P33_PCSR and P34_PCSR
ES6 = ES. On LVDS TX pads the ES affects the pads only in CMOS mode, not in LVDS mode. Thus, only when
LPCRx.TX_EN selects the CMOS Mode, the output is switched off in the ES event
Data Sheet
285
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TC38x AD/AE-Step
Electrical Specification Parameter Interpretation
3
Electrical Specification
3.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC38x and partly its requirements
on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with
an two-letter abbreviation in column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of the TC38x and must be
regarded for a system design.
•
SR
Such parameters indicate System Requirements which must be provided by the microcontroller system in
which the TC38x designed in.
Data Sheet
286
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Absolute Maximum Ratings
3.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3-1 Absolute Maximum Ratings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
150
Storage Temperature
T
ST SR
-65
-
-
-
-
°C
V
upto 65h @ TJ = 150°C
upto 2.8h
Voltage at VDD power supply
pins with respect to VSS
V
DD SR
-
-
-
1.65
1.45
4.43
1) 2)
V
upto 72h
Voltage at VDDP3 power supply
pins with respect to VSS
V
DDP3 SR
V
Voltage at VDDM, VEXT, VFLEX and VDDM SR
EVRSB power supply pins with
respect to VSS
-
-
-
-
6.75
5.6
V
V
upto 2.8h
upto 72h
V
Voltage on all analog and class VIN SR
-0.7
-
6.75
V
S input pins with respect to VSS
3)
Voltage on all other input pins
with respect to VSS
VIN SR
-0.7
-10
-
-
-
6.75
10
V
3)
Input current on any pin during IIN SR
mA
mA
4) 5)
overload condition
Absolute maximum sum of all
input circuit currents during
overload condition. 4)
ΣIIN SR
-100
100
1) Valid for cumulated for up to 2.8h and pulse forms followed a power supply switch on phase, where the rise
and fall times are related to the system capacities and coils.
2) Due to EVRC output voltage oscillation during switch off phase VDD can drop down to -0.72V. For VDD an input level down to
-0.72V during switch off phase will not cause any damage or reliability problem.
3) Voltages below VINmin have no Impact to the device reliability as Long as the times and currents defined in section Pin Reliability
in Overload for the affected pad(s) are not violated.
4) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may
damage the device.
5) The specified min. and max. values represent the current limits, which have to be maintained, in case of a short circuit condition
on the output of any Fast, RFast, Slow and Class S pad, not being used during operation.
This covers also output currents due to switching in operation for CL=200pF.
Data Sheet
287
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TC38x AD/AE-Step
Electrical Specification Pin Reliability in Overload
3.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience overload currents and
voltages that go beyond their own IO power supplies specification.
The following table defines overload conditions that will not cause any negative reliability impact if all the following
conditions are met:
•
allowed time interval (defined in Note column) for overload condition is not exceeded. If no time limit is defined
the allowed time includes both ‘Operation Lifetime hours’ and ‘Inactive Lifetime hours’. The number of hours
in Table 3-68 and Table 3-69 are examples only and the applicable numbers are defined by the customer
profiles accepted by Infineon.
•
Operating Conditions are met for
–
–
pad supply levels
temperature
If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters
functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still
possible in most cases but with relaxed parameters.
Table 3-2 Overload Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-5
-15 1)
Max.
5
15 1)
Input current on any digital pin IIN
during overload condition
-
-
mA
mA
except LVDS pins
except LVDS pins;
limited to max. 20
pulses with 1ms pulse
length
Input current on LVDS pin
during overload condition
IINLVDS
-3
-
3
mA
Input current on analog input pin IINANA
during overload condition
-3
-5
-
-
3
5
mA
mA
limited to 60h over
lifetime
Absolute sum of all analog input IINSA
currents for analog inputs during
overload condition
-20
-
-
20
mA
mA
Absolute maximum sum of all
input circuit currents during
overload condition (digital and
analog combined)
ΣIINS
-100
100
Signal voltage over/undershoot VOUS
at GPIOs
V
SS - 2
-
VEXT/FLEX
+ 2
V
limited to 60h over
lifetime; Valid for non
LVDS and analoge
pads
Sum of all inactive device pin
currents
IIDS
-100
-
-
-
100
2.5
5
mA
mA
mA
Static pin output current
I
OUT CC
-
-
100% duty cycle;
output driver = medium
100% duty cycle;
output driver = strong
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Pin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
digital inputs, negative
K
OVDN CC
-
-
3*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
fast pads; -5mA < IIN <
0mA
-
-
-
2*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
slow pads VGASTE1N
and VGATE1P; -5mA <
IIN < 0mA
-
1*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
slow pads; -5mA < IIN <
0mA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
0.5
Overload injected on
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for
digital inputs, positive
K
OVDP CC
1.5*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
GPIO non LVDS pads
1
Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
5*10-3
1*10-4
1*10-5
Overload injected on
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for
analog inputs, negative 2)
K
OVAN CC
Analog inputs overlaid
with slow pads or pull
down diagnostics; -
5mA < IIN < 0mA
else; -5mA < IIN < 0mA
Data Sheet
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Pin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
analog inputs, positive 2)
K
OVAP CC
-
-
2*10-4
Analoge inputs overlaid
with slow pads or pull
down diagnostics; 0mA
< IIN < 5mA
-
-
2*10-5
else; 0mA < IIN < 5mA
1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters.
2) Overload coupling on analog inputs is caused by parasitic effects between pads, input multiplexers and surrounding structures.
The given parameters have been verified for all permutations of channels. Also watch multiple connections of a pin to several
channels.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Operating Conditions
3.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the
TC38x. All parameters specified in the following tables refer to these operating conditions, unless otherwise
noticed.
Digital supply voltages applied to the TC38x must be static regulated voltages.
All parameters specified in the following tables refer to these operating conditions (see table below), unless
otherwise noticed in the Note / Test Condition column.
Table 3-3 Operating Conditions
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
300
300
300
100
300
100
200
100
-
SRI frequency
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SRI SR
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CPU Frequency (All CPUs)
PLL0 output frequency
SPB frequency
CPUx SR
PLL0 SR
SPB SR
FSI2 SR
FSI SR
-
-
20
-
-
-
FSI2 frequency
-
-
FSI frequency
20
-
-
GTM frequency
GTM SR
STM SR
ERAY SR
ADC SR
ASCLINx SR
CAN SR
I2C SR
-
STM frequency
-
-
ERAY frequency
-
80
-
VADC frequency
-
160
200
80
ASCLIN Operating Frequency
CAN frequency
-
-
-
-
I2C frequency
-
-
100
200
320
Operating MSC Frequency
MSC SR
PLL1 SR
-
-
PLL1 output frequency from
PER PLL
20
-
PLL2 output frequency from
PER PLL
f
PLL2 SR
20
-
200
MHz
QSPI Frequency
f
f
f
f
QSPI SR
-
-
-
-
-
-
200
300
100
150
125
MHz
MHz
MHz
MHz
°C
ADAS clock frequency
MCANH frequency
GETH frequency
ADAS CC
MCANH CC
GETH CC
200
-
100
-40
Ambient Temperature
TA SR
valid for all SAK
products
-40
-40
-
-
150
170
°C
°C
valid for all SAL
products with package
valid for all SAL
products without
package
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Operating Conditions
Table 3-3 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Junction Temperature
TJ SR
-40
-
150
°C
°C
valid for all SAK
products
-40
-
170
valid for all SAL
products
Core Supply Voltage
V
V
V
DD SR
1.125 1)
2.97
1.25
5.0
1.375 2)
5.5 3)
5.5 3)
V
V
V
ADC analog supply voltage
DDM SR
EXT SR
Digital external supply voltage
for pads and EVR
4.5
5.0
Nominal 5V Pad / Port
Pin supply range. 5V
pad parameters are
valid.
2.97
3.6
3.3
3.63
4.5
V
V
Nominal 3.3V Pad /
Port Pin supply range
with VDDP3 supplied
externally and EVR33
inactive. 3.3V pad
parameters are valid.
-
Flash configured in
cranking mode; Flash
read operation with
reduced performance.
EVR33 active in low
voltage mode. 3.3V pad
parameters are valid.
2.97
-
3.6
V
Incase EVR33 is active,
Flash configured in
sleep mode and
execution switched to
RAM. 3.3V pad
parameters are valid.
Digital supply voltage for Flex
port
V
V
FLEX SR
2.97
4.5
-
4.0
V
V
3.3V pad parameters
are valid
5.0
5.5 3)
5V pad parameters are
valid
Digital supply voltage for Flash
DDP3 SR
2.97
2.6
3.3
-
3.63 4)
3.63
V
V
Flash configured in
cranking mode; Flash
read operation with
reduced performance.
Digital ground voltage
V
V
SS SR
0
-
-
V
V
Analog ground voltage for VDDM
SSM CC
-0.1
0
0.1
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Operating Conditions
Table 3-3 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
EVRSB SR 2.97 5)
Max.
Digital external supply voltage
for EVR and during Standby
mode
V
V
-
5.5
V
Voltage to ensure defined pad
states
DDPPA CC 1.3 6)
-
-
V
1) For VDD 1.08V ≤ VDD < 1.125V operation is still possible but with relaxed parameters.
2) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
3) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
4) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
5) VEVRSB supply voltage can drop down upto 2.6V during Standby mode. It is required to have a capictor of 100nF on VEVRSB
supply pin.
6) HWCFG[6] pin is latched and pull-up or tristate is activated at Port pins when VEXT has reached this level.
Limitation of Supply Voltage over Time
The maximum operation voltage for VEXT/FLEX/DDM supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-4 Example Voltage Profile
VEXT/FLEX/DDM
=
Duration [h]
5.4 V < VEXT/FLEX/DDM ≤ 5.5 V
5.15 V < VEXT/FLEX/DDM ≤ 5.4 V
4.85 V < VEXT/FLEX/DDM ≤ 5.15 V
4.6 V < VEXT/FLEX/DDM ≤ 4.85 V
4.5 V < VEXT/FLEX/DDM ≤ 4.6 V
≤ 5% of lifetime
≤ 15% of lifetime
≤ 60% of lifetime
≤ 15% of lifetime
≤ 5% of lifetime
The maximum operation voltage for VDD supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-5 Example Voltage Profile
VDD=
Duration [h]
1.325 V < VDD ≤ 1.375 V
1.275 V < VDD ≤ 1.325 V
1.225 V < VDD ≤ 1.275 V
1.175 V < VDD ≤ 1.225 V
1.125 V < VDD ≤ 1.175V
≤ 5% of lifetime
≤ 15% of lifetime
≤ 60% of lifetime
≤ 15% of lifetime
≤ 5% of lifetime
Data Sheet
293
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
3.5
5 V / 3.3 V switchable Pads
Pad classes slow GPIO and fast GPIO support both Automotive Level (AL) or TTL level (TTL) operation.
Parameters are defined for AL operation and degrade in TTL operation.
Table 3-6 PORST Pad
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
PORST pad Output current
I
PORST CC
13
-
-
-
-
mA
ns
VEXT = 2.97V; VPORST =
0.9V
Spike filter always blocked pulse tSF1 CC
duration
-
80
-
Spike filter pass-through
blocked pulse duration
t
SF2 CC
260
ns
without additional
PORST Digtial Filter
active (PORSTDF = 0).
Input hysteresis 1)
HYS CC
0.055 *
VEXT
-
-
V
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
Pull-down current 2)
I
I
PDL CC
-
-
-
-
|130|
-
µA
µA
nA
VIH; TTL (degraded,
used for CIF)
|15|
-450
VIL; TTL (degraded,
used for CIF)
Input leakage current
OZ CC
450
TJ≤150°C ; (0.1 * VEXT
)
)
< VIN < (0.9 * VEXT
)
-500
-900
-
-
500
900
nA
nA
TJ≤150°C ;else
TJ≤170°C ; (0.1 * VEXT
< VIN < (0.9 * VEXT
)
-950
1.4
-
-
950
-
nA
V
TJ≤170°C ; else
Input high voltage level
Input low voltage level
Pin capacitance
VIH SR
VIL SR
CIO CC
TTL (degraded, used
for CIF); VEXT = 2.97V
2.0
-
-
-
-
V
V
TTL; VEXT = 4.5V
0.5
TTL (degraded, used
for CIF); VEXT = 2.97V
-
-
-
0.8
3
V
TTL; VEXT = 4.5V
2
pF
in addition 2.5pF from
package to be added
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
2) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Data Sheet
294
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-7 Fast 5V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL =
2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
3.2
CL = 25pF; driver =
strong sharp edge;
from 0.2 *
VEXT/FLEX/EVRSB to 0.8 *
VEXT/FLEX/EVRSB
4+0.55*CL 4+0.75*CL 12+1.0*CL ns
driver = medium;
CL≤200pF
1.0+0.18* 2.5+0.27* 5.0+0.35* ns
driver = strong edge =
CL
CL
CL
medium; CL≤200pF
0.5+0.08* 0.5+0.11* 1.0+0.17* ns
driver = strong edge =
CL
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.09 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/E
VRSB
0.075 *
VEXT/FLEX/E
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
VRSB
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
Pull-down current 5)
-
|130|
|30|
|28|
-
-
VIL; TTL
Data Sheet
295
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-7 Fast 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input leakage current
I
OZ CC
-1100
-
1100
nA
TJ ≤ 150°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-2500
-
2500
nA
TJ ≤ 150°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-6000
-3200
-
-
6000
3200
nA
nA
TJ ≤ 150°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 150°C ; LVDS_TX
/ Fast pad type ; else
-1500
-2000
-
-
1500
2000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-4000
-
4000
nA
TJ ≤ 170°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-13500
-5100
-2500
-
-
13500
5100
nA
nA
TJ ≤ 170°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 170°C ; LVDS_TX
/ Fast pad type ; else
-
-
2500
-
nA
V
TJ ≤ 170°C ; else
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 *
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
V
V
TTL
AL
-
0.44 *
VEXT/FLEX/E
VRSB
-
-
-
0.8
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
-50
50
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
constant; AL
=
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
Data Sheet
296
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-8 Fast 3.3V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL =
2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
4.5
CL = 25pF; driver =
strong sharp edge;
from 0.2 *
VEXT/FLEX/EVRSB to 0.8 *
VEXT/FLEX/EVRSB
-
-
5
ns
CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
2+0.57*CL 5.5+0.75* 10+1.25* ns
CL CL
1.5+0.18* 1.5+0.28* 8+0.4*CL ns
CL CL
driver = medium;
CL≤200pF
driver = strong edge =
medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns
driver = strong edge =
*CL
*CL
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.055 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/E
VRSB
0.09 *
VEXT/FLEX/E
-
-
-
-
V
V
non of the neighbor
pads are used as
output; TTL
VRSB
0.055 *
VEXT/FLEX/E
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
VRSB
125
-
-
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet
297
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-8 Fast 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull-up current 4)
I
PUH CC
|17|
-
-
µA
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
VIH; TTL
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF)
Pull-down current 5)
I
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
I
OZ CC
-1100
-2500
-
-
1100
2500
nA
nA
TJ ≤ 150°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
TJ ≤ 150°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-6000
-3200
-
-
6000
3200
nA
nA
TJ ≤ 150°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 150°C ; LVDS_TX
/ Fast pad type ; else
-1500
-2000
-
-
1500
2000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-4000
-
4000
nA
TJ ≤ 170°C ; (0.1 *
V
V
EXT/FLEX) < VIN < (0.9 *
EXT/FLEX) ; LVDS_TX /
Fast pad type
-13500
-5100
-2500
-
-
-
13500
5100
2500
nA
nA
nA
TJ ≤ 170°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 170°C ; LVDS_TX
/ Fast pad type ; else
TJ ≤ 170°C ; else
Data Sheet
298
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-8 Fast 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage level
VIH SR
0.7 *
-
-
V
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
-
V
V
TTL
1.4
TTL (degraded, used
for CIF)
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VEXT/FLEX/E
VRSB
-
-
-
-
0.8
V
V
TTL
0.5
1.9
33
TTL (degraded, used
for CIF)
Input low/high voltage level
Input low threshold variation
V
V
ILH SR
ILD SR
1.0
-33
-
-
V
RGMII; no hysteresis
available
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-9 Slow 5V GPIO
Parameter
Symbol
Values
Typ.
225
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
Rise / Fall time 1) 2)
R
DSON CC
125
320
Ohm
medium driver; IOH / OL =
2mA
t
RF CC
4+0.55*CL 4+0.75*CL 12+1*CL ns
1.5+0.25* 2.5+0.40* 7+0.55*CL ns
driver = medium edge =
medium ; CL≤200pF
driver = medium edge =
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Data Sheet
fIN CC
-
-
160
MHz
299
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-9 Slow 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 3)
HYS CC
0.09 *
VEXT/FLEX/E
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
VRSB
0.075 *
VEXT/FLEX/E
-
-
V
non of the neighbor
pads are used as
output; TTL
VRSB
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
PUH CC
|30|
-
-
-
-
µA
µA
VIH;AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
|130|
VIL; AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
Pull-down current 5)
Input leakage current
I
I
PDL CC
-
-
-
-
-
|130|
µA
µA
µA
nA
VIH; AL or TTL
VIL; AL
|30|
|28|
-300
-
-
VIL; TTL
OZ CC
300
TJ ≤ 150°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-400
-600
-
-
400
600
nA
nA
TJ ≤ 150°C; else
TJ ≤ 170°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-750
-
-
750
nA
nA
TJ ≤ 170°C; else
-18000
18000
P32.0 and
P32.1;TJ≤150°C
-38000
-
-
38000
-
nA
V
P32.0 and
P32.1;TJ≤170°C
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 *
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
V
V
TTL
AL
-
0.44 *
VEXT/FLEX/E
VRSB
-
-
0.8
V
TTL
Data Sheet
300
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-9 Slow 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low threshold variation
V
ILD SR
-50
-
50
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-10 Slow 3.3V GPIO
Parameter
Symbol
Values
Typ.
225
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
Rise / Fall time 1) 2)
R
DSON CC
125
320
Ohm
medium driver; IOH / OL =
2mA
t
RF CC
2+0.57*CL 5.5+0.75* 10+1.25* ns
CL CL
driver = medium edge =
medium ; CL≤200pF
2+0.30*CL 3.5+0.50* 5+0.70*CL ns
driver = medium edge =
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.055 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/E
VRSB
0.09 *
VEXT/FLEX/E
-
-
-
-
V
V
non of the neighbor
pads are used as
output; TTL
VRSB
0.055 *
VEXT/FLEX/E
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
VRSB
125
-
-
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet
301
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-10 Slow 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull-up current 4)
I
PUH CC
|17|
-
-
µA
VIH; AL and TTL
(degraded, used for
CIF); exept VGATE1P;
except VGATE1N and
TJ > 150°C
|11|
-
-
-
-
µA
µA
VIH; TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF); exept
VGATE1P; except
VGATE1N and TJ >
150°C
Pull-down current 5)
I
I
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
OZ CC
-300
-
300
nA
TJ ≤ 150°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-400
-600
-
-
400
600
nA
nA
TJ ≤ 150°C; else
TJ ≤ 170°C; (0.1 *
VEXT/FLEX/EVRSB) < VIN <
(0.9 * VEXT/FLEX/EVRSB
)
-750
-
-
750
nA
nA
TJ ≤ 170°C; else
-18000
18000
P32.0 and
P32.1;TJ≤150°C
-38000
-
-
38000
-
nA
V
P32.0 and
P32.1;TJ≤170°C
Input high voltage level
VIH SR
0.7 *
AL
VEXT/FLEX/E
VRSB
2.0
-
-
-
-
V
V
TTL
1.4
TTL (degraded, used
for CIF)
Data Sheet
302
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-10 Slow 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VEXT/FLEX/E
VRSB
-
-
-
-
0.8
V
V
TTL
0.5
1.9
33
TTL (degraded, used
for CIF)
Input low/high voltage level
Input low threshold variation
V
V
ILH SR
ILD SR
1.0
-33
-
-
V
RGMII; no hysteresis
available
mV
max. variation of 1ms;
VEXT/FLEX/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-11 RFast 5V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL =
2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
3.2
CL = 25pF; driver =
strong sharp edge;
from 0.2 * VFLEX to 0.8 *
VFLEX
4+0.55*CL 4+0.75*CL 12+1.0*CL ns
driver = medium;
CL≤200pF
1.0+0.18* 2.5+0.27* 5.0+0.35* ns
driver = strong edge =
CL
CL
CL
medium; CL≤200pF
0.5+0.08* 0.5+0.11* 1.0+0.17* ns
driver = strong edge =
CL
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
Data Sheet
t
TX_ASYM CC -0.5
-
0.5
ns
valid for all data rates
excluding clock
tolerance
303
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-11 RFast 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
MHz
V
HYS CC
0.09 *
VFLEX
non of the neighbor
pads are used as
output; AL
0.075 *
VFLEX
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
nA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
|130|
-
Pull-down current 5)
-
|30|
|28|
-1700
-
VIL; TTL
Input leakage current
I
OZ CC
1700
TJ ≤ 150°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-2100
-3000
-
-
2100
3000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-4000
-
-
-
-
4000
nA
V
TJ ≤ 170°C ; else
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7*VFLEX
-
-
AL
2.0
-
V
TTL
AL
0.44 *
V
VFLEX
-
-
-
0.8
50
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-50
mV
max. variation of 1ms;
V
FLEX = constant; AL
-
-
2
-
3.5
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
Data Sheet
304
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-12 RFast 3.3V pad
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
8
20
30
Ohm
Ohm
Ohm
Driver = RGMII; IOH / OL
= 8mA
125
31
225
55
320
80
medium driver; IOH / OL =
2mA
strong driver; IOH / OL
=
8mA
Input Duty Cycle
Rise / Fall time 1) 2)
fD SR
tRF CC
47.5
1.6
50
-
52.5
4.5
ns
ns
ns
CL = 25pF; driver =
strong sharp edge;
from 0.2 * VFLEX to 0.8 *
VFLEX
-
-
-
-
5
1
CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
Driver = RGMII; from
20%V to 80%V;
CL=15pF
2+0.57*CL 5.5+0.75* 10+1.25* ns
CL CL
1.5+0.18* 1.5+0.28* 8+0.4*CL ns
CL CL
driver = medium;
CL≤200pF
driver = strong edge =
medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns
driver = strong edge =
*CL
*CL
CL
sharp ; CL≤200pF
Asymmetry of sending
Input frequency
t
TX_ASYM CC -0.4
-
0.4
ns
valid for all data rates
excluding clock
tolerance
fIN CC
-
-
160
MHz
Data Sheet
305
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-12 RFast 3.3V pad (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 3)
HYS CC
0.055 *
VFLEX
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
0.09 *
VFLEX
-
-
V
V
non of the neighbor
pads are used as
output; TTL
0.055 *
VFLEX
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
125
|17|
-
-
-
-
mV
µA
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
VIH; TTL
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF)
Pull-down current 5)
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
I
OZ CC
-1700
-
1700
nA
TJ ≤ 150°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-2100
-3000
-
-
2100
3000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
VFLEX) < VIN < (0.9 *
VFLEX
)
-4000
0.7*VFLEX
2.0
-
-
-
-
4000
nA
V
TJ ≤ 170°C ; else
Input high voltage level
VIH SR
-
-
-
AL
V
TTL
1.4
V
TTL (degraded, used
for CIF)
Data Sheet
306
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-12 RFast 3.3V pad (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VFLEX
-
-
-
-
0.8
0.5
V
V
TTL
TTL (degraded, used
for CIF)
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-33
-
33
mV
pF
ns
max. variation of 1ms;
VFLEX = constant; AL
-
-
2
-
3.5
100
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-13 Class S 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input hysteresis 1)
fIN CC
-
-
-
MHz
V
HYS CC
0.09 *
VDDM
non of the neighbor
pads are used as
output; AL
0.075 *
VDDM
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 2)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
Pull-down current 3)
-
|130|
|30|
|28|
-
-
VIL; TTL
Data Sheet
307
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-13 Class S 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-150
-300
Max.
150
Input leakage current
I
OZ CC
-
-
nA
nA
TJ ≤ 150°C; else
300
TJ ≤ 150°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected, or two
EDSADC channels
connected
-300
-600
-
-
300
600
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected, or two
EDSADC channels
connected
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 * VDDM
-
-
-
-
-
V
V
V
AL
2.0
-
TTL
AL
0.44 *
VDDM
-
-
-
0.8
50
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-50
mV
max. variation of 1ms;
V
DDM = constant; AL
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
3) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-14 Class S 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input frequency
fIN CC
-
-
160
MHz
Data Sheet
308
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-14 Class S 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 1)
HYS CC
0.055 *
VDDM
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
0.09 *
VDDM
-
-
V
V
non of the neighbor
pads are used as
output; TTL
0.065 *
VDDM
non of the neighbor
pads are used as
output; TTL (degraded
used for CIF)
125
|17|
-
-
-
-
mV
µA
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 2)
I
I
PUH CC
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
µA
VIH; TTL
-
-
|80|
|105|
VIL
Pull-down current 3)
PDL CC
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
I
OZ CC
-150
-300
-
-
150
300
nA
nA
TJ ≤ 150°C; else
TJ ≤ 150°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected
-300
-600
-
-
300
600
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD option
available
Input high voltage level
VIH SR
0.7 * VDDM
2.0
-
-
-
-
-
-
V
V
V
AL
TTL
1.4
TTL (degraded, used
for CIF)
Data Sheet
309
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-14 Class S 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VDDM
-
-
-
-
0.8
0.5
V
V
TTL
TTL (degraded, used
for CIF)
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-33
-
33
3
mV
pF
ns
max. variation of 1ms;
VDDM = constant; AL
-
-
2
-
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that
it suppresses switching due to external system noise.
2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
3) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-15 Class D
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
150
300 1)
Input leakage current
I
OZ CC
-150
-300 1)
-
-
nA
nA
TJ ≤ 150°C; else
TJ ≤ 150°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected, or two
EDSADC channels
connected
-300
-600 2)
-
-
300
600 2)
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD option
available, or AltRef
option available and
EDSADC channel
connected, or two
EDSADC channels
connected
Pin capacitance
CIO CC
-
2
3
pF
in addition 2.5pF from
package to be added
1) For AN11 100 nA need to be added.
2) For AN11 200 nA need to be added.
Data Sheet
310
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-16 ADC Reference Pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input leakage current for VAREF
I
OZ2 CC
-2 1)
-
2 1)
µA
TJ ≤ 150°C; VAREF
<
VDDM; for EVADC; valid
for BGA292
-7 1)
-
7 1)
µA
TJ ≤ 150°C; VAREF
≤
VDDM+50mV; for
EVADC; valid for
BGA292
-4 1)
-
-
4 1)
µA
µA
TJ ≤ 170°C; VAREF
<
VDDM; for EVADC; valid
for BGA292
-14 1)
14 1)
TJ ≤ 170°C; VAREF
≤
<
VDDM+50mV; for
EVADC; valid for
BGA292
-1 2)
-
-
-
1 2)
µA
µA
µA
TJ ≤ 150°C; VAREF
VDDM; for EVADC; valid
for BGA516
-2 2)
2 2)
TJ ≤ 170°C; VAREF
<
VDDM; for EVADC; valid
for BGA516
-3.5 2)
3.5 2)
TJ ≤ 150°C; VAREF
≤
VDDM+50mV; for
EVADC; valid for
BGA516
-7 2)
-
7 2)
µA
TJ ≤ 170°C; VAREF
≤
<
VDDM+50mV; for
EVADC; valid for
BGA516
-2 3)
-4 3)
-6 3)
-
-
-
2 3)
4 3)
6 3)
µA
µA
µA
TJ ≤ 150°C; VAREF
VDDM; for EDSADC
TJ ≤ 170°C; VAREF
<
VDDM; for EDSADC
TJ ≤ 150°C; VAREF
≤
VDDM+50mV; for
EDSADC
-12 3)
-
12 3)
µA
TJ ≤ 170°C; VAREF
≤
VDDM+50mV; for
EDSADC
1) Limit is valid for VAREF2 pin.
2) Limit is valid for VAREF2 and VAREF3 pins each.
3) Limit is valid for VAREF1 pin.
Data Sheet
311
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-17 Driver Mode Selection for Slow Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Driver Setting
X
X
X
X
0
1
Speed grade 1
Speed grade 2
medium sharp edge (sm)
medium medium edge (m)
Table 3-18 Driver Mode Selection for Fast Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Strong sharp edge (ss)
Strong medium edge (sm)
medium (m)
Reserved, do not use this combination
Table 3-19 Driver Mode Selection for RFast Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Strong sharp edge (ss)
Strong medium edge (sm)
medium (m)
RGMII function active
Data Sheet
312
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification High performance LVDS Pads
3.6
High performance LVDS Pads
This LVDS pad type is used for the high speed chip to chip communication interface of the new TC38x. It compose
out of a LVDS pad and a fast pad.
CL = 2.5 pF for all LVDS parameters.
Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
0.75 1)
Output impedance
R0 CC
-
-
Ohm
ns
Vcm = 1.0 V and 1.4 V
Rise time (20% - 80%)
t
rise20 CC
ZL = 100 Ohm ±20%
@2pF external load
Fall time (20% - 80%)
t
fall20 CC
-
-
-
-
-
-
0.75 2)
330
ns
ZL = 100 Ohm ±20%
@2pF external load
Output differential voltage 3)
V
OD CC
240
280
320
380
mV
mV
mV
mV
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=00
370
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=01
410
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=10
500
RT = 100 Ohm ± 1%;
LPCRx.VDIFFADJ=11;
Multi slave operation
Output voltage high
Output voltage low
V
V
V
OH CC
OL CC
OS CC
-
-
-
-
-
-
-
1475
1500
-
mV
mV
mV
mV
mV
mV
RT = 100 Ohm +/- 1%
VDIFFADJ=00 and 01
-
RT = 100 Ohm ± 1%
VDIFFADJ=10 and 11
925
900
1125
0
RT = 100 Ohm ± 1%
VDIFFADJ=00 and 01
-
RT = 100 Ohm +/- 1%
VDIFFADJ=10 and 11
Output offset (Common mode)
voltage
1275
1600
RT = 100 Ohm ± 1%
Input voltage range
VI SR
Driver ground potential
difference < 925 mV; RT
= 100 Ohm ±10%
0
-
-
-
2400
100
mV
mV
mV
Driver ground potential
difference < 925 mV; RT
= 100 Ohm ±20%
Input differential threshold
V
idth SR
-100
-100
Driver ground potential
difference < 900 mV;
VDIFFADJ=10 and 11
100
Driver ground potential
difference < 925 mV;
VDIFFADJ=00 and 01
Data Sheet
313
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification High performance LVDS Pads
Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Receiver differential input
impedance
Rin CC
80
-
120
Ohm
mV
VI ≤ 2400 mV
Output differential voltage Sleep VODSM CC
-5
-
20
RT = 100 Ohm ± 20%;
LPCRx.VDIFFADJ=xx
Mode 4)
Delta output impedance
dR0 SR
-
-
-
-
10
25
%
Vcm = 1.0 V and 1.4 V
Change in VOS between 0 and dVOS CC
mV
RT = 100 Ohm ±1%
1
Change in Vod between 0 and 1 dVod CC
-
-
-
25
13
mV
µs
RT = 100 Ohm ±1%
Pad set-up time
tSET_LVDS
10
CC
Duty cycle
t
duty CC
45
-
55
%
1) trise20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load.
2) tfall20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load.
3) Potential violations of the IEEE Std 1596.3 are intended for the new multislave support feature. To be compliant to IEEE Std
1596.3 LPCRx.VDIFFADJ has to be configured to 01.
4) Common Mode voltage of Tx is maintained.
Note:Driver ground potential difference is defined as driver-receiver potentital difference, that can result in a
voltage shift when comparing driver output voltage level and receiver input voltage level of a transmitted
signal.
Note:RT in table ‘LVDS - IEEE standard LVDS general purpose Link (GPL)’ is as termination resistor of the
receiver according to figure 3-5 in IEEE Std 1596.3-1996 and is represent in Figure 3-1 either by Rin or by
RT=100Ohm but not both. If RT is mentioned in column Note / Test Condition always the internal resistor Rin
in Figure 3-1 is the selected one.
default after start-up = CMOS function
Data Sheet
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TC38x AD/AE-Step
Electrical Specification High performance LVDS Pads
P
Htotal=5nH
Ctotal=3.5pF
LVDS
Cext=2pF
Rin
IN
RT=100Ohm
N
Htotal=5nH
Ctotal=3.5pF
Cext=2pF
LVDS_Input_Pad_Model.vsd
Figure 3-1 LVDS pad Input model
Data Sheet
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TC38x AD/AE-Step
Electrical Specification VADC Parameters
3.7
VADC Parameters
The accuracy of the converter results depends on the reference voltage range. The parameters in the table below
are valid for a reference voltage range of (VAREF - VAGND) >= 4.5 V. If the reference voltage range is below 4.5 V
by a factor of k (e.g. 3.3 V), the accuracy parameters increase by a factor of 1.1/k (e.g. 1.1 × 4.5 / 3.3 = 1.5).
Noise on supply voltage VDDM influences the conversion. The accuracy (error) parameters are defined for a supply
voltage ripple of below 20 mVpp up to 10 MHz (below 5 mVpp above 10 MHz).
Digital functions overlapping analog inputs influence accuracy.
The total unadjusted error (TUE) is defined without noise. The overall deviation depends on TUE and ENRMS
(depending on the noise distribution). Example: For a noise distribution of 4 sigma and ENRMS = 1.0 the additional
peak-peak noise error is ±(4 × 1.0) = 8 LSB12.
Fast compare operations are executed with 10-bit values.
The noise reduction feature improves the result by adding additional conversion steps. The conversion times,
therefore, increase accordingly (4 × tADCI + 3 × tADC for each of 1, 3, or 7 steps).
Table 3-21 VADC 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
EVADC IVR output voltage
V
DDK CC
1.15
-
1.35
V
%
V
V
V
V
Measured at low
temperature.
Deviation of IVR output voltage dVDDK CC
VDDK
Analog reference voltage 1)
-2
-
2
Based on device-
specific value
V
AREF SR
4.5
5.0
3.3
VSSM
-
VDDM
0.05
+
+
4.5 V ≤ VDDM ≤ 5.5 V
2.97
VSSM
VAGND
VDDM
0.05
2.97 V ≤ VDDM < 4.5 V
Analog reference ground
Analog input voltage range
V
V
AGND SR
AIN SR
VSSM
V
SSM and VAGND are
connected together
AIN is limited by the
VAREF
V
respective pad supply
voltage; see pin
configuration (buffer
type)
Converter reference clock
Total Unadjusted Error 2) 3)
f
ADCI SR
16
16
-4
40
20
-
53.33
26.67
4
MHz
MHz
LSB
4.5 V ≤ VDDM ≤ 5.5 V
2.97 V ≤ VDDM < 4.5 V
TUE CC
12-bit resolution for
primary/secondary
groups, 10-bit
resolution for fast
compare channels
INL Error 2)
EAINL CC
EADNL CC
-3
-1
-
-
-
-
3
LSB
LSB
LSB
LSB
DNL error 2)4)
Gain Error 2)
Offset Error 2)3)
3
EAGAIN CC -3.5
EAOFF CC -4
3.5
4
Data Sheet
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TC38x AD/AE-Step
Electrical Specification VADC Parameters
Table 3-21 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
0.8
RMS Noise 2)5) 6)
ENRMS CC
-
-
-
0.5
0.5
-
LSB
LSB
pC
Noise reduction level 3
Standard conversion
1.0
20
Reference input charge
consumption per conversion
(from VAREF
Q
CONV CC
V
AIN = 0 V (worst case),
precharging disabled
AIN = 0 V (worst case),
precharging enabled,
7) 8) 9)
)
-
-
10
pC
V
VDDM - 5% < VAREF <
VDDM + 50 mV
Switched capacitance of an
analog input
C
AINS CC
AINS CC
-
-
2.5
-
3.4
3.5
pF
pC
Input buffer disabled
Analog input charge
consumption 10)
Q
Primary groups and
fast compare channels;
VAIN = VAREF; VDDM = 5.0
V; input buffer enabled;
TJ ≤ 150°C
-
-
3.8
pC
Primary groups and
fast compare channels;
VAIN = VAREF; VDDM = 5.0
V; input buffer enabled;
TJ > 150°C
-
-
-
-
4.4
4.8
pC
pC
Secondarygroups;VAIN
= VAREF; VDDM = 5.0 V;
input buffer enabled; TJ
≤ 150 °C
Secondarygroups;VAIN
= VAREF; VDDM = 5.0 V;
input buffer enabled; TJ
> 150°C
Data Sheet
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TC38x AD/AE-Step
Electrical Specification VADC Parameters
Table 3-21 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sampling time
tS SR
100
-
-
ns
Primary group or fast
compare channel, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer disabled
300
-
-
ns
Primary group or fast
compare channel, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer enabled
500
700
200
-
-
-
-
-
-
ns
ns
ns
Secondary group, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer disabled
Secondary group, 4.5 V
≤ VDDM ≤ 5.5 V; input
buffer enabled
Primary Group or fast
compare channel, 2.97
V ≤ VDDM < 4.5 V; input
buffer disabled
400
-
-
ns
Primary group or fast
compare channel, 2.97
V ≤ VDDM < 4.5 V; input
buffer enabled
1000
1200
-
-
-
-
ns
ns
Secondary group, 2.97
V ≤ VDDM < 4.5 V; input
buffer disabled
Secondary group, 2.97
V ≤ VDDM < 4.5 V; input
buffer enabled
Sampling time for calibration
t
SCAL SR
50
-
-
ns
ns
µs
µs
µs
4.5 V ≤ VDDM ≤ 5.5 V
2.97 V ≤ VDDM < 4.5 V
100
-
-
Input buffer switch-on time
Wakeup time
t
t
BUF CC
WU CC
-
-
-
-
0.4
0.1
1.6
100
1
0.2
3
-
Fast standby mode
Slow standby mode
Broken wire detection delay
against VAREF
t
t
BWR CC
cycles Result above 80% of
full scale range, analog
input buffer disabled
Broken wire detection delay
against VAGND
BWG CC
-
100
-
cycles Result below 10% of full
scale range, analog
input buffer disabled
Converter diagnostics unit
resistance 11)
R
CSD CC
45
-
-
75
10
kOhm
Converter diagnostics voltage
accuracy
dVCSD CC
-10
%
Percentage refers to
VDDM
Data Sheet
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TC38x AD/AE-Step
Electrical Specification VADC Parameters
Table 3-21 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Resistance of the multiplexer
diagnostics pull-up device
R
MDU CC
30
-
-
-
-
-
42
kOhm 0 V ≤ VIN ≤ 0.9* VDDM
,
,
Automotive Levels
56
43
18
-
78
58
25
0.3
kOhm 0 V ≤ VIN ≤ 0.9* VDDM
TTL Levels
Resistance of the multiplexer
diagnostics pull-down device
R
MDD CC
kOhm 0.1*VDDM ≤ VIN ≤ VDDM
,
Automotive level
kOhm 0.1*VDDM ≤ VIN ≤ VDDM
,
TTL level
Resistance of the pull-down test RPDD CC
kOhm Measured at pad input
device
voltage VIN = VDDM / 2.
1) These limits apply to the standard reference input as well as to the alternate reference input.
2) Parameter depends on reference voltage range and supply ripple, see introduction.
Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
Tests are done with postcalibration disabled, after completing the startup calibration.
3) Analog inputs mapped to pads of the type SLOW influence accuracy. The values for this parameter increase by 3 LSB12.
4) Monotonic characteristic, no missing codes when calibrated.
5) Parameter ENRMS refers to a 1 sigma distribution.
6) Analog inputs mapped to pads of the type SLOW the RMS noise (ENRMS) can be up to 2 LSB 12 (soft switching for DC/DC
enabled).
7) For reduced reference voltages VAREF < 3.375V, the consumed charge QCONV is reduced by the factor of k2 = VAREF [V]
/ 3.375. For reduced reference voltages 4.5V < VAREF ≤ 3.375V, QCONV is not reduced.
8) Maximum charge increases by 15 pC when BWD (Broken Wire Detection) is active.
9) Fast compare channels only consume 1/3 of the charge for a primary/secondary group.
10) For analog inputs with overlaid digital GPIOs or with PDD function this value increases by 1 pC.
11) Use a sample time of at least 1.1 µs to enable proper settling of the test voltage.
Figure 3-2 Equivalent Circuitry for Analog Inputs
Data Sheet
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TC38x AD/AE-Step
Electrical Specification DSADC Parameters
3.8
DSADC Parameters
The DSADC parameters are valid only for voltage range 4.5 V <= VDDM <= 5.5 V.
These parameters describe the product properties and do not include external circuitry. The values are valid for
junction temperatures TJ <= 150°C if not defined explicitly.
Calibration is specified for gain factors 1 and 2, calibrated values refer to these settings.
The signal-noise ratio (SNR) is specified for differential inputs. For single ended operation the resulting signal-
noise ratio is reduced by 6 dB. For quasi-differential mode (i.e. using VCM) it is reduced by 6 dB for gain = 1 and
by 3 dB for gain= 2.
Table 3-22 DSADC 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Common mode voltage bias
resistance
R
V
V
BIAS CC
AREF SR
AGND SR
105
130
155
kOhm On-chip variation ≤
±2.5%.
Positive reference voltage
Reference ground voltage
Reference load current
4.5
-
-
VDDM
0.05
+
V
VSSM
VSSM
V
VSSM and VAGND are
connected together
I
REF CC
-
-
10
-
12
14
µA
µA
Per modulator
Per modulator,
TJ>150°C
Common mode voltage
accuracy 1)
dVCM CC
DSIN SR
-100
-
-
100
mV
V
Deviation from selected
voltage
Analog input voltage range
V
VSSM
2 * VDDM
Differential;VDSxP -
VDSxN
VSSM
-
VDDM
V
Single ended
Input current 2)
I
RMS CC
7
10
13
µA
Exact value (±1%)
available in UCB; valid
for gain = 1 and fMOD
=
26.7 MHz
On-chip modulator clock
frequency
Gain error 3) 4)
f
MOD SR
16
-
40
MHz
%
EDGAIN CC -0.2 5)
±0.15)
0.2 5)
TJ≤150°C; Target,
calibrated, VAREF
constant after
calibration; fMOD
=
26.67 MHz
-
±0.25
-
%
TJ>150°C; VAREF
constant after
calibration; fMOD
=
26.67 MHz
-1
-
-
1
%
%
Calibrated once; fMOD =
26.67 MHz
-2.5
2.5
Uncalibrated; fMOD =
26.67 MHz
Data Sheet
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TC38x AD/AE-Step
Electrical Specification DSADC Parameters
Table 3-22 DSADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DC offset error 3)
EDOFF CC -5 5)
-
-
-
-
-
-
-
5 5)
mV
mV
mV
dB
dB
dB
dB
Calibrated; fMOD =
26.67 MHz
-10
-30
10
30
-
Calibrated once; fMOD =
26.67 MHz
Uncalibrated; fMOD
26.67 MHz
=
Signal-Noise Ratio for
differential input signals 2)6) 7)
SNR CC
80
78
74
-
TJ≤150°C; fPB = 30 kHz;
MOD = 26.67 MHz
TJ≤150°C; fPB = 50 kHz;
MOD = 26.67 MHz
f
-
f
-
TJ≤150°C; fPB = 100
kHz; fMOD = 26.67 MHz
Signal-Noise Ratio degradation DSNR CC
Spurious-free dynamic range 3) SFDR CC
3
TJ>150°C; Resulting
Signal-Noise Ratio
value is SNR - DSNR
60
-
-
-
dB
fMOD = 26.67 MHz
Output sampling rate
fD CC
3.906
300
kHz
16 MHz / 4096, without
integrator
Pass band
f
PB CC
1.302
1.302
-
-
100
10
kHz
kHz
Output data rate: fD =
fPB * 3; without
integrator
Output data rate: fD =
fPB * 6; without
integrator
Pass band ripple
dfPB CC
SBA CC
-0.08
40
-
-
-
-
-
-
-
0.08
dB
dB
dB
dB
dB
dB
dB
FIR filters enabled
0.5 fD ... 1.0 fD
1.0 fD ... 1.5 fD
1.5 fD ... 2.0 fD
2.0 fD ... 2.5 fD
2.5 fD ... OSR/2 fD
10-5 fD, offset
compensation filter
enabled
Stop band attenuation
-
-
-
-
-
-
45
50
55
60
DC compensation factor
Modulator settling time
DCF CC
-3
(FCFGMx.OCEN =
001B)
t
MSET CC
-
-
20
µs
After switching on,
voltage regulator
already running
1) On pins with overlaid GPIO function the max. limit increases by up to 25 mV due to leakage current for TJ > 150°C.
2) For detailed information, refer to the User Manual chapter.
3) This parameter is valid within the defined range of fMOD
.
4) Gain mismatch error between the different EDSADC channels is within ±0.5% if they have the same calibration strategy
Data Sheet
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TC38x AD/AE-Step
Electrical Specification DSADC Parameters
5) Recalibration needed in case of a temperature change >20ºC
6) These values are valid for an analog gain factor of 1. Subtract 3 dB for each higher gain factor.
7) For single ended input signals and gain1, the SNR is reduced by 6 dB.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification MHz Oscillator
3.9
MHz Oscillator
OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 16 MHz to 40 MHz crystals external
outside of the device. Support of ceramic resonators is also provided.
Table 3-23 OSC_XTAL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-70
4
Max.
70
Input current at XTAL1
Oscillator frequency
I
IX1 CC
-
-
µA
VIN>0V ; VIN<VEXT
f
OSC SR
40
MHz
Direct Input Mode
selected, if shaper is
not bypassed
16
-
-
-
-
40
MHz
ms
External Crystal Mode
selected
Oscillator start-up time
t
OSCS CC
-
3 1)
20MHz ≤ fOSC and 8pF
load capacitance
Input voltage at XTAL1 2)
VIX SR
PPX SR
-0.7
V
EXT + 0.5 V
EXT + 1.0 V
If shaper is not
bypassed
Input amplitude (peak to peak)
at XTAL1
V
0.3*VEXT
V
If shaper is not
bypassed; fOSC
25MHz
>
≤
0.35*VEXT
-
VEXT + 1.0 V
If shaper is not
bypassed; fOSC
25MHz
Internal load capacitor
Internal load capacitor
Internal load capacitor
Internal load capacitor
C
C
C
C
C
C
L0 CC
1.30
3.05
7.85
12.05
1.15
-
1.40
3.35
8.70
13.35
1.20
2.5
1.55
3.70
9.55
14.65
1.25
4
pF
pF
pF
pF
pF
pF
enabled via bit
OSCCON.CAP0EN
L1 CC
enabled via bit
OSCCON.CAP1EN
L2 CC
enabled via bit
OSCCON.CAP2EN
L3 CC
enabled via bit
OSCCON.CAP3EN
Internal load stray capacitor
between XTAL1 and XTAL2
XINTS CC
XTAL1 CC
Internal load stray capacitor
between XTAL1 and ground
Duty cycle at XTAL1 3)
Absolute RMS jitter at XTAL1 3)
Slew rate at XTAL1 3)
DCX1 SR
ABSX1 SR
35
-
-
-
-
65
28
-
%
VXTAL1 = 0.5*VPPX
J
ps
10 KHz to fOSC/2
SRXTAL1 SR 0.3
V/ns
Maximum 30%
difference between
rising and falling slew
rate
1) tOSCS is defined from the moment when the Oscillator Mode is set to External Crystal Mode until the oscillations reach an
amplitude at XTAL1 of 0.3 * VEXT.
This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.
2) For Supply (VEXT < 5.3V VIX) min could be down to -0.9V. For XTAL1 an input level down to -0.9V will not cause a damage or
a reliability problem operating with an external crystal.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification MHz Oscillator
3) Square wave input signal for XTAL1.
Note:It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Back-up Clock
3.10
Back-up Clock
The back-up clock provides an alternative clock source.
Table 3-24 Back-up Clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
BACKUT CC 70
Max.
Back-up clock accuracy before
trimming
f
f
f
100
100
70
130
MHz
MHz
kHz
VEXT≥2.97V
VEXT≥2.97V
VEXT≥2.97V
Back-up clock accuracy after
trimming 1)
BACKT CC
98
102
Standby clock
SB CC
25
110
1) A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for
temperature and voltage drifts up to temperatures of 125 celcius
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Temperature Sensor
3.11
Temperature Sensor
Table 3-25 DTS PMS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Measurement time for each
conversion 1)
tM CC
-
-
2.7
ms
°C
Measured from cold
power-on reset release
Calibration reference accuracy
T
CALACC CC -1
-
1
calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature
range
T
T
NL CC
SR SR
-2
-
-
2
°C
°C
TCALACC has to be
added in addition
DTS temperature range
-40
170
1) After warm reset tM is not restarted and is measured from last conversion.
Table 3-26 DTS Core
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Measurement time for each
conversion 1)
tM CC
-
-
2.7
ms
°C
Measured from cold
power-on reset release
Temperature difference
between on chip temperature
sensors
ΔT CC
-3
-
3
2
Calibration reference accuracy
T
CALACC CC -2
-
°C
calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature
range
T
T
NL CC
SR SR
-2
-
-
2
°C
°C
T
CALACC has to be
added in addition
DTS temperature range
-40
170
1) After warm reset tM is not restarted and is measured from last conversion.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Current
3.12
Power Supply Current
The total power supply current defined below consists of leakage and switching components.
Application relevant values are typically lower than those given in the following table and depend on the customer's
system operating conditions (e.g. thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
The real (realistic) power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
SRI = fCPUx = 300 MHz
GTM = 200 MHz
SPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz
V
V
V
DD = 1.275 V
DDP3/FLEX = 3.366 V
EXT / EVRSB = VDDM = 5.1 V
all cores are active including two lockstep cores
the following peripherals are inactive: HSM, HSCT, Ethernet, PSI5, I2C, FCE, and MTU
Table 3-27 Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
1100
840
∑ Sum of IDD core and
peripheral supply currents (incl.
I
I
DDRAIL CC
-
-
-
-
mA
mA
max power pattern
real power pattern
I
I
DDPORST+ ∑ IDDCx0+ ∑ IDDCxx
DDGTM+IDDSB
DD core current during active
+
)
I
DDPORST CC -
-
-
-
-
-
160
290
350
380
50
mA
mA
mA
mA
mA
V
DD = 1.275V;
TJ=125°C
DD = 1.275V;
TJ=150°C
DD = 1.275V;
TJ=160°C
DD = 1.275V;
power-on reset (PORST pin
held low). Leakage current of
core domain. 1)
-
V
-
-
V
V
TJ=165°C
∑ Sum of IDDP3 3.3 V supply
currents
I
DDP3RAIL CC -
max power pattern incl.
Flash read current and
Dflash programming
current.
-
-
40 2)
mA
real power pattern incl.
Flash read current and
Dflash programming
current.
∑ Sum of external IEXT supply
currents (incl.
I
EXTRAIL CC
-
-
-
-
56
50
mA
mA
max power pattern
real power pattern
I
EXTFLEX+IEVRSB+IEXTLVDS)
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Current
Table 3-27 Current Consumption (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
EXTFLEX CC -
Max.
18 3)
I
I
EXT and IFLEX supply current
I
I
-
mA
real power pattern with
port activity absent;
PORST output inactive.
EVRSB supply current 1)
EVRSB CC
-
-
8
mA
real power pattern;
PMS/EVR module
current considered
without SCR and
Standby RAM during
RUN mode.
∑ Sum of external IDDM supply
currents (incl.
I
I
DDM CC
-
-
48
mA
real power pattern; sum
of currents of EDSADC
and EVADC modules
I
DDMEVADC+IDDMEDSADC
∑ Sum of all currents (incl.
EXTRAIL+IDDMRAIL+IDDx3RAIL+IDD)
∑ Sum of all currents with DC- IDDTOTDC3
)
DDTOT CC
-
-
-
-
978
580
mA
mA
real power pattern;
TJ=150°C
I
real power pattern;
EVRC reset settings
with 72% efficiency;
4)
DC EVRC regulator active
CC
VEXT = 3.3V; TJ=150°C
∑ Sum of all currents with DC- IDDTOTDC5
-
-
-
-
440
27
mA
mA
real power pattern;
EVRC reset settings
with 72% efficiency;
4)
DC EVRC regulator active
CC
VEXT = 5V; TJ=150°C
∑ Sum of all currents (SLEEP
mode) 1)
I
I
SLEEP CC
All CPUs in idle, All
peripherals in sleep,
fSRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C
∑ Sum of all currents
STANDBY CC -
-
130 6)
µA
32 kB Standby RAM
block active. SCR
inactive. Power to
(STANDBY mode) drawn at
V
EVRSB supply pin 5)
remaining domains
switched off. TJ = 25°C;
VEVRSB = 5V
Maximum power dissipation 7)
PD SR
-
-
-
-
2400
1700
mW
mW
max power pattern
real power pattern
1) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
2) Realistic Pflash read pattern with 50% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common
decoupling capacitor of atleast 100nF for (VDDP3) is used. Continuous Dflash programming in burst mode with 3.3 V supply and
realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective
programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to 45 mA / 20
ns
which are handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply dimensioning
and not for thermal considerations.
3) The current consumption includes only minimal port activity.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Current
4) The total current drawn from external regulator is estimated with 72% EVRC SMPS regulator efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and
IDDM.
5) The same current limits apply also for the other power pattern.
6) ∑ Sum of all currents during RUN mode at VEVRSB supply pin is less than (IEVRSB + 4 mA Standby RAM current + ISCRSB
if SCR active). ∑ It is recommended to have atleast 100 nF decoupling capacitor at this pin. 32kB of Standby SRAM
contributes less than 10uA to ISTANDBY current.
7) The values are only valid if all supplies are applied from external and do not contain the power losses of EVR33 and EVRC.
Table 3-28 Module Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DDP3 supply current for
IDDP3PROG
CC
-
-
-
-
-
25
mA
Pflash 3.3V
programming of a Pflash or
Dflash bank 1)
programming current
adder when using
external 3.3V supply.
-
9 2)
mA
mA
mA
Pflash 3.3V
programming current
adder when using
external 5V supply.
I
EXT supply current added by
I
EXTLVDS CC -
9
real power pattern; 6
pairs of LVDS pins
active with receive
function
LVDS pads in LVDS mode 1)
-
24
real power pattern; 6
pairs of LVDS pins
active with transmit
function
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Current
Table 3-28 Module Current Consumption (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of external IDDM supply
currents (incl.
I
DDM CC
-
-
32
mA
real power pattern;
current for EDSADC
modules only and
EVADC modules are
inactive; 8 EDSADC
channels active
I
DDMEVADC+IDDMEDSADC)
continuously.
-
-
45 3)
mA
max power pattern;
current for EDSADC
modules only and
EVADC modules are
inactive; all EDSADC
channels active
continuously.
-
-
-
-
16
mA
mA
real power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; 12 EVADC
modules active.
20 4)
max power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; all EVADC
modules active.
I
DDP3 supply current for erasing IDDP3ERASE
-
-
-
-
25
mA
mA
Pflash 3.3V erasing
current adder when
using external 3.3V
supply.
of a Pflash or Dflash bank
CC
SCR 8-bit Standby Controller
current incl. PMS in STANDBY
Mode drawn at VEVRSB supply
pin
I
SCRSB CC
7 5)
SCR power pattern incl.
PMS current
consumption with fback
clock active; fSYS_SCR
20MHz; TJ=150°C
=
-
-
0.150
-
mA
mA
SCR power pattern incl.
PMS current
consumption with fback
inactive; fSYS_SCR =
70kHz; TJ=25°C
SCR 8-bit Standby Controller
CPU in IDLE mode 6)
I
SCRIDLE CC
-
3.5
real power pattern.
CPU set into idle mode.
1) The same current limits apply also for the other power pattern.
2) During Pflash programming at 5V, additional 3 mA is drawn at VEXT supply rail.
3) A single DS channel instance consumes 4 mA.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Current
4) A single VADC unit consumes 1.3 mA.
5) If SCR ADCOMP is activated, an additional 0.6 mA adder is to be considered.
6) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
Table 3-29 Module Core Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DD core current of CPUx main
I
I
DDCx0 CC
-
-
-
-
-
70
mA
mA
mA
mA
max power pattern;
IPC=1.2
core with CPUx lockstep core
inactive
-
-
-
45
real power pattern;
IPC=0.6
I
DD core current of CPUx main
DDCxx CC
IDDCx0
50
+
+
max power pattern;
IPC=1.2
core with CPUx lockstep core
active
IDDCx0
40
real power pattern;
IPC=0.6
I
DD core current added by GTM IDDGTM CC
-
-
-
-
125
100
mA
mA
max power pattern
real power pattern;
TIMx, TOMx, ATOMx ,
MCSx active. 3 clusters
at 200 MHz.
-
-
-
50
mA
mA
TIMx, TOMx active at
100MHz. ATOMx ,
MCSx, DPLL inactive. 2
clusters at 100 MHz.
I
I
DD core current added by HSM IDDHSM CC
DD core dynamic current added IDDLBIST CC
-
-
20 1)
max power pattern;
HSM running at
100MHz.
-
-
80 2)
200
mA
mA
LBIST Configuration A;
1.2V ≤ VDD
by LBIST
DD core dynamic current added IDDMBIST CC -
by MBIST
I
fMBIST = 300MHz;
tMBIST < 6ms. MTU
Ganging procedure for
SRAM test and
initialization; VDD =
1.375V.
1) The current consumption includes basic HSM activity incl. AES module.
2) LBIST is executed either during start-up phase or can be triggered by application software. Secondary voltage monitors are
inactive during the LBIST execution time (tLBIST).
During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static
accuracy.
If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit.
3.12.1
Calculating the 1.25 V Current Consumption
The current consumption of the 1.25 V rail is composed of two parts:
•
•
Static current consumption
Dynamic current consumption
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
The static current consumption is related to the device temperature TJ and the dynamic current consumption
depends on the configured clocking frequencies and the software application executed. These two parts need to
be added in order to get the rail current consumption.
(3.1)
mA
0, 02273 × T
--------
C
I
= 4, 7777
× e
[C]
J
0
(3.2)
mA
--------
0, 02114 × T
I
= 11, 3778
× e
[C]
J
0
C
Equation (3.1) defines the typical static current consumption and Equation (3.2) defines the maximum static
current consumption. Both functions are valid for VDD = 1.275 V.
3.13
Power Supply Infrastructure and Supply Start-up
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1
Supply Ramp-up and Ramp-down Behavior
Start-up slew rates for supply rails shall comply to SR (see Table 3-33 Supply Ramp).
3.13.1.1 Single Supply mode (a)
VEXT (externally supplied)
0
1
2
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDD
(internally generated
by EVRC)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
EVRC_tSTR
0 V
VDDP3
(internally generated
by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVR33_tSTR
0 V
tBP (incl. tEVRstartup)
T3
T0
T1
T2
T4
User Code Execution
fCPU0=100MHz default
on firmware exit
T5
EVRC & EVR33 Ramp-up
Phase
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_2 v 0.3
Figure 3-3 Single Supply mode (a) - VEXT (5 V) single supply
VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal
regulators.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
•
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited during the basic
infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling
time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the
maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the
specification.
Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware
start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-3 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started .The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated.
PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate
the respective voltages though PORST is asserted and the device is in reset state. The generated voltage
follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up.
PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU.
Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet
parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.2 Single Supply mode (e)
0
1
2
3
4
5
VEXT/VDDP3
(externally supplied)
LVD Reset release
HWCFG[1,2] latch
3.63 V
3.30 V
VRST5/
VRST33 Primary cold PORST Reset Threshold
VLVDRST5
LVD Reset Threshold
VDDPPA
HWCFG[6] latch
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDD (internally generated
by EVRC)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVRC is started with a delay after
VLVDRST5 level is reached at VEXT &
EVRC_tSTR
VLVDRSTC level is reached at VDDPD
0 V
tBP (incl. tEVRstartup)
T3
T0
T2
T4
User Code Execution
fCPU0=100MHz default
on firmware exit
T5
T1
EVRC Ramp-up
Phase
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_4 v 0.3
Figure 3-4 Single Supply mode (e) - (VEXT & VDDP3) 3.3 V single supply
VEXT = VDDP3 = 3.3 V single supply mode. VDD is generated internally by the EVRC regulator.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet
parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual
waveform may not represent the specification.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-4 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started .The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVRC regulator is initiated. PORST (input)
does not have any affect on EVRC output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC regulator has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.3 External Supply mode (d)
VEXT (externally supplied)
0
1
2
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDDP3 (internally generated
by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after
VLVDRST5 level is reached at VEXT &
EVR33_tSTR
VLVDRSTC level is reached at VDDPD
0 V
tBP (incl. tEVRstartup)
T3
T1
T0
T2
T4
User Code Execution
fCPU0=100MHz default
on firmware exit
T5
Basic Supply & Clock
Infrastructure
EVR33 Ramp-up Phase
Firmware Execution
Power Ramp-down phase
Startup_Diag_1 v 0.3
Figure 3-5 External Supply mode (d) - VEXT and VDD externally supplied
VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator.
•
External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is
defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. If VDD voltage
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
rail is ramped up before VEXT; VDD supply overshoots during start-up shall be limited within the operational
voltage range.
•
The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-5 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVR33 regulator is initiated. PORST (input)
does not have any affect on EVR33 output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVR33 regulators has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.4 External Supply mode (h)
VEXT (externally supplied)
0
1
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
VDDP3
(externally supplied)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
tPOA time to ensure adequate time between reset releases
PORST (input driven by external regulator)
PORST (output driven by PMS)
tBP
T3
T0
T1
T4
T5
User Code Execution
fCPU0=100MHz default
on firmware exit
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_3 v 0.4
Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied
All supplies, namely VEXT, VDDP3 & VDD are externally supplied.
•
External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The
slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails.
If smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall
be limited within the operational voltage ranges of the respective rails.
Data Sheet
339
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TC38x AD/AE-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
•
The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-6 is enumerated below
–
T1 up to T3 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
–
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. PORST (output) is de-asserted and HWCFG[3:5] pins are
latched on PORST rising edge by SCU. Firmware execution is initiated.
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided
supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds.
Data Sheet
340
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TC38x AD/AE-Step
Electrical Specification Reset Timing
3.14
Reset Timing
Table 3-30 Reset
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Application Reset Boot Time
System Reset Boot Time
tB CC
-
-
400
µs
operating with max.
frequencies, with valid
BMI header
t
BS CC
-
-
-
1.1
3.1
ms
ms
RAM initialization and
HSM boot time are not
included, with valid BMI
header
Cold Power on Reset Boot Time tBP CC
-
dVEXT/dT=1V/ms.
VEXT>VLVDRST5.
Boot time after Cold
PORST including EVR
ramp-up and Firmware
execution time; RAM
initialization and HSM
boot time are not
1)
included.
-
-
-
1.6
ms
Firmware execution
time after PORST
release without EVR
ramp-up; RAM
initialization and HSM
boot time is not
included
Minimum cold PORST reset
hold time in case of power fail
event issued by EVR primary
monitors
t
EVRPOR CC 10 2)
-
µs
PMS Infrastructure, EVRC and tEVRstartup
EVR33 overall start-up time till CC
cold PORST reset release
-
-
-
1
-
ms
ms
dV/dT=1V/ms. EVRC
and EVR33 active
Minimum PORST active hold
time externally after power
supplies are stable at operating
levels after start-up
t
POA SR
1 3)
Configurable PORST digital
filter delay in addition to analog
pad filter delay
t
PORSTDF CC 600
-
1200
ns
Warm Reset Sequencing Delay tWARMRSTSEQ
-
-
-
180
-
µs
ns
CC
HWCFG pins hold time from
ESR0 rising edge
t
HDH CC
16 / fSPB
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Reset Timing
Table 3-30 Reset (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
HWCFG pins setup time to
ESR0 rising edge
t
HDS CC
0
-
-
-
-
-
-
-
-
ns
s
Ports inactive after ESR0 reset tPI CC
active
8000/fBAC
18000/fBA
KT
CKT
Ports inactive after PORST
reset active
t
t
t
t
PIP CC
POH SR
POS SR
BWP CC
-
150
ns
ns
ns
ms
ms
Hold time from PORST rising
edge
150
-
Setup time to PORST rising
edge
0
-
-
Warm PORST reset boot time
1.3
6
without RAM
initalization
LBIST execution time extending tLBIST CC
-
LBIST Configuration A;
the boot time
1.2V ≤ VDD
SCR reset boot time
t
SCR CC
-
-
-
-
5
µs
µs
µs
User Mode 0
User Mode 1
-
16
-
13.3
WDT double bit ECC,
soft reset
Minimum external supplies hold tSUPHOLD CC -
-
250
µs
external supplies are
time after warm reset assertion
VEVRSB, VEXT, VFLEX
,
VDDM, VDDP3 and VDD
1) RAM initialization add 500µs in addition.
2) Cold PORST reset is driven by uC and maintained in an extended voltage range between VDDPPA limit and absolute
maximum rating VEXT/VEVRSB voltage limits.
3) The reset release on supply ramp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above
the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple consecutive
cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification Reset Timing
VDDPPA
VDDPPA
VDDP
VDD
VDDPR
tPOA
tPOA
Warm
PORST
ESR0
Cold
t PI
Programmed
tPI
tPIP
Tristate Z / pullup H
Programmed
Z / H
Z / H
Programmed
Pads
Pad-
state
undefined
Pad-
state
undefined
tPOS
tPOS
tPOH
tPOH
TRST
TESTMODE
tHDH
tHDH
tHDA
tHDH
config
tHDA
HWCFG
power -on config
config
reset_beh_aurix
Figure 3-7 Power, Pad and Reset Timing
Data Sheet
343
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TC38x AD/AE-Step
Electrical Specification PMS
3.15
PMS
Table 3-31 EVR33 LDO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
5.50
5.50
Input voltage range
VIN SR
3.60 1)
2.97 2)
-
-
V
V
Normal RUN mode
Low voltage cranking
mode
Output voltage operational
range including load/line
regulation and aging 3)
V
V
OUT CC
2.97
2.60
3.3
3.3
3.63
3.63
V
V
Normal RUN mode
Low voltage cranking
mode; IDDP3=50mA
Output VDDx3 static voltage
accuracy after trimming and
aging without dynamic load/line
regulation.
OUTT CC
3.225
2.78
3.3
3.3
3.375
3.375
V
V
Normal RUN mode
Low voltage cranking
mode; IDDP3=50mA
Output buffer capacitance on
VOUT
C
C
OUT SR
1.45
2.2
3
µF
Output buffer capacitor ESR
OUTESR SR -
60 5)
-
-
100 4)
-
mOhm f > 0.5MHz; f < 10MHz
Maximum output current of the
regulator
I
MAX CC
mA
Normal RUN mode
Startup time
External VIN supply ramp 6)
t
STR CC
-
500
1000
-
µs
Normal RUN mode
dVin/dt SR -
ΔVOUTTC CC -
1
-
V/ms
mV
Ripple on Output Voltage
33
V
EXT ≥ 2.97V ; VEXT
5.5V ; IOUTTC ≥ 10mA ;
OUTTC ≤ 60mA;
≤
I
ΔVOUTTC = (peak to
peak ripple / 2)
Load step response 7)
dVout/dIout -165
CC
-
-
-
-
-
mV
mV
mV
mV
Normal RUN mode;
dI=10 to 60mA;
dt=20ns; Tsettle=20us
-
165
-
Normal RUN mode;
dI=60 to 10mA;
dt=20ns; Tsettle=20us
-180
-
Low voltage cranking
mode; dI=10 to 50 mA;
dt=20ns; Tsettle=20us
180
Low voltage cranking
mode; dI=50 to 10mA;
dt=20ns; Tsettle=20us
Data Sheet
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification PMS
Table 3-31 EVR33 LDO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Line step response
dVout/dVin
CC
-
-
40
mV
dVin/dT=1V/ms; dV=
3.6 to 5V; IMAX=60mA;
ΔVOUTTC is included
-40
-
-
mV
dVin/dT=1V/ms; dV= 5
to 3.6V; IMAX=60mA;
ΔVOUTTC is included
-
-
-
280
-
mV
mV
dVin/dT=50V/ms; dV=
3.6 to 5V; IMAX=60mA
-165
dVin/dT=50V/ms; dV=
5 to 3.6V; IMAX=60mA
1) A maximum pass device dropout voltage of 300mV is included in the minimum input voltage to ensure optimal pass device
performance during normal operation.
2) VEXT Input voltage drop up to 2.97V leading to VDDP3 output voltage drop upto 2.6V can be tolerated if Flash is switched
before to low performance mode.
3) No external inductive load permissible if EVR33 is used.
4) It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
An additional decoupling capacitor of 100nF shall be located close to the pin before Cout.
5) IMAX is limited to 40 mA incase of Low voltage mode (cranking case) with on chip pass devices. In case EVR33 is not used,
Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during power
sequencing 3.3V is supplied before 5V by external regulator.
6) EVR is robust against residual voltage ramp-up starting between 0 - 2.97 V. A VEXT voltage ramp range between 0.5V/min
upto 120V/ms is covered in robustness validation. The generated voltage itself follows a soft ramp-up over the tSTR time to
avoid overshoots.
7) Settling time is defined until output voltage is within +-1% of the mean(VOUTT) of the individual device.
Table 3-32 Supply Monitors
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Primary Undervoltage Reset
threshold for VDDP3 before
trimming 1)
V
V
RST33 CC
-
-
3.00
V
by reset release before
EVR trimming on
supply ramp-up
Primary undervoltage reset
threshold for VDD before
trimming
RSTC CC
-
-
1.138
V
by reset release before
trimming on supply
ramp-up including 2
LSB voltage Hysteresis
V
EXT primary undervoltage
VEXTPRIUV
2.86
2.92
2.90
1.105
2.97
2.97
1.125
V
V
V
VEXT = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after trimming CC
2)
VDDP3 primary undervoltage
VDDP3PRIUV 2.86 3)
VDDP3 = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after trimming CC
2)
VDD primary undervoltage
V
DDPRIUV CC 1.08 3)
VDD = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after trimming
2)
Data Sheet
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TC38x AD/AE-Step
Electrical Specification PMS
Table 3-32 Supply Monitors (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
EVR primary monitor
measurement latency for a new
supply value
t
PRIUV CC
-
-
300
ns
The supply ramp / line
jump slope is limited to
50V/ms for VEXT, VDDP3
and VDD rails.
V
EXT, VDDM & VEVRSB secondary VEXTMON CC 3.2
3.3
3.4
4.7
5.5
5.1
V
V
V
V
SWDxxVAL,
supply monitor accuracy after
trimming 4) 5)
VDDMxxVAL &
SBxxVAL monitoring
threshold=3.3V=90h(O
V,UV).
EVRMONFILT.SWDFI
L=1.
4.5
5.3
4.9
4.6
5.4
5.0
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=4.6V=C8h(U
V)/C9h(OV).
EVRMONFILT.SWDFI
L=1
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5.4V=EAh(U
V)/ECh(OV).
EVRMONFILT.SWDFI
L=1
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5V=D9h(UV)
/DAh(OV).
EVRMONFILT.SWDFI
L=1
Data Sheet
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification PMS
Table 3-32 Supply Monitors (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
DDP3 secondary supply monitor VDDP3MON
2.97
3.035
3.30
3.565
1.15
1.25
1.35
3.1
V
EVR33xxVAL
monitoring
threshold=3.035V=CBh
(UV)/CCh(OV).
EVRMONFILT.EVR33
FIL = 3.
accuracy after trimming 5)
CC
3.235
3.365
3.63
V
V
V
V
V
EVR33xxVAL
monitoring
threshold=3.3V=DDh(
OV,UV).
EVRMONFILT.EVR33
FIL = 3.
3.5
EVR33xxVAL
monitoring
threshold=3.565V=EEh
(UV)/EFh(OV).
EVRMONFILT.EVR33
FIL = 3.
VDD & VDDPD secondary supply
V
DDMON CC 1.125
1.175
1.275
1.375
EVRCxxVAL &
monitor accuracy after trimming
PRExxVAL monitoring
threshold=1.15V=C7h(
UV)/C8h(OV).
EVRMONFILT.EVRCFI
L = 1.
5)
1.225
EVRCxxVAL &
PRExxVAL monitoring
threshold=1.25V=D9h(
OV,UV).
EVRMONFILT.EVRCFI
L = 1.
1.325
EVRCxxVAL &
PRExxVAL monitoring
threshold=1.35V=EAh(
UV)/EBh(OV).
EVRMONFILT.EVRCFI
L = 1.
V
EXT LVD Primary undervoltage VLVDRST5 CC 2.3
-
-
-
-
2.72
2.75
2.47
2.5
V
V
V
V
Power-down
Power-up
reset Monitor threshold
2.4
VEVRSB LVD Primary
VLVDRSTSB
CC
2.18
2.21
Power-down
Power-up
undervoltage reset Monitor
threshold
VEXT and VEVRSB PBIST primary VPBIST5 CC 5.63
-
-
V
overvoltage Monitor threshold
Data Sheet
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TC38x AD/AE-Step
Electrical Specification PMS
Table 3-32 Supply Monitors (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Primary undervoltage reset
threshold for VEXT before
trimming
V
RST5 CC
-
-
3.0
V
by last cold PORST
release on supply
ramp-up including
voltage hysteresis.
EVR secondary monitor
measurement latency for all 6
supply rails
t
MON CC
-
-
3.2
µs
HPOSC and SHPBG
bandgap trimmed.
Filter inactive.
1) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold and
by a voltage hysteresis of 1.5% above the undervoltage reset limit. These mechanisms serve as hysteresis to avoid multiple
consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. The
reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply is provided
externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin.
2) The monitor tolerances constitute the inherent variation of the band gap and ADC over process, voltage and temperature
operational ranges. The VxxPRIUV parameters are device individually tested in production with +-1% tolerance about the
VxxPRIUV limits. All voltages are measured on pins.
3) VRSTxx parameters are relevant only for the first cold PORST release. Later the reset levels are trimmed by the Firmware and
reflected as VxxPRIUV parameters before device is used with full performance. The cold PORST is released with a voltage
hysteresis on all the primary monitors to avoid consecutive PORST toggling behavior.
4) In case the application is using 3.3V single supply (Single Supply mode (e), i.e. VEXT and VDDP3 are shorted together), it is
recommended to use secondary supply monitoring on channel VDDP3, because of the better accuracy of parameter
VDDP3MON.
5) To monitor voltage level not provided in conditions the values for OV and UV thresholds can be generated by a linear
interpolation or extrapolation based on the given points.
Table 3-33 Supply Ramp
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
External VEXT & VEVRSB supply dVEXT/dt
8.3E-6
1
100
V/ms
ramp-up and ramp-down slope SR
1) 2) 3)
External VDDP3 supply ramp-up dVDDP3/dt 8.3E-6
1
1
1
100
100
100
V/ms
V/ms
V/ms
and ramp-down slope 1)3)
SR
External VDD supply ramp-up
dVDD/dt
SR
8.3E-6
and ramp-down slope 1)3)
External VDDM supply ramp-up dVDDM/dt 8.3E-6
and ramp-down slope 1)3)
SR
1) The device is robust against residual voltage ramp-up starting between 0 - 2.97 V for VEXT, VEVRSB, VDDP3 and VDDM
and 0-1 V for VDD. A voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation.
2) Also valid in case EVR33 or EVRC is used. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid
overshoots.
3) The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent
the specification.
•
Up to 1000000 power-cycles, matching the limits defined in the table ’Supply Ramp’ are allowed for TC38x,
without any restriction to reliability.
Data Sheet
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TC38x AD/AE-Step
Electrical Specification PMS
Table 3-34 EVRC SMPS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input VEXT Voltage range
VIN SR
2.97
-
5.5
V
V
Start-up VEXT voltage
> 2.6 V
SMPS regulator output voltage
range including load/line
regulation and aging
V
DDDC CC
1.125
-
1.375
1.275
2.0
V
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 1mA ;
DDDC ≤ 1.5A ;
untrimmed
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 1mA ;
DDDC ≤ 1.5A
≤
I
SMPS regulator static voltage
output accuracy after trimming
without dynamic load/line
regulation.
V
DDDCT CC 1.225
1.25
1.82
V
V
≤
I
Programmable switching
frequency
f
DCDC SR
1.6
MHz
Start-up frequency
switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation.
-
0.8
-
MHz
Start-up frequency
switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation. 0.8
MHz to be set in SW.
Startup time
t
STRDC CC
-
-
900
µs
SMPS Start-up Mode. It
is is defined beween
VEXTPRIUV reset
threshold till PORST
release, on condition
that all other PORST
requirements were
released before. ISTART
< 700mA.
Switching frequency modulation ΔfDCSPR CC -
spread
1.8%
-
-
MHz
mV
Maximum ripple at IMAX
ΔVDDDC CC
-
16
V
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 300mA ;
DDDC ≤ 1.5A ; ΔVDDDC
(Peak to Peak ripple / 2)
DCDC=1.82MHz;
DDDC=ISLEEP; VEXT
≤
I
=
No load current consumption of IDCNL CC
SMPS regulator
-
-
15
5
19
-
mA
mA
f
I
>
2.97 V; TJ=25°C
LPM mode;
IDDDC=ISLEEP; VEXT
>
2.97 V; TJ=25°C
Data Sheet
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TC38x AD/AE-Step
Electrical Specification PMS
Table 3-34 EVRC SMPS (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SMPS regulator load transient dVDDDCT
/
-50
-
-
-
87
mV
dI < -450mA ;
response
dlOUT CC
I
DDDC=500-1500mA;
tr=0.1us; tf=0.1us;
DDDC=1.25V;
settle=100 us
dI < -700mA ;
DDDC=750-1500mA;
tr=0.1us; tf=0.1us;
DDDC=1.25V;
settle=100 us
V
T
-100
-26
145
26
mV
mV
I
V
T
dI < 100mA ; IDDDC=50-
1500mA; tr=0.1us;
tf=0.1us; VDDDC=1.25V;
Tsettle=20us;
Maximum output current
I
MAX CC
100
1.5
-75
-12.5
-
-
-
mA
A
LPM mode. Typical
current in LPM Mode =
ISLEEP
-
-
limited by thermal
constraints and
component choice
SMPS regulator line transient
response
dVDDDCT
dVIN CC
/
-
75
12.5
-
mV
mV
%
dV/dT=120V/ms; dV <
2.97 - 5.5V ; IDDDC=50-
1500mA;
-
dV/dT=1V/ms; dV <
2.97 - 5.5V ; IDDDC=50-
1500mA;
SMPS regulator efficiency
n
DC CC
80
75
1.82
VIN=3.3V;
I
DDDC=1500mA;
DCDC=1.82MHz
VIN=5V;
DDDC=1500mA;
DCDC=1.82MHz
f
-
-
%
I
f
InputSynchronisationfrequency fDCDCSYNC
1.6
2.0
MHz
SR
Table 3-35 EVRC SMPS External components
Parameter Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
External output capacitor value COUT SR
20.8
32
43.2
µF
µF
I
DDDC=1.5A; fDDDC
0.8MHz
DDDC=1.5A; fDDDC
1.82MHz
=
=
1)
15.4
22
29.7
I
Data Sheet
350
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification PMS
Table 3-35 EVRC SMPS External components (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
External output capacitor ESR COUT_ESR
-
-
mOhm f≥0.5MHz ; f≤10MHz
SR
-
-
100
13.5
50
Ohm
µF
f=10Hz
IDDDC=1.5A
External input capacitor value 1) CIN SR
6.5
-
10
External input capacitor ESR
External inductor value
External inductor DCR
C
IN_ESR SR
-
mOhm f≥0.5MHz ; f≤10MHz
-
-
100
6.11
4.29
0.2
Ohm
f=100Hz
L
L
DC SR
3.29
2.31
4.7
3.3
-
f
DCDC=0.8MHz
DCDC=1.82MHz
µH
Ohm
V
f
DC_DCR SR -
LL SR
P + N-channel MOSFET logic
level
V
-
-
2.5
P + N-channel MOSFET drain |VBR_DS| SR +7
-
-
V
V
NMOS - VGS = 0.
PMOS - VGS = 0.
source breakdown voltage
-
-
-7
-
P + N-channel MOSFET drain
source ON-state resistance
R
ON SR
-
-
150
mOhm IDDDC=1.5A; |VGS|=2.5V
; TA=25°C
P + N-channel MOSFET Gate QG SR
-
-
-
8
-
nC
nC
mA
IDDDC=1.5A; NMOS-
|VGS|=5V; 1.5A pulsed
drain current
Charge
-8
IDDDC=1.5A; PMOS-
|VGS|=5V; 1.5A pulsed
drain current
External Inductor Saturation
Current Margin
ΔISAT SR
400
-
The saturation current
of the coil must be
larger than IDDDC
ΔISAT
+
P + N-channel MOSFET Gate
threshold voltage
V
V
GSTH SR
-
-
-
1
-
-
-
V
V
V
NMOS
PMOS
-1
0.8
N-channel MOSFET reverse
diode forward voltage
RDN SR
1) Capacitor min-max range represent typical +-35% tolerance including DC bias effect. The trace resistance from the capacitor
to the supply or ground rail should be limited to 25 mOhm.
Data Sheet
351
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TC38x AD/AE-Step
Electrical Specification System Phase Locked Loop (SYS_PLL)
3.16
System Phase Locked Loop (SYS_PLL)
Table 3-36 PLL System
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10
Max.
40
DCO Input frequency range
Modulation Amplitude
Peak Period jitter
f
REF CC
-
-
-
MHz
%
MA CC
DP CC
0
2
-200
200
ps
without modulation
(PLL output frequency)
Peak Accumulated Jitter
Total long term jitter
D
PP CC
-5
-
-
-
5
ns
ns
without modulation
J
TOT CC
11.5
including modulation;
MA 1.25%; fREF 20MHz
System frequency deviation
DCO frequency range
PLL lock-in time
f
f
SYSD CC
DCO CC
-
-
-
-
0.01
800
100
%
with active modulation
400
4
MHz
µs
tL CC
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
352
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TC38x AD/AE-Step
Electrical Specification Peripheral Phase Locked Loop (PER_PLL)
3.17
Peripheral Phase Locked Loop (PER_PLL)
Table 3-37 PLL Peripheral
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Peak Accumulated jitter at
SYSCLK pin
D
PP CC
-1000
-
1000
ps
Peak only
Peak accumulated jitter
RMS Accumulated jitter
D
D
PPI CC
-700
-100
-
-
700
100
ps
ps
Peak only
RMS CC
measured over 1 µs;
fREF = 20 MHz and fDCO
= 640 MHz or fREF = 25
MHz and fDCO = 800
MHz
Peak Period jitter
DP CC
-200
-125
-85
-
-
-
-
200
125
85
ps
ps
ps
ps
f
DCO = 640 MHz or fDCO
= 800 MHz
REF = 10 MHz; fDCO
640 MHz
REF = 20 MHz; fDCO
640 MHz
REF = 25 MHz; fDCO
800 MHz
Absolute RMS jitter (PLL out)
Absolute RMS jitter (PLL out)
Absolute RMS jitter (PLL out)
J
J
J
ABS10 CC
ABS20 CC
ABS25 CC
f
=
=
=
f
-85
85
f
DCO frequency range
DCO input frequency range
PLL lock-in time
f
f
DCO CC
REF CC
400
10
4
-
-
-
800
40
MHz
MHz
µs
tL CC
100
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
353
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TC38x AD/AE-Step
Electrical Specification AC Specifications
3.18
AC Specifications
All AC parameters are specified for the complete operating range defined in Chapter 3.4 unless otherwise noted
in column Note / Test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FLEX / VDDP3
90%
90%
10%
10%
VSS
tr
tf
rise_fall
Figure 3-8 Definition of rise / fall times
VEXT/FLEX/ VDDP3
Timing
Reference
Points
VEXT/FLEX /VDDP3
VEXT /FLEX / VDDP3
2
2
VSS
timing_reference
Figure 3-9 Time Reference Point Definition
Data Sheet
354
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TC38x AD/AE-Step
Electrical Specification JTAG Parameters
3.19
JTAG Parameters
The following parameters are applicable for communication through the JTAG debug interface. The JTAG module
is fully compliant with IEEE1149.1-2000.
Table 3-38 JTAG
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
10
10
-
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
TCK low time
-
TCK clock rise time
TCK clock fall time
4
4
-
-
TDI/TMS setup to TCK rising
edge
6.0
TDI/TMS hold after TCK rising t7 SR
6.0
-
-
ns
edge
TDO valid after TCK falling edge t8 CC
(propagation delay)
3.0
-
-
-
-
-
ns
ns
ns
ns
CL≤20pF
CL≤50pF
-
25
-
TDO hold after TCK falling edge t18 CC
2
-
TDO high impedance to valid
from TCK falling edge
t9 CC
25
CL≤50pF
CL≤50pF
TDO valid output to high
impedance from TCK falling
edge
t
10 CC
-
-
25
ns
t1
0.9 VEXT
0.1 VEXT
0.5 VEXT
t5
t4
t2
t3
MC_JTAG_TCK
Figure 3-10 Test Clock Timing (TCK)
Data Sheet
355
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TC38x AD/AE-Step
Electrical Specification JTAG Parameters
TCK
TMS
TDI
t6
t7
t6
t7
t9
t8
t10
TDO
t18
MC_JTAG
Figure 3-11 JTAG Timing
Data Sheet
356
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TC38x AD/AE-Step
Electrical Specification DAP Parameters
3.20
DAP Parameters
The following parameters are applicable for communication through the DAP debug interface.
Table 3-39 DAP
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DAP0 clock rise time
t
t
14 SR
15 SR
-
-
-
-
-
-
-
-
-
-
1
4
2
1
4
2
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
f=160MHz
f=40MHz
f=80MHz
f=160MHz
f=40MHz
f=80MHz
-
-
DAP0 clock fall time
-
-
-
DAP1 setup to DAP0 rising edge t16 SR
4
5
2
-
f=40MHz
DAP1 hold after DAP0 rising
edge
t
t
17 SR
19 CC
-
DAP1 valid per DAP0 clock
period
4
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=20pF ; f=160MHz
CL=20pF ; f=80MHz
CL=50pF ; f=40MHz
8
10
2
DAP0 high time
DAP0 low time
t
t
t
12 SR
13 SR
11 SR
2
DAP0 clock period
6.25
Table 3-40 SCR DAP
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
-
Typ.
Max.
DAP0 clock rise time
DAP0 clock fall time
t
t
14 SR
15 SR
-
-
-
-
8
8
-
ns
ns
ns
ns
f=20MHz
f=20MHz
-
DAP1 setup to DAP0 rising edge t16 SR
10
10
DAP1 hold after DAP0 rising
edge
t
17 SR
-
DAP1 valid per DAP0 clock
period
t
19 CC
30
-
-
ns
CL=20pF ; f=20MHz
DAP0 high time
DAP0 low time
t
t
t
12 SR
13 SR
11 SR
15
15
50
-
-
-
-
-
-
ns
ns
ns
DAP0 clock period
Data Sheet
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TC38x AD/AE-Step
Electrical Specification DAP Parameters
t11
t15
t14
t13
t12
0.9 VEXT
0.1 VEXT
0.5 VEXT
DAP0
t16
t17
DAP1
(Host to Device)
t11
1),2)
DAP1
(Device to Host)
t19
1) The DAP1 and DAP2 device to host timing is individual for both pins.
There is no guaranteed max. signal skew.
2) No explicit setup and hold times are given for DAP1 for the direction Device to Host.
Only t11 and t19 are guaranteed and the tool may set the sample point freely.
Figure 3-12 DAP Timing
Note:The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
Data Sheet
358
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TC38x AD/AE-Step
Electrical Specification ASCLIN SPI Master Timing
3.21
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC38x.
Note:Pad asymmetry is already included in the following timings.
Table 3-41 Master Mode strong sharp (ss) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period
t
t
t
50 CC
500 CC
51 CC
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
Deviation from ideal duty cycle
-2
2
MTSR delay from ASCLKO
shifting edge
-3.5
3.5
ASLSOn delay from the first
ASCLKO edge
t
t
t
510 CC
52 SR
53 SR
-3
25
-2
-
-
-
3.5
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
MRST setup to ASCLKO
latching edge
-
-
MRST hold from ASCLKO
latching edge
Table 3-42 Master Mode strong medium (sm) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
ASCLKO clock period
t
t
t
50 CC
500 CC
51 CC
-
-
-
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
-5
5
7
MTSR delay from ASCLKO
shifting edge
-7
ASLSOn delay from the first
ASCLKO edge
t
t
t
510 CC
52 SR
53 SR
-7
35
-5
-
-
-
7
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
Table 3-43 Master Mode medium (m) output pads
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
160
-10
Typ.
Max.
-
ASCLKO clock period
t
t
t
50 CC
500 CC
51 CC
-
-
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
10
20
MTSR delay from ASCLKO
shifting edge
-20
ASLSOn delay from the first
ASCLKO edge
t
510 CC
-20
-
20
ns
CL=50pF
Data Sheet
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TC38x AD/AE-Step
Electrical Specification ASCLIN SPI Master Timing
Table 3-43 Master Mode medium (m) output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to ASCLKO
latching edge
t
t
52 SR
53 SR
80
-
-
ns
ns
CL=50pF
CL=50pF
MRST hold from ASCLKO
latching edge
-15
-
-
t50
ASCLKO
MTSR
t51
t51
t500
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-13 ASCLIN SPI Master Timing
Data Sheet
360
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TC38x AD/AE-Step
Electrical Specification QSPI Timings, Master and Slave Mode
3.22
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC38x.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
Note:Pad asymmetry is already included in the following timings.
Table 3-44 Master Mode Timing, LVDS output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20 1)
-1 1)
Max.
-
1 1)
SCLKO clock period
t
t
50 CC
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle
500 CC
MTSR delay from SCLKO
shifting edge
t
51 CC
-3 1)
-
-
-
-
-
4 1)
ns
ns
ns
ns
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-4 1)
5.5 1)
10 1)
30 1)
-
CL=25pF, driver
strength ss
-10 1)
-30 1)
18 1)
CL=25pF, driver
strength sm
CL=25pF, driver
strength m
MRST setup to SCLK latching
edge
t
52 SR
CL=25pF; valid for
LVDS Input pads of
QSPI2 only
19.5 1)
-
-
-
-
ns
ns
CL=25pF; valid for
LVDS Input pads of
QSPI4 only
MRST hold from SCLK latching t53 SR
-1 1)
CL=25pF; valid for
edge
LVDS Input pads only
1) The load (CL=25pF) defined in the condition list is a load definition for the single end signal SLSO and does not intend to add
an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the
signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-45 Master Mode Strong Sharp (ss) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle
500 CC
-2
2
MTSR delay from SCLKO
shifting edge
t
51 CC
-4
-
-
-
-
5
5
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-4
MRST setup to SCLK latching
edge
t
52 SR
25 1) 2)
-2 1)2)
MRST hold from SCLK latching t53 SR
-
edge
Data Sheet
361
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TC38x AD/AE-Step
Electrical Specification QSPI Timings, Master and Slave Mode
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-46 Master Mode Strong Medium (sm) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period
t
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle
500 CC
-5
5
MTSR delay from SCLKO
shifting edge
t
51 CC
-7
-
-
-
-
7
7
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-7
MRST setup to SCLK latching
edge
t
52 SR
35 1) 2)
-5 1)2)
MRST hold from SCLK latching t53 SR
-
edge
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-47 Master Mode Medium (m) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
160
-10
Max.
-
SCLKO clock period
t
t
50 CC
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle
500 CC
10
MTSR delay from SCLKO
shifting edge
t
51 CC
-20
-
-
-
20
20
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-20
MRST setup to SCLK latching
edge
t
52 SR
80 1) 2)
MRST hold from SCLK latching t53 SR
edge
-15 1)2)
-13 1)2)
-
-
-
-
ns
ns
CL=50pF
CL=50pF; SCR SSC
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-48 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
-
SCLK clock period
SCLK duty cycle
t
t
54 SR
4 x TMAX
40
-
-
ns
%
55/t54 SR
60
Data Sheet
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TC38x AD/AE-Step
Electrical Specification QSPI Timings, Master and Slave Mode
Table 3-48 Slave mode timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
6
Max.
MTSR setup to SCLK latching
edge
t
56 SR
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
6
-
MTSR hold from SCLK latching t57 SR
edge
4
-
6
-
SLSI setup to first SCLK shift
edge
t
t
t
58 SR
59 SR
60 CC
4
-
6
-
SLSI hold from last SCLK
latching edge
3
-
6
-
MRST delay from SCLK shift
edge
5
35
driver = strong edge =
medium ; CL=50pF
2
-
-
-
24
80
-
ns
ns
ns
driver = strong edge =
sharp ; CL=50pF
15
14
medium driver ;
CL=50pF
medium driver ;
CL=50pF; SCR SSC
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-14 Master Mode Timing
Data Sheet
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TC38x AD/AE-Step
Electrical Specification QSPI Timings, Master and Slave Mode
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-15 Slave Mode Timing
Data Sheet
364
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TC38x AD/AE-Step
Electrical Specification MSC Timing 5 V Operation
3.23
MSC Timing 5 V Operation
The following section defines the timings.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Table 3-49 LVDS clock/data (LVDS pads in LVDS mode) valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
1) 2)
FCLPx clock period
t
40 CC
2 * TA
-
-
ns
LVDS; CL=50pF
3)
Deviation from ideal duty cycle
SOPx output delay
t
t
t
400 CC
44 CC
45 CC
-1 3)
-3 3)
-4 3)
-
-
-
1 3)
3 3)
5 3)
ns
ns
ns
LVDS; 0 < CL < 50pF
CL=50pF
ENx output delay
ss; CL=50pF; ABRA
block bypassed
-4 3)
-
4 3)
ns
ss; CL=50pF; ABRA
block used
-2 3)
-30 3)
-
-
10 3)
30 3)
ns
ns
sm; CL=50pF
m; CL=50pF
1) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The load (CL=50pF) defined in the condition list is a load definition for the single end signal EN and does not intend to add an
additional load inside the differential signal lines. For single end signals the load definition defines the max length of the signal
on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-50 Strong sharp (ss) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
-
FCLPx clock period
t
t
t
t
40 CC
400 CC
44 CC
45 CC
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
SOPx output delay
2
-4
3.5
3.5
ENx output delay
-4
Table 3-51 Strong medium (sm) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-5
Max.
FCLPx clock period
t
t
t
t
40 CC
400 CC
44 CC
45 CC
-
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
SOPx output delay
5
7
7
-7
ENx output delay
-7
Data Sheet
365
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification MSC Timing 5 V Operation
Table 3-52 Medium (m) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-10
Max.
-
FCLPx clock period
t
t
t
t
40 CC
400 CC
44 CC
45 CC
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle
SOPx output delay
10
20
20
-20
ENx output delay
-20
Table 3-53 Upstream Interface
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
-
SDI bit time
SDI rise time
SDI fall time
t
t
t
46 SR
48 SR
49 SR
8 * tMSC
-
-
-
ns
ns
ns
-
-
200
200
t40
t400
FCLP
SOP
t44
t44
t45
t45
0.5 VEXT/FLEX
EN
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-16 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
Data Sheet
366
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24
Ethernet Interface (ETH) Characteristics
3.24.1
ETH Measurement Reference Points
ETH Clock
ETH I/O
1.4
2.0
V
1.4 V
V
2.0
V
0.8
V
0.8
V
tR
tF
ETH_Testpoints.vsd
Figure 3-17 ETH Measurement Reference Points
Data Sheet
367
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.2
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 3-54 ETH Management Signal Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
400
160
160
10
Max.
ETH_MDC period
ETH_MDC high time
ETH_MDC low time
t1 CC
t2 CC
t3 CC
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
-
-
ETH_MDIO setup time (output) t4 CC
-
ETH_MDIO hold time (output)
ETH_MDIO data valid (input)
t5 CC
t6 SR
10
-
0
300
t1
t3
t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4
t5
ETH_MDIO
(output )
Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input )
Valid Data
ETH_Timing-Mgmt.vsd
Figure 3-18 ETH Management Signal Timing
Data Sheet
368
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.3
ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.
Table 3-55 ETH MII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Clock period
t7 SR
-
40
-
ns
ns
ns
ns
ns
ns
CL=25pF ;
baudrate=100Mbps
-
400
-
CL=25pF ;
baudrate=10Mbps
Clock high time
Clock low time
t8 SR
t9 SR
14
-
-
-
-
26
CL=25pF ;
baudrate=100Mbps
140 1)
14
260 2)
26
CL=25pF ;
baudrate=10Mbps
CL=25pF ;
baudrate=100Mbps
140 1)
260 2)
CL=25pF ;
baudrate=10Mbps
Input setup time
Input hold time
t
t
t
10 SR
11 SR
12 CC
10
10
0
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
-
Output valid time
25
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t7
t9
t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t10
t11
ETH_MII_RXD[3:0]
ETH_MII_RX_DV
ETH_MII_RX_ER
(sourced by PHY )
Valid Data
ETH_MII_TX_CLK
t12
ETH_MII_TXD[3:0]
ETH_MII_TXEN
Valid Data
(sourced by controller )
ETH_Timing-MII.vsd
Figure 3-19 ETH MII Signal Timing
Data Sheet
369
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.4
ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.
Table 3-56 ETH RMII Signal Timing Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ETH_RMII_REF_CL clock
period
t
13 SR
-
20
-
ns
ns
ns
ns
50ppm ; CL=25pF
CL=25pF
ETH_RMII_REF_CL clock high t14 SR
time
7 1)
7 1)
4
-
13 2)
13 2)
-
ETH_RMII_REF_CL clock low
time
t
t
15 SR
16 CC
-
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV;
setup time 3)
-
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV;
hold time 3)
t
17 CC
2
-
-
ns
CL=25pF
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
3) For ETHRXD and ETHCRSDV signals this parameter is a SR.
t13
t15
t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t16
t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0],
ETHCRSDV,
ETHRXER
Valid Data
ETH_Timing-RMII.vsd
Figure 3-20 ETH RMII Signal Timing
Data Sheet
370
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.5
ETH RGMII Parameters
In the following, the parameters of the RGMII are described.
Table 3-57 ETH RGMII Signal Timing Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
36
Max.
44
TX Clock period
t
19 CC
40
400
8
ns
ns
ns
ps
ns
100Mbps
10Mbps
Gigabit
360
7.2
-500
1
440
8.8
Data to Clock Output skew
t
t
20 CC
21 SR
0
500
2.6
Data to Clock input skew (at
receiver)
1.8
SKEWCTL.RXCFG =
0;SKEWCTL.TXCFG=
0
Clock duty cycle
t
t
duty CC
40
50
50
-
60
%
%
%
%
10/100Mbps
Gigabit
45
55
GREFCLK duty cycle
duty_in SR
45
55
GREFCLK Input accuracy
ACC SR
-0.005
-
0.005
Figure 3-21 ETH RGMII TX Signal Timing (Delay on Destination (DoD))
Figure 3-22 ETH RGMII RX Signal Timing (Delay on Source (DoS))
Data Sheet
371
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TC38x AD/AE-Step
Electrical Specification E-Ray Parameters
3.25
E-Ray Parameters
The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL =
25 pF.
Table 3-58 Transmit Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise time of TxEN
Fall time of TxEN
tdCCTxENRise2
5 CC
-
-
-
-
-
9
ns
ns
ns
ns
CL=25pF
tdCCTxENFall25
CC
-
-
-
9
CL=25pF
Sum of rise and fall time
tdCCTxRise25+d
CCTxFall25 CC
9
20% - 80% ; CL=25pF
Sum of delay between TP1_FF tdCCTxEN01
25
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxEN
CC
Sum of delay between TP1_FF tdCCTxEN10
-
-
25
ns
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxEN
CC
Asymmetry of sending
t
tx_asym CC -2.45
-
-
2.45
25
ns
ns
CL=25pF
Sum of delay between TP1_FF tdCCTxD01 CC -
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxD
Sum of delay between TP1_FF tdCCTxD10 CC -
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxD
-
-
25
9
ns
ns
TxD signal sum of rise and fall
time at TP1_BD
t
txd_sum CC
-
Table 3-59 Receive Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -30.5
ept25 SR
-
43.0
ns
ns
%
%
CL=25pF
CL=15pF
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -31.5
ept15 SR
-
-
-
44.0
70
Threshold for detecting logical TuCCLogic1
high SR
Threshold for detecting logical TuCCLogic0
35
30
65
low
SR
Data Sheet
372
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TC38x AD/AE-Step
Electrical Specification E-Ray Parameters
Table 3-59 Receive Parameters (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sum of delay between TP4_CC tdCCRxD01 CC -
and TP4_FF and delays derived
from TP4_FFi, rising edge of
RxD
-
10
ns
Sum of delay between TP4_CC tdCCRxD10 CC -
and TP4_FF and delays derived
from TP4_FFi, falling edge of
RxD
-
10
ns
Data Sheet
373
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TC38x AD/AE-Step
Electrical Specification HSCT Parameters
3.26
HSCT Parameters
Table 3-60 HSCT - Rx parasitics and loads
Parameter
Symbol
Values
Typ.
3.5
Unit
Note / Test Condition
Min.
Max.
Capacitance total budget
C
total CC
-
5
pF
Total Budget for
complete receiver
including silicon,
package, pins and
bond wire
Parasitic inductance budget
Htotal CC
-
5
-
nH
Table 3-61 HSCT - Rx/Tx setup timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
60
RX o/p duty cycle
DCrx CC
40
-
-
-
-
-
-
%
Disable time of the LVDS pad
Enable time of the LVDS pad
t
t
LVDSDIS CC
LVDSEN CC
20
ns
ns
ns
ns
-
400
250
0.2
Wakeup time from Sleep Mode tSWU CC
-
Maximum length of a wake-up
glitch that does not wake-up the
receiver
t
WUP CC
-
Bias startup time
t
bias CC
-
5
10
µs
Bias distributor waking
up from power down
and provide stable
Bias.
RX startup time
TX startup time
trxi CC
ttx CC
-
-
-
-
600
280
ns
ns
Wake-up RX from
power down.
Wake-up TX from
power down.
Data Sheet
374
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TC38x AD/AE-Step
Electrical Specification Inter-IC (I2C) Interface Timing
3.27
Inter-IC (I2C) Interface Timing
This section defines the timings for I2C in the TC38x.
All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-62 I2C Standard Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
-
-
300
ns
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Capacitive load for each bus line Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
4.7
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
and ATART condition
Rise time of both SDA and SCL t2
-
-
-
-
-
-
-
1000
ns
µs
ns
µs
µs
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data hold time
t3
t4
t5
t6
t7
0
-
-
-
-
-
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data set-up time
250
4.7
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Hold time for the (repeated)
START condition
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data Sheet
375
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OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Inter-IC (I2C) Interface Timing
Table 3-62 I2C Standard Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Set-up time for (repeated)
START condition
t8
4.7
-
-
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for STOP condition t9
4
-
-
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Table 3-63 I2C Fast Mode Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Fall time of both SDA and SCL t1
20+0.1*Cb
-
300
ns
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Capacitive load for each bus line Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
1.3
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
and ATART condition
Rise time of both SDA and SCL t2
20+0.1*Cb
-
-
-
-
-
300
ns
µs
ns
µs
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data hold time
t3
t4
t5
t6
0
-
-
-
-
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data set-up time
100
1.3
0.6
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data Sheet
376
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TC38x AD/AE-Step
Electrical Specification Inter-IC (I2C) Interface Timing
Table 3-63 I2C Fast Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Hold time for the (repeated)
START condition
t7
0.6
-
-
-
-
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for (repeated)
START condition
t8
0.6
0.6
-
-
µs
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Table 3-64 I2C High Speed Mode Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
-
Typ.
Max.
400
40 1)
80 1)
40 1)
80 1)
70 1)
-
Capacitive load for each bus line Cb SR
-
-
-
-
-
-
-
-
-
-
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fall time of SCL
t11
t12
t13
t14
t3
10 1)
10 1)
10 1)
10 1)
0 1)
10 1)
160 1)
60 1)
160 1)
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
Fall time of SDA
Rise time of SCL
Rise time of SDA
Data hold time
Data set-up time
t4
Low period of SCL clock
High period of SCL clock
t5
-
t6
-
Hold time for the (repeated)
START condition
t7
-
Set-up time for (repeated)
START condition
t8
160 1)
160 1)
-
-
-
-
ns
ns
bus line load of 100pF
bus line load of 100pF
Set-up time for STOP condition t9
1) Values are defined for Cb = 100pF, for the Timing of Cb = 400pF see the I2C Standard.
Data Sheet
377
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TC38x AD/AE-Step
Electrical Specification Inter-IC (I2C) Interface Timing
t1
t2
t4
70%
30%
SDA
SCL
t1
t3
t2
t6
9th
clock
t7
t5
t10
S
SDA
SCL
t8
t7
t9
9th
clock
Sr
P
S
Figure 3-23 I2C Standard and Fast Mode Timing
Data Sheet
378
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TC38x AD/AE-Step
Electrical Specification FSP Parameters
3.28
FSP Parameters
Table 3-65 Safety
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Skew between FSP0 and FSP1 tFSPSKEW CC -8
-
-
-
9
ns
ns
ns
CL=50pF, driver
strength m
-5
-4
6
5
CL=50pF, driver
strength sm
CL=50pF, driver
strength ss
Data Sheet
379
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TC38x AD/AE-Step
Electrical Specification Flash Target Parameters
3.29
Flash Target Parameters
Table 3-66 Flash
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program Flash Erase Time per
logical sector 1)
t
t
ERP CC
-
-
0.5
s
s
cycle count < 1000
Program Flash Erase Time per
Multi-Sector Command 1)
MERP CC
-
-
0.5
For consecutive logical
sectors in a physical
sector with total range ≤
512 kByte; cycle count
< 1000
Program Flash program time
per page in 5 V mode 1)
t
t
t
t
PRP5 CC
PRP3 CC
PRPB5 CC
PRPB3 CC
-
-
-
-
-
-
-
-
-
-
80
µs
µs
µs
µs
s
32 Byte
32 Byte
256 Byte
256 Byte
Program Flash program time
per page in 3.3 V mode 1)
115
220
530
2.2
Program Flash program time
per burst in 5 V mode 1)
Program Flash program time
per burst in 3.3 V mode 1)
Program Flash program time for tPRPB3_1MB
1 MByte with burst programming CC
in 3.3 V mode excluding
communication 1)
Derived value for
documentation purpose
Program Flash program time for tPRPB5_1MB
1 MByte with burst programming CC
in 5 V mode excluding
-
-
-
-
1
s
s
Derived value for
documentation purpose
communication 1)
Program Flash program time for tPRPB5_PF
10
Derived value for
complete PFlash with burst
programming in 5 V mode
excluding communication 1)
CC
documentation purpose
Write Page Once adder 1)
t
ADD CC
-
-
-
-
20
µs
µs
Adder to Program Time
when using Write Page
Once
Program Flash suspend to read tSPNDP CC
120
For Write Burst, Verify
Erased and for multi-
(logical) sector erase
commands
latency 1)
Data Flash Erase Disturb Limit
(single ended sensing mode)
N
N
N
DFD CC
-
-
-
-
-
-
50
cycles
cycles
cycles
Data Flash Erase Disturb Limit
(complement sensing mode)
DFDC CC
UCBD CC
500
500
UCB Erase Disturb Limit
Data Sheet
380
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TC38x AD/AE-Step
Electrical Specification Flash Target Parameters
Table 3-66 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program time data flash per
page 1)2)
t
t
PRD CC
-
-
75
µs
s
8 Byte
Complete Device Flash Erase
Time PFlash and DFlash 1)3) 4) 5)
ER_Dev CC
-
6.7
11.5
Valid for less than 1000
cycles, w/o UCB.
Derived value for
documentation
purpose.
Data Flash program time per
burst 1)2)
t
t
PRDB CC
-
-
-
-
-
-
-
-
140
120
2
µs
µs
µs
32 Byte
Data Flash suspend to read
latency 1)
SPNDD CC
Wait time after margin change tFL_MarginDel
CC
Program Flash Endurance per
Logical Sector
N
E_P CC
1000
cycles Replace logical sector
commandshall beused
if a sector fails during
erase or program
Number of erase operations per NERP CC
physical sector in program flash
-
-
-
-
16000
cycles
Program Flash Retention Time, tRET CC
Sector
20
20
-
-
years Max. 1000
erase/program cycles
UCB Retention Time
t
RTU CC
years Max. 100
erase/program cycles
per UCB, max 500
erase/program cycles
for all UCBs together
Data Flash access delay
Data Flash ECC Delay
t
t
t
t
DF CC
-
-
-
-
-
-
-
-
100
20
ns
ns
ns
ns
see RFLASH of DMU
register HF_DWAIT
DFECC CC
PF CC
see RECC of DMU
register HF_DWAIT
Program Flash access delay
Program Flash ECC delay
30
see RFLASH of DMU
register HF_PWAIT
PFECC CC
10
see RECC and CECC
of DMU register
HF_PWAIT
Number of erase operations on NERD0C CC
DF0 over lifetime (complement
sensing mode) 6)
-
-
-
-
4000000 cycles
Number of erase operations on NERD0S CC
DF0 over lifetime (single ended
sensing mode) 7)
750000
cycles
Data Sheet
381
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Flash Target Parameters
Table 3-66 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
2000000 cycles
Number of erase operations on NERD1C CC
DF1 over lifetime (complement
sensing mode) 6)
-
-
-
-
-
Number of erase operations on NERD1S CC
DF1 over lifetime (single ended
sensing mode) 7)
-
-
-
500000
500000
125000
cycles
Data Flash Endurance per
EEPROMx sector (complement CC
sensing mode) 8)
NE_EEP10C
cycles Max. data retention
time 10 years
DataFlash Endurance per
EEPROMx sector (single ended CC
sensing mode) 8)
NE_EEP10S
cycles Retention time and Tj
according below
example temperature
profile
-
-
-
-
-
125000
125000
250000
cycles max data retention time
20y, Tj=110°C
cycles max data retention time
8.2y, Tj=125°C
Data Flash Endurance per
HSMx sector (complement
sensing mode) 8)
N
N
E_HSMC CC -
cycles Max. data retention
time 10 years
Data Flash Endurance per
HSMx sector (single ended
sensing mode) 8)
E_HSMS CC -
-
125000
cycles Retention time and Tj
according below
example temperature
profile
-
-
-
-
-
125000
125000
150
cycles max data retention time
20y, Tj=110°C
cycles max data retention time
8.2y, Tj=125°C
Junction temperature limit for
PFlash program/erase
operations
T
JPFlash SR
-
°C
Data Flash Erase Time per
Sector 1)3)5)
t
t
ERD1 CC
ERDM CC
-
-
-
-
0.5
1.5
s
s
Max. 1000
erase/program cycles
Data Flash Erase Time per
Max allowed cycles,
see NE_EEP10 and
NE_HSM parameters
1)3)5)
Sector
DataFlash Adder on Erase Time tER_ADDC32C
-
-
50
ms
Adder per 32 kByte on
erase time; applicable
only when using
per 32kByte erase size when
using complement sensing
mode 1)
CC
complement mode
Data Sheet
382
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Flash Target Parameters
Table 3-66 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Data Flash Erase Time per
Multi-Sector Command 1)3)5)
t
t
MERD1 CC
-
-
0.5
s
Max 1000
erase/program cycles;
For consecutive logical
sectors ≤ 256KBytes
Data Flash Erase Time per
Multi-Sector Command 1)3)5)
MERDM CC
-
-
1.5
s
Max allowed cycles,
see NE_EEP10x and
NE_HSMxParameters;
For consecutive logical
sectors ≤ 256 kByte
Program Flash Access Delay at tPF_low_VDDP3
reduced VDDP3 voltage supply CC
during cranking
-
-
-
-
-
-
-
-
-
-
60
10
10
10
200
ns
µs
µs
µs
µs
see register
DMU_HF_PWAIT.CFL
ASH
Data Flash Erase Verify time per tVER_PAGE_DC
Time per 8 Byte page
for Verify Erased Page
command
page (Complement Sensing) 2) CC
Data Flash Erase Verify time per tVER_PAGE_DS
Time per 8 Byte page
for Verify Erased Page
command
page (Single Ended Sensing) 1) CC
Program Flash Erase Verify
time per page 1)
tVER_PAGE_P
CC
Time per 32 Byte page
for Verify Erased Page
command
Data Flash Erase Verify time per tVER_SEC_DC
Time per 2 KB sector
for Verify Erased
Logical Sector Range
command
sector (Complement Sensing) 1) CC
Data Flash Erase Verify time per tVER_SEC_DS
-
-
-
-
360
360
µs
µs
Time per 4 KB sector
for Verify Erased
Logical Sector Range
command
sector (Single Ended Sensing) 1) CC
Program Flash Erase Verify
time per sector 1)
tVER_SEC_P
CC
Time per 16KB sector
for Verify Erased
Logical Sector Range
command
Data Flash Erase Verify time per tVER_WL_DC
-
-
-
-
-
-
30
50
30
µs
µs
µs
wordline (ComplementSensing) CC
1)
Data Flash Erase Verify time per tVER_WL_DS
wordline (Single Ended
Sensing) 1)
CC
Program Flash Erase Verify
time per wordline 1)
tVER_WL_P
CC
1) Only vaild for fFSI = 100MHz.
2) Time is not dependent on program mode (5V or 3.3V).
Data Sheet
383
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Flash Target Parameters
3) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase processes
may be increased by up to 50%.
4) Using 512 kByte / 256 kByte erase commands (PFlash / DFlash).
5) If the DataFlash is operated in Complement Sensing Mode the erase time is increased by erase_size / 32kByte x
tER_ADDC32C
6) Allows segmentation of addressable memory into 8 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD
7) Allows segmentation of addressable memory into 6 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD
8) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
.
.
Data Sheet
384
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Quality Declarations
3.30
Quality Declarations
Table 3-67 Quality Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Moisture Sensitivity Level
MSL CC
-
-
3
Conforming to Jedec J-
STD--020C for 240C
ESD susceptibility according to VCDM SR
Charged Device Model (CDM)
-
-
-
500 1)
750
V
V
for all other balls/pins;
conforming to JESD22-
C101-C
-
for corner balls/pins;
conforming to JESD22-
C101-C
ESD susceptibility according to VHBM SR
Human Body Model (HBM)
-
-
-
-
2000 2)
2000
V
V
Conforming to
JESD22-A114-B
ESD susceptibility of the LVDS
pins according to Human Body
Model (HBM)
VHBM1 SR
Operation Lifetime
t
OP CC
-
-
24500
hour
see below temperature
profile as an example
1) Pads of the AGBT interface are limited to a maximum value of 250V.
2) Pads of the AGBT interface are limited to a maximum value of 1000V.
Example Temperature Profile
The following temperature profile is an example. Operation Lifetime plus Inactive time defines a 20 years period.
Application specific temperature profiles need to be aligned and approved by Infineon Technologies for the
fulfillment of quality and reliability targets.
Table 3-68 Example Operation Lifetime Temperature Profile
TJ=
Duration [h]
≤ 30
Comment
≤ 170°C
≤ 160°C
≤ 150°C
≤ 140°C
≤ 130°C
≤ 120°C
≤ 110°C
≤ 100°C
≤ 90°C
≤ 80°C
≤ 70°C
≤ 120
≤ 220
≤ 350
≤ 780
≤ 1600
≤ 3000
≤ 7000
≤ 8000
≤ 2400
≤ 1000
≤ 24500
total time
Data Sheet
385
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Quality Declarations
Table 3-69 Example Inactive Lifetime Temperature Profile
TJ=
Duration [h]
Comment
≤ 55°C
≤ 150700
Data Sheet
386
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Package Outline
3.31
Package Outline
Figure 3-24 Package Outlines FBGA-516
Figure 3-25 Package Outlines LFBGA-292
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
Data Sheet
387
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
Electrical Specification Package Outline
3.31.1
Package Parameters
Table 3-70 Package Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
14
17
3
Thermal resistance (junction to RTH_JA
ambient) 1)
-
-
-
-
-
-
-
-
-
-
-
-
K/W
K/W
K/W
K/W
K/W
K/W
FBGA516
LFBGA292
FBGA516
LFBGA292
FBGA516
LFBGA292
CC
Thermal resistance (junction to RTH_JCB
case bottom) 1)
CC
4
Thermal resistance (junction to RTH_JCT
case top) 1)
CC
5
5
1) The top and bottom thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) are to be combined with
the thermal resistances between the junction and the case given above (RTH_JCT, RTH_JCB), in order to calculate the total
thermal resistance between the junction and the ambient (RTH_JA). The thermal resistances between the case and the
ambient (RTH_CTA, RTH_CBA) depend on the external system (PCB, case) characteristics and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTH_JA * PD, where the RTH_JA is the
total thermal resistance between the junction and the ambient.
Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1).
Data Sheet
388
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
4
History
Version 0.4 is the first version of this document.
4.1
Changes from Version 0.4 to Version 0.6
•
•
Update table Platform Feature Overview
Changes in Pin Definition and Functions
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Add pad type RFAST to Legend
Corrected ball assigmant to NC and NC1
P32.0 replece name from EVR13 to EVRC
P32.1 replece name from EVR13 to EVRC
Add Function description for GTM_TIM_INxx Symbols
Change numbering for GTM_TIM_INxx Symbols
Update Function description for CAN signals
Add missing Function description for EVADC
Add missing Function description for EDSADC
Add Function description for GTM_DTMxx Symbols
Update Function description for SCU_E_REQ signals
Change Symbol for SCU_E_REQ signals
Update Function description for SCU_PD_HWCFGx signals
remove PLL_WRAPPER_ANA_0_PAD_SYSCLK
Switch CBS_TGyz from inverted to non inverted
Add CCUEXTCLK0
Add EDSADC_EDS9NB to AN70
Add EDSADC_EDS9NB to AN71
Add PMS_DCDCSYNCO to P32.4
Add DAP3 to P21.6
Remove SDMMC_DS from P15.2
ADD TDI to P21.6
Add DAPE1 to P21.6
Add DAP2 to P21.7
ADD TDO to P21.7
Remove DAP Function description from P21.7 Input
Add EVADC_G5CH2 to AN50
Add EDSADC_EDS9PB to AN70
Add EDSADC_EDS9NB to AN71
•
Changes in table 'Overload Parameters' of Overload
–
Change note of KOVDN from ''Overload injected on GPIO non LVDS pad and affecting neighbor slow pads;
-2mA < IIN < 0mA'' to ''Overload injected on GPIO non LVDS pad and affecting neighbor slow pads; -5mA
< IIN < 0mA''
–
–
Change max value of KOVDN from '6*10-4' to '1*10-4'
Change max value of KOVDN from '1.7*10-3' to '3*10-4'
Data Sheet
389
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
–
Change note of KOVDN from ''Overload injected on LVDS pad and affecting neighbor LVDS pads'' to
''Overload injected on LVDS TX pad and affecting neighbor LVDS pads''
–
–
Change max value of KOVDN from '0.3' to '0.5'
Change note of KOVDP from 'Overload injected on LVDS pad and affecting neighbor LVDS pads' to
'Overload injected on LVDS TX pad and affecting neighbor LVDS pads'
–
–
–
–
Change max value of KOVDP from 5*10-4 to 5*10-3
Change max value of KOVDP from '1*10-5' to '1.5*10-3'
Change max value of KOVAN from 1*10-4 to 1*10-5
Change note of KOVAN from 'Analog Inputs overlaid with class slow pads or pull down diagnostics; -1mA <
IIN < 0mA' to 'Analog Inputs overlaid with class slow pads or pull down diagnostics; -5mA < IIN < 0mA'
–
–
–
–
Change max value of KOVAN from 1*10-3 to 1*10-4
Change note of KOVAP from '1*10-5' to '2*10-5'
Change note of KOVAP from '1*10-4' to '2*10-4'
Add parameter IOUT
•
•
Operating Conditions
–
–
Change note of VDDM from 'Lower voltage range' to ''
Change note of VEVRSB from 'VEVRSB is bonded together with VEXT supply pin in smaller LQFP packages.'
to ''
Changes in table 'Fast 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
Change note of HYS from '0.1 * VEXT/FLEX V' to '0.09 * VEXT/FLEX V'
Change note of HYS from '0.09 * VEXT/FLEX V' to '0.075 * VEXT/FLEX V'
Change min value of RDSON from 140 Ohm to 125 Ohm
Change typ value of RDSON from 200 Ohm to 225 Ohm
Change note of RDSON from '260 Ohm' to '320 Ohm'
Change note of RDSON from '35 Ohm' to '31 Ohm'
Change note of RDSON from '50 Ohm' to '55 Ohm'
Change note of RDSON from '65 Ohm' to '80 Ohm'
Change note of tRF from ''CL = 25pF; driver = strong sharp edge'' to ''CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX''
–
–
–
–
–
–
–
–
–
–
–
–
–
Change note of tRF from '2.8 ns' to '3.2 ns'
Change min value of tRF from 0.5+0.075*CL ns to 0.5+0.08*CL ns
Change max value of tRF from 0.5+0.15*CL ns to 1.0+0.17*CL ns
Change note of tRF from '2.5+0.18*CL ns' to '1.0+0.18*CL ns'
Change note of tRF from '2.5+0.35*CL ns' to '5.0+0.35*CL ns'
Change max value of tRF from 4+0.95*CL ns to 12+1.0*CL ns
Change note of IOZ from '-3900 nA' to '-5000 nA'
Change min value of IOZ from -3600 nA to -5000 nA
Change min value of IOZ from -6700 nA to -9000 nA
Change max value of IOZ from 3900 nA to 5000 nA
Change max value of IOZ from 3600 nA to 5000 nA
Change note of IOZ from '6700 nA' to '9000 nA'
Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX
'
Data Sheet
390
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
–
–
–
Change note of fIND from '' to 'AL and TTL'
Change note of fOUTD from '' to 'medium driver'
Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'
•
Changes in table 'Fast 3.3V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
Change note of HYS from '0.065 * VEXT/FLEX V' to '0.055 * VEXT/FLEX V'
Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V
Change note of HYS from '0.07 * VEXT/FLEX V' to '0.055 * VEXT/FLEX V'
Change min value of RDSON from 140 Ohm to 125 Ohm
Change note of RDSON from '200 Ohm' to '225 Ohm'
Change note of RDSON from '300 Ohm' to '320 Ohm'
Change note of RDSON from '35 Ohm' to '31 Ohm'
Change typ value of RDSON from 50 Ohm to 55 Ohm
Change max value of RDSON from 77 Ohm to 80 Ohm
Change note of tRF from ''CL = 25pF; driver = strong sharp edge'' to ''CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX''
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Change note of tRF from '2 ns' to '1.6 ns'
Change min value of tRF from 4+0.57*CL ns to 2+0.57*CL ns
Change max value of tRF from 0.75+0.15*CL ns to 2.5+0.21*CL ns
Change max value of tRF from 1.5+0.38*CL ns to 8+0.4*CL ns
Change note of tRF from '7+1.1*CL ns' to '10+1.25*CL ns'
Change min value of IPUH from |19| µA to |17| µA
Change min value of IPUH from |9| µA to |11| µA
Change min value of IPDL from |18| µA to |15| µA
Change min value of IOZ from -4100 nA to -5000 nA
Change min value of IOZ from -3600 nA to -5000 nA
Change min value of IOZ from -6700 nA to -9000 nA
Change max value of IOZ from 4100 nA to 5000 nA
Change note of IOZ from '3600 nA' to '5000 nA'
Change max value of IOZ from 6700 nA to 9000 nA
Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX
'
–
Change note of fOUTD from '' to 'medium driver'
•
Changes in table 'Slow 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V
Change min value of HYS from 0.09 * VEXT/FLEX V to 0.075 * VEXT/FLEX V
Change min value of RDSON from 140 Ohm to 125 Ohm
Change typ value of RDSON from 200 Ohm to 225 Ohm
Change max value of RDSON from 260 Ohm to 320 Ohm
Change note of tRF from '4+0.95*CL ns' to '12+1*CL ns'
Change note of tRF from '3.5+0.55*CL ns' to '7+0.55*CL ns'
Change note of IPUH from 'VIH; AL or TTL' to 'VIH; AL or TTL; exept VGATE1P and TJ > 150°C'
Change note of IPUH from 'VIL; AL or TTL' to 'VIL; AL or TTL; exept VGATE1P and TJ > 150°C'
Data Sheet
391
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
–
Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'
•
Changes in table 'Slow 3.3V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V
Change min value of HYS from 0.065 * VEXT/FLEX V to 0.055 * VEXT/FLEX V
Change min value of HYS from 0.07 * VEXT/FLEX V to 0.055 * VEXT/FLEX V
Change note of RDSON from '140 Ohm' to '125 Ohm'
Change typ value of RDSON from 200 Ohm to 225 Ohm
Change max value of RDSON from 300 Ohm to 320 Ohm
Change note of tRF from '4+0.57*CL ns' to '2+0.57*CL ns'
Change note of tRF from '7+1.1*CL ns' to '10+1.25*CL ns'
Change note of IPUH from 'VIH; AL and TTL (degraded, used for CIF)' to 'VIH; AL and TTL (degraded, used
for CIF); exept VGATE1P and TJ > 150°C'
–
–
–
–
–
Change min value of IPUH from |19| µA to |17| µA
Change note of IPUH from ''VIH; TTL'' to ''VIH; TTL; exept VGATE1P and TJ > 150°C''
Change note of IPUH from '|9| µA' to '|11| µA'
Change min value of IPDL from |18| µA to |15| µA
Change note of IPUH from 'VIL; AL and TTL and TTL (degraded, used for CIF)' to 'VIL; AL and TTL and TTL
(degraded, used for CIF); exept VGATE1P and TJ > 150°C'
–
Change note of fOUTD from '' to 'medium driver'
•
Changes in table 'PORST Pad' of Standard Pads
–
Change note of HYS from 'non of the neighbor pads are used as output; TTL' to 'non of the neighbor pads
are used as output;TTL (degraded, used for CIF)'
–
–
–
Change min value of HYS from 0.1 * VEXT/FLEX V to 0.055 * VEXT/FLEX V
Change note of IPDL from '|18| µA' to '|15| µA'
Change note of HYS from 'two of the neighbor pads are used as output with driver=strong and edge=sharp;
TTL' to 'two of the neighbor pads are used as output with driver=strong and edge=sharp; TTL (degraded,
used for CIF)'
•
•
Changes in table 'Class S 5V' of Standard Pads
–
–
–
Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V
Change min value of HYS from 0.09 * VEXT/FLEX V to 0.075 * VEXT/FLEX V
Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'
Changes in table 'RFast 3.3V pad' of Standard Pads
–
–
–
–
–
–
–
–
–
–
Change min value of HYS from 0.065 * VEXT/FLEX V to 0.055 * VEXT/FLEX V
Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V
Change min value of HYS from 0.07 * VEXT/FLEX V to 0.055 * VEXT/FLEX V
Change min value of RDSON from 140 Ohm to 125 Ohm
Change typ value of RDSON from 200 Ohm to 225 Ohm
Change note of RDSON from '300 Ohm' to '320 Ohm'
Change note of RDSON from '35 Ohm' to '31 Ohm'
Change typ value of RDSON from 50 Ohm to 55 Ohm
Change max value of RDSON from 77 Ohm to 80 Ohm
Change note of RDSON from '10 Ohm' to '8 Ohm'
Data Sheet
392
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
–
Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX
'
–
–
–
–
–
–
–
–
–
Change min value of tRF from 2 ns to 1.6 ns
Change min value of tRF from 4+0.57*CL ns to 2+0.57*CL ns
Change note of tRF from '0.75+0.15*CL ns' to '2.5+0.21*CL ns'
Change max value of tRF from 1.5+0.38*CL ns to 8+0.4*CL ns
Change max value of tRF from 7+1.1*CL ns to 10+1.25*CL ns
Change min value of IPUH from |19| µA to |17| µA
Change note of IPUH from '|9| µA' to '|11| µA'
Change min value of IPDL from |18| µA to |15| µA
Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX
'
–
Change note of fOUTD from '' to 'medium driver'
•
Changes in table 'RFast 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
Change min value of HYS from 0.1 * VEXT/FLEX V to 0.09 * VEXT/FLEX V
Change note of HYS from '0.09 * VEXT/FLEX V' to '0.075 * VEXT/FLEX V'
Change min value of RDSON from 140 Ohm to 125 Ohm
Change max value of RDSON from 260 Ohm to 320 Ohm
Change typ value of RDSON from 200 Ohm to 225 Ohm
Change note of RDSON from '35 Ohm' to '31 Ohm'
Change max value of RDSON from 65 Ohm to 80 Ohm
Change note of RDSON from '50 Ohm' to '55 Ohm'
Change note of tRF from '2.5+0.18*CL ns' to '1.0+0.18*CL ns'
Change note of tRF from ''CL = 25pF; driver = strong sharp edge'' to ''CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX''
–
–
–
–
–
–
Change note of tRF from '2.8 ns' to '3.2 ns'
Change min value of tRF from 0.5+0.075*CL ns to 0.5+0.08*CL ns
Change note of tRF from '0.5+0.15*CL ns' to '1.0+0.17*CL ns'
Change max value of tRF from 4+0.95*CL ns to 12+1.0*CL ns
Change note of tRF from '2.5+0.35*CL ns' to '5.0+0.35*CL ns'
Change note of tRF from 'CL = 25pF; driver = strong sharp edge' to 'CL = 25pF; driver = strong sharp edge;
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX
'
–
–
–
Change note of fIND from '' to 'AL and TTL'
Change note of fOUTD from '' to 'medium driver'
Change note of IPDL from 'VIL; AL or TTL' to 'VIL; AL'
•
•
Changes in table 'Class D' of Standard Pads
–
–
Update footnote of Standard Pads to 'For AN11 200 nA need to be added.'
Change note of IOZ from 'TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC
channel connected' to 'TJ ≤ 150°C; PDD option available, or AltRef option available and EDSADC channel
connected, or two EDSADC channels connected'
Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)' of LVDS Pads
–
–
Change max value of trise20 from 0.5 ns to 0.75 ns
Change max value of tfall20 from 0.5 ns to 0.75 ns
Data Sheet
393
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
–
–
Change max value of VOD from 450 mV to 500 mV
Change min value of VOD from 360 mV to 380 mV
•
VADC 5V
–
–
–
–
–
–
Change note of dVCSD from '-20 %' to '-10 %'
Change note of dVCSD from '20 %' to '10 %'
Change note of fADCI from 'Upper voltage range' to '4.5V ≤ VDDM ≤ 5.5V'
Change note of tSCAL from 'Upper voltage range' to '4.5V ≤ VDDM ≤ 5.5V'
Change note of fADCI from 'Lower voltage range' to '2.97V ≤ VDDM < 4.5V'
Change note of tS from 'Primary group or fast compare channel, upper voltage range; input buffer disabled'
to 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled'
–
–
Change note of tSCAL from 'Lower voltage range' to '2.97V ≤ VDDM < 4.5V'
Change note of tS from 'Primary group or fast compare channel, upper voltage range; input buffer enabled'
to 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled'
–
–
–
–
–
–
Change note of tS from 'Secondary group, upper voltage range; input buffer disabled' to 'Secondary group,
4.5V ≤ VDDM ≤ 5.5V; input buffer disabled'
Change note of tS from 'Secondary group, upper voltage range; input buffer enabled' to 'Secondary group,
4.5V ≤ VDDM ≤ 5.5V; input buffer enabled'
Change note of tS from 'Primary Group or fast compare channel, lower voltage range; input buffer disabled'
to 'Primary Group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer disabled'
Change note of tS from 'Primary group or fast compare channel, lower voltage range; input buffer enabled'
to 'Primary group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer enabled'
Change note of tS from 'Secondary group, lower voltage range; input buffer disabled' to 'Secondary group,
2.97V ≤ VDDM < 4.5V; input buffer disabled'
Change note of tS from 'Secondary group, lower voltage range; input buffer enabled' to 'Secondary group,
2.97V ≤ VDDM < 4.5V; input buffer enabled'
•
DSADC 5V
–
–
Update wording in front of table DSADC 5V
Change note of DCF from '10-5 fD, offset compensation filter enabled (FCFGMx.OEN = 001B)' to '10-5 fD,
offset compensation filter enabled (FCFGMx.OCEN = 001B)'
•
•
OSC_XTAL
–
–
Add parameter CXTAL1
Change typ value of CL1 from 2.35 pF to 3.35 pF
Changes in table 'DTS PMS' of DTS
Change max value of tM from 2.6 ms to 2.7 ms
–
•
•
Add table 'DTS Core'
Current Consumption
–
–
–
–
–
–
–
Update footnote of Current Consumption to 'A single DS channel instance consumes 4 mA.'
Change note of IDDRAIL from '800 mA' to '840 mA'
Change note of IDDRAIL from '920 mA' to '1100 mA'
Change note of IDDRAIL from '960 mA' to '1100 mA'
Change note of IDDRAIL from '1020 mA' to '1100 mA'
Change note of IDDRAIL from '1110 mA' to '1100 mA'
Change note of IDDRAIL from '1099 mA' to '1100 mA'
Data Sheet
394
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
•
Changes in table 'Module Core Current Consumption' of Current Consumption
–
Change name of Module Core Current Consumption from Module Core Current Concumption to
Module Core Current Consumption
–
–
–
–
–
–
–
–
Change max value of IDDCx0 from 40 mA to 45 mA
Change note of IDDCx0 from 'real power pattern' to 'real power pattern; IPC=0.6'
Change note of IDDCx0 from '60 mA' to '70 mA'
Change note of IDDCx0 from ''max power pattern'' to ''max power pattern; IPC=1.2''
Change max value of IDDCxx from IDDCx0 + 60 mA to IDDCx0 + 50 mA
Change note of IDDCxx from 'max power pattern' to 'max power pattern; IPC=1.2'
Change max value of IDDGTM from 60 mA to 100 mA
Change note of IDDGTM from 'real power pattern; TIMx, TOMx, ATOMx , MCSx active. 5 clusters at 200
MHz.' to 'real power pattern; TIMx, TOMx, ATOMx , MCSx active. 3 clusters at 200 MHz.'
–
–
–
–
–
Change max value of IDDGTM from 88 mA to 120 mA
Change note of IDDMBIST from '100 mA' to '200 mA'
Change note of IDDCxx from 'real power pattern' to 'real power pattern; IPC=0.6'
Change max value of IDDGTM from 20 mA to 50 mA
Change note of IDDGTM from 'TIMx, TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive.' to 'TIMx,
TOMx active at 100MHz. ATOMx , MCSx, DPLL inactive. 2 clusters at 100 MHz.'
–
–
–
Change max value of IEXTRAIL from 58 mA to 50 mA
Change max value of IEXTRAIL from t.b.d mA to 56 mA
Change max value of IEXTFLEX from 30 mA to 18 mA
•
Changes in table 'Module Current Consumption' of Current Consumption
–
–
–
Change max value of IEXTLVDS from t.b.d mA to 20 mA
Change note of ISCRSB from '4 mA' to '6.5 mA'
Change note of ISCRSB from ''SCR 8-bit Standby Controller in STANDBY Mode drawn at VEVRSB supply pin''
to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin''
–
–
–
Change note of ISCRSB from ''Additional SCR 8-bit Standby Controller current in STANDBY Mode drawn at
VEVRSB supply pin'' to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB
supply pin''
Change note of ISCRSB from ''SCR 8-bit Standby Controller current in STANDBY Mode incl. PMS current
drawn at VEVRSB supply pin'' to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn
at VEVRSB supply pin''
Change note of ISCRSB from ''SCR power pattern; fSYS_SCR = 20MHz; TJ=150°C'' to ''SCR power pattern incl.
PMS current consumption with fback clock active; fSYS_SCR = 20MHz; TJ=150°C''
–
–
Change typ value of ISCRSB from 0.025 mA to 0.190 mA
Change note of ISCRSB from 'real power pattern; fSYS_SCR = 70kHz; TJ=25°C' to 'SCR power pattern incl.
PMS current consumption with fback inactive; fSYS_SCR = 70kHz; TJ=25°C'
–
Change note of ISCRSB from ''SCR 8-bit Standby Controller in STANDBY Mode drawn at VEVRSB supply pin''
to ''SCR 8-bit Standby Controller current incl. PMS in STANDBY Mode drawn at VEVRSB supply pin''
–
–
Change note of IDDM from '66 mA' to '32 mA'
Change note of IDDM from ''real power pattern ; current for EDSADC module only; 11 EDSADC channels
active.'' to ''real power pattern; current for EDSADC modules only and EVADC modules are inactive; 8
EDSADC channels active continuously.''
–
Change note of IDDM from '60 mA' to '45 mA'
Data Sheet
395
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
–
–
Change note of IDDM from ''max power pattern; All EDSADC channels active 100% time.'' to ''max power
pattern; current for EDSADC modules only and EVADC modules are inactive; all EDSADC channels active
continuously.''
Change note of IDDM from 'real pattern;12 EVADC modules active' to 'real power pattern; current for EVADC
modules only and EDSADC modules are inactive; 12 EVADC modules active.'
–
–
Change max value of IDDM from 21 mA to 20 mA
Change note of IDDM from 'max power pattern; All EVADC modules are active 100% time' to 'max power
pattern; current for EVADC modules only and EDSADC modules are inactive; all EVADC modules active.'
–
–
–
–
–
–
–
Change max value of IDDM from 56 mA to 48 mA
Change max value of ISLEEP from 10 mA to 25 mA
Change max value of IDDTOT from 924 mA to 978 mA
Change max value of PD from t.b.d. mW to 1700 mW
Change max value of PD from t.b.d. mW to 2400 mW
Change note of IDDTOTDC5 from 't.b.d mA' to '440 mA'
Change note of IDDTOTDC5 from ''real power pattern; VEXT = 5V; TJ=150°C'' to ''real power pattern; EVRC
reset settings with 72% efficiency; VEXT = 5V; TJ=150°C''
–
Change description of IDDTOTDC5 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum
of all currents with DC-DC EVRC regulator active'
–
–
Change max value of IDDTOTDC3 from t.b.d. mA to 580 mA
Change note of IDDTOTDC3 from 'real power pattern; VEXT = 3.3V; TJ=150°C' to 'real power pattern; EVRC
reset settings with 72% efficiency; VEXT = 3.3V; TJ=150°C'
–
Change description of IDDTOTDC3 from '∑ Sum of all currents with DC-DC EVR13 regulator active' to '∑ Sum
of all currents with DC-DC EVRC regulator active'
–
–
Change max value of IEVRSB from 4 mA to 8 mA
Change note of IDDPORST from '430 mA' to '490 mA'
•
Reset
–
–
Change min value of tPOH from 100 ns to 150 ns
Change note of tBP from 'dV/dT=1V/ms. including EVR ramp-up and Firmware execution time; RAM
initialization and HSM boot time is not included' to 'dVEXT/dT=1V/ms. VEXT>VLVDRST5. Boot time
after Cold PORST including EVR ramp-up and Firmware execution time; RAM initialization and HSM boot
time are not included.'
–
Change note of tB from 'operating with max. frequencies' to 'operating with max. frequencies, with valid BMI
header'
–
–
Change note of tBS from '' to 'RAM initialization and HSM boot time are not included, with valid BMI header'
Change note of tBP from 'Firmware execution time; without EVR ramp-up; RAM initialization and HSM boot
time is not included' to 'Firmware execution time after warm PORST without EVR ramp-up; RAM
initialization and HSM boot time is not included'
–
–
Change type of tPOA from CC to SR
Change description of tPOA from 'Minimum PORST active hold time externally after power supplies are
stable at operating levels' to 'Minimum PORST active hold time externally after power supplies are stable
at operating levels after start-up'
•
PMS/EVR33 LDO
–
–
–
Change min value of COUT from 0.65 µF to 1.45 µF
Change note of COUT from '1.35 µF' to '3 µF'
Change note of COUT from '1 µF' to '2.2 µF'
Data Sheet
396
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.4 to Version 0.6
–
–
–
–
Change min value of dVout/dIout from -100 mV to -180 mV
Change max value of dVout/dIout from 100 mV to 180 mV
Change note of IMAX from '100 mA' to '60 mA'
Change note of dVout/dVin from 'dVin/dT=50V/ms; dV= 5 to 3.6V' to 'dVin/dT=50V/ms; dV= 5 to 3.6V;
I
MAX=60mA'
Change note of dVout/dVin from 'dVin/dT=50V/ms; dV= 3.6 to 5V' to 'dVin/dT=50V/ms; dV= 3.6 to 5V;
MAX=60mA'
PMS/Supply Monitors
–
I
•
•
–
–
Change note of VLVDRST5 from '2.7 V' to '2.75 V'
Change note of VLVDRST5 from '2.67 V' to '2.72 V'
PMS/Supply Ramp
–
–
–
–
Change description of SR_V_EXT from 'External VEXT & VEVRSB supply ramp' to 'External VEXT & VEVRSB
supply ramp-up and ramp-down slope'
Change description of SR_V_DDP3 from 'External VDDP3 supply ramp' to 'External VDDP3 supply ramp-up
and ramp-down slope'
Change description of SR_V_DD from 'External VDD supply ramp' to 'External VDD supply ramp-up and
ramp-down slope'
Change description of SR_V_DDM from 'External VDDM supply ramp' to 'External VDDM supply ramp-up
and ramp-down slope'
•
•
Changes in table 'EVRC SMPS' of PMS/EVRC SMPS
Change name of EVRC SMPS from EVR13 SMPS to EVRC SMPS
Changes in table 'EVRC SMPS External components' of PMS/EVRC SMPS
–
–
Change name of EVRC SMPS External components from EVR13 SMPS External components to
EVRC SMPS External components
•
•
Changes in section JTAG Parameters
Update figure Test Clock Timing (TCK)
Changes in section DAP Parameters
–
–
Combine figures Test Clock Timing (DAP0), DAP Timing Host to Device, and DAP Timing Device to Host
(DAP1 and DAP2 pins) into single figure DAP Timing
–
–
–
Add t14 for condition F=40MHz
Add t15 for condition F=40MHz
Add t16 for condition F=40MHz
•
Changes in table 'Master Mode strong sharp (ss) output pads' of ASCLIN
–
–
–
Change min value of t51 from -3 ns to -3.5 ns
Change max value of t51 from 3 ns to 3.5 ns
Change max value of t510 from 3 ns to 3.5 ns
•
•
•
Changes in table 'Master Mode Timing, LVDS output pads for data and clock' of QSPI
–
–
Change note of t51 from '3 ns' to '4 ns'
Change note of t52 from '17 ns' to '18 ns'
Changes in table 'Strong sharp (ss) driver for clock/data valid for 5V' of MSC
–
–
Change min value of t45 from -3 ns to -4 ns
Change note of t44 from '-3 ns' to '-4 ns'
Changes in table 'ETH RGMII Signal Timing Parameters valid for 3.3V' of Ethernet
Data Sheet
397
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.6 to Version 0.7
–
Add parameter t21
•
Changes in table 'ETH RMII Signal Timing Parameters valid for 3.3V' of Ethernet
–
–
Change description of t16 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; setup
time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; setup time'
Change description of t17 from 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; hold
time' to 'ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV; hold time'
•
•
Changes in table 'HSCT - Rx/Tx setup timing' of LVDS Pads
Change max value of ttx from 250 ns to 280 ns
Flash
–
–
Change note of tER_Dev from ''Derived value for documentation purpose'' to ''Valid for less than 1000 cycles,
w/o UCB. Derived value for documentation purpose.''
Change note of tER_Dev from '17.8 s' to '11.5 s'
Change max value of tPRPB5_PF from 16 s to 10 s
–
–
•
Package Parameters
–
–
–
Update table Thermal Characteristics of the Package
Change package type from PG-LFBGA-516-9 to PG-LBGA-516-1
Change package type from PG-LFBGA-292-9 to PG-LFBGA-292-11
4.2
Changes from Version 0.6 to Version 0.7
•
•
•
•
•
•
•
Changed step description from “AA” to “AB”
Update of Data Flash to 512 KB in “Platform Feature Overview”
Update AGBT to “no” in Platform feature overview table
“BBB frequency” from table “Operating Conditions
Update Ctrl. for Pin ESR0
Update Ctrl. for Pin ESR1
Absolute Maximum Ratings
–
Change description of VDDM from 'Voltage at VDDM, VEXT and VFLEX power supply pins with respect to VSS'
to 'Voltage at VDDM, VEXT, VFLEX and VEVRSB power supply pins with respect to VSS'
•
Changes in table 'Overload Parameters' of Overload
–
–
–
Change note of IIN from 'except LVDS pins' to 'except LVDS pins; limited to max. Operation Livetime hours'
Change note of IINLVDS from '' to 'limited to max. Operation Livetime hours'
Change note of IID from 'All power supply voltages VDDx = 0' to 'All power supply voltages VDDx = 0; limited
to max. Inactive Livetime hours'
–
Change note of IOUT from '100% duty cycle; output driver = strong' to '100% duty cycle; output driver =
strong; limited to max. Operation Livetime hours'
–
Change of “Pin Reliability in Overload” praeamble
•
Changes in table 'Slow 3.3V GPIO' of Standard Pads
–
–
Change note of VIL from '0.44 * VEXT/FLEX V' to '0.42 * VEXT/FLEX V'
Change note of IPUH from 'VIH; AL and TTL (degraded, used for CIF); exept VGATE1P and TJ > 150°C' to
'VIH; AL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ > 150°C'
Data Sheet
398
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.6 to Version 0.7
–
Change note of IPUH from 'VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P and TJ >
150°C' to 'VIL; AL and TTL and TTL (degraded, used for CIF); exept VGATE1P; except VGATE1N and TJ
> 150°C'
–
–
Change note of IPUH from 'VIH; TTL; exept VGATE1P and TJ > 150°C' to 'VIH; TTL; exept VGATE1P; except
VGATE1N and TJ > 150°C'
Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the
configuration active'
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Change min value of IOZ from -200 nA to -300 nA
Change max value of IOZ from 200 nA to 300 nA
Change min value of IOZ from -250 nA to -400 nA
Change max value of IOZ from 250 nA to 400 nA
Change min value of IOZ from -300 nA to -600 nA
Change max value of IOZ from 300 nA to 600 nA
Change min value of IOZ from -500 nA to -750 nA
Change max value of IOZ from 500 nA to 750 nA
Change min value of IOZ from -350 nA to -300 nA
Change max value of IOZ from 350 nA to 300 nA
Change min value of IOZ from -550 nA to -400 nA
Change max value of IOZ from 550 nA to 400 nA
Change min value of IOZ from -700 nA to -600 nA
Change max value of IOZ from 700 nA to 600 nA
Change min value of IOZ from -1100 nA to -750 nA
Change max value of IOZ from 1100 nA to 750 nA
Change max value of IOZ from 11000 nA to 18000 nA
Change note of IOZ from '-11000 nA' to '-18000 nA'
Change max value of IOZ from 22000 nA to 38000 nA
Change min value of IOZ from -22000 nA to -38000 nA
•
•
Changes in table 'RFast 3.3V pad' of Standard Pads
–
–
Change note of VIL from '0.44 * VEXT/FLEX V' to '0.42 * VEXT/FLEX V'
Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the
configuration active'
Changes in table 'Fast 3.3V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
–
Change note of VIL from '0.44 * VEXT/FLEX V' to '0.42 * VEXT/FLEX V'
Change note of IOZ from '-750 nA' to '-1100 nA'
Change note of IOZ from '750 nA' to '1100 nA'
Change min value of IOZ from -5000 nA to -6000 nA
Change note of IOZ from '5000 nA' to '6000 nA'
Change min value of IOZ from -1300 nA to -2000 nA
Change max value of IOZ from 1300 nA to 2000 nA
Change min value of IOZ from -2000 nA to -2500 nA
Change note of IOZ from '2000 nA' to '2500 nA'
Change max value of IOZ from 9000 nA to 13500 nA
Change min value of IOZ from -9000 nA to -13500 nA
Data Sheet
399
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.6 to Version 0.7
–
–
–
–
–
Change note of IOZ from '-2300 nA' to '-1100 nA'
Change min value of IOZ from -5000 nA to -2000 nA
Change note of IOZ from '2300 nA' to '1100 nA'
Change max value of IOZ from 5000 nA to 2000 nA
Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the
configuration active'
•
Changes in table 'Fast 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Change max value of IOZ from 750 nA to 1100 nA
Change min value of IOZ from -750 nA to -1100 nA
Change min value of IOZ from -5000 nA to -6000 nA
Change max value of IOZ from 5000 nA to 6000 nA
Change note of IOZ from '-1300 nA' to '-2000 nA'
Change max value of IOZ from 1300 nA to 2000 nA
Change min value of IOZ from -2000 nA to -2500 nA
Change max value of IOZ from 2000 nA to 2500 nA
Change note of IOZ from '9000 nA' to '13500 nA'
Change min value of IOZ from -9000 nA to -13500 nA
Change note of IOZ from '-2300 nA' to '-1100 nA'
Change note of IOZ from '-5000 nA' to '-2000 nA'
Change max value of IOZ from 2300 nA to 1100 nA
Change max value of IOZ from 5000 nA to 2000 nA
Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the
configuration active'
•
Changes in table 'Slow 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
Change note of IOZ from '-250 nA' to '-400 nA'
Change max value of IOZ from 250 nA to 400 nA
Change min value of IOZ from -350 nA to -600 nA
Change max value of IOZ from 350 nA to 600 nA
Change note of IOZ from '500 nA' to '750 nA'
Change note of IOZ from '-500 nA' to '-750 nA'
Change min value of IOZ from -200 nA to -300 nA
Change max value of IOZ from 200 nA to 300 nA
Change note of IPUH from 'VIH; AL or TTL; exept VGATE1P and TJ > 150°C' to 'VIH;AL or TTL; exept
VGATE1P; except VGATE1N and TJ > 150°C'
–
–
Change note of IPUH from 'VIL; AL or TTL; exept VGATE1P and TJ > 150°C' to 'VIL; AL or TTL; exept
VGATE1P; except VGATE1N and TJ > 150°C'
Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the
configuration active'
–
–
–
–
–
Change min value of IOZ from -350 nA to -300 nA
Change max value of IOZ from 350 nA to 300 nA
Change min value of IOZ from -550 nA to -400 nA
Change note of IOZ from '550 nA' to '400 nA'
Change min value of IOZ from -700 nA to -600 nA
Data Sheet
400
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.6 to Version 0.7
–
–
–
–
–
–
–
Change max value of IOZ from 700 nA to 600 nA
Change min value of IOZ from -1100 nA to -750 nA
Change max value of IOZ from 1100 nA to 750 nA
Change max value of IOZ from 11000 nA to 18000 nA
Change min value of IOZ from -11000 nA to -18000 nA
Change note of IOZ from '22000 nA' to '38000 nA'
Change min value of IOZ from -22000 nA to -38000 nA
•
Changes in table 'Class S 5V' of Standard Pads
–
Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the
configuration active'
–
–
–
–
Change min value of IOZ from -350 nA to -300 nA
Change note of IOZ from '350 nA' to '300 nA'
Change min value of IOZ from -700 nA to -600 nA
Change max value of IOZ from 700 nA to 600 nA
•
Changes in table 'Class D' of Standard Pads
–
–
–
–
Change min value of IOZ from -350 nA to -300 nA
Change max value of IOZ from 350 nA to 300 nA
Change min value of IOZ from -700 nA to -600 nA
Change max value of IOZ from 700 nA to 600 nA
•
•
Changes in table 'RFast 5V GPIO' of Standard Pads
–
Change description of tSET from 'Pad set-up time' to 'Pad set-up time to get an software update of the
configuration active'
Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)' of LVDS Pads
–
–
Add parameter tSET_LVDS
Change note of Rin from '1600 mV < VI ≤ 2000 mV' to 'VI ≤ 2000 mV'
•
VADC 5V
–
–
–
–
–
–
–
Add parameter dVDDK
Change note of VDDK from '' to 'Measured at low temperature.'
Change note of tSCAL from '4.5V ≤ VDDM ≤ 5.5V' to '4.5 V ≤ VDDM ≤ 5.5 V'
Change note of fADCI from '4.5V ≤ VDDM ≤ 5.5V' to '4.5 V ≤ VDDM ≤ 5.5 V'
Change note of RPDD from '' to 'Measured at pad input voltage VIN = VDDM / 2.'
Change note of tSCAL from '2.97V ≤ VDDM < 4.5V' to '2.97 V ≤ VDDM < 4.5 V'
Change note of tS from 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled'
to 'Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled'
–
–
Change note of fADCI from '2.97V ≤ VDDM < 4.5V' to '2.97 V ≤ VDDM < 4.5 V'
Change note of tS from 'Primary group or fast compare channel, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled'
to 'Primary group or fast compare channel, 4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled'
–
–
–
Change note of tS from 'Secondary group, 4.5V ≤ VDDM ≤ 5.5V; input buffer disabled' to 'Secondary group,
4.5 V ≤ VDDM ≤ 5.5 V; input buffer disabled'
Change note of tS from 'Secondary group, 4.5V ≤ VDDM ≤ 5.5V; input buffer enabled' to 'Secondary group,
4.5 V ≤ VDDM ≤ 5.5 V; input buffer enabled'
Change note of tS from 'Primary Group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer disabled'
to 'Primary Group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer disabled'
Data Sheet
401
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.6 to Version 0.7
–
–
–
–
Change note of tS from 'Primary group or fast compare channel, 2.97V ≤ VDDM < 4.5V; input buffer enabled'
to 'Primary group or fast compare channel, 2.97 V ≤ VDDM < 4.5 V; input buffer enabled'
Change note of tS from 'Secondary group, 2.97V ≤ VDDM < 4.5V; input buffer disabled' to 'Secondary group,
2.97 V ≤ VDDM < 4.5 V; input buffer disabled'
Change note of tS from 'Secondary group, 2.97V ≤ VDDM < 4.5V; input buffer enabled' to 'Secondary group,
2.97 V ≤ VDDM < 4.5 V; input buffer enabled'
Change of “VADC Parameters” praeamble
•
DSADC 5V
–
–
Add parameter RBIAS
Change type of IREF from SR to CC
•
•
•
Changes in table 'DTS Core' of DTS
Add parameter ΔT
Current Consumption
Change max value of IDDP3RAIL from '60 mA' to '50 mA'
Changes in table 'Module Current Consumption' of Current Consumption
–
–
–
–
–
Change max value of IDDP3ERASE from 20 mA to 25 mA
Add parameter IDDP3ERASE
Change description of IDDP3ERASE from 'Current adder for' to 'IDDP3 supply current for erasing of a Pflash or
Dflash bank'
–
–
–
–
–
–
–
–
Change typ value of ISCRSB from 0.190 mA to 0.150 mA
Change max value of IDDP3PROG from '8 mA' to '9 mA'
Change max value of IDDP3PROG from '20 mA' to '25 mA'
Change max value of ISCRSB from '6.5 mA' to '7 mA'
Change max value of ISCRIDLE from '1 mA' to '3.5 mA'
Change max value of IDDPORST from ''real power pattern; TJ=125°C'' to ''VDD = 1.275V; TJ=125°C''
Change max value of IDDPORST from '190 mA' to '185 mA'
Change max value of ISLEEP from 25 mA to 27 mA
•
Changes in table 'Module Core Current Consumption' of Current Consumption
–
–
–
–
–
–
–
Change max value of IDDGTM from 120 mA to 125 mA
Change note of IDDPORST from 'real power pattern; TJ=150°C' to 'VDD = 1.275V; TJ=150°C'
Change max value of IDDPORST from 340 mA to 320 mA
Change note of IDDPORST from 'real power pattern; TJ=160°C' to 'VDD = 1.275V; TJ=160°C'
Change max value of IDDPORST from 450 mA to 400 mA
Change note of IDDPORST from ''real power pattern; TJ=165°C'' to ''VDD = 1.275V; TJ=165°C''
Change note of IDDPORST from '490 mA' to '430 mA'
•
Reset
–
–
Change max value of tBS from 1 ms to 1.05 ms
Change note of tBP from 'Firmware execution time after warm PORST without EVR ramp-up; RAM
initialization and HSM boot time is not included' to 'Firmware execution time after PORST release without
EVR ramp-up; RAM initialization and HSM boot time is not included'
–
–
–
Change description of tBP from 'Power on Reset Boot Time' to 'Cold Power on Reset Boot Time'
Change note of tLBIST from 'PATTERNS=0x00040, FREQU=5, SPLITSH=4' to 'LBIST Configuration A'
Removed parameter tLBIST with note 'PATTERNS=0x00280, FREQU=5, SPLITSH=4'
Data Sheet
402
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.6 to Version 0.7
•
PMS/EVR33 LDO
–
Change note of dVout/dVin from ''dVin/dT=1V/ms; dV= 3.6 to 5V'' to ''dVin/dT=1V/ms; dV= 3.6 to 5V;
ΔVOUTTC is included''
–
–
–
Change note of dVout/dVin from '20 mV' to '40 mV'
Change min value of dVout/dVin from -20 mV to -40 mV
Change note of dVout/dVin from 'dVin/dT=1V/ms; dV= 5 to 3.6V' to 'dVin/dT=1V/ms; dV= 5 to 3.6V;
ΔVOUTTC is included'
–
–
Add parameter dVOUTTC
Change note of tSTR from '' to 'Normal RUN mode'
•
•
•
PMS/Supply Monitors
Change max value of VRSTC from 1.135 V to 1.138 V
Changes in table 'EVRC SMPS' of PMS/EVRC SMPS
Change max value of ΔVDDDC from 12 mV to 16 mV
PLL Peripheral
–
–
–
–
–
Add parameter JABS25
Change note of DP from 'fDCO = 640 MHz' to 'fDCO = 640 MHz or fDCO = 800 MHz'
Change note of DRMS from 'measured over 1 µs; fREF = 20 MHz; fDCO = 640 MHz' to 'measured over 1 µs;
f
REF = 20 MHz and fDCO = 640 MHz or fREF = 25 MHz and fDCO = 800 MHz'
•
Flash
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Change note of NE_HSMS from 'Max. data retention time 10 years' to 'max data retention time 20y, Tj=85°C'
Change note of NE_EEP10S from 'Max. data retention time 10 years' to 'max data retention time 20y, Tj=85°C'
Add parameter NE_EEP10S
Change max value of NE_EEP10S to 125000 cycles
Add parameter NE_EEP10S
Change max value of NE_EEP10S to 125000 cycles
Add parameter NE_EEP10S
Change max value of NE_EEP10S to 70000 cycles
Add parameter NE_HSMS
Change max value of NE_HSMS to 125000 cycles
Add parameter NE_HSMS
Change max value of NE_HSMS to 125000 cycles
Add parameter NE_HSMS
Change max value of NE_HSMS to 70000 cycles
Add inactive time to Table 3-75 “Example Temperature Profile”
•
Package Parameters
–
–
–
–
–
–
–
Update table layout for table 3-67
Change max value of RTH_JA from 14,8 K/W to 17 K/W
Change max value of RTH_JA from 12 K/W to 14 K/W
Change name of RTH_JA from Thermal resistance (junction to ambient) to RTH_JA
Change description of RTH_JA from '' to 'Thermal resistance (junction to ambient)'
Change max value of RTH_JCT from 4.5 K/W to 3 K/W
Change max value of RTH_JCT from 4.7 K/W to 3 K/W
Data Sheet
403
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.7 to Version 0.71
–
–
–
Change max value of RTH_JCB from 2.8 K/W to 2 K/W
Change description of RTH_JCB from '' to 'Thermal resistance (junction to case bottom)'
Change note of RTH_JCB from '3.5 K/W' to '2 K/W'
4.3
Changes from Version 0.7 to Version 0.71
•
Pinning
–
–
Corrected descriptions of HSCT pins
Corrected descriptions of CCU_PAD_SYSCLK pin
•
•
Summary of Features
Included RGMII in the Ethernet description
Platform feature overview
–
–
–
–
Corrected number of SDMMC modules from ‘1’ to ‘0’
Corrected the value of MCDS from “yes” to “no”
Corrected number of QSPI modules from ‘6’ to ‘5’
•
•
Corrected ‘LVDSH’ to ‘LVDS’ in Section ‘High performance LVDS Pads’
Changes in table "Absolute Maximum Ratings"
–
–
Change value of Parameter "VDDM"
Change value of Parameter "VIN"
•
•
Change preamble of Section "Overload"
Changes in table "Overload Parameters" of Section "Overload"
–
–
–
–
–
Change condition of Parameter "IIN"
Change condition of Parameter "IINLVDS"
Change condition of Parameter "IOUT"
Change condition of Parameter "IINANA"
Delete Parameter "IID"
•
•
•
•
•
•
•
•
Changes in table "PORST Pad" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VEXT”
Changes in table "Class S" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VDDM”
Changes in table "RFast 3.3V pad" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VFLEX”
Changes in table "RFast 5V pad" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VFLEX”
Changes in table "Fast 3.3V pad" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB”
Changes in table "Fast 5V pad" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB”
Changes in table "Slow 3.3V pad" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB”
Changes in table "Slow 5V pad" of Section "Switchable Pads"
Change reference voltage of Parameters and values from "VEXT/FLEX" to “VEXT/FLEX/EVRSB”
–
–
–
–
–
–
–
–
Data Sheet
404
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.7 to Version 0.71
•
•
Changes in table "VADC 5V"
–
–
Add footnote to Parameter "QCON"
Update picture ‘Equivalent Circuitry for Analog Inputs’
Changes in table "DSADC 5V"
–
–
–
–
–
–
–
–
Change value of Parameter "EDGAIN"
Change value of Parameter "EDOFF"
Add footnote to Parameter "EDOFF"
Change value of Parameter "IREF"
Change value of Parameter "IRMS"
Add footnote to Parameter "IRMS"
Add footnote to Parameter "SNR"
Add footnote to Parameter "SFDR"
•
•
Changes in table "Current Consumption"
–
–
–
–
Change Parameter description of "IDDRAIL"
Change condition of Parameter "ISTANDBY"
Change value of Parameter "ISTANDBY"
Change footnote of Parameter "ISTANDBY"
Changes in table "Module Core Current Consumption" of Section "Current Consumption"
–
–
–
–
–
Change condition of Parameter "IDDLBIST"
Change value of Parameter "IDDLBIST"
Add footnote to Parameter "IDDLBIST"
Add footnote to Parameter “ISCRSB”
Change condition of Parameter "IDDMBIST"
•
•
Added section "Calculating the 1.25V Current Consumption"
Changes in table "Reset"
–
–
–
–
–
–
Change value of Parameter "tB"
Change value of Parameter "tBS"
Add footnote to Parameter "tEVRPOR"
Change value of Parameter "tBWP"
Change condition of Parameter "tLBIST"
Change Parameter description of "tLBIST"
•
•
Changes in table "EVR33 LDO"
–
–
–
Change condition of Parameter "dVout/dIout"
Change condition of Parameter "Vout/dVin"
Change footnote of Parameter "IMAX"
Changes in table "Supply Monitors"
–
–
–
–
–
–
Change condition of Parameter "tMON"
Change condition of Parameter"VDDMON"
Change condition of Parameter "VDDP3MON"
Change condition of Parameter "VEXTMON"
Add footnote to Parameter "VEXTMON"
Change condition of Parameter "VRST5"
Data Sheet
405
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.71 to Version 1.0
•
•
Changes in table "Flash"
–
–
–
–
Change condition of Parameter "NE_EEP10S"
Remove condition of Parameter "NE_EEP10S"
Change condition of Parameter "NE_HSMS"
Remove condition of Parameter "NE_HSMS"
Changes in table "Quality Parameters" of Section "Quality Declarations"
Change Parameter description of "VHBM1"
–
•
•
Add Section "TC380 Carrier Tape"
OSC_XTAL
–
–
Removed parameter VILBX
Removed parameter VIHBX
•
•
Changes in table "Back-up Clock"
Update footnote of Parameters “fBACKT"
Changes in table "PLL Peripheral"
–
–
–
Add Parameters “DPP"
Add Parameters “DPPI"
•
Changes in table "Receive Parameters" of “E-ray Parameters”
–
Update Parameters description of “tdCCRxD01"
4.4
Changes from Version 0.71 to Version 1.0
•
•
•
Changes in chapter “Summary of Features”
Changed LMU Memory size from 128 Kbyte to 256 Kbyte
Pinning
–
–
Corrected descriptions of Column “Buffer Type”: PU2
Changes in chapter Electrical Specification
–
–
–
Corrected/ added wording in sub-chapter 3.1 “Parameter Interpretation”
Added naming for temperature value, table 3-66, Example Operation Lifetime Profile
Changed naming for sub-chapter 3.16, from Phase Locked Loop (PLL) to System Phase Locked Loop
(SYS_PLL)
–
corrected temperature in “Summary of Features” section
•
•
•
Changes in Absolute Maximum Table
Add footnote 2) to VDD
Changes in Operating Conditions Table
Add footnote 1) to VDD
Changes in table 'PORST Pad' of Standard Pads
–
–
–
–
Change min value of HYS from 0.055 * VEXT/FLEX V to 0.055 * VEXT V
Change note of IOZ from 'TJ≤150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ≤150°C ; (0.1 * VEXT
< VIN < (0.9 * VEXT)'
)
–
–
Changed footnote 1) from 10% to 90% VEXT/FLEX 10% to 90% pad supply voltage
Add footnote 2) to IPDL
Data Sheet
406
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.71 to Version 1.0
–
–
Add parameter VIH for condition TTL, VEXT
Add parameter VIL for condition TTL, VEXT
•
•
•
•
•
Changes in table 'Fast 5V GPIO' of Standard Pads
–
–
–
Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V
Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VEXT/FLEX/EVRSB V'
Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms;
VEXT/FLEX/EVRSB = constant; AL'
–
–
–
Combined equal values of IOZ in single line
Add footnote 4) to IPUH
Add footnote 5) to IPDL
Changes in table 'Fast 3.3V GPIO' of Standard Pads
–
–
–
Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V
Change note of VIL from '0.42 * VEXT/FLEX V' to '0.42 * VEXT/FLEX/EVRSB V'
Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms;
VEXT/FLEX/EVRSB = constant; AL'
–
–
–
Combined equal values of IOZ in single line
Add footnote 4) to IPUH
Add footnote 5) to IPDL
Changes in table 'Slow 5V GPIO' of Standard Pads
–
–
–
Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V
Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VEXT/FLEX/EVRSB V'
Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms;
VEXT/FLEX/EVRSB = constant; AL'
–
–
–
Combined equal values of IOZ in single line
Add footnote 4) to IPUH
Add footnote 5) to IPDL
Changes in table 'Slow 3.3V GPIO' of Standard Pads
–
–
–
Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VEXT/FLEX/EVRSB V
Change note of VIL from '0.42 * VEXT/FLEX V' to '0.42 * VEXT/FLEX/EVRSB V'
Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms;
VEXT/FLEX/EVRSB = constant; AL'
–
–
–
Combined equal values of IOZ in single line
Add footnote 4) to IPUH
Add footnote 5) to IPDL
Changes in table 'RFast 5V GPIO' of Standard Pads
–
–
–
–
–
Change min value of HYS from 0.09 * VEXT/FLEX V to 0.09 * VFLEX V
Change note of HYS from '0.075 * VEXT/FLEX V' to '0.075 * VFLEX V'
Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VFLEX V
Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VFLEX V'
Change note of tRF from 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' to
'CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX
'
–
Change note of IOZ from 'TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ ≤ 170°C ; (0.1 * VFLEX
< VIN < (0.9 * VFLEX)'
)
Data Sheet
407
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.71 to Version 1.0
–
–
Change note of IOZ from 'TJ ≤ 150°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ ≤ 150°C ; (0.1 * VFLEX
< VIN < (0.9 * VFLEX)'
)
Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VFLEX
=
constant; AL'
–
–
Add footnote 4) to IPUH
Add footnote 5) to IPDL
•
Changes in table 'RFast 3.3V pad' of Standard Pads
–
–
–
–
–
–
Change min value of HYS from 0.055 * VEXT/FLEX V to 0.055 * VFLEX V
Change min value of HYS from 0.09 * VEXT/FLEX V to 0.09 * VFLEX V
Change min value of HYS from 0.055 * VEXT/FLEX V to 0.055 * VFLEX V
Change note of VIH from '0.7 * VEXT/FLEX V' to '0.7 * VFLEX V'
Change note of VIL from '0.42 * VEXT/FLEX V' to '0.42 * VFLEX V'
Change note of tRF from 'CL = 25pF; driver = strong sharp edge; from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX' to
'CL = 25pF; driver = strong sharp edge; from 0.2 * VFLEX to 0.8 * VFLEX
'
–
–
Change note of IOZ from 'TJ ≤ 170°C ; (0.1 * VEXT/FLEX) < VIN < (0.9 * VEXT/FLEX)' to 'TJ ≤ 170°C ; (0.1 * VFLEX
< VIN < (0.9 * VFLEX)'
)
Change note of VILD from 'max. variation of 1ms; VDDM = constant; AL' to 'max. variation of 1ms; VFLEX
=
constant; AL'
–
–
Add footnote 4) to IPUH
Add footnote 5) to IPDL
•
Changes in table 'Class S 5V' of Standard Pads
–
–
–
–
–
–
Change min value of HYS from 0.09 * VEXT/FLEX V to 0.09 * VDDM V
Change min value of HYS from 0.075 * VEXT/FLEX V to 0.075 * VDDM V
Change min value of VIH from 0.7 * VEXT/FLEX V to 0.7 * VDDM V
Change note of VIL from '0.44 * VEXT/FLEX V' to '0.44 * VDDM V'
Add footnote 2) to IPUH
Add footnote 3) to IPDL
•
•
Add table 'Class S 3.3V' of Standard Pads
Changes in table 'ADC Reference Pads' of Standard Pads
–
–
–
–
–
–
–
Change note of IOZ2 from 'TJ ≤ 150°C; VAREF ≤ VDDM+50mV; used for EVADC' to 'TJ ≤ 150°C; VAREF
DDM+50mV; for EVADC; valid for BGA516 and Bare Die'
≤
V
Change note of IOZ2 from 'TJ ≤ 150°C; VAREF < VDDM; used for EDSADC' to 'TJ ≤ 150°C; VAREF < VDDM; for
EDSADC'
Change note of IOZ2 from 'TJ ≤ 150°C; VAREF ≤ VDDM+50mV; used for EDSADC' to 'TJ ≤ 150°C; VAREF
DDM+50mV; for EDSADC'
≤
V
Change value of IOZ2 from 'TJ ≤ 150°C; VAREF < VDDM; used for EVADC' to 'TJ ≤ 150°C; VAREF < VDDM; for
EVADC; valid for BGA516 and Bare Die'
Change note of IOZ2 from 'TJ ≤ 170°C; VAREF < VDDM; used for EDSADC' to 'TJ ≤ 170°C; VAREF < VDDM; for
EDSADC'
Change note of IOZ2 from 'TJ ≤ 170°C; VAREF ≤ VDDM+50mV; used for EDSADC' to 'TJ ≤ 170°C; VAREF
DDM+50mV; for EDSADC'
Change note of IOZ2 from 'TJ ≤ 170°C; VAREF ≤ VDDM+50mV; used for EVADC' to 'TJ ≤ 170°C; VAREF
DDM+50mV; for EVADC; valid for BGA516 and Bare Die'
≤
V
≤
V
Data Sheet
408
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.71 to Version 1.0
–
Change note of IOZ2 from 'TJ ≤ 170°C; VAREF < VDDM; used for EVADC' to 'TJ ≤ 170°C; VAREF < VDDM; for
EVADC; valid for BGA516 and Bare Die'
–
–
–
–
Added values for IOZ2
Add footnote 1)
Add footnote 2)
Add footnote 3)
•
•
LVDS - IEEE standard LVDS general purpose link (GPL)
–
–
–
–
–
Added footnote 1) for max. value trise20
Added footnote 2) for max. value tfall20
Changed footnote number 1) for VOD to footnote number 3)
Changed footnote number 2) for VODSM to footnote number 4)
Changed marking in figure 'LVDS Input model' from 'LVDSH IN' to 'LVDS IN'
VADC 5V
–
–
–
–
–
–
–
Change note of VAREF from '' to '4.5 V ≤ VDDM ≤ 5.5 V'
Change min value of VAREF from VDDMnom * 0.9 V to 4.5 V
Add min value of VAREF
Add typ value of VAREF
Add max value of VAREF
Add note of VAREF to '2.97 V ≤ VDDM ≤ 4.5 V'
Add footnote 1)
•
•
DSADC 5V
–
–
Change min value of VAREF from VDDMnom * 0.9 V to 4.5 V
Add max value of IREF at high temperature
OSC_XTAL
–
–
–
–
Add parameter for DCx1
Add parameter for JABSX1
Add parameter for SRXTAL1
Add footnote 3)
•
Back-up Clock
–
–
Change min value of fSB from 30 kHz to 25 kHz
Change note of IfBACKT from 'A short term trimming providing the accuracy required by LIN communication
is possible by periodic trimming every 2 ms for temperature and voltage drifts ' to 'A short term trimming
providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms for
temperature and voltage drifts up to temperatures of 125 celcius'
•
•
•
DTS
–
Change note of TNL from ‘’ to ‘TCALACC has to be added in addition’
Power Supply Current
–
Changes in conditions from 'four lockstep cores' to 'two lockstep cores'
Current Consumption
–
–
–
Change max value of IDDPORST from '185 mA' to '160 mA'
Change max value of IDDPORST from '320 mA' to '290 mA'
Change max value of IDDPORST from '400 mA' to '350 mA'
Data Sheet
409
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 0.71 to Version 1.0
–
–
Change max value of IDDPORST from '430 mA' to '380 mA'
Changed footnote 3)
•
•
•
•
Module Current Consumption
Add parameter of IEXTLVDS for receive
Module Core Current Consumption
Changed footnote 1)
Changes in chapter “Calculating the 1.25 V Current Consumption”
Changes in formula (3.2)
Changes in chapter “Supply Ramp-up and Ramp-down Behavior”
–
–
–
–
–
Changed Figure and textual description for figure “Single Supply Mode (a) - VEXT (5 V) single supply”
Changed Figure and textual description for figure “Single Supply Mode (e) - (VEXT & VDDP3) 3.3 V single
supply”
–
–
Changed Figure and textual description for figure “Single Supply Mode (d) - VEXT and VDD externally
supplied”
Changed Figure and textual description for figure “Single Supply Mode (h) - VEXT, VDDP3 and VDD
externally supplied”
•
•
Reset Timing
–
Add parameter tWARMRSTSEQ
PMS/Supply Monitors
–
–
Changed min value of VEXTMON from '3.235 V to 3.2 V', and max value from '3.365 V' to '3.4 V'
Added footnote 5) for VDDMON
•
EVRC SMPS
–
–
Added typ. value of '0.8 MHz' and note for fDCDC
Added values for LDC for 'fDCDC = 0.8 MHz'
•
•
Add chapter FSP Parameters
PLL System
–
Deleted values for fMV for 'Modulation variation frequency'
Table 'Master Mode Timing'
Added footnote 1)
Table 'LVDS clock/data'
Added footnote 3)
Flash
•
•
•
–
–
–
–
–
–
Add parameter for NDFDC
Add parameter for NUCBD
Add parameter tVER_PAGE_DC
Change description of tVER_PAGE_DC from 'Data Flash Erase Verify time per page' to 'Data Flash Erase Verify
time per page (Complement Sensing)'
–
–
Change name of tVER_PAGE_DS from tVER_PAGE_D to tVER_PAGE_DS
Change description of tVER_PAGE_DS from 'Data Flash Erase Verify time per page' to 'Data Flash Erase Verify
time per page (Single Ended Sensing)'
–
Change note of tRTU from ’Max. 100 erase/program cycles per UCB, max 400 erase/program cycles
for all UCBs together’ to ‘Max. 100 erase/program cycles per UCB, max 500 erase/program cycles
for all UCBs together’
Data Sheet
410
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 1.0 to Version 1.1
•
•
Package Parameters
–
–
Change max value of RTH_JCT from 3 K/W to 5 K/W for LFBGA292
Change max value of RTH_JCT from 3 K/W to 5 K/W for LFBGA516
TC380 Carrier Tape
–
–
–
–
Added disclaimer for TC380
Changed X and Y values for 'TC380 Chip Dimensions'
Changed figure for 'Carrier Tape Dimensions'
Added accuracy value for 'TC380 Chip Dimensions'
•
Summary of Features
–
Removed ASIL value from table 'Platform Feature Overview'
4.5
Changes from Version 1.0 to Version 1.1
•
•
•
•
•
Changes in table “Platform Feature Overview” - changed package types
Changes on title page and chapter heads – AD/AE-Step”
Changes in table “Platform Feature Overview” – package naming spelling of LFBGA-516-1 and LFBGA-292-11
Change in table “Platform Feature Overview” – spelling of “HSPDM”
Chapter “Bare Die Variant Pin Configuration of TC38x” - added information concerning “neighbor pads” after
table “Pad List”
•
Changes in chapter “Legend”
–
–
–
Added information concerning I/O-Spirit file version
Changed refering IO_Spirit_file version
Changed explanation for PD2 = with pull-down device connected during startup and reset, HighZ in
Standby mode
•
•
Changes in table “Absolute Maximum Ratings”
–
–
Changed description for parameter “Absolute maximum sum”
Added footnote 5)
Changes in table 'Slow 5V GPIO' of Standard Pads
–
–
Changed conditions of parameter IOZ
Changed value of parameter VIL
•
•
•
Changes in table “Slow 3.3V GPIO” of Standard Pads
Changed conditions of parameter IOZ
Changes in table “RFast 3.3V pad” of Standard Pads
Deleted parameter for fIND
Changes in table “LVDS - IEEE standard LVDS general purpose link (GPL)” of LVDS Pads
–
–
–
–
–
–
–
Changed value of parameter VI
Changed condition of parameter Vidth
Added values for parameter Vidth
Changed condition of parameter Rin
Added notes/ hints to table footnotes for “Driver ground potential difference” and for parameter “RT”
•
Changes in table “VADC 5V”
Added condition for parameter VAIN
–
Data Sheet
411
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 1.1 to Version 1.2
•
Changes in table “DSADC 5V”
–
–
–
–
Added value for parameter IRMS
Changed footnotes of parameter EDGAIN
Changed footnotes of parameter EDOFF
Added footnote 4) for parameter EDGAIN
•
•
Changes in table “OSC_XTAL”
Changed footnote 1) for parameter tOSCS
Changes in table “Current Consumption”
–
–
–
–
Deleted footnote 1) for parameter IEXTFLEX
Changed value in footnote 1)
Changed explanation in footnote 6)
•
Changes in table “Module Current Consumption”
–
–
–
Changed values of parameter IEXTLVDS
Changed conditions of parameter IEXTLVDS
Changed value in footnote 6)
•
•
•
•
•
•
Changes in table “Reset”
Changed values of parameter tSCR
Changes in table “Supply Ramp”
Added note “power-cycles” to supply ramp table
Changes in table “EVRC SMPS”
Changed symbol for parameter “∆ fDCSPR
Changes in table “PLL System”
Changed value for parameter fREF
Changes in table “ETH RGMII Parameters”
Added figures for ETH RGMII TX and RX signals
Changes in table “Quality Parameters”
Changed value for parameter VHBM1
–
–
–
”
–
–
–
•
•
Changes in chapter “Package Outline” - changed package types
Changes in sub-chapter “TC380 Carrier Tape”
–
Changed number of figure “Carrier Tape Dimensions”
4.6
Changes from Version 1.1 to Version 1.2
•
Changes in chapter “Revision History”
Chronology completed
–
•
Changes in chapter “Summary of Features”
–
–
–
–
–
Changed wording for “DFLASH”
Added description for “AEC-Q100”
Added description for “ISO 26262 Safety Element”
Added description for Data Flash in table “Platform Feature Overview”
Changed figure for GTM clusters in table “Platform Feature Overview”
Data Sheet
412
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 1.1 to Version 1.2
–
–
Changed figures for GTM/CDTM/DTM modules in table “Platform Feature Overview”
Changed package type in table “Platform Feature Overview”
•
Changes in chapter “Pin Definition and Functions”
–
–
–
–
–
–
–
–
Changed EDSADC function description for Port 00 in “BGA-516 Package Variant” tables
Changed EDSADC function description for Port 01 in “BGA-516 Package Variant” tables
Changed EDSADC function description for Port 02 in “BGA-516 Package Variant” tables
Changed PSI5S function description for Port 02 in “BGA-516 Package Variant” tables
Deleted PMS parameter for Port 02 in “BGA-516 Package Variant” tables
Deleted SCU parameter at Port 10 in “BGA-516 Package Variant” tables
Added PMS parameter at Port 10 in “BGA-516 Package Variant” tables
Changed Buffer Type description for P11.5, P11.7, P11.8, P11.9, P11.10, P11.11, P11.12 at Port 11 in
“BGA-516 Package Variant” tables
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Changed function description for GETH at Port 11 in “BGA-516 Package Variant” tables
Changed function description for GTM at Port 11 in “BGA-516 Package Variant” tables
Deleted parameter for SCU at Port 14 in “BGA-516 Package Variant” tables
Added parameter for PMS at Port 14 in “BGA-516 Package Variant” tables
Changed function description for GTM at Port 14 in “BGA-516 Package Variant” tables
Changed function description for HSCT0 at Port 20 in “BGA-516 Package Variant” tables
Changed function description for GTM at Port 20 in “BGA-516 Package Variant” tables
Added function description for DMU at Port 21 in “BGA-516 Package Variant” tables
Changed function description for HSCT0 at Port 21 in “BGA-516 Package Variant” tables
Changed function description for GTM at Port 23 in “BGA-516 Package Variant” tables
Changed EDSADC function description for Port 33 in “BGA-516 Package Variant” tables
Changed function description for GTM at Port 33 in “BGA-516 Package Variant” tables
Changed PSI5S function description for Port 33 in “BGA-516 Package Variant” tables
Added notes to table “System I/O” for “BGA-516 Package Variant”
Changed “Ctrl.” information for balls M21, L21 in “System I/O” table for “BGA-516 Package Variant”
Changed function description for ball M22 in “System I/O” table for “BGA-516 Package Variant”
Changed “Ctrl.” information for balls M22 in “System I/O” table for “BGA-516 Package Variant”
Changed function descriptions for EDSADC at Port 00 in “BGA-292 Package Variant” tables
Changed function descriptions for EDSADC at Port 01 in “BGA-292 Package Variant” tables
Changed function descriptions for EDSADC at Port 02 in “BGA-292 Package Variant” tables
Changed function descriptions for PSI5S at Port 02 in “BGA-292 Package Variant” tables
Changed GTM input channel at Port 02 in “BGA-292 Package Variant” tables
Deleted parameter for PMS at Port 02 in “BGA-292 Package Variant” tables
Deleted parameter for SCU at Port 10 in “BGA-292 Package Variant” tables
Added parameter for PMS at Port 10 in “BGA-292 Package Variant” tables
Changed Buffer Type description for P11.5, P11.7, P11.8, P11.9, P11.10, P11.11, P11.12 at Port 11 in
“BGA-292 Package Variant” tables
–
Changed function description for GETH at Port 11 in “BGA-292 Package Variant” tables
Data Sheet
413
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 1.1 to Version 1.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Changed GTM input channel at Port 11 in “BGA-292 Package Variant” tables
Deleted parameter for SCU at Port 14 in “BGA-292 Package Variant” tables
Added parameter for PMS at Port 14 in “BGA-292 Package Variant” tables
Changed GTM input channel at Port 14 in “BGA-292 Package Variant” tables
Added function description for DMU at Port 21 in “BGA-292 Package Variant” tables
Changed function description for HSCT0 at Port 21 in “BGA-292 Package Variant” tables
Changed GTM input channel at Port 23 in “BGA-292 Package Variant” tables
Changed function descriptions for EDSADC at Port 33 in “BGA-292 Package Variant” tables
Changed GTM input channel at Port 33 in “BGA-292 Package Variant” tables
Changed PSI5S function description for Port 33 in “BGA-292 Package Variant” tables
Added notes to table “System I/O” for “BGA-292 Package Variant”
Changed “Ctrl.” information for balls G16, F16, G17 in “System I/O” table for “BGA-292 Package Variant”
Changed function description for ball G17 in “System I/O” table for “BGA-292 Package Variant”
Changed sub-chapter title from “Bare Die Variant Pin Configuration of TC38x” to “Sequence of Pads in Pad
Frame”
–
–
Changed comments for pad name VDDP3 (62, 64) in Pad List of “Sequence of Pads in Pad Frame”
Changed pad type for pad names P11.5, P11.7, P11.9, P11.8, P11.10, P11.11, P11.12 in Pad List of
“Sequence of Pads in Pad Frame”
–
–
–
Changed comments for pads 158, 159 in Pad List of “Sequence of Pads in Pad Frame”
Changed pad names for pads 198, 217, 218, 352, 383 in Pad List of “Sequence of Pads in Pad Frame”
Changed/ revised footnote for table Pad List of “Sequence of Pads in Pad Frame”
•
•
Changes in chapter “Legend”
Changed version number of “TC38xpd_IO_Spirit” file
–
Changes in chapter “Electrical Specification”
–
–
Typos corrected in footnotes for sub-chapter “Absolute Maximum Ratings”
Typo corrected for parameter IINSA in table “Overload Parameters” of sub-chapter “Pin Reliability in
Overload”
–
–
–
–
–
–
–
–
Changed values for parameter GETH frequency in table “Operating Conditions”
Changed note for parameter tTX_ASYM in table “Fast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Fast 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Slow 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Slow 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “RFast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “RFast 3.3V pad” of sub-chapter “5V/3.3V switchable Pads”
Changed notes for parameter IOZ2 in table “ADC Reference Pads” of sub-chapter “5V/3.3V switchable
Pads”
–
–
Typos corrected in footnote 3) for table “LVDS – IEEE standard LVDS general purpose link (GPL)” in sub-
chapter “High performance LVDS Pads”
Added footnote content for table “LVDS – IEEE standard LVDS general purpose link (GPL)” in sub-chapter
“High performance LVDS Pads”
Data Sheet
414
V 1.2, 2021-03
OPEN MARKET VERSION
TC38x AD/AE-Step
History Changes from Version 1.1 to Version 1.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typo corrected for parameter dVCSD in table “VADC 5V” in sub-chapter “VADC Parameters”
Changed footnote 7) of table “VADC 5V” in sub-chapter “VADC Parameters”
Changed figure “Equivalent Circuitry for Analog Inputs” in sub-chapter “VADC Parameters”
Changed footnotes 3) and 6) for table "VADC 5V" in sub-chapter "VADC Parameters"
Changed value of parameter IRMS in table “DSADC 5V” in sub-chapter “DSADC Parameters”
Changed footnote 4) in sub-chapter “DSADC Parameters”
Changed spelling in footnote 2) in sub-chapter “MHz Oscillator”
Changed spelling in initial text for sub-chapter “Power Supply Current”
Changed footnote 2) for table “Current Consumption” in sub-chapter “Power Supply Current”
Added footnote 7) for table “Current Consumption” in sub-chapter “Power Supply Current”
Typos corrected in sub-chapter “Calculating the 1.25V Current Consumption”
Added sentence to sub-chapter “Supply Ramp-up and Ramp-down Behavior”
Changed/added value for parameter tPI in table “Reset” for sub-chapter “Reset Timing”
Changed figure “DAP Timing” in sub-chapter “DAP Parameters”
Changed values (from Min. to Typ.) for parameter t7 in table “ETH MII Signal Timing Parameters” for sub-
chapter “ETH MII Parameters”
–
–
–
Changed symbols for parameters t13, t14, t15 in table “ETH RMII Signal Timing Parameters valid for 3.3V” in
sub-chapter “ETH RMII Parameters”
Changed value (from Min. to Typ.) for parameter t13 in table “ETH RMII Signal Timing Parameters valid for
3.3V” in sub-chapter “ETH RMII Parameters”
Added footnote 3) for table “ETH RMII Signal Timing Parameters valid for 3.3V” in sub-chapter “ETH RMII
Parameters”
–
–
–
Changed figure title to “Package Outlines FBGA-516” in sub-chapter “Package Outline”
Changed notes in table “Package Parameters” to “FBGA” for sub-chapter “Package Parameters”
Deleted sub-chapter “TC380 Carrier Tape”
Data Sheet
415
V 1.2, 2021-03
OPEN MARKET VERSION
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
OPEN MARKET VERSION
相关型号：
SAL-TC397XP-256F300S BC
Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontroller. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. Its mirrored embedded flash banks offers A/B swap capabilities. Key features:
INFINEON
SAL-TC399XP-256F300S BC
Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontroller. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. Its mirrored embedded flash banks offers A/B swap capabilities. Key features:
INFINEON
SAL-TC399XX-256F300S BC
Infineon releases its second generation AURIX™ microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontroller. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. Its mirrored embedded flash banks offers A/B swap capabilities.
INFINEON
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