SDA3302-5X6_技术文档

GHz PLL with I²C Bus

SDA 3302 Family

and Four Chip Addresses

Preliminary Data

Features

Bipolar IC

● 1-chip system for MPU

control (I²C bus)

● 4 programmable chip addresses

● Short pull-in time for quick channel

switch-over and optimized loop

stability

P-DIP-18-5

P-DSO-20-1

● Charge pump output with switch

off option

● Up to 3*) high current band switch

outputs (20 mA)

● Up to 4*) output ports (5 mA)

*) depending on version

P-DSO-16-1

Type

Ordering Code

Q67000-H5112

Q67000-H5111

Q67000-H5110

Q67006-H5111

Q67006-H5110

Package

SDA 3302-5

SDA 3302-5X

SDA 3302-5X6

SDA 3302-5X

SDA 3302-5X6

P-DIP-18-5

P-DSO-20-1 (SMD)

P-DSO-16-1 (SMD)

P-DSO-20-1 Tape & Reel (SMD)

P-DSO-16-1 Tape & Reel (SMD)

02.97

Semiconductor Group

1

SDA 3302 Family

Functional Description

Combined with a VCO (tuner) the SDA 3302 device, with four hardware-switched chip

addresses, forms a digitally programmable phase-locked loop for use in television sets with

PLL frequency-synthesis tuning.

The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillators

between 16 and 1300 MHz in increments of 62.5 kHz. The tuning process is controlled by a

microprocessor via an I²C bus. The crystal oscillator generates a sinusoidal signal suppressing

the higher-order harmonics, which reduces the moiré noise considerably.

Circuit Description

Tuning Section (refer to block diagram)

UHF/VHF

REF

The tuner signal is capacitively coupled at the UHF/VHF input and

subsequently amplified. The reference input REF should be decoupled to

ground using a capacitor of low series inductance. The signal passes

through an asynchronous divider with a fixed ratio of P = 8, an adjustable

divider with ratio N = 256 through 32767 and is then compared in a digital

phase/frequency detector to a reference frequency f_REFof 7.8125 kHz. The

latter is derived from a balanced, low-impedance 4 MHz crystal oscillator

(pin Q1, Q2), whose output signal is divided by Q = 512.

Q1, Q2

PD, UD

The phase detector has two outputs UP and DOWN that drive the two current

sources I+ and I– of a charge pump. If the negative edge of the divided VCO

signal appears prior to the negative edge of the reference signal, the I+

current source pulses for the duration of the phase difference. In the reverse

case the I– current source pulses.

When the two signals are in phase, the charge-pump output (PD) goes high-

impedance (PLL is locked). An active low-pass filter integrates the current

pulses to generate the tuning voltage for the VCO (internal amplifier an

external transistor at the UD output and an external RC circuitry). The

charge-pump output can also be set to high-impedance state when control

bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter

over a long period in the high-impedance state as a result of self-discharge

in the peripheral circuitry. UD can be disconnected internally by the control

bit OS to enable external adjustments.

By means of a control bit 5I the pump current can be switched between two

values by software. This switchover permits alteration of the control

response of the PLL in the locked-in state. In this way different VCO gains in

the different TV bands can be compensated for example.

Semiconductor Group

2

SDA 3302 Family

Circuit Description (cont’d)

P0-P2

P4-P7

The software-switched outputs (P0, P1, P2) can be used for direct band

selection (20-mA current output).

P4, P5, P6 and P7 are open-collector outputs for a variety of different

purposes. The test bit T1 = 1 switches the test signals f_REF(4 MHz/512) and

Cy (divided input signal) to P6 and P7.

CAS

Four different chip addresses can be set by appropriate connection of pin

CAS.

I²C-Bus Interface

SCL, SDA

Data are exchanged between the processor and the PLL on the I²C bus. The

clock is produced by the processor (input SCL), while pin SDA works as an

input or output depending on the direction of the data (open collector;

external pullup resistor). Both inputs have hysteresis and a lowpass

characteristic, which enhances the noise immunity of the I²C bus.

The data from the processor are applied to an I²C bus controller and filed in

registers according to their function. When the bus is free, both lines are in

the marking state (SDA, SCL are high). Each telegram begins with a start

condition and ends with the stop condition. Start condition: SDA goes low

while SCL remains high; stop condition: SDA goes high while SCL remains

high. All further data exchanges occur while SCL is low and are accepted by

the controller with the positive clock edge.

For what follows, refer to the table of logic allocations.

All telegrams are transmitted byte by byte, followed by a ninth clock pulse,

during which the controller puts the SDA line on low (acknowledge condition).

The first byte consists of seven address bits, with which the processor

selects the PLL from a number of peripheral devices (chip select). The eighth

bit is always low. In the data portion of the telegram the first bit of the first or

third data byte determines whether a divider ratio or control information

follows. In each case the byte following the first byte must be of the same

data type (or a stop condition).

V_S, GND

When the supply voltage is applied, a power-on reset circuit prevents the PLL

from putting the SDA line on low, which would block the bus.

Semiconductor Group

3

SDA 3302 Family

Circuit Description (cont’d)

Logic Allocations

MSB

A = Acknowledge

Address byte

1

0

MA1 MA0

0

A

Prog. divider byte 1

Prog. divider byte 2

Control info. byte 1

0

n7

1

n14 n13 n12 n11 n10

n9

n1

1

n8

n0

OS

P0

n6

5I

n5

T1

P5

n4

T0

P4

n3

1

n2

1

Control info. byte 2

P7

P6

X

P2

P1

Divider Ratio

N = 16384 × n14 + 8192 × n13 + 4096 × n12 + 2048 × n11 + 1024 × n10 + 512 × n9 + 256 × n8 +

+ 128 × n7 + 64 × n6 + 32 × n5 + 16 × n4 + 8 × n3 + 4 × n2 + 2 × n1

+ n0

Band Selection

P2-P0 = 1

Open-collector output is active.

High current.

Port Outputs

P7-P4 = 1

Pump Current Switchover

5I = 1

UD Disable

OS = 1

V_Dis disabled.

Test Mode

T1, T0 = 0,0

T1 = 1

Normal mode

P6 = f_REF; P7 = Cy

T0 = 1

Tristate charge pump PD is in high-impedance.

Semiconductor Group

4

SDA 3302 Family

Circuit Description (cont’d)

Chip-Address Switching

MA1

MA0

Voltage on CAS

(0-0.1) V_S

open

0

1

0

1

0

1

(0.4-0.6) V_S

(0.9-1) V_S

Pulse Diagram

Telegram Examples

Start-Addr-DR1-DR2-CW1-CW2-Stop

Start-Addr-CW1-CW2-DR1-DR2-Stop

Start-Addr-DR1-DR2-CW1-Stop

Start-Addr-CW1-CW2-DR1-Stop

Start-Addr-DR1-DR2-Stop

Start

Addr

DR1

DR2

CW1

CW2

Stop

= start condition

= address

= divider ratio 1st byte

= divider ratio 2nd byte

= control word 1st byte

= control word 2nd byte

= stop condition

Start-Addr-CW1-CW2-Stop

Start-Addr-DR1-Stop

Semiconductor Group

5

SDA 3302 Family

Pin Configuration (SDA 3302-5)

(top view)

P-DIP-18-5

Semiconductor Group

6

SDA 3302 Family

Pin Definitions and Functions (SDA 3302-5)

Pin No. Symbol

Function

1

PD

Active-filter input/charge-pump output

Crystal

2

Q1

3

Q2

Crystal

Data input/output for I²C bus

Clock input for I²C bus

Port output (open collector)

Chip-address switchover

Port output (open collector)

Supply voltage

4

SDA

SCL

P7

5

6

7

P6

8

P5

9

P4

10

11

12

13

14

15

16

17

18

CAS

P2

P1

P0

V_S

UHF/VHF

REF

GND

UD

Signal input

Amplifier reference input

Ground

Output active filter

Semiconductor Group

7

SDA 3302 Family

Pin Configuration (SDA 3302-5X)

(top view)

P-DSO-20-1

Semiconductor Group

8

SDA 3302 Family

Pin Definitions and Functions (SDA 3302-5X)

Pin No. Symbol

Function

1

PD

Active-filter input/charge-pump output

Crystal

2

Q1

3

Q2

Crystal

4

N.C.

SDA

SCL

P7

Not connected

Data input/output for I²C bus

Clock input for I²C bus

Port output (open collector)

Not connected

5

6

7

8

N.C.

P6

9

Port output (open collector)

Chip-address switchover

Port output (open collector)

Supply voltage

10

11

12

13

14

15

16

17

18

19

20

P5

P4

CAS

P2

P1

P0

V_S

UHF/VHF

REF

GND

UD

Signal input

Amplifier reference input

Ground

Active-filter output

Semiconductor Group

9

SDA 3302 Family

Pin Configuration (SDA 3302-5X6)

(top view)

P-DSO-16-1

Semiconductor Group

10

SDA 3302 Family

Pin Definitions and Functions (SDA 3302-5X6)

Pin No. Symbol

Function

1

PD

Active-filter input/output pump output

Crystal

2

Q1

3

Q2

Crystal

Data input/output for I²C bus

Clock input for I²C bus

Port output (open collector)

Chip-address switchover

Port output (open collector)

Supply voltage

4

SDA

SCL

P7

5

6

7

P6

8

P5

9

P4

10

11

12

13

14

15

16

CAS

P1

V_S

UHF/VHF

REF

GND

UD

Signal input

Amplifier reference input

Ground

Output active filter

Semiconductor Group

11

SDA 3302 Family

Pin Definitions and Functions, Reference List

SDA 3302

P-DIP-18-5

Pin No.

SDA 3302X SDA 3302X6 Symbol

P-DSO-20-1 P-DSO-16-1

Function

Pin No.

1

PD

Input active-filter input charge

pump output

2

Q1

Crystal

3

Q2

Crystal

-

4

-

N.C.

SDA

SCL

P7

Not connected

Data input/output for I²C bus

Clock input for I²C bus

Port output (open collector)

Not connected

4

5

4

5

6

5

6

7

6

-

8

-

N.C.

P6

7

9

7

Port output (open collector)

Chip-address switchover

Port output (open collector)

Supply voltage

8

10

11

12

13

14

15

16

17

18

19

20

8

P5

9

P4

10

11

12

13

14

15

16

17

18

10

-

CAS

P2

11

-

P1

P0

12

13

14

15

16

V_S

UHF/VHF Signal input

REF

GND

UD

Amplifier reference input

Ground

Output active filter

Semiconductor Group

12

SDA 3302 Family

Block Diagram SDA 3302-5

Pin nos. refer to P-DIP-18 package only. For other packages, see reference list on page 16

Semiconductor Group

13

SDA 3302 Family

Absolute Maximum Ratings

T_A= 25 °C

2)

Parameter

Limit Values

Unit

Remarks

Symbol

min.

max.

Supply voltage

– 0.3

– 1

6

V

V_S

Output PD

V

V₁

V_S

6

Crystal Q1

V

V₂

Crystal Q2

V

V₃

Bus input/output SDA

Bus input SCL

V

V₄

6

V

V₅

Port output P7, P6, P5, P4

Chip-address switchover

Port output P2, P1, P0

Signal input UHF/VHF

Reference input REF

Output active filter UD

Bus output SDA

16

V_S

16

0.3

V_S

5

V

V_{6, 7, 8, 9}

V₁₀

V_{11, 12, 13}

V₁₅

V₁₆

V₁₈

I_4L

V

open collector

for V_S= 0 V

V

mA

°C

mA

°C

K/W

open collector

Port output P7, P6, P5, P4

Port output P2, P1, P0

Chip temperature

– 1

5

I_{6L, 7L, 8L, 9L}

I_{11L, 12L, 13L}

T_C

– 1

20

125

25

125

80

Total port output current

Storage temperature

Thermal resistance (system-air)

Z_IL

– 40

T_stg

R_thSA

2) Pin nos. refer to P-DIP-18 package

Semiconductor Group

14

SDA 3302 Family

Absolute Maximum Ratings

T_A= 25 °C

2)

Parameter

Limit Values

Unit

Remarks

Symbol

min.

max.

Operating Range

Supply voltage

4.5

– 20

16

5.5

V

V_S

T_A

f₁₅

f_{2, 3}

N

Ambient temperature

Input frequency

80

°C

1300

4

MHz

Crystal frequency

Programmable divider factor

256

32767

1) Design note: no 100 % final inspection.

2) Pin nos. refer to P-DIP-18 package

Semiconductor Group

15

SDA 3302 Family

Characteristics

V_S= 5 V; T_A= 25 °C

2)

Parameter

Limit Values

typ. max.

35

Unit Test Condition Test

Circuit

Symbol

min.

Current

consumption

mA

1

I_S

V_S= 5 V

Crystal-oscillator

frequency

3.99975 4.000 4.00025 MHz series capaci-

tance 18 pF;

f_{2, 3}

f

= 4 MHz

xtal

1)

2.6

20

Vpp

dB

V_{2, 3}

Oscillator level

(Voltage across

crystal)

1)

Margin from 1st

and 2nd harmonic

Input Sensitivity UHF/VHF

a₁₅

– 27/10

3/315

f₁₅= 70-500 MHz 2

3)

f₁₅= 1000 MHz

f₁₅= 1100 MHz

2

Band-Select Outputs P0-P2 (switch with open collector)

Reserve current

Residual voltage

10

µA

3

I_13H

V

_13H= 13.5 V

0.5

V

V_13L

I_13H= 20 mA

Port Outputs P4-P7 (switch with open collector)

Reserve current

Residual voltage

10

µA

4

I_9H

V_9H= 13.5 V

I_9L= 1.7 mA

0.5

V

V_9L

Note: The sum of the currents in ports P0-P7 must not exceed 25 mA

Phase-Detector Output PD

Pump current

Output voltage

± 90

± 22

1.0

± 230 ± 300

± 50 ± 75

2.5

µA

V

5I = HIGH;

V₁= 2 V

I_1H

V_1L

5I = LOW;

V₁= 2 V

locked

1) Design note: no 100 % final inspection.

2) Pin nos. refer to P-DIP-18 package

3) dBm/mV

into 50 Ω

rms

Semiconductor Group

16

SDA 3302 Family

Characteristics (cont’d)

V_S= 5 V; T_A= 25 °C

2)

Parameter

Limit Values

typ. max.

Unit Test Condition Test

Circuit

Symbol

min.

Output Active Filter UD (T0 = 1)

Output current

500

µA

5

– I₁₈

V₁₈= 0.8 V;

I_IH= 90 µA

Output voltage

100

500

mV

5

V₁₈

V_1L= 0 V

OS = 1

Chip-Address Switchover

Input current

50

µA

7

I_10H

V

_10H= 5 V

_10H= 0 V

– I_10H

Bus Inputs SCL, SDA

Input voltage

3

5.5

V

6

V_5H

V_5L

Input current

10

20

µA

6

I_5H

V_5H= V_S

V_5L= 0 V

– I_5L

Output SDA (open collector)

Reverse current

Output voltage

10

µA

6

I_4H

V_4H= 5.5 V

I_4L= 3 mA

0.4

V

V_4L

Edges SCL, SDA

Rise time

1

µs

6

t_R

t_F

Fall time

0.3

Shift Clock SCL

Frequency

0

100

kHz

µs

6

f₅

H-pulse width

L-pulse width

4

t_5H

t_5L

4.7

µs

2) Pin nos. refer to P-DIP-18 package

Semiconductor Group

17

SDA 3302 Family

Characteristics (cont’d)

V_S= 5 V; T_A= 25 °C

2)

Parameter

Limit Values

typ. max.

Unit Test Condition Test

Circuit

Symbol

min.

Start

Setup time

Hold time

4.7

4

µs

6

t_SUSta

t_HDSta

Stop

Setup time

Bus free

4.7

µs

6

t_SUsto

t_BUF

Data Exchange

Setup time

0.25

0

µs

6

t_SUDat

t_HDDat

Hold time

µs

Input hysteresis¹⁾

SCL, SDA

300

500

mV

Lowpass cutoff¹⁾

frequency

kHz

SCL, SDA

1) Design note: no 100 % final inspection.

2) Pin nos. refer to P-DIP-18 package

Semiconductor Group

18

SDA 3302 Family

Test Circuit 1

Semiconductor Group

19

SDA 3302 Family

Test Circuit 2

Test Circuit 3

Semiconductor Group

20

SDA 3302 Family

Test Circuit 4

Test Circuit 5

Semiconductor Group

21

SDA 3302 Family

I²C Bus Timing Diagram

Test Circuit 6

Test Circuit 7

Semiconductor Group

22

SDA 3302 Family

Application Circuit

Semiconductor Group

23

SDA 3302 Family

Application Circuit

Calculation of Loop Filter

Loop bandwidth ω_R= √ (I_p× K_VCO) / (C₁× P × N)

Attenuation:

ξ = 0.5 × ω_R× R × C₁

P

N

I_p

K

= prescaler

= programmable divider

= pump current

_VCO= tuner slope

R, C₁= loop filter

Example for channel 47:

P = 8, N = 11520, I_p= 100 µA; K_VCO= 18.7 MHz/V, R = 22 kΩ,

C₁= 180 nF, ω_R= 336 Hz, f_r= 54 Hz, ξ = 0.67

Standard dimensioning: C₂= C_1/5

Note: The high-impedance port outputs and CAS can be blocked against external noise with

a capacitor of 1 nF.

Semiconductor Group

24

SDA 3302 Family

Input Sensitivity

I²C Bus Noise Immunity

The sinusoidal noise pulses are applied via a coupling capacitance of 33 pF to SCL and SDA

inputs.

Semiconductor Group

25

SDA 3302 Family

Package Outlines

Plastic-Package, P-DIP-18-5

(Plastic Dual In-Line Package)

Plastic-Package, P-DSO-20-1 (SMD)

(Plastic Dual Small Outline Package)

Semiconductor Group

26

SDA 3302 Family

Plastic-Package, P-DSO-16-1 (SMD)

(Plastic Dual Small Outline Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”

SMD = Surface Mounted Device

Dimensions in mm

Semiconductor Group

27


型号：	SDA3302-5X6
厂家：	Infineon
描述：	GHz PLL with I2C Bus and Four Chip Addresses GHz的PLL与I2C总线和四芯片地址光电二极管
文件：	总27页 (文件大小：866K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SDA3302-5X6 [INFINEON]

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