SDA5254M-2 [INFINEON]
ICs for Consumer Electronics; 集成电路的消费类电子产品
| 型号： | SDA5254M-2 |
| 厂家： | 
Infineon |
| 描述： | ICs for Consumer Electronics |
| 文件： | 总23页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICs for Consumer Electronics
SDA 525X to SDA 525X-2 V2.0
Delta Specification V2.0
1998-10-08
ꢀ
SDA 525X to SDA 525X-2
Revision History:
Current Version: 1998-10-08
1998-03-10
Previous Version:
Page
Page
Subjects (major changes since last revision)
(in previous (in current
Version)
Version)
15
-
“VS sampling” inserted
-
17
“RGB and blanking skew” inserted
SDA 5254-57-2 with 10 pages optional
Also SDA 5253-2 available
4, 5
4, 5
14
18
19
4, 5
4, 5
14
Hardware compatibility, topics 5 to 8 added
Timing changed to 18 MHz
21
22
Changes in application circuit (Iref, CVBS, FIL3)
Edition 1998-10-08
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endan-
gered.
SDA 525X-2
Page
Table of Contents
1
2
3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Complete Feature List Including New Features . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
P-MQFP-80-1, ROMless-Version (top view) . . . . . . . . . . . . . . . . . . . . . . . .7
P-LCC-84-2, Emulator-Version (top view) . . . . . . . . . . . . . . . . . . . . . . . . . .8
P-SDIP-52-1, ROM-Versions (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . .9
P-MQFP-64-1, ROM-Versions (top view) . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1
4.2
4.3
4.4
5
Pin Correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6
Differences of SDA 525x-2 Compared to SDA 525x . . . . . . . . . . . . . . .14
Hardware-Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Software-Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Improved Performance Sync- and Data-Slicer . . . . . . . . . . . . . . . . . . . . .14
Crystal-locked Display-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Improved Interface to External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
No UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
VS Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
RGB and Blanking Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
Registers of SDA 525x-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.1
Address Space of SDA 525x-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8
Software Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
9
10
Semiconductor Group
3
1998-10-08
SDA 525X-2
1
General Description
As its predecessors SDA 525x the SDA 525x-2 contains a slicer for VPS and TTX, an
accelerating acquisition hardware module, a display generator for “Level 1.5” TTX data,
and an 8 bit microcontroller running at 333 ns cycle time. The controller with dedicated
hardware guarantees flexibility, does most of the internal processing of TTX acquisition,
transfers data to/from the external memory interface and receives/transmits data via I2C
user interface. The block diagram shows the internal organization of the SDA 525x-2.
The slicer combined with dedicated hardware stores TTX data in a VBI buffer of
746 Byte. The microcontroller firmware performs all the acquisition tasks (hamming- and
parity-checks, page search and evaluation of header control bits) once per field.
This delta specification describes the differences of the SDA 525x-2 compared to the
SDA 525x as described in the preliminary data sheet 1997-09-01.
2
Complete Feature List Including New Features
New features compared to SDA 525x-Specification, version 06/96 are printed in italic
and bold. As described in the errata sheet 03/97, release 1.0, the newer versions of the
SDA 525x and the SDA 525x-2 will not have a serial port (UART) any more.
• Acquisition:
– Feature selection via special function register
– Simultaneous reception of TTX, VPS, and WSS
– Fixed framing code for VPS and TTX
– Acquisition during VBI
– Direct access to VBI RAM buffer
– Acquisition of packets x/26, x/27, 8/30 (firmware)
– Assistance of all relevant checks (firmware)
– 1-bit framing code error tolerance (switchable)
• Display:
– Features selectable via special function register
– 50/60 Hz display (optional 100 Hz)
– Level 1.5 serial attribute display pages
– Blanking and contrast reduction output
– 8 direct addressable display pages for SDA 5250-2, SDA 5254-2 to SDA 5257-2
(optional 10 pages)
– 1 direct addressable display page for SDA 5251-2 to SDA 5253-2
– 12 × 10 character matrix
– 96 character ROM (standard G0 character set)
– 156 national option characters for 12 languages (for European version)
– 288 characters for X/26 display
– 64 block mosaic graphic characters
– 32 characters for OSD in expanded character ROM + 32 characters
inside OSD box
Semiconductor Group
4
1998-10-08
SDA 525X-2
– Conceal/reveal
– Transparent foreground/background - inside/outside of a box
– Contrast reduction inside/outside of a box
– Cursor (color changes from foreground to background color)
– Flash (flash rate 1s, not depending on field rate)
– Programmable horizontal and vertical sync delay
– Full screen background color in outer screen
– Double size/double width/double height characters
• Synchronization:
– Display synchronization to sandcastle or Horizontal Sync (HS)
and Vertical Sync (VS)
• Microcontroller:
– 8 bit C500-CPU (8051 compatible)
– CPU-clock 18 MHz, external 6-MHz-crystal
– 333 ns instruction cycle
– Parallel 8-bit data and 16 … 19-bit address bus (ROMless-Version)
– Eight 16-bit data pointer registers (DPTR)
– Two 16-bit timers
– Watchdog timer
– Capture compare timer for infrared remote control decoding
– 256 bytes on-chip RAM
– 8 KByte on-chip display-RAM (access via MOVX) SDA 5250-2, SDA 5254-2 to
SDA 5257-2 (optional 10 Kbyte)
– 1 Kbyte on-chip display-RAM (access via MOVX) for SDA 5251-2 to SDA 5253-2
– 1 Kbyte on-chip ACQ-buffer-RAM (access via MOVX)
– 1 Kbyte on-chip extended-RAM (access via MOVX) for SDA 5250-2 and
SDA 5254-2 to SDA 5257-2
– 6 channel 8-bit pulse width modulation unit
– 2 channel 14-bit pulse width modulation unit
– 4 multiplexed ADC inputs with 8-bit resolution
– One 8-bit I/O port with open drain output and optional I2C-Bus emulation
– Two 8-bit multifunctional I/O ports
– One 4-bit port working as digital or analog inputs
– One 3-bit I/O port with optional RAM/ROM address expansion up to 512 Kbyte
(ROMless-Version)
• P-SDIP-52-1/P-MQFP-64-1 package for ROM-Versions (SDA 5251-2 to
SDA 5253-2, SDA 5254-2 to SDA 5257-2)
• P-MQFP-80-1 package for ROMless-Version (SDA 5250M-2)
• P-LCC-84-2 package for Emulator-Version (SDA 5250-2)
• 5 V supply voltage
Semiconductor Group
5
1998-10-08
SDA 525X-2
3
Block Diagram
I
Capture
Compare
Timer
TTC
TTD
Display
Timing
R
G
B
BLAN
COR
Watchdog
Timer
TTX, VPS
Slicer
Display
Generator
Acquisition
Character
ROM
448*12*10
ADC
PWM
2)
3)
1)
C500
CPU
Dual Port
Interface
Dual Port
Interface
Memory
Extended
Data
RAM
Program
Memory
ROM
(8051-comp.)
Management
Unit
4)
incl.
Timer 0/1
256 Kbyte
(MMU)
1 Kbyte
VBI Buffer
1 Kbyte
Display
RAM
1)
2)
3)
Only ROM-versions
Only ROMless-version
Only SDA 5250-2 and
SDA 5254-2 to SDA 5257-2
4)
8 K (opt. 10 K) byte for SDA 5250-2
8 K for SDA 5254-2 to SDA 5257-2
1 Kbyte for SDA 5251-2 and SDA 5252-2
UES09854
Figure 1
Differences compared to SDA 525x according to preliminary specification 06/96:
1. UART is not supported.
2. RGB-outputs deliver a current instead of a voltage.
3. Instead of FIL1SLC/FIL2SLC/FIL3SLC only FIL3 is needed with changed external
device dimensions.
4. LCIN and LCOUT are not needed any more.
Semiconductor Group
6
1998-10-08
SDA 525X-2
4
Pin Configuration
4.1
P-MQFP-80-1, ROMless-Version (top view)
V
V
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P0.5
P0.6
P0.7
P2.3
P2.2
P2.1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
D5
D0
D6
A0
D7
A1
A2
A10
A3
A4
A11
A5
A9
A6
A8
A7
A13
A12
A14
A15
P2.0
VSSA
FIL3
N.C.
N.C.
VDDA
IREF
SDA 5250M-2
CVBS
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
UEP09855
V
V
Figure 2
Differences compared to SDA 525x according to preliminary specification 06/96:
1. RGB-outputs deliver a current instead of a voltage (Pins 45, 46, 47).
2. Instead of FIL1SLC/FIL2SLC/FIL3SLC only FIL3 is needed with changed external
device dimensions (Pin 69). Former FIL1SLC and FIL2SLC remain “not connected”
(Pins 70, 71).
3. LCIN and LCOUT are not needed any more and are now used for RD and WR (see 4.)
4. P-MQFP-80-1 now has RD (Pin 52), WR (53) and PSEN (1) Pins to connect external
RAM.
‘n.c.’ = ‘not connected’ means: Pins must be left open.
Semiconductor Group
7
1998-10-08
SDA 525X-2
4.2
P-LCC-84-2, Emulator-Version (top view)
V
V
53 52 51 50 49 48
46 45
43
40 39 38 37 36 35 34 33
42 41
47
44
P0.6
P0.7
STOP_OCF
D5
D0
D6
A0
D7
A1
A2
A10
A3
PSEN
A4
A11
A5
A9
A6
A8
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
ENE
P2.3/ANA3
P2.2/ANA2
P2.1/ANA1
P2.0/ANA0
VSSA
FIL3
N.C.
N.C.
VDDA
SDA 5250-2
IREF
CVBS
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
A7
A13
A12
A14
A15
75 76
78 79 80 81 82 83
3
5
6
7
9 10
11
8
77
84
1
2
4
V
V
UEP09856
Figure 3
Differences compared to SDA 525x according to preliminary specification 06/96:
1. RGB-outputs deliver a current instead of a voltage (Pins 37, 38, 39).
2. Instead of FIL1SLC/FIL2SLC/FIL3SLC only FIL3 is needed with changed external
device dimensions (Pin 63). Former FIL1SLC and FIL2SLC remain “not connected”
(Pins 64, 65).
3. LCIN and LCOUT are not needed any more and remain “not connected” (Pins 44, 45).
‘n. c.’ = ‘not connected’ means: Pins must be left open.
Semiconductor Group
8
1998-10-08
SDA 525X-2
4.3
P-SDIP-52-1, ROM-Versions (top view)
P3.1
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
1
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P3.0
COR
BLAN
B
2
3
4
5
G
6
R
7
VS/P4.7
HS/SC
P3.2
P3.4
P3.5
P3.6
P3.7
N.C.
8
P0.0
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VDD
SDA 5251-2
SDA 5252-2
SDA 5254-2
SDA 5255-2
SDA 5256-2
SDA 5257-2
XTAL1
XTAL2
P4.0
RST
N.C.
VDD
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P3.3
VSS
P2.0
P2.1
P2.2
P2.3
P1.0
VSSA
CVBS
IREF
VDDA
N.C.
FIL3
N.C.
UEP09857
Figure 4
Differences compared to SDA 525x according to preliminary specification 06/96:
1. RGB-outputs deliver a current instead of a voltage (Pins 47, 48, 49).
2. Instead of FIL1SLC/FIL2SLC/FIL3SLC only FIL3 is needed with changed external
device dimensions (Pin 25). Former FIL1SLC and FIL2SLC remain “not connected”
(Pins 26, 27).
3. LCIN and LCOUT are not needed any more and remain “not connected” (Pins 38, 39).
‘n. c.’ = ‘not connected’ means: Pins must be left open.
Semiconductor Group
9
1998-10-08
SDA 525X-2
4.4
P-MQFP-64-1, ROM-Versions (top view)
V
V
V
V
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
N.C.
P1.3
P1.2
P1.1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
N.C.
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P3.1
P3.0
COR
BLAN
B
P1.0
VSSA
SDA 5251M-2
SDA 5252M-2
SDA 5254M-2
SDA 5255M-2
SDA 5256M-2
SDA 5257M-2
FIL3
N.C.
N.C.
VDDA
IREF
CVBS
P2.3
P2.2
P2.1
N.C.
G
R
VS/P4.7
N.C.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
V
V
V
V
UEP10218
Figure 5
Differences compared to SDA 525x according to preliminary specification 06/96:
1. RGB-outputs deliver a current instead of a voltage (Pins 19, 20, 21).
2. Instead of FIL1SLC/FIL2SLC/FIL3SLC only FIL3 is needed with changed external
device dimensions (Pin 55). Former FIL1SLC and FIL2SLC remain “not connected”
(Pins 56, 57).
3. LCIN and LCOUT are not needed any more and remain “not connected” (Pins 7, 8).
‘n. c.’ = ‘not connected’ means: Pins must be left open.
Semiconductor Group
10
1998-10-08
SDA 525X-2
5
Pin Correspondence
Table 1
Pin Correspondence P-SDIP-52-1, P-MQFP-64-1, P-MQFP-80-1, P-MQFP-80-1,
P-LCC-84-2
Symbol
Pin No.
Pin No.
Pin No.
Pin No.
Pin No.
Changes compared
P-SDIP-52-1 P-MQFP-64-1 P-MQFP-80-1 P-MQFP-80-1 P-LCC-84-2 to SDA 525x
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
9
8
7
6
5
4
3
2
34
33
31
30
29
28
27
26
56
57
58
59
60
61
62
63
58
59
60
61
62
63
64
65
48
49
50
51
52
53
54
55
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
23
22
21
20
19
18
17
16
53
52
51
50
48
47
46
44
11
10
9
8
7
6
5
4
13
12
11
10
9
8
7
6
84
83
82
81
80
79
78
77
P2.0
P2.1
P2.2
P2.3
34
33
32
31
1
67
66
65
64
69
68
67
66
61
60
59
58
63
62
61
XTAL2
XTAL1
RST
13
12
15
40
39
42
14
15
16
16
17
18
3
4
5
6 MHz crystal
6 MHz crystal
VDD
VSS
11, 37
10, 35
5, 6, 37, 38
2, 3, 35, 36
13, 51
12, 50
15, 53
14, 52
2, 43
1, 42
R
G
B
BLAN
COR
47
48
49
50
51
19
20
21
22
23
45
46
47
48
49
47
48
49
50
51
37
38
39
40
41
current output
current output
current output
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
52
1
24
25
15
4
14
13
10
9
3
2
5
4
2
1
80
79
78
77
76
75
74
73
72
71
70
69
44
36
43
42
41
40
80
79
78
77
76
75
Semiconductor Group
11
1998-10-08
SDA 525X-2
Table 1
Pin Correspondence P-SDIP-52-1, P-MQFP-64-1, P-MQFP-80-1, P-MQFP-80-1,
P-LCC-84-2 (cont’d)
Symbol
Pin No.
Pin No.
Pin No.
Pin No.
Pin No.
Changes compared
P-SDIP-52-1 P-MQFP-64-1 P-MQFP-80-1 P-MQFP-80-1 P-LCC-84-2 to SDA 525x
HS/SC
45
46
16
18
54
55
56
57
46
47
VS/P4.7/
ODD-EVEN
CVBS
30
29
60
59
74
73
76
75
68
67
New ext. comp.
values
IREF
New ext. comp.
values
VDDA
VSSA
28
24
58
24
72
68
74
70
66
62
FIL3
25
55
69
71
63
New ext. comp.
values, FIL1/2 not
needed
P4.0
14
41
18
20
9
LCIN and LCOUT are not needed any longer.
Semiconductor Group
12
1998-10-08
SDA 525X-2
Additional Pin Correspondence P-MQFP-80-1 and P-LCC-84-2
Table 2
Pin Correspondence P-MQFP-80-1, P-MQFP-80-1, P-LCC-84-2
Symbol
Pin No.
Pin No.
Pin No.
Changes vs. SDA 525x
P-MQFP-80-1 P-MQFP-80-1 P-LCC-84-2
A0
A1
A2
A3
A4
A5
A6
A7
37
35
34
32
31
29
27
25
26
28
33
30
23
24
22
21
19
39
37
36
34
33
31
29
27
28
30
35
32
25
26
24
23
21
29
27
26
24
22
20
18
16
17
19
25
21
14
15
13
12
10
A8
A9
A10
A11
A12
A13
A14
A15
A16
D0
D1
D2
D3
D4
D5
D6
D7
39
41
43
44
42
40
38
36
41
43
45
46
44
42
40
38
31
33
35
36
34
32
30
28
STOP_OCF
ENE
RD
WR
ALE
–
–
52
53
17
1
–
–
54
55
19
3
56
57
7
6
8
new for MQFP
new for MQFP
PSEN
23
new for MQFP
P4.1
20
22
11
Semiconductor Group
13
1998-10-08
SDA 525X-2
6
Differences of SDA 525x-2 Compared to SDA 525x
This delta specification describes the differences of the SDA 525x-2 compared to the
SDA 525x as described in the preliminary data sheet 1997-09-01.
6.1
Hardware-Compatibility
TVT-2 is pin-compatible to previous versions of TVT. However, some variations in
external components become necessary (see Application Circuit in Chapter 10):
1. The LC-oscillator is not necessary any longer.
2. The filters 1 and 2 are not needed any longer. Only filter 3 is needed but with different
external device dimensions.
3. Since the RBG outputs deliver a current, a voltage divider can be replaced by a single
resistor (see TVText Design Guide).
4. The external crystal is now 6 MHz instead of 18 MHz.
5. The CVBS-pin needs different dimensioning of the external components due to
changes in the internal clamping circuit.
6. The Iref-pin needs different dimensioning of the external components and an
additional blocking capacitor.
7. To avoid clock cross-talk and to improve the slicer performance use filter circuits at
the power supply pins to decouple digital and analog supplies.
8. Due to a reworked analog concept with the advantage of a more stable circuits and
better performance the power consumption has increased. For the Romless version
a maximum overall IDD-current of 95mA can be reached, for ROM versions up to
100mA.
Furthermore, the MQFP-80-packages now have RD, WR, and PSEN pins to connect to
external RAM.
6.2
Software-Compatibility
Only slight software changes may be necessary due to some register changes (see
chapter 7).
6.3
Due to crystal locked PLLs the robustness of the sync- and data-slicer is improved.
6.4 Crystal-locked Display-PLL
Improved Performance Sync- and Data-Slicer
The display clock will be locked to the internal PLL locked to the single external
6-MHz-crystal and, by this, will have very low jitter. Furthermore, the display width will
not vary. Procedures to adjust the display clock have to be disabled.
6.5
Improved Interface to External RAM
The SDA 5250M-2 (ROMless version P-MQFP-80-1) can also be used with external
RAM, because the pins RD, WR and PSEN are available. Furthermore, optional banking
Semiconductor Group
14
1998-10-08
SDA 525X-2
of external XDATA-memory will be possible, controlled by A16, A17, A18. This offers a
maximum of flexibility for 128-page-acquisition (see separate application note).
6.6
No UART
As described already in the errata sheet 03/97, release 1.0, the newer versions of the
SDA 525x and the SDA 525x-2 will not support a serial port (UART) any more.
6.7
VS Sampling
The internal sampling time of the vertical sync pulse coming from either the VS pin or
from the sandcastle signal applied at the pin HS/SC is most important for a stable
display. Because the VSYNC inside a TV set is often delayed by external components,
the real relation-chip of the VS-phase and the appropriate picture frame may get lost.
The sampling time of the SDA 525x is derived from an internal display signal which can
only be modified by programming different horizontal offset values (DHD-Register). This
has the side-effect that depending on the desired horizontal offset the sampling point is
also varied and may show an unstable display. To avoid this dependency, the
SDA 525x-2 has a separate register to determine the VS sampling point with respect to
the HS pulse, which may be varied over a whole line in steps of 8 µs. External
components for VS delaying are no more necessary and can be removed if the
programmed VS sampling points fits to the external timing between HS, VS and the
actual frame (even/odd). To get a better timing resolution in 100 Hz-applications a
special bit has been implemented to reduce the intervals between the possible sampling
points from 8 to 4 µs. The register bits are described below. The following diagram shows
the internal VS processing in principle.
HS
VS
Sample Point
Sampled VS
Field
Internal VS
UED11012
Figure 6
Internal VS Processing
Semiconductor Group
15
1998-10-08
SDA 525X-2
Default after reset: 02H
DAFR1
SFR Address B1H
(MSB)
(LSB)
-
-
-
-
VS100
VD.2
VD.1
VD.0
Bit 7 … 4
VD
Must be set to 0
Vertical Delay: Reset value 0010, corresponds to 20
microsecond delay.
If VS100 = 0, delay can be set to 4, 12, 20, 28, 36, 44, 52,
60 µs
If VS100 = 1, delay can be set to 2, 6, 10, 14, 18, 22, 26, 30 µs
VS100
For VD bits selects the sampling mode
0 = 50 Hz
1 = 100 Hz
Following table gives an overview of the sampling point equivalents of the SDA 525x and
the SDA 525x-2 at a selected pixel frequency of 12 MHz.
Sample Point in µs Equivalent DHD-Setup
Equivalent Register Setup for
SDA 525x-2 (binary)
for SDA 525x (decimal)
4
not possible
207
111
000
001
010
011
100
101
110
111
12
20
28
36
44
52
60
15
not possible
not possible
not possible
not possible
Semiconductor Group
16
1998-10-08
SDA 525X-2
6.8
RGB and Blanking Skew
In some applications the BLANK line is delayed by external components and/or special
video ICs and thus gets a delay with respect to the RGB- and COR lines which corrupts
the display by means of white and black vertical stripes at the beginning and at the end
of an OSD menu. To reduce this skew to an acceptable value, the RGB- and COR-lines
can be delayed by multiple of a pixel duration.
Default after reset: 00H
DAFR2
SFR Address B2H
(LSB)
(MSB)
-
-
-
-
-
-
RGBD.1 RGBD.0
Bit 7 … 2
Must be set to 0
RGB Delay in pixels counts
RGBD1 … 0
= 00 No delay
= 01 one pixel delay
= 10 two pixels delay
= 11 three pixel delay
Semiconductor Group
17
1998-10-08
SDA 525X-2
7
Registers of SDA 525x-2
It is very important, that registers not named or marked by “xxxx” here may in no case
be used in any way!
Register SDA 525x-2
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Common Functions
AFR
ACC
B
PSW
SP
DPH
DPL
DPSEL
PCON
A6
E0
F0
D0
81
83
82
A2
87
CDC
ACC.7
B.7
WDT
ACC.6
B.6
0
0
0
0
ACC.2
B.2
OV
SP.2
DPH.2
DPL.2
DPSEL.2
0
ACC.1
B.1
F1
SP.1
DPH.1
DPL.1
DPSEL.1
PDE
0
ACC.0
B.0
P
SP.0
DPH.0
DPL.0
DPSEL.0
IDLE
ACC.5
B.5
F0
SP.5
DPH.5
DPL.5
ACC.4
B.4
RS1
SP.4
DPH.4
DPL.4
ACC.3
B.3
RS0
SP.3
DPH.3
DPL.3
CY
AC
SP.7
DPH.7
DPL.7
SP.6
DPH.6
DPL.6
SMOD
PDS
IDLS
EM.5
Emulation Functions (Emulation Version only)
EMREG
FE
EM.7
EM.6
EM.4
EM.3
EM.2
EM.1
EM.0
Acquisition
ACQSIR
ACQMS1
ACQMS2
C0
C1
C2
EVENEN
OSDACQ
EVENST
WSSE
LIN24EN
VPSE
LIN24ST
NTSC
TEST.4
AVIREN
CRIC.1
TEST.3
AVIRST
CRIC.0
TEST.2
AHIREN
ENERT
TEST.1
AHIRST
TTXE
TEST.0
Display Generator
DHD
DVD
DTCR
DMODE1
DMODE2
TTXSIR
LANGC
DCCP
DCRP
DTIM
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CE
D6
HD.7
HD.6
HD.5
VD.5
ICRP
CON
HD.4
VD.4
IBP
DH.1
DCHAP.2
PCLK
LANGC.4
DCCP.4
DCRP.4
EO_P30
SCCH.0
BG_MODE
HD.3
VD.3
TRFI
HD.2
VD.2
TRFO
HD.1
VD.1
TRBI
BD_1_23
C10
DHIREN
LANGC.1
DCCP:7
DCRP.1
LIN9
HD.0
VD.0
TRBO
BD_0
CORI
ST_TOP
CORO
ST_DIS
DH.0
BD_24
DCHAP.1
DVIREN
LANGC.3
DCCP:6
DCRP.3
EO_VS
FL5MX
VPS_TM
DCHAP.0
DVIRST
LANGC.2
DCCP.5
DCRP.2
SANDC
SCCL.2
HG_MOD
C7
VSY
HSY
LANGC.5
DCCP:5
DHIRST
LANGC.0
DCCP.6
DCRP.0
LIN8
OSD_64
LANGC.6
DC_EN
COROS
BG_G
TRBOS
BG_R
CORTM
BG_B
SCCH.1
SCCON
DMOD
SCCH.2
SCCL.1
DH_MODE
SCCL.0
DSDW
Analog to Digital Converter
xxxx
AD7
xxxx
AD6
ADCON
ADDAT
DAPR
D8
D9
DA
IADC
AD5
BSY
AD4
ADM
AD3
0
AD2
MX1
AD1
MX0
AD0
Pulse Width Modulator
PWME
PWCL
PWCH
F8
F7
F9
F1
F2
F3
F4
F5
F6
FB
FA
FD
FC
E7
E6
E5
E4
E3
E2
E1
E0
PWCL.7
PWCH.7
COMP0.7
COMP1.7
COMP2.7
COMP3.7
COMP4.7
COMP5.7
COMP6.7
EXT6.7
PWCL.6
PWCH.6
COMP0.6
COMP1.6
COMP2.6
COMP3.6
COMP4.6
COMP5.6
COMP6.6
EXT6.6
PWCL.5
PWCH.5
COMP0.5
COMP1.5
COMP2.5
COMP3.5
COMP4.5
COMP5.5
COMP6.5
EXT6.5
PWCL.4
PWCH.4
COMP0.4
COMP1.4
COMP2.4
COMP3.4
COMP4.4
COMP5.4
COMP6.4
EXT6.4
PWCL.3
PWCH.3
COMP0.3
COMP1.3
COMP2.3
COMP3.3
COMP4.3
COMP5.3
COMP6.3
EXT6.3
PWCL.2
PWCH.2
COMP0.2
COMP1.2
COMP2.2
COMP3.2
COMP4.2
COMP5.2
COMP6.2
EXT6.2
PWCL.1
PWCH.1
COMP0.1
COMP1.1
COMP2.1
COMP3.1
COMP4.1
COMP5.1
COMP6.1
EXT6.1
PWCL.0
PWCH.0
COMP0.0
COMP1.0
COMP2.0
COMP3.0
COMP4.0
COMP5.0
COMP6.0
EXT6.0
PWCOMP0
PWCOMP1
PWCOMP2
PWCOMP3
PWCOMP4
PWCOMP5
PWCOMP6
PWEXT6
PWCOMP7
PWEXT7
COMP7.7
EXT7.7
COMP7.6
EXT7.6
COMP7.5
EXT7.5
COMP7.4
EXT7.4
COMP7.3
EXT7.3
COMP7.2
EXT7.2
COMP7.1
EXT7.1
COMP7.0
EXT7.0
Port Functions
P0
P1
P2
P3
P4
80
90
A0
B0
E8
P0.7
P1.7
P0.6
P1.6
P0.5
P1.5
P0.4
P1.4
P0.3
P1.3
P2.3
P3.3
P0.2
P1.2
P2.2
P3.2
P0.1
P1.1
P2.1
P3.1
P4.1
P0.0
P1.0
P2.0
P3.0
P4.0
P3.7
P3.6
P3.5
P3.4
Serial Interface
SCON
SBUF
98
99
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
Interrupt Controller
xxxx
IP0.4
IP1.4
IE
IP0
IP1
IRCON
A8
A9
AA
AB
EA
EADC
IP0.6
IP1.6
ETSI
IP0.5
IP1.5
ETI
EX1
IP0.2
IP1.2
EX1F
ET0
IP0.1
IP1.1
EX0R
EX0
IP0.0
IP1.0
EX0F
IP0.3
IP1.3
EX1R
Timer 0/1
TMOD
TCON
TH1
TH0
TL1
89
88
8D
8C
8B
8A
GATE
TF1
TH1.7
TH0.7
TL1.7
TL0.7
C/T
TR1
TH1.6
TH0.6
TL1.6
TL0.6
M1
TF0
TH1.5
TH0.5
TL1.5
TL0.5
M0
TR0
TH1.4
TH0.4
TL1.4
TL0.4
GATE
IE1
TH1.3
TH0.3
TL1.3
TL0.3
C/T
IT1
TH1.2
TH0.2
TL1.2
TL0.2
M1
IE0
TH1.1
TH0.1
TL1.1
TL0.1
M0
IT0
TH1.0
TH0.0
TL1.0
TL0.0
TL0
continued on next page …
Semiconductor Group
18
1998-10-08
SDA 525X-2
Register SDA 525x-2
Name Address
Watchdog Timer
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
WDCON
WDTREL
WDTL
A7
WDTS
SWDT
86
84
85
WDTREL.7 WDTREL.6 WDTREL.5 WDTREL.4 WDTREL.3 WDTREL.2 WDTREL.1 WDTREL.0
WDTL.7
WDTH.7
WDTL.6
WDTH.6
WDTL.5
WDTH.5
WDTL.4
WDTH.4
WDTL.3
WDTH.3
WDTL.2
WDTH.2
WDTL.1
WDTH.1
WDTL.0
WDTH.0
WDTH
Infrared Capture-/Compare Timer
RELL
RELH
CAPL
CAPH
IRTCON
E1
E2
E3
E4
E5
RELL.7
RELH.7
CAPL.7
CAPH.7
OV
RELL.6
RELH.6
CAPL.6
CAPH.6
PR
RELL.5
RELH.5
CAPL.5
CAPH.5
PLG
RELL.4
RELH.4
CAPL.4
CAPH.4
REL
RELL.3
RELH.3
CAPL.3
CAPH.3
RUN
RELL.2
RELH.2
CAPL.2
CAPH.2
RISE
RELL.1
RELH.1
CAPL.1
CAPH.1
FALL
RELL.0
RELH.0
CAPL.0
CAPH.0
SEL
Memory Management Unit (ROM-less versions only)
MEX1
MEX2
94
95
CB18
MB18
CB17
MB17
CB16
MB16
NB18
IB18
NB17
IB17
NB16
IB16
MM
SF
=
=
=
Register Bit read-only
Register Bit write-only
xxxx
Register Bit not available
and not needed any longer
Differences compared to SDA 525x according to preliminary specification 06/96:
1. The serial interface is not supported any longer. By this, registers SCON and SBUF
are no longer available. The “Serial Interrupt Enable Flag” ES of the Interrupt Enable
register (Bit 4 of A8) must not be written (default after reset = 0).
2. The functions and bits Prescaler Control (PSC) and ADC sample time (STADC) of the
Special Function Register ADCON are not available any more. Bits 7 and 6 of D8 must
be 0.
3. The registers following must not be written. The software needs to be checked
accordingly.
SBUF (99):
Bits 0 to 7
Bits 0 to 7
Bits 0 to 7
Bits 5 to 7
Bits 6 and 7
Bit 4
SCON (98):
ACQMS2 (C2):
DMODE2 (C7):
ADCON (D8):
IE (A8):
The allowed bits of DMODE2, ADCON and IE have to be changed with the commands
ANL or ORL.
Semiconductor Group
19
1998-10-08
SDA 525X-2
7.1
Address Space of SDA 525x-2
The registers of the SDA 525x-2 sorted by address are listed in the table following:
Register SDA 525x-2 sorted by address
Address Name
decimal
Address
hex
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
128
129
130
131
132
133
134
135
136
137
138
139
140
141
144
148
149
160
162
166
167
168
169
170
171
176
192
193
194
195
196
197
198
199
200
201
202
203
204
206
208
214
216
217
218
224
225
226
227
228
229
232
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
P0
SP
DPL
DPH
WDTL
WDTH
WDTREL
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
P1
MEX1
MEX2
P2
DPSEL
AFR
WDCON
IE
IP0
IP1
IRCON
P3
ACQSIR
ACQMS1
ACQMS2
DHD
80
81
82
83
84
85
86
87
88
P0.7
SP.7
DPL.7
DPH.7
WDTL.7
WDTH.7
P0.6
SP.6
DPL.6
DPH.6
WDTL.6
WDTH.6
P0.5
SP.5
DPL.5
DPH.5
WDTL.5
WDTH.5
P0.4
SP.4
DPL.4
DPH.4
WDTL.4
WDTH.4
P0.3
SP.3
DPL.3
DPH.3
WDTL.3
WDTH.3
P0.2
SP.2
DPL.2
DPH.2
WDTL.2
WDTH.2
P0.1
SP.1
DPL.1
DPH.1
WDTL.1
WDTH.1
P0.0
SP.0
DPL.0
DPH.0
WDTL.0
WDTH.0
WDTREL.7 WDTREL.6 WDTREL.5 WDTREL.4 WDTREL.3 WDTREL.2 WDTREL.1 WDTREL.0
SMOD
TF1
GATE
TL0.7
TL1.7
TH0.7
TH1.7
P1.7
PDS
TR1
C/T
TL0.6
TL1.6
TH0.6
TH1.6
P1.6
IDLS
TF0
M1
TL0.5
TL1.5
TH0.5
TH1.5
P1.5
PDE
IE0
M1
TL0.1
TL1.1
TH0.1
TH1.1
P1.1
NB17
IB17
P2.1
DPSEL.1
0
IDLE
IT0
M0
TL0.0
TL1.0
TH0.0
TH1.0
P1.0
NB16
IB16
P2.0
DPSEL.0
0
TR0
M0
IE1
IT1
C/T
89
GATE
TL0.3
TL1.3
TH0.3
TH1.3
P1.3
8A
8B
8C
8D
90
TL0.4
TL1.4
TH0.4
TH1.4
P1.4
TL0.2
TL1.2
TH0.2
TH1.2
P1.2
NB18
IB18
P2.2
94
95
CB18
MB18
CB17
MB17
CB16
MB16
MM
SF
P2.3
A0
A2
A6
A7
A8
A9
AA
AB
B0
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CE
D0
D6
D8
D9
DA
E0
E1
E2
E3
E4
E5
E8
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
DPSEL.2
0
CDC
WDTS
EA
WDT
SWDT
EADC
IP0.6
0
0
0
ETSI
IP0.5
IP1.5
xxxx
IP0.4
IP1.4
ETI
IP0.3
IP1.3
EX1R
P3.3
AVIREN
CRIC.1
TEST.3
HD.3
VD.3
TRFI
EX1
IP0.2
IP1.2
EX1F
P3.2
AVIRST
CRIC.0
TEST.2
HD.2
ET0
IP0.1
IP1.1
EX0R
P3.1
AHIREN
ENERT
TEST.1
HD.1
VD.1
TRBI
EX0
IP0.0
IP1.0
EX0F
P3.0
AHIRST
TTXE
TEST.0
HD.0
IP1.6
P3.7
EVENEN
OSDACQ
LIN5EN
HD.7
P3.6
EVENST
WSSE
LIN5ST
HD.6
P3.5
LIN24EN
VPSE
P3.4
LIN24ST
NTSC
TEST.4
HD.4
VD.4
IBP
DH.1
DCHAP.2
PCLK
LANGC.4
DCCP.4
DCRP.4
EO_P30
SCCH.0
RS1
BG_MODE
BSY
AD4
HD.5
VD.5
ICRP
CON
DVD
VD.2
VD.0
DTCR
DMODE1
DMODE2
TTXSIR
LANGC
DCCP
DCRP
DTIM
CORI
ST_TOP
CORO
ST_DIS
TRFO
BD_24
DCHAP.0
DVIRST
LANGC.2
DCCP.5
DCRP.2
SANDC
SCCL.2
OV
TRBO
BD_0
C7
DHIRST
LANGC.0
DCCP.6
DCRP.0
LIN8
SCCL.0
P
DSDW
MX0
DH.0
BD_1_23
C10
DCHAP.1
DVIREN
LANGC.3
DCCP:6
DCRP.3
EO_VS
FL5MX
RS0
VSY
LANGC.6
DC_EN
COROS
BG_G
HSY
LANGC.5
DCCP:5
DHIREN
LANGC.1
DCCP:7
DCRP.1
LIN9
SCCL.1
F1
DH_MODE
MX1
OSD_64
TRBOS
BG_R
CORTM
CY
BG_B
SCCH.1
F0
SCCON
PSW
SCCH.2
AC
DMOD
ADCON
ADDAT
DAPR
ACC
RELL
RELH
CAPL
VPS_TM
ADM
AD3
HG_MOD
0
AD2
xxxx
AD7
xxxx
AD6
IADC
AD5
AD1
AD0
ACC.7
RELL.7
RELH.7
CAPL.7
CAPH.7
OV
ACC.6
RELL.6
RELH.6
CAPL.6
CAPH.6
PR
ACC.5
RELL.5
RELH.5
CAPL.5
CAPH.5
PLG
ACC.4
RELL.4
RELH.4
CAPL.4
CAPH.4
REL
ACC.3
RELL.3
RELH.3
CAPL.3
CAPH.3
RUN
ACC.2
RELL.2
RELH.2
CAPL.2
CAPH.2
RISE
ACC.1
RELL.1
RELH.1
CAPL.1
CAPH.1
FALL
ACC.0
RELL.0
RELH.0
CAPL.0
CAPH.0
SEL
CAPH
IRTCON
P4
P4.1
B.1
P4.0
B.0
B
B.7
B.6
B.5
B.4
B.3
B.2
PWCOMP0
PWCOMP1
PWCOMP2
PWCOMP3
PWCOMP4
PWCOMP5
PWCL
PWME
PWCH
PWEXT6
PWCOMP6
PWEXT7
PWCOMP7
EMREG
COMP0.7
COMP1.7
COMP2.7
COMP3.7
COMP4.7
COMP5.7
PWCL.7
E7
PWCH.7
EXT6.7
COMP6.7
EXT7.7
COMP0.6
COMP1.6
COMP2.6
COMP3.6
COMP4.6
COMP5.6
PWCL.6
E6
PWCH.6
EXT6.6
COMP6.6
EXT7.6
COMP0.5
COMP1.5
COMP2.5
COMP3.5
COMP4.5
COMP5.5
PWCL.5
E5
PWCH.5
EXT6.5
COMP6.5
EXT7.5
COMP0.4
COMP1.4
COMP2.4
COMP3.4
COMP4.4
COMP5.4
PWCL.4
E4
PWCH.4
EXT6.4
COMP6.4
EXT7.4
COMP0.3
COMP1.3
COMP2.3
COMP3.3
COMP4.3
COMP5.3
PWCL.3
E3
PWCH.3
EXT6.3
COMP6.3
EXT7.3
COMP0.2
COMP1.2
COMP2.2
COMP3.2
COMP4.2
COMP5.2
PWCL.2
E2
PWCH.2
EXT6.2
COMP6.2
EXT7.2
COMP0.1
COMP1.1
COMP2.1
COMP3.1
COMP4.1
COMP5.1
PWCL.1
E1
PWCH.1
EXT6.1
COMP6.1
EXT7.1
COMP7.1
EM.1
COMP0.0
COMP1.0
COMP2.0
COMP3.0
COMP4.0
COMP5.0
PWCL.0
E0
PWCH.0
EXT6.0
COMP6.0
EXT7.0
COMP7.0
EM.0
COMP7.7
EM.7
COMP7.6
EM.6
COMP7.5
EM.5
COMP7.4
EM.4
COMP7.3
EM.3
COMP7.2
EM.2
The address space for MOVX is distributed as follows:
0000 - 7FFF: reserved for external SRAM (32k)
8000 - 9FFF: reserved for future extensions (8k)
A000 - BFFF: read access to Pixel-ROM via MOVX-command (8k)
C000- DFFF: display-chapters 1 to 8 (8k)
E000 - E7FF: display-chapters 9 and 10 (2k) (optional)
Semiconductor Group
20
1998-10-08
SDA 525X-2
E800 - F3FF: reserved for future extensions (3k)
F400 - F7FF: VBI buffer (1k)
F800 - FBFF: CPU RAM (1k)
FC00- FFFF: reserved for future extensions (1k)
8
Software Changes
All calls of the subroutine “adjust_horizontal” (inside the module IFRDEMO.C51 on the
Firmware Demo Disk) must be removed from the external controller software. This
routine was developed to adjust the display to the middle of the screen according to
tolerances of the LC-oscillator. This oscillator is not used any more. The pixel clock is
derived from the single external crystal. However, customers who are using SDA 525x-2
without emulating with SDA 5250-2 or 5250M-2 need to use some adjustment routine for
their first circuits. As soon as the correct adjustment is known, it can be used as a fixed
value for initialization or for future software.
Furthermore, due to some changes in the special function registers, the software needs
to be checked. The changes are in detail:
1. The serial interface is not supported any longer. By this, registers SCON and SBUF
are no longer available. The “Serial Interrupt Enable Flag” ES of the Interrupt Enable
register (Bit 4 of A8) must not be written (default after reset = 0).
2. The functions and bits Prescaler Control (PSC) and ADC sample time (STADC) of the
Special Function Register ADCON are not available any more. Bits 7 and 6 of D8 must
be 0.
3. The registers following must not be written. The software needs to be checked
accordingly.
SBUF (99):
Bits 0 to 7
Bits 0 to 7
Bits 0 to 7
Bits 5 to 7
Bits 6 and 7
Bit 4
SCON (98):
ACQMS2 (C2):
DMODE2 (C7):
ADCON (D8):
IE (A8):
The allowed bits of DMODE2, ADCON and IE have to be changed with the commands
ANL or ORL.
9
Timing
Although the frequency of the external quarz is now 6 MHz, all the internal timings
correspond to that of the SDA525x with an 18 MHz quarz. This is achieved by an internal
PLL.
Semiconductor Group
21
1998-10-08
SDA 525X-2
10
Application Circuit
Use of SDA 525x-2 (Design Step B) as replacement for SDA 525x:
(For more detailed application hints refer to ’TVText Design Guide V1.5’)
EPROM
D
A
33 pF
D0-7 A0-18
8
8
4
8
I/O Port 0 (Open-Drain)
I/O Port 1 (PWM)
XTAL1
P0.0-7
P1.0-7
P2.0-7
P3.0-7
6 MHz
33 pF
Input Port 2 (ADC)
I/O Port 3
330 nF
XTAL2
RST
CVBS
CVBS
10 k
Ω
10
µ
F
1 MΩ
SDA 525X-2
+5 V
R
G
B
33 nF
2.7 k
Ω
VDDA
FIL3
Sandcastle
+5 V
SC
3 x 220
Ω
10 µH
VDD
Blank
100 nF
10 µF
VSS
COR
Ι REF
VDDA VSSA
100 nF
10 nF
27 kΩ
10
µF
10 µH
+5 V
Only ROMless Versions
UED09862
Figure 7
Semiconductor Group
22
1998-10-08
SDA 525X-2
Necessary changes compared to SDA 525x according to preliminary data sheet
1998-02-18 are:
1. RGB-outputs deliver a current instead of a voltage. Any voltage divider can be
replaced by a single resistor. This resistor will have a different dimension. The nominal
output current is 5.2 mA with a resistor of 27 kΩ at the IREF-pin.
2. Instead of FIL1SLC/FIL2SLC/FIL3SLC only FIL3 is needed with changed external
device dimensions. Former FIL1SLC and FIL2SLC remain “not connected”. For best
slicer performance FIL3 is tied to VDDA. FIL3 may be tied to VSSA, if a ripple free VDDA
is available.
3. LCIN and LCOUT are not needed any more and are not connected or used for RD and
WR in the P-MQFP-80-1-package, respectively.
4. P-MQFP-80-1 now has RD (Pin 52), WR (53) and PSEN (1) Pins to connect external
RAM.
5. The 18-MHz-crystal is replaced by a 6-MHz type.
‘n. c.’ = ‘not connected’ means: Pins must be left open.
Semiconductor Group
23
1998-10-08
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