SLA24C32-S/P [INFINEON]
32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus; 32 Kbit的4096× 8位串行CMOS EEPROM的，同步的I2C 2线总线
| 型号： | SLA24C32-S/P |
| 厂家： | 
Infineon |
| 描述： | 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 文件： | 总26页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Standard EEPROM ICs
SLx 24C32
32 Kbit (4096 × 8 bit)
Serial CMOS-EEPROM with
I2C Synchronous 2-Wire Bus
Data Sheet Preliminary 1998-07-27
SLx 24C32
Revision History:
Current Version: Preliminary 1998-07-27
02.98, 04.98
Previous Version:
Page
Page
Subjects (major changes since last revision)
(in previous (in current
Version)
3
Version)
3
Text was changed to “Typical programming time 5 ms for up to
32 bytes”.
11, 12
21
11, 13
21
The erase/write cycle is finished latest after 10 8 ms.
The write or erase cycle is finished latest after 10 4 ms.
The line “erase/write cycle” was removed.
24
24
24
24
Chapter 8.4 “Erase and Write Characteristics” has been added.
2
I C Bus
2
2
Purchase of Siemens I C components conveys the license under the Philips I C patent to use the components in
2
2
the I C system provided the system conforms to the I C specifications defined by Philips.
Edition Preliminary 1998-07-27
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
©
Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.
1
A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2
Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
32 Kbit (4096 × 8 bit) Serial CMOS
SLx 24C32
EEPROMs, I2C Synchronous 2-Wire Bus
Preliminary
Features
• Data EEPROM internally organized as
4096 bytes and 128 pages × 32 bytes
• Page Protection Mode for protecting the
EEPROM against unintended data changes
(SLx 24C32.../P types only)
• Low power CMOS
P-DIP-8-4
• VCC = 2.7 to 5.5 V operation
• Two wire serial interface bus, I2C-Bus compatible
• Three chip select pins to address 8 devices
• Filtered inputs for noise suppression with
Schmitt trigger
• Clock frequency up to 400 kHz
• High programming flexibility
– Internal programming voltage
– Self timed programming cycle including erase
– Byte-write and page-write programming, between
1 and 32 bytes
P-DSO-8-3
– Typical programming time 5 ms for up to 32 bytes
• High reliability
– Endurance 106 cycles1)
– Data retention 40 years1)
– ESD protection 4000 V on all pins
• 8 pin DIP/DSO packages
• Available for extended temperature ranges
– Industrial:
– Automotive:
− 40 °C to + 85 °C
− 40 °C to + 125 °C
1)
Values are temperature dependent, for further information please refer to your Siemens sales office.
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Preliminary 1998-07-27
SLx 24C32
Voltage
Ordering Information
Type
Ordering Code Package
Temperature
SLA 24C32-D
SLA 24C32-D/P
Q67100-H3746 P-DIP-8-4 – 40 °C … + 85 °C 4.5 V...5.5 V
Q67100-H3752
SLA 24C32-S
SLA 24C32-S/P
Q67100-H3748 P-DSO-8-3 – 40 °C … + 85 °C 4.5 V...5.5 V
Q67100-H3753
SLA 24C32-D-3
SLA 24C32-D-3/P
Q67100-H3747 P-DIP-8-4 – 40 °C … + 85 °C 2.7 V...5.5 V
Q67100-H3754
SLA 24C32-S-3
SLA 24C32-S-3/P
Q67100-H3749 P-DSO-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V
Q67100-H3769
SLE 24C32-D
SLE 24C32-D/P
Q67100-H3235 P-DIP-8-4 – 40°C … + 125 °C 4.5 V...5.5 V
Q67100-H3755
SLE 24C32-S
SLE 24C32-S/P
Q67100-H3236 P-DSO-8-3 – 40°C … + 125 °C 4.5 V...5.5 V
Q67100-H3756
Other types are available on request:
– Temperature range (– 55 °C … + 150 °C)
– Package (die, wafer delivery)
– 3V types with automotive temperature range (– 40 °C … + 125 °C)
1
Pin Configuration
P-DIP-8-4
P-DSO-8-3
VCC
WP
SCL
SDA
CS0
CS1
CS2
VSS
1
2
3
4
8
7
6
VCC
WP
CS0
CS1
1
2
8
7
5
IEP02124
CS2
VSS
3
4
6
SCL
SDA
5
IEP02125
Figure 1
Pin Configuration (top view)
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SLx 24C32
Pin Definitions and Functions
Table 1
Pin No.
Symbol
Function
1, 2, 3
CS0, CS1, CS2
Chip select inputs
Ground
4
5
6
7
8
VSS
SDA
SCL
WP
VCC
Serial bidirectional data bus
Serial clock input
Write protection input
Supply voltage
Pin Description
Serial Clock (SCL)
The SCL input is used to clock data into the device on the rising edge and to clock data
out of the device on the falling edge.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses, data or control information into the
device or to transfer data out of the device. The output is open drain, performing a wired
AND function with any number of other open drain or open collector devices. The SDA
bus requires a pull-up resistor to VCC.
Chip Select (CS0, CS1, CS2)
The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven
to VCC or VSS. These inputs allow the selection of one of eight possible devices sharing
a common bus.
Write Protection (WP)
WP switched to VSS allows normal read/write operations.
WP switched to VCC protects the EEPROM against changes (hardware write protection).
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SLx 24C32
2
Description
The SLx 24C32 device is a serial electrically erasable and programmable read only
memory (EEPROM), organized as 4096 × 8 bit. The data memory is divided into
128 pages. The 32 bytes of a page can be programmed simultaneously.
The device conforms to the specification of the 2-wire serial I2C-Bus. Three chip select
pins allow the addressing of 8 devices on the I2C-Bus. Low voltage design permits
operation down to 2.7 V with low active and standby currents. All devices have a
minimum endurance of 106 erase/write cycles.
The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at
2.7 ... 5.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V
type (VCC = 4.5 … 5.5 V) with two temperature ranges for industrial and automotive
applications and as 3 V type (VCC = 2.7 … 5.5 V) for industrial applications. The
EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as
chips.
V
V
CC
SS
CS0 CS1 CS2
WP
Programming
Control
Chip Address
Control
Logic
H.V. Pump
Start/
Stop
Logic
Serial
Control
Logic
SCL
SDA
Address
Logic
X
DEC
EEPROM
Page Logic
Y DEC
Dout/ACK
IEB02525
Figure 2
Block Diagram
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Preliminary 1998-07-27
SLx 24C32
3
I2C-Bus Characteristics
Access to the SLx 24C32 device is given via the I2C bus. This bidirectional bus consists
of two wires SCL and SDA for clock and data. The protocol is master/slave oriented,
where the serial EEPROM always takes the role of a slave.
V
CC
Slave 1
Slave 5
Slave 2
Slave 6
Slave 3
Slave 7
Slave 4
Slave 8
SCL
SDA
Master
V
CC
IES02183
Figure 3
Bus Configuration
Master
Slave
Device that initiates the transfer of data and provides the clock for transmit
and receive operations.
Device addressed by the master, capable of receiving and transmitting
data.
Transmitter The device using the SDA as output is defined as the transmitter. Due to
the open drain characteristic of the SDA output the device applying a low
level wins.
Receiver
The device using the SDA as input is defined as the receiver.
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Preliminary 1998-07-27
SLx 24C32
The conventions for the serial clock line and the bidirectional data line are shown in
figure 4.
SCL
1
2
8
9
1
9
SDA
ACK
ACK
START Condition
Data allowed
to Change
Acknowledge
STOP Condition
IED02128
Figure 4
I2C-Bus Timing Conventions for START Condition, STOP Condition, Data
Validation and Transfer of Acknowledge ACK
Standby
Mode in which the bus is not busy (no serial transmission, no
programming): both clock (SCL) and data line (SDA) are in high
state. The device enters the standby mode after a STOP condition
or after a programming cycle.
START Condition High to low transition of SDA when SCL is high, preceding all
commands.
STOP Condition
Low to high transition of SDA when SCL is high, terminating all
communications. A STOP condition after writing data initiates an
EEPROM programming cycle. A STOP condition after reading
data from the EEPROM initiates the standby mode.
Acknowledge
A successful reception of eight data bits is indicated by the
receiver by pulling down the SDA line during the following clock
cycle of SCL (ACK). The transmitter on the other hand has to
release the SDA line after the transmission of eight data bits.
The EEPROM as the receiving device responds with an
acknowledge, when addressed. The master, on the other side,
acknowledges each data byte transmitted by the EEPROM and
can at any time end a read operation by releasing the SDA line (no
ACK) followed by a STOP condition.
Data Transfer
Data must change only during low SCL state, data remains valid
on the SDA bus during high SCL state. Nine clock pulses are
required to transfer one data byte, the most significant bit (MSB)
is transmitted first.
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SLx 24C32
4
Device Addressing and EEPROM Addressing
After a START condition, the master always transmits a command byte CSW or CSR.
After the acknowledge of the EEPROM control bytes follow, their contents and the
transmitter depend on the previous command byte. The description of the command and
control bytes is shown in table 2.
Command Byte Selects one of the 8 addressable slave devices: The chip select
bits CS2, CS1 and CS0 (bit positions b3 to b1) are compared to their
corresponding hard wired input pins CS2, CS1 and CS0,
respectively.
Selects operation: the least significant bit b0 is low for a write
operation (Chip Select Write Command Byte, CSW) or set high for
a read operation (Chip Select Read Command Byte, CSR).
Control Bytes
Following CSW (b0 = 0): The address bytes AHI/ALO containing
the address bits A0 to A11 are transmitted by the master.
Following CSR (b0 = 1): The EEPROM transmits the read out data.
EEPROM data are read as long as the master pulls down SDA after
each byte in order to acknowledge the transfer. The read operation
is stopped by the master by releasing SDA (no acknowledge is
applied) followed by a STOP condition.
Table 2
Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM
Command
Definition
Function
b7
1
b6
0
b5
1
b4
0
b3
b2
b1
b0
0
CSW
CSR
AHI
CS2 CS1 CS0
CS2 CS1 CS0
A11 A10 A9
chip select for write
chip select for read
1
0
1
0
1
0
0
0
0
A8 high address
A0 low address
ALO
DATA
A7
A6
A5
A4
A3
A2
A1
D7 D6 D5 D4 D3 D2 D1 D0 data byte
The device has an internal address counter which points to the current EEPROM
address.
The address counter is incremented
– after a data byte to be written has been acknowledged, during entry of further data
byte
– during a byte read, thus the address counter points to the following address after
reading a data byte.
The timing conventions for read and write operations are described in figures 5 and 6.
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SLx 24C32
Command Byte (CSW)
Data Transfer to EEPROM
SCL
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
0
1
0
CS2 CS1 CS0
0
ACK
0
0
0
0
A11 A10 A9 A8 ACK
Acknowledge from EEPROM
START from Master
Acknowledge from EEPROM
SCL
SDA
19
20
21
22
23
24
25
26
27
A7 A6 A5 A4 A3 A2 A1 A0
ACK
Acknowledge from EEPROM
IED02516
Figure 5
Timing of the Command Byte CSW
Command Byte (CSR)
Data Transfer from EEPROM
SCL
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
0
ACK
ACK
1
0
CS2 CS1 CS0
1
START from Master
Acknowledge from EEPROM
Acknowledge from Master
IED02517
Figure 6
Timing of the Command Byte CSR
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SLx 24C32
5
Write Operations
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one
programming procedure. Setting the Write Protection pin WP to VCC activates the
hardware write protection and therefore any programming is suppressed. For normal
operation WP has to be set to VSS.
5.1
Byte Write
Address Setting
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following two bytes AHI/ALO
with the EEPROM address (A0 to A11) are loaded into the
address counter of the EEPROM and acknowledged by the
EEPROM.
Transmission of Data Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Programming Cycle
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the bytes AHI (A8 to A11)
and ALO (A0 to A7). The programming procedure consists of
an internally timed erase/write cycle. In the first step, the
selected byte is erased to “1”. With the next internal step, the
addressed byte is written according to the contents of the
buffer.
S
T
A
R
T
S
T
O
P
Bus Activity
Master
Command Byte EEPROM Address EEPROM Address
CSW AHI ALO
Data Byte
SDA Line
0
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
EEPROM
IED02518
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for
speed enhancement in order to detect the end of the erase/write cycle. Please refer to
chapter 5.3, Acknowledge Polling for further information.
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SLx 24C32
5.2
Page Write
Address Setting
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address bytes AHI/ALO are
followed by a sequence of one to a maximum of 32 data bytes
with the new data to be programmed. These bytes are
transferred to the internal page buffer of the EEPROM.
Transmission of Data The first entered data byte will be stored according to the
EEPROM address n given by AHI (A8 to A11) and ALO (A0 to
A7). The internal address counter is incremented
automatically after the entered data byte has been
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A5 through A11.
Only the respective five least significant address bits A0
through A4 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.
Writing over the page border will cause the address counter to
roll over to the first address of the page.
Programming Cycle
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Those bytes of the page that have not been addressed are not included in the
programming.
S
T
A
R
T
S
T
O
P
Command
Byte
CSW
EEPROM
Address
EEPROM
Address
ALO
Data
Byte n
Data
Byte n+1
Data
Byte n+31
...
Bus Activity
Master
AHI
0
P
S
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
EEPROM
IED02519
Figure 8
Page Write Sequence
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SLx 24C32
The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for
speed enhancement in order to detect the end of the erase/write cycle. Please refer to
chapter 5.3, Acknowledge Polling for further information.
5.3
Acknowledge Polling
During the erase/write cycle the EEPROM will not respond to a new command byte until
the internal write procedure is completed. At the end of active programming the chip
returns to the standby mode and the last entered EEPROM byte remains addressed by
the address counter. To determine the end of the internal erase/write cycle acknowledge
polling can be initiated by the master by sending a START condition followed by a
command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/
write cycle is not completed, the device will not acknowledge the transmission. If the
internal erase/write cycle is completed, the device acknowledges the received command
byte and the protocol activities can continue.
Internal Programming
Procedure
Send Start
Send CS-Byte
Acknowledge
No
from EEPROM
received?
Yes
Next Operation
IED02131
Figure 9
Flow Chart “Acknowledge Polling”
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SLx 24C32
STOP from Master initiates erase/write cycle
START from Master
CSR
CSR
CSR
SDA
P
S
1
S
1
S
S
1
P
Acknowledge of EEPROM
indicates complete erase/
write cycle
STOP from Master initiates erase/write cycle
START from Master
e.g. STOP condition
CSW
CSW
CSW
SDA
0
0
0
P
S
S
S
S
P
Acknowledge of EEPROM
indicates complete erase/
write cycle
IED02166
Figure 10
Principle of Acknowledge Polling
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SLx 24C32
6
Read Operations
Reading of the EEPROM data is initiated by the Master with the command byte CSR.
6.1
Random Read
Random read operations allow the master to access any memory location.
Address Setting
The master generates a START condition followed by the
command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low state on the SDA
line. Now the master transmits the EEPROM address (AHI/
ALO) to the EEPROM and the internal address counter is
loaded with the desired address.
Transmission of CSR After the acknowledge for the EEPROM address is received,
the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.
Transmission of
EEPROM Data
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter by one
byte.
STOP Condition from During the following clock cycle the masters releases the bus
Master
and then transmits the STOP condition.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Bus Activity
Master
Command Byte EEPROM Address EEPROM Address
Command Byte
CSR
CSW
AHI
ALO
SDA Line
0
S
S
1
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte
Bus Activity
EEPROM
IED02520
Figure 11
Random Read
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SLx 24C32
6.2
Current Address Read
The EEPROM content is read without setting an EEPROM address, in this case the
current content of the address counter will be used (e.g. to continue a previous read
operation after the Master has served an interrupt).
Transmission of CSR For a current address read the master generates a START
condition, which is followed by the command byte CSR (Chip
Select Read). The receipt of the CSR-byte is acknowledged by
the EEPROM with a low on the SDA line.
Transmission of
EEPROM Data
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter by one
byte.
STOP Condition from During the following clock cycle the masters releases the bus
Master
and then transmits the STOP condition.
S
T
A
R
T
S
T
O
P
Bus Activity
Master
Command Byte
CSR
SDA Line
S
1
P
A
C
K
Data Byte
Bus Activity
EEPROM
IED02132
Figure 12
Current Address Read
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SLx 24C32
6.3
Sequential Read
A sequential read is initiated in the same way as a current read or a random read except
that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM
then continues the data transmission. The internal address counter is incremented by
one during each data byte transmission.
A sequential read allows the entire memory to be read during one read operation. After
the highest addressable memory location is reached, the internal address pointer “rolls
over” to the address 0 and the sequential read continues.
The transmission is terminated by the master by releasing the SDA line (no
acknowledge) and generating a STOP condition (see figure 13).
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
Bus Activity
Master
Command Byte
CSW
SDA Line
S
1
P
A
C
K
Data Byte n
Data Byte n+1
Data Byte n+x
Bus Activity
EEPROM
IED02134
Figure 13
Sequential Read
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SLx 24C32
7
Page Protection ModeTM
The page protection mode is supported by the SLx 24C32.../P types only. For example
SLA 24C32-D/P has the same functionality as SLA 24C32-D enhanced by page
protection mode.
Each page (32 bytes) in the data memory can be protected against unintended data
changes by an associated protection bit. The protection bit memory consists of an
additional EEPROM of 128 bit (figure 14).
Data in the data memory can be modified only if the assigned protection bit is erased
(logical state “1”). After writing the data bytes to a page, the protection is achieved by
writing the associated protection bit (logical state “0”). Further changes in the data in a
protected page is possible only after erasing the protection bit.
Data Memory Area
0
1
2
3
Page 0
Page 1
Page 2
Page 3
.
.
.
.
.
.
.
.
.
n
Page n
0
1
2
3
. . .
31
Byte
Bit
IED02521
Figure 14
Data Page and Assigned Protection Memory
A special procedure to write or erase a protection bit guarantees proper activation or
deactivation of page protection. For protection bit write or erase all 32 data bytes of the
respective page have to be entered for verification. The data then are compared
internally with the data to be protected. In case of identity the protection bit is written or
erased respectively.
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SLx 24C32
7.1
Protection Bit Handling
The bits of the protection memory can be addressed directly for reading or programming.
A protection bit address corresponds to the lowest address within the respective page
(A5 to A11, A0 to A4 = zero). The status of each protection bit is sensed internally. A
written state (“0”) prevents programming in the associated page. If an already protected
memory page is accidentally addressed for programming, the programming procedure
is suppressed.
The conventional I2C-Bus protocol allows data bytes to be read and programmed only.
Therefore an independent instruction sequence for addressing and manipulation of
protection bits is implemented. For protection bit instructions the command byte CSW
with its preceding START condition followed by the associated address bytes have to be
entered twice (figures 15 through 17). The first command byte CSW is followed by the
address bytes AHI/ALO with the bit/page address A0 through A4 always at zero. The
second CSW is required for entering a control byte CTx for protection bit manipulation.
The three control bytes for read, write or erase of a protection bit are listed below
(table 3):
Table 3
Control Byte for Protection Bit Manipulation
Address
Name
Definition
Function
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
0
b0
0
CTR
CTW
CTE
Protection bit read
Protection bit write
Protection bit erase
x
x
x
x
x
x
0
1
x
x
x
x
x
x
1
1
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SLx 24C32
7.2
Protection Bit Write and Erase
For writing or erasing a protection bit the data of the respective page have to be known
by the master. The master has to present the page data as a reference for comparison
by the EEPROM. A successful comparison is necessary in order to change the value of
the protection bit.
The data of the page are not affected by the write or erase procedure of the protection
bit. The I2C-Bus protocol is shown in figure 15 for protection bit write and figure 16 for
protection bit erase.
S
T
A
R
T
S
T
A
R
T
Command EEPROM EEPROM
Command
Byte
CSW
Control
Byte
CTW
Data
Byte n
Data
Data
S
T
O
P
Bus
Activity
Master
...
Byte
Address
Address
Byte n+1 Byte n+31
CSW
AHI
ALO
0
0 0 0 0 0
0
0 1
S
S
P
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
EEPROM
IED02522
Figure 15
Sequence for Protection Bit Write
S
S
T
A
R
T
Command EEPROM EEPROM
T
A
R
T
Command
Byte
CSW
Control
Byte
CTE
Data
Byte n
Data
Data
S
Bus
Activity
Master
T
O
P
Byte
Address
Address
Byte n+1 Byte n+31
CSW
AHI
ALO
0
0 0 0 0 0
0
1 1
S
S
P
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
EEPROM
IED02523
Figure 16
Sequence for Protection Bit Erase
The first command byte CSW followed by the address bytes AHI/ALO determines the
page to be protected. The second command byte CSW (identical content of first CSW)
is followed by the control byte CTW = 01H for protection bit write or CTE = 03H for
protection bit erase. Depending on CTx, the addressed protection bit will be either
written or erased.
The control byte CTx is followed by 32 parameter bytes identical to the 32 data bytes of
the page to be protected or unprotected. The data of the first entered byte must be
identical to the data byte stored at the lowest address of the current page. The other
Semiconductor Group
20
Preliminary 1998-07-27
SLx 24C32
31 bytes have to be identical to the bytes stored in ascending address order within the
same page.
A successful verification of each byte is indicated by the EEPROM by pulling the SDA
line to low (acknowledge ACK).
The bit programming procedure is initiated by the STOP condition after verification of the
last byte. Programming is started only if all 256 bits of a page have been verified
successfully. If bit programming has taken place, the address counter points to the
uppermost address of the respective page. The write or erase cycle is finished latest
after 4 ms. Acknowledge polling can be used for speed enhancement in order to detect
the end of the write or erase cycle (refer to chapter 5.3, Acknowledge Polling).
7.3
Protection Bit Read
The byte sequence for random bit read is shown in figure 17.
S
T
A
R
T
S
T
A
R
T
A
C
K
A
C
K
Command EEPROM EEPROM
Command
Byte
CSW
Control
Byte
CTR
S
T
O
P
Bus
Activity
Master
Byte
Address
Address
CSW
AHI
ALO
0
0 0 0 0 0
0
0 0
S
S
P
SDA Line
b
b
b
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data
Byte n
Data
Byte n+1
...
Bus Activity
EEPROM
b = Protection Bit
IED02524
Figure 17
Byte Sequence for Protection Bit Read
The first command byte CSW followed by the address bytes AHI/ALO determine the
protection bit to be read. The second command byte CSW is followed by the control byte
00H for protection bit read. The first bit (MSB) of the transferred byte is the protection bit
of the addressed page. The other 7 bits are not valid. The page protection status is
indicated as follows:
Protection Bit = 1: A normal write operation changes the data in the associated page
Protection Bit = 0: The data in the associated page are protected against changes.
If the master acknowledges a byte with a low state of the SDA line, the protection bit of
the next page can be read as the first bit of the following byte. If the master releases the
SDA line, a STOP condition has to complete the read procedure. Any number of bytes
with a page protection status at the first bit position can be requested by the master. After
the bit of the uppermost page has been addressed an overflow of the address counter
occurs and the protection bit of the first page will be read next.
Semiconductor Group
21
Preliminary 1998-07-27
SLx 24C32
8
Electrical Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not
otherwise specified, typical characteristics apply at TA = 25 °C and the given supply
voltage.
8.1
Absolute Maximum Ratings
Stresses above those listed here may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational section of this data sheet is not implied.
Exposure to absolute maximum ratings for extended periods may affect device reliability.
Parameter
Limit Values
Units
Operating temperature
range 1 (industrial)
range 2 (automotive) – 40 to + 125
– 40 to + 85
°C
°C
Storage temperature
Supply voltage
– 65 to + 150
°C
V
– 0.3 to + 7.0
All inputs and outputs with respect to ground
ESD protection (human body model)
– 0.3 to VCC + 0.5
V
4000
V
8.2
DC Characteristics
Symbol
Parameter
Limit Values
typ. max.
5.5
Units Test Condition
min.
Supply voltage VCC
4.5
V
5 V type
VCC
2.7
5.5
3
V
3 V type
Supply current1) ICC
mA
VCC = 5 V; fc = 100 kHz
(write)
Standby
current2)
ISB
ILI
1
µA
µA
µA
V
Inputs at VCC or VSS
VIN = VCC or VSS
Input leakage
current
0.1
0.1
1
Output leakage ILO
current
1
V
OUT = VCC or VSS
Input low
voltage
VIL
– 0.3
0.3 × VCC
Semiconductor Group
22
Preliminary 1998-07-27
SLx 24C32
8.2
DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
typ. max.
Units Test Condition
min.
Input high
voltage
VIH
0.7 × VCC
VCC + 0.5 V
Output low
voltage
VOL
CI/O
0.4
83)
V
IOL = 3 mA; VCC = 5 V
IOL = 2.1 mA; VCC = 3 V
Input/output
capacitance
(SDA)
pF
pF
VIN = 0 V; VCC = 5 V
Input
CIN
63)
VIN = 0 V; VCC = 5 V
capacitance
(other pins)
1)
The values for ICC are maximum peak values
Valid over the whole temperature range
This parameter is characterized only
2)
3)
Semiconductor Group
23
Preliminary 1998-07-27
SLx 24C32
8.3
AC Characteristics
Parameter
Symbol Limit Values
Limit Values Units
VCC = 2.7-5.5 V VCC = 4.5-5.5 V
min.
max.
min.
max.
SCL clock frequency
Clock pulse width low
Clock pulse width high
SDA and SCL rise time
SDA and SCL fall time
Start set-up time
fSCL
100
400
kHz
µs
µs
ns
ns
µs
µs
ns
µs
µs
ns
µs
µs
tlow
4.7
4.0
1.2
thigh
0.6
1)
tR
1000
300
300
300
1)
tF
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tAA
4.7
4.0
200
0
0.6
0.6
100
0
Start hold time
Data in set-up time
Data in hold time
SCL low to SDA data out valid
Data out hold time
0.1
100
4.0
4.7
4.5
0.1
50
0.9
tDH
Stop set-up time
tSU.STO
0.6
1.2
Time the bus must be free before tBUF
a new transmission can start
SDA and SCL spike suppression tl
50
100
50
100
ns
time at constant inputs
1)
The minimum rise and fall times can be calculated as follows: (20 + (0.1/pF) × Cb) ns
Example: Cb = 100 pF → tR = (20 + 0.1 × 100) ns = 30 ns
8.4
Erase and Write Characteristics
Symbol Limit Values
VCC = 2.7-5.5 V VCC = 4.5-5.5 V
Parameter
Limit Values Units
typ.
5
max.
typ.
5
max.
Erase + write cycle (per page)
Erase page protection bit
Write page protection bit
tWR
8
4
4
8
4
4
ms
ms
ms
2.5
2.5
2.5
2.5
Semiconductor Group
24
Preliminary 1998-07-27
SLx 24C32
t
R
t
t
t
HIGH
F
LOW
SCL
t
t
SU.DAT
SU.STA
t
t
t
t
BUF
HD.STA
HD.DAT
SU.STO
SDA In
Start Condition
Stop Condition
t
t
DH
AA
SDA Out
IED02127
Figure 18
Bus Timing Data
Semiconductor Group
25
Preliminary 1998-07-27
SLx 24C32
9
Package Outlines
P-DIP-8-4
(Plastic Dual In-line Package)
P-DSO-8-3
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
26
Preliminary 1998-07-27
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