SLB 9665XT2.0 [INFINEON]

英飞凌可信平台模块 (TPM 2.0) SLB 9665 完全符合基于最新可信计算组织 (TCG) 规范 2.0 的 TPM 标准。;


型号：	SLB 9665XT2.0
厂家：	Infineon
描述：	英飞凌可信平台模块 (TPM 2.0) SLB 9665 完全符合基于最新可信计算组织 (TCG) 规范 2.0 的 TPM 标准。
文件：	总25页 (文件大小：496K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Data Sheet

Devices

•

SLB 9665VQ2.0

SLB 9665XQ2.0

SLB 9665TT2.0

SLB 9665XT2.0

Key Features

•

Compliant to TPM Main Specification, Family "2.0", Level 00, Revision 01.16 (see [3])

LPC interface

Meets Intel TXT, Microsoft Windows and Google Chromebook certification criteria for successful platform

qualification

•

Random Number Generator (RNG) according to NIST SP800-90A

Full personalization with Endorsement Key (EK) and EK certificate

Standard (-20..+85°C) and enhanced temperature range (-40..+85°C)

TSSOP-28 and VQFN-32 package

Pin-compatible to SLB 9660

Optimized for battery operated devices: low standby power consumption (typ. 150µA)

24 PCRs (SHA-1 or SHA-256)

7206 Byte free NV memory

Up to 3 loaded sessions (TPM_PT_HR_LOADED_MIN)

Up to 64 active sessions (TPM_PT_ACTIVE_SESSIONS_MAX)

Up to 3 loaded transient Objects (TPM_PT_HR_TRANSIENT_MIN)

Up to 7 loaded persistent Objects (TPM_PT_HR_PERSISTENT_MIN)

Up to 8 NV counters

Up to 1 kByte for command parameters and response parameters

Up to 768 Byte for NV read or NV write

1280 Byte I/O buffer

Built-in support by Linux Kernel Version 3.10 and higher

Data Sheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

Revision 1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

About this document

Scope and purpose

This data sheet describes the OPTIGA™ TPM SLB 9665 TPM2.0 Trusted Platform Module together with its features,

functionality and programming interface.

Intended audience

This data sheet is primarily intended for system developers.

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Table of contents

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

List of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SYNC Field Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Localities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

LPC Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

1.3

1.4

Device Types / Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Typical Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1

4.2

4.3

4.4

4.5

Package Dimensions (TSSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Packing Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chip Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1

5.2

5.3

Package Dimensions (VQFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Packing Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chip Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1

6.2

6.3

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Licenses and Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

List of figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Pinout of the SLB 9665TT2.0 / SLB 9665XT2.0 (PG-TSSOP-28-2 Package, Top View) . . . . . . . . . . . . . . 9

Pinout of the SLB 9665VQ2.0 / SLB 9665XQ2.0 (PG-VQFN-32-13 Package, Top View). . . . . . . . . . . . . . 9

Typical Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LRESET# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Package Dimensions PG-TSSOP-28-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Tape & Reel Dimensions PG-TSSOP-28-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Recommended Footprint PG-TSSOP-28-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chip Marking PG-TSSOP-28-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package Dimensions PG-VQFN-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10 Tape & Reel Dimensions PG-VQFN-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11 Recommended Footprint PG-VQFN-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12 Chip Marking PG-VQFN-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

List of tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

Table 11

Table 12

LT Register Access Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Not Connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DC Characteristics for non-LPC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC Characteristics for LPC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

LPC Interface

The OPTIGA™ TPM SLB 9665 features the Low Pin Count (LPC) interface (for a specification, please refer to [1]).

From the cycle types defined in the mentioned specification, only the TPM-type cycles (read and write) are

supported. All accesses with different cycle types are ignored by the device.

1.1

SYNC Field Usage

Since the legacy interface is not supported anymore, the OPTIGA™ TPM SLB 9665 will never generate SYNC

ERRORs on the LPC. It will either acknowledge a cycle with SYNC OK or use a “Long Wait” SYNC field to enlarge a

cycle (that means, inserting wait states on the bus).

1.2

Localities

The interface explicitly does not support standard IO cycles (read and write). This implies that IO-mapped

addressing of the device is not possible; only accesses via the locality-based TPM-type cycles are possible which

also means that “locality none” as defined in [4] is not supported as well.

For a detailed description of the locality addressing scheme and the registers located in each locality, please refer

to [4] as well.

1.3

Power Management

The OPTIGA™ TPM SLB 9665 does not support the LPC power down signal (signal LPCPD) or the clock run

protocol (signal CLKRUN). Power management is handled internally; no explicit power-down or standby mode is

available. The device automatically enters a low-power state after each successful command/response

transaction. If a transaction is started on the LPC bus from the host platform, the device will wake immediately

and will return to the low power idle mode 50 ms after the last TPM command has been executed.

1.4

LPC Access Rights

The registers located in the address space of the OPTIGA™ TPM SLB 9665 are described in the respective TCG

document (please refer to [4]). The registers READFIFO and WRITEFIFO mentioned in Table 1 below refer to the

DATAFIFO register, the names are used to state whether this register is read or written.

Each register has its own access rights which describe if the register is updated on a write or can be read if the

associated ACTIVE.LOCALITY is set respectively not set. If the access cycle is not accepted by the TPM, it will be

master aborted (no LPC SYNC cycle will be generated and no action is done on the internal registers). Table 1

shows which operation is done by the TPM on each register depending on the ACTIVE.LOCALITY bit.

Note:

In Table 1, “abort” means that no valid SYNC is generated when a cycle is seen by the interface which

shall be aborted. The data present in an aborted write access cycle does not change the addressed

Table 1

LT Register Access Matrix

ACTIVE.LOCALITY set for this ACTIVE.LOCALITY set for

ACTIVE.LOCALITY not set

locality

READ

read

different LOCALITY

WRITE

write

READ

abort

read

WRITE

READ

abort

read

WRITE

abort

STS

abort

INT.ENABLE

INT.VECTOR

read

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

LPC Interface

Table 1

LT Register Access Matrix (continued)

ACTIVE.LOCALITY set for this ACTIVE.LOCALITY set for

ACTIVE.LOCALITY not set

locality

READ

read

different LOCALITY

WRITE

READ

read

WRITE

READ

read

WRITE

abort

INT.STATUS

reset

abort

interrupt

INT.CAPABILITY read

- (abort)

write

read

abort

read

- (abort)

write

read

abort

read

- (abort)

write

ACCESS

read

READFIFO

WRITEFIFO

read¹⁾

abort

read

abort

write

abort

Configuration

Registers

write

HASH.START

HASH.DATA

HASH.END

abort

write

write³⁾

abort

write²⁾

abort

1) If STS.DATA.AVAIL is not set, this access is ‘abort’.

2) The write to HASH.START sets ACCESS.ACTIVE.LOCALITY of locality 4.

3) The write to HASH.END is an implicit release of the TPM (like a ‘1’-write to the ACCESS.ACTIVE.LOCALITY bit of locality 4).

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Device Types / Ordering Information

The OPTIGA™ TPM SLB 9665 product family features devices with different packages. Table 2 shows the different

versions. Please check the latest “Errata and Updates” document of the OPTIGA™ TPM SLB 9665 for availability of

these versions.

Table 2

Device Configuration

Device Name

Package

Remarks

SLB 9665VQ2.0

SLB 9665XQ2.0

SLB 9665TT2.0

SLB 9665XT2.0

PG-VQFN-32-13

PG-TSSOP-28-2

Standard temperature range

Enhanced temperature range

Standard temperature range

Enhanced temperature range

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Pin Description

TPM

SLB 9665TT2.0

PG-TSSOP-28-2

Figure 1

Pinout of the SLB 9665TT2.0 / SLB 9665XT2.0 (PG-TSSOP-28-2 Package, Top View)

VDD

LAD1

LFRAME#

LCLK

TPM

GPIO

LAD2

SLB 9665VQ2.0

VDD

LAD3

PG-VQFN-32-13

LRESET#

Figure 2

Pinout of the SLB 9665VQ2.0 / SLB 9665XQ2.0 (PG-VQFN-32-13 Package, Top View)

Table 3

Buffer Type

Buffer Types

Description

Tri-State pin

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Pin Description

Table 3

Buffer Type

Buffer Types (continued)

Description

Schmitt-Trigger pin

Open-Drain pin

Table 4

I/O Signals

Pin Number

Name

LAD0

Type

Buffer

Type

Function

PG-TSSOP- PG-VQFN-

28-2

32-13

I/O

LPC Address/Data Bit 0

Multiplexed LPC command, address and data bus.

Connect these pins to the LAD[3:0] pins of the LPC

host.

LAD1

I/O

LPC Address/Data Bit 1

see description of LAD0 above.

LAD2

LPC Address/Data Bit 2

see description of LAD0 above.

LAD3

LPC Address/Data Bit 3

see description of LAD0 above.

LFRAME#

LPC Framing Signal

LPC framing signal. This pin is connected to the LPC

LFRAME# signal and indicates the start of a new

cycle on the LPC bus or the termination of a broken

cycle. The signal is active low.

LCLK

Clock Input

This pin provides the external clock for the chip and

is typically connected to the PCI clock of the host.

The clock frequency range is 1 MHz - 33 MHz

(nominal).

LRESET#

GPIO

Reset

External reset signal. Asserting this pin

unconditionally resets the device. The signal is

active low and is typically connected to the PCIRST#

signal of the host.

I/O

General Purpose I/O

This pin is a general purpose I/O pin. It is defined as

GPIO-Express-00, please refer to [4] and the PCI-SIG

ECN “Trusted Configuration Space for PCI Express”.

This pin may be left unconnected; however, to

minimize power consumption, it shall be connected

to a fixed level (either GND or VDD) via an external

resistor (4.7 kΩ..10 kΩ).

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Pin Description

Table 4

I/O Signals (continued)

Name

Pin Number

Type

Buffer

Type

Function

PG-TSSOP- PG-VQFN-

28-2

32-13

Physical Presence

This pin indicates physical presence; for usage of

this signal, please refer to the TCG specification

v1.2. The TPM 2.0 device does not use this

functionality.

For compatibility reasons (downgrade capability to

a TPM 1.2), the pin should be connected to a

jumper. The standard position of the jumper should

connect the pin to GND. If the pin is connected to

VDD, some special commands are enabled for a

TPM 1.2.

This pin does not have an internal pull-up or

pulldown resistor and must not be left floating if it

is used for physical presence detection via

hardware pin.

If physical presence detection via hardware pin is

not used, this pin may be left unconnected;

however, to minimize power consumption, it shall

be connected to a fixed level (either GND or VDD)

directly or via an external resistor.

SERIRQ

Name

I/O

Serial Interrupt Request

Interrupt request signal, uses the serial interrupt

request protocol (see [2]). Connect to the LPC host.

Table 5

Power Supply

Pin Number

Type

Buffer

Type

Function

PG-TSSOP- PG-VQFN-

28-2 32-13

5, 10, 19, 24 1, 9, 10, 20, VDD

PWR

GND

—

Power Supply

All VDD pins must be connected externally and

should be bypassed to GND via 100 nF capacitors.

4, 11, 18, 25 16, 26, 32

GND

Ground

All GND pins must be connected externally.

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Pin Description

Table 6

Not Connected

Pin Number

Name

Type

Buffer

Type

Function

PG-TSSOP- PG-VQFN-

28-2 32-13

1, 2, 3, 8, 12, 2, 3, 6, 7, 11, NC

13, 14, 15, 28 12, 13, 14,

15, 17, 29,

—

Not Connected

All pins must not be connected externally (must be

left floating).

30, 31

—

Not Connected

This pin may be connected to the Reset signal (for

backward compatibility) or may be left floating.

3.1

Typical Schematic

Figure 3 shows the typical schematic for the OPTIGA™ TPM SLB 9665. The power supply pins should be bypassed

to GND with capacitors located close to the device. The physical presence input may be connected to a jumper as

shown in the schematic; or it may be driven by other devices (this is application- or platform-dependent).

3.3V

LAD[3:0]

LCLK

LAD[3:0]

LCLK

VDD

GND

1 µF

LFRAME#

LRESET#

LFRAME#

LRESET#

4x 100 nF (place close to

device VDD/GND pins)

SERIRQ

3.3V

GPIO

OPTIGA^TMTPM

SLB 9665

Schematic _SLB9665 .vsd

Figure 3

Typical Schematic

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Electrical Characteristics

This chapter lists the maximum and operating ranges for various electrical and timing parameters.

4.1

Absolute Maximum Ratings

Table 7

Absolute Maximum Ratings

Parameter

Symbol

Min.

Values

Unit

Note or Test Condition

Typ. Max.

Supply Voltage

V_DD

-0.3

-20

-40

–

3.6

–

Voltage on any pin

Ambient temperature

Storage temperature

V_max

T_A

V_DD+0.3

–

°C

Standard temperature devices

Enhanced temperature devices

–

T_A

T_S

125

2000

ESD robustness HBM:

V_ESD,HBM

According to EIA/JESD22-A114-B

1.5 kΩ, 100 pF

ESD robustness

V_ESD,CDM

–

500

100

According to ESD Association

Standard STM5.3.1 - 1999

Latchup immunity

I_latch

According to EIA/JESD78

Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability. Maximum

ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the

integrated circuit.

4.2

Functional Operating Range

Table 8

Functional Operating Range

Parameter

Symbol

Min.

Values

Unit

Note or Test Condition

Typ. Max.

Supply Voltage

V_DD

T_A

3.0

-20

-40

–

3.3

–

3.6

–

Ambient temperature

Useful lifetime

°C

Standard temperature devices

Enhanced temperature devices

T_A

–

Operating lifetime

Average T_Aover lifetime

–

°C

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Electrical Characteristics

4.3

DC Characteristics

T_A= 25°C, V_DD= 3.3V ± 0.3V unless otherwise noted

Table 9

Current Consumption

Symbol

Parameter

Values

Unit

Note or Test Condition

Min.

Typ. Max.

Current consumption in I_{VDD_Active}

Active mode

2.5

Assuming operating state S0, that

means active. Note that since the

device is mostly in an internal

sleep state in a “typical”

application, the typical average

current consumption is far less

than the maximum value. It is

assumed that in a normal

environment, the device is in an

internal sleep state for

approximately 90% of the

operating time of the platform.

Current consumption in I_{VDD_Sleep}

0.9

Pins LRESET#, LFRAME#, LADn,

Sleep mode

SERIRQ = V_DD.

Assuming operating state S0 with

active clock. No ongoing internal

TPM operation. The device is in an

internal sleep state.

Current consumption in I_{VDD_Sleep_CS}

Sleep mode with stopped

clock

150

1.8

µA

Pins LRESET#, LFRAME#, LADn,

SERIRQ = V_DDand LCLK = GND.

Assuming operating state S3 with

clock stopped.¹⁾

Current consumption in I_{VDD_LPI}

Pins LRESET#, LFRAME#, LADn,

Low Power Idle mode

SERIRQ = V_DD.

Assuming operating state S0 with

active clock. No ongoing internal

TPM operation. The device is in an

internal low power idle state.

Current consumption in I_{VDD_LPI_CS}

Low Power Idle mode

with stopped clock

1.3

Pins LRESET#, LFRAME#, LADn,

SERIRQ = V_DDand LCLK = GND.

Assuming operating state S3 with

clock stopped.¹⁾

1) Obviously, this value is zero if the TPM is not powered in S3 state (this is platform dependent).

Note:

Current consumption does not include any currents flowing through resistive loads on output pins! For

the definition of power/operating states, please refer to the ACPI standard.

Low power idle mode will be entered 50 ms after the last TPM command has been executed.

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Electrical Characteristics

Table 10

DC Characteristics for non-LPC Pins

Parameter

Symbol

Min.

Values

Typ.

Unit

Note or Test Condition

Max.

V_DD

Input voltage high

Input voltage low

V_IH

V_IL

I_IH

0.7 V_DD

GPIO and PP pins

0.3 V_DD

GPIO and PP pins

Input high leakage

current

-15

µA

V_IN= V_DD, GPIO and PP pins

Input low leakage current I_IL

-15

µA

V_IN= 0V, GPIO and PP pins

I_OH= 1mA, Pin GPIO

Output high voltage

Output low voltage

V_OH

V_OL

V_DD-0.3

0.3

I_OL= 1mA, Pin GPIO

Table 11

DC Characteristics for LPC Pins

Symbol

Parameter

Values

Unit

Note or Test Condition

Min.

0.5 V_DD

-0.3

Typ. Max.

V_DD+0.3

Ínput voltage high

Input voltage low

V_IH

V_IL

I_IH

All signal pins except GPIO and PP

0.28 V_DD

Input high leakage

current

-10

µA

V_IN= V_DD, all signal pins except

GPIO and PP

Input low leakage current I_IL

-10

µA

V_IN= 0V, all signal pins except GPIO

and PP

Output high voltage

Output low voltage

V_OH

V_OL

0.9 V_DD

I_OH= -500µA, pins LAD[3:0] and

SERIRQ

0.1 V_DD

I_OL= 1.5mA, pins LAD[3:0] and

SERIRQ

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Electrical Characteristics

4.4

AC Characteristics

t_POR

VDD

t_RSTIN

t_WRST

t_RSTIN

t_WRST

t_RSTIN

TPM commands

LRESET#

LRESET_Timing .vsdx

Figure 4

LRESET# Timing

Table 12

AC Characteristics

Symbol

Parameter

Values

Typ.

Unit

Note or Test Condition

Min.

Max.

Cold (Power-On) Reset

Warm Reset

t_POR

µs

see Section 4.5

t_WRST

t_RSTIN

Reset Inactive Time

4.5

Timing

Some pads are disabled after deassertion of the reset signal for up to 500 µs. This is especially important for the

SERIRQ signal; after deassertion of the reset signal, this signal is only valid after that time has expired.

The OPTIGA™ TPM SLB 9665 features a sophisticated protection mechanism against dictionary attacks on TPM-

based authorization data. Basically, the device counts the number of failed authorization attempts in a counter

which is located in the non-volatile memory. An attacker who has physical access to the device could try to

cirumvent that mechanism by resetting the device after the authorization attempt but before the updated failure

counter has been written into the NVM.

Certain countermeasures have been added to the OPTIGA™ TPM SLB 9665. In certain time windows during

power-on or warm boot of the device, such reset events might influence the dictionary attack counters and

trigger other security mechanisms as well. In worst case, this might trigger special security defense modes from

which a recovery is very complex or even not possible.

To avoid that the OPTIGA™ TPM SLB 9665 reaches such a security defense state, the LRESET# signal must not be

asserted in certain time windows. After the deassertion of the LRESET# signal, the system should wait for a

minimum time of t_RSTINbefore asserting LRESET# again (see Figure 4 and Table 12).

TPM commands should only be started after t_RSTINhas expired (see Figure 4 again). If a TPM command is running,

LRESET# should not be asserted; otherwise, this might also trigger some security functions. When the TPM shall

be reset, the command TPM2_Shutdown should be issued before the assertion of the LRESET# signal.

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Package Dimensions (TSSOP)

All dimensions are given in millimeters (mm) unless otherwise noted. The packages are “green” and RoHS

compliant.

0.1

4.4

0.65

0.1

28x

0.1

0.6

SEATING

PLANE

COPLANARITY

6.4

0.2 A-B, H C

2x 14 TIPS

13 x 0.65 = 8.45

+0.08

-0.03

0.22

28x

A B C

0.1

9.7

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Does not include dambar protrusion of 0.08 max. per side

3) Does not include interlead flash or protrusion of 0.25 max. per side

PG-TSSOP-28-2, -16-PO V07

Figure 5

Package Dimensions PG-TSSOP-28-2

5.1

Packing Type

PG-TSSOP-28-2: Tape & Reel (reel diameter 330mm), 3000 pcs. per reel

0.3

Index

Marking

1.2

1.6

6.8

PG-TSSOP-28-2, -16-TP V01

Figure 6

Tape & Reel Dimensions PG-TSSOP-28-2

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Package Dimensions (TSSOP)

5.2

Recommended Footprint

Controlling dimension is millimeters (mm).

0.29

0.25

0.65

Stencil apertures

PG-TSSOP-28-2, -16-FP V01

Copper

Solder mask

Figure 7

Recommended Footprint PG-TSSOP-28-2

5.3

Chip Marking

Line 1: SLB9665TT20 or SLB9665XT20, see Table 2

Line 2: G <datecode> KMC, <K> indicates assembly site code, <MC> indicates mold compound code

Line 3: 00 <Lot number>, the 00 is an internal FW indication (only at manufacturing due to field upgrade option)

12345678901

KMC

12XXXXXXXXXXX

Assembly Site Code

Mold Compound Code

Softwarecode

Lot Code

ChipMarking.vsd

Figure 8

Chip Marking PG-TSSOP-28-2

For details and recommendations regarding assembly of packages on PCBs, please refer to

http://www.infineon.com/cms/en/product/technology/packages/

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Package Dimensions (VQFN)

All dimensions are given in millimeters (mm) unless otherwise noted. The packages are “green” and RoHS

compliant.

7 x 0.5 = 3.5

0.5

0.9 MAX.

0.1

32x

0.05 C

0.1 C

Index Marking

0.1

Index Marking

+0.05

-0.07

32x

0.25

0.1

A B C

0.1

3.6

0.05

(0.2)

0.05 MAX.

0.05

(4.2)

0.4

PG-VQFN-32-13-PO V01

Figure 9

Package Dimensions PG-VQFN-32-13

6.1

Packing Type

PG-VQFN-32-13: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel

0.3

5.25

1.1

Index Marking

PG-VQFN-32-13-TP V01

Figure 10 Tape & Reel Dimensions PG-VQFN-32-13

6.2

Recommended Footprint

Figure 11 shows the recommended footprint for the PG-VQFN-32-13 package. The exposed pad of the package is

internally connected to GND. It shall be connected to GND externally as well.

4.1

3.6

Package outline 5 x 5

0.5

0.25

PG-VQFN-32-13-FP V01

Figure 11 Recommended Footprint PG-VQFN-32-13

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Package Dimensions (VQFN)

6.3

Chip Marking

Line 1: SLB9665

Line 2: VQ20 yy or XQ20 yy (see Table 2), the <yy> is an internal FW indication (only at manufacturing due to field

upgrade option)

Line 3: <Lot number> H <datecode>

Infineon

1234567

VQ20 YY

Softwarecode

XXH

Lot Code

ChipMarking_VQFN.vsd

Figure 12 Chip Marking PG-VQFN-32-13

For details and recommendations regarding assembly of packages on PCBs, please refer to

http://www.infineon.com/cms/en/product/technology/packages/

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

References

[1] —, “Low Pin Count (LPC) Interface Specification”, Version 1.1, Intel

[2] —, “Serialized IRQ Support for PCI Systems”, Version 6.0, September 1, 1995, Cirrus Logic et al.

[3] —, “Trusted Platform Module Library (Part 1-4)”, Family 2.0, Level 00, Rev. 01.16, October 30, 2014, TCG

[4] —, “TCG PC Client Specific Platform TPM Profile (PTP) Specification”, Family 2.0, Level 00, Rev. 43, January

26, 2015, TCG

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Terminology

ESW

HMAC

LPC

Embedded Software

Hashed Message Authentication Code

Low Pin Count (bus)

PCR

Platform Configuration Register

Public Endorsement Key

Symmetric Crypto Processor

Trusted Computing Group

Trusted Platform Module

TCG Software Stack

PUBEK

SCP

TCG

TPM

TSS

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Licenses and Notices

The following License and Notice Statements are reproduced from [3].

Licenses and Notices

1. Copyright Licenses:

Trusted Computing Group (TCG) grants to the user of the source code in this specification (the "Source Code") a

worldwide, irrevocable, nonexclusive, royalty free, copyright license to reproduce, create derivative works,

distribute, display and perform the Source Code and derivative works thereof, and to grant others the rights

granted herein.The TCG grants to the user of the other parts of the specification (other than the Source Code) the

rights to reproduce, distribute, display, and perform the specification solely for the purpose of developing

products based on such documents.

2. Source Code Distribution Conditions:

Redistributions of Source Code must retain the above copyright licenses, this list of conditions and the following

disclaimers.

Redistributions in binary form must reproduce the above copyright licenses, this list of conditions and the

following disclaimers in the documentation and/or other materials provided with the distribution.

3. Disclaimers:

THE COPYRIGHT LICENSES SET FORTH ABOVE DO NOT REPRESENT ANY FORM OF LICENSE OR WAIVER, EXPRESS

OR IMPLIED, BY ESTOPPEL OR OTHERWISE, WITH RESPECT TO PATENT RIGHTS HELD BY TCG MEMBERS (OR

OTHER THIRD PARTIES) THAT MAY BE NECESSARY TO IMPLEMENT THIS SPECIFICATION OR OTHERWISE. Contact

TCG Administration (admin@trustedcomputinggroup.org) for information on specification licensing rights

available through TCG membership agreements.

THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO EXPRESS OR IMPLIED WARRANTIES WHATSOEVER,

INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ACCURACY,

COMPLETENESS, OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, OR ANY WARRANTY OTHERWISE

ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.

Without limitation, TCG and its members and licensors disclaim all liability, including liability for infringement of

any proprietary rights, relating to use of information in this specification and to the implementation of this

specification, and TCG disclaims all liability for cost of procurement of substitute goods or services, lost profits,

loss of use, loss of data or any incidental, consequential, direct, indirect, or special damages, whether under

contract, tort, warranty or otherwise, arising in any way out of use or reliance upon this specification or any

information herein.

Any marks and brands contained herein are the property of their respective owners.

Data Sheet

Revision1.2

2018-09-21

OPTIGA™ TPM SLB 9665 TPM2.0

Trusted Platform Module

Revision History

Page or Item

Subjects (major changes since previous revision)

Revision 1.2, 2018-09-21

Updated document template.

Revision 1.1, 2013-09-13

New template. Changed lifetime in Table 8. Fixed pinning for PG-VQFN-32-13 package,

affected pins are GPIO and PP. Added Section 4.4 and enhanced Section 4.5.

Revision 1.0, 2013-07-19

Initial version.

Data Sheet

Revision1.2

2018-09-21

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2018-09-21

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Except as otherwise explicitly approved by Infineon

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Email:

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security.chipcard.ics@infineon.com

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