SLE66CL80M-C [INFINEON]
Micro Peripheral IC, CMOS;
| 型号： | SLE66CL80M-C |
| 厂家： | 
Infineon |
| 描述： | Micro Peripheral IC, CMOS |
| 文件： | 总13页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Chip Card & Security
SLE 66CL80PE(M) Family
8/16-Bit High Security Dual Interface Controller
For Contact based and Contactless Applications
ISO/IEC 7816 and 14443 Type B & A Compliant Interfaces
Contactless interface acc. ISO/IEC 18092 passive mode
(SONY FeliCa® communication interface)
with Linear Addressing Instruction Set For Large Memories
in 0.22 µm CMOS Technology
92-Kbyte User ROM, 2304-byte RAM,
8-Kbyte EEPROM
112-Bit Dual Key DES Accelerator
supporting DES, 3DES Algorithms
Mifare™ is a registered trademark of NXP Semiconductors
Short Product Information
12.2009
Preliminary SLE 66CL80PE(M) Family Short Product Information
Ref.: SPI_SLE66CL80PE_091106.doc
This document contains preliminary information on a new product under development.
Details are subject to change without notice.
Revision History: Current Version: 2009-12-16
Previous Releases:
Page
Subjects (changes since last revision)
Important: Further information is confidential and on request. Please contact:
Infineon Technologies AG in Munich, Germany,
Chip Card & Security
Email: security.chipcard.ics@infineon.com
www.infineon.com/security
Published by Infineon Technologies AG,
81726 Munich, Germany
© Infineon Technologies AG 2009
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits,
descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon
Technologies Office in Germany or our Infineon Technologies Representatives world-wide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of
that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or
systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect
human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
SLE66CL80PE(M)
8/16-Bit High Security Dual Interface Controller in 0.22 µm CMOS Technology
for Contact and Contactless Operation
with ISO/IEC 7816 and 14443 Type B & A Compliant Interfaces
Contactless interface acc. ISO/IEC 18092 passive mode
(SONY FeliCa® communication interface)
with MMU and Linear Addressing Instruction Set For Large Memories
and optional MIFARETM compatible emulation
92-Kbyte User ROM, 2304-byte RAM, 8-Kbyte EEPROM
112-Bit Dual Key DES Accelerator supporting DES, 3DES algorithm
· Certified True Random Number Generator
General Features
with firmware test function supporting AIS-31
requirements
· Enhanced low power non-standard
architecture 8051 CPU with extended
addressing modes for dual interface smart
card and contactless applications
· Dual Key Triple DES (DDES) Accelerator
· CC EAL5+ Certification planned according to
BSI–PP-0002
· Instruction set opcode compatible with
standard 8051 processor with additional
powerful instructions optimized for smart card
application
· CRC Module according to ISO/IEC 3309
supporting CCIT V.41 & HDLC X25 with
configurable initial values
· 16 Interrupt Vectors Module with 3 priority
· Execution time at least 6 times faster than
standard 8051 processor at same external
clock
levels to ensure real time operation
· Internal clock controlled by PLL: up to 30MHz
asynchronous clock frequency (optional use)
· Additional enhanced instructions for direct
physical memory access of >64-Kbyte
· Adjustable internal frequency according to
available power or required performance
· Typically saves up to 90 % code space and
increases execution speed up to 80%
· Increased internal frequency for maximum
performance
· 92-Kbyte User ROM for operating system and
application (programs & data)
· Internal frequency adjusted to guarantee a
given limited power consumption
· 256 bytes reserved ROM for Resource
Management System (RMS) with
Contactless optimized EEPROM
write/erase routines
· Two 16-bit Auto-reload Timers with interrupt
capability for protocols, security checks &
watch dog implementations
· 8-Kbyte Secure EEPROM in MicroSlim
· Power saving sleep and clock stop modes
technology for application program and data
· Temperature range:
· MIFARETM compatible emulation
· 4-Kbyte reserved in User ROM
contact-based: -25°C to +85°C
contact-less:
-25°C to +70°C
· 2-Kbyte additional EEPROM protected by
RMS Firewall
· 2048-byte XRAM and 256-byte internal RAM
for fast data processing
· Enhanced Memory Management Unit with
application and user defined segment
MIFA RETM is a trademark of NXP B.V.
· EEPROM voltage generated on chip
4 / 13
12.2009
SLE66CL80PE(M)
MIFARETM compatible Interface
Full operation either via Contact-based
and/or Contactless interfaces controlled
by Operating System enhances Security
Level
· Optionally 1-Kbyte emulation
· Operation controlled by RMS functions: same
functionality and command set as given by the
MIFARETM technology
· Support of multiple MIFARETM compliant
Contact-based Interface
interfaces on one controller
· Contact configuration and serial interface
according to ISO/IEC 7816
· Unique Identification number
· UART handling serial interface compliant with
ISO/IEC 7816 supporting transmission
· Personalisation also possible in Contact
based mode secured by RMS functions
protocols T=0/1 and up to Division Factor 8
· Supply voltage range:
5V ± 10% (Class A)
E²PROM Technology
· Byte wise EEPROM programming and read
3V ± 10% (Class B)
1.8V ± 10% (Class C) (on request)
accesses
· Flexible page mode for 1 to 64 bytes
· Current consumption < 10 mA @ 5.5 V
write/erase operation
· External CPU clock frequency:
· 32 bytes security area including:
- 16 bytes chip unique identification number
- 16 bytes PROM area (OTP like)
1 to 7.5 MHz
· Internal CPU clock frequency:
up to 30 MHz
· Fast personalisation mode =1.0 ms
· Typical Page Programming time of 2.2ms
· ESD protection larger than 6 kV
· Enhanced ECC Module controlled by
Contactless Interface
Operating System
· Platform prepared for flash-like erasing of up
· Interface according to ISO/IEC 14443 for both
to 2-Kbyte EEPROM-segments
Type B and Type A
· Minimum of 500.000 Write/erase cycles
@25°C per page
· Interface according to ISO/IEC 18092 passive
mode Interface (SONY FeliCa®)
· Data retention for a minimum of 25 years
· Carrier frequency 13.56 MHz
@25°C
· Data rate in both directions
· EEPROM programming voltage generated on
up to 848 Kbit/s in type B operation
up to 848 Kbit/s in type A operation
up to 424Kbit/s in FeliCa® operation
chip
Memory Management and
Protection Unit
· Anticollision & Transmission Protocol
supported by open source application notes
for both Type B & A
· Addressable memory up to 16 Mbytes
· supported by RMS functions
· Separates OS (system mode) and Application
· Flexible Internal CPU clock frequency:
(application mode) by usage of descriptors
fully configurable from 1.7MHz up to 30 MHz
· Enhanced multi-application support by 16
· 256 bytes buffer for contactless data
descriptors
exchange (FiFo circular architecture)
· System routines called by interrupts
· Parallel operation of CPU, Peripherals like
DES, CRC and Contactless Interface for high
demanding applications.
· Access Restrictions to peripherals in
application mode controlled by OS
· Code execution from XRAM possible
5 / 13
12.2009
SLE66CL80PE(M)
·
·
Secure start of the operating system ensured
by certified Self Test Software (STS)
Security Features
Certified EEPROM programming routines
(RMS)
·
·
Enhanced Error Correction Unit (ECU)
Operation state mechanism
Certified True Random Number Generator
including firmware test function supporting
AIS-31 requirements.
· Low and high voltage sensors
· Internal voltage sensor
· Frequency sensors and filters
· Light sensor
·
High Speed SPA/DPA resistant Dual Key
DES (DDES) Accelerator
· Glitch sensors
· Temperature sensor
· Life Test function for sensors
· Internal power-on reset sensor
Anti Snooping
· Automatic randomization and smoothing of
power profile
· Non standard dedicated Smart Card
CPU Core
· Active Shield with automatic and user
· HW-countermeasures against SEMA/DEMA,
controlled attack detection
SPA/DPA, DFA and Timing Attacks
· Active Shield with automatic and user
Secure chip and firmware
design
controlled attack detection
·
·
Sparkling SFR encryption for DDES, ACE,
RNG and CRC modules
Targeted Evaluation
· CC EAL5+
· Visa Level 3
· CAST
Security scrambled, dual rail pre-charge logic
design & optimized chip layout against
physical chip manipulation
·
·
Bus Confusion
· EMVCo
Immediate internal RAM erase upon security
reset detection
Supported Standards
·
·
·
Security Reset
· ISO/IEC 7816
· EMV 2000
ROM code not visible due to implantation
Mask dependant ROM code encrypted during
production
· MasterCard PayPass® M/Stripe and M/Chip
· Visa Wave® and MSD
· GSM 11.1x
· ETSI TS 102 221
· ISO/IEC 14443
·
·
·
Chip unique encryption of the XRAM and
EEPROM
Flexible encryption of part or whole EEPROM
by additional user-defined key
Memory encryption/decryption module (MED)
for XRAM, ROM and EEPROM against
reverse engineering and power attacks
· ISO/IEC 18092 (passive mode)
· ISO/IEC 3309
· CCIT v.41
· HDLC X25
·
·
16 byte Unique Chip IDentification number
for anti-clone countermeasure & secure
tracking
16 bytes security PROM hardware protected
(OTP like)
6 / 13
12.2009
SLE66CL80PE(M)
Document References
Application Support
· HW-& SW-Tools (Emulator, ROM Monitor,
· Confidential Data Book
Simulator, Evaluation Kit Proximity
SLE 66CL(X)xxxPE(M)
(Contactless Reader package), SmartMask™
package, Simulated Reader Software, etc.)
· Confidential Instruction Set SLE 66CxxxPE(M)
· Confidential Quick Reference
· Open Source Application Notes Tutorial (e.g.:
T=0, T=1, DES and 3DES, Crypto Library,
Anticollision and Contactless Transmission
Protocols for both Type B and A, Card Coil
Design Guide, Card Coil Antenna Reference
Design List, etc.)
SLE 66CxxxPE(M)
· Chip Qualification report
· Chip delivery specification for wafer with chip-
layout (die size, orientation, ...)
· Module specification containing description of
· Certified CC EAL5+ Crypto Library
package, etc.
· Worldwide Application Engineer Team and
customer dedicated Field Application
Engineers
· Module Qualification report
· Dedicated Team for Contactless Design-in
Development Tools Overview
support and Analysis
· Straight forward migration of existing tool
chain for 66P towards 66PE family by
firmware update
· Regular Customer trainings on Cryptography,
Contactless and Dual interface controllers
including ISO/IEC 14443 related topics
· Software Development Kit SDK CC
· On-site trainings available on request
· ROM Monitor RM66P/PE-II with stand alone
functionality for ROM mask qualification in the
end user system
· Emulator ET66P/PE Hitex or ET66P/PE KSC
· Smart Mask™ Package for chip evaluation
· Smart Mask™ Dual Interface modules M8.4
(supplied by Infineon) supporting both
ISO/IEC 14443 Type B & A and ISO/IEC 7816
for implantation process testing and
production setup
· Evaluation Kit Proximity (Contactless reader
package)
· Reader Optimization Kit
7 / 13
12.2009
SLE66CL80PE(M)
Cryptographic Timing Performances
Timing performances are independent of the contact or contactless interface.
Operation
Data Block
Length
Encryption Time for an
8-byte Block including Data Transfer
5 MHz
15 MHz
30MHz
High Speed and Secure
56-bit Single DES Encryption
(incl. key loading)
64 bit
37 µs
12 µs
6 µs
High Speed and Secure
56-bit Single DES Encryption
64 bit
64 bit
23 µs
60 µs
8 µs
4 µs
High Speed and Secure
112-bit Triple DES Encryption
(incl. key loading)
20 µs
10 µs
High Speed and Secure
64 bit
35 µs
12 µs
6 µs
112-bit Triple DES Encryption
Table 1
Performance DDES Accelerator1
Ordering Information
Type
Package Voltage Temperature Frequency
Frequency
Range
Range2
Range
Range
(external
clock CB)
(internal
clock)
MCC83
M8.44
Chip
1.62 V
to
– 25°C
1 MHz
to
SLE 66CL80PE(M) – MCC8
SLE 66CL80PE(M) – M8.4
SLE 66CL80PE(M) – C
Up to 30MHz
to
5.5 V
+ 85°C
7.5 MHz
Table 2
Package Product Information5
1 Preliminary values based on internal test results
2 External Contactless clock range according to ISO/IEC14443
3 Pure Contactless Module (MCC8): for standard thickness inlays (330µm)
4 Dual Interface Module (M8.4)
5 Ordering Codes are available on request
8 / 13
12.2009
SLE66CL80PE(M)
Pin Description and Pad Configuration
C1
C2
C3
C4
C5
C6
C7
C8
Figure 1
M8.4 Pin Configuration Wire-bonded Module (top view)
LA
LB
CLK
RST
I/O
VDD
SLE 66CL80PE(M)
GND
Figure 2
Pad Configuration (die)
Card Contact
Symbol
VDD
RST
CLK
GND
I/O
Function
C1
C2
C3
C5
C7
Supply voltage
Reset input
Processor clock input
Ground
Bi-directional data port
Coil connection pin LA
Coil connection pin LB
LA
LB
Table 3
Pin Definitions and Functions
9 / 13
12.2009
SLE66CL80PE(M)
Block Diagram Description
Active Shield
Non Volatile Memory (NVM)
VCC
IFX
used
NVM
USER
EEPROM
Timers
(0, 1)
16 Byte ROM
16 Byte PROM
UART
RNG
CRC
I/O
ECO 2000
CPU
MED
MMU
Sleep Mode
CLK
Logic
Address-/Databus
RST
Security
Sensors
256 Bytes
IRAM
GND
ROM
Inter-
rupt
DES
ACE
XRAM
6 kByte
IF-RMS
Ext. Voltage
Int. Voltage
Sensor
HF/LF
Sensors
F-Curse
Sensor
USER
ROM
STS
SH-RMS
Light
Sensor
Temp
Sensor
Glitch
Sensor
UmSLC
LA
On-Chip Firmware
STS, RMS
Voltage
Regulator
Clock Unit
VCO
CODEC
FIFO
256 byte
Crypto
RFI
ISO14443 A,B
SONY FeliCa
LB
(Dual -Supply CB/CL)
Figure 3
Block Diagram of SLE 66CL80PE(M)
10 / 13
12.2009
SLE66CL80PE(M)
General Description
The dual interface security controllers SLE 66CL80PE(M) belong to the family of the Infineon
Technologies SLE 66CxxxPE high-end security controller family in 0.22 µm CMOS technology which
are designed for contactless security systems that requires continuous ongoing improvements with
the highest degree of protection against fraudulent attacks.
SLE 66CL80PE(M) is targeting dual interface and pure contactless smart card applications such as ID
cards, banking, security access and transport.
SLE 66CL80PE(M) offers 92 Kbytes of User-ROM, 256 bytes internal RAM, 2 Kbytes XRAM and
8 Kbytes EEPROM, which can be used as data and as program memory. The non-volatile memory
consists of high reliability cells to guarantee data integrity. This is especially important when the
EEPROM is used as program memory.
It features ISO/IEC 14443 Type B contactless interfaces and Type A and ISO/IEC 7816 contact-
based interface on a single chip. They also support symmetric algorithms, such like DES and 3DES,
independently of the communication mode.
The CPU provides the high efficiency of the 8051 instruction set extended by additional powerful
instructions with enhanced performance, memory sizes and security features tailored for contact and
contactless smart card applications. Using the embedded PLL, the internal clock is adjustable up to
30 MHz independent from the carrier frequency of the magnetic field supplied by the contactless
terminal.
The Memory Management Unit allows a secure separation of the operating system and the
applications. Using the system/application mode, it allows to securely downloading applications in the
field after card personalisation. Using the MMU transparent mode allows keeping the memory mapping
for code compatibility to previous 66P Infineon security controller family member. These new features
suit the requirements of the new generation of operating systems.
The UART supports the half-duplex transmission protocols T=0 and T=1 according to ISO/IEC 7816-3.
All relevant transmission parameters can be adjusted by software, as e.g. the clock division factor,
direct/inverse convention and the number of stop bits. To minimize the overall power consumption, the
smart card controller can be set into sleep mode supporting clock stop mode.
Timers ease the implementation of advanced communication protocols such as T=CL (according to
ISO/IEC 14443-4) and all other time critical processes for contactless communications. Both Timers
features auto-reload mechanisms as well as their own dedicated interrupt vectors. Additional interrupts
capability of the RF interface module allows real time operation of the pure contactless smart card with
the contactless terminals.
SLE 66CL80PE(M) is able to communicate with any Proximity Card Device (PCD) defined in
ISO/IEC 14443 such as the Infineon Evaluation Kit Proximity. The power supply and data are received
by an antenna, which consists of a coil with a few turns directly connected to the IC. DES acceleration
by a factor of more than 500 compared to software solutions in combination with the high data transfer
rate up to 848 Kbit/s keep the transaction times short. For more independence and flexibility, the
controller offers the two modulation type B and type A according ISO/IEC 14443.
The Anticollision and Contactless Transmission Protocol are supported by open source
application notes for both Type B and A in order to offer a maximum flexibility to the Operating
System. Both Contactless Communication protocol may be implemented in the Operating
System while the final selection of the Type B or A is based upon the personalisation data of the
contactless smart card. The communication type can also be changed during runtime in the field.
Thus, SLE 66CL80PE(M) ensures a simplified handling of the ROM mask, high reactivity by a
tailored personalisation during production of the contactless smart card in order to answer to the
increasing market demand and applications.
11 / 13
12.2009
SLE66CL80PE(M)
SLE 66CL80PE(M) features a new Resource Management System (RMS_E) which optimizes
Contactless EEPROM write/erase routines. EEPROM programming is enhanced over the entire
communication distance compared to the standard RMS. Thus, the reduction of programming times
and power consumption is ensured independently of the use of the contact or the contactless interface.
The CRC module allows the easy generation of checksums according to ISO/IEC 3309 (16-Bit-CRC),
thus it supports the two different CRC calculation required for ISO/IEC 14443 Type B and Type A.
It additionally features an configurable initial value to avoid checksum computation re-starting
from zero in the case interrupts requiring use of the CRC module are triggered. Therefore, data as well
as program located in the EEPROM can be extra-secured by a CRC checksum enabling the Operating
System to detect errors while downloading new application in the field.
To minimize the overall power consumption, the pure contactless smart card controller can be set into
sleep mode.
The certified random number generator (RNG) is able to supply the CPU with true random numbers on
all conditions. It allows creating session key used for authentication in open networks and enable
secure downloading of new applications.
The DDES module supports symmetrical crypto algorithms according to the Data Encryption Standard
in the Electronic Code Book Mode. It features two internal registers for storage of the two keys required
for a Triple DES computation. Together with the fast contactless interface, it offers high security and
high speed for dual interface smart card applications.
As an important feature, SLE 66CL80PE(M) provides a new and enhanced level of on-chip
security, which fulfils the strong security requirements of a Common Criteria evaluation at an
EAL5+ High level. Each security measure is designed to act as an integral part of the complete system
in order to strengthen the system as a whole.
Thus, porting an existing Operating System to SLE 66CL80PE(M) requires only very limited
changes as it is typically reduced to add the Contactless Library and the Contactless Optimized
Resource Management System (RMS_E) to the existing Operating System.
SLE 66CL80PE(M) integrates outstanding memory sizes, additional peripherals in combination with
enhanced performance and optimized power consumption on a minimized die size.
In conclusion, SLE 66CL80PE(M) fulfils the requirements of for both contact-based and contactless
smart card applications such like ID cards, banking, security access and transport. The family concept
offers to select the right product for a given application in terms of available memory and price.
12 / 13
12.2009
SLE66CL80PE(M)
Glossary
AES
Advanced Encryption Standard
AIS-31
Functionality classes and evaluation methodology guidelines for physical random number
generators defined by the German Institute for the Security of the Information Technology.
Cache memories are Random Access Memories that the CPU can access more quickly than it
can access regular RAM.
Caches
CLK
Clock
CPU
CMOS
Central Processing Unit
Complementary Metal-Oxide Semiconductor, the technology used to manufacture most of
today's microchips.
CRT
DES, 3DES
DSA
Chinese Remainder Theorem, computing technique
Data Encryption Standard
Digital Signature Algorithm
EAL 5+
EC
Common Criteria Certification level
Elliptic Curves
EEPROM
ESD
Electrically Erasable Programmable Read-Only Memory
Electrostatic Discharge, release of static electricity that can damage a chip
Component of RSA key
Exponent
F_4
Fermat Number F4 , computing term.
GF(2m)
GF(p)
Galois Field: finite field of 2m elements represented by polynomials with degree < m
Galois Field, set of whole numbers less than prime number p
Input/Output
I/O
Modulus
RAM
Component of RSA key
Random Access Memory
RISC
Reduced Instruction Set Computer
RNG, TRNG
ROM
Random Number Generator, True Random Number Generator
Read-Only Memory
RSA
SHA-1
STS
Rivest, Shamir and Adleman, inventors of the RSA cryptosystem
Secure Hash Algorithm revision 1
Self Test Software
T=0, T=1
UART
Communication Protocols defined in ISO 7816 standard
Universal Asynchronous Receiver/Transmitter
Sales code name
SLE: IFX name
S: Solitary Digital Circuits
L: Free selectable
CL: Contactless
controller
Ordinal number:
e.g.: 0, 1
E: Temperature range
(-25°C up to +85°C)
SLE 66 CL
8 0 PE(M)
Chip Family
EEPROM size
Product Family
66: 8/16-bit
e.g.:
8: 8KB
PE: Plus Enhanced
M:MIFARETM
compatible interface
Optimized for high-end
applications
13 / 13
12.2009
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