SP0002-19052 [INFINEON]

OptiMOS㈢ Power-Transistor; OptiMOS㈢功率三极管
SP0002-19052
型号: SP0002-19052
厂家: Infineon    Infineon
描述:

OptiMOS㈢ Power-Transistor
OptiMOS㈢功率三极管

文件: 总8页 (文件大小:155K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IPB100N08S2L-07  
IPP100N08S2L-07  
OptiMOS® Power-Transistor  
Product Summary  
Features  
VDS  
75  
6.5  
100  
V
• N-channel Logic Level - Enhancement mode  
R
DS(on),max (SMD version)  
m  
A
• Automotive AEC Q101 qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
Green package (lead free)  
• Ultra low Rds(on)  
I D  
PG-TO263-3-2  
PG-TO220-3-1  
• 100% Avalanche tested  
Type  
Package  
Ordering Code Marking  
IPB100N08S2L-07  
IPP100N08S2L-07  
PG-TO263-3-2  
PG-TO220-3-1  
SP0002-19053  
SP0002-19052  
PN08L07  
PN08L07  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
Continuous drain current1)  
I D  
T C=25 °C, VGS=10 V  
T C=100 °C,  
100  
98  
A
V
GS=10 V2)  
Pulsed drain current2)  
Avalanche energy, single pulse2)  
Gate source voltage4)  
I D,pulse  
EAS  
T C=25 °C  
I D=80A  
400  
810  
mJ  
V
VGS  
±20  
Ptot  
T C=25 °C  
Power dissipation  
300  
W
°C  
T j, T stg  
Operating and storage temperature  
-55 ... +175  
Rev. 1.0  
page 1  
2006-03-03  
IPB100N08S2L-07  
IPP100N08S2L-07  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
R thJA  
Thermal resistance, junction - case  
-
-
-
-
0.5  
62  
K/W  
Thermal resistance, junction -  
ambient, leaded  
SMD version, device on PCB  
minimal footprint  
-
-
-
-
62  
40  
6 cm2 cooling area5)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS  
VGS(th)  
V
V
GS=0 V, I D= 1 mA  
Drain-source breakdown voltage  
Gate threshold voltage  
75  
-
-
V
DS=VGS, I D=250 µA  
1.2  
1.6  
2.0  
V
DS=75 V, VGS=0 V,  
I DSS  
Zero gate voltage drain current  
-
0.01  
1
µA  
T j=25 °C  
V
DS=75 V, VGS=0 V,  
-
-
-
1
1
100  
T j=125 °C2)  
I GSS  
V
V
GS=20 V, VDS=0 V  
GS=4.5 V, I D=80 A,  
Gate-source leakage current  
100 nA  
R DS(on)  
Drain-source on-state resistance  
6.5  
8.7  
mΩ  
SMD version  
V
GS=4.5 V, I D=80 A,  
-
-
-
6.2  
5.0  
4.7  
8.4  
6.8  
6.5  
SMD version  
RDS(on)  
V
V
GS=10 V, I D=80 A,  
GS=10 V, I D=80 A,  
Drain-source on-state resistance  
m  
SMD version  
Rev. 1.0  
page 2  
2006-03-03  
IPB100N08S2L-07  
IPP100N08S2L-07  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
5400  
1300  
590  
19  
-
-
-
-
-
-
-
pF  
ns  
V
GS=0 V, VDS=25 V,  
f =1 MHz  
56  
V
DD=40 V, VGS=10 V,  
I D=100 A, R G=1.1 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
85  
22  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
18  
70  
25  
124  
246  
-
nC  
Q gd  
V
V
DD=60 V, I D=100 A,  
GS=0 to 10 V  
Q g  
182  
3.5  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
100  
400  
T C=25 °C  
I S,pulse  
V
GS=0 V, I F=80 A,  
VSD  
Diode forward voltage  
Reverse recovery time2)  
Reverse recovery charge2)  
-
-
-
0.9  
95  
1.3  
V
T j=25 °C  
VR=40 V, I F=I S,  
diF/dt =100 A/µs  
t rr  
120 ns  
300 nC  
VR=40 V, I F=I S,  
diF/dt =100 A/µs  
Q rr  
240  
1) Current is limited by bondwire; with an R thJC = 0.5K/W the chip is able to carry 138A at 25°C. For detailed  
information see Application Note ANPS071E at www.infineon.com/optimos  
2) Defined by design. Not subject to production test.  
3) See diagram 13  
4) Qualified at -20V and +20V.  
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 3  
2006-03-03  
IPB100N08S2L-07  
IPP100N08S2L-07  
1 Power dissipation  
2 Drain current  
P
tot = f(T C); VGS 4 V  
I D = f(T C); VGS 10 V  
350  
300  
250  
200  
150  
100  
50  
120  
100  
80  
60  
40  
20  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
Z
parameter: D =t p/T  
100  
1000  
100  
10  
0.5  
1 µs  
10 µs  
100 µs  
10-1  
0.1  
1 ms  
0.05  
10-2  
0.01  
single pulse  
10-3  
1
10-7  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
t p [s]  
V
DS [V]  
Rev. 1.0  
page 4  
2006-03-03  
IPB100N08S2L-07  
IPP100N08S2L-07  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
DS(on) = (I D); T j = 25 °C  
R
parameter: VGS  
300  
20  
18  
16  
10 V  
3.5 V  
250  
200  
150  
100  
50  
3 V  
14  
12  
10  
8
4 V  
4 V  
4.5 V  
3.5 V  
6
10 V  
4
3 V  
2
2.5 V  
0
0
0
2
4
6
8
10  
0
20  
40  
60  
80  
100  
120  
I
D [A]  
V
DS [V]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. Forward transconductance  
g fs = f(I D); T j = 25°C  
parameter: g fs  
200  
180  
160  
140  
120  
100  
80  
250  
200  
150  
100  
50  
60  
40  
175 °C  
20  
25 °C  
-55 °C  
0
0
1
2
3
4
0
50  
100  
150  
200  
I
D [A]  
V
GS [V]  
Rev. 1.0  
page 5  
2006-03-03  
IPB100N08S2L-07  
IPP100N08S2L-07  
9 Typ. Drain-source on-state resistance  
DS(ON) = f(T j)  
10 Typ. gate threshold voltage  
GS(th) = f(T j); VGS = VDS  
R
V
parameter: I D = 80 A; VGS = 10 V  
parameter: I D  
12  
2.5  
10  
8
2
1.5  
1
1250µA  
250µA  
6
4
0.5  
2
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
T j [°C]  
11 Typ. capacitances  
12 Typical forward diode characteristicis  
C = f(VDS); VGS = 0 V; f = 1 MHz  
IF = f(VSD)  
parameter: T j  
104  
103  
Ciss  
102  
Coss  
103  
25 °C  
175 °C  
Crss  
101  
102  
100  
0
5
10  
15  
20  
25  
30  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
V
DS [V]  
V
SD [V]  
Rev. 1.0  
page 6  
2006-03-03  
IPB100N08S2L-07  
IPP100N08S2L-07  
13 Typical avalanche energy  
AS = f(T j)  
14 Typ. gate charge  
GS = f(Q gate); I D = 100 A pulsed  
E
V
parameter: I D=80A  
parameter: VDD  
900  
12  
15V  
60V  
800  
700  
600  
500  
400  
300  
200  
100  
10  
8
6
4
2
0
0
0
40  
80  
Q
120  
gate [nC]  
160  
200  
25  
75  
125  
175  
T j [°C]  
15 Typ. drain-source breakdown voltage  
16 Gate charge waveforms  
V
BR(DSS) = f(T j); I D = 1 mA  
86  
VGS  
Qg  
81  
76  
71  
66  
Qgate  
Qgd  
Qgs  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
Rev. 1.0  
page 7  
2006-03-03  
IPB100N08S2L-07  
IPP100N08S2L-07  
Published by  
Infineon Technologies AG  
St.-Martin-Straße 53  
D-81541 München  
© Infineon Technologies AG 2004  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as  
a guarantee of characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,  
regarding circuits, descriptions and charts stated herein.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact your  
nearest Infineon Technologies Office (www.infineon.com)  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact your nearest Infineon Technologies Office.  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,  
it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 8  
2006-03-03  

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