SPD50P03L G [INFINEON]
Infineon’s highly innovative OptiMOS™ families include p-channel power MOSFETs. These products consistently meet the highest quality and performance demands in key specifications for power system design such as on-state resistance and figure of merit characteristics.;
| 型号： | SPD50P03L G |
| 厂家： | 
Infineon |
| 描述： | Infineon’s highly innovative OptiMOS™ families include p-channel power MOSFETs. These products consistently meet the highest quality and performance demands in key specifications for power system design such as on-state resistance and figure of merit characteristics. |
| 文件： | 总9页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPD50P03L G
OptiMOS®-P Power-Transistor
Product Summary
Features
V DS
-30
7
V
• P-Channel
R DS(on),max
I D
mΩ
A
• Enhancement mode
-50
• Logic level
• 175°C operating temperature
• Avalanche rated
PG-TO252-5
• dv /dt rated
• High current rating
• Pb-free lead-plating, RoHS compliant
Package
Marking
Tape and reel information
Lead Free
Yes
Packing
Non dry
Type
SPD50P03L G
PG-TO252-5
50P03L
1000 pcs / reel
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol Conditions
Unit
T C=25 °C1)
I D
-50
-50
Continuous drain current
A
T C=100 °C1)
I D,pulse
E AS
T C=25 °C
-200
256
Pulsed drain current
I D=-50 A, R GS=25 Ω
Avalanche energy, single pulse
mJ
I D=-50 A, V DS=24 V,
di /dt =-200 A/µs,
-6
Reverse diode dv /dt
dv /dt
kV/µs
T
j,max=175 °C
V GS
±20
150
Gate source voltage
V
P tot
T C=25 °C
Power dissipation
W
°C
Operating and storage temperature
T j, T stg
-55…+175
1C
ESD class HBM
Soldering temperature
260
55/175/56
IEC climatic category; DIN IEC 68-1
Rev. 1.9
page 1
2012-09-13
SPD50P03L G
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Thermal characteristics
R thJC
Thermal resistance, junction - case
-
-
-
-
-
-
1
K/W
R thJA
minimal footprint
75
50
Thermal resistance,
junction - ambient
6 cm2 cooling area2)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS
V GS(th)
V
V
GS=0 V, I D=-250 µA
DS=V GS
Drain-source breakdown voltage
Gate threshold voltage
-30
-1
-
-
V
,
-1.5
-2
I D=-250 µA
V
DS=-30 V, V GS=0 V,
I DSS
Zero gate voltage drain current
-
-0.1
-1
µA
T j=25 °C
V
DS=-30 V, V GS=0 V,
-
-
-
-10
-10
8.5
-100
T j=175 °C
I GSS
V
V
GS=-20 V, V DS=0 V
Gate-source leakage current
-100 nA
GS=-4.5 V,
R DS(on)
Drain-source on-state resistance
12.5 mΩ
I D=-30 A
R DS(on)
V GS=-10 V, I D=-50 A
Drain-source on-state resistance
Transconductance
-
5.7
94
7.0
|V DS|>2|I D|R DS(on)max
I D=-50 A
,
g fs
47
-
S
1) Current is limited by bondwire; with anR thJC=1 K/W the chip is able to carry 123 A.
2
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.9
page 2
2012-09-13
SPD50P03L G
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Dynamic characteristics
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C iss
-
-
-
-
-
-
-
4590
1220
1000
14.8
21.7
139
6880 pF
1830
V
V
GS=0 V,
C oss
C rss
t d(on)
t r
DS=-25 V, f =1 MHz
1500
22
32
ns
V
V
DD=-15 V,
GS=-10 V, I D=-1 A,
t d(off)
t f
Turn-off delay time
Fall time
208
156
R G=6 Ω
104
Gate Charge Characteristics3)
Gate to source charge
Gate to drain charge
Q gs
Q gd
-
-
-14
-35
-19
-53
nC
V
DD=-24 V, I D=-50 A
VDD=-24 V, ID=-50 A,
GS=0 to -10 V
Q g
Gate charge total
-
-
-95
-126
-
V
V plateau VDD=-24 V, ID=-50 A
Gate plateau voltage
-3.0
V
A
Reverse Diode
I S
Diode continous forward current
Diode pulse current
-
-
-
-
-50
T C=25 °C
I S,pulse
-200
V
GS=0 V, I F=50 A,
V SD
Diode forward voltage
Reverse recovery time
Reverse recovery charge
-
-
-
-1
38
46
-1.65
47
V
T j=25 °C
V R=-15 V, I F=|I S|,
di F/dt =100 A/µs
t rr
ns
nC
Q rr
57
3) See figure 16 for gate charge parameter definition
Rev. 1.9
page 3
2012-09-13
SPD50P03L G
1 Power dissipation
2 Drain current
P
tot=f(T C)
I D=f(T C); |V GS|≥10 V
160
140
120
100
80
55
50
45
40
35
30
25
20
15
10
5
60
40
20
0
0
0
40
80
120
C [°C]
160
200
0
40
80
120
160
200
T
T C [°C]
3 Safe operating area
4 Max. transient thermal impedance
thJC=f(t p)
I D=f(V DS); T C=25 °C; D =0
parameter: t p
Z
parameter: D =t p/T
103
101
limited by on-state
resistance
1 µs
10 µs
102
100
10-1
10-2
10 ms
100 µs
DC
1 ms
0.5
101
0.2
0.1
0.05
0.02
0.01
single pulse
100
10-1
100
101
102
10-5
10-4
10-3
10-2
10-1
-V DS [V]
t
p [s]
Rev. 1.9
page 4
2012-09-13
SPD50P03L G
5 Typ. output characteristics
I D=f(V DS); T j=25 °C
6 Typ. drain-source on resistance
DS(on)=f(I D); T j=25 °C
R
parameter: V GS
parameter: V GS
15
200
-5 V
-10 V
180
160
140
120
100
80
-4.5 V
-4 V
10
-4.5 V
-5.5 V
-3.5 V
5
V 6-
-6.5 V
-7 V
60
-3 V
40
-10 V
-2.5 V
20
0
0
0
40
80
120
-ID [A]
160
200
0
2
4
6
8
10
-V DS [V]
7 Typ. transfer characteristics
I D=f(V GS); |V DS|>2|I D|R DS(on)max
parameter: T j
8 Typ. forward transconductance
g fs=f(I D); T j=25 °C
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
C °25
C °175
0
1
2
3
4
0
20
40
60
-ID [A]
-V GS [V]
Rev. 1.9
page 5
2012-09-13
SPD50P03L G
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
R
DS(on)=f(T j); I D=-50 A; V GS=-10 V
V
GS(th)=f(T j); V GS=V DS; I D=-250 µA
2.5
11
98%.
2
9
98 %
1.5
typ.
7
typ.
1
2%
5
3
0.5
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
T j [°C]
T j [°C]
11 Typ. capacitances
12 Forward characteristics of reverse diode
I F=f(V SD
C =f(V DS); V GS=0 V; f =1 MHz
)
parameter: T j
104
10000
1000
Ciss
100
10
Coss
Crss
103
1000
25 °C, typ
175 °C, typ
25 °C, 98%
175 °C, 98%
102
100
1
0
0
5
10
15
20
25
0.5
1
1.5
2
2.5
-V SD [V]
-V DS [V]
Rev. 1.9
page 6
2012-09-13
SPD50P03L G
13 Avalanche characteristics
AS=f(t AV); R GS=25 Ω
14 Typ. gate charge
GS=f(Q gate); I D=-50 A pulsed
V
I
parameter: T j(start)
parameter: V DD
100
12
V 24-
V 15-
V 6-
C °25
10
8
C °100
C °150
10
6
4
2
1
1
0
10
100
1000
0
20
40
60
-Q gate [nC]
80
100
120
t
AV [µs]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V
BR(DSS)=f(T j); I D=-250 µA
36
35
34
33
32
31
30
29
28
27
V GS
Q g
V gs(th)
Q g(th)
Q sw
Q gd
Q gate
Q gs
-60
-20
20
60
100
140
180
T j [°C]
Rev. 1.9
page 7
2012-09-13
SPD50P03L G
Package Outline
PG-TO252-5: Outline
Footprint
Packaging
Tape
Dimensions in mm
Rev. 1.9
page 8
2012-09-13
SSPPDD5500PP0033LLG
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies
hereby disclaims any and all warranties and liabilities of any kind, including without limitation,
warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information
on the types in question, please contact the nearest Infineon Technologies Office. Infineon
Technologies components may be used in life-support devices or systems only with the express
written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be
implanted in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be
endangered.
Rev. 1.9
page 9
2012-09-13
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