TC1197 [INFINEON]
32-Bit Single-Chip Microcontroller; 32位单芯片微控制器
| 型号： | TC1197 |
| 厂家： | 
Infineon |
| 描述： | 32-Bit Single-Chip Microcontroller |
| 文件： | 总183页 (文件大小：1977K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Bit
TC1197
32-Bit Single-Chip Microcontroller
Data Sheet
V1.1 2009-05
Microcontrollers
Edition 2009-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
32-Bit
TC1197
32-Bit Single-Chip Microcontroller
Data Sheet
V1.1 2009-05
Microcontrollers
TC1197
TC1197 Data Sheet
Revision History: V1.1, 2009-05
Previous Version: V1.0, 2009-01
Page
Subjects (major changes since last revision)
Typo of TTCAN-related text is deleted from the MultiCAN features.
Page 1-4
Page 1-6
Description is added for the derivatives of TC1797.
Page 2-26
Page 2-53
Page 5-129
Page 5-133
Page 5-141
Page 5-149
Text which describes the endurance of PFlash and DFlash is enhanced.
Typo of big-endian support is deleted from the EBU section.
The spike-filters parameters are included, tSF1, tSF2
.
The maximum limit for IOZ1 is updated.
The temperature sensor measurement time parameter is added.
The condition for HWCFG is deleted from hold time from PORST rising
edge.
Page 5-150
Page 5-151
Page 5-166
The power, pad, reset timing figure is updated.
The notes under the PLL sections are updated.
Footnote for t12 and t21 for EBU Burst Mode Access Timing section is
updated.
Page 5-166
Footnote 2 is added for t10, footnote 5 is added for t23, t24 t25 and t26 in
EBU Burst Mode Access Timing section.
Trademarks
TriCore® is a trademark of Infineon Technologies AG.
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Please send your proposal (including a reference to this document) to:
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Data Sheet
V1.1, 2009-05
TC1197
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Related Documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reserved, Undefined, and Unimplemented Terminology . . . . . . . . . . . . 9
Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System Architecture of the TC1197 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TC1197 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CPU Cores of the TC1197 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High-performance 32-bit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High-performance 32-bit Peripheral Control Processor . . . . . . . . . . . 17
On-Chip System Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Flexible Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Features of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Die Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
General Purpose I/O Ports and Peripheral I/O Lines . . . . . . . . . . . . . . . 23
Program Memory Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overlay RAM and Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Emulation Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Tuning Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Program and Data Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Access Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
On-Chip Peripheral Units of the TC1197 . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Asynchronous/Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . 33
High-Speed Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . 35
Micro Second Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MultiCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Micro Link Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General Purpose Timer Array (GPTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.2
2.2.1
2.2.2
2.2.3
2.2.3.1
2.2.3.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.4.1
2.3.4.2
2.3.4.3
2.3.4.4
2.3.4.5
2.3.5
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.4
2.3.6.5
2.3.7
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
Data Sheet
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V1.1, 2009-05
TC1197
Table of Contents
2.5.6.1
2.5.6.2
2.5.7
2.5.7.1
2.5.7.2
2.5.8
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Functionality of LTCA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FADC Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Real Time Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Calibration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Tool Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Self-Test Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
FAR Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3
3.1
3.1.1
3.1.2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
TC1197 Pin Definition and Functions: PG-BGA-416-10 . . . . . . . . . . . . . . 57
TC1197 PG-BGA-416-10 Package Variant Pin Configuration . . . . . . . . 58
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . 118
4
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5
5.1
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . 123
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Analog to Digital Converters (ADC0/ADC1/ADC2) . . . . . . . . . . . . . . . 133
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . 138
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
Data Sheet
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V1.1, 2009-05
TC1197
Table of Contents
5.3.9.1
5.3.9.2
5.3.9.3
5.3.10
5.3.10.1
5.3.10.2
5.3.10.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 172
SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Data Sheet
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V1.1, 2009-05
TC1197
Summary of Features
1
Summary of Features
• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 180 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 180 MHz operation at full temperature range
• Multiple on-chip memories
– 4 or 21) Mbyte Program Flash Memory (PFLASH) with ECC
– 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 128 Kbyte Data Memory (LDRAM)
– 40 Kbyte Code Scratchpad Memory (SPRAM)
– Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
– Data Cache: up to 4 Kbyte (DCACHE, configurable)
– 8 Kbyte Overlay Memory (OVRAM)
– 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• 32-bit External Bus Interface Unit (EBU) with
– 32-bit demultiplexed / 16-bit multiplexed external bus interface (3.3V, 2.5V)
– Support for Burst Flash memory devices
– Scalable external bus timing up to 75 MHz
• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
• High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, EBU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridges (LFI Bridge)
• Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Two High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Two serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
1) Derivative dependent.
Data Sheet
4
V1.1, 2009-05
TC1197
Summary of Features
– Two High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
• 44 analog input lines for ADC
– 3 independent kernels (ADC0, ADC1, ADC2)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
– Performance for 12 bit resolution (@fADCI = 10 MHz)
• 4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz)
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• 221 digital general purpose I/O lines1) (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1797ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL
• Core supply voltage of 1.5 V
• I/O voltage of 3.3 V
• Temperature range: -40° to +125°C
• Package variants: PG-BGA-416-10
1) TC1197 package variant PG-BGA-416-10: 86 GPIO´s
Data Sheet
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V1.1, 2009-05
TC1197
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
• The package and the type of delivery.
For the available ordering codes for the TC1197 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1
TC1197 Derivative Synopsis
AmbientTemperature Program Flash CPU
Derivative
Range
frequency
180MHz
180MHz
SAK-TC1197-512F180E
SAK-TC1197-256F180E
TA = -40oC to +125oC
TA = -40oC to +125oC
4 MBytes
2 MBytes
Data Sheet
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V1.1, 2009-05
TC1197
Introduction
2
Introduction
This Data Sheet describes the Infineon TC1197, a 32-bit microcontroller DSP, based on
the Infineon TriCore Architecture.
2.1
About this Document
This document is designed to be read primarily by design engineers and software
engineers who need a detailed description of the interactions of the TC1197 functional
units, registers, instructions, and exceptions.
This TC1197 Data Sheet describes the features of the TC1197 with respect to the
TriCore Architecture. Where the TC1197 directly implements TriCore architectural
functions, this manual simply refers to those functions as features of the TC1197. In all
cases where this manual describes a TC1197 feature without referring to the TriCore
Architecture, this means that the TC1197 is a direct implementation of the TriCore
Architecture.
Where the TC1197 implements a subset of TriCore architectural features, this manual
describes the TC1197 implementation, and then describes how it differs from the TriCore
Architecture. Such differences between the TC1197 and the TriCore Architecture are
documented in the section covering each such subject.
2.1.1
Related Documentations
A complete description of the TriCore architecture is found in the document entitled
“TriCore Architecture Manual”. The architecture of the TC1197 is described separately
this way because of the configurable nature of the TriCore specification: Different
versions of the architecture may contain a different mix of systems components. The
TriCore architecture, however, remains constant across all derivative designs in order to
preserve compatibility.
This Data Sheets together with the “TriCore Architecture Manual” are required to
understand the complete TC1197 micro controller functionality.
2.1.2
Text Conventions
This document uses the following text conventions for named components of the
TC1197:
• Functional units of the TC1197 are given in plain UPPER CASE. For example: “The
SSC supports full-duplex and half-duplex synchronous communication”.
• Pins using negative logic are indicated by an overline. For example: “The external
reset pin, ESR0, has a dual function.”.
• Bit fields and bits in registers are in general referenced as
“Module_Register name.Bit field” or “Module_Register name.Bit”. For example: “The
Current CPU Priority Number bit field CPU_ICR.CCPN is cleared”. Most of the
Data Sheet
7
V1.1, 2009-05
TC1197
Introduction
register names contain a module name prefix, separated by an underscore character
“_” from the actual register name (for example, “ASC0_CON”, where “ASC0” is the
module name prefix, and “CON” is the kernel register name). In chapters describing
the kernels of the peripheral modules, the registers are mainly referenced with their
kernel register names. The peripheral module implementation sections mainly refer
to the actual register names with module prefixes.
• Variables used to describe sets of processing units or registers appear in mixed
upper and lower cases. For example, register name “MSGCFGn” refers to multiple
“MSGCFG” registers with variable n. The bounds of the variables are always given
where the register expression is first used (for example, “n = 0-31”), and are repeated
as needed in the rest of the text.
• The default radix is decimal. Hexadecimal constants are suffixed with a subscript
letter “H”, as in 100H. Binary constants are suffixed with a subscript letter “B”, as in:
111B.
• When the extent of register fields, groups register bits, or groups of pins are
collectively named in the body of the document, they are represented as
“NAME[A:B]”, which defines a range for the named group from B to A. Individual bits,
signals, or pins are given as “NAME[C]” where the range of the variable C is given in
the text. For example: CFG[2:0] and SRPN[0].
• Units are abbreviated as follows:
– MHz = Megahertz
– μs = Microseconds
– kBaud, kbit = 1000 characters/bits per second
– MBaud, Mbit = 1,000,000 characters/bits per second
– Kbyte, KB = 1024 bytes of memory
– Mbyte, MB= 1048576 bytes of memory
In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by
1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The
kBaud unit scales the expression preceding it by 1000. The M prefix scales by
1,000,000 or 1048576, and μ scales by .000001. For example, 1 Kbyte is
1024 bytes, 1 Mbyte is 1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits
per second, 1 MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is
1,000,000 Hz.
• Data format quantities are defined as follows:
– Byte = 8-bit quantity
– Half-word = 16-bit quantity
– Word = 32-bit quantity
– Double-word = 64-bit quantity
Data Sheet
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Introduction
2.1.3
Reserved, Undefined, and Unimplemented Terminology
In tables where register bit fields are defined, the following conventions are used to
indicate undefined and unimplemented function. Furthermore, types of bits and bit fields
are defined using the abbreviations as shown in Table 2.
Table 2
Bit Function Terminology
Function of Bits
Description
Unimplemented,
Reserved
Register bit fields named 0 indicate unimplemented functions
with the following behavior.
• Reading these bit fields returns 0.
• These bit fields should be written with 0 if the bit field is
defined as r or rh.
• These bit fields have to be written with 0 if the bit field is
defined as rw.
These bit fields are reserved. The detailed description of these
bit fields can be found in the register descriptions.
rw
rwh
r
The bit or bit field can be read and written.
As rw, but bit or bit field can be also set or reset by hardware.
The bit or bit field can only be read (read-only).
w
The bit or bit field can only be written (write-only). A read to this
register will always give a default value back.
rh
s
This bit or bit field can be modified by hardware (read-hardware,
typical example: status flags). A read of this bit or bit field give
the actual status of this bit or bit field back. Writing to this bit or
bit field has no effect to the setting of this bit or bit field.
Bits with this attribute are “sticky” in one direction. If their reset
value is once overwritten by software, they can be switched
again into their reset state only by a reset operation. Software
cannot switch this type of bit into its reset state by writing the
register. This attribute can be combined to “rws” or “rwhs”.
f
Bits with this attribute are readable only when they are accessed
by an instruction fetch. Normal data read operations will return
other values.
2.1.4
Register Access Modes
Read and write access to registers and memory locations are sometimes restricted. In
memory and register access tables, the terms as defined in Table 3 are used.
Data Sheet
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Introduction
Table 3
Symbol
U
Access Terms
Description
Access Mode: Access permitted in User Mode 0 or 1.
Reset Value: Value or bit is not changed by a reset operation.
Access permitted in Supervisor Mode.
SV
R
Read-only register.
32
Only 32-bit word accesses are permitted to this register/address range.
Endinit-protected register/address.
E
PW
NC
BE
nBE
Password-protected register/address.
No change, indicated register is not changed.
Indicates that an access to this address range generates a Bus Error.
Indicates that no Bus Error is generated when accessing this address
range, even though it is either an access to an undefined address or the
access does not follow the given rules.
nE
Indicates that no Error is generated when accessing this address or
address range, even though the access is to an undefined address or
address range. True for CPU accesses (MTCR/MFCR) to undefined
addresses in the CSFR range.
2.1.5
Abbreviations and Acronyms
The following acronyms and terms are used in this document:
ADC
Analog-to-Digital Converter
Address General Purpose Register
Arithmetic and Logic Unit
Asynchronous/Synchronous Serial Controller
Bus Control Unit
AGPR
ALU
ASC
BCU
BROM
CAN
Boot ROM & Test ROM
Controller Area Network
CMEM
CISC
CPS
PCP Code Memory
Complex Instruction Set Computing
CPU Slave Interface
CPU
Central Processing Unit
Data Sheet
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Introduction
CSA
Context Save Area
CSFR
DAP
Core Special Function Register
Device Access Port
DAS
Device Access Server
DCACHE
DFLASH
DGPR
DMA
DMI
Data Cache
Data Flash Memory
Data General Purpose Register
Direct Memory Access
Data Memory Interface
External Bus Interface
EBU
EMI
Electro-Magnetic Interference
Fast Analog-to-Digital Converter
Flash Array Module
FADC
FAM
FCS
Flash Command State Machine
Flash Interface and Control Module
Flexible Peripheral Interconnect (Bus)
Floating Point Unit
FIM
FPI
FPU
GPIO
GPR
GPTA
ICACHE
I/O
General Purpose Input/Output
General Purpose Register
General Purpose Timer Array
Instruction Cache
Input / Output
JTAG
LBCU
LDRAM
LFI
Joint Test Action Group = IEEE1149.1
Local Memory Bus Control Unit
Local Data RAM
Local Memory-to-FPI Bus Interface
Local Memory Bus
LMB
LTC
Local Timer Cell
MLI
Micro Link Interface
MMU
MSB
MSC
Memory Management Unit
Most Significant Bit
Micro Second Channel
Data Sheet
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Introduction
NC
Not Connected
NMI
Non-Maskable Interrupt
On-Chip Debug Support
Overlay Memory
OCDS
OVRAM
PCP
Peripheral Control Processor
Program Memory Unit
Phase Locked Loop
PMU
PLL
PCODE
PFLASH
PMI
PCP Code Memory
Program Flash Memory
Program Memory Interface
Program Memory Unit
PCP Parameter RAM
Random Access Memory
Reduced Instruction Set Computing
System Peripheral Bus Control Unit
System Control Unit
PMU
PRAM
RAM
RISC
SBCU
SCU
SFR
Special Function Register
System Peripheral Bus
Scratch-Pad RAM
SPB
SPRAM
SRAM
SRN
Static Data Memory
Service Request Node
Synchronous Serial Controller
System Timer
SSC
STM
WDT
Watchdog Timer
Data Sheet
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Introduction
2.2
System Architecture of the TC1197
The TC1197 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
• Reduced Instruction Set Computing (RISC) processor architecture
• Digital Signal Processing (DSP) operations and addressing modes
• On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1197 include:
• Efficient memory organization: instruction and data scratch memories, caches
• Serial communication interfaces – flexible synchronous and asynchronous modes
• Peripheral Control Processor – standalone data operations and interrupt servicing
• DMA Controller – DMA operations and interrupt servicing
• General-purpose timers
• High-performance on-chip buses
• On-chip debugging and emulation facilities
• Flexible interconnections to external components
• Flexible power-management
The TC1197 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1197 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1197 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1197, all these peripheral
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect
(FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1197 ports are
reserved for these peripheral units to communicate with the external world.
Data Sheet
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Introduction
2.2.1
TC1197 Block Diagram
Figure 1-1 shows the block diagram of the TC1197.
Abbreviations:
ICACHE: Instruction Cache
DCACHE Data Cache
FPU
DMI
PMI
SPRAM:
LDRAM:
OVRAM:
BROM:
PFlash:
DFlash:
PRAM:
Scratch-Pad RAM
Local Data RAM
Overlay RAM
Boot ROM
Program Flash
Data Flash
Parameter RAM in PCP
Code RAM in PCP
TriCore
CPU
124 KB LDRAM
24 KB SPRAM
4 KB DCACHE
16 KB ICACHE
(Configurable)
(Configurable)
CPS
PCODE:
Local Memory Bus (LMB)
EBU
BCU
1.5V, 3.3V
Ext. Supply
PMU0
PMU1
M
1)
DMA
2 MB PFlash
64 KB DFlash
8 KB OVRAM
16 KB BROM
Bridge
16 channels
OCDS L1 Debug
Interface/JTAG
2 MB PFlash
M/S
1) The 2 MBs of the PMU1
are available only
in the 4MByte derivative
MLI0
MLI1
System Peripheral Bus
(SPB)
16 KB PRAM
Interrupt
System
MemCheck
ASC0
ASC1
PCP2
Core
STM
SCU
s well)
5V (3.3V supported a
Ext. ADC Supply
32 KB CMEM
ADC0
ADC1
ADC2
Ports
SBCU
GPTA0
SSC0
SSC1
FADC
GPTA1
LTCA2
3.3V
Ext. FADC Supply
Multi
CAN
(4 Nodes,
128 MO)
Ext.
Request
Unit
MSC
MSC
1
0
(LVDS)
(LVDS)
BlockDiagram
TC1197
Figure 1
TC1197 Block Diagram
Data Sheet
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Introduction
2.2.2
System Features
The TC1197 has the following features:
Package
• PG-BGA-416-10 package, 1mm pitch
Clock Frequencies for the 180 MHz derivative
• Maximum CPU clock frequency: 180 MHz1)
• Maximum PCP clock frequency: 180 MHz2)
• Maximum system clock frequency: 90 MHz3)
1) For CPU frequencies > 90 MHz, 2:1 mode has to be enabled. CPU 2:1 mode means: fFPI = 0.5 * fCPU
2) For PCP frequencies > 90 MHz, 2:1 mode has to be enabled. PCP 2:1 mode means: fFPI = 0.5 * fPCP
3) CPU 1:1 Mode means: fFPI = fCPU . PCP 1:1 mode means: fFPI = fPCP
Data Sheet
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Introduction
2.2.3
CPU Cores of the TC1197
The TC1197 includes a high Performance CPU and a Peripheral Control Processor.
2.2.3.1
High-performance 32-bit CPU
This chapter gives an overview about the TriCore 1 architecture.
TriCore (TC1.3.1) Architectural Highlights
• Unified RISC MCU/DSP
• 32-bit architecture with 4 Gbytes unified data, program, and input/output address
space
• Fast automatic context-switching
• Multiply-accumulate unit
• Floating point unit
• Saturating integer arithmetic
• High-performance on-chip peripheral bus (FPI Bus)
• Register based design with multiple variable register banks
• Bit handling
• Packed data operations
• Zero overhead loop
• Precise exceptions
• Flexible power management
High-efficiency TriCore Instruction Set
• 16/32-bit instructions for reduced code size
• Data types include: Boolean, array of bits, character, signed and unsigned integer,
integer with saturation, signed fraction, double-word integers, and IEEE-754 single-
precision floating point
• Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, and 64-bit double-
word data formats
• Powerful instruction set
• Flexible and efficient addressing mode for high code density
Integrated CPU related On-Chip Memories
• Instruction memory: 40 KB total. After reset, configured into:1)
– 40 Kbyte Scratch-Pad RAM (SPRAM)
– 0 Kbyte Instruction Cache (ICACHE)
• Data memory: 128 KB total. After reset, configured into:1)
– 128 Kbyte Local Data RAM (LDRAM)
1) Software configurable. Available options are described in the CPU chapter.
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– 0 Kbyte Data Cache (DACHE)
• On-chip SRAMs with parity error detection
2.2.3.2
High-performance 32-bit Peripheral Control Processor
The PCP is a flexible Peripheral Control Processor optimized for interrupt handling and
thus unloading the CPU.
Features
• Data move between any two memory or I/O locations
• Data move until predefined limit supported
• Read-Modify-Write capabilities
• Full computation capabilities including basic MUL/DIV
• Read/move data and accumulate it to previously read data
• Read two data values and perform arithmetic or logical operation and store result
• Bit-handling capabilities (testing, setting, clearing)
• Flow control instructions (conditional/unconditional jumps, breakpoint)
• Dedicated Interrupt System
• PCP SRAMs with parity error detection
• PCP/FPI clock mode 1:1 and 2:1 available
Integrated PCP related On-Chip Memories
• 32 Kbyte Code Memory (CMEM)
• 16 Kbyte Parameter Memory (PRAM)
Data Sheet
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Introduction
2.3
On-Chip System Units
The TC1197 microcontroller offers several versatile on-chip system peripheral units
such as DMA controller, embedded Flash module, interrupt system and ports.
2.3.1
Flexible Interrupt System
The TC1197 includes a programmable interrupt system with the following features:
Features
• Fast interrupt response
• Independent interrupt systems for CPU and PCP
• Each SRN can be mapped to the CPU or PCP interrupt system
• Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per interrupt
system
2.3.2
Direct Memory Access Controller
The TC1197 includes a fast and flexible DMA controller with 16 independant DMA
channels (two DMA Move Engines).
Features
• 8 independent DMA channels
– 8 DMA channels in the DMA Sub-Block
– Up to 16 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within the DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
• 3-level programmable priority of the DMA Sub-Block at the on chip bus interfaces
• Buffer capability for move actions on the buses (at least 1 move per bus is buffered)
• Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous Mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated
– Programmable address modification
– Two shadow register modes (with / w/o automatic re-set and direct write access).
• Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Data block move supports > 32 Kbyte moves per DMA transaction
– Circular buffer addressing mode with flexible circular buffer sizes
• Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
• Register set for each DMA channel
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Introduction
– Source and destination address register
– Channel control and status register
– Transfer count register
• Flexible interrupt generation (the service request node logic for the MLI channel is
also implemented in the DMA module)
• DMA module is working on SPB frequency, LMB interface on LMB frequency.
• Dependant on the target/destination address, Read/write requests from the Move
Engine are directed to the SPB, LMB, MLI or to the the Cerberus.
Data Sheet
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Introduction
2.3.3
System Timer
The TC1197’s STM is designed for global system timing applications requiring both high
precision and long range.
Features
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Flexible interrupt generation based on compare match with partial STM content
• Driven by maximum 90 MHz (= fSYS, default after reset = fSYS/2)
• Counting starts automatically after a reset operation
• STM registers are reset by an application reset if bit ARSTDIS.STMDIS is cleared. If
bit ARSTDIS.STMDIS is set, the STM is not reset.
• STM can be halted in debug/suspend mode
Special STM register semantics provide synchronous views of the entire 56-bit counter,
or 32-bit subsets at different levels of resolution.
The maximum clock period is 256 × fSTM. At fSTM = 90 MHz, for example, the STM counts
25.39 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life time of a system without overflowing.
In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After
one of these reset conditions, the STM is enabled and immediately starts counting up. It
is not possible to affect the content of the timer during normal operation of the TC1197.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the TC1197
(initiated by writing an appropriate value to STM_CLC register), the STM clock is
stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
to count between the two load operations, there is a chance that the two values read are
not consistent (due to possible overflow from the low part of the timer to the high part
between the two read operations). To enable a synchronous and consistent reading of
the STM content, a capture register (STM_CAP) is implemented. It latches the content
of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5
is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time
when the lower part is read. The second read operation would then read the content of
the STM_CAP to get the complete timer value.
The content of the 56-bit System Timer can be compared against the content of two
compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be
generated on a compare match of the STM with the STM_CMP0 or STM_CMP1
registers.
Data Sheet
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Introduction
Figure 2 provides an overview on the STM module. It shows the options for reading
parts of STM content.
STM Module
31
23
15
7
0
STM_CMP0
Compare Register 0
to DMA etc.
31
23
15
7
0
STM_CMP1
Compare Register1
STM
IRQ0
55
47
39
31
23
15
7
0
Interrupt
Control
STM
IRQ1
56-bit System Timer
Enable /
Disable
00H
00H
STM_CAP
STM_TIM6
Clock
Control
fSTM
STM_TIM5
STM_TIM4
Address
Decoder
STM_TIM3
STM_TIM2
STM_TIM1
STM_TIM0
PORST
MCB06185_mod
Figure 2
General Block Diagram of the STM Module Registers
Data Sheet
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Introduction
2.3.4
System Control Unit
The following SCU introduction gives an overview about the TC1197 System Control
Unit (SCU) For Information about the SCU see chapter 3.
2.3.4.1 Clock Generation Unit
The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1197.
During user program execution the frequency can be programmed for an optimal ratio
between performance and power consumption.
2.3.4.2 Features of the Watchdog Timer
The main features of the WDT are summarized here.
• 16-bit Watchdog counter
• Selectable input frequency: fFPI/256 or fFPI/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated Password Access mechanism with fixed and user-definable password
fields
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled
• Double Reset Detection
2.3.4.3 Reset Operation
The following reset request triggers are available:
• 1 External power-on hardware reset request trigger; PORST, (cold reset)
• 2 External System Request reset triggers; ESR0 and ESR1,(warm reset)
• Watchdog Timer (WDT) reset request trigger, (warm reset)
• Software reset (SW), (warm reset)
• Debug (OCDS) reset request trigger, (warm reset)
• Resets via the JTAG interface
There are two basic types of reset request triggers:
• Trigger sources that do not depend on a clock, such as the PORST. This trigger force
the device into an asynchronous reset assertion independently of any clock. The
activation of an asynchronous reset is asynchronous to the system clock, whereas
its de-assertion is synchronized.
Data Sheet
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Introduction
• Trigger sources that need a clock in order to be asserted, such as the input signals
ESR0, ESR1, the WDT trigger, the parity trigger, or the SW trigger.
2.3.4.4 External Interface
The SCU provides interface pads for system purpose. Various functions are covered by
these pins. Due to the different tasks some of the pads can not be shared with other
functions but most of them can be shared with other functions. The following functions
are covered by the SCU controlled pads:
• Reset request triggers
• Reset indication
• Trap request triggers
• Interrupt request triggers
• Non SCU module triggers
The first three points are covered by the ESR pads and the last two points by the ERU
pads.
2.3.4.5 Die Temperature Measurement
The Die Temperature Sensor (DTS) generates a measurement result that indicates
directly the current temperature. The result of the measurement can be read via an DTS
register.
2.3.5
General Purpose I/O Ports and Peripheral I/O Lines
The TC1197 includes a flexible Ports structure with the following features:
Features
• Digital General-Purpose Input/Output (GPIO) port lines
• Input/output functionality individually programmable for each port line
• Programmable input characteristics (pull-up, pull-down, no pull device)
• Programmable output driver strength for EMI minimization (weak, medium, strong)
• Programmable output characteristics (push-pull, open drain)
• Programmable alternate output functions
• Output lines of each port can be updated port-wise or set/reset/toggled bit-wise
2.3.6
Program Memory Unit (PMU)
The devices of the AudoF family contain at least one Program Memory Unit. This is
named “PMU0”. Some devices contain additional PMUs which are named “PMU1”, …
In the TC1197, the PMU0 contains the following submodules:
• The Flash command and fetch control interface for Program Flash and Data Flash.
• The Overlay RAM interface with Online Data Acquisition (OLDA) support.
Data Sheet
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Introduction
• The Boot ROM interface.
• The Emulation Memory interface.
• The Local Memory Bus LMB slave interface.
Following memories are controlled by and belong to the PMU0:
• 2 Mbyte of Program Flash memory (PFlash)
• 64 Kbyte of Data Flash memory (DFlash, represents 16 Kbyte EEPROM)
• 16 Kbyte of Boot ROM (BROM)
• 8 Kbyte Overlay RAM (OVRAM)
In the TC1197 an additional PMU is included with only a subset of PMU0’s submodules:
• The Flash command and fetch control interface but only for Program Flash.
• The Local Memory Bus LMB slave interface.
The following memories are controlled and belong to the PMU1:
• 2 Mbyte of Program Flash memory (PFlash).
Because of its independence from PMU0 this second PMU enables additional
functionality: Read while Write (RWW), Write while Write (WWW) or concurrent data and
instruction accesses, if those are operating on different PMUs.
Data Sheet
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Introduction
The following figure shows the block diagram of the PMU0:
To/From
Local Memory Bus
64
LMB Interface
PMU0
Slave
Overlay RAM
PMU
Control
Interface
64
64
ROM Control
64
64
OVRAM
Flash Interface Module
64
64
BROM
DFLASH
PFLASH
Emulation
Memory
Interface
PMU0_BasicBlockDiag_generic
Emulation Memory
(ED chip only)
Figure 3
PMU0 Basic Block Diagram
As described before the PMU1 is reduced to the PFLASH and its controlling
submodules.
2.3.6.1 Boot ROM
The internal 16 Kbyte Boot ROM (BROM) is divided into two parts, used for:
• firmware (Boot ROM), and
• factory test routines (Test ROM).
The different sections of the firmware in Boot ROM provide startup and boot operations
after reset. The TestROM is reserved for special routines, which are used for testing,
stressing and qualification of the component.
Data Sheet
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Introduction
2.3.6.2 Overlay RAM and Data Acquisition
The overlay memory OVRAM is provided in the PMU especially for redirection of data
accesses to program memory to the OVRAM by using the data overlay function. The
data overlay functionality itself is controlled in the DMI module.
For online data acquisition (OLDA) of application or calibration data a virtual 32 KB
memory range is provided which can be accessed without error reporting. Accesses to
this OLDA range can also be redirected to an overlay memory.
2.3.6.3 Emulation Memory Interface
In TC1197 Emulation Device, an Emulation Memory (EMEM) is provided, which can fully
be used for calibration via program memory or OLDA overlay. The Emulation Memory
interface shown in Figure 0-1 is a 64-bit wide memory interface that controls the CPU-
accesses to the Emulation Memory in the TC1197 Emulation Device. In the TC1197
production device, the EMEM interface is always disabled.
2.3.6.4 Tuning Protection
Tuning protection is required by the user to absolutely protect control data (e.g. for
engine control), serial number and user software, stored in the Flash, from being
manipulated, and to safely detect changed or disturbed data. For the internal Flash,
these protection requirements are excellently fulfilled in the TC1197 with
• Flash read and write protection with user-specific protection levels, and with
• dedicated HW and firmware, supporting the internal Flash read protection, and with
• the Alternate Boot Mode.
Special tuning protection support is provided for external Flash, which must also be
protected.
2.3.6.5 Program and Data Flash
The embedded Flash modules of PMU0 includes 2 Mbyte of Flash memory for code or
constant data (called Program Flash) and additionally 64 Kbyte of Flash memory used
for emulation of EEPROM data (called Data Flash). The Program Flash is realized as
one independent Flash bank, whereas the Data Flash is built of two Flash banks,
allowing the following combinations of concurrent Flash operations:
• Read code or data from Program Flash, while one bank of Data Flash is busy with a
program or erase operation.
• Read data from one bank of Data Flash, while the other bank of Data Flash is busy
with a program or erase operation.
• Program one bank of Data Flash while erasing the other bank of Data Flash, read
from Program Flash.
Data Sheet
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Introduction
In TC1197 the PMU1 contains 2 Mbyte of Program Flash realized as one Flash bank. It
does not contain any Data Flash.
Since in TC1197 the two PMUs can work in parallel, further combinations of concurrent
operations are supported if those are operating on Flash modules in different PMUs, e.g.
• Read data from Flash1 while accessing code from Flash0.
• Read code or data from one Flash while the other Flash is busy with program or erase
operation.
• Both Flash modules are concurrently busy with program or erase operation.
Both, the Program Flash and the Data Flash, provide error correction of single-bit errors
within a 64-bit read double-word, resulting in an extremely low failure rate. Read
accesses to Program Flash are executed in 256-bit width, to Data Flash in 64-bit width
(both plus ECC). Single-cycle burst transfers of up to 4 double-words and sequential
prefetching with control of prefetch hit are supported for Program Flash.
The minimum programming width is the page, including 256 bytes in Program Flash and
128 bytes in Data Flash. Concurrent programming and erasing in Data Flash is
performed using an automatic erase suspend and resume function.
A basic block diagram of the Flash Module is shown in the following figure.
Redundancy
Control
FSI
Voltage Control
Control
Control
Flash Command
State Machine FCS
SFRs
FSRAM
Microcode
Address
Addr Bus
Write Bus
Page
Write
Buffers
256 byte
and
Program
Flash
64
64
WR_DATA
128 byte
8
8
PF-Read
Buffer
256+32 bit
and
ECC Code
Bank 0
Bank 1
ECC Block
Data
Flash
64
DF-Read
Buffer
64+8 bit
Read Bus
64
RD_DATA
Flash Array Module
FAM
Flash Interface&Control Module
FIM
PMU
Flash FSI & Array
Flash_BasicBlockDiagram_generic.vsd
Figure 4
Basic Block Diagram of Flash Module
All Flash operations are controlled simply by transferring command sequences to the
Flash which are based on JEDEC standard. This user interface of the embedded Flash
is very comfortable, because all operations are controlled with high level commands,
such as “Erase Sector”. State transitions, such as termination of command execution, or
errors are reported to the user by maskable interrupts. Command sequences are
Data Sheet
27
V1.1, 2009-05
TC1197
Introduction
normally written to Flash by the CPU, but may also be issued by the DMA controller (or
OCDS).
The Flash also features an advanced read/write protection architecture, including a read
protection for the whole Flash array (optionally without Data Flash) and separate write
protection for all sectors (only Program Flash). Write protected sectors can be made re-
programmable (enabled with passwords), or they can be locked for ever (ROM function).
Each sector can be assigned to up to three different users for write protection. The
different users are organized hierarchically.
Program Flash Features and Functions
• 2 Mbyte on-chip Program Flash in PMU0.
• 2 Mbyte on-chip Program Flash in PMU1.
• Any use for instruction code or constant data.
• Double Flash module system approach:
– Concurrent read access of code and data.
– Read while write (RWW).
– Concurrent program/erase in both modules.
• 256 bit read interface (burst transfer operation).
• Dynamic correction of single-bit errors during read access.
• Transfer rate in burst mode: One 64-bit double-word per clock cycle.
• Sector architecture:
– Eight 16 Kbyte, one 128 Kbyte and seven 256 Kbyte sectors.
– Each sector separately erasable.
– Each sector lockable for protection against erase and program (write protection).
• One additional configuration sector (not accessible to the user).
• Optional read protection for whole Flash, with sophisticated read access supervision.
Combined with whole Flash write protection — thus supporting protection against
Trojan horse programs.
• Sector specific write protection with support of re-programmability or locked forever.
• Comfortable password checking for temporary disable of write or read protection.
• User controlled configuration blocks (UCB) in configuration sector for keywords and
for sector-specific lock bits (one block for every user; up to three users).
• Pad supply voltage (VDDP) also used for program and erase (no VPP pin).
• Efficient 256 byte page program operation.
• All Flash operations controlled by CPU per command sequences (unlock sequences)
for protection against unintended operation.
• End-of-busy as well as error reporting with interrupt and bus error trap.
• Write state machine for automatic program and erase, including verification of
operation quality.
• Support of margin check.
• Delivery in erased state (read all zeros).
• Global and sector status information.
Data Sheet
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TC1197
Introduction
• Overlay support with SRAM for calibration applications.
• Configurable wait state selection for different CPU frequencies.
• Endurance = 1000; minimum 1000 program/erase cycles per physical sector;
reduced endurance of 100 per 16 KB sector.
• Operating lifetime (incl. Retention): 20 years with endurance=1000.
• For further operating conditions see data sheet section “Flash Memory Parameters”.
Data Flash Features and Functions
Note: Only available in PMU0.
• 64 Kbyte on-chip Flash, configured in two independent Flash banks of equal size.
• 64 bit read interface.
• Erase/program one bank while data read access from the other bank.
• Programming one bank while erasing the other bank using an automatic
suspend/resume function.
• Dynamic correction of single-bit errors during read access.
• Sector architecture:
– Two sectors of equal size.
– Each sector separately erasable.
• 128 byte pages to be written in one step.
• Operational control per command sequences (unlock sequences, same as those of
Program Flash) for protection against unintended operation.
• End-of-busy as well as error reporting with interrupt and bus error trap.
• Write state machine for automatic program and erase.
• Margin check for detection of problematic Flash bits.
• Endurance = 30000 (can be device dependent); i.e. 30000 program/erase cycles per
sector are allowed, with a retention of min. 5 years.
• Dedicated DFlash status information.
• Other characteristics: Same as Program Flash.
Data Sheet
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V1.1, 2009-05
TC1197
Introduction
2.3.7
Data Access Overlay
The data overlay functionality provides the capability to redirect data accesses by the
TriCore to program memory (internal Program Flash or external memory) to the Overlay
SRAM in the PMU, or to the Emulation Memory in Emulation Device ED, or to the
external memory. This functionality makes it possible, for example, to modify the
application’s test and calibration parameters (which are typically stored in the program
memory) during run time of a program. Note that read and write data accesses from/to
program memory are redirected.
Attention: As the address translation is implemented in the DMI, it is only effective
for data accesses by the TriCore. Instruction fetches by the TriCore or
accesses by any other master (including the debug interface) are not
affected!
Note: The external memory can be used as overlay memory only in Emulation Devices
“ED” with an EBU. Generally this feature is not supported in Production Devices
“PD”. However, this function is fully described here in this spec.
Summary of Features and Functions
• 16 overlay ranges (“blocks”) configurable for Program Flash and external memory
• Support of 8 Kbyte embedded Overlay SRAM (OVRAM) in PMU
• Support of up to 512 Kbyte overlay/calibration memory in Emulation Device (EMEM)
• Support of up to 2 MB overlay memory in external memory (EBU space)
• Support of Online Data Acquisition into range of up to 32 KB and of its overlay
• Support of different overlay memory selections for every enabled overlay block
• Sizes of overlay blocks selectable from 16 byte to 2 Kbyte for redirection to OVRAM
• Sizes of overlay blocks selectable from 1 Kbyte to 128 Kbyte for redirection to EMEM
or to external memory
• All configured overlay ranges can be enabled with only one register write access
• Programmable flush (invalidate) control for data cache in DMI
2.4
Development Support
Overview about the TC1197 development environment:
Complete Development Support
A variety of software and hardware development tools for the 32-bit microcontroller
TC1197 are available from experienced international tool suppliers. The development
environment for the Infineon 32-bit microcontroller includes the following tools:
• Embedded Development Environment for TriCore Products
• The TC1197 On-chip Debug Support (OCDS) provides a JTAG port for
communication between external hardware and the system
Data Sheet
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Introduction
• Flexible Peripheral Interconnect Buses (FPI Bus) for on-chip interconnections and its
FPI Bus control unit (SBCU)
• The System Timer (STM) with high-precision, long-range timing capabilities
• The TC1197 includes a power management system, a watchdog timer as well as
reset logic
Data Sheet
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TC1197
Introduction
2.5
On-Chip Peripheral Units of the TC1197
The TC1197 microcontroller offers several versatile on-chip peripheral units such as
serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the
TC1197 ports are reserved for these peripheral units to communicate with the external
world.
On-Chip Peripheral Units
• Two Asynchronous/Synchronous Serial Channels (ASC) with baud-rate generator,
parity, framing and overrun error detection
• Two Synchronous Serial Channels (SSC) with programmable data length and shift
direction
• Two Micro Second Bus Interfaces (MSC) for serial communication
• One CAN Module with four CAN nodes (MultiCAN) for high-efficiency data handling
via FIFO buffering and gateway data transfer
• Two Micro Link Serial Bus Interfaces (MLI) for serial multiprocessor communication
• Two General Purpose Timer Arrays (GPTA) with a powerful set of digital signal
filtering and timer functionality to accomplish autonomous and complex Input/Output
management. One additional Local Timer Cell Array (LCTA).
• Three Analog-to-Digital Converter Units (ADC) with 8-bit, 10-bit, or 12-bit resolution.
• One fast Analog-to-Digital Converter Unit (FADC)
• One External Bus Interface (EBU)
Data Sheet
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TC1197
Introduction
2.5.1
Asynchronous/Synchronous Serial Interfaces
The TC1197 includes two Asynchronous/Synchronous Serial Interfaces, ASC0 and
ASC1. Both ASC modules have the same functionality.
Figure 5 shows a global view of the Asynchronous/Synchronous Serial Interface (ASC).
fASC
Clock
Control
RXD
TXD
RXD
TXD
Address
Decoder
ASC
Module
(Kernel)
Port
Control
EIR
TBIR
TIR
RIR
Interrupt
Control
To DMA
MCB05762_mod
Figure 5
General Block Diagram of the ASC Interface
The ASC provides serial communication between the TC1197 and other
microcontrollers, microprocessors, or external peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock that is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal, which can be accurately adjusted
by a prescaler implemented as fractional divider.
Data Sheet
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TC1197
Introduction
Features
• Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity-bit generation/checking
– One or two stop bits
– Baud rate from 5.625 Mbit/s to 1.34 bit/s (@ 90 MHz module clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
• Half-duplex 8-bit synchronous operating mode
– Baud rate from 11.25 Mbit/s to 915.5 bit/s (@ 90 MHz module clock)
• Double-buffered transmitter/receiver
• Interrupt generation
– On a transmit buffer empty condition
– On a transmit last bit of a frame condition
– On a receive buffer full condition
– On an error condition (frame, parity, overrun error)
• Implementation features
– Connections to DMA Controller
– Connections of receiver input to GPTA (LTC) for baud rate detection and LIN break
signal measuring
Data Sheet
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TC1197
Introduction
2.5.2
High-Speed Synchronous Serial Interfaces
The TC1197 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1.
Both SSC modules have the same functionality.
Figure 6 shows a global view of the Synchronous Serial interface (SSC).
MRSTA
MRSTB
MTSR
fSSC
fCLC
Master
Clock
Control
MTSR
MRST
MTSRA
MTSRB
MRST
Slave
Slave
Address
Decoder
SCLKA
SCLKB
SCLK
SSC
Module
(Kernel)
Port
Control
RIR
TIR
EIR
Master
Slave
SCLK
SLSI[7:1]
Interrupt
Control
SLSI[7:1]
SLSO[7:0]
SLSOANDO[7:0]
SLSOANDI[7:0]
SLSO[7:0]
SLSOANDO[7:0]
Master
DMA Requests
Enable
M/S Select
MCB06058_mod
Figure 6
General Block Diagram of the SSC Interface
The SSC supports full-duplex and half-duplex serial synchronous communication up to
45 Mbit/s (@ 90 MHz module clock, Master Mode). The serial clock signal can be
generated by the SSC itself (Master Mode) or can be received from an external master
(Slave Mode). Data width, shift direction, clock polarity and phase are programmable.
This allows communication with SPI-compatible devices. Transmission and reception of
data are double-buffered. A shift clock generator provides the SSC with a separate serial
clock signal. One slave select input is available for slave mode operation. Eight
programmable slave select outputs (chip selects) are supported in Master Mode.
Data Sheet
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V1.1, 2009-05
TC1197
Introduction
Features
• Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock/data phase: Data shift with leading or trailing edge of the shift
clock
• Baud rate generation
– Master Mode:
– Slave Mode:
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
• Flexible SSC pin configuration
• Seven slave select inputs SLSI[7:1] in Slave Mode
• Eight programmable slave select outputs SLSO[7:0] in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
– Combinable with SLSO output signals from other SSC modules
Data Sheet
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TC1197
Introduction
2.5.3
Micro Second Channel Interface
The TC1197 includes two Micro Second Channel interfaces, MSC0 and MSC1. Both
MSC modules have the same functionality.
Each Micro Second Channel (MSC) interface provides serial communication links
typically used to connect power switches or other peripheral devices. The serial
communication link includes a fast synchronous downstream channel and a slow
asynchronous upstream channel. Figure 7 shows a global view of the interface signals
of an MSC interface.
fMSC
Clock
Control
fCLC
FCLP
FCLN
SOP
SON
EN0
Address
Decoder
MSC
Module
(Kernel)
SR[3:0]
16
Interrupt
Control
EN1
4
EN2
To DMA
EN3
ALTINL[15:0]
ALTINH[15:0]
EMGSTOPMSC
8
SDI[7:0]
16
MCB06059
Figure 7
General Block Diagram of the MSC Interface
The downstream and upstream channels of the MSC module communicate with the
external world via nine I/O lines. Eight output lines are required for the serial
communication of the downstream channel (clock, data, and enable signals). One out of
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The
source of the serial data to be transmitted by the downstream channel can be MSC
register contents or data that is provided on the ALTINL/ALTINH input lines. These input
lines are typically connected with other on-chip peripheral units (for example with a timer
unit such as the GPTA). An emergency stop input signal makes it possible to set bits of
the serial data stream to dedicated values in an emergency case.
Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.
Data Sheet
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V1.1, 2009-05
TC1197
Introduction
Features
• Fast synchronous serial interface to connect power switches in particular, or other
peripheral devices via serial buses
• High-speed synchronous serial transmission on downstream channel
– Serial output clock frequency: fFCL = fMSC/2 (fMSCmax = 90 MHz)
– Fractional clock divider for precise frequency control of serial clock fMSC
– Command, data, and passive frame types
– Start of serial frame: Software-controlled, timer-controlled, or free-running
– Programmable upstream data frame length (16 or 12 bits)
– Transmission with or without SEL bit
– Flexible chip select generation indicates status during serial frame transmission
– Emergency stop without CPU intervention
• Low-speed asynchronous serial reception on upstream channel
– Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256 (fMSCmax = 90 MHz)
– Standard asynchronous serial frames
– Parity error checker
– 8-to-1 input multiplexer for SDI lines
– Built-in spike filter on SDI lines
• Selectable pin types of downstream channel interface:
four LVDS differential output drivers or four digital GPIO pins
Data Sheet
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TC1197
Introduction
2.5.4
MultiCAN Controller
The MultiCAN module provides four independent CAN nodes, representing four serial
communication interfaces. The number of available message objects is 128.
MultiCAN Module Kernel
fCAN
TXDC3
CAN
Clock
Control
Node 3
fCLC
RXDC3
TXDC2
RXDC2
TXDC1
Message
Object
Buffer
CAN
Node 2
Linked
List
Control
Port
Control
Address
Decoder
CAN
Node 1
128
Objects
RXDC1
TXDC0
CAN
Node 0
RXDC0
Interrupt
Control
CAN Control
MCA06060_N4
Figure 8
Overview of the MultiCAN Module
The MultiCAN module contains four independently operating CAN nodes with Full-CAN
functionality that are able to exchange Data and Remote Frames via a gateway function.
Transmission and reception of CAN frames is handled in accordance to CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
All four CAN nodes share a common set of message objects. Each message object can
be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects can be combined to build
gateways between the CAN nodes or to set up a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to the message object list of the CAN node, and it transmits
only messages belonging to this message object list. A powerful, command-driven list
controller performs all message object list operations.
The bit timings for the CAN nodes are derived from the module timer clock (fCAN) and are
programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected to
a CAN node via a pair of receive and transmit pins.
Data Sheet
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Introduction
Features
• Compliant with ISO 11898
• CAN functionality according to CAN specification V2.0 B active
• Dedicated control registers for each CAN node
• Data transfer rates up to 1 Mbit/s
• Flexible and powerful message transfer control and error handling capabilities
• Advanced CAN bus bit timing analysis and baud rate detection for each CAN node
via a frame counter
• Full-CAN functionality: A set of 128 message objects can be individually
– Allocated (assigned) to any CAN node
– Configured as transmit or receive object
– Setup to handle frames with 11-bit or 29-bit identifier
– Identified by a timestamp via a frame counter
– Configured to remote monitoring mode
• Advanced Acceptance Filtering
– Each message object provides an individual acceptance mask to filter incoming
frames.
– A message object can be configured to accept standard or extended frames or to
accept both standard and extended frames.
– Message objects can be grouped into four priority classes for transmission and
reception.
– The selection of the message to be transmitted first can be based on frame
identifier, IDE bit and RTR bit according to CAN arbitration rules, or on its order in
the list.
• Advanced message object functionality
– Message objects can be combined to build FIFO message buffers of arbitrary size,
limited only by the total number of message objects.
– Message objects can be linked to form a gateway that automatically transfers
frames between 2 different CAN buses. A single gateway can link any two CAN
nodes. An arbitrary number of gateways can be defined.
• Advanced data management
– The message objects are organized in double-chained lists.
– List reorganizations can be performed at any time, even during full operation of the
CAN nodes.
– A powerful, command-driven list controller manages the organization of the list
structure and ensures consistency of the list.
– Message FIFOs are based on the list structure and can easily be scaled in size
during CAN operation.
– Static allocation commands offer compatibility with MultiCAN applications that are
not list-based.
• Advanced interrupt handling
Data Sheet
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Introduction
– Up to 16 interrupt output lines are available. Interrupt requests can be routed
individually to one of the 16 interrupt output lines.
– Message post-processing notifications can be combined flexibly into a dedicated
register field of 256 notification bits.
Data Sheet
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TC1197
Introduction
2.5.5
Micro Link Serial Bus Interface
This TC1197 contains two Micro Link Serial Bus Interfaces, MLI0 and MLI1.
The Micro Link Interface (MLI) is a fast synchronous serial interface to exchange data
between microcontrollers or other devices, such as stand-alone peripheral components.
Figure 9 shows how two microcontrollers are typically connected together via their MLI
interfaces.
Controller 1
CPU
Controller 2
CPU
Peripheral
A
Peripheral
B
Peripheral
C
Peripheral
D
Memory
MLI
MLI
Memory
System Bus
System Bus
MCA06061
Figure 9
Features
Typical Micro Link Interface Connection
• Synchronous serial communication between an MLI transmitter and an MLI receiver
• Different system clock speeds supported in MLI transmitter and MLI receiver due to
full handshake protocol (4 lines between a transmitter and a receiver)
• Fully transparent read/write access supported (= remote programming)
• Complete address range of target device available
• Specific frame protocol to transfer commands, addresses and data
• Error detection by parity bit
• 32-bit, 16-bit, or 8-bit data transfers supported
• Programmable baud rate: fMLI/2 (max. fMLI = fSYS
)
• Address range protection scheme to block unauthorized accesses
• Multiple receiving devices supported
Data Sheet
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V1.1, 2009-05
TC1197
Introduction
Figure 10 shows a general block diagram of the MLI module.
TREADY[D:A]
4
4
TVALID[D:A]
TDATA
fSYS
Fract.
Divider
MLI
Transmitter
I/O
Control
TCLK
TR[3:0]
fMLI
Port
Control
MLI Module
BRKOUT
SR[7:0]
RCLK[D:A]
4
4
4
4
RREADY[D:A]
RVALID[D:A]
RDATA[D:A]
Move
Engine
MLI
Receiver
I/O
Control
MCB06062_mod
Figure 10
General Block Diagram of the MLI Modules
The MLI transmitter and MLI receiver communicate with other MLI receivers and MLI
transmitters via a four-line serial connection each. Several I/O lines of these connections
are available outside the MLI module kernel as a four-line output or input vector with
index numbering A, B, C and D. The MLI module internal I/O control blocks define which
signal of a vector is actually taken into account and also allow polarity inversions (to
adapt to different physical interconnection means)
Data Sheet
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V1.1, 2009-05
TC1197
Introduction
2.5.6
General Purpose Timer Array (GPTA)
The TC1197 contains the General Purpose Timer Array (GPTA0), plus the additional
Local Timer Cell Array (LTCA2). Figure 11 shows a global view of the GPTA modules.
The GPTA provides a set of timer, compare, and capture functionalities that can be
flexibly combined to form signal measurement and signal generation units. They are
optimized for tasks typical of engine, gearbox, and electrical motor control applications,
but can also be used to generate simple and complex signal waveforms required for
other industrial applications.
GPTA0
Clock Generation Cells
FPC0
DCM0
FPC1
FPC2
FPC3
FPC4
FPC5
PDL0
PDL1
DCM1
DCM2
DCM3
DIGITAL
PLL
fGPTA Clock Distribution Cells
Clock
Conn .
Signal
Generation Cells
GT0
GT1
LTCA2
GTC00
GTC01
GTC02
GTC03
LTC00
LTC01
LTC02
LTC03
LTC00
LTC01
LTC02
LTC03
Global
Timer
Cell Array
Local
Timer
Cell Array
Local
Timer
Cell Array
GTC30
GTC31
LTC62
LTC63
LTC62
LTC63
I/O Line
Sharing Block
I/O Line Sharing Block
Interrupt Sharing Block
Interrupt
Sharing Block
MCB05910_TC1767
Figure 11
General Block Diagram of the GPTA Modules in the TC1197
Data Sheet
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V1.1, 2009-05
TC1197
Introduction
2.5.6.1 Functionality of GPTA0
The General Purpose Timer Array (GPTA0) provides a set of hardware modules
required for high-speed digital signal processing:
• Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
• Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
• Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
• A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
• Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
• Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may also be used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
• Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or
triggered by various external or internal events.
• On-chip Trigger and Gating Signals (OTGS) can be configured to provide trigger or
gating signals to integrated peripherals.
Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following list summarizes the specific features of the GPTA units.
Clock Generation Unit
• Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA module clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock.
– fGPTA/2 maximum input signal frequency in Filter Modes
• Phase Discriminator Logic (PDL)
– Two independent units
– Two operating modes (2- and 3- sensor signals)
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Introduction
– fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input
signal frequency in 3-sensor Mode
• Duty Cycle Measurement (DCM)
– Four independent units
– 0 - 100% margin and time-out handling
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Digital Phase Locked Loop (PLL)
– One unit
– Arbitrary multiplication factor between 1 and 65535
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Clock Distribution Unit (CDU)
– One unit
– Provides nine clock output signals:
f
GPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock
Signal Generation Unit
• Global Timers (GT)
– Two independent units
– Two operating modes (Free-Running Timer and Reload Timer)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Global Timer Cell (GTC)
– 32 units related to the Global Timers
– Two operating modes (Capture, Compare and Capture after Compare)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
• Local Timer Cell (LTC)
– 64 independent units
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Interrupt Sharing Unit
• 286 interrupt sources, generating up to 92 service requests
Data Sheet
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Introduction
On-chip Trigger Unit
• 16 on-chip trigger signals
I/O Sharing Unit
• Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and
MSC interface
2.5.6.2 Functionality of LTCA2
The Local Timer Cell Array (LTCA2) provides a set of hardware modules required for
high-speed digital signal processing:
• Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or
triggered by various external or internal events.
The following list summarizes the specific features of the LTCA unit.
The Local Timer Arrays (LTCA2) provides a set of hardware modules required for high-
speed digital signal processing:
Signal Generation Unit
• Local Timer Cell (LTC)
– 32 independent units
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
I/O Sharing Unit
• Interconnecting inputs and outputs from internal clocks, LTC, ports, and MSC
interface
Data Sheet
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Introduction
2.5.7
Analog-to-Digital Converters
The TC1197 includes three Analog to Digital Converter modules (ADC0, ADC1, ADC2)
and one Fast Analog to Digital Converter (FADC).
2.5.7.1 ADC Block Diagram
The analog to digital converter module (ADC) allows the conversion of analog input
values into discrete digital values based on the successive approximation method.
This module contains 3 independent kernels (ADC0, ADC1, ADC2) that can operate
autonomously or can be synchronized to each other. An ADC kernel is a unit used to
convert an analog input signal (done by an analog part) and provides means for
triggering conversions, data handling and storage (done by a digital part).
analog part kernel 0
digital part kernel 0
analog
inputs
AD
converter
data (result)
handling
conversion
control
request
control
analog part kernel 1
digital part kernel 1
analog
inputs
AD
converter
data (result)
handling
bus
inter-
face
conversion
control
request
control
analog part kernel 2
digital part kernel 2
analog
inputs
AD
converter
data (result)
handling
conversion
control
request
control
ADC_3_kernels
Figure 12
ADC Module with three ADC Kernels
Features of the analog part of each ADC kernel:
Data Sheet
48
V1.1, 2009-05
TC1197
Introduction
• Input voltage range from 0V to analog supply voltage
• Analog supply voltage range from 3.3 V to 5 V (single supply)
(5V nominal supply voltage, performance degradation accepted for lower voltages)
• Input multiplexer width of 16 possible analog input channels (not all of them are
necessarily available on pins)
• Performance for 12 bit resolution (@fADCI = 10 MHz):
- conversion time about 2µs, TUE1) of ±4 LSB12 @ operating voltage 5 V
- conversion time about 2µs, TUE of ±4 LSB12 @ operating voltage 3.3 V
• VAREF and 1 alternative reference input at channel 0
• Programmable sample time (in periods of fADCI
)
• Wide range of accepted analog clock frequencies fADCI
• Multiplexer test mode (channel 7 input can be connected to ground via a resistor for
test purposes during run time by specific control bit)
• Power saving mechanisms
Features of the digital part of each ADC kernel:
• Independent result registers (16 independent registers)
• 5 conversion request sources (e.g. for external events, auto-scan, programmable
sequence, etc.)
• Synchronization of the ADC kernels for concurrent conversion starts
• Control an external analog multiplexer, respecting the additional set up time
• Programmable sampling times for different channels
• Possibility to cancel running conversions on demand with automatic restart
• Flexible interrupt generation (possibility of DMA support)
• Limit checking to reduce interrupt load
• Programmable data reduction filter by adding conversion results
• Support of conversion data FIFO
• Support of suspend and power down modes
• Individually programmable reference selection for each channel (with exception of
dedicated channels always referring to VAREF
)
1) This value reflects the ADC module capability in an adapted electrical environment, e.g. characterized by
“clean” routing of analog and digital signals and separation of analog and digital PCB areas, low noise on
analog power supply (< 30mV), low switching activity of digital pins near to the ADC, etc.
Data Sheet
49
V1.1, 2009-05
TC1197
Introduction
2.5.7.2 FADC Short Description
General Features
• Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz)
• 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• Successive approximation conversion method
• Two differential input channels with impedance control available on dedicated pins
• Two differential input channels with impedance control overlaid with ADC1 inputs
• Each differential input channel can also be used as single-ended input
• Offset calibration support for each channel
• Programmable gain of 1, 2, 4, or 8 for each channel
• Free-running (Channel Timers) or triggered conversion modes
• Trigger and gating control for external signals
• Built-in Channel Timers for internal triggering
• Channel timer request periods independently selectable for each channel
• Selectable, programmable digital anti-aliasing and data reduction filter block with four
independent filter units
VDDAF
VFAGND VSSAF
VFAREF
VDDMF VDDIF
VSSMF
fFADC
fCLC
Data
Reduction
Unit
Clock
Control
FAIN0P
FAIN0N
FAIN1P
FAIN1N
FAIN2P
FAIN2N
FAIN3P
FAIN3N
input
channel 0
A/D
Control
input
channel 1
A/D
Converter
Stage
SRx
SRx
Interrupt
Control
input
channel 2
input
channel 3
DMA
TS[H:A]
GS[H:A]
Channel
Trigger
Control
Channel
Timers
MCB06065_m4
Figure 13
Block Diagram of the FADC Module with 4 Input Channels
Data Sheet
50
V1.1, 2009-05
TC1197
Introduction
As shown in Figure 13, the main FADC functional blocks are:
• An Input Structure containing the differential inputs and impedance control.
• An A/D Converter Stage responsible for the analog-to-digital conversion including an
input multiplexer to select between the channel amplifiers
• A Data Reduction Unit containing programmable anti-aliasing and data reduction
filters
• A Channel Trigger Control block determining the trigger and gating conditions for the
FADC channels
• A Channel Timer for each channel to independently trigger the conversions
• An A/D Control block responsible for the overall FADC functionality
FADC Power Supply and References
The FADC module is supplied by the following power supply and reference voltage lines:
• VDDMF / VSSMF: FADC Analog Channel Amplifier Power Supply (3.3 V)
• VDDIF / VSSMF: FADC Analog Input Stage Power Supply (3.3 - 5 V),
the VDDIF supply does not appear as supply pin, because it is internally connected to
the VDDM supply of the ADC that is sharing the FADC input pins.
• VDDAF / VSSAF: FADC Analog Part Power Supply (1.5 V),
to be fed in externally
• VFAREF / VFAGND: FADC Reference Voltage (3.3 V max.) and FADC Reference Ground
Input Structure
The input structure of the FADC in the TC1197 contains:
• A differential analog input stage for each input channel to select the input impedance
(differential or single-ended measurement) and to decouple the FADC input signal
from the pins.
• Input channels 2 and 3 are overlaid with ADC1 input signals (AN28, AN29, AN30,
AN31), whereas input channels 0 and 1 are available on dedicated input pins (AN32,
AN33, AN34, AN35).
• A channel amplifier for each input channel with a settling time (about 5µs) when
changing the characteristics of an input stage (changing between unused,
differential, single-ended N, or single-ended P mode).
Data Sheet
51
V1.1, 2009-05
TC1197
Introduction
Analog Input
Stages
Channel Amplifier
Stages
Converter Stage
V
DDMF
FAIN0P
FAIN0N
Rp
conversion
control
A/D
Control
Rn
gain
VSSMF
CHNR
Rp
Rn
V
DDMF
FAIN2P
FAIN2N
V
SSMF
A/D
Rp
Rn
V
DDMF
FAIN1P
FAIN1N
V
DDAF
V
SSAF
VSSMF
Rp
Rn
V
DDMF
FAIN3P
FAIN3N
VSSMF
MCA06432_m4n
V
DDIF
VSSMF
Figure 14
FADC Input Structure in TC1197
Data Sheet
52
V1.1, 2009-05
TC1197
Introduction
2.5.8
External Bus Interface
The External Bus Unit (EBU) of the TC1197 controls the accesses from peripheral units
to external memories.
Features:
• 64-bit internal LMB interface
• 32-bit demultiplexed / 16-bit multiplexed external bus interface (3.3V, 2.5V)
– Support for Intel-style and Motorola-style interface signals
– Support for Burst Flash memory devices
– Flexibly programmable access parameters
– Programmable chip select lines
– Little-endian support
• Examples for memories that has to be supported
– Burst Flash:
– Spansion: S29CD016, S29CD032
– Spansion: S29CL032J1RFAM010 @3,3V
– ST: M58BW016, M58BW032
– ST: M58BW032GB B45ZA3T @3,3V
– Flash (for 16 bit muxed mode):
– http://www.spansion.com/products/Am29LV160B.html
– SRAM (for 16 bit muxed mode):
– http://www.idt.com/products/files/10372/71V016saautomotive.pdf
– http://213.174.55.51/zmd.biz/pdf/ UL62H1616A.pdf
– IDT 71V416YS15BEI
• Scalable external bus frequency
– Derived from LMB frequency (fCPU) divided by 1, 2, 3, or 4
– Maximum 75 MHz1)
• Data buffering supported
– Code prefetch buffer
– Read/write buffer
2.6
On-Chip Debug Support (OCDS)
The TC1197 contains resources for different kinds of “debugging”, covering needs from
software development to real-time-tuning. These resources are either embedded in
specific modules (e.g. breakpoint logic of the TriCore) or part of a central peripheral
(known as CERBERUS).
1) Maximum frequency of today available automotive Burst Flash devices.
Data Sheet
53
V1.1, 2009-05
TC1197
Introduction
2.6.1
On-Chip Debug Support
The classic software debug approach (start/stop, single-stepping) is supported by
several features labelled “OCDS Level 1”:
• Run/stop and single-step execution independently for TriCore and PCP.
• Means to request all kinds of reset without usage of sideband pins.
• Halt-after-Reset for repeatable debug sessions.
• Different Boot modes to use application software not yet programmed to the Flash.
• A total of four hardware breakpoints for the TriCore based on instruction address,
data address or combination of both.
• Unlimited number of software breakpoints (DEBUG instruction) for TriCore and PCP.
• Debug event generated by access to a specific address via the system bus.
• Tool access to all SFRs and internal memories independent of the Cores.
• Two central Break Switches to collect debug events from all modules (TriCore, PCP,
DMA, BCU, break input pins) and distribute them selectively to breakable modules
(TriCore, PCP, break output pins).
• Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals)
instead if breaking them as reaction to a debug event.
• Dedicated interrupt resources to handle debug events inside TriCore (breakpoint
trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing
Monitor programs.
• Access to all OCDS Level 1 resources also for TriCore and PCP themselves for
debug tools integrated into the application code.
• Triggered Transfer of data in response to a debug event; if target is programmed to
be a device interface simple variable tracing can be done.
• In depth performance analysis and profiling support given by the Emulation Device
through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit,
wait state, interrupt accepted).
2.6.2
Real Time Trace
For detailed tracing of the system’s behavior a pin-compatible Emulation Device will be
available.1)
2.6.3
Calibration Support
Two main use cases are catered for by resources in addition the OCDS Level 1
infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling:
• 8 KB SRAM for Overlay.
• Can be split into up to 16 blocks which can overlay independent regions of on-chip
Data Flash.
1) The OCDS L2 interface of AudoNG is not available.
Data Sheet
54
V1.1, 2009-05
TC1197
Introduction
• Changing the configuration is triggered by a single SFR access to maintain
consistency.
• Overlay configuration switch does not require the TriCore to be stopped or
suspended.
• Invalidation of the Data Cache (maintaining write-back data) can be done
concurrently with the same SFR.
• 256 KB additional Overlay RAM on Emulation Device.
• The 256 KB Trace memory of the Emulation Device can optionally be used for
Overlay also.
• A dedicated trigger SFR with 32 independent status bits is provided to centrally post
requests from application code to the host computer.
• The host is notified automatically when the trigger SFR is updated by the TriCore or
PCP. No polling via a system bus is required.
2.6.4
Tool Interfaces
Three options exist for the communication channel between Tools (e.g. Debugger,
Calibration Tool) and TC1197:
• Two wire DAP (Device Access Port) protocol for long connections or noisy
environments.
• Four (or five) wire JTAG (IEEE 1149.1) for standardized manufacturing tests.
• CAN (plus software linked into the application code) for low bandwidth deeply
embedded purposes.
• DAP and JTAG are clocked by the tool.
• Bit clock up to 40 MHz for JTAG, up to 80 MHz for DAP.
• Hot attach (i.e. physical disconnect/reconnect of the host connection without reset of
the TC1197) for all interfaces.
• Infineon standard DAS (Device Access Server) implementation for seamless,
transparent tool access over any supported interface.
• Lock mechanism to prevent unauthorized tool access to critical application code.
2.6.5
Self-Test Support
Some manufacturing tests can be invoked by the application (e.g. after power-on) if
needed:
• Hardware-accelerated checksum calculation (e.g. for Flash content).
• RAM tests optimized for the implemented architecture.
2.6.6
FAR Support
To efficiently locate and identify faults after integration of a TC1197 into a system special
functions are available:
• Boundary Scan (IEEE 1149.1) via JTAG and DAP.
Data Sheet
55
V1.1, 2009-05
TC1197
Introduction
• SSCM (Single Scan Chain Mode1)) for structural scan testing of the chip itself.
1) This function requires access to some device pins (e.g. TESTMODE) in addition to those needed for OCDS.
Data Sheet
56
V1.1, 2009-05
TC1197
Pinning
3
Pinning
3.1
TC1197 Pin Definition and Functions: PG-BGA-416-10
Figure 15 is showing the TC1197 Logic Symbol for the package variant:
PG-BGA-416-10.
Alternate Functions :
PORST
16
TESTMODE
ESR0
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
GPTA / HWCFG
General Control
16
16
16
16
16
12
8
GPTA / MLI0 / ERU / SSC1
GPTA / SSC0 / SSC1
ESR1
TRST
TCK / DAP0
GPTA
TDI / BRKIN/
BRKOUT
OCDS /
JTAG Control
ASC0 / ASC1 / MSC0 /
MSC1 / LVDS / MLI0
TDO /BRKOUT/
DAP2 / BRKIN
ASC0 / ASC1 / SSC1 / CAN /
ERU / ADC-Mux
TMS / DAP1
XTAL1
8
MLI1 / GPTA
XTAL2
VDD OSC
15
MSC0 / MSC1 / GPTA
SSC0
VDD OSC3
6
16
8
Oscillator
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
VSSOSC
/
TC1197
VSS
EBU
VDD PF
EBU
VDD PF3C3
16
16
16
9
11
13
3
GPTA / EBU
GPTA / EBU
EBU
VDD EBU
VDD P
VD D
Digital Circuitry
Power Supply
VD DFL3
VDD SBRAM
VSS
4
EBU
79
VSSAF
ADC
Analog Inputs
VSSMF
AN[43:0]
VFAGND
VFAR EF
VDD MF
VDD AF
FADC Analog
Power Supply
3
VAREFx
VAGN Dx
VD DM
3
ADC0 /ADC1
Analog Power Supply
9
VSSM
N.C.
TC1197_LogSym_416
Figure 15
TC1197 Logic Symbol for the package variant PG-BGA-416-10.
Data Sheet
57
V1.1, 2009-05
TC1197
Pinning
3.1.1
TC1197 PG-BGA-416-10 Package Variant Pin Configuration
Figure 16 shows the TC1197 pin configuration for the PG-BGA-416-10 package variant.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
B
A
VDDFL3
ESR1 ESR0
VDDP VSS
N.C. P2.9 P2.13 P2.15 P0.14 P0.5 P0.2 P0.1 P0.0 P3.14 P3.5 P3.1 P5.1 P5.2 P5.7 P5.12 P5.15
P2.6 P2.7 P2.10 P2.14 P0.9 P0.6 P0.4 P0.3 P3.15 P3.6 P3.3 P3.0 P5.0 P5.3 P5.6 P5.13 P5.14
P9.0 P9.3 P9.9
P9.1 P9.2 P9.10
N.C.
PO TEST
B
VDDFL3
VDDP VSS
VDD
MODE
RST
C
C
VDDP VSS
VDD
P2.5 P2.8 P2.11 P2.12 P0.12 P0.10 P0.8 P0.7 P3.7 P3.10 P3.9 P3.4 P3.2 P5.5 P5.4 P5.9 P5.10 P5.11 P9.6 P9.8 P9.11 N.C.
P9.13
P9.14
D
D
VDDP VSS
VDD
VDDP VSS
VDD
VDDP VSS VDD TDO
P2.4 P2.3 P2.2 P0.15 P0.13 P0.11
P6.12 P6.11 P6.6 P6.9
P3.8 P3.12 P3.13 P3.11
P5.8 P9.4 P9.5 P9.7 P9.12
VDD
OSC3
E
E
VDD TCK TDI
VSS
OSC
VDD
OSC
F
F
TRST TMS
P6.14 P6.10 P6.4 P6.8
XTAL XTAL
G
G
H
VDDPF VDDPF3
P6.15 P6.13 P6.7 P6.5
2
1
H
VDDFL3 VDD
VDDEBU VDDEBU VDDEBU VDDEBU
P11.3 P12.6 P12.7 P11.0
P8.1 P8.0
J
J
VSS
P8.4 P8.3 P8.2
P8.7 P8.5 P8.6
K
K
VDDP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P11.7 P11.4 P11.1 P11.2
P11.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P1.15 P1.14 P1.13 P1.11
P1.10 P1.9 P1.8 P1.5
P1.3 P1.7 P1.6 P1.4
P11.5 P11.6
11
P11.
10
M
N
M
N
VDDEBU
P11.9 P11.8
P11. P11. P11. P11.
13
14
15
12
P
P
VDD
P1.2 P1.1 P1.0 P1.12
VDD
P12.1 P12.2 P12.0
P12.3 P12.5 P12.4
P13.1 P13.3 P13.0
R
R
VDD
VSS
P7.1 P7.0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SBRAM
T
T
VSS
VDDEBU
P7.6 P7.5 P7.4
U
U
AN23 P7.7 P7.3 P7.2
AN22 AN21 AN19 AN16
P13.6 P13.9 P13.5 P13.2
P13.
V
V
VDD
P13.8 P13.4
13
P13.
P13.7
12
W
Y
W
Y
VDDM
VSS
AN20 AN17 AN13
AN18 AN14 AN10
P14.0
P13. P13.
VSSM
VDDEBU
P14.2
14
10
P13.
11
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
AN15 AN11 AN5 AN2
P14.3 P14.6 P14.1
P13.
15
VDD
AN12 AN9 AN3 AN7
P14.5 P14.4
P14.
VSS
VSS
VSS
VDDEBU
VAGND1
VDDAF
VDD
P10.5 VDDP
VDD
VDDEBU VSS
AN8 AN4 AN32 AN38 AN42
AN6 AN1 AN34 AN40 AN35
AN26 AN24
AN27 AN25
P4.4 P4.8 P4.12
N.C.
P14.9 P14.7
12
P14. P14.
VAREF1
VAREF2
P10.2 VDDP P15.5 P16.1 P15.3 P15.2 P15.1 P16.2
P15.
P4.0 P4.2 P4.5 P4.11 P4.15
N.C.
P14.8
P14. P14. P14.
15
11
VAREF0
VFAGND VDDMF
P10.4 P10.0
VDDP
P15.4 P15.7 P16.3
P15.0
N.C. N.C.
AN0 AN33 AN36 AN41
N.C. AN37 AN39 AN43
AN28 AN30
AN29 AN31
P4.1 P4.3 P4.7 P4.13
P4.6 P4.9 P4.10 P4.14
11
P15.8 P15.9
20 21
14
13
10
P15.
P16.0 P15.6
12
P15. P15. P15. P15.
VAGND0
5
VFAREF VSSMF
P10.3 P10.1
14 15
VDDP
16
N.C.
10
13
14
15
1
2
3
4
6
7
8
9
10
11
12
13
17
18
19
22
23
24
25
26
mca05584_97.vsd
Figure 16
TC1197 Pinning for PG-BGA-416-10 Package
Data Sheet
58
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package)
Symbol Ctrl. Type Function
Port 0
A9
P0.0
I/O0 A1/
Port 0 General Purpose I/O Line 0
PU
HWCFG0
OUT56
OUT56
OUT80
P0.1
I
Hardware Configuration Input 0
OUT56 Line of GPTA0
O1
O2
OUT56 Line of GPTA1
O3
OUT80 Line of LTCA2
A8
A7
B8
I/O0 A1/
Port 0 General Purpose I/O Line 1
Hardware Configuration Input 1
OUT57 Line of GPTA0
PU
HWCFG1
OUT57
OUT57
OUT81
P0.2
I
O1
O2
OUT57 Line of GPTA1
O3
OUT81 Line of LTCA2
I/O0 A1/
Port 0 General Purpose I/O Line 2
Hardware Configuration Input 2
OUT58 Line of GPTA0
PU
HWCFG2
OUT58
OUT58
OUT82
P0.3
I
O1
O2
OUT58 Line of GPTA1
O3
OUT82 Line of LTCA2
I/O0 A1/
Port 0 General Purpose I/O Line 3
Hardware Configuration Input 3
OUT59 Line of GPTA0
PU
HWCFG3
OUT59
OUT59
OUT83
I
O1
O2
O3
OUT59 Line of GPTA1
OUT83 Line of LTCA2
Data Sheet
59
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
B7
P0.4
I/O0 A1/
Port 0 General Purpose I/O Line 4
PU
HWCFG4
OUT60
OUT60
OUT84
P0.5
I
Hardware Configuration Input 4
OUT60 Line of GPTA0
OUT60 Line of GPTA1
OUT84 Line of LTCA2
Port 0 General Purpose I/O Line 5
Hardware Configuration Input 5
OUT61 Line of GPTA0
OUT61 Line of GPTA1
OUT85 Line of LTCA2
Port 0 General Purpose I/O Line 6
Hardware Configuration Input 6
OUT62 Line of GPTA0
OUT62 Line of GPTA1
OUT86 Line of LTCA2
Port 0 General Purpose I/O Line 7
Hardware Configuration Input 7
OUT63 Line of GPTA0
OUT63 Line of GPTA1
OUT87 Line of LTCA2
Port 0 General Purpose I/O Line 8
-
O1
O2
O3
A6
B6
C8
C7
I/O0 A1/
PU
HWCFG5
OUT61
OUT61
OUT85
P0.6
I
O1
O2
O3
I/O0 A1/
PU
HWCFG6
OUT62
OUT62
OUT86
P0.7
I
O1
O2
O3
I/O0 A1/
PU
HWCFG7
OUT63
OUT63
OUT87
P0.8
I
O1
O2
O3
I/O0 A1/
PU
Reserved
Reserved
Reserved
O1
O2
O3
-
-
Data Sheet
60
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
B5
P0.9
I/O0 A1/
Port 0 General Purpose I/O Line 9
PU
Reserved
Reserved
Reserved
Reserved
P0.10
I
-
O1
-
O2
-
O3
-
C6
D6
C5
D5
I/O0 A2/
Port 0 General Purpose I/O Line 10
PU
Reserved
Reserved
Reserved
P0.11
O1
-
O2
-
O3
-
I/O0 A2/
Port 0 General Purpose I/O Line 11
PU
Reserved
Reserved
Reserved
P0.12
O1
-
O2
-
O3
-
I/O0 A2/
Port 0 General Purpose I/O Line 12
PU
Reserved
Reserved
Reserved
P0.13
O1
-
O2
-
O3
-
I/O0 A1/
Port 0 General Purpose I/O Line 13
PU
Reserved
Reserved
Reserved
Reserved
P0.14
I
-
O1
-
O2
-
O3
-
A5
I/O0 A2/
Port 0 General Purpose I/O Line 14
PU
Reserved
Reserved
Reserved
O1
-
-
-
O2
O3
Data Sheet
61
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
D4
P0.15
I/O0 A1/
Port 0 General Purpose I/O Line 15
PU
Reserved
Reserved
Reserved
O1
-
-
-
O2
O3
Port 1
P3
P1.0
I/O0 A2/
Port 1 General Purpose I/O Line 0
PU
REQ0
I
External trigger Input 0
EXTCLK1
Reserved
Reserved
P1.1
O1
External Clock Output 1
O2
-
O3
-
P2
P1
N1
I/O0 A1/
Port 1 General Purpose I/O Line 1
PU
REQ1
I
External trigger Input 1
Reserved
Reserved
Reserved
P1.2
O1
-
O2
-
O3
-
I/O0 A1/
Port 1 General Purpose I/O Line 2
PU
REQ2
I
External trigger Input 2
Reserved
Reserved
Reserved
P1.3
O1
-
O2
-
O3
-
I/O0 A1/
Port 1 General Purpose I/O Line 3
External trigger Input 3
PU
REQ3
I
TREADY0B
Reserved
Reserved
Reserved
I
MLI0 Transmit Channel ready Input B
O1
O2
O3
-
-
-
Data Sheet
62
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
N4
P1.4
I/O0 A2/
Port 1 General Purpose I/O Line 4
MLI0 Transmit Channel Clock Output
PU
TCLK0
O1
Reserved
Reserved
P1.5
O2
-
O3
-
M4
I/O0 A1/
Port 1 General Purpose I/O Line 35
MLI0 Transmit Channel ready Input A
-
PU
TREADY0A
Reserved
Reserved
Reserved
P1.6
I
O1
O2
-
O3
-
N3
N2
M3
I/O0 A2/
Port 1 General Purpose I/O Line 6
MLI0 Transmit Channel valid Output A
Slave Select Output Line 10
-
PU
TVALID0A
SLSO10
Reserved
P1.7
O1
O2
O3
I/O0 A2/
Port 1 General Purpose I/O Line 7
MLI0 Transmit Channel Data Output
-
PU
TData0
Reserved
Reserved
P1.8
O1
O2
O3
-
I/O0 A1/
Port 1 General Purpose I/O Line 8
MLI0 Receive Channel Clock Input A
OUT64 Line of GPTA0
OUT64 Line of GPTA1
OUT88 Line of LTCA2
Port 1 General Purpose I/O Line 9
MLI0 Receive Channel ready Output A
Slave Select Output Line 11
OUT65 Line of GPTA0
PU
RCLK0A
OUT64
OUT64
OUT88
P1.9
I
O1
O2
O3
M2
I/O0 A2/
PU
RREADY0A O1
SLSO11
OUT65
O2
O3
Data Sheet
63
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
M1
P1.10
I/O0 A1/
Port 1 General Purpose I/O Line 10
PU
RVALID0A
OUT66
OUT66
OUT90
P1.11
I
MLI0 Receive Channel valid Input A
OUT66 Line of GPTA0
O1
O2
OUT66 Line of GPTA1
O3
OUT90 Line of LTCA2
L4
I/O0 A1/
Port 1 General Purpose I/O Line 11
MLI0 Receive Channel Data Input A
OUT67 Line of GPTA0
PU
RData0A
OUT67
OUT67
OUT91
P1.12
I
O1
O2
OUT67 Line of GPTA1
O3
OUT91 Line of LTCA2
P4
L3
I/O0 A2/
Port 1 General Purpose I/O Line 12
External Clock Output 0
PU
EXTCLK0
OUT68
OUT68
P1.13
O1
O2
OUT68 Line of GPTA0
O3
OUT68 Line of GPTA1
I/O0 A1/
Port 1 General Purpose I/O Line 13
MLI0 Receive Channel Clock Input B
OUT69 Line of GPTA0
PU
RCLK0B
OUT69
OUT69
OUT93
P1.14
I
O1
O2
OUT69 Line of GPTA1
O3
OUT93 Line of LTCA2
L2
I/O0 A1/
Port 1 General Purpose I/O Line 14
MLI0 Receive Channel valid Input B
OUT70 Line of GPTA0
PU
RVALID0B
OUT70
OUT70
OUT94
I
O1
O2
O3
OUT70 Line of GPTA1
OUT94 Line of LTCA2
Data Sheet
64
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
L1
P1.15
I/O0 A1/
Port 1 General Purpose I/O Line 15
PU
RData0B
OUT70
OUT70
OUT95
I
MLI0 Receive Channel Data Input B
OUT71 Line of GPTA0
O1
O2
O3
OUT71 Line of GPTA1
OUT95 Line of LTCA2
Port 2
D3
P2.2
I/O0 A2/
Port 2 General Purpose I/O Line 2
Slave Select Output Line 2
PU
SLSO02
SLSO12
O1
O2
O3
Slave Select Output Line 12
SLSO02
AND
Slave Select Output Line 2 AND Slave Select
Output Line 12
SLSO12
D2
D1
P2.3
I/O0 A2/
Port 2 General Purpose I/O Line 3
Slave Select Output Line 3
PU
SLSO03
SLSO13
O1
O2
O3
Slave Select Output Line 13
SLSO03
AND
SLSO13
Slave Select Output Line 3 AND Slave Select
Output Line 13
P2.4
I/O0 A2/
Port 2 General Purpose I/O Line 4
Slave Select Output Line 4
PU
SLSO04
SLSO14
O1
O2
O3
Slave Select Output Line 14
SLSO04
AND
Slave Select Output Line 4 AND Slave Select
Output Line 14
SLSO14
Data Sheet
65
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
C1
P2.5
I/O0 A2/
Port 2 General Purpose I/O Line 5
PU
SLSO05
SLSO15
O1
Slave Select Output Line 5
Slave Select Output Line 15
O2
O3
SLSO05
AND
Slave Select Output Line 5 AND Slave Select
Output Line 15
SLSO15
B1
B2
C2
P2.6
I/O0 A2/
Port 2 General Purpose I/O Line 6
Slave Select Output Line 6
PU
SLSO06
SLSO16
O1
O2
O3
Slave Select Output Line 16
SLSO06
AND
SLSO16
Slave Select Output Line 6 AND Slave Select
Output Line 16
P2.7
I/O0 A2/
Port 2 General Purpose I/O Line 7
Slave Select Output Line 7
PU
SLSO07
SLSO17
O1
O2
O3
Slave Select Output Line 17
SLSO07
AND
SLSO17
Slave Select Output Line 7AND Slave Select
Output Line 17
P2.8
IN0
I/O0 A1/
Port 2 General Purpose I/O Line 8
IN0 Line of GPTA0
PU
I
IN0
I
IN0 Line of GPTA1
IN0
I
IN0 Line of LTCA2
OUT0
OUT0
OUT0
O1
O2
O3
OUT0 Line of GPTA0
OUT0 Line of GPTA1
OUT0 Line of LTCA2
Data Sheet
66
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
A2
P2.9
IN1
I/O0 A1/
Port 2 General Purpose I/O Line 9
PU
I
IN1 Line of GPTA0
IN1
I
IN1 Line of GPTA1
IN1
I
IN1 Line of LTCA2
OUT1
OUT1
OUT1
P2.10
IN2
O1
OUT1 Line of GPTA0
OUT1 Line of GPTA1
OUT1 Line of LTCA2
Port 2 General Purpose I/O Line 10
IN2 Line of GPTA0
O2
O3
B3
I/O0 A1/
PU
I
IN2
I
IN2 Line of GPTA1
IN2
I
IN2 Line of LTCA2
OUT2
OUT2
OUT2
P2.11
IN3
O1
OUT2 Line of GPTA0
OUT2 Line of GPTA1
OUT2 Line of LTCA2
Port 2 General Purpose I/O Line 11
IN3 Line of GPTA0
O2
O3
C3
I/O0 A1/
PU
I
IN3
I
IN3 Line of GPTA1
IN3
I
IN3 Line of LTCA2
OUT3
OUT3
OUT3
O1
O2
O3
OUT3 Line of GPTA0
OUT3 Line of GPTA1
OUT3 Line of LTCA2
Data Sheet
67
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
C4
P2.12
IN4
I/O0 A1/
Port 2 General Purpose I/O Line 12
PU
I
IN4 Line of GPTA0
IN4
I
IN4 Line of GPTA1
IN4
I
IN4 Line of LTCA2
OUT4
OUT4
OUT4
P2.13
IN5
O1
OUT4 Line of GPTA0
OUT4 Line of GPTA1
OUT4 Line of LTCA2
Port 2 General Purpose I/O Line 13
IN5 Line of GPTA0
O2
O3
A3
I/O0 A1/
PU
I
IN5
I
IN5 Line of GPTA1
IN5
I
IN5 Line of LTCA2
OUT5
OUT5
OUT5
P2.14
IN6
O1
OUT5 Line of GPTA0
OUT5 Line of GPTA1
OUT5 Line of LTCA2
Port 2 General Purpose I/O Line 14
IN6 Line of GPTA0
O2
O3
B4
I/O0 A1/
PU
I
IN6
I
IN6 Line of GPTA1
IN6
I
IN6 Line of LTCA2
OUT6
OUT6
OUT6
O1
O2
O3
OUT6 Line of GPTA0
OUT6 Line of GPTA1
OUT6 Line of LTCA2
Data Sheet
68
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
A4
P2.15
IN7
I/O0 A1/
Port 2 General Purpose I/O Line 15
PU
I
IN7 Line of GPTA0
IN7 Line of GPTA1
IN7 Line of LTCA2
OUT7 Line of GPTA0
OUT7 Line of GPTA1
OUT7 Line of LTCA2
IN7
I
IN7
I
OUT7
OUT7
OUT7
O1
O2
O3
Port 3
B12
P3.0
IN8
I/O0 A1/
Port 3 General Purpose I/O Line 0
IN8 Line of GPTA0
PU
I
IN8
I
IN8 Line of GPTA1
IN8
I
IN8 Line of LTCA2
OUT8
OUT8
OUT8
P3.1
IN9
O1
OUT8 Line of GPTA0
OUT8 Line of GPTA1
OUT8 Line of LTCA2
Port 3 General Purpose I/O Line 1
IN9 Line of GPTA0
O2
O3
A12
I/O0 A1/
PU
I
IN9
I
IN9 Line of GPTA1
IN9
I
IN9 Line of LTCA2
OUT9
OUT9
OUT9
O1
O2
O3
OUT9 Line of GPTA0
OUT9 Line of GPTA1
OUT9 Line of LTCA2
Data Sheet
69
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
C13
P3.2
I/O0 A1/
Port 3 General Purpose I/O Line 2
PU
IN10
I
IN10 Line of GPTA0
IN10
I
IN10 Line of GPTA1
IN10
I
IN10 Line of LTCA2
OUT10
OUT10
OUT10
P3.3
O1
OUT10 Line of GPTA0
OUT10 Line of GPTA1
OUT10 Line of LTCA2
Port 3 General Purpose I/O Line 3
IN11 Line of GPTA0
O2
O3
B11
I/O0 A1/
PU
IN11
I
IN11
I
IN11 Line of GPTA1
IN11
I
IN11 Line of LTCA2
OUT11
OUT11
OUT11
P3.4
O1
OUT11 Line of GPTA0
OUT11 Line of GPTA1
OUT11 Line of LTCA2
Port 3 General Purpose I/O Line 4
IN12 Line of GPTA0
O2
O3
C12
I/O0 A1/
PU
IN12
I
IN12
I
IN12 Line of GPTA1
IN12
I
IN12 Line of LTCA2
OUT12
OUT12
OUT12
O1
O2
O3
OUT12 Line of GPTA0
OUT12 Line of GPTA1
OUT12 Line of LTCA2
Data Sheet
70
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
A11
P3.5
I/O0 A1/
Port 3 General Purpose I/O Line 5
PU
IN13
I
IN13 Line of GPTA0
IN13
I
IN13 Line of GPTA1
IN13
I
IN13 Line of LTCA2
OUT13
OUT13
OUT13
P3.6
O1
OUT13 Line of GPTA0
OUT13 Line of GPTA1
OUT13 Line of LTCA2
Port 3 General Purpose I/O Line 6
IN14 Line of GPTA0
O2
O3
B10
I/O0 A1/
PU
IN14
I
IN14
I
IN14 Line of GPTA1
IN14
I
IN14 Line of LTCA2
OUT14
OUT14
OUT14
P3.7
O1
OUT14 Line of GPTA0
OUT14 Line of GPTA1
OUT14 Line of LTCA2
Port 3 General Purpose I/O Line 7
IN15 Line of GPTA0
O2
O3
C9
I/O0 A1/
PU
IN15
I
IN15
I
IN15 Line of GPTA1
IN15
I
IN15 Line of LTCA2
OUT15
OUT15
OUT15
O1
O2
O3
OUT15 Line of GPTA0
OUT15 Line of GPTA1
OUT15 Line of LTCA2
Data Sheet
71
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
D10
P3.8
I/O0 A1/
Port 3 General Purpose I/O Line 8
PU
IN16
I
IN16 Line of GPTA0
IN16
I
IN16 Line of GPTA1
IN16
I
IN16 Line of LTCA2
OUT16
OUT16
OUT16
P3.9
O1
OUT16 Line of GPTA0
OUT16 Line of GPTA1
OUT16 Line of LTCA2
Port 3 General Purpose I/O Line 9
IN17 Line of GPTA0
O2
O3
C11
I/O0 A1/
PU
IN17
I
IN17
I
IN17 Line of GPTA1
IN17
I
IN17 Line of LTCA2
OUT17
OUT17
OUT17
P3.10
IN18
O1
OUT17 Line of GPTA0
OUT17 Line of GPTA1
OUT17 Line of LTCA2
Port 3 General Purpose I/O Line 10
IN18 Line of GPTA0
O2
O3
C10
I/O0 A1/
PU
I
IN18
I
IN18 Line of GPTA1
IN18
I
IN18 Line of LTCA2
OUT18
OUT18
OUT18
O1
O2
O3
OUT18 Line of GPTA0
OUT18 Line of GPTA1
OUT18 Line of LTCA2
Data Sheet
72
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
D13
P3.11
IN19
I/O0 A1/
Port 3 General Purpose I/O Line 11
PU
I
IN19 Line of GPTA0
IN19
I
IN19 Line of GPTA1
IN19
I
IN19 Line of LTCA2
OUT19
OUT19
OUT19
P3.12
IN20
O1
OUT19 Line of GPTA0
OUT19 Line of GPTA1
OUT19 Line of LTCA2
Port 3 General Purpose I/O Line 12
IN20 Line of GPTA0
O2
O3
D11
I/O0 A1/
PU
I
IN20
I
IN20 Line of GPTA1
IN20
I
IN20 Line of LTCA2
OUT20
OUT20
OUT20
P3.13
IN21
O1
OUT20 Line of GPTA0
OUT20 Line of GPTA1
OUT20 Line of LTCA2
Port 3 General Purpose I/O Line 13
IN21 Line of GPTA0
O2
O3
D12
I/O0 A1/
PU
I
IN21
I
IN21 Line of GPTA1
IN21
I
IN21 Line of LTCA2
OUT21
OUT21
OUT21
O1
O2
O3
OUT21 Line of GPTA0
OUT21 Line of GPTA1
OUT21 Line of LTCA2
Data Sheet
73
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
A10
P3.14
IN22
I/O0 A1/
Port 3 General Purpose I/O Line 14
PU
I
IN22 Line of GPTA0
IN22
I
IN22 Line of GPTA1
IN22
I
IN22 Line of LTCA2
OUT22
OUT22
OUT22
P3.15
IN23
O1
OUT22 Line of GPTA0
OUT22 Line of GPTA1
OUT22 Line of LTCA2
Port 3 General Purpose I/O Line 15
IN23 Line of GPTA0
O2
O3
B9
I/O0 A1/
PU
I
IN23
I
IN23 Line of GPTA1
IN23
I
IN23 Line of LTCA2
OUT23
OUT23
OUT23
O1
O2
O3
OUT23 Line of GPTA0
OUT23 Line of GPTA1
OUT23 Line of LTCA2
Port 4
AD10 P4.0
IN24
I/O0 A2/
Port 4 General Purpose I/O Line 0
IN24 Line of GPTA0
PU
I
IN24
I
IN24 Line of GPTA1
IN24
I
IN24 Line of LTCA2
OUT24
O1
O2
O3
OUT24 Line of GPTA0
OUT24 Line of GPTA1
OUT24 Line of LTCA2
OUT24
OUT24
Data Sheet
74
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AE10 P4.1
IN25
I/O0 A2/
Port 4 General Purpose I/O Line 1
PU
I
IN25 Line of GPTA0
IN25
I
IN25 Line of GPTA1
IN25
I
IN25 Line of LTCA2
OUT25
O1
OUT25 Line of GPTA0
OUT25 Line of GPTA1
OUT25 Line of LTCA2
Port 4 General Purpose I/O Line 2
IN26 Line of GPTA0
OUT25
OUT25
O2
O3
AD11 P4.2
I/O0 A2/
PU
IN26
I
IN26
I
IN26 Line of GPTA1
IN26
I
IN26 Line of LTCA2
OUT26
OUT26
OUT26
O1
OUT26 Line of GPTA0
OUT26 Line of GPTA1
OUT26 Line of LTCA2
Port 4 General Purpose I/O Line 3
IN27 Line of GPTA0
O2
O3
AE11 P4.3
I/O0 A2/
PU
IN27
I
IN27
I
IN27 Line of GPTA1
IN27
I
IN27 Line of LTCA2
OUT27
OUT27
OUT27
O1
O2
O3
OUT27 Line of GPTA0
OUT27 Line of GPTA1
OUT27 Line of LTCA2
Data Sheet
75
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AC12 P4.4
IN28
I/O0 A2/
Port 4 General Purpose I/O Line 4
PU
I
IN28 Line of GPTA0
IN28
I
IN28 Line of GPTA1
IN28
I
IN28 Line of LTCA2
OUT28
O1
OUT28 Line of GPTA0
OUT28 Line of GPTA1
OUT28 Line of LTCA2
Port 4 General Purpose I/O Line 5
IN29 Line of GPTA0
OUT28
OUT28
O2
O3
AD12 P4.5
I/O0 A2/
PU
IN29
I
IN29
I
IN29 Line of GPTA1
IN29
I
IN29 Line of LTCA2
OUT29
OUT29
OUT29
O1
OUT29 Line of GPTA0
OUT29 Line of GPTA1
OUT29 Line of LTCA2
Port 4 General Purpose I/O Line 6
IN30 Line of GPTA0
O2
O3
AF10 P4.6
I/O0 A2/
PU
IN30
I
IN30
I
IN30 Line of GPTA1
IN30
I
IN30 Line of LTCA2
OUT30
OUT30
OUT30
O1
O2
O3
OUT30 Line of GPTA0
OUT30 Line of GPTA1
OUT30 Line of LTCA2
Data Sheet
76
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AE12 P4.7
IN31
I/O0 A2/
Port 4 General Purpose I/O Line 7
PU
I
IN31 Line of GPTA0
IN31
I
IN31 Line of GPTA1
IN31
I
IN31Line of LTCA2
OUT31
O1
OUT31 Line of GPTA0
OUT31 Line of GPTA1
OUT31 Line of LTCA2
Port 4 General Purpose I/O Line 8
IN32 Line of GPTA0
OUT31
OUT31
O2
O3
AC13 P4.8
I/O0 A1/
PU
IN32
I
IN32
I
IN32 Line of GPTA1
OUT32
OUT32
OUT0
O1
OUT32 Line of GPTA0
OUT32 Line of GPTA1
OUT0 Line of LTCA2
Port 4 General Purpose I/O Line 9
IN33 Line of GPTA0
O2
O3
AF11 P4.9
I/O0 A1/
PU
IN33
IN33
I
I
IN33 Line of GPTA1
OUT33
OUT33
OUT1
O1
OUT33 Line of GPTA0
OUT33 Line of GPTA1
OUT1 Line of LTCA2
Port 4 General Purpose I/O Line 10
IN34 Line of GPTA0
O2
O3
AF12 P4.10
IN34
I/O0 A1/
PU
I
IN34
I
IN34 Line of GPTA1
OUT34
OUT34
OUT2
O1
O2
O3
OUT34 Line of GPTA0
OUT34 Line of GPTA1
OUT2 Line of LTCA2
Data Sheet
77
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AD13 P4.11
IN35
I/O0 A1/
Port 4 General Purpose I/O Line 11
PU
I
IN35 Line of GPTA0
IN35
I
IN35 Line of GPTA1
OUT35
OUT35
OUT3
O1
OUT35 Line of GPTA0
OUT35 Line of GPTA1
OUT3 Line of LTCA2
Port 4 General Purpose I/O Line 12
IN36 Line of GPTA0
O2
O3
AC14 P4.12
IN36
I/O0 A1/
PU
I
IN36
I
IN36 Line of GPTA1
OUT36
OUT36
OUT4
O1
OUT36 Line of GPTA0
OUT36 Line of GPTA1
OUT4 Line of LTCA2
Port 4 General Purpose I/O Line 13
IN37 Line of GPTA0
O2
O3
AE13 P4.13
IN37
I/O0 A1/
PU
I
IN37
I
IN37 Line of GPTA1
OUT37
OUT37
OUT5
O1
OUT37 Line of GPTA0
OUT37 Line of GPTA1
OUT5 Line of LTCA2
Port 4 General Purpose I/O Line 14
IN38 Line of GPTA0
O2
O3
AF13 P4.14
IN38
I/O0 A1/
PU
I
IN38
I
IN38 Line of GPTA1
OUT38
OUT38
OUT6
O1
O2
O3
OUT38 Line of GPTA0
OUT38 Line of GPTA1
OUT6 Line of LTCA2
Data Sheet
78
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AD14 P4.15
IN39
I/O0 A1/
Port 4 General Purpose I/O Line 15
PU
I
IN39 Line of GPTA0
IN39 Line of GPTA1
OUT39 Line of GPTA0
OUT39 Line of GPTA1
OUT7 Line of LTCA2
IN39
I
OUT39
OUT39
OUT7
O1
O2
O3
Port 5
B13
P5.0
I/O0 A2/
Port 5 General Purpose I/O Line 0
ASC0 Receiver Input/Output A
ASC0 Receiver Input/Output A
OUT72 Line of GPTA0
PU
RXD0A
RXD0A
OUT72
OUT72
P5.1
I
O1
O2
O3
OUT72 Line of GPTA1
A13
A14
I/O0 A2/
Port 5 General Purpose I/O Line 1
ASC0 Transmitter Output A
OUT73 Line of GPTA0
PU
TXD0
O1
OUT73
OUT73
P5.2
O2
O3
OUT73 Line of GPTA1
I/O0 A2/
Port 5 General Purpose I/O Line 2
ASC1 Receiver Input/Output A
ASC1 Receiver Input/Output A
OUT74 Line of GPTA0
PU
RXD1A
RXD1A
OUT74
OUT74
P5.3
I
O1
O2
O3
OUT74 Line of GPTA1
B14
I/O0 A2/
Port 5 General Purpose I/O Line 3
ASC1 Transmitter Output A
OUT75 Line of GPTA0
PU
TXD1
O1
OUT75
OUT75
O2
O3
OUT75 Line of GPTA1
Data Sheet
79
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
C15
P5.4
I/O0 A2/
Port 5 General Purpose I/O Line 4
MSC0 Device Select Output 0
PU
EN00
O1
RREADY0B O2
MLI0 Receive Channel ready Output B
OUT76 Line of GPTA0
OUT76
P5.5
O3
C14
I/O0 A2/
Port 5 General Purpose I/O Line 5
MSC0 serial Data Input
PU
SDI0
I
OUT77
OUT77
OUT101
P5.6
O1
OUT77 Line of GPTA0
O2
OUT77 Line of GPTA1
O3
OUT101 Line of LTCA2
B15
A15
I/O0 A2/
Port 5 General Purpose I/O Line 6
MSC1 Device Select Output 0
MLI0 Transmit Channel valid Output B
OUT78 Line of GPTA0
PU
EN10
O1
TVALID0B
OUT78
P5.7
O2
O3
I/O0 A2/
Port 5 General Purpose I/O Line 7
MSC1 serial Data Input
PU
SDI1
I
OUT79
OUT79
OUT103
P5.8
O1
OUT79 Line of GPTA0
O2
OUT79 Line of GPTA1
O3
OUT103 Line of LTCA2
D17
I/O0 F/
Port 5 General Purpose I/O Line 8
PU
SON0
O1
MSC0 Differential Driver serial Data Output
Negative
OUT80
OUT80
O2
O3
OUT80 Line of GPTA0
OUT 80 Line of GPTA1
Data Sheet
80
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
I/O0 F/ Port 5 General Purpose I/O Line 9
C16
P5.9
PU
SOP0A
O1
MSC0 Differential Driver serial Data Output
Positive A
OUT81
OUT81
P5.10
O2
OUT81 Line of GPTA0
O3
OUT81 Line of GPTA1
C17
C18
A16
B16
I/O0 F/
Port 5 General Purpose I/O Line 10
PU
FCLN0
O1
MSC0 Differential Driver Clock Output
Negative
OUT82
OUT82
P5.11
O2
OUT82 Line of GPTA0
O3
OUT82 Line of GPTA1
I/O0 F/
Port 5 General Purpose I/O Line 11
PU
FCLP0A
O1
MSC0 Differential Driver Clock Output
Positive A
OUT83
OUT83
P5.12
O2
OUT83 Line of GPTA0
O3
OUT83 Line of GPTA1
I/O0 F/
Port 5 General Purpose I/O Line 12
PU
SON1
O1
MSC1 Differential Driver serial Data
OutputNegative
OUT84
OUT84
P5.13
O2
OUT84 Line of GPTA0
O3
OUT84 Line of GPTA1
I/O0 F/
Port 5 General Purpose I/O Line 13
PU
SOP1A
O1
MSC1 Differential Driver serial Data Output
Positive A
OUT85
OUT85
O2
O3
OUT85 Line of GPTA0
OUT85 Line of GPTA1
Data Sheet
81
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
I/O0 F/ Port 5 General Purpose I/O Line 14
MSC1 Differential Driver Clock Output
B17
P5.14
PU
FCLN1
O1
Negative
OUT86
OUT86
P5.15
O2
OUT86 Line of GPTA0
OUT86 Line of GPTA1
Port 5 General Purpose I/O Line 15
O3
A17
I/O0 F/
PU
FCLNP1A
O1
MSC1 Differential Driver Clock Output
Positive A
OUT87
OUT87
O2
O3
OUT87 Line of GPTA0
OUT87 Line of GPTA1
Port 6
F3
P6.4
I/O0 A2/
Port 6 General Purpose I/O Line 4
PU
MTSR1
MTSR1
I
SSC1 Slave Receive Input (Slave Mode)
O1
SSC1 Master Transmit Output (Master
Mode)
Reserved
Reserved
P6.5
O2
-
O3
-
G4
E3
I/O0 A2/
Port 6 General Purpose I/O Line 5
PU
MRST1
MRST1
Reserved
Reserved
P6.6
I
SSC1 Master Receive Input (Master Mode)
O1
SSC1 Slave Transmit Output (Slave Mode)
O2
-
O3
-
I/O0 A2/
Port 6 General Purpose I/O Line 6
PU
SCLK1
I
SSC1 Clock Input/Output
SCLK1
O1
O2
O3
SSC1 Clock Input/Output
Reserved
Reserved
-
-
Data Sheet
82
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
G3
P6.7
I/O0 A2/
Port 6 General Purpose I/O Line 7
PU
SLSI11
Reserved
Reserved
Reserved
P6.8
I
SSC1 Slave Select Input
O1
-
O2
-
O3
-
F4
I/O0 A2/
Port 6 General Purpose I/O Line 8
PU
RXDCAN0
I
CAN Node 0 Receiver Input 0
CAN Node 3 Receiver Input 1
RXD0B
Reserved
RXD0B
Reserved
P6.9
I
ASC0 Receiver Input/Output B
O1
-
O2
ASC0 Receiver Input/Output B
-
O3
E4
F2
I/O0 A2/
Port 6 General Purpose I/O Line 9
CAN Node 0 Transmitter Output
ASC0 Transmitter Output B
-
PU
TXDCAN0
TXD0
O1
O2
Reserved
P6.10
O3
I/O0 A2/
Port 6 General Purpose I/O Line 10
PU
RXDCAN1
I
CAN Node 1 Receiver Input 0
CAN Node 0 Receiver Input 1
RXD1B
I
ASC1 Receiver Input/Output B
Reserved
RXD1B
O1
O2
O3
-
ASC1 Receiver Input/Output B
-
Reserved
Data Sheet
83
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
E2
P6.11
I/O0 A2/
Port 6 General Purpose I/O Line 11
PU
TXDCAN1
TXD1
O1
CAN Node 1 Transmitter Output
ASC1 Transmitter Output B
-
O2
Reserved
P6.12
O3
E1
I/O0 A1/
Port 6 General Purpose I/O Line 12
PU
RXDCAN2
I
CAN Node 2 Receiver Input 0
CAN Node 1 Receiver Input 1
Reserved
Reserved
Reserved
Reserved
P6.13
I
-
O1
-
O2
-
O3
-
G2
F1
I/O0 A2/
Port 6 General Purpose I/O Line 13
PU
TXDCAN2
Reserved
Reserved
P6.14
O1
CAN Node 2 Transmitter Output
O2
-
O3
-
I/O0 A1/
Port 6 General Purpose I/O Line 14
PU
RXDCAN3
I
CAN Node 3 Receiver Input 0
CAN Node 2 Receiver Input 1
Reserved
Reserved
Reserved
Reserved
P6.15
I
-
O1
-
O2
-
O3
-
G1
I/O0 A2/
Port 6 General Purpose I/O Line 15
PU
TXDCAN3
Reserved
Reserved
O1
CAN Node 3 Transmitter Output
O2
O3
-
-
Data Sheet
84
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
Port 7
R3
P7.0
I/O0 A1/
Port 7 General Purpose I/O Line 0
External trigger Input 4
PU
REQ4
I
AD2EMUX0 O1
ADC2 external multiplexer Control Output 2
Reserved
Reserved
P7.1
O2
-
O3
-
R2
I/O0 A1/
Port 7 General Purpose I/O Line 1
PU
REQ5
I
External trigger Input 5
AD0EMUX2 O1
ADC0 external multiplexer Control Output 2
Reserved
Reserved
P7.2
O2
O3
-
-
U4
U3
T3
I/O0 A1/
PU
Port 7 General Purpose I/O Line 2
AD0EMUX0 O1
ADC0 external multiplexer Control Output 0
Reserved
Reserved
P7.3
O2
O3
-
-
I/O0 A1/
PU
Port 7 General Purpose I/O Line 3
AD0EMUX1 O1
ADC0 external multiplexer Control Output 1
Reserved
Reserved
P7.4
O2
-
O3
-
I/O0 A1/
Port 7 General Purpose I/O Line 4
PU
REQ6
I
External trigger Input 6
AD2EMUX0 O1
ADC2 external multiplexer Control Output 0
Reserved
Reserved
O2
O3
-
-
Data Sheet
85
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
T2
P7.5
I/O0 A1/
Port 7 General Purpose I/O Line 5
External trigger Input 7
PU
REQ7
I
AD2EMUX1 O1
ADC2 external multiplexer Control Output 1
Reserved
Reserved
P7.6
O2
O3
-
-
T1
U2
I/O0 A1/
PU
Port 7 General Purpose I/O Line 6
AD1EMUX0 O1
ADC1 external multiplexer Control Output 0
Reserved
Reserved
P7.7
O2
O3
-
-
I/O0 A1/
PU
Port 7 General Purpose I/O Line 7
AD1EMUX1 O1
ADC1 external multiplexer Control Output 1
Reserved
Reserved
O2
O3
-
-
Port 8
H2
P8.0
I/O0 A2/
Port 8 General Purpose I/O Line 0
I/O Line of GPTA0
PU
IN40
I
IN40
I
I/O Line of GPTA1
OUT40
OUT40
TCLK1
O1
O2
O3
I/O Line of GPTA0
I/O Line of GPTA1
MLI1 Transmit Channel Clock Output
Data Sheet
86
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
H1
P8.1
I/O0 A1/
Port 8 General Purpose I/O Line 1
PU
IN41
I
I/O Line of GPTA0
I/O Line of GPTA1
IN41
I
TREADY1A
OUT41
OUT41
Reserved
P8.2
I
MLI1 Transmit Channel ready Input A
I/O Line of GPTA0
O1
O2
I/O Line of GPTA1
O3
-
J3
J2
J1
I/O0 A2/
Port 8 General Purpose I/O Line 2
I/O Line of GPTA0
PU
IN42
I
IN42
I
I/O Line of GPTA1
OUT42
OUT42
TVALID1A
P8.3
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MLI1 Transmit Channel valid Output A
Port 8 General Purpose I/O Line 3
I/O Line of GPTA0
I/O0 A2/
PU
IN43
I
IN43
I
I/O Line of GPTA1
OUT43
OUT43
TData1
P8.4
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MLI1 Transmit Channel Data Output A
Port 8 General Purpose I/O Line 4
I/O Line of GPTA0
I/O0 A1/
PU
IN44
I
IN44
I
I/O Line of GPTA1
RCLK1A
OUT44
OUT44
Reserved
I
MLI1 Receive Channel Clock Input A
I/O Line of GPTA0
O1
O2
O3
I/O Line of GPTA1
-
Data Sheet
87
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
K2
P8.5
I/O0 A2/
Port 8 General Purpose I/O Line 5
PU
IN45
I
I/O Line of GPTA0
I/O Line of GPTA1
I/O Line of GPTA0
I/O Line of GPTA1
IN45
I
OUT45
OUT45
O1
O2
RREADY1A O3
MLI1 Receive Channel ready Output A
Port 8 General Purpose I/O Line 6
I/O Line of GPTA0
K3
P8.6
I/O0 A1/
PU
IN46
I
IN46
I
I/O Line of GPTA1
RVALID1A
OUT46
OUT46
Reserved
P8.7
I
MLI1 Receive Channel valid Input A
I/O Line of GPTA0
O1
O2
O3
I/O Line of GPTA1
-
K1
I/O0 A1/
Port 8 General Purpose I/O Line 7
I/O Line of GPTA0
PU
IN47
I
IN47
I
I/O Line of GPTA1
RData1A
OUT47
OUT47
Reserved
I
MLI1 Receive Channel Data Input A
I/O Line of GPTA0
O1
O2
O3
I/O Line of GPTA1
-
Port 9
Data Sheet
88
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
A19
P9.0
I/O0 A2/
Port 9 General Purpose I/O Line 0
PU
IN48
I
I/O Line of GPTA0
IN48
I
I/O Line of GPTA1
OUT48
OUT48
EN12
P9.1
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MSC1 Device Select Output 2
Port 9 General Purpose I/O Line 1
I/O Line of GPTA0
B19
B20
A20
I/O0 A2/
PU
IN49
I
IN49
I
I/O Line of GPTA1
OUT49
OUT49
EN11
P9.2
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MSC1 Device Select Output 1
Port 9 General Purpose I/O Line 2
I/O Line of GPTA0
I/O0 A2/
PU
IN50
I
IN50
I
I/O Line of GPTA1
OUT50
OUT50
SOP1B
P9.3
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MSC1 serial Data Output
Port 9 General Purpose I/O Line 3
I/O Line of GPTA0
I/O0 A2/
PU
IN51
I
IN51
I
I/O Line of GPTA1
OUT51
OUT51
FCLP1B
O1
O2
O3
I/O Line of GPTA0
I/O Line of GPTA1
MSC1 Clock Output
Data Sheet
89
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
D18
P9.4
I/O0 A2/
Port 9 General Purpose I/O Line 4
PU
IN52
I
I/O Line of GPTA0
IN52
I
I/O Line of GPTA1
OUT52
OUT52
EN03
P9.5
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MSC0 Device Select Output 3
Port 9 General Purpose I/O Line 5
I/O Line of GPTA0
’D19
C19
D20
I/O0 A2/
PU
IN53
I
IN53
I
I/O Line of GPTA1
OUT53
OUT53
EN02
P9.6
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MSC0 Device Select Output 2
Port 9 General Purpose I/O Line 6
I/O Line of GPTA0
I/O0 A2/
PU
IN54
I
IN54
I
I/O Line of GPTA1
OUT54
OUT54
EN01
P9.7
O1
I/O Line of GPTA0
O2
I/O Line of GPTA1
O3
MSC0 Device Select Output 1
Port 9 General Purpose I/O Line 7
I/O Line of GPTA0
I/O0 A2/
PU
IN55
I
IN55
I
I/O Line of GPTA1
OUT55
OUT55
SOP0B
O1
O2
O3
I/O Line of GPTA0
I/O Line of GPTA1
MSC0 serial Data Output
Data Sheet
90
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
C20
P9.8
I/O0 A2/
Port 9 General Purpose I/O Line 8
PU
FCLP0B
FCLP0B
FCLP0B
P9.9
O1
MSC0 Clock Output
O2
MSC0 Clock Output
O3
MSC0 Clock Output
A21
B21
I/O0 A1/
Port 9 General Purpose I/O Line 9
PU
Reserved
Reserved
Reserved
P9.10
O1
-
O2
-
O3
-
I/O0 A1/
Port 9 General Purpose I/O Line 10
PU
EMGSTOP
Reserved
Reserved
Reserved
P9.11
I
Emergency Stop
O1
-
O2
-
O3
-
C21
D21
I/O0 A1/
Port 9 General Purpose I/O Line 11
PU
Reserved
Reserved
Reserved
P9.12
O1
-
O2
-
O3
-
I/O0 A1/
Port 9 General Purpose I/O Line 12
PU
Reserved
Reserved
Reserved
O1
-
-
-
O2
O3
Data Sheet
91
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
C26
P9.13
I/O0 A2/
Port 9 General Purpose I/O Line 13
PU
BRKIN
I
OCDS Break Input
Reserved
Reserved
Reserved
BRKOUT
P9.14
O1
-
O2
-
O3
-
O
OCDS Break Output
D26
I/O0 A2/
Port 9 General Purpose I/O Line 14
PU
BRKIN
I
OCDS Break Input
Reserved
Reserved
Reserved
BRKOUT
O1
O2
O3
O
-
-
-
OCDS Break Output
Port 10
AE15 P10.0
MRST0
I/O0 A2/
Port 10 General Purpose I/O Line 0
PU
I
SSC0 Master Receive Input (Master Mode)
MRST0
O1
SSC0 Slave Transmit Output (Slave Mode)
Reserved
Reserved
AF15 P10.1
MTSR0
O2
-
O3
-
I/O0 A2/
Port 10 General Purpose I/O Line 1
PU
I
SSC0 Slave Receive Input (Slave Mode)
MTSR0
O1
SSC0 Master Transmit Output (Master
Mode)
Reserved
Reserved
O2
O3
-
-
Data Sheet
92
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
Pin
AD15 P10.2
SLSI01
I/O0 A1/
Port 10 General Purpose I/O Line 2
PU
I
SSC0 Slave Select Input
Reserved
Reserved
Reserved
AF14 P10.3
SCLK0
O1
-
O2
-
O3
-
I/O0 A2/
Port 10 General Purpose I/O Line 3
PU
I
SSC0 Clock Input/Output
SCLK0
O1
SSC0 Clock Input/Output
Reserved
Reserved
AE14 P10.4
SLSO00
O2
-
O3
-
I/O0 A2/
Port 10 General Purpose I/O Line 4
PU
O1
SSC0 Slave Select Output Line 0
Reserved
Reserved
AC15 P10.5
SLSO01
O2
-
O3
-
I/O0 A2/
Port 10 General Purpose I/O Line 5
PU
O1
SSC0 Slave Select Output Line 1
Reserved
Reserved
Port 11
O2
O3
-
-
J26
P11.0
I/O0 B1/
Port 11 General Purpose I/O Line 0
PU
Reserved
Reserved
Reserved
A0
O1
-
O2
O3
O
-
-
EBU Address Bus Line 0
Data Sheet
93
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
K25
P11.1
I/O0 B1/
Port 11 General Purpose I/O Line 1
PU
Reserved
Reserved
Reserved
A1
O1
-
O2
-
O3
-
O
EBU Address Bus Line 1
K26
J23
K24
L25
P11.2
I/O0 B1/
Port 11 General Purpose I/O Line 2
PU
Reserved
Reserved
Reserved
A2
O1
-
O2
-
O3
-
O
EBU Address Bus Line 2
P11.3
I/O0 B1/
Port 11 General Purpose I/O Line 3
PU
Reserved
Reserved
Reserved
A3
O1
-
O2
-
O3
-
O
EBU Address Bus Line 3
P11.4
I/O0 B1/
Port 11 General Purpose I/O Line 4
PU
Reserved
Reserved
Reserved
A4
O1
-
O2
-
O3
-
O
EBU Address Bus Line 4
P11.5
I/O0 B1/
Port 11 General Purpose I/O Line 5
PU
Reserved
Reserved
Reserved
A5
O1
-
O2
O3
O
-
-
EBU Address Bus Line 5
Data Sheet
94
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
L26
P11.6
I/O0 B1/
Port 11 General Purpose I/O Line 6
PU
Reserved
Reserved
Reserved
A6
O1
-
O2
-
O3
-
O
EBU Address Bus Line 6
K23
M26
M25
M24
P11.7
I/O0 B1/
Port 11 General Purpose I/O Line 7
PU
Reserved
Reserved
Reserved
A7
O1
-
O2
-
O3
-
O
EBU Address Bus Line 7
P11.8
I/O0 B1/
Port 11 General Purpose I/O Line 8
PU
Reserved
Reserved
Reserved
A8
O1
-
O2
-
O3
-
O
EBU Address Bus Line 8
P11.9
I/O0 B1/
Port 11 General Purpose I/O Line 9
PU
Reserved
Reserved
Reserved
A9
O1
-
O2
-
O3
-
O
EBU Address Bus Line 9
P11.10
Reserved
Reserved
Reserved
A10
I/O0 B1/
Port 11 General Purpose I/O Line 10
PU
O1
-
O2
O3
O
-
-
EBU Address Bus Line 10
Data Sheet
95
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
L24
P11.11
I/O0 B1/
Port 11 General Purpose I/O Line 11
PU
Reserved
Reserved
Reserved
A11
O1
-
O2
-
O3
-
O
EBU Address Bus Line 11
N26
P11.12
I/O0 B1/
Port 11 General Purpose I/O Line 12
PU
Reserved
Reserved
Reserved
A12
O1
-
O2
-
O3
-
O
EBU Address Bus Line 12
N23
P11.13
I/O0 B1/
Port 11 General Purpose I/O Line 13
PU
Reserved
Reserved
Reserved
A13
O1
-
O2
-
O3
-
O
EBU Address Bus Line 13
N24
P11.14
I/O0 B1/
Port 11 General Purpose I/O Line 14
PU
Reserved
Reserved
Reserved
A14
O1
-
O2
-
O3
-
O
EBU Address Bus Line 14
N25
P11.15
I/O0 B1/
Port 11 General Purpose I/O Line 15
PU
Reserved
Reserved
Reserved
A15
O1
-
O2
O3
O
-
-
EBU Address Bus Line 15
Port 12
Data Sheet
96
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
P26
P12.0
I/O0 B1/
Port 12 General Purpose I/O Line 0
PU
Reserved
Reserved
Reserved
A16
O1
-
O2
-
O3
-
O
EBU Address Bus Line 16
P24
P25
R24
R26
P12.1
I/O0 B1/
Port 12 General Purpose I/O Line 1
PU
Reserved
Reserved
Reserved
A17
O1
-
O2
-
O3
-
O
EBU Address Bus Line 17
P12.2
I/O0 B1/
Port 12 General Purpose I/O Line 2
PU
Reserved
Reserved
Reserved
A18
O1
-
O2
-
O3
-
O
EBU Address Bus Line 18
P12.3
I/O0 B1/
Port 12 General Purpose I/O Line 3
PU
Reserved
Reserved
Reserved
A19
O1
-
O2
-
O3
-
O
EBU Address Bus Line 19
P12.4
I/O0 B1/
Port 12 General Purpose I/O Line 4
PU
Reserved
Reserved
Reserved
A20
O1
-
O2
O3
O
-
-
EBU Address Bus Line 20
Data Sheet
97
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
R25
P12.5
I/O0 B1/
Port 12 General Purpose I/O Line 5
PU
Reserved
Reserved
Reserved
A21
O1
-
O2
-
O3
-
O
EBU Address Bus Line 21
J24
J25
P12.6
I/O0 B1/
Port 12 General Purpose I/O Line 6
PU
Reserved
Reserved
Reserved
A22
O1
-
O2
-
O3
-
O
EBU Address Bus Line 22
P12.7
I/O0 B1/
Port 12 General Purpose I/O Line 7
PU
Reserved
Reserved
Reserved
A23
O1
-
O2
O3
O
-
-
EBU Address Bus Line 23
Port 13
T26
P13.0
AD0
I/O0 B1/
Port 13 General Purpose I/O Line 0
EBU Address/Data Bus Line 0
OUT88 Line of GPTA0
PU
I
OUT88
OUT88
OUT80
AD0
O1
O2
O3
O
OUT88 Line of GPTA1
OUT80 Line of LTCA2
EBU Address/Data Bus Line 0
Data Sheet
98
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
T24
P13.1
AD1
I/O0 B1/
Port 13 General Purpose I/O Line 1
PU
I
EBU Address/Data Bus Line 1
OUT89 Line of GPTA0
OUT89
OUT89
OUT81
AD1
O1
O2
OUT89 Line of GPTA1
O3
OUT81 Line of LTCA2
O
EBU Address/Data Bus Line 1
Port 13 General Purpose I/O Line 2
EBU Address/Data Bus Line 2
OUT90 Line of GPTA0
U26
T25
V26
P13.2
AD2
I/O0 B1/
PU
I
OUT90
OUT90
OUT82
AD2
O1
O2
OUT90 Line of GPTA1
O3
OUT82 Line of LTCA2
O
EBU Address/Data Bus Line 2
Port 13 General Purpose I/O Line 3
EBU Address/Data Bus Line 3
OUT91 Line of GPTA0
P13.3
AD3
I/O0 B1/
PU
I
OUT91
OUT91
OUT83
AD3
O1
O2
OUT91 Line of GPTA1
O3
OUT83 Line of LTCA2
O
EBU Address/Data Bus Line 3
Port 13 General Purpose I/O Line 4
EBU Address/Data Bus Line 4
OUT92 Line of GPTA0
P13.4
AD4
I/O0 B1/
PU
I
OUT92
OUT92
OUT84
AD4
O1
O2
O3
O
OUT92 Line of GPTA1
OUT84 Line of LTCA2
EBU Address/Data Bus Line 4
Data Sheet
99
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
U25
P13.5
AD5
I/O0 B1/
Port 13 General Purpose I/O Line 5
PU
I
EBU Address/Data Bus Line 5
OUT93 Line of GPTA0
OUT93
OUT93
OUT85
AD5
O1
O2
OUT93 Line of GPTA1
O3
OUT85 Line of LTCA2
O
EBU Address/Data Bus Line 5
Port 13 General Purpose I/O Line 6
EBU Address/Data Bus Line 6
OUT94 Line of GPTA0
U23
W26
V25
P13.6
AD6
I/O0 B1/
PU
I
OUT94
OUT94
OUT86
AD6
O1
O2
OUT94 Line of GPTA1
O3
OUT86 Line of LTCA2
O
EBU Address/Data Bus Line 6
Port 13 General Purpose I/O Line 7
EBU Address/Data Bus Line 7
OUT95 Line of GPTA0
P13.7
AD7
I/O0 B1/
PU
I
OUT95
OUT95
OUT87
AD7
O1
O2
OUT95 Line of GPTA1
O3
OUT87 Line of LTCA2
O
EBU Address/Data Bus Line 7
Port 13 General Purpose I/O Line 8
EBU Address/Data Bus Line 8
OUT96 Line of GPTA0
P13.8
AD8
I/O0 B1/
PU
I
OUT96
OUT96
OUT88
AD8
O1
O2
O3
O
OUT96 Line of GPTA1
OUT88 Line of LTCA2
EBU Address/Data Bus Line 8
Data Sheet
100
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
U24
P13.9
AD9
I/O0 B1/
Port 13 General Purpose I/O Line 9
PU
I
EBU Address/Data Bus Line 9
OUT97 Line of GPTA0
OUT97
OUT97
OUT89
AD9
O1
O2
OUT97 Line of GPTA1
O3
OUT89 Line of LTCA2
O
EBU Address/Data Bus Line 9
Port 13 General Purpose I/O Line 10
EBU Address/Data Bus Line 10
OUT98 Line of GPTA0
Y26
P13.10
AD10
I/O0 B1/
PU
I
OUT98
OUT98
OUT90
AD10
O1
O2
OUT98 Line of GPTA1
O3
OUT90 Line of LTCA2
O
EBU Address/Data Bus Line 10
Port 13 General Purpose I/O Line 11
EBU Address/Data Bus Line 11
OUT99 Line of GPTA0
AA26 P13.11
AD11
I/O0 B1/
PU
I
OUT99
O1
OUT99
O2
OUT99 Line of GPTA1
OUT91
O3
OUT91 Line of LTCA2
AD11
O
EBU Address/Data Bus Line 11
Port 13 General Purpose I/O Line 12
EBU Address/Data Bus Line 12
OUT100 Line of GPTA0
W25
P13.12
AD12
I/O0 B1/
PU
I
OUT100
OUT100
OUT92
AD12
O1
O2
O3
O
OUT100 Line of GPTA1
OUT92 Line of LTCA2
EBU Address/Data Bus Line 12
Data Sheet
101
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
V24
P13.13
AD13
I/O0 B1/
Port 13 General Purpose I/O Line 13
PU
I
EBU Address/Data Bus Line 13
OUT101 Line of GPTA0
OUT101
OUT101
OUT93
AD13
O1
O2
OUT101 Line of GPTA1
O3
OUT93 Line of LTCA2
O
EBU Address/Data Bus Line 13
Port 13 General Purpose I/O Line 14
EBU Address/Data Bus Line 14
OUT102 Line of GPTA0
Y25
P13.14
AD14
I/O0 B1/
PU
I
OUT102
OUT102
OUT94
AD14
O1
O2
OUT102 Line of GPTA1
O3
OUT94 Line of LTCA2
O
EBU Address/Data Bus Line 14
Port 13 General Purpose I/O Line 15
EBU Address/Data Bus Line 15
OUT103 Line of GPTA0
AB26 P13.15
AD15
I/O0 B1/
PU
I
OUT103
OUT103
OUT95
O1
O2
O3
O
OUT103 Line of GPTA1
OUT95 Line of LTCA2
AD15
EBU Address/Data Bus Line 15
Port 14
W24
P14.0
I/O0 B1/
Port 14 General Purpose I/O Line 0
EBU Address/Data Bus Line 16
OUT96 Line of GPTA0
PU
AD16
I
OUT96
OUT96
OUT96
AD16
O1
O2
O3
O
OUT96 Line of GPTA1
OUT96 Line of LTCA2
EBU Address/Data Bus Line 16
Data Sheet
102
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AA25 P14.1
AD17
I/O0 B1/
Port 14 General Purpose I/O Line 1
PU
I
EBU Address/Data Bus Line 17
OUT97 Line of GPTA0
OUT97
OUT97
OUT97
AD17
O1
O2
OUT97 Line of GPTA1
O3
OUT97 Line of LTCA2
O
EBU Address/Data Bus Line 17
Port 14 General Purpose I/O Line 2
EBU Address/Data Bus Line 18
OUT98 Line of GPTA0
Y24
P14.2
I/O0 B1/
PU
AD18
I
OUT98
OUT98
OUT98
AD18
O1
O2
OUT98 Line of GPTA1
O3
OUT98 Line of LTCA2
O
EBU Address/Data Bus Line 18
Port 14 General Purpose I/O Line 3
EBU Address/Data Bus Line 19
OUT99 Line of GPTA0
AA23 P14.3
AD19
I/O0 B1/
PU
I
OUT99
O1
OUT99
O2
OUT99 Line of GPTA1
OUT99
O3
OUT99 Line of LTCA2
AD19
O
EBU Address/Data Bus Line 19
Port 14 General Purpose I/O Line 4
EBU Address/Data Bus Line 20
OUT100 Line of GPTA0
AB25 P14.4
AD20
I/O0 B1/
PU
I
OUT100
OUT100
OUT100
AD20
O1
O2
O3
O
OUT100 Line of GPTA1
OUT100 Line of LTCA2
EBU Address/Data Bus Line 20
Data Sheet
103
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AB24 P14.5
AD21
I/O0 B1/
Port 14 General Purpose I/O Line 5
PU
I
EBU Address/Data Bus Line 21
OUT101 Line of GPTA0
OUT101
O1
OUT101
OUT101
AD21
O2
OUT101 Line of GPTA1
O3
OUT101 Line of LTCA2
O
EBU Address/Data Bus Line 21
Port 14 General Purpose I/O Line 6
EBU Address/Data Bus Line 22
OUT102 Line of GPTA0
AA24 P14.6
I/O0 B1/
PU
AD22
I
OUT102
OUT102
OUT102
AD22
O1
O2
OUT102 Line of GPTA1
O3
OUT102 Line of LTCA2
O
EBU Address/Data Bus Line 22
Port 14 General Purpose I/O Line 7
EBU Address/Data Bus Line 23
OUT103 Line of GPTA0
AC26 P14.7
I/O0 B1/
PU
AD23
I
OUT103
OUT103
OUT103
AD23
O1
O2
OUT103 Line of GPTA1
O3
OUT103 Line of LTCA2
O
EBU Address/Data Bus Line 23
Port 14 General Purpose I/O Line 8
EBU Address/Data Bus Line 24
OUT104 Line of GPTA0
AD26 P14.8
I/O0 B1/
PU
AD24
I
OUT104
OUT104
OUT104
AD24
O1
O2
O3
O
OUT104 Line of GPTA1
OUT104 Line of LTCA2
EBU Address/Data Bus Line 24
Data Sheet
104
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AC25 P14.9
AD25
I/O0 B1/
Port 14 General Purpose I/O Line 9
PU
I
EBU Address/Data Bus Line 25
OUT105 Line of GPTA0
OUT105
O1
OUT105
OUT105
AD25
O2
OUT105 Line of GPTA1
O3
OUT105 Line of LTCA2
O
EBU Address/Data Bus Line 25
Port 14 General Purpose I/O Line 10
EBU Address/Data Bus Line 26
OUT106 Line of GPTA0
AE26 P14.10
AD26
I/O0 B1/
PU
I
OUT106
OUT106
OUT106
AD26
O1
O2
OUT106 Line of GPTA1
O3
OUT106 Line of LTCA2
O
EBU Address/Data Bus Line 26
Port 14 General Purpose I/O Line 11
EBU Address/Data Bus Line 27
OUT107 Line of GPTA0
AD25 P14.11
AD27
I/O0 B1/
PU
I
OUT107
OUT107
OUT107
AD27
O1
O2
OUT107 Line of GPTA1
O3
OUT107 Line of LTCA2
O
EBU Address/Data Bus Line 27
Port 14 General Purpose I/O Line 12
EBU Address/Data Bus Line 28
OUT108 Line of GPTA0
AC24 P14.12
AD28
I/O0 B1/
PU
I
OUT108
OUT108
OUT108
AD28
O1
O2
O3
O
OUT108 Line of GPTA1
OUT108 Line of LTCA2
EBU Address/Data Bus Line 28
Data Sheet
105
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
Pin
AE25 P14.13
AD29
I/O0 B1/
Port 14 General Purpose I/O Line 13
PU
I
EBU Address/Data Bus Line 29
OUT109 Line of GPTA0
OUT109
OUT109
OUT109
AD29
O1
O2
OUT109 Line of GPTA1
O3
OUT109 Line of LTCA2
O
EBU Address/Data Bus Line 29
Port 14 General Purpose I/O Line 14
EBU Address/Data Bus Line 30
OUT110 Line of GPTA0
AE24 P14.14
AD30
I/O0 B1/
PU
I
OUT110
OUT110
OUT110
AD30
O1
O2
OUT110 Line of GPTA1
O3
OUT110 Line of LTCA2
O
EBU Address/Data Bus Line 30
Port 14 General Purpose I/O Line 15
EBU Address/Data Bus Line 31
OUT111 Line of GPTA0
AD24 P14.15
AD31
I/O0 B1/
PU
I
OUT111
OUT111
OUT111
AD31
O1
O2
O3
O
OUT111 Line of GPTA1
OUT111 Line of LTCA2
EBU Address/Data Bus Line 31
Port 15
AE21 P15.0
Reserved
Reserved
Reserved
CS0
I/O0 B1/
Port 15 General Purpose I/O Line 0
PU
O1
-
O2
O3
O
-
-
Chip Select Output Line 0
Data Sheet
106
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
Pin
AD21 P15.1
I/O0 B1/
Port 15 General Purpose I/O Line 1
PU
Reserved
O1
-
Reserved
Reserved
CS1
O2
-
O3
-
O
Chip Select Output Line 1
AD20 P15.2
I/O0 B1/
Port 15 General Purpose I/O Line 2
PU
Reserved
Reserved
Reserved
CS2
O1
-
O2
-
O3
-
O
Chip Select Output Line 2
AD19 P15.3
I/O0 B1/
Port 15 General Purpose I/O Line 3
PU
Reserved
Reserved
Reserved
CS3
O1
-
O2
-
O3
-
O
Chip Select Output Line 3
AE17 P15.4
I/O0 B1/
Port 15 General Purpose I/O Line 4
PU
Reserved
Reserved
Reserved
BC0
O1
-
O2
-
O3
-
O
Byte Control Line 0
AD17 P15.5
I/O0 B1/
Port 15 General Purpose I/O Line 5
PU
Reserved
Reserved
Reserved
BC1
O1
-
O2
O3
O
-
-
Byte Control Line 1
Data Sheet
107
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
Pin
AF18 P15.6
I/O0 B1/
Port 15 General Purpose I/O Line 6
PU
Reserved
O1
-
Reserved
Reserved
BC2
O2
-
O3
-
O
Byte Control Line 2
AE18 P15.7
I/O0 B1/
Port 15 General Purpose I/O Line 7
PU
Reserved
Reserved
Reserved
BC3
O1
-
O2
-
O3
-
O
Byte Control Line 3
AF20 P15.8
I/O0 B1/
Port 15 General Purpose I/O Line 8
PU
Reserved
Reserved
Reserved
RD
O1
-
O2
-
O3
-
O
Read Control Line
AF21 P15.9
I/O0 B1/
Port 15 General Purpose I/O Line 9
PU
Reserved
Reserved
Reserved
RD/WR
O1
-
O2
-
O3
-
O
Write Control Line
AF22 P15.10
I/O0 B1/
Port 15 General Purpose I/O Line 10
PU
Reserved
Reserved
Reserved
ADV
O1
-
O2
O3
O
-
-
Address Valid Output
Data Sheet
108
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AE20 P15.11
WAIT
I/O0 B1/
Port 15 General Purpose I/O Line 11
PU
I
Wait Input for inserting Wait-States
Reserved
O1
-
Reserved
Reserved
O2
-
O3
-
AF19 P15.12
I/O0 B1/
Port 15 General Purpose I/O Line 12
PU
Reserved
Reserved
Reserved
MR/W
O1
-
-
-
O2
O3
O
Motorola-style Read/Write Control Signal
AF23 P15.13
I/O0 B1/
Port 15 General Purpose I/O Line 13
PU
Reserved
Reserved
Reserved
BAA
O1
-
O2
-
O3
-
O
Burst Address Advance Output
AF24 P15.14
I/O0 B1/
Port 15 General Purpose I/O Line 14
PU
BFCLKI
I
Burst FLASH Clock Input (Clock Feedback).
Reserved
Reserved
Reserved
O1
-
O2
-
O3
-
AF25 P15.15
I/O0 B2/
Port 15 General Purpose I/O Line 15
PU
Reserved
Reserved
Reserved
BFCLKO
O1
-
-
-
O2
O3
O
Burst Mode Flash Clock Output (Non-
Differential)
Data Sheet
109
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
Port 16
AF17 P16.0
HOLD
I/O0 B1/
Port 16 General Purpose I/O Line 0
PU
I
Hold Request Input
Reserved
O1
-
Reserved
Reserved
O2
-
O3
-
AD18 P16.1
I/O0 B1/
Port 16 General Purpose I/O Line 1
PU
HLDA
I
Hold Acknowledge Output
Reserved
Reserved
Reserved
HLDA
O1
-
O2
-
O3
-
O
Hold Acknowledge Output
AD22 P16.2
I/O0 B1/
Port 16 General Purpose I/O Line 2
PU
Reserved
Reserved
Reserved
BREQ
O1
-
O2
-
O3
-
O
Bus Request Output
AE19 P16.3
I/O0 B1/
Port 16 General Purpose I/O Line 3
PU
Reserved
Reserved
O1
-
O2
O3
O
-
Reserved
-
CSCOMB
Combined Chip Select Output
Analog Input Port
AE1
AD2
AA4
AN0
AN1
AN2
I
I
I
D
D
D
Analog Input 0
Analog Input 1
Analog Input 2
Data Sheet
110
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AB3
AC2
AA3
AD1
AB4
AC1
AB2
Y3
AN3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Analog Input 3
Analog Input 4
Analog Input 5
Analog Input 6
Analog Input 7
Analog Input 8
Analog Input 9
Analog Input 10
Analog Input 11
Analog Input 12
Analog Input 13
Analog Input 14
Analog Input 15
Analog Input 16
Analog Input 17
Analog Input 18
Analog Input 19
Analog Input 20
Analog Input 21
Analog Input 22
Analog Input 23
Analog Input 24
Analog Input 25
Analog Input 26
Analog Input 27
Analog Input 28
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AA2
AB1
W3
Y2
AA1
V4
W2
Y1
V3
W1
V2
V1
U1
AC8
AD8
AC7
AD7
AE6
Data Sheet
111
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AF6
AE7
AF7
AC3
AE2
AD3
AD5
AE3
AF2
AC4
AF3
AD4
AE4
AC5
AF4
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
AN40
AN41
AN42
AN43
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Analog Input 29
Analog Input 30
Analog Input 31
Analog Input 32
Analog Input 33
Analog Input 34
Analog Input 35
Analog Input 36
Analog Input 37
Analog Input 38
Analog Input 39
Analog Input 40
Analog Input 41
Analog Input 42
Analog Input 43
System I/O
B22
A23
PORST
I
Input Power-on Reset Input
only/ (input pad with input spike-filter)
PD
ESR0
ESR1
I/O
A2
External System Request Reset Input 0
Default configuration during and after reset is
open-drain Driver, corresponding to A2 strong
Driver, sharp edge. The Driver drives low during
power-on reset.
A22
E24
I/O
A2/
PD
External System Request Reset Input 1
TCK
I
I
Input JTAG Module Clock Input
only/
PD
DAP0
Device Access Port Line 0
Data Sheet
112
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
E25
TDI
I
A2/
PU
JTAG Module Serial Data Input
BRKIN
BRKOUT
I
OCDS Break Input (Alternate Output)
OCDS Break Output (Alternate Input)
O
B23
TESTMODE I
Input Test Mode Select Input
only/
PU
F24
F23
TMS
I
A2/
PD
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
TRST
I/O
I
Input JTAG Module Reset/Enable Input
only/
PD
G26
G25
D25
XTAL1
XTAL2
TDO
I
Main Oscillator/PLL/Clock Generator Input
Main Oscillator/PLL/Clock Generator Output
O
O
I
A2/
PU
JTAG Module Serial Data Output
OCDS Break Input (Alternate Input)
OCDS Break Output (Alternate Output)
Device Access Port Line 2
BRKIN
BRKOUT
DAP2
N.C.
O
O
-
A1,
AF1,
AF26,
A24,
-
Not connected. These pins are reserved for
future extension and shall not be connected
externally.
C22,
AC21,
AD23,
AE22,
AE23
Power Supply
W4
Y4
VDDM
VSSM
-
-
-
-
-
-
ADC Analog Part Power Supply (3.3V - 5V)
ADC Analog Part Ground
AE5
VAREF0
ADC0 Reference Voltage
Data Sheet
113
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AF5
VAGND0
VAGND2
VAREF1
VAGND1
VAREF2
VFAREF
VFAGND
VDDMF
VDDAF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC0 Reference Ground
ADC2 Reference Ground
ADC1 Reference Voltage
ADC1 Reference Ground
ADC2 Reference Voltage
FADC Reference Voltage
FADC Reference Ground
AD6
AC6
AD9
AF8
AE8
AE9
AC9
FADC Analog Part Power Supply (3.3V)1)
FADC Analog Part Logic Power Supply
(1.5V)
AF9
VSSMF
VSSAF
VDDFL3
-
-
-
-
-
-
FADC Analog Part Ground
FADC Analog Part Logic Ground
Flash Power Supply (3.3V)
A18,
B18,
H3
F25
VSSOSC
VSS
-
-
-
-
-
-
-
-
-
-
-
-
Main Oscillator Ground
Digital Ground
F26
E26
G23
G24
VDDOSC
VDDOSC3
VDDPF
Main Oscillator Power Supply (1.5V)
Main Oscillator Power Supply (3.3V)
PLL Power Supply (1.5V)
PLL Power Supply (3.3V)
VDDPF3
Data Sheet
114
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AC11, VDD
AC20,
AB23,
V23,
-
-
Digital Core Power Supply (1.5V)
P23,
E23,
D24,
C25,
B26,
D16,
D9,
H4,
R4
AC16, VDDP
AD16,
AE16,
AF16,
D22,
-
-
Port Power Supply (3.3V)
C23,
B24,
A25,
D14,
D7, K4
H23,
H24,
H25,
H26,
M23,
T23,
VDDEBU
-
-
EBU Port Power Supply (2.5V - 3.3V)
Y23,
AC18,
AC22
R1
VDDE(SB)
-
-
Emulation Stand-by SRAM Power Supply
(1.5V) (Emulation device only)
Note: This pin is N.C. in a productive device.
Data Sheet
115
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
AC10, VSS
AC17,
AC19,
AC23,
W23,
R23,
-
-
Digital Ground (outer balls)
L23,
D23,
C24,
B25,
A26,
D15,
D8,
J4, T4
K10,
K11,
K12,
K13,
K14,
K15,
K16,
K17
VSS
VSS
VSS
-
-
-
-
-
-
Digital Ground (center balls)
L10,
L11,
L12,
L13,
L14,
L15,
L16,
L17
Digital Ground (center balls cont’d)
M10,
M11,
M12,
M13,
M14,
M15,
M16,
M17
Digital Ground (center balls cont’d)
Data Sheet
116
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
N10,
N11,
N12,
N13,
N14,
N15,
N16,
N17
VSS
VSS
VSS
VSS
-
-
-
-
-
-
-
-
Digital Ground (center balls cont’d)
Digital Ground (center balls cont’d)
Digital Ground (center balls cont’d)
Digital Ground (center balls cont’d)
P10,
P11,
P12,
P13,
P14,
P15,
P16,
P17
R10,
R11,
R12,
R13,
R14,
R15,
R16,
R17
T10,
T11,
T12,
T13,
T14,
T15,
T16,
T17
Data Sheet
117
V1.1, 2009-05
TC1197
Pinning
Table 4
Pin
Pin Definitions and Functions (BGA-416 Package) (cont’d)
Symbol Ctrl. Type Function
Digital Ground (center balls cont’d)
U10,
U11,
U12,
U13,
U14,
U15,
U16,
U17
VSS
-
-
1) This pin is also connected to the analog power supply for comparator of the ADC module.
Legend for Table 4
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11B (ALT3)
Column “Type”:
A1 = Pad class A1 (LVTTL)
A2 = Pad class A2 (LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
3.1.2
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 5
List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
Pull-up
PORST = 1
all GPIOs, TDI, TESTMODE
PORST, TRST, TCK, TMS
Pull-down
Data Sheet
118
V1.1, 2009-05
TC1197
Pinning
Table 5
Pins
List of Pull-Up/Pull-Down Reset Behavior of the Pins
PORST = 0
PORST = 1
Pull-up2)
ESR0
The open-drain driver is
used to drive low.1)
ESR1
TDO
Pull-down2)
Pull-up
High-impedance
1) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter
for details.
2) See the SCU_IOCR register description.
Data Sheet
119
V1.1, 2009-05
TC1197
Identification Registers
4
Identification Registers
The Identification Registers uniquely identify a module or the whole device.
Table 4-1
Short Name
ADC0_ID
ADC1_ID
ADC2_ID
ASC0_ID
ASC1_ID
CAN_ID
TC1197 Identification Registers 1)
Value
Address
Stepping
0059 C000H
0059 C000H
0059 C000H
0000 4402H
0000 4402H
002B C051H
0000 6350H
1015 A083H
0015 C007H
000A C006H
001A C004H
0008 C005H
0014 C009H
0027 C003H
0053 C001H
0055 C001H
0054 C003H
0029 C005H
0029 C005H
000F C005H
000C C006H
002A C005H
001B C001H
0025 C007H
0025 C007H
0028 C003H
0028 C003H
F010 1008H
F010 1408H
F010 1808H
F000 0A08H
F000 0B08H
F000 4008H
F000 0408H
F000 0464H
F7E0 FF08H
F7E1 FE18H
F000 3C08H
F87F FC08H
F800 0008H
F010 0408H
F800 2008H
F800 4008H
F7E1 A020H
F000 1808H
F000 2008H
F87F FE08H
F87F FF08H
F000 2808H
F010 C208H
F010 C008H
F010 C108H
F000 0808H
F000 0908H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CBS_JDPID
CBS_JTAGID
CPS_ID
CPU_ID
DMA_ID
DMI_ID
EBU_ID
FADC_ID
FLASH0_ID
FLASH1_ID
FPU_ID
GPTA0_ID
GPTA1_ID
LBCU_ID
LFI_ID
LTCA2_ID
MCHK_ID
MLI0_ID
MLI1_ID
MSC0_ID
MSC1_ID
Data Sheet
Intro, V1.5
4-120
V1.1, 2009-05
TC1197
Identification Registers
Table 4-1
Short Name
PCP_ID
TC1197 Identification Registers (cont’d)1)
Value
Address
Stepping
0020 C006H
000B C005H
0050 C001H
0051 C001H
0000 6A0CH
0000 9001H
0052 C001H
0000 1820H
0000 0003H
0000 4511H
0000 4511H
0000 C006H
F004 3F08H
F87F FD08H
F800 0508H
F800 6008H
F000 0108H
F000 0640H
F000 0508H
F000 0644H
F000 0648H
F010 0108H
F010 0208H
F000 0208H
–
PMI_ID
–
PMU0_ID
PMU1_ID
SBCU_ID
SCU_CHIPID
SCU_ID
–
–
–
–
–
SCU_MANID
SCU_RTID
SSC0_ID
SSC1_ID
STM_ID
–
AC only
–
–
–
1) Valid for all design steps except if explicitely defined.
Data Sheet
Intro, V1.5
4-121
V1.1, 2009-05
TC1197
Electrical Parameters
5
Electrical Parameters
5.1
General Parameters
5.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1197
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
• CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1197 and must be regarded for a system design.
• SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1197 designed in.
Data Sheet
122
V1.1, 2009-05
TC1197
Electrical Parameters
5.1.2
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 6
Pad Driver and Pad Classes Overview
Class Power Type
Supply
Sub Class Speed Load Leakage1) Termination
Grade
A
3.3 V
LVTTL A1
6 MHz 100 pF 500 nA
No
I/O,
(e.g. GPIO)
LVTTL
outputs
A2
(e.g. serial
I/Os)
40
MHz
50 pF 6 μA
50 pF 6 μA
Series
termination
recommended
B
2.375 - LVTTL B1
3.6 V2) I/O
(e.g. Ext.
40
MHz
No
Bus
Interface)
B2
75
35 pF
Series
(e.g. Bus
Clock)
MHz
termination
recommended
(for f > 25 MHz)
F
3.3 V
5 V
LVDS/
CMOS
–
50
MHz
–
–
–
–
Parallel
termination3),
100 Ω ± 10%
DE
ADC
–
–
see Table 11
1) Values are for TJmax = 150 °C.
2) AC characteristics for EBU pins are valid for 2.5 V ± 5% and 3.3 V ± 5%.
3) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.
Data Sheet
123
V1.1, 2009-05
TC1197
Electrical Parameters
5.1.3
Absolute Maximum Ratings
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the
voltage on the related VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Table 7
Absolute Maximum Rating Parameters
Symbol Values
Min. Typ. Max.
Parameter
Unit Note /
Test Con
dition
Ambient temperature
Storage temperature
Junction temperature
TA
TST
TJ
SR -40
–
–
–
–
125
150
150
2.25
°C
°C
°C
V
Under bias
SR -65
SR -40
–
Under bias
–
Voltage at 1.5 V power supply VDD
pins with respect to VSS
–
1)
SR
Voltage at 3.3 V power supply VDDEBU
–
–
–
3.75
5.5
V
V
V
–
–
2)
pins with respect to VSS
VDDP SR
Voltage at 5 V power supply VDDM SR –
pins with respect to VSS
Voltage on any Class A input VIN
pin and dedicated input pins
with respect to VSS
SR -0.5 –
V
DDP + 0.5
Whatever
is lower
or max. 3.7
Voltage on any Class B input VIN
pin with respect to VSS
SR -0.5 –
-0.5 –
V
DDEBU + 0.5 V
Whatever
is lower
or max. 3.7
Voltage on any Class D
analog input pin with respect VAREFx
to VAGND
VAIN
V
V
DDM + 0.5
DDM + 0.5
V
V
–
SR
Voltage on any shared Class VAINF
-0.5 –
–
D analog input pin with
VFAREF
respect to VSSAF, if the FADC
is switched through to the pin.
SR
Data Sheet
124
V1.1, 2009-05
TC1197
Electrical Parameters
Table 7
Absolute Maximum Rating Parameters
Symbol Values
Min. Typ. Max.
Parameter
Unit Note /
Test Con
dition
CPU Frequency
PCP Frequency
fCPU SR –
fPCP SR –
–
–
180
150
MHz Derivative
dependent
180
150
MHz Derivative
dependent
1) Applicable for VDD, VDDOSC, VDDPF, and VDDAF
.
2) Applicable for VDDP, VDDEBU, VDDFL3, DPF3, and VDDMF
V
.
5.1.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1197. All parameters specified in the following table refer to these
operating conditions, unless otherwise noticed.
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1197. All parameters specified in the following table refer to these
operating conditions, unless otherwise noted.
Table 8
Operating Condition Parameters
Symbol Values
Typ. Max.
Parameter
Unit Note /
Test Condition
Min.
Digital supply voltage1) VDD
SR 1.42
–
–
–
1.582)
V
V
V
–
VDDOSC SR
VDDP
3.13
3.473)
For Class A pins
(3.3 V ± 5%)
SR
V
DDOSC3 SR
VDDEBU SR 3.13
3.473)
2.625
For Class B
(EBU) pins
2.375
VDDFL3 SR 3.13
–
–
–
–
3.473)
3.473)
1.582)
5.25
V
V
V
V
–
Analog supply voltages VDDMF SR 3.13
FADC
FADC
VDDAF SR
1.42
VDDM
SR 4.75
For Class DE
pins, ADC
Digital ground voltage
VSS
TA
SR 0
–
–
–
V
–
–
Ambient temperature
under bias
SR -40
+125 °C
Data Sheet
125
V1.1, 2009-05
TC1197
Electrical Parameters
Table 8
Operating Condition Parameters
Symbol Values
Typ. Max.
Parameter
Unit Note /
Test Condition
Min.
Analog supply voltages –
–
–
–
–
See separate
specification
Page 133,
Page 138
4)
Overload current at
class D pins
IOV
-1
–
–
–
–
–
–
–
–
–
–
–
–
3
mA
Sum of overload current Σ|IOV|
at class D pins
10
mA per single ADC
0 < IOV < 3 mA
Overload coupling
KOVAP
5×10-
5
factor for analog inputs5)
KOVAN
5×10-
4
-1 mA< IOV < 0
CPU & LMB Bus
Frequency
fCPU SR
fPCP SR
fSYS SR
180
150
MHz Derivative
dependent
PCP Frequency
180
150
MHz Derivative
dependent6)
6)
FPI Bus Frequency
Short circuit current
–
–
–
90
+5
20
MHz
7)
ISC
SR -5
mA
Absolute sum of short
circuit currents of a pin
group (see Table 9)
Σ|ISC_PG
|
–
mA See note
SR
Inactive device pin
current
IID
SR -1
–
–
1
mA All power supply
voltages VDDx = 0
mA See note4)
Absolute sum of short
circuit currents of the
device
Σ|ISC_D
|
–
100
SR
External load
capacitance
CL
SR –
–
–
pF
Dependingonpin
class. See DC
characteristics
1) Digital supply voltages applied to the TC1197 must be static regulated voltages which allow a typical voltage
swing of ±5%.
2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated summary of the pulses does not exceed 1 h.
3) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than
100 μs and the cumulated summary of the pulses does not exceed 1 h
Data Sheet
126
V1.1, 2009-05
TC1197
Electrical Parameters
4) See additional document “TC1767 Pin Reliability in Overload“ for definition of overload current on digital pins.
5) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to
the resulting leakage current (IleakTOT) into an adjacent pin: IleakTOT = ±kA × |IOV| + IOZ1.
Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent
analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN ×
|IleakTOT|.
The definition of adjacent pins is related to their order on the silicon.
The Injected leakage current always flows in the opposite direction from the causing overload current.
Therefore, the total leakage current must be calculated as an algebraic sum of the both component leakage
currents (the own leakage current IOZ1 and the optional injected leakage current).
6) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
7) Applicable for digital outputs.
Table 9
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Pins
Group
1
P4.[7:0]
2
P4.[15:8]
3
P10.[5:0]
4
P15.[0, 1, 7:4, 11, 12]
P15.[3:0, 8, 13], P16.3
P15.9, P16.2, P15.10, P15.[15:14]
P14.[15:10]
5
6
7
8
P14.[9:8]
9
P14.[7:2]
10
11
12
13
14
15
16
17
18
19
20
P14.[1:0], P13.[15:14]
P13.[13:12]
P13.[11:6]
P13.[5:2]
P13.[1:0], P12[5:4]
P12.[3:0]
P11.[15:12]
P11.[11:8]
P11.[7:4]
P11.[3:0]
P12.[7:6]
Data Sheet
127
V1.1, 2009-05
TC1197
Electrical Parameters
Table 9
Group
21
Pin Groups for Overload / Short-Circuit Current Sum Parameter
Pins
P9.[14:13, 10:9]
P9.[12:11, 8:7, 2]
P9.[6:5, 3, 1]
P9.[0, 4], P5.[10, 11]
P5.[15:14, 9:8]
P5.[13:12, 6, 4]
P5.[7:5, 3, 0]
P3.[7:0]
22
23
24
25
26
27
28
29
P3.[15:8]
30
P0.[7:0]
31
P0.[15:8]
32
P2.[15:9]
33
P2.[8:4]
34
P2.[3:2], P6[9:8]
P6[11, 6:4]
35
36
P6.[15:12, 10, 7]
P8.[7:0]
37
38
P1.[15:13, 11:8, 5]
P1.[12, 7, 6, 4, 3]
P1.[1:0], P7.0
P7.[5:1]
39
40
41
42
P7.[7:6]
Data Sheet
128
V1.1, 2009-05
TC1197
Electrical Parameters
5.2
DC Parameters
5.2.1
Input/Output Pins
Table 10
Input/Output DC-Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
General Parameters
Pull-up current1)
|IPUH
|
10
5
–
–
–
100
85
μA VIN < VIHAmin
;
CC
class A1/A2/F/Input pads.
μA VIN < VIHBmin
;
class B1/B2 pads.
Pull-down
current1)
|IPDL
|
10
150
μA VIN >VILAmax
;
CC
CC
class A1/A2/F/Input pads.
VIN > VILBmax
class B1/B2 pads
pF f = 1 MHz
;
Pin capacitance1) CIO
(Digital I/O)
–
–
10
TA = 25 °C
Input only Pads (VDDP = 3.13 to 3.47 V = 3.3 V ± 5%)
Input low voltage VILI
-0.3
–
0.36 ×
VDDP
V
V
–
SR
Input high voltage VIHI
0.62 × –
VDDP
+
Whatever is lower
SR VDDP
0.3 or
max.
3.6
Ratio VIL/VIH
CC 0.58
–
–
–
–
Input high voltage VIHJ
TRST, TCK
0.64 × –
SR VDDP
VDDP
+
V
Whatever is lower
0.3 or
max.
3.6
4)
Input hysteresis
HYSI
0.1 ×
CC VDDP
–
–
–
V
Input leakage
current
IOZI
–
±3000 nA ((VDDP/2)-1) < VIN <
CC
±6000
((VDDP/2)+1)
Otherwise2)
Data Sheet
129
V1.1, 2009-05
TC1197
Electrical Parameters
Table 10
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Spike filter always tSF1
blocked pulse
duration
–
–
10
ns
CC
CC
Spike filter pass- tSF2
through pulse
100
–
–
ns
duration
Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
Output low voltage VOLA
–
–
0.4
V
V
V
IOL = 2 mA for medium
and strong driver mode,
IOL = 500 μA for weak
driver mode
3)
CC
Output high
voltage2) 3)
VOHA
2.4
–
–
I
OH = -2 mA for medium
and strong driver mode,
OH = -500 μA for weak
driver mode
OH = -1.4 mA for medium
and strong driver mode,
OH = -400 μA for weak
CC
I
V
0.4
DDP - –
–
I
I
driver mode
Input low voltage VILA
Class A1/2 pins
-0.3
–
0.36 ×
VDDP
V
V
–
SR
Input high voltage VIHA1
0.62 × –
VDDP
+
Whatever is lower
Class A1 pins
SR VDDP
0.3 or
max.
3.6
Ratio VIL/VIH
CC 0.58
–
–
–
–
Class A1 pins
Input high voltage VIHA2
Class A2 pins
0.60 × –
SR VDDP
VDDP
+
V
Whatever is lower
0.3 or
max.
3.6
Ratio VIL/VIH
Class A2 pins
CC 0.6
–
–
–
–
–
4)
Input hysteresis
HYSA
0.1 ×
–
V
CC VDDP
Data Sheet
130
V1.1, 2009-05
TC1197
Electrical Parameters
Table 10
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Input leakage
current Class A2
pins
IOZA2
–
–
±3000 nA ((VDDP/2)-1) < VIN <
((VDDP/2)+1)
±6000
CC
Otherwise2)
Input leakage
current
IOZA1
–
–
±500
nA 0 V <VIN < VDDP
CC
Class A1 pins
Class B Pads (VDDEBU = 2.375 to 3.47 V)
Output low voltage VOLB CC –
–
–
0.4
–
V
V
IOL = 2 mA
IOL = 2 mA
Output high
voltage
VOHB
VDDEBU
CC - 0.4
Input low voltage VILB
Input high voltage VIHB
-0.3
–
0.34 ×
VDDEBU
V
V
–
SR
0.64 × –
SR VDDEBU
VDDEBU
+ 0.3 or
max.
Whatever is lower
3.6
Ratio VIL/VIH
CC 0.53
–
–
–
–
–
–
4)
Input hysteresis
HYSB
0.1 ×
V
CC VDDEBU
Input leakage
current
Class B pins
IOZB
–
–
±3000 nA ((VDDEBU/2)-0.6) < VIN
CC
±6000
<
((VDDEBU/2)+0.6)5)
Otherwise2)
Class F Pads, LVDS Mode (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
Output low voltage VOL CC 875
–
–
–
–
–
–
mV Parallel termination
100 Ω ± 1%
Output high
voltage
VOH CC
1525
400
1325
140
mV Parallel termination
100 Ω ± 1%
Output differential VOD CC 150
voltage
mV Parallel termination
100 Ω ± 1%
Output offset
voltage
VOS CC 1075
mV Parallel termination
100 Ω ± 1%
Output impedance R0 CC 40
Ω
–
Data Sheet
131
V1.1, 2009-05
TC1197
Electrical Parameters
Table 10
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Class F Pads, CMOS Mode (VDDP = 3.13 to 3.47 V = 3.3V ± 5%)
Input low voltage VILF
-0.3
–
0.36 ×
V
–
Class F pins
SR
VDDP
Input high voltage VIHF
Class F pins
0.60 × –
SR VDDP
VDDP
+
V
Whatever is lower
0.3 or
max.
3.6
Input hysteresis
Class F pins
HYSF
0.05 × –
–
V
CC VDDP
Input leakage
current Class F
pins
IOZF
–
–
±3000 nA ((VDDP/2)-1) < VIN
<
±6000
((VDDP/2)+1)
Otherwise2)
Output low voltage VOLF
–
–
–
0.4
V
IOL = 2 mA
6)
CC
Output high
voltage2) 6)
VOHF
2.4
CC
–
–
V
V
IOH = -2 mA
V
DDP - –
IOH = -1.4 mA
0.4
Class D Pads
See ADC Characteristics
–
–
–
–
–
1) Not subject to production test, verified by design / characterization.
2) Only one of these parameters is tested, the other is verified by design characterization
3) Maximum resistance of the driver RDSON, defined for P_MOS / N_MOS transistor separately:
25 / 20 Ω for strong driver mode, IOH / L < 2 mA,
200 / 150 Ω for medium driver mode, IOH / L < 400 uA,
600 / 400 Ω for weak driver mode, IOH / L < 100 uA,
verified by design / characterization.
4) Function verified by design, value verified by design characterization.
Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce.
It cannot be guaranteed that it suppresses switching due to external system noise.
5) VDDEBU = 2.5 V ± 5%. For VDDEBU = 3.3 ± 5% see class A2 pads.
6) The following constraint applies to an LVDS pair used in CMOS mode: only one pin of a pair should be used
as output, the other should be used as input, or both pins should be used as inputs. Using both pins as outputs
is not recommended because of the higher crosstalk between them.
Data Sheet
132
V1.1, 2009-05
TC1197
Electrical Parameters
5.2.2
Analog to Digital Converters (ADC0/ADC1/ADC2)
All ADC parameters are optimized for and valid in the range of VDDM = 5V ± 5%.
Table 11
ADC Characteristics (Operating Conditions apply)
Symbol Values Unit Note /
Test Condition
Parameter
Min.
Typ. Max.
Analog supply
voltage
VDDM SR 4.75
5
5.25 1)
V
V
V
–
3.13
3.3
1.5
3.47
1.582)
–
VDD
SR 1.42
Power supply for
ADC digital part,
internal supply
Analog ground
voltage
VSSM SR -0.1
–
0.1
V
V
–
Analogreference VAREFx SR
V
AGNDx+1 VDDM VDDM+
–
voltage16)
V
0.05
1)3)4)
Analogreference VAGNDx SR VSSMx
-
0
–
–
V
1V
AREF - V
–
–
–
ground16)
0.05V
Analog input
voltage range
VAIN
SR VAGNDx
VAREFx
V
Analogreference VAREFx
-
V
DDM/2
VDDM + V
0.05
voltage range5)16) VAGNDx SR
Converter Clock fADC SR
1
–
–
90
10
MHz –
MHz –
Internal ADC
clocks
fADCI
CC 0.5
Sample time
tS
CC 2
–
–
257
TAD –
CI
Total unadjusted TUE6) CC –
error5)
±4
LSB 12-bit conversion,
without noise7)8)
–
–
–
–
±2
±1
LSB 10-bit conversion8)
LSB 8-bit conversion8)
DNL error9) 5)
INL error9)5)
EADNL
EAINL
–
±1.5 ±3.0
LSB 12-bit conversion
without noise8)10)
CC
CC
–
±1.5 ±3.0
LSB 12-bit convesion
without noise8)10)
Data Sheet
133
V1.1, 2009-05
TC1197
Electrical Parameters
Table 11
ADC Characteristics (cont’d) (Operating Conditions apply)
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Condition
Min.
Gain error9)5)
Offset error9)5)
EAGAIN
–
±0.5 ±3.5
LSB 12-bit conversion
without noise8)10)
CC
EAOFF
–
±1.0 ±4.0
LSB 12-bit converson
without noise8)10)
CC
Input leakage
current at analog
IOZ1 CC
-300
-100
-100
–
–
–
–
100
200
300
±1.5
nA
nA
nA
μA
(0% VDDM) < VIN <
(3% VDDM
(3% VDDM) < VIN <
(97% VDDM
(97% VDDM) < VIN <
)
inputs of ADC0/1
11) 12) 13)
)
(100% VDDM
)
Input leakage
current at
IOZ2
CC –
0 V < VAREF
<
V
DDM, no conversion
VAREF0/1/2,
running
per module
Input current at IAREF CC –
35
20
75
40
μA
0 V < VAREF
<
16)
14)
VAREF0/1/2
,
rms VDDM
per module
8)
Total
CAREFTOT
–
–
pF
capacitance of
the voltage
reference
CC
inputs15)16)
8)17)
Switched
CAREFSW
15
30
pF
capacitance at
the positive
reference
CC
voltage input16)
Resistance of
the reference
voltage input
path15)
RAREF
–
–
500 1000
Ω
500 Ohm increased
for AN[1:0] used as
reference input8)
CC
CC
1)8)
Total
CAINTOT
25
30
pF
capacitance of
the analog
inputs15)
Data Sheet
134
V1.1, 2009-05
TC1197
Electrical Parameters
Table 11
ADC Characteristics (cont’d) (Operating Conditions apply)
Parameter
Symbol
Values
Typ. Max.
20
Unit Note /
Test Condition
Min.
8)18)
Switched
CAINSW
–
7
pF
capacitance at
the analog
CC
voltage inputs
8)
ON resistance of RAIN
the transmission
gates in the
CC –
700 1500
Ω
analog voltage
path
ON resistance
for the ADC test
(pull-down for
AIN7)
RAIN7T CC 180
550 90019)
Ω
Test feature
available only for
AIN78) 20)
Current through IAIN7T CC –
resistanceforthe
ADC test (pull-
15
30
mA
Test feature
available only for
AIN78)
rms peak
down for AIN7)
1) Voltage overshoot to tbd. V are permissible, provided the pulse duration is less than 100 μs and the cumulated
summary of the pulses does not exceed 1 h.
2) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 μs and the cumulated
summary of the pulses does not exceed 1 h.
3) A running conversion may become inexact in case of violating the normal operating conditions (voltage
overshoot).
4) If
the
reference
voltage
VAREF
increases
or
the
VDDM
decreases,
so
that
V
AREF = (VDDM + 0.05 V to VDDM + 0.07V), then the accuracy of the ADC decreases by 4LSB12.
5) If a reduced reference voltage in a range of VDDM/2 to VDDM is used, then the ADC converter errors increase.
If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase
with the factor 1/k.
If a reduced reference voltage in a range of 1 V to VDDM/2 is used, then there are additional decrease in the
ADC speed and accuracy.
6) TUE is tested at VAREF = 5.0 V, VAGND = 0 V and VDDM = 5.0 V
7) ADC module capability.
8) Not subject to production test, verified by design / characterization.
9) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error.
10) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25.
For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625.
11) The leakage current definition is a continuous function, as shown in Figure 19. The numerical values defined
determine the characteristic points of the given continuous linear approximation - they do not define step
function.
Data Sheet
135
V1.1, 2009-05
TC1197
Electrical Parameters
12) Only one of these parameters is tested, the other is verified by design characterization.
13) The leakage current decreases typically 30% for junction temperature decrease of 10oC.
14) IAREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion
with a duration of up to tC = 25 µs can be calculated with the formula IAREF_MAX = QCONV / tC. Every conversion
needs a total charge of QCONV = 150 pC from VAREF
.
All ADC conversions with a duration longer than tC = 25µs consume an IAREF_MAX = 6µA.
15) For the definition of the parameters see also Figure 18.
16) Applies to AINx, when used as auxiliary reference inputs.
17) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this smaller capacitances are successively switched to the reference voltage.
18) The sampling capacity of the conversion C-Network is pre-charged to VAREF / 2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx deviates from VAREF/2, and is typically 1.35 V.
19) RAIN7T = 1400 Ohm maximum and 830 Ohm typical in the VDDM = 3.3 V ± 5% range.
20) The DC current at the pin is limited to 3 mA for the operational lifetime.
clock
generation
ADC kernel
f
ADC
interrupts,
etc.
divider for
divider for
fADCI
f
ADCD
digital clock
analog clock
f
ADCI
f
ADCD
registers
analog part
arbiter
ADC_clocking
Figure 17
ADC0/ADC1 Clock Circuit
Table 12
Conversion Time (Operating Conditions apply)
Parameter
Symbol Value
Unit Note
Conversion
time with
tC CC 2 × TADC + (4 + STC + n) × TADCI μs
n = 8, 10, 12 for
n - bit conversion
post-calibration
T
T
ADC = 1 / fADC
ADCI = 1 / fADCI
Conversion
2 × TADC + (2 + STC + n) × TADCI
time without
post-calibration
Data Sheet
136
V1.1, 2009-05
TC1197
Electrical Parameters
Analog Input Circuitry
RAIN, On
REXT
ANx
VAIN
CEXT
CAINSW
=
C
AINTOT - CAINSW
VAGNDx
RAIN7T
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
C
AREFTOT - CAREFSW
CAREFSW
VAGNDx
Analog_InpRefDiag
Figure 18
ADC0/ADC1 Input Circuits
Ioz1
300nA
200nA
100nA
V IN [V D D M % ]
-100nA
-300nA
3%
97% 100%
AD C Leakage 10.vsd
Figure 19
ADC0/ADC1Analog Inputs Leakage
Data Sheet
137
V1.1, 2009-05
TC1197
Electrical Parameters
5.2.3
Fast Analog to Digital Converter (FADC)
All parameters apply to FADC used in differential mode, which is the default and the
intended mode of operation, and which takes advantage of many error cancelation
effects inherent to differential measurements in general.
Table 13
FADC Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ. Max.
9)
DNL error
EFDNL CC –
EFINL CC –
–
–
–
±1
±4
±5
LSB
LSB
%
9)
INL error
Gradient error9)
EFGRAD
–
Without calibration
gain 1, 2, 4
CC
–
–
±6
%
Without calibration
gain 8
Offset error9)1)
EFOFF
EFREF
–
–
–
–
–
–
±203)
±903)
±60
mV
mV
mV
With calibration1)
Without calibration
–
2)
CC
Reference error of
internal VFAREF/2
CC
Analog supply
voltages
VDDMF SR 3.13
VDDAF SR 1.42
–
–
–
3.474)
1.585)
0.1
V
V
V
–
–
–
Analog ground
voltage
VSSAF
-0.1
SR
SR
Analog reference
voltage
VFAREF
VFAGND
3.13
–
3.474)6)
V
Nominal 3.3 V
Analog reference
ground
V
SSAF - –
V
SSAF + V
–
–
SR 0.05 V
0.05 V
Analog input voltage VAINF
VFAGND
–
VDDMF
V
range
SR
Analog supply
currents
IDDMF SR –
IDDAF SR –
–
–
–
15
mA
mA
–
7)
12
Input current at
VFAREF
IFAREF
–
–
–
120
μA
rms
Independent of
conversion
CC
CC
CC
Input leakage current IFOZ2
–
–
±500
±8
nA
0 V < VIN < VDDMF
8)
at VFAREF
Input leakage current IFOZ3
μA
0 V < VIN < VDDMF
8)
at VFAGND
Data Sheet
138
V1.1, 2009-05
TC1197
Electrical Parameters
Table 13
FADC Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
CC –
Typ. Max.
Conversion time
Converter Clock
tC
–
21
CLK
For 10-bit conv.
of fADC
fFADC SR –
–
–
90
MHz
–
9)
Input resistance of
the analog voltage
path (Rn, Rp)
RFAIN
100
200
kΩ
CC
Channel Amplifier
Cutoff Frequency9)
fCOFF
tSET
2
–
–
–
5
MHz
–
–
CC
Settling Time of a
Channel Amplifier
after changing ENN
or ENP9)
CC –
μs
1) Calibration should be performed at each power-up. In case of continuous operation, calibration should be
performed minimum once per week, or on regular basis in order to compensate for temperature changes.
2) The offset error voltage drifts over the whole temperature range maximum ±6 LSB.
3) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must
be multiplied with the applied gain.
4) Voltage overshoots up to 4 V are permissible, provided the pulse duration is less than 100 μs and the
cumulated summary of the pulses does not exceed 1 h.
5) Voltage overshoots up to 1.7 V are permissible, provided the pulse duration is less than 100 μs and the
cumulated sum of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the normal operating conditions (voltage
overshoots).
7) Current peaks of up to 40 mA with a duration of max. 2 ns may occur
8) This value applies in power-down mode.
9) Not subject to production test, verified by design / characterization.
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized. The offset calibration must run first,
followed by the gain calibration.
Data Sheet
139
V1.1, 2009-05
TC1197
Electrical Parameters
FADC Analog Input Stage
RN
FAINxN
-
+
VFAREF/2
VFAGND
+
RP
FAINxP
-
FADC Reference Voltage
Input Circuitry
VFAREF
IFAREF
VFAREF
VFAGND
FADC_InpRefDiag
Figure 20
FADC Input Circuits
Data Sheet
140
V1.1, 2009-05
TC1197
Electrical Parameters
5.2.4
Oscillator Pins
Table 14
Oscillator Pins Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ. Max.
Frequency Range
fOSC CC 4
–
–
–
–
–
40
MHz Direct Input Mode
selected
8
25
MHz External Crystal
Mode selected
Input low voltage at VILX SR -0.2
0.3 ×
VDDOSC3
V
–
XTAL11)
Input high voltage at VIHX SR 0.7 ×
VDDOSC3
+ 0.2
V
–
XTAL11)
VDDOSC3
Input current at
XTAL1
IIX1 CC –
±25
μA
0 V < VIN < VDDOSC3
1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 × VDDOSC3 is
necessary.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal
supplier.
5.2.5
Temperature Sensor
Table 15
Temperature Sensor Characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
Temperature sensor range TSR SR
-40
150 °C
Junction
temperature
Temperature sensor
measurement time
tTSMT SR
–
–
100 μs
–
Start-up time after reset
Sensor accuracy
tTSST SR
TTSA CC
–
–
–
–
10
μs
–
±6
°C
Calibrated
Data Sheet
141
V1.1, 2009-05
TC1197
Electrical Parameters
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bitfield of the DTSSTAT register.
(1)
DTSSTATRESULT – 619
Tj = -----------------------------------------------------------------
2, 28
Data Sheet
142
V1.1, 2009-05
TC1197
Electrical Parameters
5.2.6
Power Supply Current
The default test conditions (differences explicitly specified) are:
VDD=1.58 V, VDD=3.47 V, fCPU=180 MHz, Tj=150oC
Table 16
Power Supply Currents (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
Core active mode
supply current1)2)
IDD
CC –
–
600 mA
f
CPU=180 MHz
fCPU/fSYS = 2:1
Realistic core active
–
–
430 mA
VDD = 1.53 V,
mode supply current 3) 4)
TJ = 150oC
PLL 1.5 V supply
PLL 3.3 V supply
IDDPF
CC –
–
–
–
4
mA
mA
mA
–
4)
IDDPF3 CC –
IDDMF CC –
5
–
FADC 3.3 V analog
supply current
15
–
4)
FADC 1.5 V analog
supply current
IDDAF
CC –
–
–
–
12
mA
–
Flash memory 3.3 V
supply current
IDDFL3R CC –
IDDFL3E CC –
125 mA continuously reading
the Flash memory 5)
120 mA Flash memory
erase-verify 6)
4)
Oscillator 1.5 V supply IDDOSC CC –
Oscillator 3.3 V supply IDDOSC3 CC –
–
–
–
–
–
3
mA
mA
–
–
4)
10
30
30
54
LVDS 3.3 V supply
ILVDS
IDDP
–
mA in total for four pairs
4) 7)
Pad currents, sum of
CC –
mA
mA
–
V
DDP 3.3 V supplies
IDDP_FP CC –
I
DDP including Data
Flash programming
current 7) 8)
ADC 5 V power supply IDDM
CC –
SR –
–
–
6
mA ADC0/1/2
Maximum Average
Power Dissipation1)
PD
1800 mW worst case
TA = 125oC,
PD × RΘJA < 25oC
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each custom
application will most probably be lower than this value, but must be evaluated separately.
2) The IDD decreases typically by 120 mA if the fCPU decreases by 50 MHz, at constant TJ = 150oC, for the
Infineon Max Power Loop.
The dependency in this range is, at constant junction temperature, linear.
Data Sheet
143
V1.1, 2009-05
TC1197
Electrical Parameters
3) The IDD decreases by typically 70 mA if the fCPU is decreased by 50 MHz, at constant TJ = 150oC, for the
Realistic Pattern.
The dependency in this range is, at constant junction temperature, linear.
4) Not tested in production separately, verified by design / characterization.
5) This value assumes worst case of reading flash line with all cells erased. In case of 50% cells written with “1”
and 50% cells written with “0”, the maximum current drops down to 95 mA.
6) Relevant for the power supply dimensioning, not for thermal considerations.
In case of erase of Data Flash, internal flash array loading effects may generate transient current spikes of up
to 15 mA for maximum 5 ms.
7) No GPIO and EBU activity, LVDS off
8) This value is relevant for the power supply dimensioning. The currents caused by the GPIO and EBU activity
depend on the particular application and should be added separately. If two Flash modules are programmed
in parallel, the current increase is 2 × 24 mA.
Data Sheet
144
V1.1, 2009-05
TC1197
Electrical Parameters
5.3
AC Parameters
All AC parameters are defined with the temperature compensation disabled. That
means, keeping the pads constantly at maximum strength.
5.3.1
Testing Waveforms
VDDP
VDDEBU
90%
90%
10%
10%
VSS
tR
tF
rise_fall
Figure 21
Rise/Fall Time Parameters
VDDP
VDDEBU
VDDE / 2
VDDE / 2
Test Points
VSS
mct04881_a.vsd
Figure 22
Testing Waveform, Output Delay
VLoad+ 0.1 V
VLoad- 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VOL - 0.1 V
MCT04880_new
Figure 23
Testing Waveform, Output High Impedance
Data Sheet
145
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.2
Output Rise/Fall Times
Table 17
Output Rise/Fall Times (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note / Test Condition
Min. Typ. Max.
Class A1 Pads
Rise/fall times1)
t
RA1, tFA1
–
–
50
140
18000
150
550
ns
ns
Regular (medium) driver, 50 pF
Regular (medium) driver, 150 pF
Regular (medium) driver, 20 nF
Weak driver, 20 pF
Weak driver, 150 pF
Weak driver, 20 000 pF
65000
Class A2 Pads
Rise/fall times
tRA2, tFA2
–
–
3.7
7.5
7
18
Strong driver, sharp edge, 50 pF
Strong driver, sharp edge, 100pF
Strong driver, med. edge, 50 pF
Strong driver, soft edge, 50 pF
Medium driver, 50 pF
1)
50
140
18000
150
550
65000
Medium driver, 150 pF
Medium driver, 20 000 pF
Weak driver, 20 pF
Weak driver, 150 pF
Weak driver, 20 000 pF
Class B Pads 3.3V ± 5%
Rise/fall times tRB, tFB
–
–
–
–
3.0
3.7
7.5
ns
ns
35 pF
50 pF
100 pF
1)2)
Class B Pads 2.5V ± 5%
Rise/fall times tRB, tFB
3.7
4.6
9.0
35 pF
50 pF
100 pF
1)3)
Class F Pads
Rise/fall times
Rise/fall times
t
RF1, tRF1
RF2, tRF2
–
–
–
–
2
ns
ns
LVDS Mode
t
60
CMOS Mode, 50 pF
1) Not all parameters are subject to production test, but verified by design/characterization and test correlation.
2) Parameter test correlation for VDDEBU = 2.5 V ± 5%
3) Parameter test correlation for VDDEBU = 2.5 V ± 5%
Data Sheet
146
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.3
Power Sequencing
V
+-5%
5V
VAREF
+-5%
3.3V
1.5V
-12%
+-5%
0.5V
-12%
0.5V
0.5V
t
VDDP
PORST
power
down
power
fail
t
Power-Up 8.vsd
Figure 24
5 V / 3.3 V / 1.5 V Power-Up/Down Sequence
The following list of rules applies to the power-up/down sequence:
• All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
• At any moment,
each power supply must be higher than any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.5 - 0.5 V;VDD3.3 > VDD1.5 - 0.5 V, see
Figure 24.
• During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.5 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than
100 mV. On the other hand, all power supply pins with the same name (for example
Data Sheet
147
V1.1, 2009-05
TC1197
Electrical Parameters
all VDDP ), are internally directly connected. It is recommended that the power pins
of the same voltage are driven by a single power supply.
• The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.5, and VAREF
power-supplies and the oscillator have reached stable operation, within the normal
operating conditions.
• At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
• At power fail the PORST signal must be activated at latest when any 3.3 V or 1.5 V
power supply voltage falls 12% below the nominal level. The same limit of 3.3 V-12%
applies to the 5 V power supply too. If, under these conditions, the PORST is
activated during a Flash write, only the memory row that was the target of the write
at the moment of the power loss will contain unreliable content. In order to ensure
clean power-down behavior, the PORST signal should be activated as close as
possible to the normal operating voltage range.
• In case of a power-loss at any power-supply, all power supplies must be powered-
down, conforming at the same time to the rules number 2 and 4.
• Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
• Aditionally, regarding the ADC reference voltage VAREF:
– VAREF must power-up at the same time or later than VDDM, and
– VAREF must power-down eather earlier or at latest to satisfy the condition
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF
filter capacitance through the ESD diodes through the VDDM power supply. In
case of discharging the reference capacitance through the ESD diodes, the
current must be lower than 5 mA.
Data Sheet
148
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.4
Power, Pad and Reset Timing
Table 18
Power, Pad and Reset Timing Parameters
Parameter
Symbol
Values
Unit Note /
Test Con
Min.
Typ. Max.
dition
Min. VDDP voltage to ensure
V
DDPPA CC 0.6
–
–
V
–
defined pad states1)
Oscillator start-up time2)
tOSCS CC –
SR 10
–
–
10
–
ms
ms
–
–
Minimum PORST active time tPOA
after power supplies are stable
at operating levels
ESR0 pulse width
tHD
CC Program –
mable3)5)
–
fSYS
–
PORST rise time
tPOR
tPOS
SR –
SR 0
–
–
50
–
ms
ns
–
–
Setup time to PORST rising
edge4)
TESTMODE
TRST
Hold time from PORST rising tPOH
edge
SR 100
SR 0
–
–
–
–
–
–
ns
ns
ns
ns
Setup time to ESR0 rising
edge
tHDS
tHDH
tPIP
–
–
HWCFG
Hold time from ESR0 rising
edge
SR 16 ×
–
5)
1/fSYS
Ports inactive after PORST
reset active6)7)
CC –
CC –
150
–
–
Ports inactive after ESR0 reset tPI
8 × 1/ ns
active (and for all logic)
fSYS
Power on Reset Boot Time8) tBP
CC –
–
–
2.5
ms
–
–
Application Reset Boot Time tB
CC 125
575
μs
at fCPU=180MHz9)
1) This parameter is valid under assumption that PORST signal is constantly at low level during the power-
up/power-down of the VDDP
.
2) tOSCS is defined from the moment when VDDOSC3 = 3.13 V until the oscillations reach an amplitude at XTAL1 of
0,3 × VDDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (fFPI) cycles.
Data Sheet
149
V1.1, 2009-05
TC1197
Electrical Parameters
4) Applicable for input pins TESTMODE and TRST.
5) fFPI = fCPU/2
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
user instruction has entered the CPU and its processing starts.
9) The duration of the boot time is defined between the following events:
1. Hardware reset: the falling edge of a short ESR0 pulse and the moment when the first user instruction has
entered the CPU and its processing starts, if the ESR0 pulse is shorter than
SCU_RSTCNTCON.RELSA × TFPI
.
If the ESR0 pulse is longer than SCU_RSTCNTCON.RELSA × TFPI, only the time beyond should be added to
the boot time (ESR0 falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
VDDP -12%
VDDPPA
VDDPPA
VDDP
VDD
VDD -12%
t
POA
t
POA
PORST
t
t
POH
POH
TRST
TESTMODE
t
t
hd
hd
ESR0
t
t
HDH
t
t
HDH
HDH
PI
HWCFG
t
t
PIP
PIP
t
PI
Pads
t
t
t
PI
PI
PI
t
PIP
Pad-state undefined
Tri-state or pull device active
As programmed
reset_beh2
Figure 25
Power, Pad and Reset Timing
Data Sheet
150
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.5
Phase Locked Loop (PLL)
Note: All PLL characteristics defined on this and the next page are not subject to
production test, but verified by design characterization.
Table 19
PLL Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Con
Min.
Typ. Max.
dition
Accumulated jitter
|Dm|
–
–
7
ns
–
VCO frequency range
fVCO
400
8
–
800
16
MHz –
MHz –
MHz –
VCO input frequency range fREF
PLL base frequency1)
–
fPLLBASE
tL
50
–
200
–
320
200
PLL lock-in time
μs
–
1) The CPU base frequency with which the application software starts after PORST is calculated by dividing the
limit values by 16 (this is the K2 factor after reset).
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB-
Bus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the
number m of consecutive fLMB clock periods.
for
(K2 ≤ 100)
and
(m ≤ (fLMB[MHz]) ⁄ 2)
(1 – 0, 01 × K2) × (m – 1)
0, 5 × fLMB[MHz] – 1
(2)
(3)
740
⎛
⎞
⎛
⎝
⎞
--------------------------------------------
----------------------------------------------------------------
+ 0, 01 × K2
Dm[ns] =
+ 5 ×
⎝
⎠
⎠
K2 × fLMB[MHz]
740
--------------------------------------------
+ 5
else
Dm[ns] =
K2 × fLMB[MHz]
Data Sheet
151
V1.1, 2009-05
TC1197
Electrical Parameters
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency fLMB results in a higher absolute maximum jitter value.
Figure 26 gives the jitter curves for several K2 / fLMB combinations.
±10.0
Dm
ns
fLMB = 50 MHz (K2 = 8)
fLMB = 100 MHz (K2 = 4)
±8.0
±7.0
±6.0
fLMB = 180 MHz (K2 = 4)
fLMB = 150 MHz (K2 = 4)
±4.0
fLMB = 100 MHz (K2 = 8)
fLMB = 50 MHz (K2 = 16)
±2.0
±1.0
±0.0
0
20
40
60
80
100
120
oo
m
D
m = Max. jitter
m
K2
= Number of consecutive fLMB periods
= K2-divider of PLL
TC1797_PLL_JITT_M
Figure 26
Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies fLMB
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
not exceed CL = 20 pF with the maximum driver and sharp edge. In case of
applications with many pins with high loads, driver strengths and toggle rates the
specified jitter values could be exceeded.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
V
V
DDOSC3 at pin E26 and VSSOSC at pin F25, is limited to a peak-to-peak voltage of
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V
V
DDOSC at pin F26 and VSSOSC at pin F25, is limited to a peak-to-peak voltage of
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise
frequencies above 300 KHz.
Data Sheet
152
V1.1, 2009-05
TC1197
Electrical Parameters
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
153
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.6
BFCLKO Output Clock Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%,;
TA = -40 °C to +125 °C; CL = 35 pF
Table 20
BFCLK0 Output Clock Timing Parameters1)
Parameter
Symbol
Values
Unit Note /
Test Con
Min.
BFCLKO CC 13.332)
Typ. Max.
dition
BFCLKO clock period
BFCLKO high time
BFCLKO low time
BFCLKO rise time
BFCLKO fall time
t
–
–
ns
ns
ns
ns
ns
%
–
–
–
–
–
–
t5
t6
t7
t8
CC 3
–
–
CC 3
CC –
–
–
–
–
3
–
3
CC
BFCLKO duty cycle t5/(t5 + t6)3) DC
45
50
55
1) Not subject to production test, verified by design/characterization.
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K divider has to
be regarded.
tBFCLKO
0.9 VDD
0.5 VDDP05
BFCLKO
0.1 VDD
t8
t7
t5
t6
MCT04883_mod
Figure 27
BFCLKO Output Clock Timing
Data Sheet
154
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.7
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 21
JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
25
12
10
–
Typ.
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
–
–
–
–
–
–
–
–
–
4
4
–
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
TCK low time
TCK clock rise time
TCK clock fall time
–
TDI/TMS setup
6
to TCK rising edge
TDI/TMS hold
t7 SR
6
–
–
ns
–
after TCK rising edge
TDO valid after TCK falling t8 CC
–
–
2
–
–
–
13
3
ns
ns
ns
CL = 50 pF
CL = 20 pF
edge1) (propagation delay)
t8 CC
TDO hold after TCK falling t18 CC
–
edge1)
TDO high imped. to valid t9 CC
–
–
–
–
14
ns
ns
CL = 50 pF
CL = 50 pF
from TCK falling edge1)2)
TDO valid to high imped. t10 CC
13.5
from TCK falling edge1)
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
155
V1.1, 2009-05
TC1197
Electrical Parameters
t1
0.9 VDDP
0.5 VDDP
0.1 VDDP
t5
t4
t2
t3
MC_JTAG_TCK
Figure 28
Test Clock Timing (TCK)
TCK
t6
t7
TMS
t6
t7
TDI
t9
t8
t10
TDO
t18
MC_JTAG
Figure 29
JTAG Timing
Data Sheet
156
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.8
DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 22
DAP Interface Timing Parameters
(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
DAP0 clock period
DAP0 high time
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
12.5
–
–
–
–
–
–
–
–
–
2
2
–
ns
ns
ns
ns
ns
ns
–
4
4
–
–
6
–
–
–
–
–
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup
to DAP0 rising edge
DAP1 hold
after DAP0 rising edge
t17 SR
t19 SR
t19 SR
6
–
–
–
–
–
–
ns
ns
ns
–
DAP1 valid
8
80 MHz,
CL = 20 pF
per DAP0 clock period1)
10
40 MHz,
CL = 50 pF
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VDDP
0.1 VDDP
0.5 VDDP
t15
t14
t12
t13
MC_DAP0
Figure 30
Test Clock Timing (DAP0)
Data Sheet
157
V1.1, 2009-05
TC1197
Electrical Parameters
DAP0
DAP1
t16
t17
MC_DAP1_RX
Figure 31
DAP Timing Host to Device
t11
DAP1
t19
MC_DAP1_TX
Figure 32
DAP Timing Device to Host
Data Sheet
158
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.9
EBU Timings
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40 °C to +125 °C; CL = 35 pF for address/data; CL = 40pF for the control lines.
5.3.9.1 EBU Asynchronous Timings
For each timing, the accumulated PLL jitter of the programed duration in number of clock
periods must be added separately. Operating conditions apply and CL = 35 pF.
Table 23
Common timing parameters for all asynchronous timings1)
Symbol Limit Values Unit Edge
Parameter
Setting
min
max
1.5
1
Pulse width deviation from the ideal
programmed width due to the A2 pad
asymmetry, strong driver mode,
rise delay - fall delay. CL = 35 pF.
ta
CC -1
ns
sharp
-2
medium
AD(31:0) output delay to ADV rising edge, t13
CC -5.5
CC -5.5
2
2
–
–
multiplexed
AD(31:0) output delay
t14
read / write
1) Not subject to production test, verified by design/characterization.
Data Sheet
159
V1.1, 2009-05
TC1197
Electrical Parameters
Read Timings
Table 24
Asynchronous read timings, multiplexed and demultiplexed1)
Symbol Limit Values
Parameter
Unit
min
CC -2.5
CC -2.5
CC -2
max
2.5
2.5
2.5
4.5
2.5
–
A(23:0) output delay
A(23:0) output delay
CS rising edge
to RD rising edge,
deviation from the ideal
programmed value.
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
ns
ADV rising edge
BC rising edge
CC -1.5
CC -2.5
SR 12
SR 0
WAIT input setup
WAIT input hold
Data input setup
Data input hold
–
SR 12
SR 0
–
–
MR / W output delay
CC -2.5
1.5
1) Not subject to production test, verified by design/characterization.
Data Sheet
160
V1.1, 2009-05
TC1197
Electrical Parameters
Multiplexed Read Timing
Address
Phase
Address Hold
Phase (opt.) Delay Phase
Command
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
EBU
STATE
Control Bitfield:
ADDRC
1...15
AHOLDC
0...15
CMDDELAY
0...7
RDWAIT
1...31
RDRECOVC
0...15
ADDRC
1...15
Duration Limits in
EBU_CLK Cycles
Next
A[23:0]
Valid Address
Addr.
pv +
pv +
pv +
t2
t0
ta
t1
CS[3:0]
CSCOMB
pv +
pv +
t3
ta
ADV
pv +
pv +
ta
RD
pv +
ta
t4
ta
BC[3:0]
pv +
t5
t6
WAIT
pv +
t14
pv +
t13
t7
t8
Address Out
AD[31:0]
MR/W
Data In
pv +
t9
pv = programmed value,
new_MuxRD_Async_10.vsd
T
EBU_CLK * sum (correponding bitfield values)
Figure 33
Multiplexed Read Access
Data Sheet
161
V1.1, 2009-05
TC1197
Electrical Parameters
Demultiplexed Read Timing
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
EBU
STATE
Control Bitfield:
ADDRC
1...15
AHOLDC
0...15
RDWAIT
1...31
RDRECOVC
0...15
ADDRC
1...15
Duration Limits in
EBU_CLK Cycles
Next
A[23:0]
Valid Address
pv +
Addr.
pv +
t2
t0
t1
pv +
ta
CS[3:0]
CSCOMB
pv +
pv +
t3
ta
ADV
pv +
ta
RD
pv +
ta
t4
pv +
ta
BC[3:0]
pv +
t5
t6
WAIT
t7
t8
AD[31:0]
MR/W
Data In
pv +
t9
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
new_DemuxRD_Async_10.vsd
Figure 34
Demultiplexed Read Access
Data Sheet
162
V1.1, 2009-05
TC1197
Electrical Parameters
Write Timings
Table 25
Asynchronous write timings, multiplexed and demultiplexed1)
Symbol Limit Values
Parameter
Unit
min
t30 CC -2.5
t31 CC -2.5
t32 CC -2
t33 CC -2
t34 CC -2.5
t35 SR 12
t36 SR 0
max
2.5
2.5
2
A(23:0) output delay to RD/WR rising edge,
ns
deviation from the ideal
programmed value.
CS rising edge
A(23:0) output delay
ADV rising edge
BC rising edge
4.5
2
WAIT input setup
WAIT input hold
Data output delay
Data output delay
MR / W output delay
–
–
t37 CC -5.5
t38 CC -5.5
t39 CC -2.5
2
2
1.5
1) Not subject to production test, verified by design/characterization.
Data Sheet
163
V1.1, 2009-05
TC1197
Electrical Parameters
Multiplexed Write Timing
Data
Hold Phase
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
EBU
STATE
Control Bitfield:
ADDRC
1...15
AHOLDC
0...15
RDWAIT
1...31
DATAC
0...15
RDRECOVC
0...15
ADDRC
1...15
Duration Limits in
EBU_CLK Cycles
Next
A[23:0]
Valid Address
Addr.
pv +
t30
pv +
t31
pv +
ta
pv +
t32
CS[3:0]
CSCOMB
pv +
t33
pv +
ta
ADV
pv +
ta
RD/WR
BC[3:0]
pv +
ta
pv +
ta
t34
t35
WAIT
t36
t14
t37
pv +
pv +
t13
t38
AD[31:0]
Data Out
Address Out
pv +
t39
MR/W
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
new_MuxWR_Async_10.vsd
Figure 35
Multiplexed Write Access
Data Sheet
164
V1.1, 2009-05
TC1197
Electrical Parameters
Demultiplexed Write Timing
Data
Hold Phase
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
EBU
STATE
Control Bitfield:
ADDRC
1...15
AHOLDC
0...15
RDWAIT
1...31
DATAC
0...15
RDRECOVC
0...15
ADDRC
1...15
Duration Limits in
EBU_CLK Cycles
Next
A[23:0]
Valid Address
Addr.
pv +
t30
pv +
t31
pv +
ta
pv +
t32
CS[3:0]
CSCOMB
pv +
t33
pv +
ta
ADV
pv +
ta
RD/WR
BC[3:0]
pv +
ta
pv +
ta
t34
t35
WAIT
t36
t37
pv +
t38
AD[31:0]
MR/W
Data Out
pv +
t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
new_DemuxWR_Async_10.vsd
Figure 36
Demultiplexed Write Access
Data Sheet
165
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.9.2 EBU Burst Mode Access Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40 °C to +125 °C; CL = 35 pF;
Table 26
EBU Burst Mode Read / Write Access Timing Parameters1)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
Output delay from BFCLKO
active edge2)
t10 CC -2
–
–
–
–
–
–
–
–
–
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
RDandRD/WRactive/inactive t12 CC -2
2
–
–
–
–
–
–
–
–
after BFCLKO active edge3)
CSx output delay from
BFCLKO active edge3)
t21
t22
CC -2.5
CC -2
1.5
2
ADV active/inactive after
BFCLKO active edge4)
BAA active/inactive after
BFCLKO active edge4)
t22a CC -2.5
1.5
–
Data setup to BFCLKI rising
edge5)
t23
SR 3
SR 0
SR 3
SR 0
Data hold from BFCLKI rising t24
–
edge5)
WAIT setup (low or high) to
BFCLKI rising edge5)
t25
–
WAIT hold (low or high) from t26
–
BFCLKI rising edge5)
1) Not subject to production test, verified by design/characterization.
2) This is a default parameter which are applicable to all timings which are not explicitly covered by the other
parameters.
3) An active edge can be rising or falling edge, depending on the settings of bits BFCON.EBSE / ECSE and clock
divider ratio.
Negative minimum values for these parameters mean that the last data read during a burst may be corrupted.
However, with clock feedback enabled, this value is oversampling not required for the LMB transaction and
will be discarded.
4) This parameter is valid for BUSCONx.EBSE = 1 and BUSAPx.EXTCLK = 00B.
For BUSCONx.EBSE = 1 and other values of BUSAPx.EXTCLK, ADV and BAA will be delayed by 1 / 2 of the
LMB bus clock period TCPU = 1 / fCPU
.
For BUSCONx. EBSE = 0 and BUSAPx.EXTCLK = 11B, add 2 LMB clock periods.
For BUSCONx. EBSE = 0 and other values of BUSAPx.EXTCLK add 1 LMB clock period.
Data Sheet
166
V1.1, 2009-05
TC1197
Electrical Parameters
5) If the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as
at asynchronous access. So t5, t6, t7 and t8 from the asynchronous timings apply.
Address
Phase(s)
Command
Phase(s)
Burst
Phase(s)
Burst
Phase(s)
Recovery
Phase(s)
Next Addr.
Phase(s)
BFCLKI
1)
BFCLKO
t10
t10
Next
A[23:0]
ADV
Burst Start Address
Addr.
t22
t22
t22
t21
t21
t21
CS[3:0]
CSCOMB
t12
t12
t22a
t24
RD
RD/WR
t22a
BAA
t24
t23
t23
D[31:0]
(32-Bit)
Data (Addr+0)
Data (Addr+4)
D[15:0]
(16-Bit)
Data (Addr+0)
Data (Addr+2)
t26
t25
WAIT
1)
Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRDWR_4.vsd
Figure 37
EBU Burst Mode Read / Write Access Timing
Data Sheet
167
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.9.3 EBU Arbitration Signal Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
TA = -40°C to +125 °C; CL = 35 pF;
Table 27
EBU Arbitration Signal Timing Parameters1)
Parameter
Symbol
Values
Unit Note /
Test Con
Min.
CC –
SR 11
SR 2
Typ. Max.
dition
Output delay from BFCLKO
rising edge
t27
t28
t29
–
–
–
3
–
–
ns
ns
ns
–
Data setup to BFCLKO
falling edge
–
–
Data hold from BFCLKO
falling edge
1) Not subject to production test, verified by design/characterization.
BFCLKO
t27
t27
HLDA Output
t27
t27
BREQ Output
BFCLKO
t28
t29
t28
t29
HOLD Input
HLDA Input
EBUArb_1
Figure 38
EBU Arbitration Signal Timing
Data Sheet
168
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.10
Peripheral Timings
Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.
5.3.10.1 Micro Link Interface (MLI) Timing
MLI Transmitter Timing
t13
t14
t10
t12
TCLKx
t11
t15
t15
TDATAx
TVALIDx
t16
t17
TREADYx
MLI Receiver Timing
t23
t24
t20
t22
RCLKx
t21
t25
t26
RDATAx
RVALIDx
t27
t27
RREADYx
MLI_Tmg_2.vsd
Figure 39
MLI Interface Timing
Data Sheet
169
V1.1, 2009-05
TC1197
Electrical Parameters
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Table 28
MLI Timings (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Typ.
Unit Note /
Test Co
Min.
Max.
ndition
MLI Transmitter Timing
TCLK clock period
TCLK high time
1)
t10
t11
t12
t13
t14
t15
CC 2 × TMLI
–
–
ns
2)3)
0.45 × t10 0.5 × t10 0.55 × t10 ns
CC
2)3)
TCLK low time
CC 0.45 × t10 0.5 × t10 0.55 × t10 ns
4)
TCLK rise time
CC –
CC –
CC -3
–
–
–
ns
ns
ns
–
–
–
4)
TCLK fall time
TDATA/TVALID output
delay time
4.4
TREADY setup time to
TCLK rising edge
t16
t17
SR 18
SR 0
–
–
–
–
ns
ns
–
–
TREADY hold time from
TCLK rising edge
MLI Receiver Timing
RCLK clock period
RCLK high time
1)
t20
t21
t22
SR 1 × TMLI
SR –
–
–
–
ns
ns
ns
5)6)
5)6)
0.5 × t20
RCLK low time
SR –
0.5 × t2 –
0
7)
7)
RCLK rise time
RCLK fall time
t23
R
S
S
S
S
C
–
–
–
–
–
–
4
ns
ns
ns
ns
ns
t24
R
–
4
RDATA/RVALID setup
time to RCLK falling edge
t25
R
4.2
2.2
0
–
–
–
–
RDATA/RVALID hold time t26
from RCLK rising edge
–
R
RREADY output delay time t27
16
C
1) TMLImin. = TSYS = 1/fSYS. When fSYS = 90 MHz, t10 = 22.22 ns and t20 = 11.11 ns.
2) The following formula is valid: t11 + t12 = t10
Data Sheet
170
V1.1, 2009-05
TC1197
Electrical Parameters
3) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
4) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
5) The following formula is valid: t21 + t22 = t20
6) The min. and max. value of is parameter can be adjusted by considering the other receiver timing parameters.
7) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
Data Sheet
171
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.10.2 Micro Second Channel (MSC) Interface Timing
Table 29
MSC Interface Timing (Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Typ.
Unit Note /
Test Con
Min.
Max.
dition
3)
FCLP clock period1)2)
t40 CC 2 × TMSC
t45 CC -10
–
–
ns
ns
–
–
SOP/ENx outputs delay
from FCLP rising edge
10
SDI bit time
SDI rise time
SDI fall time
t46 CC 8 × TMSC
t48 SR
–
ns
ns
ns
–
–
–
100
100
t49 SR
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 × TMSC
.
3) TMSCmin = TSYS = 1 / fSYS. When fSYS = 90 MHz, t40 = 22,2ns
t40
0.9 VDDP
0.1 VDDP
FCLP
t45
t45
SOP
EN
t48
t49
0.9 VDDP
0.1 VDDP
SDI
t46
t46
MSC_Tmg_1.vsd
Figure 40
MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
172
V1.1, 2009-05
TC1197
Electrical Parameters
5.3.10.3 SSC Master/Slave Mode Timing
Table 30
SSC Master/Slave Mode Timing
(Operating Conditions apply), CL = 50 pF
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Con
dition
Min.
Master Mode Timing
1)2)3)
SCLK clock period
t50
t51
CC 2 × TSSC
–
–
–
8
ns
MTSR/SLSOx delay from
SCLK rising edge
0
ns
ns
ns
–
CC
3)
MRST setup to SCLK
falling edge
t52
t53
SR 13
SR 0
–
–
–
–
3)
MRST hold from SCLK
falling edge
Slave Mode Timing
SCLK clock period
SCLK duty cycle
1)3)
t54
SR 4 × TSSC
–
–
–
–
ns
%
t55/t54 SR 45
55
–
–
3)4)
MTSR setup to SCLK
latching edge
t56
t57
t58
t59
t60
SR TSSC + 5
ns
3)4)
3)
MTSR hold from SCLK
latching edge
SR TSSC + 5
SR TSSC + 5
SR 7
–
–
–
–
–
–
ns
ns
ns
ns
ns
SLSI setup to first SCLK
shift edge
–
SLSI hold from last SCLK
latching edge
–
–
–
–
MRST delay from SCLK
shift edge
CC 0
15
12
SLSI to valid data on MRST t61
CC –
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 × TSSC
.
3) TSSCmin = TSYS = 1/fSYS. When fSYS = 90 MHz, t50 = 22.2 ns.
4) Fractional divider switched off, SSC internal baud rate generation used.
Data Sheet
173
V1.1, 2009-05
TC1197
Electrical Parameters
t50
SCLK1)2)
MTSR1)
t51
t51
t52
t53
Data
valid
MRST1)
SLSOx2)
t51
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM
Figure 41
SSC Master Mode Timing
t54
First latching
SCLK edge
Last latching
SCLK edge
First shift
SCLK edge
SCLK1)
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
t61
t59
t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_TmgSM
Figure 42
SSC Slave Mode Timing
Data Sheet
174
V1.1, 2009-05
TC1197
Electrical Parameters
5.4
Package and Reliability
5.4.1
Package Parameters
Table 31
Device
Thermal Characteristics of the Package
Package
RΘJCT1) RΘJCB1) Unit
Note
TC1197
PG-BGA-416-10
4
6
K/W
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the
case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
R
TJA can be obtained from the upper four partial thermal resistances.
Data Sheet
175
V1.1, 2009-05
TC1197
Electrical Parameters
5.4.2
Package Outline
25 x 1 = 25
A26
A1
AF1
1
+0.07
416x
ø0.63
-0.13
M
ø0.25
A B C
C
0.15
C
M
ø0.1
A
Index Marking
0.2
0.5
0.2
20
24
27
Index Marking
(sharp edge)
B
PG-BGA-416-4, -10, -13, -14-PO V02
Figure 43
Package Outlines PG-BGA-416-10, Plastic (Green) Ball Grid Array
Data Sheet
176
V1.1, 2009-05
TC1197
Electrical Parameters
You can find all of our packages, sorts of packing and others in Infineon Internet Page.
5.4.3
Flash Memory Parameters
The data retention time of the TC1197’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Table 32
Flash Parameters
Symbol
Parameter
Values
Unit
Note /
Test Condition
Min.
Typ. Max.
Program Flash
tRET
20
–
–
–
–
–
years Max. 1000
erase/program
Retention Time,
CC
Physical Sector1)2)
cycles
Program Flash
Retention Time
Logical Sector1)2)
tRETL
20
–
years Max. 100
CC
CC
CC
erase/program
cycles
Data Flash
Endurance
(64 KB)
NE
30 000 –
120000 –
cycles Max. data
retention time
5 years
Data Flash Endurance, NE8
EEPROM Emulation
(4 × 16 KB)
cycles Max. data
retention time
5 years
Programming Time
per Page3)
tPR
–
–
–
–
–
–
–
–
5
ms
s
–
CC
CC
CC
CC
Program Flash Erase
Time per 256-KB Sector
tERP
5
f
CPU = 180 MHz
CPU = 180 MHz
Data Flash Erase Time tERD
for 2 × 32-KB Sectors
2.5
s
f
Wake-up time
tWU
4000/fCPU μs
+ 180
–
1) Storage and inactive time included.
2) At average weighted junction temperature Tj = 100oC, or
the retention time at average weighted temperature of Tj = 110oC is minimum 10 years, or
the retention time at average weighted temperature of Tj = 150oC is minimum 0.7 years.
3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
Data Sheet
177
V1.1, 2009-05
TC1197
Electrical Parameters
5.4.4
Quality Declarations
Table 33
Quality Parameters
Symbol
Parameter
Values
Unit Note / Test Condition
Min. Typ. Max.
Operation
Lifetime1)
tOP
–
–
24000 hours –2) 3)
ESD susceptibility VHBM
according to
–
–
2000
V
Conforming to
JESD22-A114-B
Human Body
Model (HBM)
ESD susceptibility VHBM1
of the LVDS pins
–
–
–
–
500
500
V
V
–
ESD susceptibility VCDM
according to
Conforming to
JESD22-C101-C
Charged Device
Model (CDM)
Moisture
Sensitivity Level
MSL
–
–
3
–
Conforming to Jedec
J-STD-020C for 240°C
1) This lifetime refers only to the time when the device is powered on.
2) For worst-case temperature profile equivalent to:
2000 hours at Tj = 150oC
16000 hours at Tj = 125oC
6000 hours at Tj = 110oC
3) This 30000 hours worst-case temperature profile is also covered:
300 hours at Tj = 150oC
1000 hours at Tj = 140oC
1700 hours at Tj = 130oC
24000 hours at Tj = 120oC
3000 hours at Tj = 110oC
Data Sheet
178
V1.1, 2009-05
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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