TC1920_技术文档

Data Sheet, V 1.3, Oct. 2003

TC1920

32-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2003-10

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

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list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Data Sheet, V 1.3, Oct. 2003

TC1920

32-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

TC1920

Preliminary

Revision History:

2003-10

V 1.3

Previous Version:

1.2

Page

Subjects (major changes since last revision)

ASC and SSC baudrates calculated for 50 MHz

DC parameters updated with characterization values

AC parameters updated with characterization values

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

TC1920

Preliminary

TC1920 Features

The TC1920 offers a 32 bit TriCore based microcontroller/DSP, which is mainly designed

for automotive telematics applications. Due to its high integration, this microcontroller/

DSP offers high system performance at minimized cost. Typical telematics functions

processed by RISC-, DSP- and speech- (CODEC) modules are now combined in one

component. The combination of dedicated automotive peripherals (CAN, J1850) and

standard peripherals (ADC, SSC/SPI, ASC and IIC), makes this microcontroller/DSP the

engine tailored for a wide variety of telematics applications such as navigation,

emergency call, speech interface or communication interface.

• TriCore CPU/DSP with 4-Stage Pipeline:

– 100 MHz max. CPU clock frequency, 50 MHz max. FPI Bus clock frequency.

– 32-bit super-scalar TriCore main CPU

– 4-GByte unified memory space support

– Fast context-switching

– Dual 16 x 16 Multiply-Accumulate (MAC) Unit

– 64-bit Local Memory Bus (LMB)

– 32-bit Flexible Peripheral Interface (FPI)

– 32-bit wide external bus unit (EBU)

• 32-bit Peripheral Control Processor (PCP2) with DMA-support

• On-chip memories:

– 24 KByte Code Scratch-Pad RAM (CSRAM)

– 8 KByte Instruction Cache (ICACHE)

– 24 KByte Data Scratch-Pad RAM (DSRAM)

– 8 KByte Data Cache (DCACHE)

– 64 KByte fast LMB SRAM

– 16 KByte FPI SRAM (of which 8 KByte Stand-By SRAM)

– 20 KByte PCP RAM: 16 KByte Code and 4 KByte Data SRAM

– 32 KByte Boot ROM

• Product Specific Peripherals:

– 14-bit double CODEC with flexible sample rates and FIFO support

• Automotive Peripherals:

– Two independent CAN-nodes (TwinCAN) with gateway support

– J1850 (SDLM)

• Standard Peripherals:

– 6-channel, 8-/10-/12-bit ADC

– 3 x asynchronous serial interface (ASC) with IrDa-support

– 1 SPI-compatible synchronous serial interface

– 2-channel IIC

– 6 x 32 bit timer

– ≥ 16 I/O- and interrupt pins (GPIO)

• General Peripherals:

– Real time clock (RTC)

Data Sheet

1

V 1.3, 2003-10

TC1920

Preliminary

– Watchdog timer (WDT)

• Clock Generation Unit with PLL

• Debug Support:

– Debug Interface (OCDS level 2) with Trace Port

• Power saving features

• Dual voltage supply (1.8V core, 3.3V I/O)

• -40°C to +85°C temperature range

• LBGA-260 package

Data Sheet

2

V 1.3, 2003-10

TC1920

Preliminary

Block Diagram

The figure below shows the block diagram of the TC1920 device.

LFI

Bridge

SRAM

64 kB

EBU

32 bit External M em ory Bus

ADC

ASC0

ASC1

ASC2

SSC

64-bit Local M em ory Bus (LM B)

MMU

CODEC

GPTU0

GPTU1

PMU

DMU

24KB

CSRAM

8KB

TriCore

(TC1.3)

DSRAM

8KB

DCACHE

ICACHE

CPS

Port

Control

IIC

PCODE

16kB

PRAM

4kB

PCP2

OCDS

Debug

Interface

/JTAG

Twin

CAN

FPI-Bus Interface

J1850

32-bit Flexible Peripheral Interface (FPI)Bus

Boot

ROM

32kB

SRAM

16kB

RTC

STM

SCU

TC1920

Figure 1

TC1920 Device Block Diagram

Data Sheet

3

V 1.3, 2003-10

TC1920

Preliminary

Target applications

• On-board and off-board navigation

• Emergency call systems

• Car speech interface

• Car communication interface

• Gateways: automotive - infotainment

• Occupant Sensing

• Drowsiness detection

• Rear- & side-mirror replacement

• Pre-crash sensing

Logical Symbol

Alternate Functions

G P IO /EX Ix,

PLL_CTRL

TEST

Port 0

8-bit

Codec Bypass

GPIO /

G PTU1

Port 1

8-bit

CLKOUT

HDRST

PO RST

General

Control

CAN0/1 / J1850 / SSC

A SC 0 / IIC

Port 2

16-bit

A SC 1/2 / AD CM U X

AD CE XTIN / G PTU 0

Port 3

16-bit

NMI

BYPASS

6

ADC

XTAL1

XTAL2

XTAL3

10

CODEC 0/1

XTAL4

V_DDOSC1

83

O scillators

PLL

V_SSOSC1

V_DDOSC2

V_SSOSC2

V_DDPLL

TC1920

External Bus Interface

16

Port 5

GPIO / Trace

V_SSPLL

8

O CDS/JTAG

Control

V_DD

V_DDP

V_DDSB

V_SS

D igital Circuitry

P ower Supply

V_{DD_COD0}

V_{SS_COD0}

V_{DD_COD1}

V_{SS_COD1}

V_{REF_CO D}

V_{GND_COD}

CO DEC

V_DDA

V_SSA

Analog Power

Supply

ADC Analog

Power Supply

V_AREF

V_AGND

Figure 2

Logical Symbol of the TC1920 Device

Data Sheet

4

V 1.3, 2003-10

TC1920

Preliminary

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

TM_

C TR L1

V_{SS P}

V_DD

_

V_SS

_

V_{SS A}

_

A

B

C

D

E

F

V_SS

V _DDR

V_DD

N MI

A

XTAL3

XTA L1

P 4.5

P4.3

P4.1

AI0-

AI1-

AO+

C EX T

_OSC

OSC1

GUARD

ADC

TM_

C TR L0

POR S

V_{S S}

_

V_SS

_

V _AGND

_

V_{SS P}

V_{RE F}

_

B Y

PA SS

P LLCTRL

_A0

V _SS

AD 31

V_DD

X TA L4

V_{DD R}

V_DD

XTAL2

P4.2

P4.4

A O1-

AO1+

AI1+

AO-

B

T

OS C

P LL

A DC

ADC

COD

V_{DD_}V_{DDP_}V_SS

_

V_DD

V_{DD P}

V_GND

_

V _{SSP_}C OD E C LK

V _SS

AD 27 AD 30

V _DD

P4.0

P2.11

C

D

E

F

C _D IS OU T

OS C2

OSC

GUARD GUARD

ADC

COD

COD0

V_{DDP_}V_{S SP}

_

V_DD

_

V_SSP

_

V_{A REF}

V_{SS P}

V _{SSA_}

V _{S S}

V _SS

AD 26 AD 28 A D 29

H R ST

A I0+

P2.13 P2.10

OSC

P LL

A DC

ADC

COD0

V _{DDP_}

AD 23 AD 24 A D 25 AD 18

AD 19 AD 20 A D 22 AD 21

AD 13 AD 14 A D 15 AD 17

AD 10 AD 11 A D 12 AD 16

P2.14 P2.8

P 2.4

P 2.3

P 2.0

COD0

P 2.15 P2.12 P2.5

V _SS

G

H

J

V _DDP

V _SS

V_DDP

V _DDP

V_DDP

V _{S S}

P2.9

P2.6

P2.7

P2.1

G

H

J

V _{S S}

V _SS

P2.2 P3.14 P3.13

V _{S S}

V _SS

A D 8

A D 6

A D 4

AD 9

AD 5

AD 1

AD 7

AD 2

AD 0

A 20

A 15

A 11

A8

V _DD

AD 3

V _DD

A 22

A 21

A 19

V _DD

A4

P 3.12 P3.15 P3.11 P 3.9

SC AN

V _SS

V _{S S}

V _SS

V _{S S}

K

L

P3.10 P3.7

P 3.8

P 3.6

P 3.3

P 0.5

P 0.4

P 0.0

P 1.6

P 1.4

K

L

M OD E

V _{S S}

V _SS

V _DDP

V_DDP

P3.0

P3.5

P3.1

P0.1

P1.2

P1.1

TCK

TD O

P3.4

P3.2

P0.2

EBU BFC LK

C LK

M

N

P

R

T

V _DDP

V_DDP

V _DDP

V_DDP

P0.7

P0.6

P0.3

M

N

P

R

T

0

A23

A18

A17

A16

A10

A 7

A14

A13

A 9

P1.7

P1.5

V_{DD_}

A12

A1

B C 1

C AS

B C 3

C S2

BC 0

C S6

C S1

C S0

AD V

A LE

C KE

P5.9

P5.8

P 5.5

P 5.2

P5.3

SB

C S

OVL

BR K

OU T

A6

W AIT

P1.3

P 5.12 P5.7

TMS

C S

GLB

U

V

A 5

A3

R D

R AS

BA A

C S

BR KIN

TR S T

P 5.14 P5.11 P 5.6

P5.1

U

V

R D /

W R

C M

OC D

SE

A 2

1

A 0

2

BC 2

4

C S5

5

C S 4

6

C S3

7

MR /W

10

P 5.15 P5.13 P5.10 P5.4

11 12 13 14

P5.0

15

TD I

17

P 1.0

18

EMU D ELAY

3

8

9

16

TOP VIEW

LBGA 260

Figure 3

TC1920 Pinning

Data Sheet

5

V 1.3, 2003-10

TC1920

Preliminary

Pin List

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

External Bus Unit interface

external address/data bus (multiplexed bus

mode) or data bus (demultiplexed bus mode) for

the EBU:

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

274

273

272

271

270

269

268

264

263

262

261

260

259

258

253

252

251

250

249

248

247

243

242

241

240

239

238

237

232

231

230

229

L3

L2

K3

K4

L1

K2

K1

J3

I/O,s Address/data bus / Data bus line 0

I/O,s Address/data bus / Data bus line 1

I/O,s Address/data bus / Data bus line 2

I/O,s Address/data bus / Data bus line 3

I/O,s Address/data bus / Data bus line 4

I/O,s Address/data bus / Data bus line 5

I/O,s Address/data bus / Data bus line 6

I/O,s Address/data bus / Data bus line 7

I/O,s Address/data bus / Data bus line 8

I/O,s Address/data bus / Data bus line 9

I/O,s Address/data bus / Data bus line 10

I/O,s Address/data bus / Data bus line 11

I/O,s Address/data bus / Data bus line 12

I/O,s Address/data bus / Data bus line 13

I/O,s Address/data bus / Data bus line 14

I/O,s Address/data bus / Data bus line 15

I/O,s Address/data bus / Data bus line 16

I/O,s Address/data bus / Data bus line 17

I/O,s Address/data bus / Data bus line 18

I/O,s Address/data bus / Data bus line 19

I/O,s Address/data bus / Data bus line 20

I/O,s Address/data bus / Data bus line 21

I/O,s Address/data bus / Data bus line 22

I/O,s Address/data bus / Data bus line 23

I/O,s Address/data bus / Data bus line 24

I/O,s Address/data bus / Data bus line 25

I/O,s Address/data bus / Data bus line 26

I/O,s Address/data bus / Data bus line 27

I/O,s Address/data bus / Data bus line 28

I/O,s Address/data bus / Data bus line 29

I/O,s Address/data bus / Data bus line 30

I/O,s Address/data bus / Data bus line 31

AD8

AD9

J1

J2

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

H1

H2

H3

G1

G2

G3

H4

G4

E4

F1

F2

F4

F3

E1

E2

E3

D1

C1

D2

D3

C2

B1

Data Sheet

6

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

External Bus Unit interface (continued)

external address bus for the EBU or chip select

output lines.

A0

A1

A2

A3

A4

A5

A6

A7

9

6

5

4

3

2

V2

T5

V1

U3

T4

U2

T3

U1

R3

T2

T1

P3

R5

R2

P2

N3

R1

P1

N2

P4

M3

N4

M4

N1

R9

R8

R7

V7

V6

V5

U7

V8

T9

I/O,s Address bus line 0

I/O,s Address bus line 1

I/O,s Address bus line 2

I/O,s Address bus line 3

I/O,s Address bus line 4

I/O,s Address bus line 5

I/O,s Address bus line 6

I/O,s Address bus line 7

I/O,s Address bus line 8

I/O,s Address bus line 9

I/O,s Address bus line 10

I/O,s Address bus line 11

I/O,s Address bus line 12

I/O,s Address bus line 13

I/O,s Address bus line 14

I/O,s Address bus line 15

I/O,s Address bus line 16

I/O,s Address bus line 17

I/O,s Address bus line 18

I/O,s Address bus line 19

I/O,s Address bus line 20

I/O,s Address bus line 21

I/O,s Address bus line 22

I/O,s Address bus line 23

307

306

303

302

301

300

299

295

294

293

292

291

290

289

285

284

283

282

28

27

26

25

24

23

22

36

37

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CSEMU

CSOVL

O,u

Chip select output 0

Chip select output 1

Chip select output 2

Chip select output 3

Chip select output 4

Chip select output 5

Chip select output 6

Chip select for emulator region

Chip select for emulator overlay memory

Data Sheet

7

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

External Bus Unit interface (continued)

control bus for the EBU control lines.

RD

RD/WR

ALE

ADV

BC0

BC1

BC2

BC3

WAIT

BAA

11

12

45

46

218

17

16

15

32

U4

V3

T10

R10

T7

R6

V4

U6

T8

U8

M1

M2

U9

V9

I/O,u Read control line

I/O,u Write control line

O,d

O,u

Address latch enable

Address valid output

I/O,u Byte control line 0

I/O,u Byte control line 1

I/O,u Byte control line 2

I/O,u Byte control line 3

I/O,u Wait input

33

O,u

O,d

O,u

I,u

Burst address advance output

External Bus Clock

Additional clock

Chip Select Global

Command Delay

EBUCLK

BFCLK0

CSGLB

278

279

38

CMDELAY 39

MR/W

CKE

RAS

CAS

40

44

13

14

V10

U10

U5

T6

O,u

O,d

O,u

Motorola-style Read/Write

Clock Enable

Row Address Strobe

Column Address Strobe

P0

Port 0

Port 0 serves as 8-bit general purpose I/O port,

that can also be used for the codec digital signals.

P0.[3:0] also serve as external interrupt inputs.

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

94

95

98

102

103

104

105

106

R18

N16

N17

P15

P18

N18

N15

M15

I/O

EXI0IN

EXI1IN

EXI2IN

EXI3IN

SCLK

LRCK

MUTE0

MUTE1

External interrupt input 0

Ext. interrupt input 1 / DATA_IN

Ext. interrupt input 2 / DATA_OUT

Ext. interrupt input 3 / MCLK

Data Sheet

8

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

P1

Port 1

Port 1 is an 8-bit bidirectional general purpose I/O

port which is also used as input/output for the

GPTU1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

83

84

85

86

87

91

92

93

V18

R16

P16

T17

U18

R17

T18

P17

I/O

GPTU1.0

GPTU1.1

GPTU1.2

GPTU1.3

GPTU1.4

GPTU1.5

GPTU1.6

GPTU1.7

GPTU1 I/O line 0

GPTU1 I/O line 1

GPTU1 I/O line 2

GPTU1 I/O line 3

GPTU1 I/O line 4

GPTU1 I/O line 5

GPTU1 I/O line 6

GPTU1 I/O line 7

P2

Port 2

Port 2 is a 16-bit bidirectional general purpose I/O

port which is also used as input/output for serial

interfaces (CAN, J1850, IIC, ASC0, SSC)

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

131

132

133

137

138

139

140

141

142

143

147

148

149

150

151

152

G18

G17

H16

F18

E18

F17

H15

G16

E17

G15

D18

C18

F16

D17

E16

F15

I/O

RXDCAN0

TXDCAN0

RXDCAN1

TXDCAN1

RXJ1850

TXJ1850

SCL0

SDA0

SCL1

SDA1

RXD0

CAN 0 receiver input

CAN 0 transmitter output

CAN 1 receiver input

CAN 1 transmitter output

SDLM receiver input

SDLM transmitter output

IIC Serial Port Clock line 0

IIC Serial Port Data line 0

IIC Serial Port Clock line 1

IIC Serial Port Data line 1

ASC0 receiver input/output

ASC0 transmitter output

SSC clock line

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

TXD0

SCLK

MRST

MTSR

SSC master receive/slave transmit

SSC master transmit/slave receive

PLL_CLC.LOCK Monitoring of PLL_CLC.LOCK

Data Sheet

9

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

P3

Port 3

Port 3 is a 16-bit bidirectional general purpose I/O

port which is also used as input/output for serial

interfaces (ASC0 and ASC1), for timer (GPTU0)

and ADC control lines

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

P3.10

P3.11

107

108

109

110

115

116

117

118

119

120

124

125

L15

M16

M17

M18

L17

L16

L18

K17

K18

J18

K16

J17

I/O

GPTU0.0

GPTU0.1

GPTU0.2

GPTU0.3

GPTU0.4

GPTU0.5

GPTU0.6

GPTU0.7

RXD1

GPTU0 I/O line 0

GPTU0 I/O line 1

GPTU0 I/O line 2

GPTU0 I/O line 3

GPTU0 I/O line 4

GPTU0 I/O line 5

GPTU0 I/O line 6

GPTU0 I/O line 7

ASC1 receiver input/output

ASC1 transmitter output

ASC2 receiver input/output

ASC2 transmitter output

OSCBYP latch-in input

TXD1

RXD2

TXD2

P3.12

P3.13

P3.14

P3.15

126

127

128

129

J15

H18

H17

J16

I/O

ADCMUX0/EXI5IN/HWCFG0

ADC external mux control 0 /

external interrupt input 5 /

hardware configuration input 0 /

ADCMUX1/EXI6IN/HWCFG1

ADC external mux control 1 /

external interrupt input 6 /

hardware configuration input 1

ADCMUX2/EXI7IN/HWCFG2

ADC external mux control 2 /

external interrupt input 7/

hardware configuration input 2

ADC external trigger input

ADEXTIN

Data Sheet

10

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

P4

Port 4

Port 4 provides the 6 analog input lines for the AD

Converter (ADC).

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

190

191

192

193

194

195

C11

A11

B10

A10

C10

A9

I

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

Analog input 0

Analog input 1

Analog input 2

Analog input 3

Analog input 4

Analog input 5

CODEC

AI0+

AI0-

AO0+

AO0-

AI1+

180

181

169

165

176

177

170

172

162

163

D13

A13

A15

B15

D14

A14

C14

B14

A17

C16

I

O

I

CODEC 0 Non-Inverting Input

CODEC 0 Inverting Input

CODEC 0 Non-Inverting Output

CODEC 0 Inverting Output

CODEC 1 Non-Inverting Input

CODEC 1 Inverting Input

CODEC 1 Non-Inverting Output

CODEC 1 Inverting Output

Codec External Clock Input

Codec Disable (power saving)

AI1-

I

AO1+

AO1-

CEXT

CODEC_DIS

O

I

DEBUG

DEBUG (OCDS/JTAG Control)

TRST

TCK

TDI

TDO

TMS

OCDSE

BRKIN

BRKOUT

82

81

80

76

75

73

72

71

U17

T16

V17

U16

T15

V16

U15

T14

I,d

I,u

O

I,u

O

Reset/module enable

JTAG clock input

Serial data input

3)

Serial data output

State machine control signal

OCDS enable input

OCDS break input

OCDS break output

3)

Test

Test pins

SCAN_MODE 114

K15

B8

B4

I

Scan Mode

Control current of different analog stages

Test Mode Control 0

PLLCTRL_AO

TM_CTRL0

215

202

TM_CTRL1

216

A3

Test Mode Control 1

Data Sheet

11

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

P5

Port 5

TRACE

[15:0]

Trace Lines to output CPU or PCP2 OCDS level 2

trace signals

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

70

69

68

67

63

62

61

60

59

58

54

53

52

51

48

47

V15

U14

T13

R14

V14

R13

U13

T12

R12

R11

V13

U12

T11

V12

U11

V11

I/O

CPU or PCP2 trace output 0 / GPIO

CPU or PCP2 trace output 1 / GPIO

CPU or PCP2 trace output 2 / GPIO

CPU or PCP2 trace output 3 / GPIO

CPU or PCP2 trace output 4 / GPIO

CPU or PCP2 trace output 5 / GPIO

CPU or PCP2 trace output 6 / GPIO

CPU or PCP2 trace output 7 / GPIO

CPU or PCP2 trace output 8 / GPIO

CPU or PCP2 trace output 9 / GPIO

CPU or PCP2 trace output 10 / GPIO

CPU or PCP2 trace output 11 / GPIO

CPU or PCP2 trace output 12 / GPIO

CPU or PCP2 trace output 13 / GPIO

CPU or PCP2 trace output 14 / GPIO

CPU or PCP2 trace output 15 / GPIO

P5.8

P5.9

P5.10

P5.11

P5.12

P5.13

P5.14

P5.15

BYPASS

NMI

161

160

159

158

B17

A18

D16

B18

I,d

I,u

PLL Bypass Control Input.

Non-Maskable Interrupt Input

HRST

I/O,u Bidirectional Hardware Reset

PORST

I,u

Power-on Reset Input

PORST must be active during power-up of the

device

CLKOUT

156

C17

O

CPU Clock Output

XTAL1

XTAL2

208

207

A6

B7

I

O

PLL/Oscillator Input/Output

XTAL3

XTAL4

214

213

A4

B5

I

O

Real Time Clock Oscillator input/output (32 KHz)

V

206

212

211

205

A7

C6

B6

D7

-

Main Oscillator Power Supply (1.8V)

RTC Oscillator Power Supply (1.8V)

RTC & Main Oscillator Ground (1.8V)

RTC & Main Oscillator Power Supply (3.3V)

DD_OSC1

DD_OSC2

SS_OSC

DDP_OSC

Data Sheet

12

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

V

210

203

209

198

199

185

184

186

196

187

189

188

166

C7

-

RTC & Main Oscillator Power Supply (3.3V)

RTC & Main Oscillator Ground (3.3V)

PLL Supply (1.8V)

DDP_OSC

SSP_OSC

DD_PLL

D8

A5

D9

B9

PLL Ground (1.8V)

SS_PLL

C12

B12

D12

D10

A12

D11

B11

E15

ADC Port and Analog Part Power Supply (3.3V)

ADC Port and Analog Part Ground (3.3V)

ADC Analog Ground (3.3V)

DDP_ADC

SSP_ADC

SSA_ADC

AREF_ADC

AGND_ADC

DDP_COD0

ADC Reference Voltage

ADC Reference Ground

Codec 0 Port and Analog Part Power Supply

(3.3V)

V

167

175

D15

E15

-

Codec 0 Analog Ground

SSA_COD0

DDP_COD1

Codec 1 Port and Analog Part Power Supply

(3.3V)

V

174

168

173

178

179

217

224

200

201

204

97

D15

C15

B13

C13

A2

-

Codec 1 Analog Ground

SSA_COD1

SSP_COD0

SSP_COD1

REF_COD

GND_COD

DDR

Codec 0 Pad Ground (3.3V)

Codec 1 Pad Ground (3.3V)

Codec 0,1 Reference Voltage

Codec 0,1 Reference Ground

Stand-By SRAM Power Supply (1.8V)

Guard Ring Supply (1.8V)

-

C5

DDR

C9

DD_GUARD

SS_GUARD

DD_SB

A8

Guard Ring Ground (1.8V)

C8

Guard Ring Ground (1.8V)

R15

Stand-By SRAM Battery Backed Stand-By Power

Supply (1.8V)

4)

V

-

Port Pins Power Supply (3.3V)

DDP

Data Sheet

13

V 1.3, 2003-10

TC1920

Preliminary

Table 1

Pin Definitions and Functions

1)

Symbol

Pad

BGA In/

BALL Out

Functions

2)

5)

6)

V

-

Core Power Supply (1.8V)

Ground for Core and Ports

DD

SS

V

1)

The pin number describes the position of a signal on the silicon. The mapping of the pin number to the

corresponding BGA ball is done according to the used package.

2)

The notification ’,u’ after the input/output type defines an internal pull-up resistor. An internal pull-down resistor

is indicated by ’,d’. For the lines AD[31:0] and A[23:0], the type of the pull device can be selected ’s’.

3)

4)

5)

Output driver comparable to GPIO Medium Driver/Sharp Edge.

The BGA balls for the 3.3V port power supply are: G11, G12, G7, G8, H12, H7, L12, L7, M11, M12, M7, M8.

The BGA balls for the 1.8V core power supply are:

A16, B16, B3, C4, D5, J4, L4, R4.

6)

The BGA balls for the digital ground are:

A1, B2, C3, D4, D6, G10, G9, H10, H11, H8, H9, J10, J11, J12, J7, J8, J9, K10, K11, K12, K7, K8, K9, L10,

L11, L8, L9, M10, M9.

Data Sheet

14

V 1.3, 2003-10

TC1920

Preliminary

System Architecture and Control

32-Bit TriCore CPU

• 32-bit architecture with 4-GByte unified data, program and input/output address space

• Fast automatic context-switch

• Dual 16 x 16 Multiply-accumulate (MAC) unit

• Saturating integer arithmetic

• Register based design with multiple variable register banks

• Bit handling

• Packed data operations

• Zero overhead loop

• Precise exceptions

• Flexible power management

Instruction Set with High Efficiency:

• 16/32-bit instructions for reduced code size

• Little endian byte ordering with support for big and little endian byte ordering at bus

interface

• Boolean, array of bits, character, signed and unsigned integer, integer with saturation,

signed fraction, double word integers and IEEE-754 single precision floating-point

data types

• Bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats

• Powerful instruction set

• Flexible and efficient addressing mode for high code density

On-chip Code Memories

PMU Scratch-Pad SRAM (CSRAM):

The PMU memory consists of 24-KByte Code Scratchpad RAM (CSRAM) and 8-KByte

Instruction Cache (ICACHE).

Address range of the CSRAM:

• D400 0000 - D400 5FFF

H

Boot ROM (BROM):

The TC1920 contains 32 KByte of Boot ROM memory, which can be used for device

operating mode initialization routines, bootstrap loader support or test functions.

The address range of the Boot ROM is:

• DFFF 8000 – DFFF FFFF

H

Data Sheet

15

V 1.3, 2003-10

TC1920

Preliminary

On-chip Data Memories

DMU Scratch-Pad SRAM (DSRAM):

The DMU memory consists of 24-KByte Data Scratchpad RAM (DSRAM) and 8-KByte

Data Cache (DCACHE).

Address range of the DSRAM:

• D000 0000 - D000 5FFF

H

Local Memory Bus Memory (LMBRAM):

Address range of the 64 KByte Local Memory Bus Memory:

• C000 0000 - C000 FFFF (in segment 12 for cached operation)

H

• E800 0000 - E800 FFFF (in segment 14 for non-cached operation)

H

FPI-Bus Data Memory (FPIDRAM):

The FPI-Bus Data Memory (FPIDRAM) is a 16-KByte static RAM located on the FPI-

Bus. It contains two parts: FPIDRAM0 and FPIDRAM1. One half of it (FPIDRAM1) can

be used for standby power operation.

Address range of the FPI Data Memory:

• 9FFF 8000 - 9FFF BFFF (in segment 9 for cached operation)

H

• BFFF 8000 - BFFF BFFF (in segment 11 for non-cached operation)

H

On-chip PCP Memories

PCP Code Memory (PCODE):

The address range of the 16 KByte PCP Code Memory (PCODE) is:

• F002 0000 - F002 3FFF

H

PCP Data Memory (PRAM):

The address range of the 4 KByte PCP Data Memory (PRAM) is:

• F001 0000 - F001 0FFF

H

Data Sheet

16

V 1.3, 2003-10

TC1920

Preliminary

System Control Unit (SCU)

The System Control Unit of the TC1920 basically handles all system control tasks. All

these system functions are tightly coupled and therefore they are handled physically by

one unit, the SCU. The system tasks of the SCU are:

• Clock Generation and Control

• Reset control

• Power Management control and wake-up

• Watchdog timer

• Trace port control

• Device identification

• Standby SRAM control

• External interrupt capability (8 sources)

System timer (STM)

The System Timer is designed for global system timing applications requiring both high

precision and long range. It is used by the CPU for software operating system issues.

Features:

• Free-running 56-bit counter

• All 56 bits can be read synchronously

• Different 32-bit portions of the 56-bit counter can be read synchronously

• Driven by clock, f

(normally identical with the system clock).

STM

• Counting begins at power-on reset

• Continuous operation is not affected by any reset condition except power-on reset

Data Sheet

17

V 1.3, 2003-10

TC1920

Preliminary

External Bus Interface (EBU_LMB)

EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1920 and also to the

FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus.

Any LMB masters thus can access external memories or devices through EBU_LMB.

Currently the maximum length of the bursts are according to the size of program and

data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8-

bit, 16-bit and 32-bit wide access.

EBU_LM B

XBC

LM B Bus 64-bit

Buffer

SDRAM

Slower

Devices

50 M Hz

DM E

FPI Bus 32-bit

XM I

External

M aster

External Bus Unit

EBUL3045_L

Figure 4

EBU_LMB block diagram

Features supported in EBU_LMB:

• Local Memory Bus (LMB 64-bit) support.

• External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4.

• Highly programmable access parameters.

• Intel-style and Motorola-style peripheral/device support.

• SDRAM support (burst access, multibanking, precharge, refresh).

• 16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices.

• Burst flash support.

• Multiplexed access (address & data on the same bus) when SDRAM is not present on

the External Bus.

• Data Buffering: Code Prefetch Buffer, Read/Write Buffer.

• External master arbitration (compatible to C166 and other TriCore devices).

• 8 programmable address regions (1 dedicated for emulator).

• Little-endian and Big-endian support.

• CSGLB signal, dedicated pin, bit programmable to combine one or more CS lines, for

buffer control.

• RMW signal reflecting a read-modify-write action.

• Signal for controlling data flow of slow-memory buffer.

• Slave unit for external (off-chip) master to access devices on the FPI bus.

• Master unit for FPI master to access external (off-chip) devices.

• Data Mover Engine.

Data Sheet

18

V 1.3, 2003-10

TC1920

Preliminary

Interrupt System

• Flexible interrupt prioritizing scheme with 256 interrupt priority levels

• Fast interrupt response

• Service requests are serviced by the CPU or by the PCP (two independent interrupt

buses, that can be selected by each interrupt source)

PCP Interrupt

Arbitration Bus

C PU Interrupt

Arbitration Bus

Module A

PC P Interrupt Control

n Service

Request

Nodes

PC P

Interrupt

Control

Unit

M odule

Kernel

PCP

(PICU)

Kernel

12 Service

Request

Nodes

12

Module B

n Service

Request

Nodes

M odule

Kernel

M ain Interrupt Control

CPU

Interrupt

C ontrol

Unit

Module C

CPU

Core

(ICU)

n Service

Request

Nodes

M odule

Kernel

4 Service

Request

Nodes

4

Figure 5

Block Diagram Interrupt System

Data Sheet

19

V 1.3, 2003-10

TC1920

Preliminary

Peripheral Control Processor (PCP)

C ode

M em ory

PC O DE

Param eter

M em ory

PR AM

PC P

Processor

Core

PCP Service

R eq. Nodes

PSRN s

PC P Interrupt

C ontrol Unit

PICU

FPI-Interface

FPI Bus

PC P Interrupt

Arbitration Bus

CPU Interrupt

Arbitration Bus

M CB04784_m od

Figure 6

PCP block diagram

The PCP is designed to work in partnership with a host CPU and performs many of the

tasks that would conventionally be performed by CPU interrupt service routines or a

DMA controller. The PCP off-loads the host CPU from most of the time critical interrupts,

easing the implementation of systems based on operating systems.

In principle the PCP may be considered to be a conventional processor which only

executes code in response to interrupt service requests (i.e. has no processing which is

not at interrupt level). It has an architecture which efficiently supports DMA type of bus

transactions to / from arbitrary devices and memory addresses and also some

reasonable computational capabilities. Whenever the PCP responds to a PCP interrupt

request (which has a specific interrupt priority level) it will use a register set ("context")

specific to that individual interrupt level and will also generally execute code which is also

specific to that interrupt level. For this reason the term "Channel" will be used throughout

the remainder of this document to refer to all PCP resources associated with a particular

PCP interrupt level.

The architecture is flexible enough to allow the implementation of a subset of the

commands/instructions as a simple DMA controller.

The PCP has a Harvard architecture (i.e. separate code and data memory spaces). Any

FPI bus master (including the PCP itself) can access both PCP code (PCODE) and data

(PRAM) memory via the FPI bus.

Data Sheet

20

V 1.3, 2003-10

TC1920

Preliminary

FPI Bus

The Flexible Peripheral Interconnect Bus is designed with the requirements of high-

performance Systems-on-Chip in mind.

Key Features:

• Core independent

• Multi-master capability

• Demultiplexed operation

• Clock synchronous

• Peak transfer rate of up to 200 MBytes/s (@ 50 MHz bus clock)

• Address and data bus scalable (32 bit address bus, 32 bit data bus )

• 8-/16- and 32 bit data transfers

• Broad range of transfer types from single to multiple data transfers

• Burst transfer capability

• EMI and power consumption minimized

LMB-Bus

The Local Memory Bus is a synchronous, pipelined, split bus with variable block size

transfer support. All signals relate to the positive clock edge.

The protocol supports 8,16,32 & 64 bits single beat transactions and variable length 64

bits block transfers.

Key Features:

The LMB provides the following features:

• Optimized for high speed and high performance

• 32 bit address, 64 bit data busses

• Central simple per cycle arbitration

• Slave controlled wait state insertion

• Address pipelining (max. depth - 2)

• Split transactions

• Variable block length - 2, 4 or 8 beats of 64 bit data

Data Sheet

21

V 1.3, 2003-10

TC1920

Preliminary

On-Chip Debug System (OCDS)

The TC1920 architecture is supporting OCDS level 1 and 2.

Level

Run Time

Control

System access via

Basic PC trace

JTAG

Yes

Trace bus

1

Yes

No

2

Yes

Table 2

Module

Core-related and System Control Modules

Address Range

I/O Lines

Interrupt

Nodes

TriCore CPU

Slave Registers (CPS) F7E0 FFFF

F7E0 FF00 -

-

CPU_SRC0..3

CPU_SRCSB

H

1)

Memory Management

Unit (MMU)

F7E1 8000 -

-

H

F7E1 80FF

H

Segment Protection

F7E1 C000 -

-

H

1)

Registers

F7E1 C0FF

H

1)

Core Debug

F7E1 FD00 -

-

H

(Core OCDS)

F7E1 FDFF

H

1)

TriCore CPU

F7E1 FE00 -

-

H

SFR, GPR

F7E1 FFFF

H

2)

Program Memory Unit

(PMU)

F87F FD00 -

-

H

F87F FDFF

H

2)

Data Memory Unit

(DMU)

F87F FC00 -

-

H

F87F FCFF

H

Peripheral Control

Processor (PCP)

F000 3F00 -

PCP_SRC0..11

-

H

F000 3FFF

H

External Bus Unit

(EBU)

F800 0000 -

AD[31:0], A[23:0],

27 control lines

H

F800 03FF

H

System Control Unit

(SCU)

F000 0000 -

4 XTAL, PORST,

EXI_SRC0..4

H

3)

F000 00FF

HRST, 8 EXIN, NMI, NMI

4 test, CLKOUT,

BYPASS

H

FPI Bus Control Unit

(BCU)

F000 0200 -

-

BCU_SRC

H

F000 02FF

H

Data Sheet

22

V 1.3, 2003-10

TC1920

Preliminary

Table 2

Module

Core-related and System Control Modules (cont’d)

Address Range

I/O Lines

Interrupt

Nodes

LMB Bus Control Unit

(LCU)

F87F FE00 -

-

LCU_SRC

H

F87F FEFF

H

LMB to FPI Bus Bridge F87F FF00 -

(LFI)

-

H

F87F FFFF

H

Port Control

(Ports 0, 1, 2, 3, 5)

F000 2800 -

P0 (7), P1(7),

P2(15), P3(15),

P5(15)

H

F000 2CFF

H

Debug Support

(JTAG, OCDS)

F000 0400 -

TRST, TCK, TDI,

TDO, TMS, OCDSE,

BRKIN, BRKOUT,

16 trace outputs

-

H

F000 04FF

H

1)

This address range is also accessed via the CPS by the FPI bus.

This address range is accessed via the LMB.

2)

3)

The NMI is directly connected to the core (no SRC) and always acts on the highest priority. It is used as highest

priority interrupt for the NMI input, the watchdog, the PLL and for wake-up via the RTC or via the EXIx inputs.

On-Chip Peripheral Units

The TC1920 offers several on-chip peripheral units such as serial controllers, timer units,

AD converter and Codec interface. Within the TC1920 all these peripheral units are

connected to the TriCore CPU/system via the FPI (Flexible Peripheral Interconnect) Bus.

Several IO lines on the TC1920 ports are reserved for these peripheral units to

communicate with the external world.

Peripheral Units of the TC1920:

• Three Asynchronous/Synchronous Serial Channels with baudrate generator, parity,

framing and overrun error detection, IrDA mode, FIFO buffers.

• One High Speed Synchronous Serial Channels with programmable data length and

shift direction

• TwinCAN Module with two interconnected CAN nodes for high efficiency data

handling via FIFO buffering and gateway data transfer

• Serial Data Link Module compliant to SAE Class B J1850 specification

• IIC module with connection to 2 external busses

• 2 multi-functional General Purpose Timer Units with three 32-bit timer/counter

• One Analog-to-Digital Converter Units with 8-bit, 10-bit, or 12-bit resolution and 6

analog inputs

• Dual channel Codec interface

• GPIO blocks

Data Sheet

23

V 1.3, 2003-10

TC1920

Preliminary

Table 3

Module

Peripheral Modules

Address Range

I/O Lines

Interrupt Nodes

Asynchronous

Serial Channel 0

(ASC0)

F000 0A00 -

RDX0, TDX0

ASC0_TSRC

ASC0_RSRC

ASC0_ESRC

ASC0_TBSRC

H

F000 0AFF

H

Asynchronous

Serial Channel 1

(ASC1)

F000 0B00 -

RDX1, TDX1

RDX2, TDX2

ASC1_TSRC

ASC1_RSRC

ASC1_ESRC

ASC1_TBSRC

H

F000 0BFF

H

Asynchronous

Serial Channel 2

(ASC2)

F000 0C00 -

ASC2_TSRC

ASC2_RSRC

ASC2_ESRC

ASC2_TBSRC

H

F000 0CFF

H

Synchronous Serial F000 0800 -

SCLK, MRST,

MTSR

SSC_TSRC

SSC_RSRC

SSC_ESRC

H

Channel (SSC)

F000 08FF

H

Inter-IC Bus (IIC)

F000 0500 -

SCL[1:0],

SDA[1:0]

IIC_XP0SRC

IIC_XP1SRC

IIC_XP2SRC

H

F000 05FF

H

Real Time Clock

(RTC)

F000 0100 -

-

RTC_SRC

H

F000 01FF

H

System Timer Unit F000 0300 -

-

H

(STM)

F000 03FF

H

General Purpose

Timer 0 (GPTU0)

F000 0700 -

GPTU0[7:0]

GPTU1[7:0]

GPTU0_SRC0..7

GPTU1_SRC0..7

CAN_SRC0..7

SDLM_SRC0..1

H

F000 07FF

H

General Purpose

Timer 1 (GPTU1)

F000 0600 -

H

F000 06FF

H

CAN (TwinCAN)

F010 0000 -

RXDCAN[1:0],

TXDCAN[1:0]

H

F010 0BFF

H

SDLM (J1850)

F000 2600 -

RXJ1850,

TXJ1850

H

F000 26FF

H

Data Sheet

24

V 1.3, 2003-10

TC1920

Preliminary

Table 3

Module

Peripheral Modules (cont’d)

Address Range

I/O Lines

Interrupt Nodes

Speech Interface

(Codec)

F000 2400 -

2*2 analog IN,

2*2 analog OUT,

CEXT,

CODEC_SRC0..5

H

F000 24FF

H

CODEC_DIS

Analog to Digital

Converter (ADC)

F000 2200 -

AIN[5:0] = P4,

ADEMUX[2:0],

ADEXTIN

ADC_SRC0..3

H

F000 23FF

H

Asynchronous/Synchronous Serial Interfaces (ASC 0/1/2)

The Asynchronous/Synchronous Serial Interface ASC provides serial communication

between the TriCore and other microcontrollers, microprocessors or external

peripherals. The implementation is held parametrizable in order to allow the usage of

parallel busses of different width and with different protocols.

Features:

• Full duplex asynchronous operating modes

– 8- or 9-bit data frames, LSB first

– Parity bit generation/checking

– One or two stop bits

– Baudrate from 3.125 MBaud to 0.74 Baud (@ 50 MHz module clock)

– Multiprocessor mode for automatic address/data byte detection

– Loop-back capability

• Half-duplex 8-bit synchronous operating mode

– Baudrate from 6.25 MBaud to 637 Baud (@ 50 MHz module clock)

• Double buffered transmitter/receiver

• Interrupt generation

– on a transmitter buffer empty condition

– on a transmit last bit of a frame condition

– on a receiver buffer full condition

– on an error condition (frame, parity, overrun error)

• Support for IrDA

• Automatic Baudrate Detection

• 8 Byte FIFO

Data Sheet

25

V 1.3, 2003-10

TC1920

Preliminary

f_{hw_clk}

C lock

C ontrol

Address

Decoder

R XD

TXD

RXD

ASC

M odule

(Kernel)

Port

C ontrol

TIR

TXD

TBIR

R IR

Interrupt

C ontrol

EIR

ABSTIR

ABDETIR

M CA05253

Figure 7

ASC Interface Diagram

Data Sheet

26

V 1.3, 2003-10

TC1920

Preliminary

High-Speed Synchronous Serial Interface (SSC)

The High Speed Synchronous Serial Interface SSC provides serial communication

between microcontrollers, microprocessors or external peripherals. The SSC supports

full-duplex and half-duplex synchronous communication up to 25 MBaud (@ 50 MHz

module clock). The serial clock signal can be generated by the SSC itself (master mode)

or be received from an external master (slave mode). Data width, shift direction, clock

polarity and phase are programmable. This allows communication with SPI-compatible

devices. Transmission and reception of data are double-buffered. A 16-bit baud rate

generator provides the SSC with a separate serial clock signal.

Features:

• Master and slave mode operation

– Full-duplex or half-duplex operation

• Flexible data format

– Programmable number of data bits : 2 to 16 bit

– Programmable shift direction : LSB or MSB shift first

– Programmable clock polarity : idle low or high state for the shift clock

– Programmable clock/data phase : data shift with leading or trailing edge of SCLK

• Maximum baudrates: 25 MBaud in Master, 12.5 in Slave mode (@ 50 MHz module

clock)

Interrupt generation

– on a transmitter empty condition

– on a receiver full condition

– on an error condition (receive, phase, baudrate, transmit error)

• Three pin interface

f_{hw_clk}

C lock

C ontrol

R XD

M TSR

M R ST

SCLK

TXD

Address

Decoder

SSC

M odule

(Kernel)

R XD

TXD

Port

Control

EIR

R IR

TIR

Slave

M aster

Interrupt

C ontrol

M C B04505_m od

Figure 8

SSC Interface Diagram

Data Sheet

27

V 1.3, 2003-10

TC1920

Preliminary

Inter-IC Interface (IIC)

IIC supports a certain protocol to allow devices to communicate directly with each other

via two wires. One line is responsible for clock transfer and synchronization (SCL), the

other is responsible for the data transfer (SDA).

The on-chip IIC Bus module connects the platform buses to other external controllers

and/or peripherals via the two-line serial IIC interface. The IIC Bus module provides

communication at data rates of up to 400 kBit/s and features 7-bit addressing as well as

10-bit addressing. This module is fully compatible to the IIC bus protocol.

SDA0

Generic

data line

SDA1

IIC Kernel

SCL0

Generic

clock line

SCL1

IIC M odule

Figure 9

IIC Bus Line Connections

The module can operate in three different modes:

Master mode, where the IIC controls the bus transactions and provides the clock signal.

Slave mode, where an external master controls the bus and provides the clock signal.

Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can

be master or slave.

The module unloads the CPU of low level tasks like:

• (De)Serialization of bus data.

• Generation of start and stop conditions.

• Monitoring the bus lines in slave mode.

• Evaluation of the device address in slave mode.

• Bus access arbitration in multimaster mode.

IIC Features:

• Extended buffer allows up to 4 send/receive data bytes to be stored.

• Selectable baud rate generation.

• Support of standard 100 kBaud and extended 400 kBaud data rates.

• Operation in 7-bit addressing mode or 10-bit addressing mode.

• Flexible control via interrupt service routines or by polling.

• Dynamic access to up to 2 physical IIC busses.

Data Sheet

28

V 1.3, 2003-10

TC1920

Preliminary

CAN Interface (TwinCAN)

Figure 10 shows a global view of the functional blocks of the TwinCAN module.

TwinC AN M odule Kernel

f_{C AN}

C AN

Node A

CAN

N ode B

C lock

C ontrol

TXDC A

R XD CA

Address

Decoder

Port

M essage

Control

O bject

Buffer

TXDC B

R XD CB

Interrupt

C ontrol

TwinC AN C ontrol

M CB04515

Figure 10

General Block Diagram of the TwinCAN Interfaces

TwinCAN Features:

• CAN functionality according to CAN specification V2.0 B active.

• Dedicated control registers are provided for each CAN node.

• A data transfer rate up to 1MBaud is supported.

• Flexible and powerful message transfer control and error handling capabilities are

implemented.

• Full-CAN functionality: 32 message objects can be individually

– assigned to one of the two CAN nodes,

– configured as transmit or receive object,

– participate in a 2,4,8,16 or 32 message buffer with FIFO algorithm,

– setup to handle frames with 11 bit or 29 bit identifiers,

– provided with programmable acceptance mask register for filtering,

– monitored via a frame counter,

– configured to Remote Monitoring Mode.

• Up to eight individually programmable interrupt nodes can be used.

• CAN Analyzer Mode for bus monitoring is implemented.

The TwinCAN module has four IO lines. The TwinCAN module is further supplied by a

clock control, interrupt control, address decoding, and port control logic.

Data Sheet

29

V 1.3, 2003-10

TC1920

Preliminary

The CAN module contains two Full-CAN nodes operating independently or exchanging

data and remote frames via a gateway function. Transmission and reception of CAN

frames is handled in accordance to CAN specification V2.0 part B (active). Each of the

two Full-CAN nodes can receive and transmit standard frames with 11-bit identifiers as

well as extended frames with 29-bit identifiers.

Both CAN nodes share the TwinCAN module’s resources in order to optimize the CAN

bus traffic handling and to minimize the CPU load. The flexible combination of Full-

functionality and FIFO architecture reduces the efforts to fulfill the real-time requirements

of complex embedded control applications. Improved CAN bus monitoring functionality

as well as the increased number of message objects permit precise and comfortable

CAN bus traffic handling.

Depending on the application, each of the 32 message objects can be individually

assigned to one of the two CAN nodes. Gateway functionality allows automatic data

exchange between two separate CAN bus systems, which reduces CPU load and

improves the real time behavior of the entire system.

The bit timings for both CAN nodes are derived from the peripheral clock (f

) and are

CAN

programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connect

each CAN node to a bus transceiver.

Data Sheet

30

V 1.3, 2003-10

TC1920

Preliminary

Serial Data Link Module (J1850)

Figure 11 shows a global view of the functional blocks of the J1850 interface.

f_SDLM

C lock

C ontrol

R XD

R XJ1850

TXJ1850

SDLM

M odule

(Kernel)

Address

Decoder

Port

C ontrol

TXD

Interrupt

C ontrol

M CB04550

Figure 11

General Block Diagram of the SDLM Interface

The J1850 module communicates with the external world via two I/O lines, the J1850

bus. The RXD line is the receive data input signal and TXD is the transmit data output

signal. The Serial Data Link Module provides serial communication to a J1850 based

serial bus. J1850 bus transceivers have to be implemented externally in a system. The

J1850 module is conform to the SAE Class B J1850 specification and compatible to

class 2 protocol.

General SDLM Features:

• Compliant to SAE Class B J1850 specification

• Full support of GM class 2 protocol

• Variable Pulse Width (VPW) format with 10.4 kBaud

• High speed receive/transmit 4x mode with 41.6 kBaud

• Digital noise filter

• Power save mode and automatic wake up upon bus activity

• Support of single byte headers or consolidated headers

• CRC generation & check

• Support of block mode for receive and transmit

Data Link Operation Features:

• 11 bytes transmit buffer

• Double buffered 11 bytes receive buffer

• Support of In-frame response (IFR) types 1,2,3

• Advanced interrupt handling for RX, TX and error conditions

• All interrupt sources can be enabled/disabled individually

• Support of automatic IFR for types 1,2 for three byte consolidated headers

Data Sheet

31

V 1.3, 2003-10

TC1920

Preliminary

Timer Units (GPTU 0/1)

Figure 12 shows a global view of all functional blocks of one GPTU module.

IN 0

IN 1

IN 2

IN 3

IN 4

IN 5

IN 6

IN 7

IO 0

IO 1

IO 2

IO 3

IO 4

IO 5

IO 6

IO 7

P0.0 / G PT0

P0.1 / G PT1

P0.2 / G PT2

P0.3 / G PT3

P0.4 / G PT4

P0.5 / G PT5

P0.6 / G PT6

f_GPTU

C lock

C ontrol

Address

Decoder

G PTU

M odule

(Kernel)

Port

Control

SR0

SR1

SR2

SR3

SR4

SR5

SR6

SR7

O UT0

O UT1

O UT2

O UT3

O UT4

O UT5

O UT6

O UT7

Interrupt

C ontrol

P0.7 / G PT7

M CB05052_m odified

Figure 12

General Block Diagram of the GPTU Interface

The GPTU consists of three 32-bit timers designed to solve such application tasks as

event timing, event counting, and event recording. The GPTU communicates with the

external world via eight inputs and eight outputs.

The three timers of the GPTU module T0, T1, and T2, can operate independently from

each other, or can be combined:

General Features:

• All timers are 32-bit precision timers with a maximum input frequency of f

• Events generated in T0 or T1 can be used to trigger actions in T2

• Timer overflow or underflow in T2 can be used to clock either T0 or T1

• T0 and T1 can be concatenated to form one 64-bit timer

/2.

GPTU

Features of T0 and T1:

• Each timer has a dedicated 32-bit reload register with automatic reload on overflow

• Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload

registers

• Overflow signals can be selected to generate service requests, pin output signals, and

T2 trigger events

• Two input pins can determine a count option

Data Sheet

32

V 1.3, 2003-10

TC1920

Preliminary

Features of T2:

• Optionally count up or down

• Operating modes:

– Timer

– Counter

– Incremental Interface Mode

• Options:

– External start/stop, one-shot operation, timer clear on external event

– Count direction control through software or an external event

– Two 32-bit reload/capture registers

• Reload modes:

– Reload on overflow or underflow

– Reload on external event: positive transition, negative transition, or both transitions

• Capture modes:

– Capture on external event: positive transition, negative transition, or both

transitions

– Capture and clear timer on external event: positive transition, negative transition, or

both transitions

• Can be split into two 16-bit counter/timers

• Timer count, reload, capture, and trigger functions can be assigned to input pins. T0

and T1 overflow events can also be assigned to these functions.

• Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle

output pins

• T2 events are freely assignable to the service request nodes.

Data Sheet

33

V 1.3, 2003-10

TC1920

Preliminary

Analog to Digital Converter (ADC)

Figure 13 shows a global view of the ADC module kernel with the module specific

interface connections.

V_SSA

V _{DD A}

V_{DD M}

V_{AR EF}

V_{AGN D}

V _SSM

EM U X0

EM U X1

EM U X2

f_{A DC}

C lock

C ontrol

Port

Control

Address

Decoder

AIN0

AIN1

SR 0

SR 1

SR 2

SR 3

AD C

M odule

Kernel

Interrupt

C ontrol

AIN5

ASG T

EXI0IN

ETR, EG T

Q TR , Q G T

TTR, TG T

EXI7IN

Interrupt

Inputs

ADEXTIN

TC1920_ADC_blockdiagram

SW 0TR=0

SW 0G T=1

Figure 13

General Block Diagram of the ADC module

The on-chip ADC module of the TC1920 is an analog to digital converter with 8-bit, 10-

bit or 12-bit resolution including sample & hold functionality. The A/D converter operates

by the method of the successive approximation. A multiplexer selects between up to 6

analog input channels. Conversion requests are generated either under software control

or by hardware. An automatic self-calibration adjusts the ADC module to changing

temperatures or process variations.

Data Sheet

34

V 1.3, 2003-10

TC1920

Preliminary

Features:

The following functionality has been implemented in the on chip ADC module to fulfill the

enhanced requirements of embedded control applications:

• 8-bit, 10-bit, 12-bit A/D Conversion

• Successive approximation conversion method

• Total Unadjusted Error (TUE) of ± 2 LSB @ 10-bit resolution

• Integrated sample and hold functionality

• 6 analog input channels

• Dedicated control and status registers for each analog channel

• Flexible conversion request mechanisms

• Selectable reference voltages for each channel

• Programmable sample and conversion timing schemes

• Limit checking

• Flexible ADC module service request control unit

• Automatic control of external analog multiplexer

• Equidistant samples initiated by timer

• External trigger inputs for conversion requests

• Power reduction and clock control feature

Real Time Clock Unit RTC

The Real Time Clock (RTC) module is basically an independent timer chain and counts

clock ticks. The base frequency of the RTC can be programmed via a reload counter.

The RTC can work fully asynchronous to the system frequency and is optimized on low

power consumption.

Features:

The RTC serves different purposes:

• Absolute system clock to determine the current time and date

• Cyclic time based interrupt

• Alarm interrupt for wake up on a defined time

• 48-bit timer for long term measurements

Data Sheet

35

V 1.3, 2003-10

TC1920

Preliminary

Codec Interface

The speech A/D and D/A converters (called codec) is designed for telephone and

speech recognition quality. They can be used for microphone / earpiece applications.

The TC1920 configuration implements a dual channel speech codec connected to the

FPI bus.

V_DDV_{S S}

V_DDV_SS

CO D0

COD0

CO D1 CO D1

ch0 non-inv. input

ch0 inv. input

AI0+

f_per

Clock

Control

AI0-

ch0 non-inv. output

ch0 inv. output

AO0+

AO0-

Address

Decoder

ch1 non-inv. input

ch1 inv. input

AI1+

AI1-

SR0

SR1

SR2

SR3

CO DEC

M odule

Kernel

ch1 non-inv. output

ch1 inv. output

AO1+

AO1-

Interrupt

Control

clock disable

SR4

SR5

CO DEC_DIS

CEXT

external clock input

m ute channel 0

m ute channel 1

V_{RE F}

M UTE0

M UTE1

COD

V_{G ND}

COD

Codec bypass

5

IIS

signals

Figure 14

General Codec Overview

General Purpose I/Os (GPIO)

• Push/pull output drivers

• 3.3 Volt operation for GPIO

• Programmable pull-up/-down devices at all pins

• Optional Open Drain Output Mode

Data Sheet

36

V 1.3, 2003-10

TC1920

Preliminary

Power Supply

Figure 15 shows the TC1920 power supply concept, where certain logic modules are

individually supplied with power. In this way, the noise margin is improved in the

especially sensitive modules, like the A/D converter and the CODEC.

V_{D DA}

V_{SS A}

V_{D DA}

V_SSA

V_{DD A}

V_SSA

V_{DD A}

V_SSA

V_{D DA}

V_{SS A}

V_{DD A}

V_SSA

RTC

OSC

PLL

(analog)

ADC

(analog)

CO DEC 0

(analog)

CO DEC 1

(analog)

M AIN

O SC

V_{D DP}

V_{SS P}

B attery

ALL DIG ITAL CORE

CO MPO NENTS

B acked

S tand- By

S RAM

X

V_{D DP}

V_{SS P}

Y

V_{D D_SB}

V_{D DR}

V_SS

V_DD

V_SS

V_{D D}

V_SS

Figure 15

TC1920 Power Supply Concept

Data Sheet

37

V 1.3, 2003-10

TC1920

Preliminary

Power-Up Sequence

During Power-Up reset pin PORST has to be held active until both power supply

voltages have reached at least their minimum values.

During the Power-Up time (rising of the supply voltages from 0 to their regular operating

values) it has to be ensured, that the core V power supply reaches its operating value

DD

first, and then the GPIO V

power supply. During the rising time of the core voltage it

DDP

must be ensured that 0< V -V

<0.5 V.

DD DDP

During power-down, the core and GPIO power supplies V

and V

respectively,

DDP

DD

have to be switched off until all capacitances are discharged to zero, before the next

power-up.

Note: The states of the pins are undefined when only the port voltage V

is on.

DDP

Data Sheet

38

V 1.3, 2003-10

TC1920

Preliminary

ID Register Table

Table 4

List of TC1920 ID registers

Short Name Description

Address

Value

0019 C002

SCU_ID

MANID

CHIPID

RTID

SCU Identification Register

F000 0008

F000 0070

F000 0074

H

Manufacturer Identification Register

Chip Identification Register

0000 1820

0000 8902

0000 0000

H

Redesign Tracing Identification Register F000 0078

RTC_ID

BCU_ID

STM_ID

RTC Module Identification Register

BCU Identification Register

F000 0108

F000 0208

F000 0308

0000 5A04

0000 6A06

H

System Timer Module Identification

Register

0000 C002

H

JDP_ID

JTAG/OCDS Module Identification

Register

F000 0408

0000 6305

0000 4604

H

IIC_ID

IIC Module Identification Register

GPTU Module Identification Register

SSC Module Identification Register

ASC Module Identification Register

ADC Module Identification Register

F000 0508

F000 0708

F000 0608

F000 0808

H

GPTU0_ID

GPTU1_ID

SSC_ID

0001 C002

H

0000 4503

H

ASC0_ID

ASC1_ID

ASC2_ID

ADC_ID

F000 0A08

F000 0B08

0000 44E1

H

F000 0C08

H

F000 2208

F000 2408

F000 2608

0000 3104

H

CODEC_ID Codec Identification Register

001C C002

H

SDLM_ID

PCP_ID

CAN_ID

CPS_ID

MMU_ID

CPU_ID

EBU_ID

DMU_ID

PMU_ID

LCU_ID

LFI_ID

SDLM Module Identification Register

PCP Module Identification Register

CAN Module Identification Register

CPU Module Identification Register

MMU Identification Register

0000 4204

H

F000 3F08

0020 C003

H

F010 0008

0000 4110

H

F7E0 FE08

0015 C004

0009 C002

H

F7E1 8008

H

CPU Identification Register

F7E1 FE18

F800 0008

000A C003

H

EBU_LMB Identification Register

DMU Identification Register

0014 C003

0008 C002

H

F87F FC08

F87F FD08

H

PMU Module Identification Register

LCU Identification Register

000B C002

H

F87F FE08

F87F FF08

000F C003

LFI Identification Register

000C C003

H

Data Sheet

39

V 1.3, 2003-10

TC1920

Preliminary

Electrical characteristics

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the TC1920

and partly its demands on the system. To aid in interpreting the parameters right, when

evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the TC1920 will provide signals with the respective characteristics.

SR (System Requirement):

The external system must provide signals with the respective characteristics to the

TC1920.

Data Sheet

40

V 1.3, 2003-10

TC1920

Preliminary

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

min. max.

Unit Notes

Ambient temperature

Storage temperature

Junction temperature

T_A

-40

-65

–

85

°C

V

under bias

T_ST

T_J

150

125

4.2

Voltage on I/O Supply pins with V_DDP

respect to ground (V_SS)

-0.5

Voltage on Core Supply pins

with respect to ground (V_SS)

V_DD

-0.3

2.1

4.2

10

V

Voltage on PLL Supply pins

with respect to ground (V_SS)

V_DDPLL

V

PLL

Voltage between Oscillator

Supply Pins and ground (V_SS).

V_DDOSC-0.3

V

Voltage on any pin with respect V_IN

to ground (V_SS)

-0.5

-10

–

V

Input current on any pin during I

overload condition

mA

W

OV

Absolute sum of all input

currents at overload condition

ΣI

|100|

1.4

OV

Power dissipation

P_DISS

–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN>V_DDor V_IN<V_SS) the

voltage on V_DDpins with respect to ground (V_SS) must not exceed the values

defined by the absolute maximum ratings.

Data Sheet

41

V 1.3, 2003-10

TC1920

Preliminary

Package Parameters (P-LBGA-260)

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

1.4

Power dissipation

Thermal resistance

P_DISS

R_THA

–

W

–

27.8

K/W Chip to ambient

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the TC1920. All parameters specified in the following sections refer to these

operating conditions, unless otherwise noticed.

Parameter

Symbol

Limit Values

min. max.

Unit Notes

1)

Supply voltage

V_DDP

V_DD

3.0

3.6

V

I/O supply

2)

1.71

1.89

V

Core supply

PLL supply

V_DDPLL

V

V_DDOSC1.71

V

Oscillator supply

Ground voltage

V_SS

0

V

Input current on any pin

during overload

condition

I

-5

–

5

mA

V

> V_DDP+ 0.3V

< V_SS- 0.3V

OV

Absolute sum of all input Σ| I

currents at overload

condition

|

|50|

85

mA

°C

OV

Ambient temperature

under bias

T_A

-40

CPU clock

f_CPU

C_L

–

100

50

MHz

pF

External Load

Capacitance

1)

Voltage overshoot to 4 V is permissible, provided the pulse duration is less than 100 µs and the cumulated

summary of the pulses does not exceed 1 h

2)

Voltage overshoot to 2 V is permissible, provided the pulse duration is less than 100 µs and the cumulated

summary of the pulses does not exceed 1 h

Data Sheet

42

V 1.3, 2003-10

TC1920

Preliminary

DC Characteristics

GPIO pins

Parameter

Symbol

Limit values

Unit Test

Conditions

min.

max.

Output low voltage

(strong driver)

V

-

1

0.4

V

I

= 10 mA

= 2.5 mA

OL

OH

OL

OH

OL

OH

OL

Output high voltage

(strong driver)

2.4

-

I

= - 2.5 mA

OH

OL

OH

OL

OH

Output low voltage

0.4

-

= 1 mA

1)

(medium driver)

Output high voltage

2.4

-

= - 1 mA

= 100 µA

= - 100 µA

1)

(medium driver)

Output low voltage

0.4

-

1)

(weak driver)

Output high voltage

2.4

1)

(weak driver)

Input low voltage

Input high voltage

V

-0.3

2.0

0.8

V

LVTTL

IL

V

+0.3 V

whatever is

lower

IH

DDP

or

3.7V

Input leakage current

I

-

±500

nA

0V< V <

in

OZ1

V

DDP

OUT

2)

Pull-up current

|I

|

-

1

µA

pF

= 2.0V

= 0.8V

= 2.0V

PUH

3)

Pull-up current

|

20

-

PUL

PDL

Pull-down current

|

0.8

-

|

20

-

PDH

1)

Pin capacitance

C

10

f = 1MHz @

IO

o

T = 25 C

A

1)

Not subject to production test, verified by design/characterization.

2)

3)

The maximum current that may be drawn while the respective signal line remains inactive.

The minimum current that must be drawn in order to drive the respective signal line active.

Data Sheet

43

V 1.3, 2003-10

TC1920

Preliminary

NMI Pin

NMI Pin is an input pin with different Pull-Up characteristics than other pins. The related

characteristics are given in the following table

Parameter

Symbol

Limit values

Unit Test

Conditions

min.

max.

Max. current allowed

through the Pull-Up

device while pin (input)

voltage remains still at the

high level

|I

|

-

4

uA

V

=2.0V

PUH

PUL

OUT

Min. current needed

|

100

-

uA

V

=0.8V

OUT

through the Pull-Up

device so that pin voltage

is driven to the low level.

Note: NMI Pin does not have a Pull-Down device.

Oscillator Pins

Parameter

Symbol Limit values

min.

Unit Test

Conditions

max.

Input leakage current

(analog input) at

XTAL1

I

-

±200

nA

0V< V < V

OZ1

in

DDP

CC

1)

Input low voltage

XTAL1

V

SR

-

0.3

V

-

ILX

Input high voltage

V

0.8

V

-0.3

-0.35

-0.4

f

=4MHz

=8MHz

=12MHz

=16MHz

IHX

DD

OSC

2)

XTAL1

SR

-0.43

XTAL1 input current

I

-

± 20

µA

0V < V < V

IN

IX1

DD

CC

2)

XTAL3 input current

I

± 0.5

0V < V < V

IN

IX3

DD

CC

1)

Only applicable in deep sleep mode

2)

Not subject to production test, verified by design/characterization.

Data Sheet

44

V 1.3, 2003-10

TC1920

Preliminary

IIC Pins

Each IIC Pin is an open drain output pin with different characteristics than other pins. The

related characteristics are given in the following table

Parameter

Symbol

Limit values

Unit Test

Conditions

min.

max.

Output low voltage

V

CC

-

0.4

0.6

V

3 mA

6 mA

OL

1)

Input high voltage

V

0.7V

3.6

V

-

IH

DDP

SR

1)

Input low voltage

V

-0.3

0.3V

V

-

IL

DDP

SR

Input leakage current

I

-

+ - 500

10

nA

pF

OZ2

CC

1)

Pin capacitance

C

f=1MHz@

IO

o

CC

T =25 C

A

1)

Not subject to production test, verified by design/characterization.

Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.60

V must be applied to these pads.

Note: IIC pins have no Pull-Up and Pull-Down devices.

Data Sheet

45

V 1.3, 2003-10

TC1920

Preliminary

ADC Analog I/O DC Characteristics

Parameter

Symbol Limit values

Unit Test

Conditions

min.

typ.

max.

Core supply voltage

Analog supply voltage

Analog supply ground

V

SR

1.71

1.8

1.89

V

-

DD

V

SR

3.0

-0.1

1.5

3.3

0.0

-

3.6

-

DDA

V

SR

+0.1

SSA

3)

Reference voltage

V

+

AREF

AGND

DDA

0.05

Reference ground

V

SSA

+ 0.05

SSA

- 0.05

Analog input voltage

V

−

V

AREF

A

AGND

Internal A/D Converter

clock

f

0.5

3.5

MHz -

ANA

Input leakage current

(analog input)

I

-

±200

±500

+5

nA

mA

-

0V< V <

in

OZ1

CC

V

DDA

Input leakage current

I

-

0V< V <

in

OZ2

( V

, V

)

CC

V

AGnd

ARef

DDA

1) 5)

Overload current

Overload coupling factor

Sample time

I

-2

-

AOV

SR

2)

-4

-3

3)

k

1.0x10

1.5x10

I

>0

<0

A

AOV

t

CC 4*(CHCON .STC+2)*t

for channel n

s

n

BC

3)

Conversion time

CC t + 40*t + 2*t

for 8- bit

conversion

c

S

BC

DIV

t =1/f

BC

BC,

t

=1/f

DIV

DIV,

t + 48*t + 2*t

for 10- bit

conversion

S

BC

see Figure 17.

t + 56*t + 2*t

for 12- bit

S

BC

conversion

Data Sheet

46

V 1.3, 2003-10

TC1920

Preliminary

Parameter

Symbol Limit values

Unit Test

Conditions

min.

typ.

max.

4)

Total unadjusted error

TUE

CC

± 1 LSB

for 8- bit

conversion

± 2 LSB

± 6 LSB

for 10- bit

conversion

5)

for 12- bit

conversion

On resistance of the

R

1900

Ohm

AIN

transmission gates in the CC

7)

analog voltage path

Resistance of the

reference voltage path

R

CC

2000

10

Ohm

pF

REF

7)

Switched capacitance at

the analog voltage input. CC

C

AINSW

7)

Total capacitance at

analog voltage input

C

CC

-

15

-

pF

AINTOT

6)

Switched capacitance at

the positive reference

voltage input.

C

CC

15

pF

AREFSW

7)

1)

Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the

specified operating range (i.e. V_AOV> V_DDP+0.3V or V_AOV< V_SSP-0.3V ) or a short circuit condition occurs on

the respective ADC pin. The absolute sum of input leakage and I_AOVcurrents on all port pins must not exceed

10 mA at any time. The supply voltage (V_DD, V_DDPand V_SS, V_SSP) must remain within the specified limits.

Under short-circuit conditions the corresponding pin is not ready for use.

2)

The overload coupling factor (k_A) defines the worst case relation of an overload condition (I_OV) at one pin to

the resulting total leakage current (I_leakTOT) into an adjacent pin: |I_leakTOT| = k_A× |I_OV| + I_OZ1V

Thus under overload conditions an additional error leakage voltage (V_AEL) will be induced onto an adjacent

analog input pin due to the resistance of the analog input source (R_AIN). That means V_AEL= R_AIN× |I_leakTOT|.

Please see also the analog/digital converter specification, chapter “Error Through Overload Conditions”, for

further explanations.

3)

4)

The nominal conversion time is valid for V_AREF>3.0. For V_AREF<3.0, it is approximately double.

At V_AREF=+3.3V and V_AGNDin the specified range. For V_AREF<3.3V, TUE rise and is to be multiplied with a

factor of 3.3/Vref. For V_AGNDoutside the specified range, TUE is not guaranteed.

5)

6)

7)

Tested in production on request. Standard production test is 10-bit TUE test.

Not subject to production test, verified by design/characterization.

Simulation values.

Data Sheet

47

V 1.3, 2003-10

TC1920

Preliminary

A/D C onverter

R _{AIN , Source}

R _{AIN, O n}

V_{A IN}

C _{AIN , Block}

C _{AINTO T}

-

C _{AINS W}

C _AINSW

=

M CS04879

Figure 16

Equivalent Circuitry of an Analog Input

A/D Converter Module

Sam ple

Tim e t_S

Peripheral

Clock D ivider

(1:1) to (1:8)

Program m able

Clock D ivider

(1:1) to (1:256)

f_ANA

f_DIV

f_BC

f_{AD C}

Program m able

C ounter

1:4

CO N .PCD

C O N.CTC

CH CO N n.STC

f_{TIM ER}

Arbiter

(1:20)

Control U nit

(Tim er)

Control/Status Logic

Interrupt Logic

External Trigger Logic

External M ultiplexer Logic

R equest G eneration Logic

M CA04657_m od

Figure 17

ADC Clock Circuit

Data Sheet

48

V 1.3, 2003-10

TC1920

Preliminary

Codec Electrical Characteristics

Parameter

Symbol Limit values

min. typ.

Unit

Test

Conditions

max.

1.89

3.6

Digital supply voltage

Analog supply voltage

Analog supply ground

V

1.71

3.0

1.8

3.3

0.0

1.2

V

DD

DDA

SSA

AREF

-0.1

1.14

+0.1

+1.26

1)

2)

External reference voltage V

Analog reference ground

V

0.05

- V

V

+

AGND

AIN

SSA

0.05

3)

Analog input voltage

(RMS)

0.775

-

V

rms

Analog output voltage

(RMS)

AOUT

Input Resistace of the

Analog Inputs

Ra

-

30

15

60

30

1.2

kOhm differential

input, gain:

4)

-12,-6, 0 dB

-

kOhm single-ended

input, gain:

-12,-6, 0 dB

-

kOhm differential

input, gain:

6 to 30 dB

-

kOhm single-ended

input, gain:

6 to 30 dB

Internal Reference

V

1.1

1.3

V

AGCCR.

BGPSEL[1,0]

=00

BGP

Voltage Vref (Bandgap

5)

Voltage)

1)

Reference voltage outside the nominal range causes reduced dynamic range, decreased distortion/clipping

margins, increased/decreased gain.

2)

3)

4)

5)

V_SSA=V_AGND=0V

Please take the gain settings of the analog preamplifier into account, therefore V_imaxreal=V_imax/gain

Simulation value.

For external usage only, Bandgap reference voltage is strongly dependent on the external load (<500 MOhm).

In this case, high impedance buffer must be used.

Data Sheet

49

V 1.3, 2003-10

TC1920

Preliminary

Codec ADC and DAC path characteristics

Test conditions¹⁾

Parameters

min.

typ.

max.

Unit

0

< 0.025

Attenuation distortion

(ref. freq. 1014 Hz)

(ref. level 0dBm0)²⁾

dB

-0.25

0

0.025-0.0375

0.0375-0.3

0.3-0.425

> 0.425

0.25

0.45

-55

-45

dB

at 0dBm0

Signal to total distor-

tion

-0.3

-0.6

-1.6

0.3

0.6

1.6

dB

+3 to -40 dBm0

-40 to -50 dBm0

-50 to -55 dBm0

Gain tracking

(ref. freq. 1014 Hz)

(ref. level 0dBm0)²⁾

-80

-75

dBm

0

receive &transmit

Idle channel noise

-80

-60

0

-75

-50

0.8

dB

Cross talk

at 0dBm0

Harmonic distortion

-0.8

-

receive &transmit

Gain

(ref. freq. 1014 Hz)

(ref. level 0dBm0)²⁾

3)

-60

-40

-35

dB

Receive (0.0375-0.425)

Transmit (0.0375-0.425)

Power supply

3)

rejection ratio (PSRR)

1)

2)

3)

Values given in this table are valid for all sampling frequencies.

0dBm0 is equivalent to -12dBm is equal to 194.7 mV_RMS.

Supply ripple 70 mV.

Note: Numbers without units in the test conditions column are relative frequency values

to the chosen sampling frequency. e.g. 0.425 equals 3.4 kHz @ 8 kHz sampling

frequency.

Data Sheet

50

V 1.3, 2003-10

TC1920

Preliminary

Power Supply Current

Parameter

Symbol

Limit values

Unit

Test Conditions

1)

typ.

max.

Active mode supply

current

I_DD

260

–

mA

Sum of all I_DD.

2) 3)

4)

Idle mode supply current I_ID

170

–

mA

at 1.8V Core Supply

Deep sleep mode supply I_DDS

0.25

current

1)

Typical values are measured at 25°C, CPU clock at 100MHz and nominal supply voltage, i.e. 3.3V for V_DDP

and 1.8V for V_DD, V_DDPLL, V_DDOSC

2)

3)

PORST=V

IH

The typical power consumption values in active mode are measured while running a typical application pattern.

The power consumption of modules can increase or decrease using different application programs. The PLL

is bypassed and powered down during this measurement.

4)

CPU is in idle state, input clock to all peripherals are enabled.

AC Characteristics

Operating Conditions apply.

Output Rise/Fall Times

GPIO pins

Rise/fall time measurements are made between 10% and 90%.

The following table is valid for the GPIO pins pad drivers. Output pad characteristics are

controllable via DRVCTRx registers.

Pad Modus

Symbol

Limit values

Temp Unit Test

rise / fall time

Comp

Conditions

min.

max.

Strong driver

• sharp edge

• medium edge

SF

SM

SS

-

3

6

12

yes

ns

@50pF

1)

• soft edge

1)

Not subject to production test, verified by design/characterization.

Data Sheet

51

V 1.3, 2003-10

TC1920

Preliminary

Timing Characteristics

(Operating Conditions apply)

Note: Timing parameters are not subject to production test, they are verified by design/

characterization.

2.4V

2.0V

0.8V

2.0V

0.8V

Test Points

0.4V

M CT04880

AC inputs during

testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”. Timing

measurements are made at V

for a logic “1” and V

for a logic “0”.

IHmin

ILmax

Figure 18

Input/Output Waveforms for AC Tests

- for GPIO, Dedicated and EBU pins

External Oscillator at XTAL1 Timing Requirements

(Operating Conditions apply)

Parameter

Symbol

Limits

Unit

min.

max.

1)

Main Oscillator XTAL frequency

with/without

PLL

f_OSCSR

4

16

MHz

3)

Frequency of an external oscillator with PLL

f_OSCDD

4

-

25

2)

4)

driving at XTAL1

without PLL

SR

Input Clock high time

Input Clock low time

Input Clock rise time

Input Clock fall time

t₁

t₂

t₃

t₄

SR 16

−

ns

−

7

SR −

Data Sheet

52

V 1.3, 2003-10

TC1920

Preliminary

1)

Oscillator Bypass Pin P3.11 latch-in value high. Internal oscillator provides the input clock signal.

2)

Oscillator Bypass Pin P3.11 latch-in value low. Internal oscillator disabled. External oscillator provides the input

clock signal.

3)

4)

Internal PLL provides the system clock. BYPASS pin latch-in value low. PLL prescaler value P=1.

Internal PLL bypassed. BYPASS pin latch-in value high. External oscillator provides the system clock directly.

When ADC and CODEC modules are active their frequency limitations must be taken into consideration,

together with LMB/FPI bus frequency ratio. Otherwise, minimum frequency in this mode can go as low as zero.

t_{O SC}

V_{IH X}

Input C lock

at XTAL1

0.5 V _{DD OSC}

V_ILX

t₄

t₃

t₁

t₂

M CT04882

Figure 19

External Clock at XTAL1 Requirements

, V and V are defined in the Oscillator Pins DC Characteristics

Note: V

DDOSC

IHX

IHL

Chapter.

Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters

for the oscillator operation. Please refer to the limits specified by the crystal

supplier.

Data Sheet

53

V 1.3, 2003-10

TC1920

Preliminary

CPU Clock Timing

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

CLKOUT period

t_CLKOUT10

−

ns

CC

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

t₁CC 4

t₂CC 4

−

3

ns

t₃CC

t₄CC

−

t_CPUCLK

0.9 V _DD

0.1 V _DD

0.5 V_DD

CLKOUT

t₄

t₃

t₁

t₂

M CT04883

Figure 20

CLKOUT Timing

Data Sheet

54

V 1.3, 2003-10

TC1920

Preliminary

PLL Parameters

1)

Parameter

Symbol

Limit Values

min. max.

Unit

Accumulated jitter

D_N

see Figure 21

–

2)

VCO frequency range

f_VCO

100

150

200

250

300

MHz

µs

3)

4)

5)

150

200

250

20

2)

PLL base frequency

f_PLLBASE

80

3)

20

130

180

230

200

4)

5)

20

PLL lock-in time

t_L

–

1)

Not subject to production test, verified by design/characterization.

2)

3)

4)

5)

@ vcosel = ’00’

@ vcosel = ’01’

@ vcosel = ’10’

@ vcosel = ’11’

Note: When TC1920 starts-up with the PLL not bypassed, first user instructions are

executed with the frequency defined by the VCO free-running frequency

(f_PLLBASE) and by the reset value of the PLL_CLC register (the K-divider and

VCOSEL bitfields). It is software responsibility to initialize its own appropriate

values in the bitfields in this register, before giving the command for the VCO to

lock to the input frequency. For more information, see the Users Manual, System

Units, System Control Unit chapter.

Data Sheet

55

V 1.3, 2003-10

TC1920

Preliminary

f_SYS= 100 MHz (K = 3)

f_SYS= 80 MHz (K = 3)

f_SYS= 60 MHz (K = 5)

f_SYS= 40 MHz (K = 7)

TC1920_pll_jitter

±5.0

ns

D_N

±4.0

±3.0

±2.0

±1.0

±0.0

0

5

10

15

20

25

30

35

P

D_N

= Max. jitter

P

K

= Number of consecutive f_SYSperiods

= K-divider of PLL

Figure 21

Approximated Maximum Accumulated PLL Jitter

The following two formulas define the (absolute) approximate maximum value of jitter D_N

in [ns] dependent on the K-factor, the system clock frequency f_SYSin [MHz], and the

number P of consecutive f_SYSperiods.

P

×

735

[1]

+ 0.5 ]

D_N[ns] = ± [(

+ 0.9)

×

for P <

0.25× f_SYS

f_SYS

0.25

f_SYS

×

K

735

for P >

[2]

D_N[ns] = ±

[

0.25× f_SYS

+ 1.4 ]

f_SYS

×

K

With rising number P of clock cycles the maximum jitter increases linearly up to a specific

value of P. Beyond this value of P the maximum accumulated jitter remains at a constant

value.

Data Sheet

56

V 1.3, 2003-10

TC1920

Preliminary

Timing for EBU_LMB Clock Outputs

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

EBUCLK period

EBUCLK high time

EBUCLK low time

EBUCLK rise time

EBUCLK fall time

BFCLK0 period

t₁CC 10

t₂CC 4.5

t₃CC 3

−

ns

−

t₄CC

t₅CC

−

2.5

−

t₆CC 20

t₇CC 9

t₈CC 9

BFCLK0 high time

BFCLK0 low time

BFCLK0 rise time

BFCLK0 fall time

−

t₉CC

t₁₀CC

−

3.5

2.5

t₁(t₆)

0.9 V _DD

0.1 V _DD

EBUCLK/

0.5 V _DD

BFCLK0

t₂(t₇)

t₃(t₈)

t₅(t₁₀)

t₄(t₉)

M CT04884

Figure 22

EBU_LMB Clock Output Timing

Data Sheet

57

V 1.3, 2003-10

TC1920

Preliminary

Timing for SDRAM Access Signals

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

CKE high from EBUCLK

t₁CC -

7.0

-

ns

CKE low from EBUCLK

t₂CC 2.0

t₃CC -

A(23:0) output valid from EBUCLK

A(23:0) output hold from EBUCLK

CS(6:0) low from EBUCLK

CS(6:0) high from EBUCLK

RAS low from EBUCLK

7.0

-

t₄CC 2.0

t₅CC -

7.0

-

t₆CC 2.0

t₇CC -

7.0

-

RAS high from EBUCLK

t₈CC 2.0

t₉CC -

CAS low from EBUCLK

7.0

-

CAS high from EBUCLK

t₁₀CC 2.0

t₁₁CC -

RD/WR low from EBUCLK

RD/WR high from EBUCLK

BC(3:0) low from EBUCLK

BC(3:0) high from EBUCLK

AD(31:0) output valid from EBUCLK

AD(31:0) output hold from EBUCLK

AD(31:0) input setup to EBUCLK

7.0

-

t₁₂CC 2.0

t₁₃CC -

7.0

-

t₁₄CC 2.0

t₁₅CC -

7.7

-

t₁₆CC 2.0

t₁₇SR 2.0

-

AD(31:0) input hold from EBUCLK

t₁₈SR 4.0

-

ns

Data Sheet

58

V 1.3, 2003-10

TC1920

Preliminary

Write Access:

EBUCLK

t₁

CKE

t₃

t₅

t₄

Row

Column

A(23:0)

t₆

CSx

t₈

RAS

t₇

t₁₀

CAS

t₉

t₁₂

RD/WR

BC(3:0)

AD(31:0)

t₁₁

t₁₃

t₁₄

Data

(0)

Data

(n-1)

t₁₅

t₁₆

Read Access:

EBUCLK

t₂

CKE

t₃

t₄

Row

Column

A(23:0)

t₆

CSx

RAS

t₁₀

t₉

CAS

RD/WR

BC(3:0)

t₁₃

t₁₄

t₁₈

t₁₇

Data

(0)

Data

(n-1)

AD(31:0)

MCT05319

Figure 23

SDRAM Access Timing

Data Sheet

59

V 1.3, 2003-10

TC1920

Preliminary

Timing for Burst Flash Access Signals

Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

A(23:0) output valid from BFCLK0

A(23:0) output hold from BFCLK0

CS(6:0) low from BFCLK0

ADV low from BFCLK0

t₁CC −

11.0

−

ns

t₂CC 0.0

t₃CC −

t₅CC −

t₆CC 3.0

t₇CC −

t₈CC 3.0

t₉CC −

t₁₁SR 6.0

t₁₂SR 3.0

9.0

10.0

−

ADV high from BFCLK0

BAA low from BFCLK0

10.0

−

BAA high from BFCLK0

RD low from BFCLK0

10.0

−

AD(31:0) input setup to BFCLK0

AD(31:0) input hold from BFCLK0

−

Data Sheet

60

V 1.3, 2003-10

TC1920

Preliminary

BFCLK0

A[23:0]

ADV

t₁

t₅

t₃

t₂

Address Valid

t₆

CSx

RD

t₉

t₇

t₈

BAA

t₁₁

t₁₂

Valid

D[31:0]

Note: Between the end of the Address Phase (ADV goes high) and the beginning of the Command

Phase (RD goes low) several cycles of Command Delay Phase can be inserted.

mct04889_mod_la

Figure 24

Burst Flash Access Timing (Instruction Read)

Data Sheet

61

V 1.3, 2003-10

TC1920

Preliminary

1)

Timing for Demultiplexed Access Signals

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

8.0

Uni

t

ALE high from EBUCLK

t₁CC −

ns

ALE low from EBUCLK

t₂CC 2.0

t₃CC −

−

A(23:0) output valid from EBUCLK

A(23:0) output hold from EBUCLK

CS(6:0) low from EBUCLK

CS(6:0) high from EBUCLK

MR/W low from EBUCLK

8.0

−

t₄CC 2.0

t₅CC −

8.0

−

t₆CC 2.0

t₇CC −

8.0

−

MR/W high from EBUCLK

RMW low from EBUCLK

t₈CC 2.0

t₉CC −

8.0

−

RMW high from EBUCLK

t₁₀CC 1.0

t₁₁CC −

RD low from EBUCLK

8.0

−

RD high from EBUCLK

t₁₂CC 0.0

t₁₃CC −

RD/WR low from EBUCLK

RD/WR high from EBUCLK

CMDELAY input setup to EBUCLK

CMDELAY hold from EBUCLK

WAIT input setup to EBUCLK

WAIT hold from EBUCLK

8.0

t₁₄CC 2.0

t₁₅SR 4.0

t₁₆SR 3.0

t₁₇SR 4.0

t₁₈SR 3.0

t₁₉CC −

−

BC(3:0) low from EBUCLK

BC(3:0) high from EBUCLK

AD(31:0) output valid from EBUCLK

AD(31:0) output hold from EBUCLK

AD(31:0) input setup to EBUCLK

AD(31:0) input hold from EBUCLK

8.0

−

t₂₀CC 2.0

t₂₁CC −

8.0

−

t₂₂CC 0.0

t₂₃SR 4.0

t₂₄SR 4.0

−

1)

It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase

length according to the particular asynchronous memory/peripheral device specification.

Data Sheet

62

V 1.3, 2003-10

TC1920

Preliminary

EBUCLK

ALE

t₁

t₂

t₃

t₄

Address

A(23:0)

CSx

t₅

t₆

t₇

MR/W

t₁₄

RD/WR

CMDELAY

t₁₆

t₁₅

t₁₃

t₁₈

t₁₇

WAIT

t₂₀

t₁₉

t₂₀

BC(3:0)

AD(31:0)

t₂₁

t₂₂

Data Out

MCT05320

Figure 25

Demultiplexed Write Access

Data Sheet

63

V 1.3, 2003-10

TC1920

Preliminary

EBUCLK

ALE

t₁

t₂

t₃

t₄

Address

A(23:0)

CSx

t₆

t₅

MR/W

RMW

t₈

t₁₀

t₉

t₁₂

RD

t₁₆

t₁₅

t₁₁

CMDELAY

t₁₈

t₁₇

WAIT

t₁₉

t₂₀

BC(3:0)

AD(31:0)

t₂₃

t₂₄

Data

Note: RMW signal is available only during Read-Modify-Write Access.

MCT05321

Figure 26

Demultiplexed Read Access

Data Sheet

64

V 1.3, 2003-10

TC1920

Preliminary

1)

Timing for Multiplexed Access Signals

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

ALE high from EBUCLK

t₁CC −

8.0

−

ns

ALE low from EBUCLK

t₂CC 2.0

t₃CC −

AD(31:0) output valid from EBUCLK

AD(31:0) output hold from EBUCLK

AD(31:0) input setup to EBUCLK

AD(31:0) input hold from EBUCLK

CS(6:0) low from EBUCLK

CS(6:0) high from EBUCLK

MR/W low from EBUCLK

8.0

−

t₄CC 0.0

t₅SR 4.0

t₆SR 4.0

t₇CC −

−

8.0

−

t₈CC 1.0

t₉CC −

8.0

−

MR/W high from EBUCLK

RMW low from EBUCLK

t₁₀CC 2.0

t₁₁CC −

8.0

−

RMW high from EBUCLK

t₁₂CC 1.0

t₁₃CC −

RD/WR low from EBUCLK

RD/WR high from EBUCLK

RD low from EBUCLK

8.0

−

t₁₄CC 2.0

t₁₅CC −

8.0

−

RD high from EBUCLK

t₁₆CC 0.0

t₁₇SR 4.0

t₁₈SR 3.0

t₁₉SR 4.0

t₂₀SR 3.0

t₂₁CC −

CMDELAY input setup to EBUCLK

CMDELAY hold from EBUCLK

WAIT input setup to EBUCLK

WAIT hold from EBUCLK

−

BC(3:0) low from EBUCLK

BC(3:0) high from EBUCLK

8.0

−

t₂₂CC 2.0

1)

It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase

length according to the particular asynchronous memory/peripheral device specification.

Data Sheet

65

V 1.3, 2003-10

TC1920

Preliminary

EBUCLK

ALE

t₁

t₂

t₃

t₄

Address

Data

AD(31:0)

CSx

t₇

t₄

t₈

t₃

t₉

MR/W

t₁₄

RD/WR

CMDELAY

WAIT

t₁₈

t₁₇

t₁₃

t₂₀

t₁₉

t₂₂

t₂₁

t₂₂

BC(3:0)

MCT05322

Figure 27

Multiplexed Write Access

Data Sheet

66

V 1.3, 2003-10

TC1920

Preliminary

EBUCLK

ALE

t₁

t₂

t₅

t₃

t₆

Address

Data

AD(31:0)

CSx

t₄

t₈

t₇

t₁₀

t₁₁

MR/W

RMW

t₁₂

t₁₆

RD

t₁₈

t₁₇

t₁₅

CMDELAY

t₂₀

t₁₉

WAIT

t₂₁

t₂₂

BC(3:0)

Note: RMW signal is only available during Read-Modify-Write Access.

MCT05323

Figure 28

Multiplexed Read Access

Data Sheet

67

V 1.3, 2003-10

TC1920

Preliminary

Timing for External Bus Arbitration Signals

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

HOLD input setup to EBUCLK

HOLD input hold from EBUCLK

HLDA low from EBUCLK

t₁SR 6.0

t₂SR 8.0

t₃CC −

t₄CC −

t₅SR 8.0

t₆SR 8.0

t₇CC −

t₈CC −

−

ns

−

10.0

9.0

−

HLDA high from EBUCLK

HLDA input setup to EBUCLK

HLDA input hold from EBUCLK

BREQ low from EBUCLK

−

10.0

9.0

BREQ high from EBUCLK

Note: The signals HOLD, HLDA and BREQ are alternate function of the CS5, CS6 and

CSOVL Pins.

Data Sheet

68

V 1.3, 2003-10

TC1920

Preliminary

External Master Mode

EBU C LK

t₁

t₂

H OLD

t₄

H LDA

t₃

t₈

BR EQ

t₇

External Slave Mode

EBU C LK

t₇

t₈

BR EQ

H LDA

H OLD

t₅

t₆

t₁

t₂

M CT05324_m od

Figure 29

External Bus Arbitration Timing

Data Sheet

69

V 1.3, 2003-10

TC1920

Preliminary

SSC Master Mode Timing

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limit Values

max.

Unit

min.

CC 40

CC

SCLK period

t

ns

SCLK

MTSR low/high from SCLK edge

MRST setup to SCLK edge

MRST hold from SCLK edge

-

2.0

5

6

7

SR 15

-

t_SCLK

0.9 V_{D D}

SCLK

0.5 V_DD

(C O N.PO ,CO N.P H=00 or 11)

0.1 V_{D D}

0.9 V_{D D}

0.1 V_{D D}

SCLK

0.5 V_DD

(C O N.PO ,CO N.P H=01 or 10)

t₅

MTSR

MRST

State n-1

S tate n

State n+1

t₆

t₇

Data valid

M C T04885m od

Figure 30

SSC Master Mode Timing

Data Sheet

70

V 1.3, 2003-10

TC1920

Preliminary

Package Outlines

Figure 31

LBGA-260 Package

You can find all of our packages, sorts of packing and other in our Infineon Internet Page

“Products”: http://www.infineon.com/products

•

Data Sheet

71

V 1.3, 2003-10

TC1920

Preliminary

Data Sheet

72

V 1.3, 2003-10

((73))

Infineon goes for Business Excellence

“Business excellence means intelligent approaches and clearly

defined processes, which are both constantly under review and

ultimately lead to good operating results.

Better operating results and business excellence mean less

idleness and wastefulness for all of us, more professional

success, more accurate information, a better overview and,

thereby, less frustration and more satisfaction.”

Dr. Ulrich Schumacher

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	TC1920
厂家：	Infineon
描述：	32-Bit Single-Chip Microcontroller 32位单芯片微控制器微控制器
文件：	总78页 (文件大小：2938K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC1920 [INFINEON]

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