TDA21310XUMA1 [INFINEON]
Half Bridge Based MOSFET Driver,;
| 型号： | TDA21310XUMA1 |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based MOSFET Driver, |
| 文件： | 总23页 (文件大小：694K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Performance DrBLADE
5 mm x 5 mm x 0.6 mm IQFN
TDA21310
Data Sheet
Revision 2.1, 2013-09-05
Power Management and Multi Market
Edition 2013-09-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all
warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual
property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
TDA21310
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 2.1 2013-09-05
Temperature Rise diagram added
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™,
CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™,
PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™,
SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE
OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd.
Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2010-10-26
Data Sheet
3
Revision 2.1, 2013-09-05
TDA21310
Applications
1
Applications
Desktop and Server buck-converter
Single Phase and Multiphase POL
CPU/GPU Regulation in Desktop Graphics Cards, DDR Memory, Graphic Memory
High Power Density Voltage Regulator Modules (VRM).
2
Features
Compatible to Intel® VR12 Driver and Mosfets Module (DrMOS) functionality for Desktop/Server Applications
For synchronous buck converter step down voltage applications
Power MOSFETs rated 25 V for safe operation under all conditions
Fast switching technology for improved performance at high switching frequencies (> 1 MHz)
+5 V high side and low side MOSFETs driving voltage
Compatible to standard +3.3 V PWM controller integrated circuits
Small package: LG-UIQFN-32-2 (5 x 5 x 0.6 mm³)
Optimized footprint for improved cooling by the PCB
DC output current up to 40A
94% peak efficiency at 1.2V1
DC input voltage up to +16 V
Remote driver disable function
Includes bootstrap diode
Undervoltage lockout
Shoot through protection
Tri-state PWM input functionality
Top side cooling
RoHS compliant
Table 1
Product Identification
Temp Range
Part Number
TDA21310
Package
Marking
LG-UIQFN-32-2 (5 x 5 x 0.6 mm³)
TDA21310
-25 C to 125 C
Figure 1
Picture of the Product
1 Typical power stage efficiency, VIN=12V, VDRV=VCIN=5V, fSW=300kHz, L=210nH, 0.2mΩ, no air flow, no heat sink.
Data Sheet Revision 2.1, 2013-09-05
4
TDA21310
Description
3
Description
3.1
Pinout
VIN Pin #9
VIN Pin #10
VIN Pin #11
VSWH Pin #12
Pin #32 VCIN
Pin #31
Pin #30
VDRV
PGND
VIN
Pin #29 VSWH
VSWH
PGND
PGND
Pin #13
Pin #14
Pin #28
Pin #27 VSWH
Pin #26 VSWH
Pin #25 VSWH
VSWH
PGND Pin #15
PGND Pin #16
Figure 2
Pinout, numbering and name of pins (transparent top view)
I/O Signals
Table 2
Pin No.
4
Name
Pin Type Buffer Type Function
PWM
I
I
I
I
+3.3 V logic PWM drive logic input
The tri-state PWM input is compatible with 3.3 V.
+3.3 V logic Enable signal (active high)
5
6
7
DR_EN
BOOT
Connect to GND to disable the IC.
Bootstrap voltage pin
Analog
Analog
Connect to BOOT capacitor
PHASE
Switch node (reference for Boot voltage)
internally connected to VSWH pin, connect to BOOT
capacitor
12, 25 to 29, VSWH
VSWH pad
O
Analog
Switch node output
High current output switching node
Data Sheet
5
Revision 2.1, 2013-09-05
TDA21310
Description
Table 3
Pin No.
Power Supply
Name Pin Type Buffer Type Function
8 to 11, VIN pad
VIN
VDRV POWER
VCIN POWER
POWER
–
–
–
Input voltage
Supply of the drain of the high side MOSFET
FET gate supply voltage
31
32
High and low side MOSFETs gate drive supply
Logic supply voltage
5 V bias voltage for the internal logic
Table 4
Pin No.
1
Ground Pins
Name
Pin Type Buffer Type Function
CGND GND
–
Control signal ground
Should be connected to PGND externally
13 to 24, 30
PGND GND
–
Power ground
All these pins must be connected to the power GND
plane through multiple low inductance vias.
Table 5
Pin No.
2, 3
Not Connected
Name
Pin Type Buffer Type Function
NC
–
–
No internal connection
Leave pin floating or tie to GND.
Data Sheet
6
Revision 2.1, 2013-09-05
TDA21310
Description
3.2
General Description
The Infineon TDA21310 is a multichip module that incorporates Infineon’s premier MOSFET technology for a
single high side and a single low side MOSFET coupled with a robust, high performance, high switching
frequency gate driver in a single 32 pin LG-UIQFN-32-2 package. The optimized gate timing allows for
significant light load efficiency improvements over discrete solutions. State of the art MOSFET technology
provides exceptional full load performance.
When combined with Infineon’s family of digital multi-phase controllers, the TDA21310 forms a complete core-
voltage regulator solution for advanced micro and graphics processors as well as point-of-load applications.
The TDA21310 is not pin compatible to the Intel 6x6 DrMOS specification, but compatible by functionality. The
device package height is only 0.6 mm, and is an excellent choice for applications with critical height limitations.
It has reduced thermal impedance from junction to top case compared to DrMOS, allowing for top side cooling.
PHASE
BOOT
VCIN
DRIVER
IC
VIN
HS
Driver
HS
MOSFET
GH
Level
UVLO
Shifter
10k
VDRV
DR_EN
500k
Shoot Through
Protection Unit
HS
Logic
+
CGND
VCIN
-
VSWH
+
16k5
Input
Logic
Tri-
-
PWM
7k1
LS
VDRV
State
MOSFET
CGND
GL
LS
Logic
LS
Driver
10k
PGND
CGND
VDRV
Figure 3
Simplified Block Diagram
Attention: GH and GL are not accessible. They are mentioned for clarity in this block diagram.
Data Sheet
7
Revision 2.1, 2013-09-05
TDA21310
Electrical Specification
4
Electrical Specification
4.1
Absolute Maximum Ratings
Note: TA = 25°C
Stresses above those listed in Table 6 “Absolute Maximum Ratings” may cause permanent damage to the
device. These are absolute stress ratings only and operation of the device is not implied or recommended at
these or any other conditions in excess of those given in the operational sections of this specification. Exposure
over values of the recommended ratings (Table 8) for extended periods may adversely affect the operation and
reliability of the device.
Table 6
Absolute Maximum Ratings
Symbol
Parameter
Values
Unit
Note / Test Condition
Min.
–
Typ.
–
Max.
1.2 MHz
Frequency of the PWM input
Maximum DC load current
Input Voltage
fSW
–
–
IOUT
–
–
40
16
A
V
VIN (DC)
-0.30
-0.30
-0.30
-1
–
Logic supply voltage
VCIN (DC)
VDRV (DC)
VSWH (DC)
VSWH (AC)
VPHASE (DC)
VPHASE (AC)
VBOOT (DC)
VBOOT (AC)
–
6.5
6.5
16
–
–
–
–
–
–
–
–
–
High and Low side driver voltage
Switch node voltage
–
–
-102
–
25
PHASE node voltage
BOOT voltage
-1
–
16
-10
-0.3
-12
–
25
–
22.5
31.5
6.5
–
VBOOT-PHASE
(DC)
-1
–
DR_EN voltage
VDR_EN
VPWM
TJmax
TSTG
-0.3
-0.3
-40
-55
–
–
–
–
5.5
5.5
–
–
–
–
PWM voltage
Junction temperature
Storage temperature
150
150
C
Note: All rated voltages are relative to voltages on the CGND and PGND pins unless otherwise specified.
2 AC is limited to 10 ns
Data Sheet
8
Revision 2.1, 2013-09-05
TDA21310
Electrical Specification
4.2
Thermal Characteristics
Table 7
Thermal Characteristics
Parameter
Symbol
Values
Typ.
29
Unit
Note / Test Condition
Min.
Max.
θJS-driver
θJtop-driver
θJS-HS
K/W
Thermal resistance between driver
junction and soldering point3
–
–
–
Thermal resistance between driver
junction and top of package
–
–
14
2
–
–
–
–
Thermal resistance between high-side
MOSFET junction and soldering point3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
θJtop-HS
Thermal resistance between high-side
MOSFET junction and top of package
7
θJS-LS
Thermal resistance between low-side
MOSFET junction and soldering point3
1
θJtop-LS
Thermal resistance between low-side
MOSFET junction and top of package
2
θJJ-driver-HS
θJJ-driver-LS
θJJ-LS-HS
Thermal resistance between driver
junction and high-side MOSFET junction
40
60
36
Thermal resistance between driver
junction and low-side MOSFET junction
Thermal resistance between low-side
MOSFET junction and high-side MOSFET
junction
4.3
Recommended Operating Conditions and Electrical Characteristics
Note: VDRV = VCIN = 5 V, TA = 25°C
Table 8
Recommended Operating Conditions
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
16
6
Input voltage
VIN
5
–
5
5
V
–
–
MOSFET driver voltage
Logic supply voltage
VDRV
VCIN
4.5
4.5
6
VCIN rising,3.3V to 3.9V:
dvCIN/dt > 300V/s
Junction temperature
TjOP
-25
–
125
°C
–
3 The junction-soldering point is referred to the bottom exposed pad.
Data Sheet
9
Revision 2.1, 2013-09-05
TDA21310
Electrical Specification
Table 9
Voltage Supply And Biasing Current
Parameter
Symbol
Min.
Values
Typ.
Unit
Note / Test Condition
Max.
UVLO rising
VUVLO_R
–
3.5
–
V
VCIN rising,3.3V to 3.9V:
dvCIN/dt > 300V/s
VCIN falling
UVLO falling
Driver current
VUVLO_F
–
–
3.1
12
–
–
IVDRV_300kHz
mA
DR_EN = 3.3V,
fSW = 300 kHz
IVDRV_1MHz
IVDRV_PWML
–
–
38
25
–
–
DR_EN = 3.3V,
fSW = 1 MHz
μA
DR_EN = 3.3V, PWM =
0 V
DR_EN = 0V, PWM = 3.3V
IVDRV_PWMH
IVCIN_PWML
–
–
12
–
–
IC current (control)
IC quiescent
400
DR_EN = 3.3 V, PWM =
0 V
IVCIN_O
–
–
500
–
DR_EN = 3.3 V,
PWM = Open
DR_EN = 0 V
ICIN+IDRV
–
550
Table 10
Logic Inputs And Threshold
Symbol
Parameter
Values
Typ.
1.1
Unit
Note / Test Condition
Min.
0.7
1.9
–
Max.
DR_EN Input low
Input high
VDR_EN_L
VDR_EN_H
IDR_EN
1.3
V
VDR_EN falling
VDR_EN rising
VDR_EN = 1 V
VPWM falling
VPWM rising
VPWM = 1 V
VPWM_O
2.1
2
2.4
–
Sink current
μA
PWM
Input low
VPWM_L
VPWM_H
RIN-PWM
VPWM_O
VPWM_S
–
–
0.7
–
V
Input high
2.4
3
–
k
Input resistance
Open voltage
5
7
–
1.5
–
–
V
Tri-state shutdown
window4
1.2
1.9
–
4 Maximum voltage range for tri-state
Data Sheet
10
Revision 2.1, 2013-09-05
TDA21310
Theory of Operation
Table 11
Timing Characteristics
Parameter
Symbol
Values
Typ.
15
Unit
Note / Test Condition
Min.
Max.
PWM tri-state to VSWH rising
delay or VSWH falling delay
t_pts
–
–
ns
VSWH Shutdown Hold-Off time t_tsshd
–
–
150
20
–
–
PWM to VSWH turn-off
propagation delay
t_pdlu
PWM to VSWH turn-on
propagation delay
t_pdll
–
–
–
20
20
20
–
–
–
DR_EN turn-off propagation
delay falling
t_pdl_DR_EN
t_pdh_DR_EN
DR_EN turn-on propagation
delay rising
PWM minimum pulse width
PWM minimum off time
ton_min_PWM
toff_min_PWM
–
–
25
–
–
100
5
Theory of Operation
The TDA21310 incorporates a high performance gate driver, one high-side power MOSFET and one low-side
power MOSFET in a single 32 pin LG-UIQFN-32-2 package. The advantages of this arrangement are found in
the areas of increased performance, increased efficiency and lower overall package and layout inductance. This
module is ideal for use in Synchronous Buck Regulators.
The power MOSFETs are optimized for 5 V gate drive enabling excellent high load and light load efficiency. The
gate driver is a robust high-performance driver rated at the switching node for DC voltages ranging from -1 V to
+16 V. The power density for transmitted power in a multiphase regulator of this approach can easily be higher
than 40 W per phase within a 25 mm2 area.
5.1
Driver Characteristics
The gate driver of the TDA21310 has two input voltages, VCIN and VDRV. VCIN is the 5 V logic supply for the
driver. VDRV sets the driving voltage for the high side and low side MOSFETs. The reference for the gate driver
control circuit (VCIN) is CGND. To decouple the sensitive control circuitry (logic supply) from a noisy
environment a ceramic capacitor must be placed between VCIN and CGND close to the pins. VDRV needs also
to be decoupled using a ceramic capacitor (MLCC) between VDRV and PGND in close proximity to the pins.
PGND serves as reference for the power circuitry including the driver output stage.
Referring to the Block Diagram page 7, VCIN is internally connected to the UVLO circuit. It will force shut-down
for insufficient VCIN voltage. VDRV supplies the floating high-side drive – consisting of an active boot circuit -
and the low-side drive circuit. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to
prevent false GH turn on during insufficient power supply level condition (BOOT cap charging/discharging
sequence). During undervoltage both GH and GL are driven low actively; further passive pull-down (10 k) is
placed across gate-source of both FETs.
Data Sheet
11
Revision 2.1, 2013-09-05
TDA21310
Theory of Operation
UVLO Output
Logic Level
“H”
Enable
Shutdown
“L”
VUVLO_R
VUVLO_F
VCIN
Figure 4
Internal Output Signal from UVLO Unit
5.2
Inputs to the Internal Control Circuits
The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3 V.
The PWM input has tri-state functionality. When the voltage remains in the specified PWM-shutdown-window for
at least the PWM-shutdown-holdoff time t_tsshd, the operation will be suspended by keeping both MOSFET
gate outputs low. Once left open, the pin is held internally at a level of VPWM_O = 1.5 V level.
Table 12
PWM Pin Functionality
PWM logic level
Driver output
Low
GL= High, GH = Low
GL = Low, GH = High
GL = Low, GH = Low
High
Open (left floating, or high impedance)
Using a wide range VCIN power supply (from 4.5 V to 6 V) causes a shifting in the threshold voltages for the
following parameters: VPMW_O, VPWM_H, VPWM_L. The typical behavior of these thresholds over VCIN voltage
variation is shown in the following graph.
Data Sheet
12
Revision 2.1, 2013-09-05
TDA21310
Theory of Operation
Figure 5
Variation of PWM levels versus VCIN logic supply voltage
Attention: The VPWM_S is also temperature dependent.
VCIN requires a minimum dv/dt of 300V/s in the vicinity of the UVLO threshold to prevent the driver logic from
emitting any gate drive glitches.
The DR_EN is an active high signal. When DR_EN is pulled low, the power stage is disabled.
Table 13
DR_EN Pin Functionality
DR_EN logic level
Driver output
Low
Shutdown : GL = GH = Low
Enable : GL = GH = Active
Shutdown : GL = GH = Low
High
Open (left floating, or high impedance)
5.3
Shoot Through Protection
The TDA21310 driver includes gate drive functionality to protect against shoot through. In order to protect the
power stage from overlap, both high-side and low-side MOSFETs being on at the same time, the adaptive
control circuitry monitors specific voltages. When the PWM signal transitions to low, the high-side MOSFET will
begin to turn off after the propagation delay time t_pdlu. When VGS of the high-side MOSFET is discharged
below 1 V (a threshold below which the high-side MOSFET is off), a secondary delay t_pdhl is initiated. After
that delay the low-side MOSFET turns on regardless of the state of the “VSWH” pin. It ensures that the
converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each
switching cycle. See Figure 8 for more detail.
Data Sheet
13
Revision 2.1, 2013-09-05
TDA21310
Application
6
Application
6.1
Implementation
CBOOT
470 nF
PWM
VIN
VIN (4.5V - 16V)
1 µF
8
7
CIN
4x10 µF
6
5
4
3
2
1
VCIN
32
31
30
9
+ 5 V
VDRV
PGND
10
11
12
13
14
15
16
1 µF
VIN
VIN
29
28
27
26
25
VSWH
VSWH
PGND
VSWH
L
VOUT
COUT
17 18 19 20 21 22 23
24
PGND
Figure 6
Note:
Pin interconnection outline (transparent top view)
1. Pin PHASE is internally connected to VSWH node
2. It is recommended to place a RC filter between VCIN and VDRV as shown.
3. During power-up and down sequences, the PWM signal must be either low or tri-state (open voltage), but
never high, in order to avoid uncontrolled output voltage.
Data Sheet
14
Revision 2.1, 2013-09-05
TDA21310
Application
6.2
Typical Application
Figure 7
Four-phase voltage regulator - typical application (simplified schematic)
Data Sheet
15
Revision 2.1, 2013-09-05
TDA21310
Gate Driver Timing Diagram
7
Gate Driver Timing Diagram
VPWM_H
VPWM_H
VPWM_H
Tri-State
VPWM_L
PWM
VPWM_L
t_pdlu
t_pdll
t_pts
t_tsshd
t_tssh
t_pts
VSWH
Note: VSWH during entering/exiting tri-state
behaves dependend on inductor current.
Figure 8
Adaptive gate driver timing diagram
Active
Active
VDR_EN_H
DR_EN
Deactivated
VDR_EN_L
t_pdh(DR_EN)
t_pdl(DR_EN)
Figure 9
DR_EN timing diagram (PWM is assumed “high”)
Data Sheet
16
Revision 2.1, 2013-09-05
TDA21310
Performance Curves – Typical Data
8
Performance Curves – Typical Data
Operating conditions (unless otherwise specified): VIN = +12 V, VCIN = VDRV = +5 V, LOUT=150nH (Cooper,
FPI0906R1-R15, DCR = 0.29 mΩ) inductor, TA = 25 °C, airflow = 300 LFM, no heatsink. Efficiency and power
loss reported herein include only TDA21310 losses.
8.1
Temperature Rise
Figure 10 Temperature Rise over Output Current
Data Sheet
17
Revision 2.1, 2013-09-05
TDA21310
Performance Curves – Typical Data
8.2
Driver Current versus Switchig Frequency
Figure 11 Driver Current over Switching Frequency in CCM Operation
Data Sheet
18
Revision 2.1, 2013-09-05
TDA21310
Performance Curves – Typical Data
8.3
Efficiency and Power Loss versus Switching Frequency
Figure 12 Efficiency at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.82 V, Parameter: fSW
Figure 13 Power Loss at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.82 V, Parameter: fSW
Data Sheet 19 Revision 2.1, 2013-09-05
TDA21310
Performance Curves – Typical Data
Figure 14 Efficiency at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.218 V, Parameter: fSW
Figure 15 Power Loss at VIN = 12 V, VCIN = VDRV = 5 V, VOUT = 1.218 V, Parameter: fSW
Data Sheet 20 Revision 2.1, 2013-09-05
TDA21310
Mechanical Drawing LG-UIQFN-32-2
9
Mechanical Drawing LG-UIQFN-32-2
Figure 16 Mechanical dimensions
Data Sheet
21
Revision 2.1, 2013-09-05
TDA21310
Mechanical Drawing LG-UIQFN-32-2
Figure 17 Stencil dimensions (in mm)
Data Sheet
22
Revision 2.1, 2013-09-05
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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