TDA38725-0000 [INFINEON]
OptiMOS™ IPOL single-voltage synchronous buck regulator 25 A with PMBus interface;
| 型号： | TDA38725-0000 |
| 厂家： | 
Infineon |
| 描述： | OptiMOS™ IPOL single-voltage synchronous buck regulator 25 A with PMBus interface |
| 文件： | 总65页 (文件大小：1651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA38740/25
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Quality Requirement Category: Industrial
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 4.5 V to 17 V application or Wide Input Voltage Range from 3.0 V to 17 V with external Vcc
Output Voltage Range: 0.25 V to 5.12 V based on Output Feedback resistor divider network
Enhanced Fast COT Engine Stable with Ceramic output Capacitors without External Compensation
Optional Forced Continuous Conduction Mode and Diode Emulation for Enhanced Light Load Efficiency
Pin programmable Output Voltage, Switching Frequency/mode selection with 16 unique selectable settings
Programmable Switching Frequency from 400 kHz to 2 MHz in steps of 200 kHz, excluding 1600 kHz
Monotonic Start-Up with Selectable Soft-Start Time through PMBus commands & Pre-Bias Start-Up
Thermally Compensated Internal Over Current Protection with Eight Selectable Settings
Enable input with Voltage Monitoring Capability & Power Good Output
PMBus system interface for reporting of Temperature, Voltage, Current & Power telemetry
Single image Multiple Time Programming (MTP) for the USER section
Digitally programmable load-line without any external components
Operating temp: -40 °C < Tj < 125 °C
Small Size: 5 mm x 6 mm PQFN
Lead-free, Halogen-free and RoHS2 Compliant with Exemption 7a
Applications
•
•
•
•
Server Applications
Storage Applications
Telecom & Datacom Applications
Distributed Point of Load Power Architectures
Description
The TDA38740/725 is an easy-to-use, fully integrated and highly efficient dc-dc regulator. The onboard PWM
c87tr855er a7d O9t2MOS™ FETs with integrated bootstrap diode make TDA38740/725 a small footprint solution,
providing high-efficiency power delivery. Furthermore, it uses a fast Constant On-Time (COT) control scheme,
which simplifies the design efforts and achieves fast transient response.
TDA38740/725 is a versatile regulator, operating with wide input and output voltage ranges, offering
programmable switching frequency from 400 kHz to 2 MHz, and providing eight unique selectable current limits.
It features a programmable dc loadline, which provides an additional tool to manage the transient response.
It also features important protection functions, such as pre-bias start-up, thermally compensated current limit,
over voltage and under voltage protection, and thermal shutdown to give required system level security in the
event of fault conditions. The dev2ce c87f20urat287 ca7 be eas25y def27ed us270 I7f27e87ꢀs XDP Designer GUI and is
stored in the on-chip memory. The controller requires the fewest possible external components and results in a
simplified Bill of Materials (BOM).
Final Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Table of contents
1
2
3
4
5
6
Ordering Information ..................................................................................................... 4
Functional Block Diagram............................................................................................... 5
Typical Application Diagram ........................................................................................... 6
Pin Descriptions ............................................................................................................ 7
Absolute Maximum Ratings............................................................................................. 9
Thermal Characteristics ................................................................................................11
7
7.1
Electrical Specifications ................................................................................................12
Electrical Characteristics ......................................................................................................................13
8
Pin Strap Resistors Application Information ....................................................................19
9
Typical Efficiency and Power Loss Curves ........................................................................23
PVin = Vin = 12 V, Vout = 1.2V, Fsw = 600kHz .............................................................................................23
PVin = Vin = 12 V, Fsw = 800 kHz ................................................................................................................24
PVin = Vin = 12 V, Fsw = 1000 kHz...............................................................................................................25
9.1
9.2
9.3
10
11
12
Thermal De-rating curves ..............................................................................................27
RDS(on)of MOSFET Over Temperature ............................................................................29
Typical operating characteristics (-ꢀꢁ °C ≤ Tj ≤ +ꢂꢃꢄ °Cꢅ .....................................................30
13
General Description ......................................................................................................32
PMBUS Operating Mode........................................................................................................................32
Multiple Time Programming Memory (MTP) ........................................................................................32
Voltage Sense ........................................................................................................................................32
I2C & PMBus Interface ...........................................................................................................................33
Infineon XDP Designer GUI....................................................................................................................33
Programming.........................................................................................................................................34
Real-time Monitoring ............................................................................................................................34
13.1
13.2
13.3
13.4
13.5
13.6
13.7
14
Theory of Operation......................................................................................................35
Device Power-On and Initialization ......................................................................................................35
Pre-bias start-up....................................................................................................................................35
Internal Low-Droput (LDO) Regulator ..................................................................................................35
Fast Constant ON-Time Control............................................................................................................36
EN (Enable) Pin......................................................................................................................................36
Switching Frequency and FCCM/DEM Operation.................................................................................37
Soft Start................................................................................................................................................37
Load-line................................................................................................................................................38
Output Voltage Differential Sensing.....................................................................................................38
Output Current Sensing ........................................................................................................................39
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
15
Faults and Protections ..................................................................................................40
Over Current Protection (OCP) .............................................................................................................40
Output Under Voltage Protection (UVP)...............................................................................................41
Over Voltage Protection (OVP)..............................................................................................................42
Over Temperature Protection (OTP) ....................................................................................................43
Boot Under Voltage Lockout (UVLO) ....................................................................................................43
Minimum On - Time and Minimum Off - Time ......................................................................................43
High-Side Short (HSS) Detection ..........................................................................................................44
15.1
15.2
15.3
15.4
15.5
15.6
15.7
16
16.1
16.2
Faults Communication ..................................................................................................45
PMBUS Slave Addressing ......................................................................................................................45
Real-Time Telemetry.............................................................................................................................45
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
16.3
16.4
16.5
SMBUS/PMBUS PROTOCOLS ................................................................................................................45
11-BIT Linear Data Format....................................................................................................................51
16-BIT Linear Data Format....................................................................................................................52
17
Design example ............................................................................................................53
Enabling the TDA38740/725..................................................................................................................53
Programming the Switching Frequency and Operation Mode............................................................53
Selecting Input Capacitors....................................................................................................................53
Inductor Selection.................................................................................................................................54
Output Capacitor Selection ..................................................................................................................54
Bootstrap Capacitor..............................................................................................................................55
VI and VCC/LDO bypass Capacitor........................................................................................................55
Design Recommendations....................................................................................................................55
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
18
Layout Recommendations .............................................................................................56
PCB Metal and Component Placement ................................................................................................57
Solder Resist..........................................................................................................................................57
Stencil Design ........................................................................................................................................58
18.1
18.2
18.3
19
Package.......................................................................................................................60
Marking Information .............................................................................................................................60
Dimensions............................................................................................................................................60
Tape and Reel Information ...................................................................................................................63
19.1
19.2
19.3
20
21
Environmental Qualifications.........................................................................................64
Revision History ...........................................................................................................65
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Ordering Information
1
Order270 I7f8r6at287
Table 1
Ordering Information
Package Type
Base Part
Number
Standard Pack
Orderable Part Number
Form and Qty
TDA38740
TDA38725
QFN 5 mm x 6 mm
QFN 5 mm x 6 mm
Tape and Reel
Tape and Reel
5000
5000
TDA38740aabbAUMA1
TDA38725aabbAUMA1
TDA38740-aabb
Configuration File Identifier
00: Register Configurable
20: Pin Configurable
Customer Identifier
00: Generic part
Orderable Part Number Description
TDA38740/25
29
35
34
33
32
31
30
36
1
2
3
4
5
6
28
ILIM
PGOOD
VIN
VBT
27
26
EN
BOOT
25
VCC/LDO
PHASE
PVIN
24
23
22
VDRV
GATEL
37
GATEL
PVIN
7
PGND
PGND
PGND
PGND
PVIN
PVIN
8
21
20
19
9
PVIN
10
PGND
11
12
15
17
13
16
14
18
SW SW SW SW SW SW SW SW
Figure 1
Package Top View
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Functional Block Diagram
2
Fu7ct287a5 B58c4 D2a0ra6
VDRV
VIN
VCC/LDO
AGND
PGOOD
LDO
AGND
Boot Drive
IMON
VO
VCC
BOOT
PVIN
Boot
UVLO
VDAC
AGND
VBT
DIGITAL
Signal
POR
Conditioning
Block
BLOCK
Registers and MTP
HDrVin
HDrv
OVP
UVLO
OTP
Fault Control
POR, OCP, OVP, OTP, Retry
PHASE
SW
Retry
UVP
GATE
DRIVE
LOGIC
VDRV
EN
3V3
LDrVin
LDrv
PWM
VO PVin
PWM
COMP
SS
SM_ADDR/PROG
VOSENM
+
-
ADAPTIVE
ON-TIME
GENERATOR
SET
ZC
-
+
PGND
Zero Cross
DETECTION
Sw
VO
PGND
GATEL
AFE
AOCP
VDAC
Low Side
Rdson Sensing
VOSENP
IMON
RAMP GENERATOR
3V3
3V3
MODE/TON
ILIM
Sw
ILIM Ref
3V3
SM_ALERT#
VDAC
VREF
VBT
PMBUS INTERFACE BLOCK
SM_CLK
VBT
SM_DATA
Digital Block
Figure 2
Block Diagram
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Typical Application Diagram
3
Typ2ca5 App52cat287 D2a0ra6
4.5V<Vin<17V
Enable
PVin
Vin
Enable
Boot
Phase
SW
3.3V
Vcc
Vcc/LDO
3.3V
Vo
VDRV
PGood
PGood
TDA38740/25
SM_ALERT#
SM_CLK
ALERT#
CLK
SM_DAT
VBT
DATA
GATEL
SM_ADDR/PROG
VOSENP
VOSENM
Ton/Mode
ILIM
AGnd
PGnd
Figure 3
TDA38740/725 application circuit for Vout< 2.5 V
4.5V<Vin<17V
Enable
PVin
Vin
Enable
Boot
Phase
SW
3.3V
Vcc
Vcc/LDO
3.3V
Vo
VDRV
PGood
PGood
TDA38740/25
R1
R2
R3
SM_ALERT#
SM_CLK
ALERT#
CLK
SM_DAT
VBT
DATA
GATEL
SM_ADDR/PROG
VOSENP
VOSENM
Ton/Mode
ILIM
AGnd
PGnd
Figure 4
TDA38740/725 application circuit for Vout> 2.5 V
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Pin Descriptions
4
P27 Descr2pt287s
Note: A- Analog; D- Digital; [I]- INPUT; [O]- OUTPUT; [B]- BI-DIRECTIONAL; [P]- POWER
Table 2
Pin#
Pin Descriptions
Pin Name
Pin Type
Pin Description
Connect a resistor to ground to set Over Current Protection
(OCP) limit. Eight user selectable OCP limits are available.
Power Good status output pin is open drain. Connect a pull
up resistor from this pin to an external bias voltage.
Input voltage for an Internal LDO. A 4.7 uF capacitor should
be connected between this pin and PGND. If an external
supply is connected to theVcc/LDO pin, this pin should be
shorted to the Vcc/LDO pin and a 2.2 uF ceramic capacitor
can be shared with Vin and Vcc/LDO.
1
ILIM
A[I]
2
PGood
D[O]
3
VIN
A[I]
Input bias for an external Vcc voltage /Output of the internal
LDO. A 2.2 uF ceramic capacitor is recommended to use
between Vcc, VDRV and the Power ground (PGND). An
optional decoupling capacitor can be placed between
Vcc/LDO and AGND. Connect to external supply when
internal LDO not being used.
VDRV should be shorted to the Vcc/LDO pin on the PCB. A
2.2 uF ceramic capacitor is recommended to use between
VDRV, Vcc/LDO and the Power ground (PGND). Connect to
external supply when internal LDO not being used.
Gate of Low-side FET. The signal on this pin should be used
for test purposes only and should not have external
components connected to it. Leave it opened if not used.
Power Ground. S18u5d be c877ected t8 t1e syste6ꢀs 98wer
ground plane. PGND and AGND are internally connected via
the lead frame.
4
5
Vcc/LDO
VDRV
A[P]
A[P]
6, 37
GATEL
PGND
A [O]
-
7, 8, 9, 10, 19
11, 12, 13, 14,
15, 16, 17, 18
SW
A [O]
A [P]
Switch Node. Connect these pins to an output inductor.
Input supply for the power stage.
20, 21, 22, 23,
24
PVin
Source of High-side FET. Connect a bootstrap capacitor
between this pin and the Boot pin. A high temperature (X7R)
0.1 uF or greater value ceramic capacitor is recommended.
Supply voltage for the high side driver. Connect this pin to
the Phase pin of the regulator through a bootstrap
capacitor.
25
26
Phase
Boot
A [O]
A [I]
Enable pin to turn the IC on and off. Leave it open or ground
it when not used
A resistor from this pin to ground defines the default boot
voltage that the part will boot up in.
27
28
EN
A [I]
A[I]
VBT
PMBus Slave Address and PROG pin. A resistor to ground on
this pin points to one of the unique sixteen PMBus slave
devices which needs to be addressed on the board. The
29
SM_ADDR/PROG
D[I]
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Pin Descriptions
Pin#
Pin Name
Pin Type
Pin Description
same address also defines the specific configuration file that
will be loaded from the OTP during power-up.
Output voltage feedback pin. Connect this pin to the output
of the regulator to regulate the output voltage.
The pin provides the return path for the remote voltage
sensing. It is used as a reference for the Analog Front End
(AFE)
30
31
VOSENP
VOSENM
A [I]
A [I]
Signal ground for the internal circuitry. AGND to be
connected to PGND on the PCB.
32
33
AGND
-
Serial data line I/O. PMBus bi-directional serial data line.
Leave the pin open or ground it if not being used.
Serial Clock Line Input. PMBus serial clock input. The
interface is rated to max of 1 MHz. Leave the pin open or
ground it if not being used.
SMB Active low alert line. Leave the pin open if not being
used.
Multi-function pin. This pin can be used to select one of
eight switching frequencies, and FCCM or DEM mode by
connecting a resistor from this pin to ground.
SM_DATA
D [B]
34
35
36
SM_CLK
D [I]
D [O]
D [I]
SM_ALERT#
MODE/TON
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Absolute Maximum Ratings
5
Abs85ute Max26u6 Rat270s
Stresses higher than those mentioned in Table 3 below may result in permanent damage to the device. These
are the absolute stress ratings only and the operation of the device is not recommended or implied at these or
a7y 8t1er c87d2t287ꢀs 27 excess 8f t18se 02ve7 27 t1e rec866e7ded 89erat270 rat270s 27 Tab5e 5. Exposure of
values over and above the recommended ratings for extended periods may adversely affect the operation and
reliability of the device.
Table 3
Absolute Maximum Ratings
Values
Note/ Test
Conditions
Description
Symbol
Unit
Min
-0.3
-0.3
-0.3
Typ
Max
25
Power Input voltage
LDO Input voltage
Enable voltage
VPVIN
VIN
-
-
-
V
V
V
Note 1, PVIN Pin
Note 1, VIN Pin
EN Pin
25
VEN
25
-5 V for 5 ns, -0.3
V dc
34 V for 1 ns,
25 V dc
PVIN-PHASE voltage
VIN-PHASE voltage
VPVIN -VPHASE
VVIN-VPHASE
VPVIN -VSW
-
-
-
V
V
V
PVIN-PHASE pin
VIN-PHASE pin
PVIN- SW Pin
-5 V for 5 ns, -0.3
V dc
34 V for 1 ns,
25 V dc
PVIN-Switch Node
voltage
-5 V for 5 ns, -0.3
V dc
34 V for 1 ns,
25 V dc
Internal Driver voltage
Gate Low Pin voltage
VDRV
-0.3
-0.3
-
-
6
6
V
V
Note 1, VCC/VDRV Pin
GateL Pin
VGATEL
-0.3 V for 5 ns, -
0.3 V dc
VBOOT
VBOOT - VPHASE
VSW
-
-
-
-
-
-
-
29 V dc
V
V
V
V
V
V
V
BOOT Pin
BOOT – PHASE Pin
Switch Node Pin
Phase Pin
BOOT voltage
7 V for 5 ns,
6 V dc
-0.3
-5 V for 5 ns, -0.3
V dc
34 V for 1 ns,
25 V dc
Switch Node voltage
Phase Node voltage
Address/PROG voltage
-5 V for 5 ns, -0.3
V dc
34 V for 1 ns,
25 V dc
VPHASE
Note 1,
SM_ADDR/PROG Pin
VSM_ADDR/PROG
VVOSENP
-0.3
3.6
3.6
0.3
Output Positive Sense
voltage
-1.5 V for 5 ns, -
0.3 V dc
Note 1, VOSENP Pin
Note 1, VOSENM Pin
Output Negative Sense
voltage w.r.t AGND
VVOSENM
-0.3
Voltage Regulator Power
Good
VPGOOD
VILIM
-0.3
-0.3
-0.3
-
-
-
3.6
3.6
3.6
V
V
V
Note 1, PGOOD Pin
Note 1, ILIM Pin
ILIM Voltage
Note 1, MODE/TON
Pin
MODE/TON voltage
VMODE/TON
Note 1, VBT voltage
pin
VBT voltage
VVBT
-0.3
-
-
3.6
V
V
Power GND w.r.t Analog
GND voltage
-1.5 V for 5 ns, -
0.3 V dc
1.5 V for 5 ns,
0.3 V dc
VPGND- VAGND
PGND – AGND Pin
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Absolute Maximum Ratings
Values
Note/ Test
Conditions
Description
SM CLK voltage
Symbol
Unit
Min
-0.3
-0.3
-0.3
-40
Typ
Max
3.6
VSM_CLK
VSM_DAT
VSM_ALERT#
TJmax
-
-
-
-
-
V
V
SM_CLK Pin
SM Data voltage
3.6
SM_DAT Pin
SM Alert voltage
3.6
V
SM_ALERT# Pin
Juntion Temperature
Storage Temperature
150
150
°C
°C
-
-
TSTORAGE
-55
Note:
1. PGND and AGND pins are connected together.
Attention: Stresses beyond these listed under ꢀAbsolute Maximum Ratingsꢁ may cause permanent damage
to the device. These are stress ratings only and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications are not
implied.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Thermal Characteristics
6
T1er6a5 C1aracter2st2cs
Table 4
Thermal Characteristics
Description
Symbol Values
Test Conditions
Note 2
Junction to Ambient Thermal Resistance
Junction to PCB Thermal Resistance
Junction to Case Top Termal Resistance
θJA
θJC-PCB
θJC
19 ℃/W
1.1 ℃/W
24 ℃/W
Note 3
Note:
2. Thermal resistance is measured with components mounted on a standard EVAL_TDA38740_1.2Vout demo
board in free air
3. Thermal resistance is based on the board temperature near pin 22
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Electrical Specifications
7
E5ectr2ca5 Spec2f2cat287s
Table 5
Recommended Operating Conditions for Reliable Operation
Description
Min
Max
17
17
5.5
5.12
40
Unit
Note
PVin Voltage Range with External Vcc
PVin Voltage Range with Internal LDO
Vcc Supply Voltage Range
Output Voltage Range
Continuous Output Current Range for
TDA38740
3
V
V
V
V
A
Note 4, Note 5
4.5
4.5
0.25
Note 5 , Note 6 & Note 10
Note 4 , Note 7
Note 8
Note 9
Continuous Output Current Range for
TDA38725
25
A
Note 9
400
-40
2000
125
kHz
℃
Switching Frequency (excluding 1600 kHz)
Operating Junction Temperature
Note 10
Note:
4. VCC/VDRV pin is connected to an external bias voltage when Pvin is less than 4.5 V
5. A common practice is to have 20% margin on the maximum SW node voltage in the design. For applications
requiring PVin equal to or above 14 V, a small resistor in series with the Boot pin should be used to ensure the
maximum SW node spike voltage does not exceed absolute maximum specs. Alternatively, a snubber can be
used at SW node to reduce the SW node spike.
6. PVin with internal LDO is used. For single-rail applications with the internal LDO and PVin = 4.5 V-5.4 V, the internal
LDO may enter dropout mode. AOCP limits can be reduced due to the lower VCC voltage.
7. The TDA38740/725 is designed to function with VCC down to 4.5 V. However, electrical specifications such as
AOCP limits may be degraded.
8. The maximum output voltage is limited by the minimum off-time. For output voltages above 2.56 V an external
feedback resistor divider is needed.
9. Refer to Section 15.1 for maximum output current rating at different ambient temperature and OCP threshold
tolerance
10. The maximum LDO output current must be limited within 50 mA for operations requiring the full operating
temperature range of -40 °C ꢀ TJ ꢀ 125 °C. Thermal De-rating may be needed at an elevated ambient
temperature to ensure the junction temperature remains within the recommended operating range.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Electrical Specifications
7.1
E5ectr2ca5 C1aracter2st2cs
Unless otherwise specified, these specifications apply over, 4.5 V ꢁ V27 = PV27 ꢁ ꢂꢃ V, in 0 °C < TJ < 125 °C.
Typical values are specified at Ta = 25 °C.
Table 6
Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power Stage
VBoot – Vsw= 5.0 V, Io =
35 A, Tj =25 °C
Top Switch
Rds(on)_Top
Rds(on)_Bot
-
-
2.9
-
-
6Ω
Vcc = 5.0, Io= 35 A, Tj
=25 °C
Bottom Switch
1.00
Bootstrap Diode
Forward Voltage
I(Boot) = 25 mA
-
-
-
780
950
175
175
mV
µA
SW = 0 V, EN = 0 V
-
-
SW Leakage Current
ISW
SW = 0 V, EN = high,
No Switching
SW Node rising edge,
40 A , Internal LDO,
Tj=25 °C, Note 11
-
-
10
10
-
-
Dead Band Time
Tdb
ns
SW Node falling edge,
40 A , Internal LDO,
Tj=25 °C, Note 11
Supply Voltage
PVin, Vin and External VCC
PVin range (using
external VCC = 5V)
-
3-17
-
V
Fsw = 600 kHz
-
-
4.5 -17
4.5 –17
5
-
-
V
V
V
Vin Range (using
internal LDO)
Fsw = 2000 kHz
External VCC
4.5
5.5
Supply Current
Iin
PVin Supply Current
(standby)(External
Vcc)
EN = Low, No Switching,
Note 14
Iin (Standby)
-
-
-
-
2
-
-
-
-
PVin Supply Current
(dynamic)(External
Vcc)
EN = High, Fs = 800kHz,
Vin=PVin=12 V,
Vout =1.1 V, Note 14
Iin (Dyn)
15
12
48
mA
PVin Supply Current
(standby)(Internal
Vcc)
EN = Low, No Switching,
Note 14
Iin (Standby)
PVin Supply Current
(dynamic)(Internal
Vcc)
EN = High, Fs = 800kHz,
Vin=PVin=12 V,
Vout =1.1 V, Note 14
Iin (Dyn)
Remote Voltage
Sense Inputs
VOSENP, VOSENM
VOSENP = 3.6 V
-
-85
-
-
-
230
µA
µA
µA
VOSENP Input Current
Final Datasheet
VOSENP = -0.3 V
VOSENM = 0.3 V
-
-
-155
13 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOSENM Input
Current
VOSENM = -0.3 V
-200
-
-
µA
Differential Input
Voltage Range
-
-
-
2.56
V
VOSENM Input CM
Voltage
±300
-
mV
MODE/TON
Output Current
VBT/ILIM/SM_ADDR
Output Current
-
-
104
15
-
-
µA
µA
Open-Drain
Outputs-20mA
Drive
SM_CLK, SM_DAT, SM_ALERT#
Output Low Voltage
On Resistance
I = 20 mA
I = 20 mA
0 – 3.6 V
-
-
-
7
-
0.26
V
Ω
-
Tri-State Leakage
On-Time Timer
-5
5
µA
Frequency Range
(programmable)
Excluding 1600 kHz
and in steps of 200 kHz
400
--
2000
KHz
ns
Tj=25C, PVin=12 V,
Vo=0 V, Note 11
Minimum On-Time
Minimum Off-Time
-
-
25
-
-
Tj=25C, VFB=0 V,
Toff(Min)
Note 11
150
ns
System Set Point Accuracy
ꢄ.ꢅꢆ V ꢁ V8ut ꢁ ꢄ.445 V
0.45 V ꢁ V8ut ꢁ ꢄ.995 V
ꢂ.ꢄ V ꢁ V8ut ꢁ 2.52 V
-
-
-
±10
±8
-
-
-
mV
mV
%
-40 °C ꢁ TJ ꢁ ꢂꢅꢆ°C
Typ = 3σ, Note 11 & 12
±1
VCC LDO Output
Vcc
5.5 V ꢁ PVin ꢁ 17 V,
Vcc Output Voltage
Vcc
4.7
-
5.0
5.3
-
V
when Icc =20 mA,
Cload = 2.2 uF, Tj=25C
PVin = 4.5 V, Icc=20 mA,
Cload=2.2uF, Tj=25C
VCC Dropout
Vcc_drop
650
mV
Under Voltage
Lockout
Vcc_Good Start
Threshold
Vcc Rising Trip Level
3.8
3.6
4.0
4.2
4.0
VCC_UVLO_Start
V
V
Vcc_Good Stop
Threshold
VCC_UVLO_Stop Vcc Falling Trip Level
Enable_UVLO_Start Ramping up
3.8
Enable-Start-
Threshold
0.61
0.51
0.65
0.55
0.69
0.59
Enable-Stop-
Threshold
Enable_UVLO_Stop Ramping down
Final Datasheet
14 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
BOOT_UVLO_Risin Boot-Phase Ramping
up, Note 11
Boot Rising Threshold
3.7
3.85
4.0
g
V
Boot Falling
Threshold
BOOT_UVLO_Fallin Boot-Phase Ramping
3.5
3.65
3.8
g
down, Note 11
Over Current Limit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
15
20
25
30
40
50
60
10
15
20
25
25
25
25
25
TDA38740 Current
Limit Threshold
(Valley Current)
Ioc
Tj = 25 °C, Vcc =5.0 V,
A
TDA38725 Current
Limit Threshold
(Valley Current)
Ioc
Tj = 25 °C, Vcc =5.0 V,
See Note 11
A
Current Limit
Threshold Accuracy
±20
%
Over Voltage
Protection
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
1.0
1.2
1.35
1.5
1.8
2.2
2.85
1.6
2.0
2.4
2.7
3.0
3.6
4.4
5.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
In VOUT_SCALE_LOOP
1:1 mode,
8 Discrete Options
V
Fixed OVP Threshold
(Programmable)
OVP_Vth
In VOUT_SCALE_LOOP
1:2 mode,
8 Discrete Options.
Note 11 & 13
V
Output Fixed OVP
Threshold Accuracy
See note 11
±5
-
%
Relative to Vout in steps
of 50 mV in
50
400
mV
Final Datasheet
15 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOUT_SCALE_LOOP 1:1
mode
Relative OVP
Threshold
(programmable)
Relative to Vout in steps
of 100 mV
VOUT_SCALE_LOOP 1:2
100
-
800
mV
mode
VOUT_SCALE_LOOP 1:1
-
-
±100
±200
-
-
mV
mV
Output Relative OVP
Threshold Accuracy
VOUT_SCALE_LOOP 1:2,
Note 13 & 14
Under Voltage
Protection
UVP Trip Threshold
UVP_Vth
Relative to Vout in steps
of 50 mV in
VOUT_SCALE_LOOP 1:1
mode
50
-
-
400
800
mV
mV
Relative to Vout in steps
of 100 mV in
VOUT_SCALE_LOOP 1:2
mode
100
VOUT_SCALE_LOOP 1:1
-
-
±100
±200
-
-
mV
mV
Output Relative UVP
Threshold Accuracy
VOUT_SCALE_LOOP 1:2,
Note 13 & 14
IMON Reporting
Accuracy
Vin = 12 V, Vout = 1.2 V,
Iout = 40 A, Note 11
IMON Accuracy
Imon
-
±6
-
%
Power Good
Pgood
mA
µA
Pgood Sink Current
IPG
VPG = 0.5 V, Rpull-up =
500 Ω to 3.3 V
-
5
-
6
5
Pgood Open Drain
Leakage Current
VPG = 3.6 V
-5
Pgood Low Voltage
Pgood Low Voltage
VPG_L
VPG_H
Vin = Vcc = 5 V, I = 20 mA
-
-
-
-
0.1
0.7
V
V
Vin = Vcc = 0 V, Rpull-up
= 4.7 4Ω t8 ꢇ.ꢇ V, Note
11
Thermal Shutdown
Thermal Shutdown
Hysteresis
Note 11
Note 11
-
-
-
-
-
-
140
20
-
-
-
-
-
-
°C
PMBus Reporting
kHz
kHz
kHz
Normal
Fast
100
400
Bus Speed
High-Speed
1000
0.625,
0.977,
1.953,
Output Voltage
Resolution
mV
See Note 14 & 15
16 of 66
-
-
Final Datasheet
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
3.906
Output Voltage Filter
Rate
kHz
kHz
V
-
-
-
-
8
379
-
-
Output Voltage Update
Rate
-
VOUT_SCALE_LOOP=1:
1
2.56
5.12
Highest Reported Vout
VOUT_SCALE_LOOP=1:
2
V
-
-40 ℃ - 125 ℃ (Tj),
4.5 V < Vcc < 5.5 V,
%
%
-2
-1
-
-
2
1
ꢄ.ꢅꢆ ꢁ V8ut ꢁ ꢄ.ꢆ;
VOUT_SCALE_LOOP in
1:1 mode
Vout Reporting Accuracy
-40 ℃ - 125 ℃ (Tj),
4.5 V < Vcc < 5.5 V,
ꢄ.ꢆ<V8ut ꢁ ꢅ.ꢆꢅ;
VOUT_SCALE_LOOP in
1:1 mode
A
-
-
-
0.0625
8
-
-
-
Iout Resolution
Iout Filter Rate
Iout Update Rate
kHz
kHz
379
Iout Digital Monitoring
Range
A
-
-
64
0 ℃-125 ℃,
4.5 V<Vcc<5.5 V
ꢄ A ꢁ I8ut ꢁ ꢈꢄ A
%
-
±6
-
Iout Accuracy (PMBus)
ꢄ.ꢅꢆ V ꢁ V8ut ꢁ ꢅ.ꢆꢅ V
-
-
1
4
-
-
℃
Temperature Resolution
Temperature Filter Rate
kHz
Temperature Update
Rate
-
-40
-
189
-
-
125
-
kHz
℃
Temperature Monitoring
Range
℃
Temperature Reporting
Accuracy
Note 11
±1
PMBus Interface
Timing Specifications
SM_DAT, SM_CLK
0.997
0.839
0.996
-
-
-
1.208
1.057
1.201
V
V
V
Data Rising Threshold
Data Falling Threshold
Clock Rising Threshold
Clock Falling
Threshold
0.836
1.057
V
Final Datasheet
17 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Electrical Specifications
Parameter
Data pulldown
resistance
Symbol
Conditions
Min
Typ
Max
Unit
5
-
13
Ω
SMALERT# pulldown
resistance
5
-
20
Ω
-1
-
-
-
1
4
µA
pF
Input Leakage
See Note 11
Pin Capacitance
Note: .
11. Guaranteed by design and not tested in production
12. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in
production
13. FOVP, ROVP and RUVP threshold accuracies for VOUT_SCALE_LOOP 1:2 are based on the use of an output
divider as specified in section 13.3
14. Guaranteed by Bench Characterization at Room Temperature and not tested in production
15. Actual output voltage resolution is limited by internal DAC
Final Datasheet
18 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Pin Strap Resistors Application Information
8
P27 Strap Res2st8rs App52cat287 I7f8r6at287
The TDA38740/725 devices allow pinstrapping functionality to boot up the part with parameters set by resistor
from pin to ground. The pin functionality can be enabled by writ270 ꢉꢄꢀ t8 t1e re02sters
ilim_docp_override_pin(0x5E[0]),
vboot_override_pin(0x5E[3]),
ilim_aocp_override_pin(0x5E[1]),
ton_override_pin(0x5E[4]),
lcf_zero_override_pin(0x5E[2]),
fccm_override_pin(0x5E[5]),
fovp_override_pin(0x5E[6]), rovp_override_pin(0x5E[7]). The pinstrapping functionality is disabled on
TDA38740/725-0000 parts and these parameters are set by PMBus commands. The TDA38740/725-0000 parts have
VOUT_COMMAND set to 0V and there will not be any output until the output is set to desired value. The
pinstrapping functionality is enabled on TDA38740/725-0020 parts. Refer to Section 1 for custom part number
information for Pin configurable and Register configurable parts.
The tables and descriptions below detail different parameters that can be set using pin strap resistor.
Table 7
MODE/TON Table
Bin
0
MODE/TON ꢆ4Ωꢅ
SHORT
2.49
Freq (kHz)
600
MODE
1
2
1000
1400
2000
1200
1400
1800
2000
400
FCCM
3.24
3
4.02
4
4.87
5
5.76
6
6.81
7
7.87
DEM
8
9.09
9
10.5
600
10
11
12
13
14
15
12.1
800
14
1000
400
15.8
17.8
1800
1200
800
FCCM
20
FLOAT
When operating in the pin strap resistor mode the switching frequency and the mode can be set by connecting a
resistor from MODE/TON pin to GND per table above. Switching frequency can be selected from 400kHz to 2000kHz
in steps of 200kHz except the 1600kHz. Mode can be selected between Forced Continous Conduction Mode (FCCM)
and Diode Emulation Mode (DEM).
Final Datasheet
19 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Pin Strap Resistors Application Information
Table 8
TDA38740/725 Boot Up Voltage and OVP Limits Table for VOUT_SCALE_LOOP 1:1.
VBT ꢆ4Ωꢅ
BOOT-Up Voltage (V)
Relative OVP/UVP (mV)
Fixed OVP (V)
FLOAT
150
127
105
88.7
75
61.9
51.1
43.2
36.5
30.1
21
2.5
1.8
1.65
1.5
1.35
1.25
1.2
1.1
1.05
1
0.90
0.8
0.7
0.6
0.5
0.4
300
300
300
300
250
250
200
200
200
200
200
200
150
150
150
150
2.85
2.2
2.2
2.2
1.8
1.8
1.5
1.35
1.35
1.35
1.2
1.2
1.2
1
14
9.53
5.62
SHORT
1
0.8
Table 9
TDA38740/725 Boot Up Voltage and OVP Limits Table for VOUT_SCALE_LOOP 1:2
VBT ꢆ4Ωꢅ
BOOT-Up Voltage (V)
Relative OVP/UVP (mV)
Fixed OVP (V)
FLOAT
150
127
105
88.7
75
61.9
51.1
43.2
36.5
30.1
21
5.0
3.6
3.3
3.0
2.7
2.5
2.4
2.2
2.1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
300
300
300
300
300
300
300
300
300
300
300
300
300
200
200
200
5.7
4.4
4.4
3.6
3.6
3.0
3.0
2.7
2.7
2.7
2.4
2.4
2.0
1.6
1.6
1.6
14
9.53
5.62
SHORT
When operating in the pin strap resistor mode, the output voltage can be selected by connecting a resistor from
the VBT pin to GND per the table above.
When setting the output voltage using VOUT_COMMAND, the VOUT_SCALE_LOOP 1:1 should be used for
obtaining outputs in the range of 0.25 V to 2.56 V. For obtaining output voltages between 2.56 V to 5.12 V, the
VOUT_SCALE_LOOP 1:2 should be used. When operating in VOUT_SCALE_LOOP 1:1 mode the full output voltage
should be fed back to the VOSENP pin as shown in Figure 3. When operating in VOUT_SCALE_LOOP 1:2, half of
the output voltage is fed back to the VOSENP Pin by using a resistor divider as shown in Figure 4. The VBT pin can
be used to set the output voltages in the range of 0.4 V to 2.5 V in VOUT_SCALE_LOOP 1:1 and from 0.8 V to 5 V in
VOUT_SCALE_LOOP 1:2.
Final Datasheet
20 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Pin Strap Resistors Application Information
Table 10 TDA38740 OCP and Internal Phase margin Zero selection
RILIMꢆ4Ωꢅ
Typical OCP(A)
Internal Loop-Compensation-
Filter-Zero Register (LCF)
Default LCF zero capacitor
value (pF), Note 16
SHORT
3.32
6.98
11
15
60
20
10
15
20
25
30
40
50
25
60
40
50
10
30
LCF 0
LCF 4
LCF 2
LCF 0
LCF 1
LCF 1
LCF 2
LCF 2
LCF 3
LCF 4
LCF 1
LCF 3
LCF 2
LCF 3
LCF 1
LCF 3
1
8
4
1
2
2
4
4
6
8
2
6
4
6
2
6
15.4
20.8
26.1
31.6
43.2
51.1
64.9
78.7
95.3
113
133
FLOAT
Table 11 TDA38725 OCP and Internal Phase margin Zero selection
RILIMꢆ4Ωꢅ
Typical OCP(A)
Internal Loop-Compensation-
Filter-Zero Register (LCF)
Default LCF zero capacitor
value (pF), Note 16
SHORT
3.32
6.98
11
15
15
20
10
15
20
25
10
15
20
25
10
15
20
10
25
LCF 0
LCF 4
LCF 2
LCF 0
LCF 1
LCF 1
LCF 2
LCF 2
LCF 3
LCF 4
LCF 1
LCF 3
LCF 2
LCF 3
LCF 1
LCF 3
1
8
4
1
2
2
4
4
6
8
2
6
4
6
2
6
15.4
20.8
26.1
31.6
43.2
51.1
64.9
78.7
95.3
113
133
FLOAT
Final Datasheet
21 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Pin Strap Resistors Application Information
When operating in the pin strap resistor mode, the OCP limit can be selected by connecting a resistor from the
ILIM pin to GND per the table above. The Internal Loop-compensation-filter zero can also be set by configuration
register 0x64[14:12] through PMBus.
Table 12 SM_ADDR/PROG Pin with the consecutive images starting from Config 0 at location 0
Resistor to GND
PROG pin
SM_ADDR pin : Offset from the Programmability Access
(kΩ)
base Address
for Multi-image config file
SHORT
5.62
9.53
14
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
CONFIG7
CONFIG8
CONFIG9
CONFIG10
CONFIG11
CONFIG12
CONFIG13
CONFIG14
CONFIG15
0
1
2
3
21
4
30.1
36.5
43.2
51.1
61.9
75
5
6
Please refer to section 13.2
for single image and multi-
image programming details
7
8
9
10
11
12
13
14
15
88.7
105
127
150
FLOAT
A resistor to ground on this pin sets both a fixed I2C slave address offset and selects a configuration from the 16
possible config files in the OTP during power-up. As shown in Table above, the SM_ADDR pin selects an offset
based on the resistor connected to the SM_ADDR/PROG pin. The PROG functionality is used to select one of the 16
images to load from the OTP. The pin programming limits the offset adjust capability via the pin to a maximum of
4 as per the programming capability available to the customer. For any application which needs more than 5
images or greater than 4h offsets to base address, please contact Infineon. For more information please refer to
Section 13.2.
Note:
16. The default LCF value can be changed using Registers 0x64[14:12], 0x62[2:0], 0x62[6:4], 0x62[10:8], 0x62[14:12]
for LCF 0, LCF 1, LCF 2, LCF 3, LCF 4 respectively
Final Datasheet
22 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Typical Efficiency and Power Loss Curves
9
Typ2ca5 Eff2c2e7cy a7d P8wer L8ss Curves
9.1
PV27 = V27 = ꢂꢃ V, V8ut = ꢂ.ꢃV, Fsw = ꢇꢁꢁ4Hz
The test for efficiency was done at 0 LFM and the driver losses are included in the efficiency numbers. Solid lines
indicate efficiency and dashed lines show power loss at 600 kHz.
Table 13 Inductors for PVin=Vin=12 V, Fs = 600 kHz
Vout (V)
1.2
Lout (nH)
150
P/N
Size (mm)
10 x 6.4 x 12
10 x 7 x 10
DCR (m)
0.125
L101247A-100L
L101158A-R47MHF
470
0.81
3.3
Efficiency and Power Loss vs Iout
98
96
94
92
90
88
86
84
82
80
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
Iout (A)
1.2V Efficiency 600KHz Int LDO (%)
1.2V Power Loss 600KHz Int LDO (W)
Figure 5
Typical efficiency and power loss curves, PVin = Vin = 12 V, Vout = 1.2 V, Fsw = 600 kHz
Final Datasheet
23 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Typical Efficiency and Power Loss Curves
Efficiency and Power Loss wrt Iout
98
96
94
92
90
88
86
84
82
80
9
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
Iout (A)
3.3V Efficiency 600KHz Int LDO (%)
3.3V Power Loss 600KHz Int LDO (W)
Figure 6
Typical efficiency and power loss curves, PVin = Vin = 12 V, Vout = 3.3 V, Fsw = 600 kHz
9.2
PV27 = V27 = ꢂꢃ V, Fsw = ꢈꢁꢁ 4Hz
The test for efficiency was done at 0 LFM and the driver losses are included in the efficiency numbers. Solid line
indicate Efficiency and dashed lines are showing power loss at 800 kHz.
Table 14 Inductors for PVin=Vin=12 V, Fsw = 800 kHz
Vout (V)
1.2
Lout (nH)
150
P/N
Size (mm)
10 x 6.4 x 12
10 x 7 x 10
DCR (m)
0.125
L101247A-150L
L101158A-R47MHF
3.3
470
0.81
Final Datasheet
24 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Typical Efficiency and Power Loss Curves
Efficiency and Power Loss vs Iout
98
96
94
92
90
88
86
84
82
80
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
Iout (A)
1.2V Efficiency 800KHz Int LDO (%)
1.2V Power Loss 800KHz Int LDO (W)
Figure 7
Typical efficiency and power loss curves, PVin = Vin = 12 V, Vout = 1.2 V, Fsw = 800 kHz
Efficiency and Power Loss wrt Iout
98
9
8
7
6
5
4
3
2
1
0
96
94
92
90
88
86
84
82
80
0
5
10
15
20
25
30
35
40
Iout (A)
3.3V Efficiency 800KHz Int LDO (%)
3.3V Power Loss 800KHz Int LDO (W)
Figure 8
Typical efficiency and power loss curves, PVin = Vin = 12 V, Vout = 3.3 V, Fsw = 800 kHz
9.3
PV27 = V27 = ꢂꢃ V, Fsw = ꢂꢁꢁꢁ 4Hz
The test for efficiency was done at 0 LFM and the driver losses are included in the efficiency numbers. Solid lines
indicate efficiency and dashed lines show power loss at 1000 kHz.
Table 15 Inductors for PVin=Vin=12 V, Fsw = 1000 kHz
Vout (V)
Lout (nH)
P/N
Size (mm)
DCR (m)
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Typical Efficiency and Power Loss Curves
1.2
3.3
150
470
L101247A-150L
0.125
0.81
10 x 6.4 x 12
10 x 7 x 10
L101158A-R47MHF
Efficiency and Power Loss vs Iout
98
96
94
92
90
88
86
84
82
80
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
Iout (A)
1.2V Efficiency 1000KHz Int LDO (%)
1.2V Power Loss 1000KHz Int LDO (W)
Figure 9
Typical efficiency and power loss curves, PVin = Vin = 12 V, Vout =1.2 V, Fsw = 1000 kHz
Efficiency and Power Loss wrt Iout
98
9
96
94
92
90
88
86
84
82
80
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
Iout (A)
3.3V Efficiency 1000KHz Int LDO (%)
3.3V Power Loss 1000KHz Int LDO (W)
Figure 10 Typical efficiency and power loss curves, PVin = Vin = 12 V, Vout =3.3 V, Fsw = 1000 kHz
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Thermal De-rating curves
10
T1er6a5 De-rat270 curves
Measurement is done on Evaluation board DB356. The PCB is an 8-layer board with 2 oz Copper for top and
bottom layers and 2 oz Copper for the inner layers, FR4 material, size 5.25ꢊx4.1ꢊ.
Figure 11 Thermal de-rating curves, PVin = 12 V, Vout = 1.2 V, fsw = 800 kHz, VCC = Internal LDO
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Thermal De-rating curves
Figure 12 Thermal de-rating curves, PVin = 12 V, Vout= 3.3 V, fsw = 800 kHz, VCC = Internal LDO
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
RDS(on) of MOSFET Over Temperature
11
RDS(on) 8f MOSFET Over Te6perature
Synchronous FET RDS(on) Variation with Temperature
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Vcc = 5 V
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Control FET RDS(on) Variation with Temperature
5
4.5
4
3.5
3
2.5
2
1.5
1
Vcc = 5 V
0.5
0
-40
-20
0
20
40
60
80
100
120
140
Temperature(°C)
Figure 13 RDS(on) of MOSFETs over Junction Temperature
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Typical operating characteristics (-40 C ≤ T3 ≤ +ꢂꢃꢄ Cꢅ
12
Typ2ca5 8perat270 c1aracter2st2cs ꢆ-ꢀꢁ °C ≤ T3 ≤ +ꢂꢃꢄ °Cꢅ
PGOOD Rising and Falling Thresholds
Figure 14 Typical operating characteristics (set 1 of 2)
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Typical operating characteristics (-ꢀꢁ C ≤ T3 ≤ +ꢂꢃꢄ Cꢅ
FOVP Thresholds
RUVP Thresholds
ROVP Thresholds
Analog OCP Thresholds
Figure 15 Typical operating characteristics (set 2 of 2)
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
General Description
13
Ge7era5 Descr2pt287
The TDA38740/725 is an easy-to-use, fully integrated, and highly efficient dc-dc regulator optimized to convert a
12 V input supply to a voltage level required by high performance microprocessors, DDR memory, housekeeping
supplies, base stations, etc. T1e 87b8ard PWM c87tr855er a7d O9t2MOS™ FETs w2t1 27te0rated b88tstra9 d28de
make TDA38740/725 a small footprint solution, providing highly efficient power delivery. Using a fast Constant On-
Time (COT) control scheme simplifies design efforts and achieves fast control response. The device configuration
ca7 be eas25y def27ed us270 I7f27e87ꢀs XDP Designer GUI and is stored in the on-chip memory.
13.1
PMBUS Operat270 M8de
The TDA38740/725 can be used in PMBUS mode. In PMBUS mode, the output voltage is controlled by the PMBUS
VOUT_COMMAND command. The VOUT_MODE resolution can be set to 0.625 mV/lsb, 0.977 mV/lsb, 1.953 mV/lsb,
or 3.906 mV/lsb. The output DAC resolution is 1.25 mV/lsb. The resolution is user-programmable via a
configuration file.
See Table 18 for
a full list of all supported PMBUS commands. Please refer to App Note
AN_2203_PL12_2204_184108 for more details.
13.2
Mu5t2p5e T26e Pr80ra66270 Me68ry ꢆMTPꢅ
The multiple time programming memory (MTP) stores the device configuration. At power-up, MTP contents are
transferred to operating registers for access during device operation. MTP allows customization during both
design and high-volume manufacturing. MTP integrity is verified by Cyclic Redundancy Check (CRC) validation on
each power up. The controller will not start up in the event of a CRC error.
The TDA38740/725 allows up to 5 unique configurations, to configure basic device parameters such as frequency,
fault operation characteristics, and boot voltage. This represents a significant size and component saving
compared to traditional analog methods. In addition, the TDA38740/725 also allows loading of multi-image (up to
5 consecutive) configuration files and automatic selection of a unique file after power-up based on the resistor
value at the SM-ADDR/PROG pin and the pointer (0x00[13:8]). There are registers available in the CNFG section of
the register map which allow the user the capability to set the starting point for a multi-image (register
0x0000[13:8]) and number of images as part of the multi-image config file (register 0x0000[3:0]).
TDA38740/725 can be programmed successfully for an application up to 16 times for a single image config file.
This should be done during offline programming or by using Infineon programming solution. Additonally, the
TDA38740 also allows loading a maximum of 5 config files for the multi-image designs. For any application which
needs multi-image configuration, Infineon will establish custom part numbers and will program at an Infineon
production facility. After soldering parts with a 5-image multi-image, it may be programmed two more times with
a single image.
The user still has access to all the possible I2C slave addresses. The user has to use the registers to do this. This
requires the address offset capability of the SM_ADDR/PROG pin to be disabled by setting the bit 0x42[6] to 1. Thus,
the base address register 0x40[14:8] for I2C and 0x40[6:0] for PMBus will represent the effective slave address for
the device. In this case the SM_ADDR/PROG effectively becomes just the PROG pin used for selecting the correct
config file for an application. For example, for an effective 7-bit I2C address of 14h the register 0x40[14:8] should
be set to 14h. The second method for choosing the effective slave address is using the base address in register
0x40 and adding the offset selected by the SM_ADDR/PROG pin. The pin configuration limits the offset capability
available for an application, as shown in Table 12.
13.3
V85ta0e Se7se
An error voltage is generated from the difference between the target voltage, defined by the output voltage and
load line (if implemented), and the differentially sensed output voltage (remote sense). The error voltage is
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
General Description
digitized by a high-speed, high-precision ADC. An anti-alias filter provides the necessary high frequency noise
rejection.
The gain and offset of the voltage sense circuitry for each loop is factory trimmed to deliver the required accuracy.
In order to achieve tight regulation in vout_scale_loop of 1:2 where a resistor divider is used to feedback the
output voltage, connect a 31 4Ω resistor R3 in parallel to the top resistor R1 of the divider as shown in Figure 4.
This will compensate for the error caused by impedance of the Analog front end (AFE) circuit. The recommended
value for R1 and R2 is 499 Ohms and the recommended tolerance for R1, R2 and R3 is 1%.
13.4
IꢃC & PMBus I7terface
An I2C or PMBus interface is used to communicate with the TDA38740/725. This two-wire serial interface consists
of clock and data signals, and operates as fast as 1 MHz. The bus provides read & write access to the internal
registers for configuration, and for monitoring of operating parameters. The bus is also used to program on-chip
non-volatile memory (MTP) to store operating parameters.
To ensure operation with multiple devices on the bus, a base address for TDA38740/25 is programmed into the
MTP. The unique slave address for the device is a combination of the base address in the device register plus the
offset generated by the SM_ADDR/PROG pin (depending on the resistor value connected to the pin). Alternatively,
the same thing is achieved by programming the effective I2C address into the base address register and disable
the SM_ADDR/PROG pin offset functionality via bit 0x42[6] in the USER section.
To protect customer configuration and information, the I2C and PMBus interface can be configured for either
limited access or locked with a 16-bit software password. Limited access includes both write and read protection
options. In addition, there is a telemetry-only mode which only allows reads from the telemetry registers.
Refer to the PMBus Command Codes in Table 18 for more information. One can access the non-PMBus registers
(I2C register) via the MFR_REG_ACCESS(D0h) PMBus Command. Through the PMBus, it is possible to access
configuration registers and the PMBus registers in the device. It has a 7-bit register to set the base PMBus address
0x40[6:0] of the device. Setting this address to zero disables the PMBus interface. The recommended addresses
are 0x40-0x47 and 0x70-0x77. If the I2C base address, 0x40[14:8], register is set to 0, the device is forced into test
mode. Reserved addresses should be avoided: (0x00 to 0x07), 0x08, 0x0c, 0x28, 0x37, 0x61, (0x78 to 0x7F). All
registers at this address are protected by the i2c_pmb_addr_lock register 0xD4[2]. Please refer to the App note
AN_2204_PL12_2204_183614 for more information on the register map.
13.5
I7f27e87 XDP Des207er GUI
The Infineon XDP Designer GUI provides the designer with a comprehensive design environment that includes
input settings, output settings, telemetry and PMBus interface. With these tools, a designer can monitor and set
system configuration settings for fault thresholds and output behavior in real time. The XDP Designer GUI allows
real-time design monitoring of key parameters such as output current and power, input current and power,
efficiency, temperature, and faults. Figure 16 shows the GUI home screen with the available parameter windows.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
General Description
Figure 16 XDP Designer GUI home screen.
13.6
Pr80ra66270
Once a design is complete, the XDP Designer GUI produces a complete configuration file. These configurations
files can be saved and loaded. Infineon does not recommend loading a new config file and programming the
device while the device is operating to produce an output voltage. Please refer to the programming guide
AN_2204_PL12_2204_185449 for more details.
13.7
Rea5-t26e M872t8r270
The TDA38740/725 can be accessed through the use of PMBus Command codes (described in Table 18) to read
the real-time status of the power supply (dc-dc converter) including input and output voltages, input and output
currents, input and output power and temperature.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Theory of Operation
14
T1e8ry 8f Operat287
14.1
Dev2ce P8wer-O7 a7d I72t2a52zat287
TDA38740/725 is ready to communicate as soon as Vcc is above the threshold of 3.7 V. The device starts
switching once the Enable signal is pulled high. Based on whether Vcc is supplied externally or an internal LDO is
used, the recommended power-up sequences are shown in Figure 17.
Device Startup with Internal LDO
Pre-Bias
PVIN
Int. LDO
Enable
Device Startup with External Vcc (Case 1)
Device Startup with External Vcc (Case 2)
Pre-Bias
Pre-Bias
PVIN
Ext. Vcc
PVIN
Ext. Vcc
Enable
Enable
Figure 17 Device power-on sequence.
14.2
Pre-b2as start-up
The TDA38740/725 is able to start up into a pre-charged output without causing oscillations and disturbances of
the output voltage upto 0.5 V prebias level.
Prebias operation requirements are:
•
The Startup sequence should follow the sequencing shown in Figure 17
• T1e ꢋpower down analog circuit w1e7 t1e 8ut9ut 2s 78t e7ab5edꢊ feature should be disabled (set register
0x6C value to 0xF240)
For any application needs with prebias level > 0.5 V please contact Infineon.
14.3
I7ter7a5 L8w-Dr8put ꢆLDOꢅ Re0u5at8r
The TDA38740/725 has an integrated low-dropout LDO regulator to provide the bias voltage for internal circuitry.
VIN pin is the input for the LDO. When the VCC voltage rises above the VCC_UVLO_Start threshold and the EN
voltage is above the Enable_UVLO_Start threshold, the soft-start sequence starts. When using the internal LDO for
single rail operation, the VIN pin should be connected to the PVIN pin. To save power losses on the LDO, an external
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Theory of Operation
bias voltage can be used by connecting the VIN pin to the VCC/LDO pin. Figure 18 illustrates the possible
configurations of VCC/LDO and VIN pins.
PVin
Ext Vcc
PVin
4.7uF
VIN
VCC
PVin
VIN
VCC
PVin
TDA38740
PGND
2.2uF ~10uF
TDA38740
PGND
10uF
Single rail operation with the internal LDO
Use an external Vcc
Figure 18 Configuration of using the internal LDO or an external VCC.
14.4
Fast C87sta7t ON-T26e C87tr85
The TDA38740/725 features a proprietary Fast Constant On-Time (COT) Control, which can provide fast load
transient response, good output regulation and minimize design effort. Fast COT control compares the output
voltage, Vo, to a floor voltage combined with an internal ramp signal. When Vout drops below that signal, a PWM
signal is initiated to turn on the high-side FET for a fixed on-time. The floor voltage is generated from an internal
compensated error amplifier, which compares Vout with a reference voltage. Compared to traditional COT
control, Fast COT control significantly improves Vout regulation.
14.5
EN ꢆE7ab5eꢅ P27
The EN pin controls the on/off state of the TDA38740/725. When the VCC/LDO voltage rises above the
VCC_UVLO_Start threshold, the soft-start sequence starts. The EN pin voltage needs to be toggled when the VCC
voltage drops below VCC_UVLO_Stop and rises above the VCC_UVLO_Start threshold to start the soft-start
sequence.
The EN pin can be configured in four ways. Three of them are as shown in Figure 19. Configuration one is an
external logic signal. The second and third possible configurations derive the enable signal from the PVin voltage
by a resistive divider, REN1 and REN2 or tie EN to Pvin. The fourth configuration is control via PMBus register
0x204[7:0] using the PMBus lines. TDA38740/725 utilizes the PMBus ON_OFF_CONFIG command in combination
with the OPERATION command, register 0x202[7:0], to control the soft enable. Using this, a preference between
hardware or software enable may be established. More information is available in the PMBUs app note
AN_2203_PL12_2204_184108.
The EN pin should not be left floating. T1ere 2s a7 27ter7a5 9u55 d8w7 res2st8r 8f ꢂMΩ fr86 EN t8 GND 927. A pull-
down resistor in the range of tens of kilohms is recommended.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Theory of Operation
PVin
PVin
PVin
Vin
Vin
PVin
PVin
REN1
Vcc
Vcc
PVin
Vin
En
En
Vcc
TDA38740
TDA38740
En
TDA38740
REN2
ꢁ
ꢂꢃꢄ
EN = an external logic signal
EN = ꢁ
× ꢆꢇ
ꢂꢃꢄ
EN = PVin
Configuration 3
ꢈꢉ
+ꢁ
ꢂꢃꢅ
Configuration 1
Configuration 2
Figure 19 Enable Configurations
14.6
Sw2tc1270 Freque7cy a7d FCCM/DEM Operat287
The TDA38740/725 offers two operation modes: Forced Continuous Conduction (FCCM) and Diode Emulation
Mode (DEM). With FCCM, the TDA38740/725 always operates as a synchronous buck converter with a pseudo
constant switching frequency and therefore achieves small output voltage ripple. In DEM, the synchronous FET is
turned off when the inductor current is close to zero, which reduces the switching frequency and improves
efficiency at light load. At heavy load, both FCCM and DEM operate in the same way. The operation mode can be
selected by bit 0x5C [1] in the configuration register, value 1 for this bit programs the device to operate in FCCM
mode and 0 for DEM. It should be noted that the selection of the operation mode cannot be changed on the fly. To
load a new configuration, EN or VCC voltage must be cycled.
The TDA38740/725 offers eight programmable switching frequencies, fsw, from 400 kHz to 2 MHz excluding 1600
kHz, by editing the PMBus register, 0x266[15:0], using the PMBus lines. Alternatively, switching frequency and
mode can be selected using eight resistor selectable options at Ton/Mode pin. The selected Ton/mode bin is
loaded to the IC during the power up and cannot be changed on the fly. To change the switching frequency and
mode, users must cycle the EN signal or VCC voltage. To use the pin functionality, the ton_override_pin bit (0x5e
[4]) and fccm_override_pin bit (0x5e [5]) should be set to 0. Based on the selected fsw, the TDA38740/725 generates
the corresponding on-time of the Control FET for a given PVin and Vo, as shown by the formula below.
ꢇꢌ
ꢍ
ꢊ
ꢋꢉ
=
×
ꢆꢇ
ꢎ
ꢏꢐ
ꢈꢉ
Where fsw is the desired switching frequency. During operation, the TDA38740/725 monitors PVin and Vo, and can
automatically adjust the on-time to maintain the pre-selected fsw. With the increase of the load, the switching
frequency can increase to compensate for the power losses. Therefore, the TDA38740/725 has a pseudo constant
switching frequency.
Using the FREQUENCY_SWITCH PMBus command, the switching frequency may be programmed between 400
kHz and 2 MHz in steps of 200 kHz except 1600 kHz.
14.7
S8ft Start
The soft-start functionality is based on the PMBus TON_RISE command. As shown in the waveform below, when
the TON_RISE is set to 50 ms, the output voltage rises from zero to set value in 50 ms.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Theory of Operation
Figure 20 Vo=5V, Ch1=Vout, Ch3=Switching node, Ch4=Enable Signal
After the EN pin is enabled, the TON_DELAY command is executed before the TON_RISE command. Hence, the
output will not begin to rise until the specified delay is completed. In the above example, the delay is also set to
50 ms.
14.8
L8ad-527e
The TDA38740/725 offers a digital load line which can be set via configuration registers, without any need for
external components. The 58ad 527e ca7 be 9r80ra66ed fr86 ꢄ t8 ꢂꢄ 6Ω at a res85ut287 8f ꢂꢌ.ꢆꢇ µΩ using the
VOUT_DROOP command 0x250[15:0]. The range and resolution of the VOUT_DROOP may be increased by using
the bit loadline_range_sel 0x6a [6] to ꢄ t8 ꢆꢄ 6Ω at a res85ut287 8f ꢂꢄꢄ µΩ. In addition to this, the bandwidth of
the digital load line is also programmable from 30 kHz to 500 kHz in steps of 30 kHz by using 4 bits of register 0x6a
[3:0].
14.9
Output V85ta0e D2ffere7t2a5 Se7s270
The TDA38740/725 VOSENP and VOSENM pins are connected across the output capacitors near the load to provide
true differential remote voltage sensing with high common-mode rejection. Fast COT control compares the output
voltage to a floor voltage combined with an internal ramp signal. When Vout drops below that signal, a PWM signal
is initiated to turn on the high-side FET for a fixed on-time. The floor voltage is generated from an internal
compensated error amplifier, which compares the Vout with a reference voltage. As shown in Figure 21, the output
sense pins VOSENP and VOSENM are connected across the output capacitors.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Theory of Operation
Figure 21 Output voltage sensing connections
14.10
Output Curre7t Se7s270
Current sensing for both telemetry and over current protection is done by sensing the voltage across the sync FET
RDS(on). This method increases t1e c87verterꢀs eff2c2e7cy, reduces c8st by e52627at270 a curre7t se7se res2st8r a7d
minimizes any sensitivity to layout related noise issues. A novel scheme allows reconstruction of the inductor
current from the voltage sensed across the Sync FET RDS(on).
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults and Protections
15
Fau5ts a7d Pr8tect287s
15.1
Over Curre7t Pr8tect287 ꢆOCPꢅ
The TDA38740/725 has two levels of OCP protection: Analog OCP (AOCP) and Digital OCP (DOCP). The AOCP
current limit is based on valley inductor current, whereas the DOCP is based on average current information. AOCP
is a fast fault response, and should be set to a value that prevents failure of the device.
A novel scheme allows reconstruction of the inductor current from the voltage sensed across the Sync FET RDS(on).
It should be noted here that it is this reconstructed average inductor current that is digitized by the ADC and used
for output current reporting.
The over current (OC) fault protection circuit also uses the voltage sensed across the RDS(on) of the Synchronous
MOSFET; however, the protection mechanism relies on a fast comparator to compare the sensed signal to the over
current threshold and does not depend on the ADC or reported current. The current limit scheme uses an internal
temperature compensated current source that has the same temperature coefficient as the RDS(on) of the
Synchronous MOSFET. As a result, the over current trip threshold remains almost constant over temperature.
The TDA38740/725 AOCP can be accessed via three bits in the register map (aocp_thresh_sel [0:2]). The digital OCP
(DOCP) is availble via the PMBus register IOUT_OC_FAULT_LIMIT, and the response is decided by
IOUT_OC_FAULT_RESPONSE. Available responses are shutdown, retry 6 times and latch off, or retry indefinitely.
The indication of the fault is available in STATUS_IOUT register in PMBus.
AOCP shall be enabled during soft-start and normal operation including FCCM and DEM modes. When AOCP is
crossed, the low side MOSFET will continue to stay on for the remaining cycle and the following high side pulse
will be ignored to allow inductor relaxation (pulse skipping). If an AOCP condition is detected on the rising edge
of a PWM pulse, the high side will still be blocked from turning on and the pulse will be skipped.
The high side will continue to be ignored if the current remains above the AOCP threshold. A 10-count counter is
implemented to count 10 AOCP events, then a signal is sent to the digital block to perform the programmed
response when the Digital OCP is triggered from the Analog OCP. The counter is reset after 3 consecutive non-OCP
events. The count occurs at the valley of the current. Note that COT switching frequency will decrease when
skipping pulses. Figure 22 is an example AOCP response.
The TDA38740/725 also offers cycle-by-cycle AOCP response with a choice of eight selectable current limits, which
is set by the resistance at ILIM pin. The selected OCP limit bank is loaded to the IC during the power up and cannot
be changed on the fly. To change the OCP limit, users must cycle the EN signal or VCC voltage. Cycle-by-cycle OCP
response allows the TDA38740/725 to fulfill a brief high current demand, such as a high inrush current during start-
up. The output slew rate and the output capacitance will affect the AOCP during startup. At higher output voltages,
a higher output slew rate or a higher output capacitance can false trigger AOCP at startup. The TON_RISE time
should be increased or output capacitance should be reduced to avoid false triggering of AOCP.
The AOCP is activated when EN voltage is above its threshold. During AOCP events, the valley of the inductor
current is regulated around the AOCP limit. But during the first switching cycle when the AOCP is tripped, the valley
of the inductor current can drop slightly below the AOCP limit. It should be noted that AOCP events do not pull the
PGOOD signal low unless the output voltage eventually drops below the Under Voltage Protection (UVP) threshold
and triggers UVP.
The OCP limits are thermally compensated. The corresponding output dc current can be calculated as follows:
∆ꢛꢗ
ꢑꢋꢒꢓ_ꢔꢕꢖ = ꢑꢗꢘꢙ
ꢚ
ꢜ
Where: Iout_OCP = Output dc current when AOCP is tripped. ILIM = AOCP limit, which is the valley of inductor current.
ΔiL = Peak-peak inductor ripple current.
Final Datasheet
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults and Protections
To avoid the inductor saturation during AOCP events, the following criterion is recommended for the inductor
saturation current rating.
ꢑꢏꢝꢓ ꢞ ꢑꢗꢘꢙ_ꢟꢝꢠ ꢚ ∆ꢛꢗ
Where: Isat is the inductor saturation current and ILIM_max is the maximum spec of the AOCP limit.
AOCP Tripped
Current
Limit
Inductor
Current
UVP
shutdown
Pulse
skipped
HDrv
LDrv
PGood
UVP
Threshold
Vo
PGood Turn-off
Threshold
Figure 22 AOCP response timing diagram.
15.2
Output U7der V85ta0e Pr8tect287 ꢆUVPꢅ
The TDA38740/725 UVP response is a relative limit configurable from 50 mV to 400 mV in steps of 50 mV using the
register bits relative_uvp_thresh[2:0] in configuration register 0x5e. The limit is programmed by
VOUT_UV_FAULT_LIMIT PMBus command, and the response is programmed via the VOUT_UV_FAULT_RESPONSE
command. Possible responses are ignore, shutdown, and retry indefinitely.
When using the VBT pin to set the output voltage, the VOUT_COMMAND value should be same as the VBT pinstrap
setting to avoid improper UVP triggering.
When the UVP fault is triggered, a flag is raised and the part is tri-stated until the flag is cleared using the PMBus
CLEAR_FAULTS command. The part is started again by either cycling the Vcc or the EN signal to the part. The
shutdown response entails tri-stating both the MOSFETs and discharging the output either via a bleed resistor at
the output or through the body diode of the low side FET.
If the response is set to retry, a user defined timer (1 ms to 8 ms in steps of 1 ms) is started as soon as the UVP fault
is triggered and the output is tri-stated. At the end of the timer the output is checked against a fixed level of 250
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40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults and Protections
mV. If the output is below this voltage, the start-up sequence is initiated. Otherwise, the timer is reset and the
output tri-state continues (both the MOSFET's are tri-stated).
There are options for UVP protection to be lifted during voltage transitions (Vboot, Vout transition up and/or
down) using the register bits blank_uv_sel[1:0] in configuration register 0x60. The options for this register are
outlined in Table 16.
Table 16 Optional UVP blanking via register blank_uv_sel (0x60[11:10]).
sel
3
Description
blank UV faults during Vout transition up or down (including Vboot)
blank UV faults during Vout transition up (including Vboot)
blank UV faults during Vboot
2
1
0
no UV fault blanking
15.3
Over V85ta0e Pr8tect287 ꢆOVPꢅ
The OVP response is divided into two parts: Fixed OVP (FOVP) and Relative OVP (ROVP). The Fixed OVP is typically
used for start-up, all DVIDs, and when EN is low. ROVP covers all other situations during operation. Figure 23
depicts an example of when FOVP and ROVP are utilized.
When using the VBT pin to set the output voltage, the VOUT_COMMAND value should be the same as the VBT
pinstrap setting to avoid improper ROVP triggering.
The FOVP has 8 distinct levels (0.8 V, 1 V, 1.2 V, 1.35 V, 1.5 V, 1.8 V, 2.2 V, and 2.85 V in VOUT_SCALE_LOOP 1:1 and
the levels are doubled in VOUT_SCALE_LOOP 1:2). FOVP is programmable via the configuration fixed_ovp_thresh
[2:0] in configuration register 0x60. The response to an OVP event is programmed via the
VOUT_OV_FAULT_RESPONSE command. OVP can have four responses: ignore, shutdown, and retry n (max 6)
times after n (defined by PMBus) sec before latching and retry foreever. The threshold for ROVP is relative to the
programmed output voltage, and can be set from 50 mV to 400 mV in steps of 50 mV. The OVP fault can also be
blanked by using the bits [13:12] of register 0x60 in common regmap space. Please refer to Table 17 for more
details. The threshold for ROVP is relative to the programmed output voltage, and can be set from 50 mV to 400
mV in steps of 50 mV using the I2C register relative_ovp_thresh [2:0] (0x5e [14:12]). The PMBUs commands could
be over-ridden by using the relative_ovp_thresh_en (0x5e [15]) bit to over-ride the PMBUs commands.
Table 17
sel
Optional OVP blanking via blank_ov_sel(0x60[13:12])
Description
3
2
1
0
blank OV faults during DVID up or down (including Vboot)
blank OV faults during DVID up (including Vboot)
blank OV faults during Vboot
no OV fault blanking
When the output triggers an FOVP event the OVP flag is set, low side switch is turned ON and high side switch is
turned OFF. The low side switch is turned ON till the output voltage is dragged down to the set FOVP threshold.
After that the output voltage walks down to zero with its natural decay.
When the output triggers an ROVP event, the Vout set point is moved to 0 V at a controlled slew rate of 30 mV/uS
and the OVP flag is set. Next the low side switch is turned ON and the high side is turned off. This allows the output
to discharge until Vout set point reaches zero or Vout catches up with the VID set point at which point the low side
and high side switched turn ON and OFF as required to maintain the output at the VID set point. How fast the
output voltage discharges during this event is determined by the output voltage, output capacitance and output
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40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults and Protections
inductor. This determines if the output voltage is discharged to zero by the end of the controlled Vout ramp down.
At the end of the ramp, if the output is not already at zero, the output voltage will discharge to zero with its natural
decay.
FOVP
ROVP
VID
VID LEVEL
ROVP(Programmable)
FOVP (Programmable)
RUVP (Programmable)
Time
Figure 23 OVP example diagram. Note the situations in which FOVP takes over from ROVP.
15.4
Over Te6perature Pr8tect287 ꢆOTPꢅ
The temperature is measured by a thermal sensor in the controller die. Temperature protection is programmable
via the OT_FAULT_LIMIT, OT_WARN_LIMIT, and OT_FAULT_RESPONSE PMBus registers. The TDA38740/725
supports three responses: ignore, shutdown, and retry idefinitely. The fault is non-latching.
An OTP event is triggered when the device temperature reaches the OT_FAULT_LIMIT. The switching output is tri-
stated and the output discharges, while staying biased with the internal LDO on. With the output off, the device
cools until reaching the OTP_WARN_LIMIT, and if set to retry, the device will hiccup with the potential for pre-
biased startup.
15.5
B88t U7der V85ta0e L8c48ut ꢆUVLOꢅ
The voltage from the BOOT pin to PHASE pin is monitored on the TDA38740/725. If the Boot UVLO lower threshold
violation is detected within the PWM cycle, the event is counted and a fault is asserted after 10 violations. After 3
consecutive cycles without a BOOT UVLO event (above the lower threshold during the PWM cycle), the counter
resets. To clear the fault Vcc or EN has to be cycled. The Boot UVLO fault is in the fail_code_sticky register.
15.6
M2726u6 O7 - T26e a7d M2726u6 Off - T26e
The minimum on-time refers to the shortest time for the Control MOSFET to be reliably turned on. The minimum
off-time refers to the minimum time duration in which the Synchronous FET stays on before a new PWM pulse is
generated. The minimum off-time is needed for TDA38740/725 to charge the bootstrap capacitor, and to sense the
current of the Synchronous MOSFET for OCP.
For applications requiring a small duty cycle, it is important that the selected switching frequency results in an on-
time larger than the maximum spec of the minimum on-time in the Section 7. Otherwise, the resulting switching
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40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults and Protections
frequency may be lower than the desired target. The following formula can be used to check for the minimum on-
time requirement.
ꢇꢌ
> max ꢢꢣꢤꢥ ꢦꢎ ꢊꢋꢉ ꢨiꢩ
ꢧ
ꢪ
ꢡꢎ × ꢇ
ꢏꢐ
ꢈꢉ
Where fsw is the desired switching frequency. k is the variation of the switching frequency. As a rule of thumb,
select k = 1.25 to ensure design margin.
For applications requiring a high duty cycle, it is important to make sure a proper switching frequency is selected
so that the resulting off-time is longer than the maximum spec of the minimum off-time in the Section 7 which can
be calculated as shown below.
ꢇ
− ꢇꢌ
ꢈꢉ
> max ꢢꢣꢤꢥ ꢦꢎ ꢊꢋꢫꢫ ꢨiꢩ
ꢧ
ꢪ
ꢡꢎꢏꢐ × ꢇ
ꢈꢉ
Where fsw is the desired switching frequency. k is the variation of the switching frequency. As a rule of thumb,
select k = 1.25 to ensure the design margin.
The resulting maximum duty cycle is therefore determined by the selected on-time and minimum off-time.
ꢊ
ꢋꢉ
ꢬꢟꢝꢠ
=
ꢊ
ꢋꢉ
ꢚ ꢊꢋꢫꢫꢧꢨiꢩꢪ
15.7
H201-S2de S18rt ꢆHSSꢅ Detect287
The TDA38740/725 offers high-side FET short detection. The phase pin is monitored when the low-side FET is
active. HSS monitoring happens both at start-up and during normal operation. In an HSS event, if the HSS
threshold is reached, the PGOOD pin is de-asserted. Once the HSS threshold is reached, the low-side FET is turned
on and the switching stops. There is no current reporting during this time. The fault is sticky and only clears when
either the VCC or EN signal is cycled.
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults Communication
16
Fau5ts C866u72cat287
TDA38740/725 supports the the following FAULTs OCP, OVP, UVP and OTP via telemetry.
16.1
PMBUS S5ave Address270
The TDA38740/725 supports PMBus through the use of exclusive addressing. By using a 7-bit address, the user
can configure the device to any one of 127 different PMBus addresses. Once the address of the TDA38740/725 is
set, it can be locked to protect it from being overwritten. Optionally, a resistor can be tied to the SM_ADDR/PROG
pin to generate an offset as shown in Figure 24 .
Setting a base 7-bit PMBus address of 40h with a resistor offset of +15 sets the 7-bit PMBus address to 4Fh.
SM_ADDR/PROG
R1
Figure 24 SM-ADDR/PROG Pin Components
16.2
Rea5-T26e Te5e6etry
TDA38740/725 provides real-time accurate measurement of input voltage, output voltage, output current,
temperature, output power, and input power over the PMBus interface. Output voltage is calculated based upon
the output voltage setting and the result is reported through the PMBus.
16.3
SMBUS/PMBUS PROTOCOLS
To access TDA38740 and TDA38725 configuration and monitoring registers, 4 different protocols are required:
•
•
•
•
the SMBus Read/Write Byte/Word protocol with/without PEC (for status and monitoring)
the SMBus Send Byte protocol with/without PEC (for CLEAR_FAULTS only)
the SMBus Block Read protocol for accessing Model and Revision information
the SMBus Process call (for accessing Configuration Registers)
In addition, the TDA38740/725 supports:
•
•
•
Alert Response Address (ARA)
Bus timeout
Group Command for writing to many VRs with one command
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40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults Communication
S: Start Condition
8
1
S
7
Slave
Address
1
1
8
1
8
1
1
1
P
A: Acknowledge (0')
N: Not Acknowledge (1')
Sr: Repeated Start Condition
P: Stop Condition
Command
Code
A*
BYTE
A
A
Data Byte
A
PEC*
W
1
S
1
R: Read (1')
7
Slave
Address
1
8
8
1
Command
Code
Data Byte
Low
W: Write (0')
WORD
A
A
A
W
…
PEC: Packet Error Checking
*: Present if PEC is enabled
: Master to Slave
1
8
1
1
P
8
Data Byte
High
A*
PEC*
A
: Slave to Master
Figure 25 SMBus Write Byte/Word
1
1
P
1
S
1
1
8
1
1
7
Slave
Address
1
1
8
1
7
Slave
Address
8
Command
Code
Data Byte
A*
A
A
R
A
PEC*
N
Sr
BYTE
W
1
S
7
Slave
Address
1
1
8
1
1
7
Slave
Address
1
R
1
8
1
Command
Code
Data Byte
Low
A
A
Sr
A
A
WORD
W
…
1
1
8
1
8
Data Byte
High
A*
PEC*
N
P
Figure 26 SMBus Read Byte/Word
1
S
7
Slave
Address
1
1
8
1
8
1
1
P
Command
Code
PEC*
A
A*
A
W
Figure 27 SMBus Send Byte
1
S
7
Slave
Address
1
1
8
1
Command
Code
W
A
A
…
1
7
Slave
Address
1
R
1
8
8
8
1
1
1
1
Byte Count =1
Data Byte
A*
A
A
PEC*
N
P
Sr
Figure 28 SMBus Block Read with Byte Count=1
Figure 29 MFR specific command to Write an MFR Register
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40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults Communication
PMBus
Address
Command
D0h
Register
Address
S
W
A
A
A
...
PMBus
Address
Address+1
Data Byte
Data Byte
PEC*
Sr
R
A
A
A*
N
P
Figure 30 SMBus Custom Process Call to Read an MFR Register
1
S
7
Slave
Address 1
1
1
8
1
8
Low
Data Byte
1
8
High
Data Byte
1
8
1
Command
Code 1
A*
A
A
A
W
A
PEC1*
…
…
…
1 or more bytes
7
Slave
Address 2
1
1
1
8
1
8
Low
Data Byte
1
8
High
Data Byte
1
8
1
Command
Code 2
A
A*
A
A
A
Sr
W
PEC2*
…
1 or more bytes
1
7
1
1
1
8
1
8
1
8
1
8
1
Low
Data Byte
Slave
Address n
Command
Code n
High
Data Byte
A
A
A
P
Sr
W
A
A
PECn*
…
1 or more bytes
Figure 31 Group Command
Table 18 PMBus Commands Supported
I2C
Register
Address
PMBus
COMMAND
CODE
PMBus
PROTOCOL
COMMAND
DESCRIPTION
0x200
PAGE
Read/Write Byte
Read/Write Byte
00h
Allows access of each loop via paging.
Enables or disables the output and controls
margining. Ignores OVP on Margin High, UVP on
Margin Low.
0x202
OPERATION
01h
Configures the combination of CONTROL pin and
OPERATION commands needed to turn the unit
on and off.
0x204
0x206
0x20A
ON_OFF_CONFIG
CLEAR FAULTS
Read/Write Byte
Send Byte
02h
03h
05h
Clears contents of Fault registers
Set the PAGE within a device, send a command,
and send the data for the command in one
packet.
PAGE_PLUS_WRITE
Write Block
Set the PAGE within a device, send a command,
and read the returned data by the command in
one packet
Block Write/ Block
Read Process Call
0x20C
PAGE_PLUS_READ
06h
Protects from overwriting the configuration files
and modes accidentally
0x220
0x222
WRITE_PROTECT
Read/Write Byte
Sen Byte
10h
11h
Instructs the device to copy the entire contents of
the configuration registers to the NVM
STORE_DEFAULT_ALL
0x224
0x22A
0x22C
RESTORE_DEFAULT_ALL
STORE_USER_ALL
Send Byte
Send Byte
Send Byte
12h
15h
16h
Reloads the OTP
Stores the user OTP section
Reloads the user OTP section
RESTORE_USER_ALL
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Faults Communication
I2C
Register
Address
PMBus
COMMAND
CODE
PMBus
PROTOCOL
COMMAND
DESCRIPTION
Returns 1010xxxx to indicate Packet Error
Checking is supported. Maximum bus speed is 400
kHz
0x232
0x236
0x240
CAPABILITY
Read Byte
19h
1Bh
20h
Set to prevent warning or fault conditions from
asserting the SMBALERT# signal. Write command
code for STATUS register to be masked in the low
byte, the bit to be masked in the High byte.
Block Write/ Block
Read Process Call
SMBALERT_MASK
VOUT_MODE
Sets the format for VOUT related commands.
Linear mode, -8, -9, -10, -11 and -12 exponents
supported.
Read/Write Byte
Read/Write Word
Sets the voltage to which the device should set
the output. Format according to VOUT_MODE.
Resolution is 5 mV when the IC Vout is configured
with a load line. Resolution is 5 mV or 0.625 mV
when the IC is configured without a load line.
0x242
VOUT_COMMAND
21h
Sets an upper limit on the output voltage the unit
can command. Format according to VOUT_MODE.
0x248
0x24A
VOUT_MAX
Read/Write Word
Read/Write Word
24h
25h
Sets the margin high voltage when commanded
by OPERATION. Must be in format determined by
VOUT_MODE.
VOUT_MARGIN_HIGH
Sets the margin low voltage when commanded by
OPERATION. Must be in format determined by
VOUT_MODE.
0x24C
VOUT_MARGIN_LOW
Read/Write Word
26h
Sets the rate at which the output changes voltage
due to VOUT_COMMAND or OPERATION
commands.
0x24E
0x250
0x252
VOUT_TRANSITION_RATE
VOUT_DROOP
Read/Write Word
Read/Write Word
Read/Write Word
27h
28h
29h
Allows the user to set the load-line value in
res85ut287 8f ꢆ/ꢅꢆꢍ Ω. Ex987e7t 2s ꢂ
Used to account for any external attenuation
network on VOUT sense feedback and provide
correct VOUT reporting.
VOUT_SCALE_LOOP
Sets a lower limit on the commanded output
voltage. Format according to VOUT_MODE
0x256
0x266
0x26A
VOUT_MIN
FREQUENCY_SWITCH
VIN_ON
Read/Write Word
Read/Write Word
Read/Write Word
2Bh
33h
35h
Sets the switching frequency in kHz per table
found in user note UN0047. Exp = 0, 1
Sets the value of the input voltage at which the
unit should begin power conversion. Exp = -1.
Sets the value of the input voltage at which the
unit, once operation has started, should stop
power conversion. Exp = -1.
0x26C
VIN_OFF
Read/Write Word
36h
0x270
0x272
IOUT_CAL_GAIN
Read/Write Word
Read/Write Word
38h
39h
Used t8 ca52brate t1e 8ut9ut curre7tꢀs 0a27
Used to null out any offsets in the output current
sensing circuitry. Exp = 2.
IOUT_CAL_OFFSET
Returns the value of the output voltage,
measured at the sense or output pins, that causes
an output over voltage fault.
VOUT_OV_FAULT_
LIMIT
0x280
Read Only
40h
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Faults Communication
I2C
Register
Address
PMBus
COMMAND
CODE
PMBus
PROTOCOL
COMMAND
DESCRIPTION
Instructs the device on what action to take in
response to an output over voltage fault. Only
shutdown and ignore are supported.
VOUT_OV_FAULT_
RESPONSE
0x282
0x288
0x28A
Read/Write Byte
Read Only
41h
44h
45h
Returns the value of the output voltage,
measured at the sense or output pins, that causes
an output under voltage fault.
VOUT_UV_FAULT_
LIMIT
Instructs the device on what action to take in
response to an output under voltage fault.
Only shutdown and ignore are supported.
VOUT_UV_FAULT_
RESPONSE
Read/Write Byte
Sets the value of the output current, in amperes,
that causes the over current detector to indicate
an over current fault condition. Set by writing this
command in Linear format with a -1 exponent.
IOUT_OC_FAULT_
LIMIT
0x28C
0x28E
Read/Write Word
Read/Write Byte
46h
47h
Instructs the device on what action to take in
response to an output over current fault.
Only C0h (shutdown immediately), F8h (hiccup
forever), and D8 (hiccup 3 times) are supported.
IOUT_OC_FAULT_
RESPONSE
Sets the temperature, in degrees Celsius, of the
unit at which it should indicate an over
temperature fault. Exp = 0.
0x29E
0x2A0
OT_FAULT_LIMIT
Read/Write Word
Read/Write Byte
4Fh
50h
Instructs the device on what action to take in
response to an over temperature fault. Only
shutdown and ignore are supported.
OT_FAULT_RESPONSE
Sets the temperature, in degrees Celsius, of the
unit at which it should indicate an over
temperature Warning alarm. Exp = 0.
0x2A2
0x2AA
0x2AC
OT_WARN_LIMIT
VIN_OV_FAULT_LIMIT
VIN_OV_FAULT_RESPONSE
Read/Write Word
Read/Write Word
Read/Write Byte
51h
55h
56h
Sets the value of the input voltage that causes an
input over voltage fault. Exp = -4.
Instructs the device on what action to take in
response to an input over voltage fault. Only
shutdown and ignore are supported.
Sets the output voltage at which an optional
POWER_GOOD signal should be asserted. Format
according to VOUT_MODE. See Note 17
0x2BC
0x2BE
POWER_GOOD_ON
POWER_GOOD_OFF
Read/Write Word
Read/Write Word
5Eh
5Fh
Sets the output voltage at which an optional
POWER_GOOD signal should be negated. Format
according to VOUT_MODE. See Note 17
Sets the time, in milliseconds, from when a start
condition is received (as programmed by the
ON_OFF_CONFIG command) until the output
voltage starts to rise. Exp = 0.
0x2C0
0x2C2
0x2C8
TON_DELAY
TON_RISE
Read/Write Word
Read/Write Word
Read/Write Word
60h
61h
64h
Sets the time, in milliseconds, from when the
output starts to rise until the voltage has entered
the regulation band. Exp = 0.
Sets the time (in ms) from when a stop condition
is received (as programmed by the
ON_OFF_CONFIG command) until the unit stops
transferring energy to the output. Exp = 0.
TOFF_DELAY
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Faults Communication
I2C
Register
Address
PMBus
COMMAND
CODE
PMBus
PROTOCOL
COMMAND
DESCRIPTION
Sets the time, in milliseconds, from the end of the
turn-off delay time until the voltage is
commanded to zero. Exp = 0.
0x2CA
0x2F0
TOFF_FALL
Read/Write Word
Read/Write Byte
65h
Returns 1 byte where the bit meanings are:
Bit <7> Reserved
Bit <6> Output off (due to fault or enable)
Bit <5> Output over-voltage fault
Bit <4> Output over current fault
Bit <3> Input Under voltage fault
Bit <2> Temperature fault
STATUS_BYTE
78h
Bit <1> Communication/Memory/Logic fault
Bit <0>: None of the Above
Returns 2 bytes where the Low byte is the same as
the STATUS_BYTE data. The High byte has bit
meanings are:
Bit <7> Output high or low fault
Bit <6> Output over current fault
Bit <5> Input voltage or current fault.
Bit <4> MFR_SPECIFIC
0x2F2
STATUS_WORD
Read/Write Word
79h
Bit <3> POWR GOOD#
Bit <2:0> Not Supported
Bit <7> Output over voltage Fault
Bit <6> Not Supported
Bit <5> Not Supported
0x2F4
0x2F6
STATUS_VOUT
STATUS_IOUT
Read/Write Byte
Read/Write Byte
7Ah
7Bh
Bit <4> Output under voltage Fault
Bit <3> VOUT_MAX Warning
Bit <2:0> Not Supported
Bit <7> Output Over current Fault
Bit <6> Not Supported
Bit <5> Output Overcurent Warning
Bit <4:0> Not Supported
Bit <7> Input over voltage Fault
Bit <6:0> Not Supported
0x2F8
0x2FA
STATUS_INPUT
Read/Write Byte
Read/Write Byte
7Ch
7Dh
Bit <7> Over Temperature Fault
Bit <6> Over Temperature Warning
Bit <5:0> Reserved
STATUS_TEMPERATURE
Returns 1 byte where the bit meanings are:
Bit <7> Invalid or unsupported command
Bit <6> Invalid or unsupported data
Bit <5> PEC fault
0x2FC
STATUS_CML
Read/Write Byte
7Eh
Bit <4:2> Reserved
Bit <1> Other communication fault not listed here
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults Communication
I2C
Register
Address
PMBus
COMMAND
CODE
PMBus
PROTOCOL
COMMAND
DESCRIPTION
Bit <0> Reserved
0x310
0x312
READ_VIN
READ_IIN
Read Word
Read Word
88h
89h
Returns the input voltage in Volts
Returns the input current in Amperes
Returns the output voltage in the format set by
VOUT_MODE
0x316
0x318
0x31A
READ_VOUT
READ_IOUT
Read Word
Read Word
Read Word
8Bh
8Ch
8Dh
Returns the output current in Amperes
Returns the addressed loop NTC temperature in
degrees Celsius
READ_TEMPERATURE_1
0x32C
0x32E
READ_POUT
READ_PIN
Read Word
Read Word
96h
97h
Returns the output power in Watts
Returns the input power in Watts
Reports PMBus Part I rev 1.1 & PMBUs
Part II rev 1.2
0x330
PMBUS_REVISION
Read Byte
98h
The MFR_ID is set to IR (ASCII 52 49) unless
programmed differently in the USER registers of
the controller.
Block Read/Write
Byte count = 2
0x332
MFR_ID
99h
The MFR_MODEL is the same as the device ID if
the USER register for Manufacturer model is
00. Otherwise MFR_Model command returns the
value in the USER register for MFR_MODEL.
Block Read,
Byte count = 1
0x334
0x336
MFR_MODEL
9Ah
9Bh
The MFR_REVISION is the same as the device
revision if the USER register for Manufacturer
revision is 00. Otherwise MFR_REVISION
command returns the value in the USER register
for MFR_REVISION.
Block Read,
Byte count = 2
MFR_REVISION
Returns a 1-byte code with the following values:
84h = TDA38740
0x35A
0x35C
0x3A0
IC_DEVICE_ID
Block Read
Block Read
ADh
AEh
D0h
C1h
IC_DEVICE_REV
The IC revision that is stored inside the IC
MFR_READ/WRITE_
REG
Custom MFR
protocol
Read/Write I2C registers
0x382
0x384
MFR_VENDOR_INFO_1
MFR_VENDOR_INFO_2
Read Word
Returns the product id and silicon revision
Available for vendor use. Default 0x0
Read/ write Wod
Note:
17. PGOOD_ON and PGOOD_OFF thresholds are asserted at half of the programmed value when
VOUT_SCALE_LOOP is set to 1:2 mode. The threshold values should be set to twice of the desired PGOOD levels.
16.4
ꢂꢂ-BIT L27ear Data F8r6at
Monitored parameters use the Linear Data Format encoding into 1 Word (2 bytes), where:
Value =Y *2N
N8te N a7d Y are ꢋs207edꢊ va5ues. If VOUT 2s set t8 527ear f8r6at ꢎby VOUT_MODEꢏ, t1e7 N 2s set by t1e VOUT_MODE
command and only Y is returned in the data-field as a 16-bit unsigned number.
Final Datasheet
51 of 66
V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Faults Communication
Databyte Low
Databyte High
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
N
Y
Figure 32 11-Bit Linear Data Format
16.5
ꢂꢇ-BIT L27ear Data F8r6at
This format is only used for VOUT related commands (READ_VOUT, VOUT_COMMAND, VOUT_MARGIN_HIGH,
VOUT_MARGIN_LOW, POWER_GOOD_ON, and POWER_GOOD_LOW):
Value =Y *2N
N8te N a7d Y are ꢋs207edꢊ va5ues. If VOUT is set to linear format (by VOUT_MODE), then N is set by the
VOUT_MODE command and only Y is returned in the data-field as a 16-bit unsigned number.
Figure 33 16-BIT Linear Data Format
Final Datasheet
52 of 66
V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Design example
17
Des207 exa6p5e
In this section, an example is used to explain how to design a buck regulator with the TDA38740/725. The
application circuit is shown in Figure 3. The design specifications are given below.
•
•
•
•
•
PVin = 12 V (±10%)
Vo = 1.0 V
Io = 40 A
Vo ripple voltage = ±1% of Vo
Load transient response = ± 3% of Vo with a step load current = 9 A and slew rate = 30 A/µs
17.1
E7ab5270 t1e TDAꢉꢈꢊꢀꢁ/ꢊꢃꢄ
The TDA38740/725 has a precise Enable threshold voltage, the Enable feedback resistor, REN1 and REN2, can be
calculated as follows.
ꢭꢮꢯꢰ
ꢆꢇ
×
ꢞ ꢇꢮꢯꢧꢨꢲꢳꢪ
ꢈꢉꢧꢨiꢩꢪ
ꢭꢮꢯꢱ ꢚ ꢭꢮꢯꢰ
ꢇꢮꢯꢧꢨꢲꢳꢪ
ꢆꢇꢈꢉꢧꢨiꢩꢪ − ꢇꢮꢯꢧꢨꢲꢳꢪ
ꢭꢮꢯꢰ ꢞ ꢭꢮꢯꢱ
×
Where VEN(max) is the maximum spec of the En-start-threshold as defined in the Absolute Maximum Ratings table.
For PVin (min) =10.8 V, select REN1=49.9 kΩ and REN2 > 3.4 kΩ. REN2 suggested = 7.5 kΩ
17.2
Pr80ra66270 t1e Sw2tc1270 Freque7cy a7d Operat287 M8de
The TDA38740/725 has very good efficiency performance and is suitable for high switching frequency operation.
In this case, 800 kHz is selected to achieve a good compromise between the efficiency, passive component size
and dynamic response. In addition, FCCM operation is selected to ensure a small output ripple voltage over the
entire load range. The switching frequency and FCCM operation can be selected via register bits.
17.3
Se5ect270 I7put Capac2t8rs
Without input capacitors, the pulse current of Control MOSFET is directly from the input supply power. Due to the
impedance on the cable, the pulse current can cause disturbance on the input voltage and potential EMI issues.
The input capacitors filter the pulse current, resulting in almost constant current from the input supply. The input
capacitors should be selected to tolerate the input pulse current, and to reduce the input voltage ripple. The RMS
value of the input ripple current can be expressed by:
ꢑꢁꢙꢴ = ꢑ × ꢬ × ꢧꢍ − ꢬꢪ
√
ꢋ
ꢇ
ꢋ
ꢬ =
ꢆꢇ
ꢈꢉ
Where IRMS is the RMS value of the input capacitor current. Io is the output current and D is the Duty Cycle. For Io =
40 A and D(max) = 0.09, the resulting RMS current flowing into the input capacitor is Irms = 11.6 A.
To meet the requirement of the input ripple voltage, the minimum input capacitance can be calculated as follows.
ꢑꢋ × ꢧꢍ − ꢬꢪ × ꢬ
ꢵꢈꢉꢧꢨiꢩꢪ
>
ꢧ
ꢪ
ꢎ
ꢏꢐ
× ꢧ∆ꢆꢇ − ꢶꢷꢭ × ꢑꢋ × ꢍ − ꢬ ꢪ
ꢈꢉ
Final Datasheet
53 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Design example
W1ere ∆PVin is the maximum allowable peak-to-peak input ripple voltage, and ESR is the equivalent series resistor
of the input capacitors. Ceramic capacitors are recommended due to low ESR, ESL and high RMS current
capability. For Io = 40 A, fsw = ꢐꢄꢄ 4Hz, ESR = ꢇ 6Ω, a7d ∆PVin = 240 mV, Cin(min) > 32 µF. To account for the de-rating
of ceramic capacitors under a bias voltage, 8 x 22 µF/0805/25 V MLCC and 1 x 4.7uF/25 V MLCC are used for the
input capacitors. In addition, a bulk capacitor is recommended if the input supply is not located close to the
voltage regulator.
17.4
I7duct8r Se5ect287
The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor
value results in a large ripple current, lower efficiency and high output noise, but helps with size reduction and
transient load response. Generally, the desired peak-to-9ea4 r2995e curre7t 27 t1e 27duct8r ꢎ∆2ꢏ 2s f8u7d betwee7
20% and 50% of the output current.
The inductor saturation current must be higher than the maximum spec of the OCP limit plus the peak-to-peak
inductor ripple current. For some core material, inductor saturation current may decrease as the increase of
temperature. So it is important to check the inductor saturation current at the maximum operating temperature.
The inductor value for the desired operating ripple current can be determined using the following relation:
ꢬꢟꢈꢉ
ꢸ = ꢧꢆꢇꢈꢉꢧꢨꢲꢳꢪ − ꢇ ꢪ ×
ꢋ
∆ꢛꢗꢧꢨꢲꢳꢪ × ꢹ
ꢏꢐ
ꢇ
ꢋ
ꢬꢟꢈꢉ
=
ꢆꢇ
ꢈꢉꢧꢨꢲꢳꢪ
ꢑꢏꢝꢓ ꢞ ꢺꢵꢆꢟꢝꢠ ꢚ ∆ꢛꢗꢧꢨꢲꢳꢪ
Where: PVin(max) = Maximum input voltage; ∆2Lmax = Maximum peak-to-peak inductor ripple current; OCPmax
=
maximum spec of the OCP limit as defined in Section 15.1, and Isat = inductor saturation current. In this case, select
inductor L =150 nH to achieve ∆2Lmax = 25% of Iomax. The Isat should be no less than 52 A.
17.5
Output Capac2t8r Se5ect287
The output capacitor selection is mainly determined by the output voltage ripple and transient requirements.
To satisfy the Vo ripple requirement, Co should satisfy the following criterion.
∆ꢛꢗꢟꢝꢠ
ꢵꢋ >
8 × ∆ꢇ × ꢎ
ꢋꢻ
ꢏꢐ
W1ere ∆Vor is the desired peak-to-peak output ripple voltage. For ∆2Lmax= ꢃ.ꢆ A, ∆Vor =20 mV, fsw = 800 kHz, Co must
be larger than 59 µF. The ESR and ESL of the output capacitors, as well as the parasitic resistance or inductance
due to PCB layout, can also contribute to the output voltage ripple. It is suggested to use Multi-Layer Ceramic
Capacitor (MLCC) for their low ESR, ESL and small size.
To meet the transient response requirements, the output capacitors should also meet the following criterion.
ꢸ × ∆ꢑꢋꢰꢧꢨꢲꢳꢪ
ꢵꢋ >
ꢜ × ∆ꢇꢋꢗ × ꢇ
ꢋ
W1ere ∆VOL is the allowable Vo dev2at287 dur270 t1e 58ad tra7s2e7t. ∆Io(max) is the maximum step load current. Please
note that the impact of ESL, ESR, control loop response, transient load slew rate, and PWM latency is not
considered in the calculation shown above. Extra capacitance is usually needed to meet the transient
requirements. As a rule of thumb, we can triple the Co that is calculated above as a starting point, and then
optimize the design based on the bench measurement. In this case, to meet the transient load requirement (i.e.
Final Datasheet
54 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Design example
∆VOL= 30 mV, ∆Io(max) = 9 A), select Co = ~600 µF. For more accurate estimation of Co, simulation tool should be used
to aid the design.
17.6
B88tstrap Capac2t8r
For most applications, a 0.1 µF ceramic capacitor is recommended for bootstrap capacitor placed between PHASE
and BOOT Pin. For applications requiring PVin equa5 t8 8r ab8ve ꢂꢈ V, a s6a55 res2st8r 8f ꢂ~ꢅ Ω s18u5d be used 27
series with the BOOT pin to ensure the maximum SW node spike voltage does not exceed 20 V.
17.7
VI a7d VCC/LDO bypass Capac2t8r
Please see the recommendation in 13.4 on the internal LDO. A 10 µF MLCC is selected for the VCC/LDO bypass
capacitor and a 4.7 µF MLCC is selected for the VIN bypass capacitor.
17.8
Des207 Rec866e7dat287s
Listed below are the design recommendations for proper device operation:
•
•
•
•
A 100 Ohm minimum load resistor should be connected across the output
Add a 0.1 uF and 1 uF ceramic cap across PVIN and PGND
Add 0.1 uF and 2.2 uF across VDRV to PGND.
The internal LDO should not be used to power external devices
Final Datasheet
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V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Layout Recommendations
18
Lay8ut Rec866e7dat287s
PCB layout is very important when designing high frequency switching converters. Layout will affect noise pickup
and can cause a good design to perform with less than expected results. Following design guidelines are
recommended to achieve the best performance.
•
Bypass capacitors, including input/output capacitors, VIN, VCC and VDRV bypass capacitors, should be placed
near the corresponding pins as close as possible.
•
Place bypass capacitors from TDA38740/725 power input (Drain of Control MOSFET) to PGND (Source of
Synchronous MOSFET) to reduce noise and ringing in the system. The output capacitors should be terminated
to a ground plane that is away from the input PGND to mitigate the switching spikes on the Vo. The bypass
capacitor shared by VCC and VDRV should be terminated to PGND.
•
Place a boot strap capacitor near the TDA38740/725 BOOT and PHASE pin as close as possible to minimize the
loop inductance.
•
•
SW node copper should only be routed on the top layer to minimize the impact of switching noises
Connect AGND pin to the PGND pad through a single point connection. On the TDA38740/725 demo board,
AGND pin is connected to the exposed PGND pad with a copper trace.
•
•
Via holes can be placed on PVin and PGND pads to aid thermal dissipation.
Wide copper polygons are desired for PVin and PGND connections in favor of power losses reduction and
thermal dissipation. Sufficient via holes should be used to connect power traces between different layers.
•
Output voltage sensing in TDA38740/725 is done differentially using the VOSENP and VOSENM pins.
o
A pair of PCB traces with at least 15 mil trace width, running close to each other and away from
any noise sources such as inductor and SW nodes, should be used to implement Kelvin sensing of
the voltage across a high-frequency bypass capacitor of 0.1 µF or higher.
o
o
The ground connection of the remote sensing signal must be terminated at VOSENM pin.
The Vo connection of the remote sensing signal must be connected to the feedback resistor divider
with the lower feedback resistor terminated at VOSENM pin for output voltages greater than 2.5 V.
o
o
Shield the pair of remote sensing lines with ground planes above and below.
Do NOT connect VOSENM pin and AGND pin in this configuration
•
The EN pin and configuration pins including SM_ADDRS/PROG, VBT, MODE/TON, and ILIM should be
terminated to a quiet ground. On the TDA38740/725 standard demo board, they are terminated to the PGND
copper plane away from the power current flow. Alternatively, they can be terminated to a dedicated AGND
PCB trace.
Final Datasheet
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V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Layout Recommendations
18.1
PCB Meta5 a7d C86p87e7t P5ace6e7t
Evaluation has shown that the best overall performance is achieved using the substrate/PCB layout as shown in
the following figures. PQFN devices should be placed to an accuracy of 0.050 mm on both X and Y axes. Self-
centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the
limits of self-centering on specific processes.
F8r furt1er 27f8r6at287, 95ease refer t8 ꢋSu9IRBuc4™ Mu5t2-Chip Module (MCM) Power Quad Flat No-Lead (PQFN)
B8ard M8u7t270 A9952cat287 N8te.ꢊ ꢎANꢂꢂꢇꢅꢏ
Figure 34
PCB metal pad sizing and spacing (all dimensions in mm)
18.2
S85der Res2st
Infineon recommends that larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the
underlying copper traces to be as large as possible, which helps in terms of current carrying capability and
device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05 mm larger
(on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1
mm in X & Y.) When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least
Final Datasheet
57 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Layout Recommendations
0.025 mm on each edge, (i.e. 0.05 mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure
that the solder resist in-between the smaller signal lead areas is at least 0.15 mm wide, due to the high x/y aspect
ratio of the solder mask strip.
Figure 35
Solder resist
18.3
Ste7c25 Des207
Stencils for PQFN packages can be used with thicknesses of 0.100-0.250 mm (0.004-ꢄ.ꢄꢂꢄꢊꢏ. Ste7c25s t1277er
than 0.100 mm are unsuitable because they deposit insufficient solder paste to make good solder joints with
the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125 mm-0.200
mm (0.005-ꢄ.ꢄꢄꢐꢊꢏ, w2t1 su2tab5e reduct287s, 02ve t1e best resu5ts.
A recommended stencil design is shown in Figure 36. This design is f8r a ste7c25 t12c47ess 8f ꢄ.ꢂꢅꢃ 66 ꢎꢄ.ꢄꢄꢆꢊꢏ.
The reduction should be adjusted for stencils of other thicknesses.
Final Datasheet
58 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Layout Recommendations
Figure 36
Stencil pad size and spacing (all dimensions in mm)
Final Datasheet
59 of 66
V2.6
2022-11-16
TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Package
19
Pac4a0e
19.1
Mar4270 I7f8r6at287
Figure 37 Package Marking
19.2
D26e7s287s
Figure 38 Package view
Final Datasheet
60 of 66
V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Package
Figure 39 Package Dimensions in mm
Final Datasheet
61 of 66
V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Package
Figure 40 Package Dimensions – Pad Layout
Final Datasheet
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V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
19.3
Tape a7d Ree5 I7f8r6at287
Figure 41 Pin 1 Orientation in Tape & Reel
Final Datasheet
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V2.6
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TDA38740/25 OptiMOS iPOL
40/25A Single-voltage Synchronous Buck Regulator with PMBus
Environmental Qualifications
20
E7v2r876e7ta5 Qua52f2cat287s
Table 19
Qualification Level
Industrial
JEDEC Level 2 @ 260°C
Moisture Sensitivity
5 x 6 mm QFN Package
Human Body Model
ANSI/ESDA/JEDEC JS-001, Class 2 (2000V to < 4000V)
ESD
Charged Device Model
ANSI/ESDA/JEDEC JS-002, Class C3 ꢎꢑ 1000V)
This product follows EU Directive 2015/863/EU amending
annex II to EU Directive 2011/65/EU(RoHS) and contains Pb
RoHS2 Compliant
according RoHS exemption 7a,Lead in high melting
temperature type solders
Final Datasheet
64 of 66
V2.6
2022-11-16
PointꢀofꢀLoad
TDA38740/725
RevisionꢀHistory
TDA38740/725
Revision:ꢀ2022-11-21,ꢀRev.ꢀ2.6
Previous Revision
Revision Date
Subjects (major changes since last revision)
2.0
2.1
2.2
2.3
2.4
2.5
2022-04-08
Release of final version
2022-04-13
2022-05-13
2022-08-12
2022-08-19
2022-10-21
Updated the Abs max table with VIN-PH voltage
Final datasheet revision - updated block diagram and EC table
Updated Multiple time programmable section
corrected the number of MTP writes on page 1
Added the setpoint accuracy data to table 6, updated the Pgood pull up resistor to 4.7k,
updated the absolute max ratings (table 3) to align with 741 DS, Updated MTP capability
of the device in section 13.2,Added description for pinstrapping in section 8
2.6
2022-11-21
Updated Prebias section, Programming Section, Absolute max ratings table, Electrical
Characteristics Table, Updated page number formatting
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automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
65
Rev.ꢀ2.6,ꢀꢀ2022-11-21
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带 PMBus 接口的 40 A OptiMOS™ IPOL 单电压同步降压调节器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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