TDA4605-3 [INFINEON]
Control IC for Switched-Mode Power Supplies using MOS-Transistor; 控制IC使用MOS三极管开关模式电源
| 型号： | TDA4605-3 |
| 厂家： | 
Infineon |
| 描述： | Control IC for Switched-Mode Power Supplies using MOS-Transistor |
| 文件： | 总20页 (文件大小：558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Control IC for Switched-Mode Power Supplies
using MOS-Transistor
TDA 4605-3
Bipolar IC
Features
● Fold-back characteristics provides overload protection for
external components
● Burst operation under secondary short-circuit condition
implemented
● Protection against open or a short of the control loop
● Switch-off if line voltage is too low (undervoltage switch-off)
● Line voltage depending compensation of fold-back point
● Soft-start for quiet start-up without noise generated by the
transformer
P-DIP-8-1
● Chip-over temperature protection implemented (thermal
shutdown)
● On-chip ringing suppression circuit against parasitic
oscillations of the transformer
● AGC-voltage reduction at low load
Type
Ordering Code
Package
TDA 4605-3
Q67000-A5066
P-DIP-8-1
The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and
protection functions in free running flyback converters. Because of the fact that a wide load range
is achieved, this IC is applicable for consumer as well as industrial power supplies.
The serial circuit and primary winding of the flyback transformer are connected in series to the input
voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the
switch-off period the energy is fed to the load via the secondary winding. By varying switch-on time
of the power transistor, the IC controls each portion of energy transferred to the secondary side
such that the output voltage remains nearly independent of load variations. The required control
information is taken from the input voltage during the switch-on period and from a regulation winding
during the switch-off period. A new cycle will start if the transformer has transferred the stored
energy completely into the load.
Semiconductor Group
74
06.94
TDA 4605-3
In the different load ranges the switched-mode power supply (SMPS) behaves as follows:
No load operation
The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be
a little bit higher or lower than the nominal value depending of the design of the transformer and the
resistors of the control voltage divider.
Nominal operation
The switching frequency is reduced with increasing load and decreasing AC-voltage.
The output voltage is only dependent on the load.
Overload point
Maximal output power is available at this point of the output characteristic.
Overload
The energy transferred per operation cycle is limited at the top. Therefore the output voltages
declines by secondary overloading.
Semiconductor Group
75
TDA 4605-3
Pin Definitions and Functions
Pin No.
Function
1
Information Input Concerning Secondary Voltage. By comparing the
regulating voltage - obtained trom the regulating winding of the transformer - with
the internal reference voltage, the output impulse width on pin 5 is adjusted to the
load of the secondary side (normal, overload, short-circuit, no load).
2
3
Information Input Regarding the Primary Current. The primary current rise in
the primary winding is simulated at pin 2 as a voltage rise by means of external
RC-element. When a voltage level is reached thats derived from the regulating
voltage at pin 1, the output impulse at pin 5 is terminated. The RC-element serves
to set the maximum power at the overload point set.
Input for Primary Voltage Monitoring: In the normal operation V3 is moving
between the thresholds V3H and V3L (V3H > V3 > V3L).
V3 < V3L: SMPS is switched OFF (line voltage too low).
V3 > V3H : Compensation of the overload point regulation (controlled by pin 2)
starts at V3H : V3L = 1.7.
4
5
Ground
Output: Push-pull output provides ± 1 A for rapid charge and discharge of the
gate capacitance of the power MOS-transistor.
6
Supply Voltage Input: A stable internal reference voltage VREF is derived from
the supply voltage also the switching thresholds V6A , V6E , V6 max and V6 min for
the supply voltage detector. If V6 > V6E then VREF is switched on and swiched off
when V6 < V6A . In addition the logic is only enable for V6 min < V6 < V6 max
.
7
8
Input for Soft-Start. Start-up will begin with short pulses by connecting a
capacitor from pin 7 to ground.
Input for the Oscillation Feedback. After starting oscillation, every zero
transition of the feedback voltage (falling edge) through zero (falling edge)
triggers an output pulse at pin 5. The trigger threshold is at + 50 mV typical.
Semiconductor Group
76
TDA 4605-3
Block Diagram
Semiconductor Group
77
TDA 4605-3
Circuit Description
Application Circuit
The application circuit shows a flyback converter for video recorders with an output power rating of
70 W. The circuit is designed as a wide-range power supply for AC-line voltages of 180 to 264 V.
The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1 . The NTC limits
the rush-in current.
In the period before the switch-on threshold is reached the IC is suppled via resistor R 1 ; during the
start-up phase it uses the energy stored in C2 , under steady state conditions the IC receives its
supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90.
The parallel connected capacitor C3 and the inductance of primary winding n 2 determine the
system resonance frequency. The R 2-C4-D2 circuitry limits overshoot peaks, and R 3 protects the
gate of T1 against static charges.
During the conductive phase of the power transistor T1 the current rise in the primary winding
depends on the winding inductance and the mains voltage. The network consisting of R 4-C5 is used
to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage
is fed into pin 2 of the IC. The RC-time constant given by R 4-C5 must be designed that way that
driving the transistor core into saturation is avoided.
The ratio of the voltage divider R 10/R 11 is fixing a voltage level threshold. Below this threshold the
switching power supply shall stop operation because of the low mains voltage. The control voltage
present at pin 3 also determines the correction current for the fold-back point. This current added to
the current flowing through R 4 and represents an additional charge to C5 in order to reduce the turn-
on phase of T1. This is done to stabilize the fold-back point even under higher mains voltages.
Regulation of the switched-mode power supplies via pin 1. The control voltage of winding n1 during
the off period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by
R 5 , R 6 and R 7 . The R 8-C7 network suppresses parasitic overshoots (transformer oscillation). The
peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage
applied across the control winding, and hence the output voltages, are at the desired level.
When the transformer has supplied its energy to the load, the control voltage passes through zero.
The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are
also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore
the IC ignores zero crossings occurring within a specified period of time after T1 turn-off.
The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to
keep the operating frequency outside the audible range during start-up.
On the secondary side, five output voltages are produced across winding n3 to n7 rectified by D4 to
D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors.
Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which
are designed to supply only small loads.
Semiconductor Group
78
TDA 4605-3
Block Diagram
Pin 1
The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR
in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If
the control voltage is rather small at pin 1 an additional current is added by means of current source
which is controlled according the level at pin 7. This additional current is virtually reducing the
control voltage present at pin 1.
Pin 2
A voltage proportional to the drain current of the switching transistor is generated there by the
external RC-combination in conjunction with the primary current transducer. The output of this
transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage
V2 exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator
and consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage
are the output for the start impulse generator with the stable reference potential VST and the
supply voltage motor.
Pin 3
The down divided primary voltage applied there stabilizes the overload point. In addition the logic is
disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary
voltage monitor block.
Pin 4
Ground
Pin 5
In the output stage the output signals produced by the logic are shifted to a level suitable for MOS-
power transistors.
Pin 6
From the supply voltage V6 are derived a stable internal references VREF and the switching
threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All references values (VR ,
V2B , VST) are derived from VREF . If V6 > VVE , the VREF is switched on and switched off when V6 <
V 6A . In addition, the logic is released only for V6 min < V6 < V6 max
.
Pin 7
The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction
in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is
connected to ground by a capacitor.
Semiconductor Group
79
TDA 4605-3
Pin 8
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per sheet 88 is represented an sheet 90 for a line
voltage barely above the lower acceptable limit time t0 the following voltages built up:
– V6 corresponding to the half-wave charge current over R1
– V2 to V2 max (typically 6.6 V)
– V3 to the value determined by the divider R 10/R 11
.
The current drawn by the IC in this case is less than 1.6 mA.
If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The
current draw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2B
and the starting impulse generator generates the starting impulses from time point t5 to t6 . The
feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are
controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short-
circuit event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting
attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases
to V6 . The IC switches off; V6 can rise again (time point t4) and a new start-up attempt begins at
time point t1 . If the rectified alternating Iine voltage (primary voltage) collapses during load, V3 can
fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The
primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new start-
up attempt begins at time point t1 .
Semiconductor Group
80
TDA 4605-3
Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is
400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak
voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the
overload amplifier begins to regulate the pulse width downward. This point is referred to as the
overload point of the power supply. As the IC-supply voltage V6 is directly proportional to the
secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls
below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave
charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up
without problems from the virtual short-circuit, which every switching on with V1 = 0 represents. If
the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency
increases up to the resonance frequency of the system. If the load is further reduced, the secondary
voltages and V6 increase. When V6 = V6 max the logic is blocked. The IC converts to burst
operation.This renders the circuit absolutely safe under no-load conditions.
Behaviour when Temperature Exceeds Limit
An integrated temperature protection disables the logic when the chip temperature becomes too
high. The IC automatically interrogates the temperature and starts as soon as the temperature
decreases to permissible values.
Semiconductor Group
81
TDA 4605-3
Absolute Maximum Ratings
TA = – 20 to 85 ˚C
Parameter
Symbol
Limit Values Unit Remarks
min.
max.
Voltages
Currents
pin 1
pin 2
pin 3
pin 5
pin 6
pin 7
V1
V2
V3
V5
V6
V7
– 0.3
– 0.3
– 0.3
– 0.3 V6
– 0.3
3
V
V
V
V
V
V
20
Supply voltage
– 0.3
pin 1
pin 2
pin 3
pin 4
pin 5
pin 6
pin 7
pin 8
I1
I2
I3
I4
I5
I6
I7
I8
3
3
3
mA
mA
mA
A
A
A
– 1.5
– 0.5
tp ≤ 50 µs; v ≤ 0.1*)
tp ≤ 50 µs; v ≤ 0.1
tp ≤ 50 µs; v ≤ 0.1
1.5
0.5
3
mA
mA
– 5
3
Junction temperature
Storage temperature
Tj
125
125
˚C
˚C
Tstg
– 40
Operating Range
Supply voltage
V6
TA
7.5
15.5
85
V
IC "on"
Ambient temperature
Heat resistance
– 20
˚C
Junction to environment
Junction case
Rth JE
Rth JC
100
70
K/W
K/W measured at pin 4
*) t p= pulse width
v= duty circle
Semiconductor Group
82
TDA 4605-3
Characteristics
TA = 25 ˚C; VS = 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Start-Up Hysteresis
Start-up current drain I6E0
0.6
12
5
0.8
13
5.5
14
13
mA
V
V6 = V6E
1
1
1
1
1
Switch-on voltage
Switch-off voltage
Switch-on current
Switch-off current
V6E
V6A
I6E1
I6A1
11
4.5
7
V
11
10
mA
mA
V6 = V6E
V6 = V6A
5
Voltage Clamp (V6 = 10 V, IC switched off)
At pin 2 (V6 ≤ V6E)
At pin 3 (V6 ≤ V6E)
V2 max
V3 max
5.6
5.6
6.6
6.6
8
8
V
V
I2 = 1 mA
I3 = 1 mA
1
1
Control Range
Control input voltage V1R
390
30
400
43
410
60
mV
dB
2
2
Voltage gain of the
control circuit in the
control range
– VR
VR = d
(V2S – V2B) / – dV1
f = 1 kHz
Primary Current Simulation Voltage
Basic value 0.97
V2B
1.00
1.03
V
2
Overload Range and Short-Circuit Operation
Peak value in the
range of secondary
overload
V2B
2.9
3.0
3.1
2.6
V
V
V1 = V1R – 10 mV
V1 = 0 V
2
2
Peak value in the
V2K
2.2
2.4
range of secondary
short-circuit operation
Fold-Back Point Correction
Fold-back point
– I2
300
500
650
µA
V3 = 3.7 V
1
correction current
Semiconductor Group
83
TDA 4605-3
Characteristics (cont’d)
TA = 25 ˚C; VS = 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Generally Valid Data (V6 = 10 V)
Voltage of the Zero Transition Detector
Positive clamping
voltage
V8P
0.7
0.75
0.82
V
I8 = 1 mA
2
2
Negative clamping
voltage
V8N
– 0.25 – 0.2 – 0.15 V
I8 = – 1 mA
Threshold value
V8S
tUL
40
50
76
mV
2
2
Suppression of
3.0
3.5
3.8
µs
transformer ringing
Input current
– I8
0
4
µA
V8 = 0
2
Push-Pull Output Stage
Saturation voltages
Pin 5 sourcing
Pin 5 sinking
Pin 5 sinking
VSat0
VSatV
VSatV
1.5
1.0
1.4
2.0
1.2
1.8
V
V
V
I5 = – 0.1 A
I5 = + 0.1 A
I5 = + 0.5 A
1
1
1
Output Slew Rate
Rising edge
+ dV5/dt
+ dV5/dt
70
V/µs
V/µs
2
2
Falling edge
100
Reduction of Control Voltage
Current to reduce the – I1
50
130
µA
V7 = 1.1 V, V1 = 0.4 V
control voltage
Semiconductor Group
84
TDA 4605-3
Characteristics (cont’d)
TA = 25 ˚C; VS = 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Protection Circuit
Undervoltage
protection
for V6 : voltage at
pin 5 = V5 min
if V6 < V5 min
V6 min
V6 max
V3A
7.0
7.25
16
7.5
V
V
2
2
Undervoltage
protection for V6 :
voltage at
pin 5 = V5 min
if V6 > V6 max
15.5
985
16.5
Undervoltage
protection for VAC
voltage at
pin 4 = V5 min
if V3 < V3A
:
1000 1015 mV
V2 = 0 V
1
2
Over temperature at
the given chip
temperature the IC
will switch V5 toV5 min Tj
150
˚C
Voltage at pin 3 if one
of the protection
function was
triggered;
(V3 will be clamped
until V6 < V6A)
V3Sat
I6
0.4
8
0.8
V
I3 = 750 µA
1
1
Current drain during
burst operation
mA
V3 = V2 = 0 V
Semiconductor Group
85
TDA 4605-3
Test Circuit 1
Test Circuit 2
Semiconductor Group
86
TDA 4605-3
Application Circuit
Semiconductor Group
87
TDA 4605-3
Diagrams
Semiconductor Group
88
TDA 4605-3
Semiconductor Group
89
TDA 4605-3
Start-Up Hysteresis
Semiconductor Group
90
TDA 4605-3
Operation in Test Circuit 2
Semiconductor Group
91
TDA 4605-3
Start-Up Current as a Function of the
Ambient Temperature
Overload Point Correction as a Function of
the Voltage at Pin 3
Semiconductor Group
92
TDA 4605-3
Recommended Heat Sink by 60 ˚C Ambient Temperature
Narrow Range 180 V ... 120 V ~
Narrow Range 90 V ... 270 V ~
Semiconductor Group
93
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