TDA5221 [INFINEON]

ASK/FSK Single Conversion Receiver; ASK / FSK单一转换接收器
TDA5221
型号: TDA5221
厂家: Infineon    Infineon
描述:

ASK/FSK Single Conversion Receiver
ASK / FSK单一转换接收器

电信集成电路 电信电路
文件: 总44页 (文件大小:679K)
中文:  中文翻译
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Wireless Components  
ASK/FSK Single Conversion Receiver  
TDA 5221 Version 0.1  
Target Specification October 2001  
confidential  
preliminary  
Revision History  
Current Version: 0.1. as of 31.10.01  
Please note that this is a target specification that is subject to change.  
Previous Version: n.a.  
Page  
Page(s)  
Subjects (major changes since last revision)  
(in previous  
Version)  
(in current  
Version)  
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Edition 10.01  
Published by Infineon Technologies AG,  
Balanstraße 73,  
81541 München  
© Infineon Technologies AG October 2001.  
All Rights Reserved.  
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TDA 5221  
preliminary  
Product Info  
Product Info  
Package  
General Description The IC is a very low power consump-  
tion single chip FSK/ASK Superhet-  
erodyne Receiver (SHR) for the  
frequency band 300 to 340 MHz. The  
IC offers a high level of integration and  
needs only a few external compo-  
nents. The device contains a low noise  
amplifier (LNA), a double balanced  
mixer, a fully integrated VCO, a PLL  
synthesiser, a crystal oscillator, a lim-  
iter with RSSI generator, a PLL FSK  
demodulator, a data filter, a data com-  
parator (slicer) and a peak detector.  
Additionally there is a power down fea-  
ture to save battery life.  
Features Low supply current (Is = 6.4 mA  
typ. in FSK mode, Is = 5.6 mA typ.  
in ASK mode)  
Selectable frequency ranges 300-  
320 MHz and 300-340 MHz  
Limiter with RSSI generation,  
Supply voltage range 5V ±10%  
operating at 10.7MHz  
Power down mode with very low  
Selectable reference frequency  
supply current (50nA typ.)  
2nd order low pass data filter with  
FSK and ASK demodulation capa-  
external capacitors  
bility  
Data slicer with self-adjusting  
Fully integrated VCO and PLL  
threshold  
Synthesiser  
FSK sensitivity better than  
-102 dBm over specified tempera-  
ture range (- 40 to +105°C)  
ASK sensitivity better than  
-110 dBm over specified tempera-  
ture range (- 40 to +105°C)  
Applications Keyless Entry Systems  
Remote Control Systems  
Alarm Systems  
Low Bitrate Communication  
Systems  
Ordering Information  
Type  
Ordering Code  
Q67037-A1147  
Package  
TDA 5221  
samples available  
P-TSSOP-28-1  
Wireless Components  
Product Info  
Target Specification, October 2001  
1
Table of Contents  
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
2
2.1  
2.2  
2.3  
2.4  
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
2
2
3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
2
3.1  
3.2  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3
3.3  
3.4  
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
9
9
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.6 FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.7 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
9
10  
10  
10  
10  
11  
11  
12  
12  
12  
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
2
4.1  
4.2  
4.3  
4.4  
Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4
5
6
4.5  
4.6  
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7
8
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
9
10  
4.7  
Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
11  
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
2
3
4
9
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5.1.3 AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
2
Product Description  
Contents of this Chapter  
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
TDA 5221  
preliminary  
Product Description  
2.1 Overview  
The IC is a very low power consumption single chip FSK/ASK Superheterodyne  
Receiver (SHR) for receive frequencies between 300 and 340 MHz. The IC  
offers a high level of integration and needs only a few external components. The  
device contains a low noise amplifier (LNA), a double balanced mixer, a fully  
integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI gen-  
erator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a  
peak detector. Additionally there is a power down feature to save battery life.  
2.2 Application  
Keyless Entry Systems  
Remote Control Systems  
Alarm Systems  
Low Bitrate Communication Systems  
2.3 Features  
Low supply current (Is = 6.4 mA typ.FSK mode, 5.6 mA typ. ASK mode)  
Supply voltage range 5V ±10%  
Power down mode with very low supply current (50nA typ.)  
FSK and ASK demodulation capability  
Fully integrated VCO and PLL Synthesiser  
RF input sensitivity ASK -113dBm typ. at 25°C, better than -110dBm over  
complete specified operating temperature range (-40 to +105°C)  
RF input sensitivity FSK -105dBm typ. at 25°C, better than -102dBm over  
complete specified operating temperature range (-40 to +105°C)  
Receive frequency range between 310 and 340 MHz  
Selectable reference frequency  
Limiter with RSSI generation, operating at 10.7MHz  
2nd order low pass data filter with external capacitors  
Data slicer with self-adjusting threshold  
Wireless Components  
2 - 2  
Target Specification, October 2001  
TDA 5221  
preliminary  
Product Description  
2.4 Package Outlines  
P_TSSOP_28.EPS  
Figure 2-1  
P-TSSOP-28-1 package outlines  
Wireless Components  
2 - 3  
Target Specification, October 2001  
3
Functional Description  
Contents of this Chapter  
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9  
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9  
TDA 5221  
preliminary  
Functional Description  
3.1 Pin Configuration  
CRST1  
VCC  
LNI  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CRST2  
PDW N  
PDO  
2
3
TAG C  
AG ND  
LNO  
4
DATA  
3VO UT  
THRES  
FFB  
5
6
VCC  
M I  
7
TDA 5221  
8
O PP  
M IX  
9
SLN  
AG ND  
FSEL  
IFO  
10  
11  
12  
13  
14  
SLP  
LIM X  
LIM  
DG ND  
VDD  
SSEL  
M SEL  
Pin_Configuration_5221.wmf  
Figure 3-1  
IC Pin Configuration  
Wireless Components  
3 - 2  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
3.2 Pin Definition and Function  
In the subsequent table the internal circuits connected to the pins of the device  
are shown. ESD-protection circuits are omitted to ease reading.  
.
Table 3-1 Pin Definition and Function  
Pin No. Symbol  
Equivalent I/O-Schematic  
Function  
1
CRST1  
External Crystal Connector 1  
4.15V  
1
50uA  
2
3
VCC  
LNI  
5V Supply  
LNA Input  
57uA  
3
500uA  
4k  
1k  
Wireless Components  
3 - 3  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
4
TAGC  
AGC Time Constant Control  
4.3V  
3uA  
4
1k  
1.4uA  
1.7V  
5
6
AGND  
LNO  
Analogue Ground Return  
LNA Output  
5V  
1k  
6
7
8
VCC  
MI  
5V Supply  
Mixer Input  
1.7V  
2k  
2k  
9
MIX  
Complementary Mixer Input  
8
9
400uA  
10  
AGND  
Analogue Ground Return  
Wireless Components  
3 - 4  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
11  
FSEL  
Frequency Selector  
1.2V  
40k  
11  
12  
IFO  
10.7 MHz IF Mixer Output  
300uA  
2.2V  
60  
12  
4.5k  
13  
14  
DGND  
VDD  
Digital Ground Return  
5V Supply (PLL Counter Cir-  
cuitry)  
15  
MSEL  
ASK/FSK Modulation Format  
Selector  
1.2V  
40k  
15  
16  
SSEL  
Data-Slicer Reference-Level  
Selector  
1.2V  
40k  
16  
Wireless Components  
3 - 5  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
17  
18  
LIM  
Limiter Input  
2.4V  
15k  
17  
LIMX  
Complementary Limiter Input  
75uA  
330  
18  
15k  
19  
SLP  
Data Slicer Positive Input  
15uA  
100  
3k  
19  
80µA  
20  
SLN  
Data Slicer Negative Input  
5uA  
10k  
20  
21  
OPP  
OpAmp Noninverting Input  
5uA  
200  
21  
Wireless Components  
3 - 6  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
22  
23  
24  
FFB  
Data Filter Feedback Pin  
AGC Threshold Input  
3V Reference Output  
5uA  
100k  
22  
THRES  
5uA  
10k  
23  
3VOUT  
24  
20k  
3.1V  
25  
DATA  
Data Output  
500  
25  
40k  
Wireless Components  
3 - 7  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
26  
PDO  
Peak Detector Output  
26  
446k  
27  
PDWN  
Power Down Input  
27  
220k  
220k  
28  
CRST2  
External Crystal Connector 2  
4.15V  
28  
50uA  
Wireless Components  
3 - 8  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
3.3 Functional Block Diagram  
VCC  
IF  
Filter  
MSEL  
H=ASK  
L=FSK  
MI  
FFB  
LNO  
MIX  
9
IFO  
12  
LIM  
LIMX  
18  
OPP  
SLP  
19  
SLN  
20  
22  
21  
6
8
17  
15  
16  
25  
SSEL  
DATA  
Logic  
CM  
-
LNI  
+
3
4
LNA  
RF  
CP  
+
-
-
FSK  
PLL Demod  
FSK  
ASK  
+
+
LIMITER  
DATA-  
SLICER  
-
+
OP  
-
TAGC  
TDA 5221  
PEAK  
DETECTOR  
PDO  
26  
23 THRES  
OTA  
U REF  
3VOUT  
24  
AGC  
Reference  
: 128  
: 129  
Φ
DET  
CRYSTAL  
OSC  
: 2  
VCO  
: 2  
VCC  
14  
13  
Bandgap  
Reference  
Loop  
Filter  
DGND  
11  
1
28  
27  
2,7  
5,10  
VCC AGND  
PDWN  
FSEL  
Crystal  
Functional_diagram_5221.wmf  
Figure 3-2  
Main Block Diagram  
3.4 Functional Blocks  
3.4.1 Low Noise Amplifier (LNA)  
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The  
gain figure is determined by the external matching networks situated ahead of  
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX  
(Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current  
consumption is 500µA. The gain can be reduced by approximately 18dB. The  
switching point of this AGC action can be determined externally by applying a  
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally  
with the received signal (RSSI) level generated by the limiter circuitry. In case  
that the RSSI level is higher than the threshold voltage the LNA gain is reduced  
and vice versa. The threshold voltage can be generated by attaching a voltage  
divider between the 3VOUT pin (Pin 24) which provides a temperature stable  
3V output generated from the internal bandgap voltage and the THRES pin as  
described in Section 4.1. The time constant of the AGC action can be deter-  
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen  
along with the appropriate threshold voltage according to the intended operat-  
Wireless Components  
3 - 9  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
ing case and interference scenario to be expected during operation. The opti-  
mum choice of AGC time constant and the threshold voltage is described in  
Section 4.1.  
3.4.2 Mixer  
The Double Balanced Mixer downconverts the input frequency (RF) in the  
range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-  
tage gain of approximately 21dB by utilising either high- or low-side injection of  
the local oscillator signal. In case the mixer is interfaced only single-ended, the  
unused mixer input has to be tied to ground via a capacitor. The mixer is fol-  
lowed by a low pass filter with a corner frequency of 20MHz in order to suppress  
RF signals to appear at the IF output (IFO pin). The IF output is internally con-  
sisting of an emitter follower that has a source impedance of approximately  
330=to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter  
without additional matching circuitry.  
3.4.3 PLL Synthesizer  
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous  
divider chain, a phase detector with charge pump and a loop filter and is fully  
implemented on-chip. The VCO is including spiral inductors and varactor  
diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO  
was designed to guarantee over production spread and the specified tempera-  
ture range a receive frequency range between 300 and 340 MHz depending on  
whether high- or low-side injection of the local oscillator is used. The oscillator  
signal is fed both to the synthesiser divider chain and to a divider that is dividing  
the signal by 2 before it is applied to the downconverting mixer. Local oscillator  
high side injection has to be used for receive frequencies between approxi-  
mately 300 and 320 MHz, low side injection for receive frequencies between  
320 and 340MHz - see also Section 4.4..  
3.4.4 Crystal Oscillator  
The calculation of the value of the necessary quartz load capacitance is shown  
in Section 4.3, the quartz frequency calculation is explained in Section 4.4.  
3.4.5 Limiter  
The Limiter is an AC coupled multistage amplifier with a cumulative gain of  
approximately 80 dB that has a bandpass-characteristic centred around  
10.7 MHz. It has a typical input impedance of 330 =to allow for easy interfacing  
to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal  
Strength Indicator (RSSI) generator which produces a DC voltage that is  
Wireless Components  
3 - 10  
Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
directly proportional to the input signal level as can be seen in Figure 4-2. This  
signal is used to demodulate ASK-modulated receive signals in the subsequent  
baseband circuitry. The RSSI output is applied to the modulation format switch,  
to the Peak Detector input and to the AGC circuitry.  
In order to demodulate ASK signals the MSEL pin has to be in its High-state  
as described in the next chapter.  
3.4.6 FSK Demodulator  
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is  
contained fully on chip. The Limiter output differential signal is fed to the linear  
phase detector as is the output of the 10.7 MHz center frequency VCO. The  
demodulator gain is typically 140µV/kHz. The passive loop filter output that is  
comprised fully on chip is fed to both the VCO and the modulation format switch  
described in more detail below. This signal is representing the demodulated sig-  
nal with low frequencies applied to the demodulator demodulated to logic ones  
and high frequencies demodulated to logic zeroes. However this is only valid in  
case the local oscillator is low-side injected to the mixer which is applicable to  
receive frequencies above 330MHz (e.g. 345MHz). In case of receive frequen-  
cies below 330MHz (e.g.315MHz) high frequencies are demodulated as logical  
ones due to a sign inversion in the downconversion mixing process. See also  
Section 4.4.  
The modulation format switch is actually a switchable amplifier with an AC gain  
of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table.  
This gain was chosen to facilitate detection in the subsequent circuits. The DC  
gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset  
produced by the demodulator in case of large frequency offsets of the IF signal.  
The resulting frequency characteristic and details on the principle of operation  
of the switch are described in Section 4.6.  
Table 3-2 MSEL Pin Operating States  
MSEL  
Modulation Format  
Open  
ASK  
FSK  
Shorted to ground  
The demodulator circuit is switched off in case of reception of ASK signals.  
3.4.7 Data Filter  
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a  
voltage follower and two 100k= on-chip resistors. Along with two external  
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the  
capacitor values is described in Section 4.2.  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Functional Description  
3.4.8 Data Slicer  
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows  
for a maximum receive data rate of up to 100kBaud. The maximum achievable  
data rate also depends on the IF Filter bandwidth and the local oscillator toler-  
ance values. Both inputs are accessible. The output delivers a digital data sig-  
nal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold  
on pin 20 its generated by a RC-term. In ASK-mode alternatively a scaled value  
of the voltage at the PDO-output (approx. 87%) can be used as the slicer-  
threshold. The data slicer threshold generation alternatives are described in  
more detail in Section 4.5.  
3.4.9 Peak Detector  
The peak detector generates a DC voltage which is proportional to the peak  
value of the receive data signal. A capacitor is necessary. The input is con-  
nected to the output of the RSSI-output of the Limiter, the output is connected  
to the PDO pin (Pin 26). This output can be used as an indicator for the received  
signal strength to use in wake-up circuits and as a reference for the data slicer  
in ASK mode. Note that the RSSI level is also output in case of FSK mode.  
3.4.10 Bandgap Reference Circuitry  
A Bandgap Reference Circuit provides a temperature stable reference voltage  
for the device. A power down mode is available to switch off all subcircuits which  
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-  
ply current drawn in this case is typically 50nA.  
Table 3-3 PDWN Pin Operating States  
PDWN  
Operating State  
Powerdown Mode  
Receiver On  
Open or tied to ground  
Tied to Vs  
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Target Specification, October 2001  
4
Applications  
Contents of this Chapter  
4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . 4-2  
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4  
4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5  
4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6  
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7  
4.6 ASK/FSK Datapatch Functional Description. . . . . . . . . . . . . . . . . . . . 4-8  
4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11  
TDA 5221  
preliminary  
Applications  
4.1 Choice of LNA Threshold Voltage and Time Constant  
In the following figure the internal circuitry of the LNA automatic gain control is  
shown.  
R1  
R2  
U
th re s h old  
23  
Pins:  
24  
RSSI (0.8 - 2.8V)  
20k  
OTA  
VCC  
+3.1V  
I
LNA  
load  
Gain control  
voltage  
RSSI > Uthres hold: Iload=4.2µA  
RSSI < Uthres hold: Iload= -1.5µA  
4
Uc :< 2.6V : Gain high  
Uc :> 2.6V : Gain low  
UC  
C
Uc max = VCC - 0.7V  
Uc min = 1.67V  
LNA_autom.wmf  
Figure 4-1  
LNA Automatic Gain Control Circuitry  
The LNA automatic gain control circuitry consists of an operational transimped-  
ance amplifier that is used to compare the received signal strength signal  
(RSSI) generated by the Limiter with an externally provided threshold voltage  
Uthres. As shown in the following figure the threshold voltage can have any  
value between approximately 0.8 and 2.8V to provide a switching point within  
the receive signal dynamic range.  
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage  
can be generated by attaching a voltage divider between the 3VOUT pin  
(Pin 24) which provides a temperature stable 3V output generated from the  
internal bandgap voltage and the THRES pin. If the RSSI level generated by the  
Limiter is higher than Uthres, the OTA generates a positive current Iload. This  
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a  
negative current. These currents do not have the same values in order to  
achieve a fast-attack and slow-release action of the AGC and are used to  
charge an external capacitor which finally generates the LNA gain control volt-  
age.  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
3
2.5  
2
RSSI Level  
1.5  
1
0.5  
0
-120  
-110  
-100  
-90  
-80  
-70  
-60  
-50  
-40  
-30  
Input Level at LNA Input [dBm]  
RSSI-AGC.wmf  
Figure 4-2  
RSSI Level and Permissive AGC Threshold Levels  
The switching point should be chosen according to the intended operating sce-  
nario. The determination of the optimum point is described in the accompanying  
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.  
It should be noted that the output of the 3VOUT pin is capable of driving up to  
50µA, but that the THRES pin input current is only in the region of 40nA. As the  
current drawn out of the 3VOUT pin is directly related to the receiver power con-  
sumption, the power divider resistors should have high impedance values. The  
sum of R1 and R2 has to be 600kin order to yield 3V at the 3VOUT pin. R1  
can thus be chosen as 240k, R2 as 360kto yield an overall 3VOUT output  
current of 5µA1 and a threshold voltage of 1.8V  
Note: If the LNA gain shall be kept in either high or low gain mode this has to  
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve  
high gain mode operation, a voltage higher than 2.8V shall be applied to the  
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain  
mode operation a voltage lower than 0.7V shall be applied to the THRES, such  
as a short to ground.  
As stated above the capacitor connected to the TAGC pin is generating the gain  
control voltage of the LNA due to the charging and discharging currents of the  
OTA and thus is also responsible for the AGC time constant. As the charging  
and discharging currents are not equal two different time constants will result.  
The time constant corresponding to the charging process of the capacitor shall  
be chosen according to the data rate. According to measurements performed  
at Infineon the capacitor value should be greater than 47nF.  
1. note the 20kresistor in series with the 3.1V internal voltage source  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
4.2 Data Filter Design  
Utilising the on-board voltage follower and the two 100kon-chip resistors a  
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-  
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as  
depicted in the following figure and described in the following formulas1.  
C1  
22  
C2  
21  
Pins:  
19  
R
R
100k  
100k  
Filter_Design.wmf  
Figure 4-3  
(1)(2)  
Data Filter Design  
b
2Q b  
R2Πf3dB  
C2 = ---------------------------  
4QRΠf3dB  
C1 = ----------------------  
with  
b
a
(3)the quality factor of the poles  
Q = ------  
where  
in case of a Bessel filter a = 1.3617, b = 0.618  
and thus Q = 0.577  
and in case of a Butterworth filtera = 1.414, b = 1  
and thus Q = 0.71  
Example: Butterworth filter with f3dB = 5kHz and R = 100k:  
C1 = 450pF, C2 = 225pF  
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
4.3 Quartz Load Capacitance Calculation  
The value of the capacitor necessary to achieve that the quartz oscillator is  
operating at the intended frequency is determined by the reactive part of the  
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the  
quartz specifications given by the quartz manufacturer.  
CS  
Pin 28  
Input  
impedance  
Crystal  
Z1-28  
TDA5221  
Pin 1  
Quartz_load_5221.wmf  
Figure 4-4  
Determination of Series Capacitance Value for the Quartz Oscillator  
Crystal specified with load capacitance  
1
CS =  
1
+ 2π f X L  
Cl  
with Cl the load capacitance (refer to the quartz crystal specification).  
Example:  
10.18 MHz: CL = 12 pF  
XL=870 Ω  
CS = 7.2 pF  
This value may be obtained by putting two capacitors in series to the quartz,  
such as 18pF and 22pF in the 5.1MHz case and 18pF and 12pF in the 10.2MHz  
case.  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
4.4 Quartz Frequency Calculation  
As described in Section 3.4.3 the operating range of the on-chip VCO is wide  
enough to guarantee a receive frequency range between 300 and 340MHz. The  
VCO signal is divided by 2 before applied to the mixer . This local oscillator sig-  
nal can be used to downconvert the RF signals both with high- or low-side injec-  
tion at the mixer. High-side injection of the local oscillator has to be used for  
receive frequencies between 300 and 320 MHz. In this case the local oscillator  
frequency is calculated by adding the IF frequency (10.7 MHz) to the RF fre-  
quency. In this case the higher frequency of a FSK-modulated signal is  
demodulated as a logical one (high).  
Low-side injection has to be used for receive frequencies between 320 and  
340 MHz. The local oscillator frequency is calculated by subtracting the IF fre-  
quency (10.7 MHz) from the RF frequency then. Please note that in this case  
sign-inversion occurs and the higher frequency of a FSK-modulated signal is  
demodulated as a logical zero (low). The overall division ratios in the PLL are  
32 or 32.25 depending on whether the FSEL-pin is left open or tied to ground.  
Therefore the quartz frequency may be calculated by using the following for-  
mula:  
ƒQU = (ƒRF ± 10.7) / r  
with ƒRF receive frequency  
ƒLO local oscillator (PLL) frequency (ƒRF ± 10.7)  
ƒQU quartz oscillator frequency  
r
ratio of local oscillator (PLL) frequency and quartz frequency as  
shown in the subsequent table  
Table 4-1 PLL Division Ratio Dependence on States of CSEL  
FSEL  
High  
Low  
Ratio r = (fLO/fQU)  
32  
32.25  
This yields the following examples:  
FSEL is Low:  
fQU  
=
(
318.55MHz+10.7MHz /32.25 =10.209375MHz  
)
FSEL is High:  
fQU  
=
(
316MHz +10.7MHz  
)
/ 32 =10.209375 MHz  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
4.5 Data Slicer Threshold Generation  
The threshold of the data slicer can be generated using an external R-C inte-  
grator as shown in Figure 4-5. The cut-off frequency of the R-C integrator has  
to be lower than the lowest frequency appearing in the data signal. In order to  
keep distortion low, the minimum value for R is 20k.  
R
C
data out  
Pins:  
19  
20  
25  
Uthreshold  
CM  
data  
filter  
data slicer  
Data_slice1.wmf  
Figure 4-5  
Data Slicer Threshold Generation with External R-C Integrator  
In case of ASK operation another possibility for threshold generation is to use  
the peak detector in connection with an internal resistive divider and one capac-  
itor as shown in the following figure. The component values are depending on  
the coding scheme and the protocol used.  
C
data out  
Pins:  
26  
25  
peak detector  
56k  
390k  
data slicer  
CP  
Uthreshold  
data  
filter  
Data_slice2.wmf  
Figure 4-6  
Data Slicer Threshold Generation Utilising the Peak Detector  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
4.6 ASK/FSK Datapatch Functional Description  
The TDA5221 is containing an ASK/FSK switch which can be controlled via  
Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that  
are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of  
the FSK amplifier in order to achieve an appropriate demodulation gain charac-  
teristic. In order to compensate for the DC-offset generated especially in case  
of the FSK PLL demodulator there is a feedback connection between the  
threshold voltage of the bit slicer comparator (Pin 20) to the negative input of  
the FSK switch amplifier.  
In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87%  
of the peak-detector output-voltage at Pin 26 (PDO) can be used as the slicer-  
reference level. The selection between these modes is controlled by Pin 16  
(SSEL). This is shown in the following figure.  
MSEL  
15  
H=ASK  
L=FSK  
PEAK  
DETECTOR  
PDO  
from RSSI Gen  
(ASK signal)  
26  
R=56k  
ASK/FSK Switch  
C=100 nF  
R=390k  
Data Filter  
Comp  
R1=100k  
R2=100k  
-
-
FSK PLL Demodulator  
0.18 mV/kHz  
+
+
CP  
CM  
ASK  
FSK  
v = 1  
25  
DATA Out  
+
-
+
-
H=CP  
L=CM  
R3=300k  
typ. 2 V  
1.5 V......2.5 V  
R4=30k  
22  
21  
19  
20  
16  
ASK mode: v=1  
FSK mode: v=11  
FFB  
C2  
OOP  
SLP  
SLN  
SSEL  
R
C1  
C
ask_fsk_datapath.WMF  
Figure 4-7  
ASK/FSK mode datapath  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
4.6.1 FSK Mode  
The FSK datapath has a bandpass characterisitc due to the feedback shown  
above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is  
determined by the external RC-combination. The upper cutoff frequency f3 is  
determined by the data filter bandwidth.  
The demodulation gain of the FSK PLL demodulator is 140µV/kHz. This gain is  
increased by the gain v of the FSK switch, which is 11. Therefore the resulting  
dynamic gain of this circuit is 1.5mV/kHz within the bandpass. The gain for the  
DC content of FSK signal remains at 140µV/kHz. The cutoff frequencies of the  
bandpass have to be chosen such that the spectrum of the data signal is influ-  
enced in an acceptable amount.  
In case that the user data is containing long sequences of logical zeroes the  
effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset  
voltage inherent at the negative input of the slicer comparator (Pin20) is used.  
The comparator has no hysteresis built in.  
This offset voltage is generated by the bias current of the negative input of the  
comparator (i.e. 20nA) running over the external resistor R. This voltage raises  
the voltage appearing at pin 20 (e.g. 1mV with R = 100k). In order to obtain  
benefit of this asymmetrical offset for the demodulation of long zeros the lower  
of the two FSK frequencies should be chosen in the transmitter as the zero-  
symbol frequency.  
In the following figure the shape of the above mentioned bandpass is shown.  
gain (pin19)  
v
v-3dB  
20dB/dec  
-40dB/dec  
3dB  
0dB  
f
DC  
f1  
f2  
f3  
0.18mV/kHz  
2mV/kHz  
frequenzgang.WMF  
Figure 4-8  
Frequency characterstic in case of FSK mode  
The cutoff frequencies are calculated with the following formulas:  
1
f1 =  
R 330kΩ  
2π  
C
R + 330kΩ  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
f2 = v f1 =11 f1  
f3 = f3dB  
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.  
Example:  
R = 100kΩ,=C = 47nF  
This leads tof1 = 44Hz and f2 = 485Hz  
4.6.2 ASK Mode  
In case the receiver is operated in ASK mode the datapath frequency charac-  
tersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff  
frequency is determined by the external capacitors C12 and C14 and the inter-  
nal 100k resistors as described in Section 4.2  
0dB  
-3dB  
-40dB/dec  
f
f3dB  
freq_ask.WMF  
Figure 4-9  
Frequency charcteristic in case of ASK mode  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
4.7 Principle of the Precharge Circuit  
In case the data slicer threshold shall be generated with an external RC network  
as described in Section 4.5 it is necessary to use large values for the capacitor  
C attached to the SLN pin (pin 20) in order to achieve long time constants. This  
results also from the fact that the choice of the value for R connected between  
the SLP and SLN pins (pins 19 and 20) is limited by the 330kresistor appear-  
ing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value  
of 100kleads to a voltage offset of 1mv at the comparator input as described  
in Section 4.6.1. The resulting startup time constant τ1 can be calculated with:  
τ1 = (R // 330k) · C  
In case R is chosen to be 100kand C is chosen as 47nF this leads to  
τ1 = (100k// 330k) · 47nF = 77k· 47nF = 3.6ms  
When the device is turned on this time constant dominates the time necessary  
for the device to be able to demodulate data properly. In the powerdown mode  
the capacitor is only discharged by leakage currents.  
In order to reduce the turn-on time in the presence of large values of C a pre-  
charge circuit was included in the TDA5221 as shown in the following figure.  
C2  
R1+R2=600k  
R2  
R1  
C
R
U
thres hold  
20  
19  
24  
23  
Iload  
Uc  
ASK/FSK Switch  
Uc>Us Uc<Us  
DataFilter  
-
U2  
+
0 / 240uA  
OTA  
Us  
U2<2.4V : I=240uA  
U2>2.4V: I=0  
-
20k  
+2.4V  
+3.1V  
precharge.WMF  
Figure 4-10 Principle of the precharge circuit  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
This circuit charges the capacitor C with an inrush current Iload of typically  
220µA for a duration of T2 until the voltage Uc appearing on the capacitor is  
equal to the voltage Us at the input of the data filter. This voltage is limited to  
2.5V. As soon as these voltages are equal or the duration T2 is exceeded the  
precharge circuit is disabled.  
τ2 is the time constant of the charging process of C which can be calculated as  
τ2 =20k· C2  
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can  
then be calculated according to the following formula:  
æ
ç
ç
ç
ç
è
ö
1
T2 = τ 2 ln  
τ 2 1.6  
2.4V  
3V  
1 −  
The voltage transient during the charging of C2 is shown in the following figure:  
U2  
3V  
2.4V  
T2  
2
e-fkt1.WMF  
Figure 4-11 Voltage appearing on C2 during precharging process  
The voltage appearing on the capacitor C connected to pin 20 is shown in the  
following figure. It can be seen that due to the fact that it is charged by a con-  
stant current source it exhibits is a linear increase in voltage which is limited to  
USmax = 2.5V which is also the approximate operating point of the data filter  
input. The time constant appearing in this case can be denoted as T3, which  
can be calculated with  
USmax  
C
2,5V  
220µA  
----------------  
T3 = ----------------------- =  
C
220µA  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Applications  
Uc  
Us  
T3  
e-Fkt2.WMF  
Figure 4-12 Voltage transient on capacitor C attached to pin 20  
As an example the choice of C2 = 22nF and C = 47nF yields  
τ2 = 0.44ms  
T2 = 0.71ms  
T3 = 0.53ms  
This means that in this case the inrush current could flow for a duration of  
0.64ms but stops already after 0.49ms when the USmax limit has been reached.  
T3 should always be chosen to be shorter than T2.  
It has to be noted finally that during the turn-on duration T2 the overall device  
power consumption is increased by the 220µA needed to charge C.  
The precharge circuit may be disabled if C2 is not equipped. This yields a T2  
close to zero. Note that the sum of R4 and R5 has to be 600kin order to pro-  
duce 3V at the THRES pin as this voltage is internally used also as the refer-  
ence for the FSK demodulator.  
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Target Specification, October 2001  
5
Reference  
Contents of this Chapter  
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
TDA 5221  
preliminary  
Reference  
5.1 Electrical Data  
5.1.1 Absolute Maximum Ratings  
WARNING  
The maximum ratings may not be exceeded under any circumstances, not even  
momentarily and individually, as permanent damage to the IC will result.  
Table 5-1 Absolute Maximum Ratings, Ambient temperature T  
=-40°C ... + 105°C  
AMB  
#
Parameter  
Symbol  
Limit Values  
Unit  
Remarks  
min  
-0.3  
max  
5.5  
1
2
3
4
5
Supply Voltage  
Vs  
Tj  
V
°C  
Junction Temperature  
Storage Temperature  
Thermal Resistance  
-40  
-40  
+150  
+125  
114  
Ts  
°C  
RthJA  
VESD  
K/W  
ESD integrity, all pins excl. Pins 1,3, 6, 28  
ESD integrity Pins 1,3,6,28  
+2  
+1.5  
kV  
kV  
HBM  
according to  
MIL STD  
883D,  
method  
3015.7  
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Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
5.1.2 Operating Range  
Within the operational range the IC operates as explained in the circuit descrip-  
tion. The AC/DC characteristic limits are not guaranteed. Currents flowing into  
the device are denoted as positive currents and v.v.  
Supply voltage: VCC = 4.5V .. 5.5V  
Table 5-2 Operating Range, Ambient temperature T  
= -40°C ... + 105°C  
AMB  
#
1
2
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
max  
Supply Current  
I
t.b.d.  
t.b.d.  
t.b.d.  
t.b.d.  
mA  
mA  
f
f
= 315MHz, FSK Mode  
= 315MHz, ASK Mode  
SF  
RF  
RF  
I
SA  
Receiver Input Level  
ASK  
FSK, frequ. dev. ± 50kHz  
@ source impedance 50,  
BER 2E-3, average power  
level, Manchester encoded  
datarate 4kBit, 280kHz IF  
Bandwidth  
RFin  
-110  
-102  
-13  
-13  
dBm  
dBm  
3
4
5
LNI Input Frequency  
MI/X Input Frequency  
fRF  
fMI  
300  
300  
340  
340  
MHz  
MHz  
3dB IF Frequency Range  
ASK  
FSK  
fIF -3dB  
5
10.4  
23  
11  
MHz  
6
7
8
Powerdown Mode On  
Powerdown Mode Off  
PWDNON  
PWDNOFF  
VTHRES  
0
2
0.8  
V
V
V
V
S
S
Gain Control Voltage,  
LNA high gain state  
2.8  
V
9
Gain Control Voltage,  
LNA low gain state  
VTHRES  
0
0.7  
V
This value is guaranteed by design.  
Wireless Components  
5 - 3  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
5.1.3 AC/DC Characteristics at TAMB = 25°C  
AC/DC characteristics involve the spread of values guaranteed within the spe-  
cified voltage and ambient temperature range. Typical characteristics are the  
median of the production. Currents flowing into the device are denoted as po-  
sitive currents and vice versa.  
The device performance parameters marked with were measured on an  
Infineon evaluation board as described in Section 5.2.  
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
Supply  
Supply Current  
1
Supply current,  
standby mode  
IS PDWN  
50  
t.b.d.  
t.b.d.  
nA  
Pin 27 (PDWN)  
open or tied to 0 V  
2
Supply current, device  
operating in FSK mode  
I
t.b.d.  
t.b.d.  
6.4  
mA  
Pin 11 (FSEL)  
open, Pin 15  
(MSEL) tied to GND  
SF  
3
Supply current, device  
operating in ASK mode  
I
5.6  
t.b.d.  
mA  
Pin 11 (FSEL)  
open, Pin 15  
(MSEL) open  
SA  
LNA  
Signal Input LNI (PIN 3), V  
> 2.8V, high gain mode  
THRES  
1
Average Power Level  
at BER = 2E-3  
(Sensitivity)  
RFin  
-113  
dBm Manchester  
encoded datarate  
4kBit, 280kHz IF  
Bandwidth  
2
Average Power Level  
at BER = 2E-3  
RFin  
-105  
dBm Manchester enc.  
datarate 4kBit,  
(Sensitivity) FSK  
280kHz IF Bandw.,  
± 50kHz pk. dev.  
3
4
5
Input impedance,  
S
0.895 / -25.5 deg  
11 LNA  
f
= 315 MHz  
RF  
Input level @ 1dB C.P.  
fRF=315 MHz  
P1dB  
IIP3  
-14  
-10  
dBm  
LNA  
Input 3rd order intercept  
LNA  
LNI  
dBm  
dBm  
fin = 315 & 317MHz  
point f = 315 MHz  
RF  
6
LO signal feedthrough  
at antenna port  
LO  
-119  
Signal Output LNO (PIN 6), V  
> 2.8V, high gain mode  
THRES  
1
2
Gain f = 315 MHz  
RF  
S
1.577 / 150.3 deg  
0.897 / -10.3 deg  
21 LNA  
Output impedance,  
S
22 LNA  
f
= 315 MHz  
RF  
Wireless Components  
5 - 4  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
21  
max  
3
4
Voltage Gain Antenna  
G
dB  
dB  
AntMI  
to MI f = 315 MHz  
RF  
Noise Figure  
NF  
2
excluding matching  
network loss - see  
Appendix  
LNA  
Signal Input LNI, V  
= GND, low gain mode  
THRES  
1
2
3
Input impedance,  
= 315 MHz  
S
0.918 / -25.2 deg  
11 LNA  
f
RF  
Input level @ 1dB C. P.  
= 315 MHz  
P1dB  
-7  
dBm matched input  
LNA  
LNA  
f
RF  
Input 3rd order intercept  
point f = 315 MHz  
IIP3  
-13  
dBm fin = 315 & 317MHz  
RF  
Signal Output LNO, V  
= GND, low gain mode  
THRES  
1
2
Gain f = 315 MHz  
S
0.193 / 153.7 deg  
RF  
21 LNA  
22 LNA  
Output impedance,  
S
0.907 / -10.5 deg  
f
= 315 MHz  
RF  
3
Voltage Gain Antenna  
G
2
dB  
AntMI  
to MI f = 315 MHz  
RF  
Signal 3VOUT (PIN 24)  
1
2
Output voltage  
Current out  
V
2.9  
-3  
3.1  
-5  
3.3  
V
3VOUT Pin open  
see Section 4.1  
3VOUT  
I
-10  
µA  
3VOUT  
Signal THRES (PIN 23)  
1
2
3
4
Input Voltage range  
LNA low gain mode  
LNA high gain mode  
Current in  
V
V
V
0
0
V
S
V
V
see Section 4.1  
THRES  
THRES  
THRES  
0.3  
3.3  
V
S
V
or shorted to VCC  
ITHRES_in  
5
nA  
Signal TAGC (PIN 4)  
1
Current out,  
LNA low gain state  
ITAGC_out  
-3.6  
1
-4.2  
1.6  
-5  
µA  
µA  
RSSI > V  
RSSI < V  
THRES  
2
Current in,  
I
2.2  
TAGC_in  
THRES  
LNA high gain state  
MIXER  
Signal Input MI/MIX (PINS 8/9)  
1
Input impedance,  
= 315 MHz  
S
0.954 / -10.9 deg  
-25  
11 MIX  
f
RF  
Input 3rd order intercept  
point  
MIX  
2
IIP3  
dBm  
Wireless Components  
5 - 5  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
Signal Output IFO (PIN 12)  
1
2
Output impedance  
Z
330  
21  
IFO  
Conversion Voltage  
G
dB  
MIX  
Gain f = 315 MHz  
RF  
3
4
Noise Figure, SSB  
(~DSB NF+3dB)  
NF  
13  
46  
dB  
dB  
MIX  
RF to IF isolation  
A
RF-IF  
LIMITER  
Signal Input LIM/X (PINS 17/18)  
1
2
3
4
Input Impedance  
RSSI dynamic range  
RSSI linearity  
Z
264  
60  
330  
396  
80  
dB  
LIM  
DR  
LIN  
f
RSSI  
RSSI  
dB  
±1  
Operating frequency  
(3dB points)  
5
10.7  
23  
MHz  
LIM  
DATA FILTER  
1
2
Useable bandwidth  
BW  
100  
1
kHz  
V
BB FILT  
RSSI Level at Data Fil-  
ter Output SLP,  
RSSI  
0.3  
1.8  
LNA in high gain  
mode  
low  
RF =-103dBm  
IN  
3
RSSI Level at Data Fil-  
ter Output SLP,  
RSSI  
3
V
LNA in high gain  
mode  
high  
RF =-30dBm  
IN  
SLICER  
Signal Output DATA (PIN 25)  
1
Maximum Datarate  
DR  
100  
0.1  
kBps NRZ, 20pF capaci-  
tive loading  
max  
2
3
LOW output voltage  
HIGH output voltage  
V
V
0
V
V
SLIC_L  
V -  
S
V -1V  
S
V -  
S
SLIC_H  
1.3V  
-100  
0.7V  
-300  
Slicer, Negative Input (PIN 20)  
Precharge Current Out  
1
I
-220  
µA  
see Section 4.7  
PCH_SLN  
Wireless Components  
5 - 6  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
PEAK DETECTOR  
Signal Output PDO (PIN 26)  
1
2
Load current  
I
-600  
-950  
446  
-1300  
t.b.d.  
µA  
load  
Internal resistive load  
R
t.b.d.  
kΩ  
CRYSTAL OSCILLATOR  
Signals CRSTL1, CRISTL 2, (PINS 1/28)  
1
Operating frequency  
f
t.b.d.  
11  
MHz fundamental mode,  
series resonance  
CRSTL  
2
Input Impedance  
@ ~10MHz  
Z
-700 +  
j 865  
1-28  
3
Serial Capacity  
@ ~10MHz  
C
=C1  
7.2  
pF  
S10  
ASK/FSK Signal Switch  
Signal MSEL (PIN 15)  
1
2
3
ASK Mode  
FSK Mode  
V
1.4  
0
4
V
V
or open  
MSEL  
V
I
0.2  
or tied to ground  
MSEL tied to GND  
MSEL  
Input Bias Current  
MSEL  
t.b.d.  
-11  
t.b.d.  
µA  
MSEL  
FSK DEMODULATOR  
1
Demodulation Gain  
G
85  
140  
225  
µV/  
FMDEM  
kHz  
2
Useable IF Bandwidth  
BW  
10.2  
10.7  
11.2  
MHz  
IFPLL  
POWER DOWN MODE  
Signal PDWN (PIN 27)  
1
2
3
Powerdown Mode On  
Powerdown Mode Off  
PWDN  
0
0.8  
V
V
ON  
PWDN  
I
2.8  
V
S
Off  
Input bias current  
PDWN  
19  
µA  
Power On Mode  
PDWN  
4
Start-up Time until valid  
IF signal is detected  
T
1
ms  
SU  
PLL DIVIDER  
Signal FSEL (PIN 11)  
1
2
Overal divison ratio 32  
V
1.4  
0
4
V
V
or open  
FSEL  
Overal division ratio  
32.25  
V
0.2  
or tied to GND  
FSEL  
3
Input bias current FSEL  
I
t.b.d.  
-11  
t.b.d.  
µA  
FSEL tied to GND  
FSEL  
Wireless Components  
5 - 7  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
DATA-SLICER REFERENCE-LEVEL  
Signal SSEL (PIN 16), ASK-Mode  
1
Slicer-Reference is  
voltage at Pin 20 (SLN)  
V
1.4  
0
4
V
V
or open  
SSEL  
2
Slicer-Reference is  
V
0.2  
SSEL  
approx. 87% of the volt-  
age at Pin 26 (PDO)  
3
Input bias current  
SSEL  
I
-3  
-5  
-7  
µA  
SSEL tied to GND  
SSEL  
Measured only in lab.  
Wireless Components  
5 - 8  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
5.1.4 AC/DC Characteristics at TAMB = -40 to 105°C  
Currents flowing into the device are denoted as positive currents and vice  
versa.  
Table 5-4 AC/DC Characteristics with T  
= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V  
AMB  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
Supply  
Supply Current  
1
Supply current,  
standby mode  
IS PDWN  
50  
t.b.d.  
t.b.d.  
nA  
Pin 27 (PDWN)  
open or tied to 0 V  
2
Supply current, device  
operating in FSK mode  
I
t.b.d.  
t.b.d.  
6.4  
mA  
Pin 11 (FSEL) tied  
to GND, Pin 15  
(MSEL) tied to GND  
SF  
3
Supply current, device  
operating in ASK mode  
I
5.6  
t.b.d.  
mA  
Pin 11 (FSEL)  
open, Pin 15  
(MSEL) open  
SA  
Signal 3VOUT (PIN 24)  
1
2
Output voltage  
Current out  
V
2.9  
-3  
3.1  
-5  
3.3  
-10  
V
3VOUT Pin open  
see Section 4.1  
3VOUT  
I
µA  
3VOUT  
Signal THRES (PIN 23)  
1
2
3
4
Input Voltage range  
LNA low gain mode  
LNA high gain mode  
Current in  
V
0
0
3
V -1V  
S
V
V
see Section 4.1  
THRES  
V
V
0.3  
THRES  
THRES  
V
S
V
or shorted to Pin 24  
ITHRES_in  
5
nA  
Signal TAGC (PIN 4)  
1
Current out,  
LNA low gain state  
ITAGC_out  
-1  
-4.2  
1.5  
-8  
5
µA  
µA  
RSSI > V  
RSSI < V  
THRES  
2
Current in, LNA high  
gain state  
V
0.5  
TAGC_in  
THRES  
MIXER  
Conversion Voltage  
Gain f = 315 MHz  
1
G
+19  
dB  
MIX  
RF  
LIMITER  
Signal Input LIM/X (PINS 17/18)  
1
2
RSSI dynamic range  
DR  
60  
80  
1
dB  
V
RSSI  
RSSI Level at Data Fil-  
ter Output SLP,  
RSSI  
0.3  
LNA in high gain  
mode  
low  
RF = -103dBm  
IN  
3
RSSI Level at Data Fil-  
ter Output SLP,  
RSSI  
1.8  
3
V
LNA in high gain  
mode  
high  
RF = -30dBm  
IN  
Wireless Components  
5 - 9  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
Table 5-4 AC/DC Characteristics with T  
= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V  
AMB  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
DATA FILTER  
Slicer, Signal Output DATA (PIN 25)  
1
Maximum Datarate  
DR  
100  
0.1  
kBps NRZ, 20pF capaci-  
tive loading  
max  
2
3
LOW output voltage  
HIGH output voltage  
V
V
0
V
V
SLIC_L  
V -  
S
V -1V  
S
V -  
S
SLIC_H  
1.5V  
-100  
0.5V  
-300  
Slicer, Negative Input (PIN 20)  
Precharge Current Out  
1
I
-220  
µA  
see Section 4.7  
PCH_SLN  
PEAK DETECTOR  
Signal Output PDO (PIN 26)  
1
2
Load current  
I
-400  
t.b.d  
-850  
446  
-1400  
t.b.d.  
µA  
load  
Internal resistive load  
R
kΩ  
CRYSTAL OSCILLATOR  
Signals CRSTL1, CRSTL 2, (PINS 1/28)  
Operating frequency  
1
f
t.b.d.  
11  
MHz  
fundamental mode,  
series resonance  
CRSTL  
ASK/FSK Signal Switch  
Signal MSEL (PIN 15)  
1
2
3
ASK Mode  
V
V
I
1.4  
0
4
V
V
or open  
MSEL  
MSEL  
FSK Mode  
0.2  
Input bias current MSEL  
t.b.d.  
-11  
t.b.d.  
µA  
MSEL tied to GND  
MSEL  
FSK DEMODULATOR  
1
Demodulation Gain  
G
105  
140  
245  
11  
µV/  
kHz  
FMDEM  
2
Useable IF Bandwidth  
BW  
10.4  
10.7  
MHz  
IFPLL  
POWER DOWN MODE  
Signal PDWN (PIN 27)  
1
2
3
Powerdown Mode On  
Powerdown Mode Off  
PWDN  
0
0.8  
V
V
ON  
PWDN  
2.8  
V
S
Off  
Start-up Time until valid  
signal is detected at IF  
T
1
ms  
SU  
PLL DIVIDER  
Signal FSEL (PIN 11)  
1
2
Overal divison ratio 32  
V
V
1.4  
0
4
V
V
or open  
FSEL  
Overal division ratio  
32.25  
0.2  
or tied to GND  
FSEL  
3
Input bias current FSEL  
I
t.b.d.  
-11  
t.b.d.  
µA  
FSEL tied to GND  
FSEL  
Wireless Components  
5 - 10  
Target Specification, October 2001  
TDA 5221  
preliminary  
Reference  
DATA-SLICER REFERENCE-LEVEL  
Signal SSEL (PIN 16), ASK-Mode  
1
Slicer-Reference is volt-  
age at Pin 20 (SLN)  
V
1.4  
0
4
V
V
or open  
SSEL  
2
Slicer-Reference is  
V
0.2  
SSEL  
approx. 87% of the volt-  
age at Pin 26 (PDO)  
3
Input bias current  
SSEL  
I
-3  
-5  
-7  
µA  
SSEL tied to GND  
SSEL  
Wireless Components  
5 - 11  
Target Specification, October 2001  

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