TDM3883 [INFINEON]
IPOL 3 A 采用集成电感的单输出高效率降压稳压器模块;型号: | TDM3883 |
厂家: | Infineon |
描述: | IPOL 3 A 采用集成电感的单输出高效率降压稳压器模块 稳压器 |
文件: | 总38页 (文件大小:1520K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TDM3883
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Optimized Module with inductor included
Micro Sized 2.7 mm x 3.1 mm x 2.3 mm
Continuous 3 A Load Capability
Single Input Voltage Range (4.5 V to 14 V)
800 kHz Switching Frequency
10 µA Supply Current at Shutdown
Enhanced Stability IPOL Engine Stable with Ceramic Capacitors and no External Compensation
Enhanced Light Load Efficiency with Reduced Switching Frequency and Diode Emulation
Forced Continuous Conduction Mode Option
Thermally Compensated Internal Over-Current Protection
Internal Soft-Start, Enable Input , PreBias Start Up, Thermal Shut Down, Power Good Output
Precision Reference Voltage (0.5 V+/-1.0%)
Lead-free, Halogen-free and RoHS6 Compliant
Potential applications
•
•
•
•
•
Server and Computing
Storage and Applications
Communications Infrastructure
General DC-DC Converters.
Distributed Point of Load Power Architectures.
Product validation
Qualified for Industrial Applications
Description
The TDM3883 3 A Point of Load Module is an easy-to-use, fully integrated and highly efficient dc-dc module. The
module’s PWM controller, MOSFETs and inductor make TDMꢀꢁꢁꢀ a space-efficient solution, providing accurate
power delivery. The TDM3883 employs an Enhanced Stability Engine that makes it stable with ceramic
capacitors without compensation.
TDM3883 can operate in Forced Continuous Conduction Mode (FCCM) or can enter Diode Emulation Mode
(DEM) during light loads to save power. With ultra-light loads, TDM3883 can enter a low quiescent current mode
making it ideal for Standby power supplies. The switching frequency is 800 kHz for an optimum solution.
It also features important protection functions, such as Pre-Bias startup, internal Soft-start, hiccup over-current
protection and thermal shutdown to give required system level security in the event of fault conditions.
Final Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Table of contents
Table of contents
Features ........................................................................................................................................ 1
Potential applications..................................................................................................................... 1
Product validation.......................................................................................................................... 1
Description .................................................................................................................................... 1
Table of contents............................................................................................................................ 2
1
Ordering Information ............................................................................................................. 3
2
2.1
2.2
Description............................................................................................................................ 4
PinOut......................................................................................................................................................4
Block Diagram .........................................................................................................................................5
3
Electrical Specifications.......................................................................................................... 6
Absolute Maximum Ratings ....................................................................................................................6
Maximum Operating Conditions.............................................................................................................6
Electrical Characteristics ........................................................................................................................7
Typical Operating Characteristics ..........................................................................................................8
Typical Efficiency Curves.......................................................................................................................11
3.1
3.2
3.3
3.4
3.5
4
Theory of Operation ..............................................................................................................12
Description ............................................................................................................................................12
Enhanced Stability IPOL Engine ...........................................................................................................12
Pseudo-Constant Switching Frequency ...............................................................................................12
Soft-Start ...............................................................................................................................................12
En/FCCM ................................................................................................................................................13
Pre-Bias Start-Up...................................................................................................................................15
Over-Current Protection .......................................................................................................................15
Minimum On-Time and Off-Time..........................................................................................................16
Over-Voltage Protection .......................................................................................................................16
PGood ....................................................................................................................................................17
Over-Temperature Protection ..............................................................................................................18
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
5
Application...........................................................................................................................19
Application Information........................................................................................................................19
Typical Application Diagrams ...............................................................................................................21
Recommended configurations .............................................................................................................23
Typical Operating Waveforms...............................................................................................................24
5.1
5.2
5.3
5.4
6
7
8
Marking Information .............................................................................................................28
Tape and Reel Information .....................................................................................................29
Mechanical Pad Drawing ........................................................................................................30
9
PCB Metal and Component Placement .....................................................................................31
9.1
Reflow guideline....................................................................................................................................31
10
11
12
13
Stencil Design .......................................................................................................................32
Layout Recommendations......................................................................................................33
Environmental Qualifications .................................................................................................35
Evaluation Board and Support Documentation.........................................................................36
Final Datasheet
2 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Ordering Information
1
Ordering Information
Table 1
Ordering Information
Base Part and Number Package Type
Standard Pack Form and Qty
Tape and Reel 2500
Orderable Part Number
TDM3883
PG-LGA-15-1
TDM3883XUMA1
2.7 mm x 3.1 mm
Figure 1
Picture of the Product
Figure 2
TDM3883 Part Number Configuration
Final Datasheet
3 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Description
2
Description
2.1
PinOut
Figure 3
Table 2
Pinout, Numbering and Name of Pins (transparent top view)
Pin Descriptions
Pin #
1
Pin Name Pin Type Pin Description
Input supply for the power stage.
S
PVin
2
AGND
S
Signal ground for the internal reference and control circuitry.
Input bias for the internal control circuitry and driver. Generated by internal LDO via
3
Vcc
S
PVin. A 2.2 µF ceramic capacitor is recommended between Vcc and the Power ground
(PGND).
Over-Current Protection (OCP) limit set point. Three user selectable OCP limits are
available by floating this pin, connecting it to Vcc or connecting it to PGND.
Power Good status pin. Output is an open Drain. Connect a pull up resistor from this pin
to Vcc or an external bias voltage.
4
5
OCSET
PG
I
O
Power Ground. These pins serve as a separate ground for the MOSFET drivers and
should be connected to the system’s power ground plane.
Output voltage. Connect this pin to the load and decoupling capacitors.
6, 8, 14, 15
PGND
S
O
I
7
9
Vout
FB
Output voltage feedback pin. Connect this pin to the output of the regulator via a
resistor divider to set the output voltage.
10
11
Vo
I
Vo sense pin. Connect this pin directly to the output of the regulator to set the on-time.
Multifunction pin: (1) Enable pin to turn the IC on and off. (2) Enable Diode Emulation
(DEM) Mode operation or Forced Continuous Conduction (FCCM) Mode operation.
Supply voltage for the high side driver. Connect this pin to the SW node of the regulator
through a bootstrap capacitor.
En/FCCM
I
12
13
BOOST
SW
I
O
Switch Node. This pin is connected to the integrated output inductor.
Note:
I = Input, O = Output, S = Signal
Final Datasheet
4 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Description
2.2
Block Diagram
Vo
VCC
AGND
PVin
LDO
VCC
Enable
LDrVin
BOOST
PVIN
VREF
INTERNAL REFERENCE
OV
Fault PVin
SOFT
START
SS
PWM
COMP
Fault
ADAPTIVE
ON-TIME
GENERATOR
PWM
+
+
-
HDrVin
HDrv
SET
+
INTERNAL RAMP
+
GATE
DRIVE
LOGIC
Vcc
HDrVin
VOUT
VCC
OV
Fault
OV
DETECTION
SW
OV
POR
LDrVin
LDrv
OV
FB
POR
Fault
FB
EN/
Zcross
THERMAL SHUT-
DOWN
PGND
FCCM
CONTROL
LOGIC
FCCM_EN
Zero Cross
DETECTION
PGND
PG
FCCM
LDrVin
Current Limit
Control
POR
OCSet
The Integrated inductor is 0.82 uH
Figure 4
TDM3883 Block Diagram
Final Datasheet
5 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Electrical Specifications
3
Electrical Specifications
3.1
Absolute Maximum Ratings
Stresses beyond these listed under ꢂAbsolute Maximum Ratingsꢃ may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications are not implied.
Table 3
TDM3883 Absolute Maximum Ratings
-0.3 V to 14 V (dc), 16 V (ac, 2 µs)
-0.3 V to 6 V
PVin, En/FCCM to PGND (Note 2, Note 3)
Vcc to PGND (Note 2)
Boost to PGND (Note 2)
-0.3 V to 22 V(dc), 24 V (ac, 10 ns)
-0.3 V to 16 V (dc), -4 V to 18 V (ac, 10 ns)
-0.3 V to Vcc+0.3 V (Note 1)
-0.3 V to 6 V(dc), 6.5 V (ac, 10 µs)
-0.3 V to 6 V
SW to PGND (Note 2)
Boost to SW
Vo, Fb to AGND (Note 2)
OCSet, PG to AGND (Note 2)
PGND to AGND
-0.3 V to +0.3 V
Thermal Information
Junction to Ambient Thermal Resistance ƟJA
Junction-to-top Thermal characterization parameter ꢄJT
Junction-to-board Thermal characterization parameter ꢄJB
Storage Temperature Range
Junction Temperature Range
43.8 °C/W (Note 13)
3.8 °C/W (Note 13)
18.1 °C/W (Note 13)
-ꢅꢅ °C ≤Ta ≤ ꢆꢇꢅ °C
-ꢈꢉ °C ≤ Tj ≤ ꢆꢇꢅ °C
Note:
1. Must not exceed 6 V.
2. PGND pin and AGND pin are connected together.
3. SW node voltage should not exceed the max voltage defined in Table 3
3.2
Maximum Operating Conditions
Table 4
Maximum Operating Conditions
Definitions
Symbol
Min
4.5
4.4
0.5
0.5
0
Max
14
Units
Input Voltage Range (Note 4, Note 5)
PVin
Vcc
Vo
Vo
Io
Supply Voltage Range (Note 5)
5.5
2.5
5.0
3
V
Output Voltage Range (PVin =4.5 to 8V, Iout =0 to 3A)
Output Voltage Range (PVin =8 to 14V, Iout =0 to 3A)
Continuous Output Current Range
A
Operating Junction Temperature
Tj
-40
125
°C
Note:
4. External Vcc supply voltage is not supported to bypass the internal LDO.
5. Maximum SW node voltage should not exceed the max voltage defined in Table 3.
Final Datasheet
6 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Electrical Specifications
3.3
Electrical Characteristics
Unless otherwise specified, these specifications apply over, 5.5 V < PVin < 14 V, 0 °C < Tj < 125 °C. Typical values
are specified at Ta = 25 °C.
Table 5
Electrical Characteristics
Symbol
Parameter
Power Stage
Top Switch
Conditions
Min
Typ
Max Unit
Rds (on)_Top
Rds (on)_Bot
VBoot –Vsw = 5.2 V, Tj = 25 C
Vcc = 5.2 V, Tj = 25 C
IBoot=10 mA
82
26
106.4
mꢊ
Bottom Switch
33.9
Boot Diode Forward Voltage
Supply Current
200
300
mV
PVin Supply Current (Standby)
PVin Supply Current (Static)
Iin (Standby)
Iin (Static)
Enable low
0.20
0.7
10
2
µA
En = 2 V, No switching
0.5
5
mA
Enable high, PVin = 12 V,
Fs = 800 kHz
PVin Supply Current (Dyn)
Iin (Dyn)
13
20
mA
Soft Start
Soft Start Ramp Rate
VFB Voltage
SSrate
VFB
0.16
0.2
0.5
0.24
mV/µs
Feedback Voltage
V
0°C < Tj < 85 °C
-40 °C < Tj < 125 °C (Note 6)
-0.6
-1
+0.6
+1
Accuracy
%
VFB Input Current
On-Time Timer Control
On Time
IVFB
VFB = 0.5 V, Tj = 25 C
-0.4
0
+0.4
Ton
109
20
ns
ns
ns
PVin = 12 V, Vout = 1.05 V
Note 7, PVin = 12 V, Vout = 0 V
Tj = 25 C, VFB = 0 V
Minimum On-Time
Minimum Off-Time
Thermal Shutdown
Thermal Shutdown
Hysteresis
Ton(Min)
Toff(Min)
50
240
300
Note 7
Note 7
145
25
°C
V
Under Voltage Lockout
Vcc-Start-Threshold
VCC-Stop-Threshold
VCC_UVLO_Start
VCC_UVLO_Stop
Enable_High
Enable_Low
REN
Vcc Rising Trip Level
Vcc Falling Trip Level
Ramping up
4
4.2
3.8
1.2
1
4.4
4.1
3.6
1.14
0.9
500
2.6
1.36
1.06
1500
Enable Threshold
V
k
V
Ramping down
Input Impedance
FCCM Start Threshold
FCCM Stop Threshold
Current Limit
1000
VFCCM_start
VFCCM_stop
2.3
0 °C<Tj< 125 °C, OCSet = PGND
4.0
5.0
5.5
A
Current Limit Threshold
Hiccup Blanking Time
Ioc
0 °C <Tj< 125 °C, OCSet = Floating
0 °C <Tj< 125 °C, OCSet = Vcc
Note 7
3.2
2.3
3.85
2.75
20
4.3
3.2
Tblk_Hiccup
ms
Final Datasheet
7 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Electrical Specifications
OV Protection
Output OV Protection Threshold
Vovp
OVP detect
115
120
5
125
%
Output OV Protection Delay
PGood
TOVPDEL
S
Power Good Upper Threshold
Power Good Lower Threshold
Power Good Sink Current
VPG(upper)
VPG(lower)
IPG
Fb Rising
85
80
90
85
5
95
90
%
mA
V
Fb Falling
PG = 0.5 V, En = 2 V
2.5
Power Good Voltage Low when
no supply
PVin = Vcc = 0 V,
Rpull-up=ꢅꢉ kΩ to ꢀ.ꢀ V
VPG(low)
0.3
0.5
Note:
6. Cold & hot temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
7. Guaranteed by design but not tested in production.
3.4
Typical Operating Characteristics
Unless otherwise specified, typical curves are generated at room temperature.
FSW vs. PVIN, FCCM, Io=0A
960
950
940
930
920
910
900
890
4
6
8
10
12
14
16
PVin (V)
Vout=1.8V
Figure 5
Switching Frequency vs. Input Voltage in FCCM, Vout = 1.8 V
Final Datasheet
8 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Electrical Specifications
FSW vs. IOUT, FCCM, PVin=12V
1040
1020
1000
980
960
940
920
900
880
0
0.5
1
1.5
Iout (A)
2
2.5
3
3.5
Vout=1.8V
Figure 6
Switching Frequency vs. Output Current in FCCM, Vout = 1.8 V
LOAD REGULATION vs. PVIN, FCCM
1.82
1.81
1.8
1.79
1.78
0
0.5
1
1.5
2
2.5
3
Iout (A)
Vin=5V
Vin=10V
Vin=12V
Vin=14V
Figure 7
Load Regulation for Vo = 1.8 V
Final Datasheet
9 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Electrical Specifications
THERMAL DERATING, PVIN = 12V
3.5
3
2.5
2
1.5
1
0.5
0
55
65
75
Ambient Temperature (°C)
12V-3.3V 12V-5V
85
95
105
115
12V-1.8V
Figure 8
TDM3883 Thermal Derating, Tested at 0LFM, Climate chamber, the Case Temperature was
monitored with a 125C limit.
Final Datasheet
10 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Electrical Specifications
3.5
Typical Efficiency Curves
PVin = 12 V and PVin = 5 V, Io = 0 A – 3 A, Room Temperature, No Air Flow. Note that the efficiency curves include
the losses of TDM3883 and the inductor losses.
TDM3883 EFFICIENCY @PVin=5V
100
95
90
85
80
75
70
65
60
Vout=0.9V - FCCM
Vout=1.0V - FCCM
Vout=1.2V - FCCM
Vout=1.8V - FCCM
Vout=0.9V - DEM
Vout=1.0V - DEM
Vout=1.2V - DEM
Vout=1.8V - DEM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Figure 9
Efficiency Curves for PVin = 5 V
TDM3883 EFFICIENCY @PVin=12V
100
95
90
85
80
75
70
65
60
Vout=1.0V - FCCM
Vout=1.2V - FCCM
Vout=1.8V - FCCM
Vout=3.3V - FCCM
Vout=5.0V - FCCM
Vout=1.0V - DEM
Vout=1.2V - DEM
Vout=1.8V - DEM
Vout=3.3V - DEM
Vout=5.0V - DEM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Figure 10
Efficiency Curves for PVin = 12 V
Final Datasheet
11 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Theory of Operation
4
Theory of Operation
4.1
Description
The TDM3883 is an easy-to-use, fully integrated and highly efficient monolithic dc-dc regulator. The on-chip
PWM controller, MOSFETs and integrated inductor make TDM3883 a space-efficient solution, providing
accurate power delivery.
The TDM3883 offers two different operation modes: Forced Continuous Conduction Mode (FCCM) and Diode
Emulation Mode (DEM). With FCCM, the device always operates as a synchronous buck converter with a
pseudo- constant switching frequency of 800 kHz and small output voltage ripples. In DEM, the synchronous
FET is turned off when the inductor current drops to zero, which provides better efficiency at light load.
4.2
Enhanced Stability IPOL Engine
The TDM3883 uses the Enhanced Stability IPOL engine that comprises Constant On-Time (COT) control with
proprietary internal ramp compensation to offer stability across a wide range of conditions.
Unlike conventional COT devices, which usually require a certain amount of output ripple voltage to ensure
stability, the TDM3883 includes proprietary internal ramp compensation, facilitating the use of low ESR ceramic
output capacitors.
In addition, the internal ramp implements the input voltage feed-forward feature, which helps to preserve the
same loop response with a wide input voltage range.
The operation of TDM3883 is described as follows. The output voltage of the regulator is fed to the FB pin
through a resistor divider. Combined with the proprietary internal ramp, the FB voltage is then compared to an
internal reference voltage. If the combined voltage is lower than the reference voltage, the control FET is turned
on for a fixed duration to charge the output capacitor. When the on-time of the control FET is finished, the
synchronous FET is turned on. In FCCM, synchronous FET stays on until the combination of FB voltage and the
internal ramp drops below the reference voltage and a new PWM pulse is initiated. In DEM, synchronous FET
will be turned off when the inductor current drops to zero.
4.3
Pseudo-Constant Switching Frequency
The TDM3883 operates with a pseudo-constant frequency of 800 kHz within the recommended operation
range. To achieve constant switching frequency, the on-time of the control FET is automatically adjusted for
different input and output voltages.
The on-time is determined by the ratio of the voltages at the V0 pin and the PVin pin, and can be calculated as
follows:
V
ꢄ
ꢂ
Tꢀꢁ =
×
PV
8ꢅꢅ kHz
iꢃ
4.4
Soft-Start
The TDM3883 has an internal digital soft-start circuit to control the output voltage rise time, and to limit the
current surge at start-up. To ensure correct start-up, the soft-start sequence initiates when Enable and Vcc
voltages rise above their UVLO thresholds and the internal Power On Ready (POR) signal is asserted. The
internal soft-start signal linearly rises at the rate of 0.2 mV/µs. The normal Vout start-up time is fixed, as shown
below.
Final Datasheet
12 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Theory of Operation
ꢋ.ꢌ ꢍ
ꢆꢇꢈꢉꢊꢈ
=
= ꢎ. ꢌ ꢏꢇ
ꢋ.ꢎ ꢏꢍ/ ꢐꢇ
The over-current protection (OCP) and over-voltage protection (OVP) are enabled during soft-start to protect
the device against any short circuit or over-voltage condition. Figure 11 illustrates the theoretical operation
waveforms during the start-up.
POR
PGood
0.5V
Internal SS
0.9* Vref
FB
Figure 11
Theoretical operation waveforms during soft-start
4.5
En/FCCM
En/FCCM is a multi-function pin. It can be used to:
•
•
•
Turn the TDM3883 on and off
Select the operation mode: FCCM or DEM
Implement Under-Voltage Lockout of the Input Voltage
When En/FCCM voltage is higher than the Enable_high threshold (1.2 V typical), the TDM3883 is turned on with
DEM. In order to operate in FCCM, the En/FCCM voltage needs to be above 2.6 V. The Enable/FCCM thresholds
are designed to be compatible with 3.3 V logic.
The TDM3883 has a precise Enable_high threshold voltage, which is internally monitored by the Under-Voltage
Lockout (UVLO) circuit. As shown in Figure 12, the input of the Enable pin can be derived from the PVin voltage
by a resistor divider, REN1 and REN2. By selecting different divider ratios, users can program the UVLO threshold
voltage. The bus voltage UVLO is a very useful feature. It prevents the TDM3883 from operating when PVin is
lower than the desired voltage level.
For some space-constrained designs, the En/FCCM pin can be directly connected to PVin without using an
external resistor divider.
The En/FCCM pin should not be left floating. A pull-down resistor in the range of tens of kilohms is
recommended.
Final Datasheet
13 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Theory of Operation
Figure 13 shows the connections of En/FCCM without using the external resistor divider. Figure 14 and Figure
15 illustrate the theoretical start-up waveforms.
PVin
PVin
Vcc
REN1
En/FCCM
TDM3883
REN2
Figure 12
Single supply configuration with adjustable PVin UVLO and optional FCCM or DEM
PVin
PVin
Vcc
En/FCCM
TDM3883
Figure 13
Single supply configuration with FCCM operation
PVin=Enable=12 V
Vcc
En Threshold
0V
Vcc_UVLO
0V
FB
90% of Vref
0V
PGood
0V
PGood stays at logic low
Figure 14
Start-up with PVin and Enable tied together. PGood is pulled up to an external supply
Final Datasheet
14 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Theory of Operation
PVin=12 V
Vcc
Vcc_UVLO
0V
0V
Enable > 1.2 V
Fb
0V
90% of Vref
PGood
0V
0V
PGood stays at logic low
Figure 15
Start-up with Enable up after PVin. PGood is pulled up to an external supply
4.6
Pre-Bias Start-Up
The TDM3883 is able to start up into a pre-charged output without causing oscillation and disturbances of the
output voltage. When TDM3883 starts up with a pre-biased output voltage, both control FET and Synch FET are
kept off until the internal soft-start signal exceeds the FB voltage.
During pre-bias start-up, the PGood signal is held low until the first gate signal for the control FET is generated.
4.7
Over-Current Protection
TDM3883 has three selectable Over-Current Protection (OCP) thresholds determined by the voltage level of the
OCSet pin. The OCP is performed by sensing the current through the RDS(on) of the Sync MOSFET. This method
enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and mitigates layout-
related noise issues. The current limit is pre-set internally and is thermally compensated to minimize OCP limit
variation.
The OCP circuit senses the current of the Sync MOSFET 100 ns after the Control FET is turned off. If the current
exceeds the OCP limit, PGood and soft start signals will be pulled low. The Sync FET remains on until the
current is decreased to zero. The TDM3883 then enters hiccup mode. Both Control FET and Sync FET remain off
during the hiccup blanking time. After the hiccup blanking time expires, the TDM3883 will try to restart. If the
over-current fault is still detected, the preceding actions will be repeated. The TDM3883 stays in hiccup mode
until the over-current fault is removed Figure 16 illustrates the operation of OCP.
Final Datasheet
15 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Theory of Operation
100ns
Current Limit
Inductor
Current
Hiccup
Blanking time
HDrv
LDrv
PGood
Figure 16
Illustration of OCP with hiccup Mode
4.8
Minimum On-Time and Off-Time
The minimum on-time refers to the shortest time for control FET to be reliably turned on. Typically, it is 20 ns.
In both DEM and FCCM, the Sync FET stays on for at least 240 ns, which is referred to as the minimum off-time.
The minimum off-time is needed to charge the bootstrap capacitor and to monitor the current of the Sync FET
for OCP.
4.9
Over-Voltage Protection
The TDM3883 senses voltage at the FB pin for Over-Voltage Protection (OVP). When FB voltage exceeds the OVP
threshold for longer than the output OV protection delay ꢋtypical value is ꢅ μsꢌ, the OVP circuitry is tripped. The
Control FET is turned off immediately and PGood is pulled low. The Sync FET is turned on to discharge the
output capacitor until the FB voltage drops below the OVP threshold.
Once OVP is tripped, the Control FET remains latched off until a reset is performed by cycling either PVin voltage
or the Enable signal. Figure 17 illustrates the operation of over-voltage protection.
Final Datasheet
16 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Theory of Operation
HDrv
LDrv
120%Vref
115%Vref
Vref
90%Vref
FB
PGood
OVP delay =5us
Figure 17
Operation of Over-Voltage Protection
4.10
PGood
The PGood pin is the open drain of an internal NFET and needs to be externally pulled high through a pull-up
resistor, e.g., ꢈꢍ.ꢍ kΩ.
The PGood signal is high when three criteria are satisfied:
1. Enable and VCC UVLO voltage are above their respective thresholds;
2. No fault occurs including over-current, over-voltage and over-temperature;
3. Output voltage (Vout) is in regulation.
In order to detect if Vout is in regulation, the PGood comparator continuously monitors the FB pin voltage. When
FB voltage ramps up above the upper threshold (90% of Vref), the PGood signal is pulled high. When FB voltage
ramps down below the lower threshold (85% of Vref), the PGood signal is pulled low. Figure 18 illustrates the
PGood upper and lower thresholds.
For pre-biased start-up, PGood is not active until the first gate signal of the control FET is initiated.
TDM3883 also integrates a PFET in parallel with the PGood NFET, as shown in Figure 4. This PFET allows the
PGood signal to stay at logic low when the bias voltage of TDM3883 is low, and/or if the En is low. Please refer
to Figure 14 and Figure 15.
Final Datasheet
17 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Theory of Operation
90%Vref
90%Vref
Vref
85%Vref
FB
PGood
Figure 18
Power Good Thresholds
4.11
Over-Temperature Protection
Temperature sensing is provided by the TDM3883. The Over-Temperature Protection (OTP) threshold is
typically set to 145 °C. When the OTP threshold is exceeded, both MOSFETs are turned off and the internal soft
start is reset. The internal LDO is still in operation when OTP is tripped.
Automatic restart is initiated when the sensed temperature drops below the OTP threshold. The hysteresis of
the OTP threshold is 25 °C.
Final Datasheet
18 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
5
Application
5.1
Application Information
The following example is a typical application for TDM3883. The application circuit is shown in Figure 19.
•
•
•
•
•
PVin =12 V
V0 = 3.3 V
I0 = 3 A
V0 Ripple voltage = ± 1% of V0
Transient response = ± 3% of V0 for 30% Load transient
ENABLE TDM3883
To enable TDM3883 in Diode Emulation Mode (DEM), the voltage at the EN/FCCM pin should be higher than the
Enable threshold, but lower than FCCM stop threshold. If a resistor divider is used to generate the Enable
voltage from PVin as shown in Figure 12, the resistor divider can be selected as follows.
REN2
PVin(min)
1.36
REN1 + REN2
REN2
PVin(max)
2.3
REN1 + REN2
Where PVin (min) and PVin (max) are the minimum and maximum input voltages respectively.
To enable TDM3883 in FCCM, the voltage at EN/FCCM pin should be no less than the FCCM start threshold. The
EN/FCCM pin can be connected directly to PVin as shown in Figure 13, or a resistor divider can be used, Figure
12. The following criterion should be satisfied when selecting the resistor divider for FCCM.
REN2
PVin(min)
2.6
REN1 + REN2
INPUT CAPACITOR SELECTION
Without input capacitors, the pulse current of the control FET is provided directly from the input power supply.
Due to the impedance on the input power supply cabling, the pulse current can disturb the input voltage and
potential EMI issues can result. The input capacitors filter the pulse current of the control FET, reducing these
risks and resulting in almost constant current from the input supply.
The input capacitors should be selected to tolerate the input pulse current, and to reduce input voltage ripple.
The RMS value of the input ripple current can be expressed as:
IRMS = I0 D(1− D)
V0
D =
V
in
Where IRMS is the RMS value of the input capacitor current. I0 is the output current. D is the duty ratio.
Final Datasheet
19 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
To meet the requirement of the input ripple voltage, the minimum input capacitance can be calculated as
follows.
I0 D(1− D)
Cin(min)
fsw V
in(max)
Where ΔVin(max) is the maximum allowable peak-to-peak input ripple voltage.
Ceramic capacitors are recommended as input capacitors due to low ESR, ESL and high RMS current capability.
In addition, a bulk capacitor is recommended if the input supply is not located close to the voltage regulator.
OUTPUT CAPACITOR SELECTION
To ensure loop stability, a minimum of one 22 µF output capacitor is suggested. The voltage ripple and
transient requirements determine the output capacitor selection.
The following formula calculates the peak-to-peak output voltage ripple due to the inductor ripple current
charging the output capacitor.
iL max
V0 =
8C0 fsw
Therefore,
iL max
C0
8
V0min fsw
Where ΔV0min is the minimum allowable peak-peak output ripple voltage. ΔiLmax is the maximum inductor ripple
current.
The ESR and ESL of the output capacitors, as well as the parasitic resistance or inductance due to PCB layout,
can also contribute to the output voltage ripple. For most applications, it is suggested to use Multi-Layer
Ceramic Capacitors (MLCC) for their low ESR, ESL and small size.
To meet the transient response requirements, the output capacitors should also meet the following criterion.
LI02max
C0
2V0L_max V0
Where ΔV0L_max is the max allowable Vo deviation during the load transient. ΔI0max is the maximum step load
current. Please note that the impact of ESL, ESR, control loop response, transient load slew rate, and PWM
latency is not considered in the calculation shown above. Extra capacitance is usually needed to meet transient
response requirements.
OUTPUT VOLTAGE PROGRAMMING
Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal
reference voltage of 0.5 V. The divider ratio is set to provide 0.5 V at the FB pin when the output is at its desired
value. The calculation of the feedback resistor divider is shown below.
R1
V0 =Vref (1+
)
R2
Final Datasheet
20 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
The bottom feedback resistor is recommended not to exceed 20 kꢊ, in order to avoid interference with the
internal circuitry.
FEEDFORWARD CAPACITOR
A small MLCC capacitor Cff, can be placed in parallel with the top feedback resistor to improve transient
response. As a general rule of thumb, for a fixed top feedback resistor of 39.2 kꢊ, 100 pF can be used for Cff.
BOOTSTRAP CAPACITOR
For most applications, a 0.1 µF ceramic capacitor is recommended for the bootstrap capacitor placed between
the SW node and the Boot pin.
VCC BYPASS CAPACITOR
A 2.2 µF ceramic capacitor should be placed between VCC and PGND.
5.2
Typical Application Diagrams
BOOST
SW
0.1µF
PVin
12V
PVin
49.9k
EN/FCCM
2x 22µF
VO
16.7k
VOUT
TDM3883
100pF
22µF 22µF 22µF
VCC
PG
2.2µF
39.2k
49.9k
FB
OCSET1
6.98k
OCSET
OCSET2
OCSET3
Vout = 3.3V
Iout = 3A
Fsw = 800kHz
Op. Mode = FCCM
PGND
AGND
Figure 19
Application Diagram PVin = 12 V, Vout = 3.3 V, Iout = 3 A, FCCM
Final Datasheet
21 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
BOOST
0.1µF
PVin
12V
PVin
SW
49.9k
EN/FCCM
2x 22µF
VO
10k
VOUT
TDM3883
100pF
22µF 22µF 22µF
VCC
PG
2.2µF
39.2k
6.98k
49.9k
FB
OCSET1
OCSET
OCSET2
OCSET3
Vout = 3.3V
Iout = 0A
Fsw = 800kHz
Op. Mode = DEM
PGND
AGND
Figure 20
Application Diagram PVin = 12 V, Vout = 3.3 V, Iout = 0 A, DEM
Final Datasheet
22 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
5.3
Recommended configurations
Table 6 lists recommended configurations for a few commonly used output voltages.
Table 6
PVin (V)
Recommended configurations
Vout (V)
Upper FB
Lower FB
Cff (pF)
Minimum Co
Maximum Co
Resistor kΩ Resistor kΩ
ꢀμFꢁ
ꢀμFꢁ
Note 10
3 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
Note 10
14 x 22µF
14 x 22µF
14 x 22µF
12 x 22µF
10 x 22µF
10 x 22µF
14 x 22µF
12 x 22µF
10 x 22µF
10 x 22µF
5.0
3.3
2.5
1.8
1.2
1.0
2.5
1.8
1.2
1.0
39.2
39.2
39.2
39.2
16.5
16.5
39.2
39.2
16.5
16.5
4.32
6.98
9.76
15.0
11.8
16.5
9.76
15.0
11.8
16.5
100
100
100
100
100
100
100
100
100
100
12
5
Note:
8. All resistors are 0402, E96 series, 1% standard
9. For typical high duty cycle application: PVin = 5V, Vout = 3.3V, Iout =3A, we recommend use TDM3885 [4A] part.
10. The output capacitors are selected to meet ±1% output ripple voltage and ±3% undershoot/overshoot at 30% of max load transient
with 2.5A/µs slew rate. Please note that 22µF is rated capacitance at 0V DC bias voltage.
11. Application should not exceed the max operating conditions defined in Table 4.
Final Datasheet
23 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
5.4
Typical Operating Waveforms
PVin = 12.0V, Vo=3.3V, Io=0A - 3A, No airflow, room temperature
Figure 21
Start-up, PVin =12V, Vout = 3.3V, Iout = 0A, FCCM. CH1 = Vout, CH2 = PVin, CH3 = PGOOD, CH4 = VCC, CH5
Enable, CH6 = VFEEDBACK
Figure 22 Start-up, PVin =12V, Vout = 3.3V, Iout = 3A, FCCM. CH1 = Vout, CH2 = PVIN, CH3 = PGOOD, CH4 = VCC, CH5 =
Enable, CH6 = VFEEDBACK
Final Datasheet
24 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
Figure 23
Start-up Prebias [1V], PVin =12V, Vout = 3.3V, Iout = 0A, FCCM. CH1 = Vout, CH2 = PVin, CH3 = PGOOD, CH4
= VCC, CH5 = Enable, CH6 = VFEEDBACK
Figure 24
OVP, PVin =12V, Vout = 3.3V, Iout = 0A, FCCM. CH1 = Vout, CH2 = PVin, CH3 = PGOOD, CH4 = VCC, CH5 =
Enable, CH6 = VFEEDBACK
Final Datasheet
25 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
Figure 25 Short Circuit, PVin =12V, Vout = 3.3V, Iout = 3A, FCCM. CH1 = Vout, CH2 = PVin, CH3 = PGOOD, CH4 = VCC, CH5
= Enable, CH6 = VFEEDBACK
Figure 26 Vout ripple, PVin =12V, Vout = 3.3V, Iout = 3A, FCCM. CH1 = Vout
Final Datasheet
26 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Application
Figure 27 SW node, PVin =12V, Vout = 3.3V, Iout = 0A, FCCM. CH1 = SW
Figure 28 Transient Response, PVin =12V, Vout = 3.3V, Iout = 0A to 3A, FCCM. CH1 = Vout, CH2 = Iout. Slew rate =
5A/µS.
Final Datasheet
27 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Marking Information
6
Marking Information
Figure 29
Package Marking, Left (Front side), Right (Rear side)
Final Datasheet
28 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Tape and Reel Information
7
Tape and Reel Information
Figure 30
Pin 1 orientation in the tape
Final Datasheet
29 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Mechanical Pad Drawing
8
Mechanical Pad Drawing
Figure 31
Mechanical Pad Drawing (all dimensions in mm), Tolerances are as per ISO 2768-mK.
Final Datasheet
30 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
PCB Metal and Component Placement
9
PCB Metal and Component Placement
Figure 32
PCB Metal Pad Sizing and Spacing (all dimensions in mm)
9.1
Reflow guideline
Infineon does not recommend specific reflow profiles for our products. Multiple factors influence the reflow
profile: PCB size, thermal mass of the board, layers, copper thickness, etc. The optimum reflow profile should
be generated initially by referring to the solder paste manufacturer’s technical datasheet, and then should be
further optimized for the assembly.
For Maximum reflow temperature and time according to J-STD-020 standard, please refer to the reflow
soldering section in the following application note.
For further information, please refer to ꢂRecommendations for Board Assembly of Infineon Packages with Land
Grid Array Configurationꢃ application note.
Final Datasheet
31 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Stencil Design
10
Stencil Design
Figure 33
Stencil Pad Spacing (all dimensions in mm)
Note:
12. Contact Infineon Technologies to receive an electronic PCB Library file in your preferred format.
13. This evaluation board is not according to the JEDEC standard. Evaluation Board Description: DB310 REV2 - The PCB is a six-layer board
(40.6mm x 55.8 mm) using FR4 material. Top and bottom layers use 0.5 oz. base copper plus 1.5 oz. plating. Inner layers use 2 oz.
copper. The PCB thickness is 1.57 mm. Layer stack-up is top – GND1 – GND2 – signal – GND3 – bottom.
Final Datasheet
32 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Layout Recommendations
11
Layout Recommendations
The pinout of TDM3883 makes it easy to route the PCB layout. General PCB design guidelines should be
followed to achieve the best performance.
•
Bypass capacitors, including input/output capacitors and Vcc bypass capacitor, should be placed as close as
possible to the corresponding pins.
•
•
SW node area should be minimized and be limited to the top layer only.
Output voltage should be sensed with a separate trace directly from the output capacitor. The sensing trace
should be away from the inductor and SW node to avoid interference from switching noise.
•
•
The exposed pad can be connected to the power ground plane through via holes to aid thermal dissipation.
Wide copper polygons are best practice for input and output power connections. This provides power loss
reduction and improved thermal performance. Sufficient via holes should be used to connect the power
traces between different layers.
Figure 34
Demo Board Layout – Top layer
Figure 35
Demo Board Layout – PGND pads
Final Datasheet
33 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Layout Recommendations
Figure 36
Demo Board Layout – Signal layer
Figure 37
Demo Board Layout – Bottom layer
Final Datasheet
34 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Environmental Qualifications
12
Environmental Qualifications
Table 7
Environmental Qualifications
Qualification Level
Industrial
Moisture Sensitivity Level
2.7 mm x 3.1 mm
PG-LGA-15-1
JEDEC Level 3 @ 260 °C
ESD
[HBM] Human Body Model
[CDM] Charge Device Model
RoHS6 Compliant
ANSI/ESDA/JEDEC JS-001, Class 2 (2000V to <4000V)
ANSI/ESDA/JEDEC JS-002, Class C2A (500 to <750)
Yes
† Qualification standards can be found at Infineon Technologies web site: www.infineon.com
Final Datasheet
35 of 37
V 2.2
2022-07-11
TDM3883 IPOL
3 A IPOL Synchronous Buck Voltage Regulator with Integrated Inductor
Evaluation Board and Support Documentation
13
Evaluation Board and Support Documentation
Table 8
TDM3883 Evaluation Boards and User Guides
Evaluation board
Specifications
Website Address
www.infineon.com/eval-tdm3883-3.3vout
12 V±10%, 3.3 V, 3 A
EVAL_TDM3883_3.3Vout
Final Datasheet
36 of 37
V 2.2
2022-07-11
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
Edition 2022-07-11
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
Published by
characteristics ꢋꢂBeschaffenheitsgarantieꢃꢌ .
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 München, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in
a written document signed by
authorized
representatives
of
Infineon
Email: erratum@infineon.com
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
Document reference
ifx1
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
3ꢀAꢀIPOLꢀSynchronousꢀBuckꢀVoltageꢀRegulatorꢀwithꢀIntegratedꢀInductor
TDM3883
RevisionꢀHistory
TDM3883
Revision:ꢀ2022-07-20,ꢀRev.ꢀ2.2
Previous Revision
Revision Date
Subjects (major changes since last revision)
Initial release
2.0
2.1
2022-02-08
2022-04-29
2022-07-20
(1) Update section 5.3 title, and table 6: Cff, Cout_min and Cout_max. (2) Add section
9.1, Reflow guideline.
2.2
Ordering information update. Tape & reel qty = 2500 units.
Trademarks
Allꢀreferencedꢀproductꢀorꢀserviceꢀnamesꢀandꢀtrademarksꢀareꢀtheꢀpropertyꢀofꢀtheirꢀrespectiveꢀowners.
WeꢀListenꢀtoꢀYourꢀComments
Anyꢀinformationꢀwithinꢀthisꢀdocumentꢀthatꢀyouꢀfeelꢀisꢀwrong,ꢀunclearꢀorꢀmissingꢀatꢀall?ꢀYourꢀfeedbackꢀwillꢀhelpꢀusꢀtoꢀcontinuously
improveꢀtheꢀqualityꢀofꢀthisꢀdocument.ꢀPleaseꢀsendꢀyourꢀproposalꢀ(includingꢀaꢀreferenceꢀtoꢀthisꢀdocument)ꢀto:
erratum@infineon.com
Publishedꢀby
InfineonꢀTechnologiesꢀAG
81726ꢀMünchen,ꢀGermany
©ꢀ2022ꢀInfineonꢀTechnologiesꢀAG
AllꢀRightsꢀReserved.
LegalꢀDisclaimer
Theꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀshallꢀinꢀnoꢀeventꢀbeꢀregardedꢀasꢀaꢀguaranteeꢀofꢀconditionsꢀorꢀcharacteristicsꢀ
(“Beschaffenheitsgarantie”)ꢀ.
Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe
product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation
warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.
Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis
documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe
productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.
Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s
technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct
informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
TechnologiesꢀOfficeꢀ(www.infineon.com).
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
38
Rev.ꢀ2.2,ꢀꢀ2022-07-20
相关型号:
©2020 ICPDF网 联系我们和版权申明