TLD2252-2EP_技术文档

TLD2252-2EP

LITIX™ Basic+

Features

•

Dual channel device with integrated and protected output stage (current

source), optimized to drive LEDs as additional low cost current source

Optimized for low cost combined “stop”/ “tail” function in Rear

Combination Light (RCL)

Asymmetric output stages to enhance luminosity control for different

functions

•

High output current (up to 120 mA)

Very low current consumption in sleep mode

Very low output leakage when channel is “off”

Low current consumption during fault

Independent output currents’ control via low power resistors

Additional output current demand supported by LITIX™ Companion direct drive

PWM engine supports digital dimming with very high accuracy

Intelligent fault management: up to 16 devices can share a common error network with only one external

resistor

•

Reverse polarity protection allows reduction of external components and improves system performance

at low battery/input voltages

•

Overload protection

Wide temperature range: -40°C < T_J< 150°C

Output current control via external low power resistor

Green product (RoHS compliant)

Potential applications

•

Cost effective “stop”/ “tail” function implementation with shared and separated LEDs per function

Turn indicators

Position, fog, rear lights and side markers

Animated light functions like wiping indicators and “welcome/goodbye” functions

Day Running Light

Interior lighting functions like ambient lighting (including RGB color control), illumination and dash board

lighting

•

LED indicators for industrial applications and instrumentation

Datasheet

www.infineon.com

Rev. 1.10

2021-06-15

1

TLD2252-2EP

LITIX™ Basic+

Product validation

Qualified for Automotive Applications. Product Validation according to AEC-Q100/101.

Description

The LITIX™ Basic+ TLD2252-2EP is a dual channel high-side driver IC with integrated output stages. It is

designed to control LEDs with a current up to 120 mA. In typical automotive applications the device is capable

of driving 3 red LEDs per chain (total 6 LEDs) with a current up to 100 mA and even above, if not limited by the

overall system thermal properties. Practically, the output current is controlled by an external resistor or

reference source, independently from load and supply voltage changes.

Table 1

Product summary

Parameter

Symbol

Values

Operating voltage

Maximum voltage

V_S(nom)

5.5 V … 40 V

40 V

V_S(max)

V_OUT1/2(max)

Nominal output (load) currents

I_OUT1/2(nom)

50/100 mA (nominal) when using the automotive

supply voltage range 8 V - 18 V. Currents up to

I_OUT1/2(max)are possible with low thermal resistance

R_thJA

Maximum output (load) currents

Current accuracy at R_SET= 10 kΩ

Current consumption in sleep mode

I_OUT1/2(max)

K_RTx

60/120 mA depending on R_thJA

300/600 ±3.33%

0.1 µA

I_{S(sleep, typ)}

Maximum current consumption during I_{S(fault, ERRN)}

fault

850 µA or less when fault is detected from another

device (disabled via ERRN) and all channels are

deactivated (D-pin open)

Type

Package

Marking

TLD2252-2EP

PG-TSDSO-14

TLD2252

Datasheet

2

Rev.1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Table of Contents

1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2

2.1

2.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1

3.2

3.3

4

4.1

4.2

Internal supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical characteristics internal supply and ENx pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5

5.1

Power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output configuration via IN_SETx pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

IN_SETx pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output current adjustment via R_SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output control via IN_SETx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

IN_SETx pins behavior during device fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Electrical characteristics power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Electrical characteristics IN_SETx and PWMI pins for output settings . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1.1

5.1.2

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.3

5.4

6

6.1

Load diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Error management via ERRN and D-pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ERRN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

D-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Overtemperature (OT), Open Load (OL) and short OUTx to GND (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Fault management (D-pin open or connected with a capacitor to GND) . . . . . . . . . . . . . . . . . . . . . 24

Fault management (D-pin connected to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Electrical characteristics: Load diagnosis and Overload management . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1.1

6.1.2

6.2

6.2.1

6.2.2

6.3

7

PWM control (Digital dimming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PWM unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Direct control of PWMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electrical characteristics PWM engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1

7.2

7.3

7.4

8

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9

10

Datasheet

3

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Block diagram

1

Block diagram

11

VS

Internal

supply

ERRN

14

EN/DEN1

EN/DEN2

D

9

10

7

Output

control

&

Thermal

protection

OUT2

OUT1

12

13

IN_SET1

IN_SET2

2

3

Current

reference

PWMI

6

5

4

PWM

PWM_SET

PWM_RST

PWMO

1

engine

GND

TLD2252-2EP

8

Figure 1

Block diagram

Datasheet

4

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Pin configuration

2

Pin configuration

2.1

Pin assignment

ERRN

OUT1

PWMO

1

2

3

4

5

6

7

14

13

12

11

10

9

IN_SET1

IN_SET2

PWM_RST

PWM_SET

PWMI

OUT2

EP

VS

EN2/DEN2

EN1/DEN1

GND

exposed pad (bottom)

D

8

TLD2252-2EP

Figure 2

Pin configuration

2.2

Pin definitions and functions

Symbol

Function

11

VS

Supply voltage; Connected to battery or supply control switch, with EMC

filter

8

2

GND

Ground; Signal ground

IN_SET1

Control input for OUT1 channel; Connect to a low power resistor to adjust

OUT1 output current. Alternatively, a different current reference (i.e. the

OUT_SET of another LITIX™ Basic+ LED Driver) may be connected

3

6

IN_SET2

PWMI

Control input for OUT2 channel; Connect to a low power resistor to adjust

OUT2 output current. Alternatively, a different current reference (i.e. the

OUT_SET of another LITIX™ Basic+ LED Driver) may be connected

PWM input; Connect to an external PWM controller or a ceramic capacitor

(when internal PWM engine is intended to be used). If not used, connect to

GND

1

4

PWMO

PWM output; Buffered PWMI logic state. Used to drive additional devices with

same timing as PWMI. If not used, leave the pin open

PWM_RST

PWM duty cycle reset input; Connect to a low power resistor to adjust PWM

frequency and duty cycle. If the internal PWM engine is not used (direct PWMI

drive) it should be left open

5

7

PWM_SET

D

PWM duty cycle set input; Connect to a low power resistor to adjust PWM

frequency and duty cycle. If the internal PWM engine is not used (direct PWMI

drive) it should be left open

Disable/delay error input; Connect to a capacitor, leave open or connect to

GND, depending on the required diagnosis management (see Chapter 6 for

further details)

Datasheet

5

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Pin configuration

14

9

Symbol

Function

ERRN

ERROR flag I/O; Open drain, active low. Connect to a pull-up resistor

EN1/DEN1

Channel 1 output enable and diagnosis control input; Connect to a control

input (i.e. to VS via a resistor divider or a Zener diode) to enable OUT1 control

and Diagnosis

10

EN2/DEN2

Channel 2 output enable and diagnosis control input; Connect to a control

input (i.e. to VS via a resistor divider or a Zener diode) to enable OUT2 control

and Diagnosis

13

12

OUT1

OUT2

EP

Channel 1 output pin; Connect to the target load

Channel 2 output pin; Connect to the target load

Exposed Pad; Connected to GND-pin in application

Exposed

Pad

Datasheet

6

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

Table 2

Absolute maximum ratings¹⁾

T_J= -40°C to +150°C; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing into input and

I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Voltage

Supply voltage

EN/DENx voltages

V_S

-18

–

40

18

V

–

P_4.1.1

P_4.1.3

P_4.1.4

V_EN/DENx-18

–

EN/DENx voltages related to V_S: V_EN/DENx(V-40

V_EN/DENx- V_S

S)

EN/DENx voltages related to

V_EN/DENx(V-18

–

40

V

–

P_4.1.5

V_OUTx: V_EN/DENx- V_OUTx

OUTx)

Output voltages

V_OUTx

-1

–

40

V

–

P_4.1.10

P_4.1.11

Output voltages related to V_S: V_SV_OUTx(VS)-18

- V_OUTx

IN_SETx voltages

PWMI voltage

PWMO voltage

PWM_RST voltage

PWM_SET voltage

ERRN voltage

D Voltage

V_{IN_SETx}-0.3

–

6

V

–

P_4.1.12

P_4.1.14

P_4.1.15

P_4.1.16

P_4.1.17

P_4.1.18

P_4.1.19

V_PWMI

-0.3

6

V_PWMO

6

V_{PWM_RST}-0.3

V_{PWM_SET}-0.3

6

V_ERRN

V_D

-0.3

40

6

Current

Output current (Output channel I_OUT1

OUT1)

0

–

70

mA

–

P_4.1.24

P_4.1.25

Output current (Output channel I_OUT2

130

OUT2)

PWMI current

I_PWMI

-0.5

-2

–

0.5

2

mA

µA

–

P_4.1.26

P_4.1.27

P_4.1.28

P_4.1.29

P_4.1.30

P_4.1.31

PWMO current

I_PWMO

I_{PWM_RST}

I_{PWM_SET}

I_{IN_SETx}

I_D

PWM_RST current

PWM_SET current

IN_SETx currents

D current

0

300

0.5

0

µA

0

µA

-0.5

mA

Temperature

Junction temperature

Storage temperature

T_J

-40

-55

–

150

°C

–

P_4.1.33

P_4.1.34

T_stg

Datasheet

7

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

General product characteristics

Table 2

Absolute maximum ratings¹⁾(cont’d)

T_J= -40°C to +150°C; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing into input and

I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

ESD susceptibility

ESD susceptibility all pins to

GND

V_ESD

-2

–

2

kV

V

HBM²⁾

P_4.1.36

P_4.1.37

P_4.1.38

ESD susceptibility all pins to

GND

-500

500

750

CDM³⁾

ESD susceptibility Pin 1, 7, 8, 14 V_ESD1,7,8,1-750

V

(corner pins) to GND

4

1) Not subject to production test, specified by design

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

3.2

Functional range

Table 3

Functional range

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

V_S(nom)5.5

Max.

Voltage range for normal

operation

18

V

–

P_4.2.1

P_4.2.2

P_4.2.4

Extended supply voltage for V_S(ext)

functional range

V_SUV(ON)

–

40

V

–

Junction temperature

T_J

-40

150

°C

Note:

Within the Normal Operation range, the IC operates as described in the circuit description. Within the

Extended Operation range, parameters deviations are possible. The electrical characteristics are

specified within the conditions given in the Electrical Characteristics table.

Datasheet

8

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

General product characteristics

3.3

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 4

Thermal resistance¹⁾

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

1)2)

Junction to Case

R_thJC

–

10

K/W

P_4.3.1

P_4.3.3

1)3)

Junction to Ambient 1s0p

board

R_thJA1

–

61

56

–

T_A= 85°C

T_A= 135°C

1)4)

Junction to Ambient 2s2p

board

R_thJA2

K/W

P_4.3.4

–

45

43

–

T_A= 85°C

T_A= 135°C

1) Not subject to production test, specified by design

2) Specified R_thJCvalue is simulated at natural convection on a cold plate setup (all pins and exposed pad are fixed to

ambient temperature). T_A= 85°C. Total power dissipation = 1.5 W

3) Specified R_thJAvalue is according to Jedec JESD51-3 at natural convection on FR4 1s0p board. The product

(chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 70 µm Cu, 300 mm²cooling area. Total power

dissipation 1.5 W distributed statically and homogenously over all power stages

4) Specified R_thJAvalue is according to Jedec JESD51-5,-7 at natural convection on FR4 2s2p board; The product

(chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Total power

dissipation 1.5 W distributed statically and homogenously over all power stages

Datasheet

9

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Internal supply

4

Internal supply

This chapter describes the internal supply in its main parameters and functionality.

4.1

Description

The internal supply principle is highlighted in the concept diagram of Figure 3.

If the voltage applied at both the EN/DEN pins are below V_ENx(th)the device enters sleep mode. In this state all

internal functions are switched off and the current consumption is reduced to I_S(sleep)

.

As soon as the voltage applied at the supply pin V_Sis above V_SUV(ON)and the voltage applied at one of the

EN/DEN pins are above V_ENx(th), after the power-on reset time t_POR, the device is ready to deliver output current

from the relative output stage. The power on reset time t_PORhas to be taken into account also in relevant

application conditions, i. e. with PWM control from VS or EN/DEN lines.

Also if PWM control is done via the PWM engine, the conditions V_S> V_SUV(ON)and V_ENn> V_ENx(th)must be fulfilled

for PWM engine (and, therefore, output) activation.

V_SUV

-

+

VS

Internal

V_EN(th)

Supply

OUTx

Control

-

+

EN/DEN

OUTx

Diagnosis

Control

+

-

V_{DE N(th)}

Figure 3

Internal supply

Furthermore, as soon as the voltage applied at the supply pin VS is above V_SUV(ON)and the voltage applied to

one of the EN/DENx pins V_ENxare above V_DENx(th), the device is ready to detect and report fault conditions via

ERRN (error network pin) as described in Chapter 6.

To program outputs enable and diagnosis enable via EN/DENx pins there are several possibilities, like a

resistor divider from VS to GND, a Zener diode from EN/DENx to VS and also a logic control pin (e.g. from a

microcontroller output).

Datasheet

10

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Internal supply

V_S

V_{SU V(th)}

t

V_EN

V_{EN (th)}

t_{PO R}

I_OUT

100%

80%

t

Figure 4

Power on reset timing diagram

Datasheet

11

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Internal supply

4.2

Electrical characteristics internal supply and ENx pins

Table 5

Electrical characteristics: Internal supply and ENx pins

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

0.1

Unit Note or

Test Condition

Number

Min.

Max.

1)

Current consumption, sleep I_S(sleep)

–

2

µA

V

= 0 V

P_5.2.1

ENx

mode

T_J< 85°C

V_S= 18 V

V

_OUTx= 3.6 V

V_ENx= 5.5 V

_{IN_SETx}= 0 µA

Currentconsumption,active I_S(active)

mode (no fault)

–

1.5

3

mA

P_5.2.3

I

T_J< 105°C

V_S= 18 V

V

_OUTx= 3.6 V

I_{PWM_SET}= I_{PWM_RST}

=

100 µA

Currentconsumptionduring I_{S(fault, ERRN)}

fault condition triggered

from another device sharing

ERRN bus (all channels

–

850

µA

V_ENx= 5.5 V

T_J< 105°C

V_S= 18 V

V_ERRN= 0 V

V_OUTx= 3.6 V

P_5.2.4

deactivated)

D open

Currentconsumptionduring I_{S(fault, OUT)}

fault condition (all channels

deactivated)

1.25

mA

V_ENx= 5.5 V

T_J< 105°C

V_S= 18 V

P_5.2.16

V

_OUT1= 0 V

V_OUT2

D open

Supply thresholds

Required supply voltage for V_SUV(ON)

output activation

–

5.5

–

V

V_ENx= V_S

V_OUTx= 3 V

R_{IN_SETx}= 6.8 kΩ

P_5.2.5

P_5.2.6

P_5.2.8

I_OUTx> 50%

I_OUTx(nom)

Required supply voltage for V_SUV(OFF)

output deactivation

4.5

–

V

V_ENx= V_S

V_OUTx= 3 V

R

_{IN_SETx}= 6.8 kΩ

I_OUTx< 50%

I_OUTx(nom)

1)

Supply voltage activation

V_SUV(hys)

200

–

mV

V

> V_EN(th)

ENx

hysteresis: V_SUV(ON)- V_SUV(OFF)

Datasheet

12

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Internal supply

Table 5

Electrical characteristics: Internal supply and ENx pins (cont’d)

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

EN pins

ENx output enable

threshold

V_ENx(th)

1.4

1.65

1.8

V

V_S= 5.5 V

V_PS= 2 V

_{IN_SETx}= 6.8 kΩ

_OUTx= 50%

P_5.2.9

R

I

I_OUTx(nom)

DENx diagnosis enable

threshold

V_DENx(th)

2.4

–

2.5

120

–

2.7

–

V

V_S= 5.5 V

P_5.2.11

P_5.2.12

P_5.2.17

P_5.2.14

P_5.2.15

1)

DENx diagnosis enable

hysteresis

V_DENx(hys)

mV

µA

R

= 6.8 kΩ

IN_SETx

EN/DENx pull-down current I_EN/DENx(PD)

Timing

–

15

35

150

¹⁾V_S> 8 V

V_EN/DENx= 2.8 V

¹⁾V_S> 8 V

V_EN/DENx= 5.5 V

¹⁾V_S> 8 V

V_EN/DENx= V_S

–

Power on reset delay time

t_POR

–

25

µs

¹⁾V_Srising from 0 V P_5.2.13

to 13.5 V

V

_OUTx= 3.6 V

_{IN_SETx}= 6.8 kΩ

_OUTx= 80%

I_OUTx(nom)

R

I

1) Not subjected to production test: specified by design

Datasheet

13

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Power stages

5

Power stages

The two asymmetric output stages are realized as high-side current sources with an output current up to

60/120mA. During off state the leakage current at the output stages is minimized in order to prevent a slightly

glowing LED.

The maximum output current is limited by the power dissipation and used PCB cooling areas.

For an operating output current control loop, the supply and output voltages have to be considered according

to the following parameters:

•

Required supply voltage for current control V_S(CC)

Voltage drop over through the output stage during current control V_PSx(CC)

Required output voltage for current control V_OUTx(CC)

5.1

Protection

The device provides embedded protective functions, which are designed to prevent IC damage under fault

conditions described in this datasheet. Fault conditions are considered as “outside” normal operating range.

Protective functions are not designed for continuous nor for repetitive operations.

5.1.1

Thermal protection

A thermal protection circuitry is integrated in the device. It is realized by a temperature monitoring of the

output stages.

As soon as the junction temperature exceeds the overtemperature threshold T_JSDthe output current of both

channels is disabled and (provided that D-pin is left open or capacitively connected to GND) the IN_SETx pins

go in a weak pull-down state with a current consumption I_{IN_SETx(fault)}. If the junction temperature cools down

below T_JSD- T_J(hys), the IN_SET pins rise again to V_{IN_SETx(ref)}(within an additional time t_{IN_SETx(del)}) and

consequently, the output currents rise again (see Chapter 6 for a detailed description of fault management).

T_j

T_jSD

T_jSD(hys)

t

Over temperature

disappear

Over temperature

occurs

Figure 5

Overtemperature shut down auto-restart thresholds

As long as the device remains into overtemperature condition, ERRN pin remains low.

Datasheet

14

Rev. 1.10

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TLD2252-2EP

LITIX™ Basic+

Power stages

5.1.2

Reverse battery protection

The device has an integrated reverse battery protection feature. This feature protects the driver IC itself and,

potentially, also connected LEDs. The output reverse current is limited to I_OUTx(REV)by the reverse battery

protection.

5.2

Output configuration via IN_SETx pins

Outputs current can be defined via IN_SETx and pins.

5.2.1

IN_SETx pins

The IN_SETx pins are multiple function pins for the outputs current definition and inputs control.

Output currents definition and analog dimming control can be done defining accordingly the IN_SETx

currents.

ref/fault selection

logic

IN_SET

I_{IN_SET}

V_{IN_SET(ref)}

I_{IN_SET(fault)}

GND

Figure 6

IN_SETx pins block diagram

5.2.2

Output current adjustment via R_SET

The output current for the channels can be defined connecting a low power resistor (R_SETx) between the

IN_SETx pins and GND. The dimensioning of the resistors can be done using the formula:

(5.1)

I_OUTx= k I_{IN _ SETx}= k V_{IN _ SETx(ref )}/ R_SETx

The gain factor k_x(defined as the ratio I_OUTx/I_{IN_SETx}) is graphically described in Figure 7.

The current through the R_SETxis defined by the resistor itself and the reference voltage V_{IN_SETx(ref)}, which is

applied to the IN_SETx pin when the device is supplied and the channel enabled.

Datasheet

15

Rev. 1.10

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TLD2252-2EP

LITIX™ Basic+

Power stages

5.2.3

Output control via IN_SETx

The IN_SETx pins can be connected via their R_SETxto the open-drain outputs of a microcontroller or to an

external NMOS transistor as described in Figure 9. This signal can be used to turn off the relative output stages

of the IC.

A minimum IN_SETx current of I_{IN_SETx(ACT)}is required to turn on the output stages. This feature is implemented

to prevent glowing of LEDs caused by leakage currents on the IN_SETn pins, see again Figure 7 for details.

I_OUTx[mA]

k_x= I_OUTx/ I_{IN_SETx}

I_OUTx

I_{IN_SETx(ACT)}

I_{IN_SETx}[µA]

I_{IN_SETx}

Figure 7

I_OUTxvs I_{IN_SETx}

k/k_(typ)

OUT1

110%

105%

100%

95%

90%

16

33

66

100

167

200

I_{IN_SET1}

[μA]

k/k_(typ)

OUT2

110%

105%

100%

95%

90%

16

33

66

100

167

200

I_{IN_SET2}

[μA]

Figure 8

Typical output current accuracy I_OUT/ I_{IN_SET}at T_J= 25°C

Datasheet

16

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Power stages

VS

Supply

Protection

LITIX™

Microcontroller

Basic+ (*)

R_SET

OUT

IN_SET

OUT

PWMI

GND

(*) The drawing refers to a generic LITIX™ BASIC+ device,

and does not represent a specific device pinout

(only the relevant connections for microcontroller IN_SET control are shown)

Figure 9

Output control via IN_SET pin and open-drain microcontroller out (simplified diagram)

5.2.4

IN_SETx pins behavior during device fault management

If a fault condition arises on the channel controlled by the IN_SETx pins, once the D-pin reaches the high level

threshold V_D(th), the current of all the IN_SETx pins is reduced to I_{IN_SETx(fault)}, in order to minimise the current

consumption of the whole device under fault condition (detailed description is in the load diagnosis section,

Chapter 6).

5.2.5

Timing diagrams

In the following diagrams (Figure 10) the influences of input on output deactivation delays are shown.

I_{IN_SET x}

t

t_{ON(IN_SET )}

t_{OFF (IN _SET )}

I_OUTx

100%

90%

10%

t

Figure 10 IN_SET turn on and turn off delay timing diagram

Datasheet

17

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Power stages

5.3

Electrical characteristics power stage

Table 6

Electrical characteristics: Power stage

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

1)

Output leakage currents

I_OUTx(leak)

–

3

µA

V

= 5.5 V

P_6.5.1

ENx

I_{IN_SETx}= 0 µA

_OUTx= 2.5 V

V

T_J= 85°C

1)

Output leakage currents

Reverse output currents

I_OUTx(leak)

–

7

3

V

= 5.5 V

P_6.5.59

P_6.5.2

ENx

I_{IN_SETx}= 0 µA

V_OUTx= 2.5 V

T_J= 150°C

1)

I_OUTx(rev)

V

= V_sx

ENx

V_Sx= -18 V

Output load: LED

with break down

voltage < - 0.6 V

Output current accuracy

K_RT1

K_LT1

K_ALL1

K_RT2

K_LT2

K_ALL2

290

285

282

580

570

564

300

600

310

315

318

620

630

636

–

¹⁾T_J= 25°C

V_S= 12.8 V

P_6.5.16

P_6.5.17

V

_PS1= 2 V

I_{IN_SET1}= 100 µA

Output current accuracy

¹⁾T_J= 25... 150°C

V_S= 8... 18 V

V_PS1= 2 V

I

_{IN_SET1}= 100 µA

¹⁾T_J= -40... 150 °C P_6.5.18

V_S= 8... 18 V

V

_PS1= 2 V

I_{IN_SET1}= 100 µA

¹⁾T_J= 25°C

V_S= 12.8 V

P_6.5.21

P_6.5.22

P_6.5.23

V

_PS2= 2 V

I_{IN_SET2}= 66 µA

¹⁾T_J= 25... 150°C

V_S= 8... 18 V

V

_PS2= 2 V

I_{IN_SET2}= 66 µA

¹⁾T_J= -40... 150°C

V_S= 8... 18 V

V_PS1= 2 V

I_{IN_SET1}= 66 µA

Datasheet

18

Rev. 1.10

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TLD2252-2EP

LITIX™ Basic+

Power stages

Table 6

Electrical characteristics: Power stage (cont’d)

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Required voltage drop

during current control

V_PSx(CC)

1.0

–

V

²⁾V_S= 8... 18 V

_OUTx> 90% of

_x(typ)*I_{IN_SETx}

²⁾V_S= 8... 18 V

_{IN_SETx}= 133 µA

I_OUTx> 90% of

_x(typ)*I_{IN_SETx}

P_6.5.36

I

K

V_PSx(CC)= V_S- V_OUTx

Required voltage drop

during current control

V_PSx(CC)= V_S- V_OUTx

V_PSx(CC)

0.65

0.75

0.85

5.5

–

V

P_6.5.37

P_6.5.38

P_6.5.39

P_6.5.40

P_6.5.41

I

K

T_J= -40°C

Required voltage drop

during current control

V

²⁾V_S= 8... 18 V

I

_{IN_SETx}= 133 µA

I_OUTx> 90% of

_x(typ)*I_{IN_SETx}

V_PSx(CC)= V_S- V_OUTx

K

T_J= 25°C

²⁾V_S= 8... 18V

Required voltage drop

during current control

I

_{IN_SETx}= 133 µA

I_OUTx> 90% of

_x(typ)*I_{IN_SETx}

V_PSx(CC)= V_S- V_OUTx

K

T_J= 150°C

Required supply voltage for V_S(CC)

current control

V_EN= 5.5 V

V

_OUTx= 3 V

R_{IN_SETx}= 6.8 kΩ

_OUTx> 90% of

I

K_x*I_{IN_SETx}

Required output voltage for V_OUTx(CC)

1.4

V_S= 8... 18 V

current control

I_OUTx> 90% of

K_x*I_{IN_SETx}

1)

Overtemperature shutdown T_JSD

threshold

150

–

175

10

190

–

°C

P_6.5.42

P_6.5.43

1)

Overtemperature hysteresis T_J(hys)

1) Not subjected to production test: specified by design

2) In these test conditions, the parameter K_x(typ)represents the typical value of output current accuracy.

Datasheet

19

Rev. 1.10

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TLD2252-2EP

LITIX™ Basic+

Power stages

5.4

Electrical characteristics IN_SETx and PWMI pins for output settings

Table 7

Electrical characteristics: IN_SETx and PWMI pins

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

1)

IN_SETx reference voltage V_{IN_SETx(ref)}

1.195 1.22

1.245

V

= 5.5 V

P_6.6.1

ENx

T_J= 25°C

1)

1.184 1.22

1.256

15

V

= 5.5 V

P_6.6.17

P_6.6.2

ENx

IN_SETx output activation I_{IN_SETx(ACT)}

current

–

µA

V_ENx= 5.5 V

_PSx= 3 V

I_OUTx> 50% of

_x(typ)*I_{IN_SETx}

V

K

Timing

IN_SETx turn on time

t_{ON(IN_SETx)}

20

10

µs

¹⁾²⁾V_S= 13.5 V

V_PSx= 4 V

P_6.6.8

P_6.6.9

I

_{IN_SETx}rising from 0

to 180 µA

_OUTx= 90% of

I

K_x*I_{IN_SETx}

¹⁾²⁾V_S= 13.5 V

IN_SETx turn off time

t_{OFF(IN_SETx)}

–

V

_PSx= 4 V

_{IN_SETx}falling from

180 to 0 µA

_OUTx= 10% of

K_x*I_{IN_SETx}

I

1) Not subjected to production test: specified by design

2) Refer to Figure 10

Datasheet

20

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Load diagnosis

6

Load diagnosis

6.1

Error management via ERRN and D-pins

Several diagnosis features are integrated in the TLD2252-2EP:

•

Open load detection (OL) for any of the output channels OUTx.

Short circuit OUTx-GND (SC) for any of the output channels OUTx.

6.1.1

ERRN pin

ERRN

fault

+

-

Output

control

no fault

V_ERRN(th)

I_ERRN(fault)

Figure 11 ERRN pin (block diagram)

The device is able to report a detected failure in one of its driven loads and react to a fault detected by another

LED driver in the system if a shared error network is implemented (i. e. driving LED chains of the same light

function). This is possible with the usage of an external pull-up resistor, allowing multiple devices to share the

open drain diagnosis output pin ERRN. All devices sharing the common error network are capable to detect

the fault from any of the channels driven by the LITIX™ Basic+ LED drivers and, if desired, to switch multiple

loads off.

Datasheet

21

Rev. 1.10

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TLD2252-2EP

LITIX™ Basic+

Load diagnosis

VS

Supply

Protection

ERRN

LITIX™

Basic+ (*)

LITIX™

Basic+ (*)

IN_SET

PWMI

GND

PWMI

GND

OUT

(*) The drawing refers to a generic LITIX™ BASIC+ device,

and does not represent a specific device pinout

(only the relevant connections are shown)

Figure 12 Shared error network principle between LITIX™ Basic+ family devices

When one of the channels is detected to be under fault conditions (for, at least, a filter time t_fault), the open-

drain ERRN pin sinks a pull-down current I_ERRN(fault)toward GND. Therefore an active low state can be detected

at ERRN pin when V_ERRN< V_ERRN(fault)and if this condition is reached, provided the proper setup of the delay pin

D, all the channels are switched off. Similarly, when the fault is removed, ERRN pin is put back in high

impedance state, and the channels reactivation procedure can be completed once D-pin voltage is below the

value V_D(th), as illustrated in the timing diagrams in this chapter.

Datasheet

22

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TLD2252-2EP

LITIX™ Basic+

Load diagnosis

6.1.2

D-pin

I_D(fault)

ERRN = H

D

ERRN = L

+

-

Ou tput

control

ERRN = H

ERRN = L

V_D(th)

I_D(PD)

Figure 13 D-pin (block diagram).

The D-pin is designed for 2 main purposes:

•

To react to error conditions in LED arrays according to the implemented fault management policy, in

systems where multiple LED chains are used for a given light function.

•

To extend the channels deactivation delay time of a value t_D, adding a small signal capacitor from the D-

pin to GND. In this way, an unstable or noisy fault condition may be prevented from switching off all the

channels of a given light function (i.e. driven by several driver ICs sharing the same error network).

The functionality of the D-pin is shown in the Figure 13 simplified block diagram:

If one LED within one chain fails in open load condition or one of the device outputs are shorted to GND, the

respective LED chain is off. Different automotive applications require a complete deactivation of a light

function, if the desired brightness of the function (LED array) can not be achieved due to an internal error

condition.

In normal operative status (no fault) a pull-down current I_D(PD)is sunk from the D-pin to GND. If there is a fault

condition (for, at least, a filter time t_fault) in one of the LED channels driven by the IC or in any of the devices

sharing the same ERRN error network line, a pull-up current I_D(fault)is instead sourced from the D-pin. As a

consequence, if a capacitive or open load is applied at this pin, its voltage starts rising.

When V_D(th)is reached at D-pin, all the channels driven by the device are switched off and if other devices share

the same ERRN and D-pins nodes, all the devices turn their outputs off.

Alternatively, if the D-pin is tied to GND, only the channel that has been detected with a fault is safely

deactivated.

Datasheet

23

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TLD2252-2EP

LITIX™ Basic+

Load diagnosis

The capacitor value used at the D-pin, C_D, sets the delay times t_D(set/reset)according to the following equations:

ꢄ_ꢁ∙ ꢅ_ꢁ(ꢀℎ)

(6.1)

ꢀ_{ꢁ(ꢂꢃꢀ)}

=

ꢆ_{ꢁ(ꢇꢈꢉꢊꢀ )}

ꢄ_ꢁ∙ ꢌꢅ_ꢁ(ꢄꢍ)− ꢅ_ꢁ(ꢀℎ)ꢎ

(6.2)

ꢀ_{ꢁ(ꢋꢃꢂꢃꢀ )}

=

ꢆ_ꢁ(ꢏꢁ)

6.2

Overtemperature (OT), Open Load (OL) and short OUTx to GND (SC)

The behavior of the device during overload conditions that lead to an excess of internal heating up to

overtemperature condition, is already described in Chapter 5.

Open load (OL) and OUTx shorted to GND (SC) diagnosis features are also integrated in the TLD2252-2EP.

An open load condition is detected if the voltage drop over one of the output stages V_PSxis below the threshold

V

_PSx(OL)at least for a filter time t_fault

A short to GND condition is detected if the voltage of one output stages V_OUTxis below the threshold V_OUTx(SC)at

least for a filter time t_fault

.

6.2.1

Fault management (D-pin open or connected with a capacitor to GND)

With D-pin open or connected with a capacitor to GND configuration, it is possible to switch off all the channels

which share a common error network, without the need of an auxiliary microcontroller. For more details refer

also to the timing diagram of Figure 14, Figure 15 and Figure 16.

If there is an OL or SC condition on one of the outputs, a pull-up current I_OUT(fault)then flows out from the

affected channel, replacing the configured output current (but limited by the actual load impedance, e.g.

reduced to zero with an ideal open load). Under these conditions, the ERRN pin starts sinking a current

I_ERRN(fault)toward GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level

below V_ERRN(fault)

.

After t_D(set), the voltage V_D(th)is reached at D-pin, the PWMO pin is pulled down and the IN_SETx goes in a weak

pull-down state with a current consumption I_{IN_SETx(fault)}after an additional latency time t_{IN_SETx(del)}. The ERRN

low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy.

The OL and SC error conditions are not latched: as soon as the fault condition is no longer present (at least for

a filter time t_fault) ERRN goes back to high impedance. When its voltage is above V_ERRN(fault), the D-pin voltage

starts decreasing and after t_D(reset)goes below (V_D(th)- V_D(th,hys)). Then the IN_SETx voltages go up to V_{IN_SETx(ref)}

,

again after a time t_{IN_SETx(del)}: at this point, the output stages are activated again. The total time between the

fault removal and the IN_SET reactivation t_ERR(reset)is extended by an additional latency which depends on the

external ERRN pin pull-up and filter circuitry.

Datasheet

24

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TLD2252-2EP

LITIX™ Basic+

Load diagnosis

V_{IN_SET}

V

IN _SET (ref)

t

t_{IN _SET (del)}

V_ERRN

VER R N(fault)

V_D

V_{D(th, hys)}

V_{D( th)}

t_D(set)

t_D(rese)t

t_{ERR(res et)}

t_fault

V_OUT

t_fault

V_S

V_S– V_{PS (O L)}

V_F

open load

occurs

open load

disappears

t

Figure 14 Open load condition timing diagram example (D-pin unconnected or connected to external

capacitor to GND, V_Frepresents the typical forward voltage of the output load)

Datasheet

25

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TLD2252-2EP

LITIX™ Basic+

Load diagnosis

V_{IN_SET}

V

IN _SET (ref)

t

t_{IN_SET (del)}

V_ERRN

VER R N(fault)

V_D

V_{D(th, hys)}

VD (th)

t_D(set)

t_D(reset)

t_{ERR(res et)}

t_fault

V_OUT

t_fault

V_S

V_F

V_{O U T(SC )}

t

short circuit

occurs

short circuit

disappears

Figure 15 Short circuit to GND condition timing diagram example (D-pin not connected or connected

to external capacitor to GND, V_Fxyzrepresents the forward voltage of the output loads)

Datasheet

26

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TLD2252-2EP

LITIX™ Basic+

Load diagnosis

V_{IN _SE T}

V_{IN_SE T(ref)}

t

t_{IN_SET(del)}

V_ERRN

V_{ER RN (fault)}

V_D

V_D(th)

t_D(set)

t_D(reset)

T_j

t_ERR(reset)

t_fault

T_JSD

T_{J SD}- T_{JSD(H YST)}

t

over temp.

occurs

over temp.

disappear

Figure 16 Overtemperature condition timing diagram example (D-pin not connected or connected to

external capacitor to GND)

6.2.2

Fault management (D-pin connected to GND)

With D-pin connected to GND configuration, it is possible to deactivate only the channel under fault

conditions, still sharing ERRN pin in a common error network with other devices of LITIX™ Basic+ family.

If there is fault condition on one of the outputs, a pull-up current I_OUT(fault)flows out from the affected channel,

replacing the configured output current (but limited by the actual load impedance, e.g. reduced to zero with

an ideal open load). Under fault conditions the ERRN pin starts sinking a current I_ERRN(fault)to ground and the

voltage level on this pin will drop below V_ERRN(fault)if the external pull-up resistor is properly dimensioned. The

ERRN low voltage can also be used as input signal for a µC to perform the desired diagnosis policy.

Datasheet

27

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Load diagnosis

The fault status is not latched: as soon as the fault condition is no longer present (at least for a filter time t_fault),

ERRN goes back to high impedance and, once its voltage is above V_ERRN(fault), finally the output stages are

activated again.

Examples of open load or short to GND diagnosis with D-pin open or connected to GND are shown in the timing

diagrams of Figure 17 and Figure 18.

V_{IN _SE T}

V_{IN_SE T(ref)}

t

V_ERRN

V_{ER RN (fault)}

t

t_fault

V_OUT

V_S

V_S– V_{PS (O L)}

V_F

open load

occurs

open load

disappears

t

Figure 17 Open load condition timing diagram example (D-pin connected to GND, V_Frepresents the

forward voltage of the output load)

Datasheet

28

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Load diagnosis

V_{IN_SET}

V

IN_SET (ref)

t

V_ERRN

V_{ER R N( fault)}

t_fault

V_OUT

V

S

V_F

V_{O U T(SC )}

t

short circuit

occurs

short circuit

disappears

Figure 18 Short circuit condition timing diagram example (D-pin connected to GND, V_Frepresents the

forward voltage of the output load)

Datasheet

29

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Load diagnosis

V_{IN _SE T}

V_{IN_SE T(ref)}

t

V_ERRN

V_{ER RN (fault)}

t_fault

T_j

T_JSD

T_{J SD}- T_{JSD(H YST)}

t

over temp.

occurs

over temp.

disappear

Figure 19 Overtemperature condition timing diagram example (D-pin connected to GND)

6.3

Electrical characteristics: Load diagnosis and Overload management

Table 8

Electrical Characteristics: Fault management

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

IN_SET fault current

I_{IN_SETx(fault)}

–

10

µA

¹⁾V_S> 8 V

V_OUTx= 3.6 V

_ERRN= 0 V

P_7.5.1

V

V_{IN_SETx}= 1 V

D open

V

_ENx> V_DENx(th,max)

¹⁾V_S> 8 V

_ERRN= 0.8 V

Fault condition

_ENx> V_DENx(th,max)

ERRN fault current

I_ERRN(fault)

2

–

mA

P_7.5.2

V

Datasheet

30

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Load diagnosis

Table 8

Electrical Characteristics: Fault management (cont’d)

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETx}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

ERRN input threshold

OL detection threshold

SC detection threshold

Fault detection current

V_ERRN(th)

V_PSx(OL)

V_OUTx(SC)

I_OUTx(fault)

0.8

2.0

V

¹⁾V_S> 8 V

P_7.5.3

P_7.5.5

P_7.5.6

P_7.5.7

0.2

0.8

50

–

0.4

V

V_S> 8 V

_ENx> V_{DENx(th, max)}

V_S> 8 V

_ENx> V_{DENx(th, max)}

V_S> 8 V

V

1.35

180

V

µA

V

_OUTx= 0 V

_ENx> V_{DENx(th, max)}

D-pin

Threshold voltage for

function de-activation

V_D(th)

1.4

–

1.7

2

–

V

V_S> 8 V

_ENx= 5.5 V

¹⁾V_S> 8 V

P_7.5.8

P_7.5.9

V

Threshold hysteresis

Fault pull-up current

Pull-down current

V_D(hys)

100

mV

V

_ENx= 5.5 V

_OUTx= V_OUTx(OL)

I_D(fault)

20

40

35

60

50

95

µA

V_S> 8 V

_OUTx= V_OUTx(OL)

P_7.5.10

P_7.5.11

V

V_D= 2 V

I_D(PD)

V_S> 8 V

V_ENx= 5.5 V

V_D= 1.4 V

V

_ERRN= 2 V

V_PSx= 3 V

No fault conditions

Internal clamp voltage

V_D(CL)

4

–

6

V

V_S> 8 V

P_7.5.12

V

_OUTx= V_OUTx(OL)

D-pin open

Timing

Fault to ERRN activation

delay

t_fault

40

–

150

10

µs

¹⁾V_S> 8 V

P_7.5.19

P_7.5.20

V

_OUTxrising from

5 V to V_S

V_ENx> V_{DENx(th, max)}

¹⁾V_S> 8 V

Fault appearance/removal t_{IN_SET(del)}

to IN_SET

deactivation/activation

delay

OUTx open

D rising from 0 V to

5 V

V

_ENx> V_{DENx(th, max)}

1) Not subjected to production test: specified by design.

Datasheet

31

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

PWM control (Digital dimming)

7

PWM control (Digital dimming)

Digital dimming via PWM control is commonly practiced to adjust luminous intensity, preventing color shift of

the LED light source.

7.1

PWM unit

V_PWMI(H)

I_{PWM_SET}

-

+

R

S

Q

PWMI

-

+

I_{PWM_RST}

V_PWMI(L)

PWMO

PWM_SET

PWM_RST

I_{PWM_SET}

I_{PWM_RST}

V_{PWM_RST(ref)}

V_{PWM_SET(ref)}

Figure 20 PWM unit concept diagram (including PWMO drive and typical external circuitry)

The PWM unit can be configured connecting a resistor on each of PWM_SET and PWM_RST configuration pins

and a capacitor to the PWMI pin. This setup (provided that V_EN> V_EN(th)and V_S> V_SUV(ON)) enables the internal

Pulse Width Modulation (PWM) generator to drive the PWMO pin with a digital signal, which represents the

desired PWM frequency and Duty Cycle (DC).

With reference to the block diagram of Figure 20 the current flowing through PWM_SET and PWR_RST

reference pins (I_{PWM_SET}and I_{PWM_RST}) are replicated to charge or discharge the capacitor C_PWMI

The following figure shows the charging and discharging phases defined by the chosen external components,

according to Figure 21 and the internal PWM unit.

Datasheet

32

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

PWM control (Digital dimming)

V_PWMI

PWMI OFF  DC=0%

V_{PWMI_H}

Internal PWM

V_{PWMI_L}

PWMI ON  DC=100%

t

PWMO

t

Figure 21 PWMI operating voltages and timing diagram example

The PWM typical characteristics can be adjusted using the formulas below.

R_{PWM _ SET}C_PWMI

C_PWMI

(7.1)

(7.2)

(7.3)

(

)

(

)

t_{PWM (ON )}

=

V_{PWMI (H )}−V_{PWMI (L)}

=

V_{PWMI (H )}−V_{PWMI (L)}

I_{PWM _ SET}

V_{REF _ SET}

R_{PWM _ RST}C_PWMI

C_PWMI

(

)

(

t_{PWM (OFF )}

=

V_{PWMI (H )}−V_{PWMI (L)}

=

V_{PWMI (H )}−V_{PWMI (L)}

I_{PWM _ RST}

V_{REF _ RST}

V_{REF _ SET / RST}

1

f_PWMI

=

(

)

t_PWMI(ON)+ t_PWMI(OFF)V_{PWMI(H )}−V_PWMI(L)R_{PWM _ SET}+ R_{PWM _ RST}C_PWMI

V_{REF_SET/RST}is equal to 1.22 V. See P_8.4.12 and P_8.4.13.

t_PWMI(ON)

R_{PWM_ SET}

(7.4)

DC_PWMI

=

t_PWMI(ON)+t_PWMI(OFF)R_{PWM_ SET}+ R_{PWM_ RST}

From these equations, the proper value C_PWMI, R_{PWM_SET}and R_{PWM_RST}can be calculated, according to the

electrical characteristics defined in Table 9.

7.2

Direct control of PWMI

The PWM engine does not drive directly the internal channels via the PWMO output pin, the PWM control can

be used to externally synchronize both output channels as well as other devices of the LITIX™ Basic+ family.

PWMI input can be also controlled by the PWMO output of another device of LITIX™ Basic+ family or,

alternatively, a push-pull output stage of a microcontroller: the host device decides the digital dimming

characteristics by applying the proper control cycle in order to set the “on”/”off” timing, according to the

chosen dimming function.

Datasheet

33

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

PWM control (Digital dimming)

7.3

Timing diagrams

V_{PWM I}

t

t_{del(PWM O,H)}

t_del(PWMO,L)

V_{PWM O}

V_PW

MI (H,max)

MI (L,m in)

V_PW

Figure 22 PWMO delay timing diagram

7.4

Electrical characteristics PWM engine

Table 9

Electrical characteristics: PWM engine

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETn}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

1.7

Unit Note or

Test Condition

Number

Min.

Max.

PWMI low threshold

PWMI high threshold

V_PWMI(L)

V_PWMI(H)

∆V_PWMI

1.5

2

V

V_S= 8 V to 18 V

V_ENX= 5.5 V

P_8.4.1

P_8.4.2

P_8.4.3

2.5

2.7

1.0

3

V_S= 8 V to 18 V

V_ENX= 5.5 V

¹⁾V_S= 8 V to 18 V

V_ENX= 5.5 V

PWMI switching threshold

difference V_PWMI(H)- V_PWMI(L)

0.85

1.15

V

_PSX= 3 V

PWMO Duty Cycle

DC_PWMO

9.5

47

10

50

10.5

53

%

¹⁾²⁾V_S= 8 V to 18 V P_8.4.9

I

_{PWM_SET}= 270 µA

_{PWM_RST}= 30 µA

C_PWMI= 110 nF

_PWMO= 50 pF

¹⁾²⁾V_S= 8 V to 18 V P_8.4.8

C

PWMO Duty Cycle

DC_PWMO

I

_{PWM_SET}= 55 µA

_{PWM_RST}= 55 µA

C_PWMI= 110 nF

_PWMO= 50 pF

C

Datasheet

34

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

PWM control (Digital dimming)

Table 9

Electrical characteristics: PWM engine (cont’d)

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETn}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

80

Unit Note or

Test Condition

Number

Min.

Max.

PWMO Duty Cycle

DC_PWMO

78

82

%

¹⁾²⁾V_S= 8 V to 18 V P_8.4.11

I

_{PWM_SET}= 35 µA

_{PWM_RST}= 140 µA

C_PWMI= 110 nF

_PWMO= 50 pF

¹⁾V_S= 12.8 V

_PS= 2 V

_{IN_SET}= 12.2 kΩ

R_{PWM_SET}= 4.5 kΩ

C

Combined output current

accuracy

I_RT1(avg)

2.86

3.81

3

4

3.14

4.19

mA

P_8.4.22

P_8.4.24

V

R

I_{IN_SET1}*K_RT1*DC_PWMO

R

_{PWM_RST}= 40.5 kΩ

C

_PWMI= 110 nF

C_PWMO= 50 pF

T_J= 25 °C

¹⁾V_S= 12.8 V

Combined output current

accuracy

I_RT2(avg)

mA

V

_PS= 2 V

_{IN_SET}= 18.3 kΩ

R_{PWM_SET}= 4.5 kΩ

I_{IN_SET2}*K_RT2*DC_PWMO

R

_{PWM_RST}= 40.5 kΩ

C

_PWMI= 110 nF

C_PWMO= 50 pF

T_J= 25 °C

1)

PWM_SET reference voltage V_{PWM_SET(ref)}1.184 1.22

PWM_RST reference voltage V_{PWM_RST(ref)}1.184 1.22

1.256

1.6

–

V

= 5.5 V

P_8.4.12

P_8.4.13

P_8.4.14

ENx

V

1)

_PSx= 3 V

V

= 5.5 V

ENx

V

_PSx= 3 V

PWMO OFF pull-up current

I_PWMO(OFF)

0.75

-1.6

–

mA

V_S= 8 V to 18 V

V

_ENx= 5.5 V

_PWMI= 3 V

V_PWMO= 3 V

No fault conditions

PWMO ON pull-down current I_PWMO(ON)

-0.75

-0.4

mA

V_S= 8 V to 18 V

P_8.4.15

P_8.4.25

V

_ENx= 5.5 V

V_PWMI= 1.5 V

_PWMO= 1.5 V

V

No fault conditions

¹⁾V_S= 8 V to 18 V

V

_ENx= 5.5 V

V_PWMI= 1.5 V

_PWMO= 1 V

No fault conditions

V

Datasheet

35

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

PWM control (Digital dimming)

Table 9

Electrical characteristics: PWM engine (cont’d)

T_J= -40°C to +150°C; V_S=5.5 V to 18 V; R_{IN_SETn}= 10 kΩ; all voltages with respect to GND, positive current flowing

into input and I/O pins, positive current flowing out from output pins (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Timing

PWMO activation delay time t_del(PWMO,L)

–

1

µs

ns

¹⁾³⁾V_S= 8 V to 18 V P_8.4.16

V_ENx= 5.5 V

C

_PWMO= 50 pF

_PWMIfalling from

5 V to 0 V

_PWMO= 1.5 V

V

PWMO deactivation delay

time

t_del(PWMO,H)

–

1

¹⁾³⁾V_S= 8 V to 18 V P_8.4.17

_ENn= 5.5 V

C_PWMO= 50 pF

_PWMIrising from

0 V to 5 V

_PWMO= 3 V

V

PWMO delay time matching ∆t_del(PWMO)-200

_del(PWMO,H)- t_del(PWMO,L)

200

¹⁾³⁾V_S= 12.8 V

T_J= 25°C

P_8.4.21

t

1) Not subjected to production test. specified by design

2) Measured at PWMO output waveform (V_PWMOcrossing 3 V when rising from V_PWMO(L), 2 V when falling from V_PWMO(H)

)

3) Refer to Figure 22.

Datasheet

36

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Application information

8

Application information

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

V_TAIL

V_STOP

Supply

Protection

TLD2252-2EP

PWMI

PWM_SET

PWM_RST

IN_SET1

GND

IN_SET2

PWMO

OUT1

OUT2

Figure 23 Application diagram example

Note:

This is a very simplified example of an application circuit. The function must be verified in the real

application.

Datasheet

37

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Package outline

9

Package outline

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Figure 24 PG-TSDSO-14

Green product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

Datasheet

38

Rev. 1.10

2021-06-15

TLD2252-2EP

LITIX™ Basic+

Revision History

10

Revision History

Revision Date

Changes

1.10

1.00

2021-06-15 Updated P_5.2.17, P_5.2.14, P_5.2.15

2019-09-26 Initial datasheet created

Datasheet

39

Rev. 1.10

2021-06-15

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2021-06-15

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

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any applications where a failure of the product or any

consequences of the use thereof can reasonably be

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a written document signed by

Document reference

LITIX™ Basic+ TLD2252-2EP


型号：	TLD2252-2EP
厂家：	Infineon
描述：	The TLD2252-2EP is designed to control LEDs with a current up to 120 mA. In typical automotive applications the device is capable of driving 3 red LEDs per chain (total 6 LEDs) with a current up to 100 mA and even above, if not limited by the overall system thermal properties. Practically, the output current is controlled by an external resistor or reference source, independently from load and supply voltage changes.
文件：	总40页 (文件大小：1154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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