TLD55411QV [INFINEON]
H-Bridge DC/DC Controller with SPI Interface;
| 型号： | TLD55411QV |
| 厂家： | 
Infineon |
| 描述： | H-Bridge DC/DC Controller with SPI Interface |
| 文件： | 总82页 (文件大小：4341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Infineon® LITIX™ Power Flex
H-Bridge DC/DC Controller with SPI
Interface
H-Bridge DC/DC Controller for High Power LED Lighting
TLD5541-1QV
Data Sheet
Rev. 1.0, 2016-05-20
Automotive Power
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Table of Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
5
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Different Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Different Possibilities to RESET the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
5.2
5.3
6
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.5
6.6
Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Regulator Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Adjustable Soft Start Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Switching Frequency setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operation of 4 switches H-Bridge architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Boost mode (VIN < VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Buck mode (VIN > VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Buck-Boost mode (VIN ~ VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Fast Output Discharge Operation Mode - Multi Floating Switches Topology . . . . . . . . . . . . . . . . . . . 27
Flexible current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programming Output Voltage (Constant Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.7
6.8
7
7.1
7.2
Digital Dimming Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8
Analog Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LED current calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1
8.2
8.3
9
9.1
9.2
Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IVCC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10
Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Overvoltage, Open Load, Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Short Circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Open Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Input voltage monitoring, protection and power derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Input current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Output current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Device Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
10.4
10.5
10.6
Data Sheet
2
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Table of Contents
10.7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11
Infineon FLAT SPECTRUM Featureset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Synchronization Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
EMC optimized schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1
11.2
11.3
11.4
11.5
12
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.1
12.2
12.3
12.4
12.5
12.6
12.6.1
12.6.2
13
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.1
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14
15
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Data Sheet
3
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller for High Power LED
Lighting
TLD5541-1QV
1
Overview
Features
•
MOSFET H-Bridge with Single Inductor DC/DC Controller for HIGH
POWER BUCK-BOOST LED control
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Constant Current and Constant Voltage Regulation
Wide VIN Range (Device 4.5V to 40V, Power Stage 4.5V to 55V)
Wide LED forward voltage Range (2V up to 55V)
Maximum Efficiency in every condition (up to 96%)
Limp Home Function (Fail Safe Mode)
PG-VQFN-48-31
Flexible current sense (Highside or Lowside)
LED current accuracy+/-3% at Tj=25° and 4% over the whole automotive temperature range
16bit SPI for diagnostics and control, providing daisy chain capability
EMC optimized device: Features an auto Spread Spectrum concept to ensure best in class EMC performance
Provides output current accuracy calibration for improved system accuracy
Provides improved dynamic behavior (load jump behavior) and adjustable Short to GND threshold
LED and Input current sense with dedicated monitor Outputs
Smart power protection features for device and load (open load, short of Load, Overtemperature)
Switching Frequency Range from 200 kHz to 700 kHz
Capability to supply Gate Drivers via external Voltage Regulator
Adjustable Soft Start
Enhanced Dimming features to adjust average LED current and PWM dimming
Available in a small thermally enhanced PG-VQFN-48-31 package
Automotive AEC Qualified
Description
The TLD5541-1QV is a synchronous MOSFET H-Bridge DC/DC controller with built in protection features and
SPI interface. This concept is beneficial for driving high power LEDs with maximum system efficiency and
minimum number of external components. The TLD5541-1QV offers both analog and digital (PWM) dimming.The
switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an external clock
source. A built in programable Spread Spectrum switching frequency modulation and the forced continuous
current regulation mode improve the overall EMC behavior. Furthermore the current mode regulation scheme
provides a stable regulation loop maintained by small external compensation components. The adjustable soft
start feature limits the current peak as well as voltage overshoot at start-up. The TLD5541-1QV is suitable for use
in the harsh automotive environment.
Type
Package
Marking
TLD5541-1QV
Data Sheet
PG-VQFN-48-31
TLD55411QV
4
Rev.1.0,2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Overview
Table 1
Product Summary
Power Stage input voltage range
Device Input supply voltage range
VPOW
4.5 V … 55 V
4.5 V … 40 V
VVIN
Maximum output voltage (depending by the
application conditions)
VOUT(max)
55 V as LED Driver Boost Mode
50 V as LED Driver Buck Mode
50 V as Voltage regulator
Switching Frequency range,
fSW
200 kHz... 700 kHz
Typical NMOS driver on-state resistance at Tj =
RDS(ON_PU)
2.3 Ω
25°C (Gate Pull Up)
Typical NMOS driver on-state resistance at Tj =
25°C (Gate Pull Down)
RDS(ON_PD)
fSCLK(MAX)
1.2 Ω
SPI clock frequency
5 MHz
Protective Functions
•
•
•
•
•
Over load protection of external MOSFETs
Shorted load, open load, output overvoltage protection
Input overvoltage and undervoltage protection
Thermal shutdown of device with autorestart behavior
Electrostatic discharge protection (ESD)
Diagnostic Functions
•
•
•
•
Latched diagnostic information via SPI
Open load detection in ON-state
Device Overtemperature shutdown and Temperature Prewarning
Smart monitoring and advanced functions provide ILED and IIN information
Limp Home Function
Limp Home activation via LHI pin
•
Applications
•
•
•
Especially designed for driving high power LEDs in automotive applications
Automotive Exterior Lighting: full LED headlamp assemblies (Low Beam, High Beam, Matrix Beam, Pixel Light)
General purpose current/voltage controlled DC/DC LED driver
Data Sheet
5
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Block Diagram
2
Block Diagram
IVCC
Internal Supply
Power
On Reset
LDO
VIN
IVCC_EXT
GATE
DRIVER
BST1
SYNC
FREQ
Oscillator
Auto-Spread
Spectrum
Generator
HSGD1
SWN1
BUCK
LOGIC
Slope Comp.
IVCC_EXT
VIN
EN/INUVLO
INOVLO
Voltage
Protection
+ Enable
Thermal Protection
+ Prewarning
LSGD1
PGND1
PWM
Generator
Diagnosis Open Load + Short
to GND
IVCC_EXT
Soft Start
SOFT_START
Limp Home Mode
Digital Dimming
LSGD2
LHI
PGND2
PWMI
BOOST
LOGIC
Analog Dimming Pin
SET
SWN2
HSGD2
BST2
Fast Output
Discharge
Operation
Mode
Output
current
accuracy
calibration
SWCS
Switch Current
Error Amplifier
SGND
VDD
8 Bit DAC
Analog
Dimming
CSN
SCLK
SI
SPI
Voltage Loop
Feedback
VFB
SO
Input
Current
Monitor
LED
Current
Monitor
FBH
FBL
Input/diagnosis
register
Feedback Error Amplifier
IIN1 IIN2
VSS
AGND
COMP
Figure 1
Block Diagram - TLD5541-1QV
Data Sheet
6
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
Figure 2
Pin Configuration - TLD5541-1QV
Data Sheet
7
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Pin Configuration
3.2
Pin Definitions and Functions
1)
Pin
Symbol
I/O
Function
Power Supply
1, 12,
n.c.
-
Not connected, tie to AGND on the Layout;
15, 21,
32, 33,
45, 48
44
31
47
VIN
-
-
I
Power Supply Voltage;
Supply for internal biasing.
VDD
Digital GPIO Supply Voltage;
Connect to reverse voltage protected 5V or 3.3V supply.
IVCC_EXT
PD External LDO input;
Input to alternatively supply internal Gate Drivers via an external LDO.
Connect to IVCC pin to use internal LDO to supply gate drivers. Must not
be left open.
5, 8
26
40
-
PGND1, 2
VSS
-
-
-
-
Power Ground;
Ground for power potential. Connect externally close to the chip.
Digital GPIO Ground;
Ground for GPIO pins
AGND
EP
Analog Ground;
Ground Reference
Exposed Pad;
Connect to external heatspreading Cu area (e.g. inner GND layer of
multilayer PCB with thermal vias).
Gate Driver Stages
2
HSGD1
O
O
Highside Gate Driver Output 1;
Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT
superimposed on the switch node voltage SWN1. Connect to gate of
external switching MOSFET.
11
HSGD2
Highside Gate Driver Output 2;
Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT
superimposed on the switch node voltage SWN2. Connect to gate of
external switching MOSFET.
6
7
LSGD1
LSGD2
O
O
Lowside Gate Driver Output 1;
Drives the lowside n-channel MOSFET between GND and VIVCC_EXT
Connect to gate of external switching MOSFET.
Lowside Gate Driver Output 2;
Drives the lowside n-channel MOSFET between GND and VIVCC_EXT
Connect to gate of external switching MOSFET.
4
9
SWN1
SWN2
IO
IO
Switch Node 1;
SWN1 pin swings from a diode voltage drop below ground up to VIN
Switch Node 2;
SWN2 pin swings from ground up to a diode voltage drop above VOUT
Data Sheet
8
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Pin Configuration
1)
Pin
Symbol
I/O
Function
46
IVCC
O
Internal LDO output;
Used for internal biasing and gate driver supply. Bypass with external
capacitor close to the pin. Pin must not be left open.
Inputs and Outputs
37
23
25
41
LHI
I
-
-
I
PD Limp Home Input Pin;
Used to enter in Limp Home state during Fail Safe condition.
TEST1
TEST2
EN/INUVLO
Test Pin;
Used for Infineon end of line test, connect to GND in application
Test Pin;
Used for Infineon end of line test, connect to GND in application
PD Enable/Input Under Voltage Lock Out;
Used to put the device in a low current consumption mode, with additional
capability to fix an undervoltage threshold via external components. Pin
must not be left open.
35
34
FREQ
SYNC
I
I
Frequency Select Input;
Connect external resistor to GND to set frequency.
PD Synchronization Input;
Apply external clock signal for synchronization
24
13
PWMI
FBH
I
I
PD Control Input; Digital input 5Vor 3.3V.
Output current Feedback Positive;
Non inverting Input (+)
14
3
FBL
I
Output current Feedback Negative;
Inverting Input (-)
BST1
IO
Bootstrap capacitor;
Used for internal biasing and to drive the Highside Switch HSGD1. Bypass
to SWN1 with external capacitor close to the pin. Pin must not be left open.
10
BST2
IO
Bootstrap capacitor;
Used for internal biasing and to drive the Highside Switch HSGD2. Bypass
to SWN2 with external capacitor close to the pin. Pin must not be left open.
17
18
SWCS
SGND
I
I
Current Sense Input;
Inductor current measurement - Non Inverting Input (+)
Current Sense Ground;
Inductor current sense - Inverting Input (-)
Route as Differential net with SWCS on the Layout
42
IIN1
I
Input Current Monitor Positive;
Non Inverting Input (+), connect to VIN if input current monitor is not
needed
43
19
38
IIN2
I
Input Current Monitor Negative;
Inverting Input (-), connect to VIN if input current monitor is not needed
COMP
O
O
Compensation Network Pin;
Connect R and C network to pin for stability phase margin adjustment
SOFT_START
Softstart configuration Pin;
Connect a capacitor CSOFT_START to GND to fix a soft start ramp default
time.
Data Sheet
9
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Pin Configuration
1)
Pin
Symbol
I/O
Function
36
INOVLO
I
Input Overvoltage Protection Pin;
Define an upper voltage threshold and switches OFF the device in case of
overvoltages on the VIN supply. Must not be left open.
20
VFB
I
Voltage Loop Feedback Pin;
VFB is intended to set output protection functions.
22
39
SET
I
Analog current sense adjustment Pin;
IINMON
O
Input current monitor output;
Monitor pin that produces a voltage that is 20 times the voltage VIN1-IN2
IINMON will be equal 1V when VIIN1-VIIN2=50mV
.
16
IOUTMON
O
Output current monitor output;
Monitor pin that produces a voltage that is 200mV + 8 times the voltage
FBH-FBL. IOUTMON will be equal 1.4V when VFBH-FBL = 150mV.
V
SPI
30
29
28
27
SI
I
PD Serial data in; Digital input 5V or 3.3V.
SCLK
CSN
SO
I
PD Serial clock; Digital input 5V or 3.3V.
I
PU SPI chip select; Digital input 5V or 3.3V. Active LOW
Serial data out; Digital output, referenced to VDD
O
1) O: Output, I: Input,
PD: pull-down circuit integrated,
PU: pull-up circuit integrated
Data Sheet
10
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 2
Absolute Maximum Ratings1)
Tj = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
Typ. Max.
Supply Voltages
VIN
Supply Input
VVIN
-0.3
-0.3
-0.3
–
–
–
60
6
V
V
V
–
P_4.1.1
P_4.1.2
P_4.1.3
VDD
VVDD
VIVCC
–
–
Digital supply voltage
IVCC
6
Internal Linear Voltage Regulator Output
voltage
IVCC_EXT
VIVCC_EXT -0.3
–
6
V
–
P_4.1.4
External Linear Voltage Regulator Input
voltage
Gate Driver Stages
LSGD1,2 - PGND1,2
Lowside Gatedriver voltage
VLSGD1,2- -0.3
–
–
–
–
–
–
–
–
–
5.5
5.5
60
V
V
V
V
V
V
V
V
V
–
–
–
–
–
–
–
–
–
P_4.1.54
P_4.1.55
P_4.1.6
P_4.1.7
P_4.1.8
P_4.1.9
P_4.1.10
P_4.1.11
P_4.1.28
PGND
HSGD1,2 - SWN1,2
Highside Gatedriver voltage
VHSGD1,2- -0.3
SWN1,2
SWN1, SWN2
switching node voltage
VSWN1, 2 -1
(BST1-SWN1), (BST2-SWN2)
Boostrap voltage
VBSTx-
-0.3
-0.3
-0.3
-0.3
-0.5
6
SWNx
BST1, BST2
Boostrap voltage related to GND
VBST1, 2
65
SWCS
VSWCS
VSGND
0.3
0.3
0.5
0.3
Switch Current Sense Input voltage
SGND
Switch Current Sense GND voltage
SWCS-SGND
Switch Current Sense differential voltage
VSWCS-
SGND
PGND1,2
VPGND1,2 -0.3
Power GND voltage
High voltage Pins
IIN1, IIN2
Input Current monitor voltage
VIIN1, 2
-0.3
–
–
60
V
V
–
–
P_4.1.12
P_4.1.13
IIN1-IIN2
VIIN1-IIN2 -0.5
0.5
Input Current monitor differential voltage
Data Sheet
11
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
General Product Characteristics
Table 2
Absolute Maximum Ratings1) (cont’d)
Tj = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
Typ. Max.
FBH, FBL
Feedback Error Amplifier voltage
VFBH, FBL -0.3
–
60
V
–
P_4.1.14
P_4.1.15
FBH-FBL
Feedback Error Amplifier differential
voltage
VFBH-FBL -0.5
–
0.5
V
–
–
EN/INUVLO
VEN/INUVLO -0.3
–
60
V
P_4.1.16
Device enable/input undervoltage
lockout
Digital (I/O) Pins
PWMI
Digital Input voltage
VPWMI
VCSN
VSCLK
VSI
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
–
–
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
V
V
–
–
–
–
–
–
–
P_4.1.17
P_4.1.18
P_4.1.19
P_4.1.20
P_4.1.21
P_4.1.22
P_4.1.58
CSN
Voltage at Chip Select pin
SCLK
Voltage at Serial Clock pin
SI
Voltage at Serial Input pin
SO
VSO
Voltage at Serial Output pin
SYNC
VSYNC
VLHI
Synchronization Input voltage
LHI
Limp Home Input Voltage
Analog Pins
VFB
VVFB
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
–
–
–
5.5
5.5
5.5
3.6
3.6
3.6
3.6
5.5
V
V
V
V
V
V
V
V
–
–
–
–
–
–
–
–
P_4.1.25
P_4.1.26
P_4.1.29
P_4.1.30
P_4.1.31
P_4.1.32
P_4.1.33
P_4.1.34
Loop Input voltage
INOVLO
Input overvoltage lockout
VINOVLO
VSET
SET
Analog dimming Input voltage
COMP
VCOMP
Compensation Input voltage
SOFT_START
Softstart Voltage
VSOFT_STA -0.3
RT
FREQ
VFREQ
-0.3
-0.3
Voltage at frequency selection pin
IINMON
Voltage at input monitor pin
VIINMON
IOUTMON
VIOUTMON -0.3
Voltage at output monitor pin
Temperatures
Junction Temperature
Tj
-40
–
150
°C
–
P_4.1.35
Data Sheet
12
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
General Product Characteristics
Table 2
Absolute Maximum Ratings1) (cont’d)
Tj = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
Typ. Max.
Storage Temperature
Tstg
-55
–
150
°C
–
P_4.1.36
ESD Susceptibility
ESD Resistivity of all Pins
ESD Resistivity to GND
ESD Resistivity of corner Pins to GND
VESD,HBM -2
VESD,CDM -500
VESD,CDM_ -750
corner
–
–
–
2
kV
V
HBM2)
CDM3)
CDM3)
P_4.1.37
P_4.1.38
P_4.1.39
500
750
V
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k ꢀ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
4.2
Functional Range
Table 3
Functional Range
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
Typ. Max.
1)
Device Extended Supply Voltage
Range
VVIN
VVIN
4.5
–
40
V
P_4.2.1
P_4.2.2
Device Nominal Supply Voltage
Range
8
–
36
V
–
1)
Power Stage Voltage Range
Digital Supply Voltage
Junction Temperature
VPOW
VDD
Tj
4.5
3
–
–
–
55
V
P_4.2.5
P_4.2.3
P_4.2.4
5.5
150
V
–
–
-40
°C
1) Not subject to production test, specified by design.
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Data Sheet
13
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
General Product Characteristics
Table 4
Parameter
Symbol
Values
Typ.
0.9
Unit Note /
Test Condition
Number
Min.
Max.
1) 2)
Junction to Case
RthJC
RthJA
–
–
–
–
K/W
K/W 3) 2s2p
P_4.3.1
P_4.3.2
Junction to Ambient
25
1) Not subject to production test, specified by design.
2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed to
ambient temperature). Ta=25°C; The IC is dissipating 1W.
3) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink
area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5 mm board. The 2s2p board
has 2 outer copper layers (2 x 70µm Cu) and 2 inner copper layers (2 x 35µm Cu). A thermal via (diameter = 0.3 mm and
25 µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner layer and
second outer layer (bottom) of the JEDEC PCB. Ta=25°C; The IC is dissipating 1W.
Data Sheet
14
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Power Supply
5
Power Supply
The TLD5541-1QV is supplied by the following pins:
•
•
•
VIN (main supply voltage)
VDD (digital supply voltage)
IVCC_EXT (supply for internal gate driver stages)
The VIN supply, in combination with the VDD supply, provides internal supply voltages for the analog and digital
blocks. In situations where VIN voltage drops below VDD voltage, an increased current consumption may be
observed at the VDD pin.
The SPI and IO interfaces are supplied by the VDD pin.
IVCC_EXT is the supply for the low side driver stages. This supply is used also to charge, through external
schottky diodes, the bootstrap capacitors which provide supply voltages to the high side driver stages. If no
external voltage is available this pin must be shorted to IVCC, which is the output of an internal 5V LDO.
The supply pins VIN, VDD and IVCC_EXT have undervoltage detections.
Undervoltage on VDD supply voltage prevents the activation of the gate driver stages and any SPI communication
(the SPI registers are reset). Undervoltage on IVCC_EXT or IVCC voltages forces a deactivation of the driver
stages, thus stopping the switching activity, but has no effect on the SPI register settings.
Moreover the double function pin EN/INUVLO can be used as an input undervoltage protection by placing a
resistor divider from VIN to GND (refer to Chapter 10.3).
If EN/INUVLO undervoltage is detected, it will turn-off the IVCC voltage regulator stop switching ,stop
communications and reset all the registers.
Figure 3 shows a basic concept drawing of the supply domains and interactions among pins VIN, VDD and
IVCC/IVCC_EXT.
VIN
VREG (5V)
R1
IVCC
Internal pre-regulated
EN/INUVLO
voltage Supply
Undervoltage
detection
R2
IVCC_EXT
VREG
digital
VREG
analog
LS - Drivers
HS - Drivers
PGND
BSTx
Undervoltage
detection
Bandgap
Reference
Register
Banks
VDD
SPI & I/O
LOGIC
SWNx
Figure 3
Power Supply Concept Drawing
Data Sheet
15
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Power Supply
Usage of EN/INUVLO pin in different applications
The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption
mode. An undervoltage threshold should be fixed by placing an external resistor divider (A) in order to avoid low
voltage operating conditions. This pin can be driven by a µC-port as shown in (B) .
A
B
Vin
Vin
VIN
VIN
R1
R2
R1
R2
EN/INUVLO
GND
EN/INUVLO
GND
µC Port
Figure 4
Usage of EN/INUVLO pin in different applications
Data Sheet
16
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Power Supply
5.1
Different Power States
TLD5541-1QV has the following power states:
•
•
•
•
SLEEP state
IDLE state
LIMP HOME state
ACTIVE state
The transition between the power states is determined according to these variables after a filter time of max. 3
clock cycles:
•
•
•
•
•
•
•
VIN level
EN/INUVLO level
IVCC level
IVCC_EXT level
VDD level
LHI level
DVCCTRL.IDLEbit state
The state diagram including the possible transitions is shown in Figure 5 .
The Power-up condition is entered when the supply voltage VVIN exceed its minimum supply voltage threshold
VVIN(ON)
.
SLEEP
When the device is powered it enters the SLEEP state, all outputs are OFF and the SPI registers are reset,
independently from the supply voltages at the pins VIN , VDD, IVCC, and IVCC_EXT. The current consumption is
low. Refer to parameters: IVDD(SLEEP), and IVIN(SLEEP)
.
The transition from SLEEP to ACTIVE state requires a specified time: tACTIVE
.
IDLE
In IDLE state, the current consumption of the device can reach the limits given by parameter IVDD (P_5.3.4). The
internal voltage regulator is working. Not all diagnosis functions are available (refer to Chapter 10 for additional
informations). In this state there is no switching activity, independently from the supply voltages VIN, VDD, IVCC
and IVCC_EXT. When VDD is available, the SPI registers are working and SPI communication is possible.
Limp Home
The Limp Home state is beneficial to fulfill system safety requirements and provides the possibility to maintain a
defined current/voltage level on the output via a backup control circuitry. The backup control circuitry turns on
required loads during a malfunction of the µC. For detailed info, refer to Chapter 8.
When Limp Home state is entered, SPI registers are reset to their default values and SPI communication is
possible but only in read mode (SPI registers can be read but cannot be written). In order to regulate the output
current/voltage, it is necessary that VIN and IVCC_EXT are present and above their undervoltage threshold.
ACTIVE
In active state the device will start switching activity to provide power at the output only when PWMI = HIGH. To
start the Highside gate drivers HSGDx the voltage level VBSTx - VSWNx needs to be above the threshold VBSTx-
VSWNx_UVth. In ACTIVE state the device current consumption via VIN and VDD is dependent on the external
MOSFET used and the switching frequency fSW
.
Data Sheet
17
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Power Supply
Power-up
LHI = LOW
EN/INUVLO = LOW
SLEEP
& EN/INUVLO = HIGH
EN/INUVLO = LOW
LHI = HIGH
& EN/INUVLO = HIGH
EN/INUVLO = LOW
LHI = HIGH
LIMP HOME
IDLE
VIN = LOW
or IVCC = LOW
VIN = HIGH
& IVCC = HIGH
EN/INUVLO = LOW
or IVCC_EXT = LOW
or VDD = LOW
& IVCC_EXT = HIGH
& VDD = HIGH
or DVCCTRL.IDLE = HIGH
& DVCCTRL.IDLE = LOW
LHI = LOW
ACTIVE
LHI = HIGH
Figure 5
Simplified State Diagram
5.2
Different Possibilities to RESET the device
There are several reset triggers implemented in the device.
After any kind of reset, the Transmission Error Flag (TER) is set to HIGH.
Under Voltage Reset:
EN/INUVLO: When EN/INUVLO is below VEN/INUVLOth (P_5.3.7), the SPI interface is not working and all the
registers are reset to their default values. In addition, the device enters SLEEP mode and the current consumption
is minimized.
VDD: When VVDD is below VVDD(UV) (P_5.3.6), the SPI interface is not working and all the registers are reset to their
default values.
Reset via SPI command:
There is a command available to RESET all registers to their default values (DVCCTRL.SWRST= HIGH).
Reset via Limp Home:
When Limp Home state is detected the registers are reset to the default values.
Data Sheet
18
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Power Supply
5.3
Electrical Characteristics
Table 5
EC Power Supply
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
Typ. Max.
Power Supply VIN
Input Voltage Startup
VVIN(ON)
–
–
–
4.7
4.5
V
V
VIN increasing;
P_5.3.1
V
V
EN/INUVLO = HIGH;
DD = 5 V;
IVCC = IVCC_EXT =
10 mA;
Input Undervoltage switch OFF VVIN(OFF)
–
VIN decreasing;
P_5.3.14
V
V
EN/INUVLO = HIGH;
DD = 5 V;
IVCC = IVCC_EXT =
10 mA;
Device operating current
IVIN(ACTIVE)
IVIN(SLEEP)
–
–
4.4
–
6
mA
µA
1)ACTIVE mode;
P_5.3.2
P_5.3.3
V
PWMI = 0 V;
VIN Sleep mode supply current
1.5
V
EN/INUVLO= 0 V;
V
CSN = VDD = 5 V;
VIN = 13.5 V;
IVCC=VIVCC_EXT= 0 V;
V
Digital Power Supply VDD
Digital supply current
IVDD
–
–
–
–
0.5
1.5
mA
µA
VIN = 13.5 V;
SCLK = 0 Hz;
PWMI = 0 V;
VEN=VCSN= VDD= 5 V;
P_5.3.4
P_5.3.5
f
V
Digital Supply Sleep mode
current
IVDD(SLEEP)
V
V
EN/INUVLO = 0 V;
CSN = VDD = 5 V;
VIN = 13.5 V;
V
IVCC= VIVCC_EXT = 0 V;
Undervoltage shutdown
threshold voltage
VVDD(UV)
1
–
3
V
V
CSN = VDD;
P_5.3.6
VSI = VSCLK = 0 V;
SO from LOW to
HIGH impedance;
EN/INUVLO Pin characteristics
Input Undervoltage falling
Threshold
VEN/INUVLOth 1.6
1.75
90
1.9
–
V
–
P_5.3.7
P_5.3.8
P_5.3.9
P_5.3.10
1)
EN/INUVLO Rising Hysteresis
VEN/INUVLO(h
–
mV
µA
µA
yst)
EN/INUVLO input Current LOW IEN/INUVLO(LO 0.45
0.89
2.2
1.34
3.3
V
V
EN/INUVLO = 0.8 V;
EN/INUVLO = 2 V;
W)
EN/INUVLO input Current HIGH IEN/INUVLO(HI 1.1
GH)
Data Sheet
19
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Power Supply
Table 5
EC Power Supply (cont’d)
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
Typ. Max.
LHI Pin characteristics
LOW level
VLHI(L)
VLHI(H)
ILHI(L)
ILHI(H)
0
-
0.8
5.5
18
V
–
P_5.3.16
P_5.3.17
P_5.3.18
P_5.3.19
HIGH level
2.0
6
-
V
–
L-Input pull-down current
H-Input pull-down current
Timings
12
30
μA
μA
V
V
LHI = 0.8 V;
LHI = 2.0 V;
15
45
1)
SLEEP mode to ACTIVE time
tACTIVE
–
–
0.7
ms
P_5.3.11
V
IVCC = VIVCC_EXT;
C
IVCC= 10µF;
VIN = 13.5 V;
DD = 5 V;
V
1) Not subject to production test, specified by design.
Data Sheet
20
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
6
Regulator Description
The TLD5541-1QV includes all of the functions necessary to provide constant current to the output as usually
required to drive LEDs. A voltage mode regulation can also be implemented (Refer to Chapter 6.7).
It is designed to control 4 gate driver outputs in a H-Bridge topology by using only one inductor and 4 external
MOSFETs. This topology is able to operate in high power BOOST, BUCK-BOOST and BUCK mode applications
with maximum efficiency.
The transition between the different regulation modes is done automatically by the device itself, with respect to the
application boundary conditions.
The transition phase between modes is seamless.
6.1
Regulator Diagram Description
The TLD5541-1QV includes two analog current control inputs (IIN1, IIN2) to limit the maximum Input current (Block
A1 and A7 in Figure 6).
A second analog current control loop (A5, A6) connected to the sensing pins FBL, FBH regulates the output
current.
The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error in the
output current loop is used to determine the appropriate duty cycle to get a constant output current.
An external compensation network (RCOMP, CCOMP) is used to adjust the control loop to various application
boundary conditions.
The inductor current for the current mode loop is sensed by the RSWCS resistor.
RSWCS is used also to limit the maximum external switches / inductor current.
If the Voltage across RSWCS exceeds its overcurrent threshold (VSWCS_buck or VSWCS_boost for buck or boost operation
respectively) the device reduces the duty cycle in order to bring the switches current below the imposed limit.
The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations.
The control loop logic block (LOGIC) provides a PWM signal to four internal gate drivers. The gate drivers
(HSGD1,2 and LSGD1,2) are used to drive external MOSFETs in an H-Bridge setup .
The control loop block diagram displayed in Figure 6 shows a typical constant current application. The voltage
across RFB sets the output current. RIN is used to fix the maximum input current.
The output current is fixed via the SPI parameter (LEDCURRADIM.ADIMVAL= 11110000B = default at 100%) plus
an offset trimming (LEDCURRCAL.CALIBVAL= 0000B = default in the middle of the range). Refer to Chapter 8.1
for more details.
Data Sheet
21
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
RIN
RFB
IIN
IOUT
VIN
Rfilter
M4
M3
M1
M2
COUT
HSGD2
LSGD2
HSGD1
LSGD1
FBH
FBL
VOUT
Cfilter
LOUT
+
-
A5
IIN1
IIN2
ISWCSx
SWCS
SGND
BOOST
+
-
A2
A1
A8
A9
HSGD1
HSGD2
RSWCS
SLOPE SELECTION
& Compensation
LOGIC
CLK
LSGD1
LSGD2
A3
BUCK
A6
A7
SET
Vi_REF
COMP
RCOMP
CCOMP
VCOMP
Figure 6
Regulator Block Diagram - TLD5541-1QV
Data Sheet
22
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
6.2
Adjustable Soft Start Ramp
The soft start behavior limits the current through the inductor and the external MOSFET switches during
initialization (at first turn on and restarting after output fault condition).
The soft start function gradually increases the current of the inductor (LOUT) over tSOFT_START to minimize potential
overvoltage at the output. The soft start ramp is defined by a capacitor placed at the SOFT_START pin.
Selection of the SOFT_START capacitor (CSOFT_START) can be done according to the approximate formula
described in Equation (1):
Vss_th_eff
tSOFT_ START
=
⋅CSOFT_ START
(1)
ISOFT_ START(PU)
Note:Vss_th_eff is the soft start effectiveness threshold, that depends on load condition. Its value is about 0.7V for
the buck mode and 1.4V for the boost mode
The SOFT START pin is also used to define a fault filter time.
Once an open load or a short on the output is detected, a pull-down current source ISOFT_START_PD (P_6.4.20) is
activated. This current brings down the VSOFT_START until VSOFT_START_RESET (P_6.4.22) is reached, then the pull-up
current source ISOFT_START_PU (P_6.4.19) turns on again. If the fault condition hasn’t been removed until
VSOFT_START_LOFF (P_6.4.21) is reached, the pull-down current source turns back on again, initiating a new cycle.
This will continue until the fault is removed.
6.3
Switching Frequency setup
The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ
pin to GND or by suppliyng a sync signal as specified in chapter Chapter 11.2. Select the switching frequency with
an external resistor according to the graph in Figure 7 or the following approximate formulas.
fSW [kHz] = 5375* RFREQ [kΩ]-0.8
(2)
RFREQ[kΩ] = 46023* fSW[kHz]−1.25
(3)
Figure 7
Switching Frequency fSW versus Frequency Select Resistor to GND RFREQ
6.4
Operation of 4 switches H-Bridge architecture
Inductor LOUT connects in an H-Bridge configuration with 4 external N channel MOSFETs (M1, M2, M3 & M4)
Data Sheet 23 Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
•
•
•
Transistor M1 and M3 provides a path between VIN and ground through LOUT in one direction (Driven by top
and bottom gate drivers HSGD1 and LSGD2).
Transistor M2 and M4 provides a path between VOUT and ground through LOUT in the other direction (Driven
by top and bottom gate drivers HSGD2 and LSGD1).
Nodes SWN1, SWN2, voltage across RSWCS, input and load currents are also monitored by the TLD5541-1QV.
BOOST
BUCK-BOOST
BUCK
MODE
MODE
MODE
M1
M2
M3
M4
ON
PWM
PWM
PWM
PWM
PWM
PWM
OFF
ON
OFF
PWM
PWM
Figure 8
4 switches H-Bridge architecture Transistor Status summary
VIN
VOUT
M1
M4
HSGD2
LSGD2
HSGD1
LSGD1
LOUT
SWN1
SWN2
M2
M3
RSWCS
Figure 9
4 switches H-Bridge architecture overview
6.4.1
Boost mode (VIN < VOUT)
•
•
•
•
•
M1 is always ON, M2 is always OFF
Every cycle M3 turns ON first and inductor current is sensed (peak current control)
M3 stays ON until the upper reference threshold is reached across RSWCS (Energizing)
M3 turns OFF, M4 turns ON until the end of the cycle (Recirculation)
Switches M3 and M4 alternate, behaving like a typical synchronous boost Regulator (see Figure 10)
Data Sheet
24
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
VIN
VOUT
ON
M1
M4
(2) Recirculation
ILOUT
HSGD2
LSGD2
HSGD1
LSGD1
LOUT
SWN1
SWN2
(1) Energizing
OFF
M2
M3
t
M1
+
M4
M1
+
M4
M1
+
M4
M1+M3
M1+M3
M1+M3
RSWCS
Figure 10 4 switches H-Bridge architecture in BOOST mode
Simplified comparison of 4 switches H-Bridge architecture to traditional asynchronous Boost approach.
•
•
•
M2 is always OFF in this mode (open).
M1 is always ON in this mode (closed connection of inductor to VIN).
M4 acts as a synchronous diode, with significantly lower conduction power losses (I2 x RDSON vs. 0.7V x I)
Note:Diode is source of losses and lower system efficiency!
LOUT
LOUT
D1
M1 (ON)
M4
VIN
VOUT
VOUT
VIN
M2
(OFF)
HSGD2
LSGD2
HSGD1
M3
M3
LSGD1
RSWCS
RSWCS
b) standard asynchronous BOOSTER
a) 4 switch architecture BOOSTER
Figure 11 4 switches H-Bridge architecture in BOOST mode compared to standard async Booster
6.4.2
Buck mode (VIN > VOUT)
•
•
•
•
•
M4 is always ON, M3 is always OFF
Every cycle M2 turns ON and inductor current is sensed (valley current control)
M2 stays ON until the lower reference threshold is reached across RSWCS (Recirculation)
M2 turns OFF, M1 turns ON until the end of the cycle (Energizing)
Switches M1 and M2 alternate, behaving like a typical synchronous BUCK Regulator (see Figure 12)
Data Sheet
25
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
VIN
VOUT
ILOUT
ON
M1
M4
(3) Energizing
HSGD2
LSGD2
HSGD1
LSGD1
LOUT
SWN1
SWN2
(4) Recirculation
t
OFF
M1
+
M4
M1
+
M4
M1
+
M4
M2
M3
M2+M4
M2+M4
M2+M4
RSWCS
Figure 12 4 switches H-Bridge architecture in BUCK mode
Simplified comparison of 4 switches architecture to traditional asynchronous Buck approach.
•
•
•
M3 is always OFF in this mode (open).
M4 is always ON in this mode (closed connection inductor to VOUT).
M2 acts as a synchronous diode, with significantly lower conduction losses (I2 x RDSON vs. 0.7V x I)
LOUT
M4
(ON)
LOUT
M1
M1
VIN
VOUT
VIN
VOUT
HSGD1
LSGD1
M3
(OFF)
HSGD1
HSGD2
M2
LSGD2
D1
RSWCS
b) standard asynchronous BUCK
a) 4 switch architecture BUCK
Figure 13 4 switches H-Bridge architecture in BUCK mode compared to standard async BUCK
6.4.3
Buck-Boost mode (VIN ~ VOUT)
•
•
When VIN is close to VOUT the controller is in Buck-Boost operation.
All switches are switching in buck-boost operation. The direct energy transfer from the Input to the output
(M1+M4 = ON) is beneficial to reduce ripple current and improves the energy efficiency of the Buck-Boost
control scheme.
•
The two buck boost waveforms and switching behaviors are displayed in Figure 14 below.
Data Sheet
26
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
VIN ≤ VOUT
ILOUT
VIN
VOUT
M1
M4
(2) Direct Transfer
HSGD2
LSGD2
HSGD1
LSGD1
(4) Direct Transfer
M1
+
M3
M1
+
M4
M1
+
M4
M1
+
M3
M1
+
M4
M1
+
M4
M1
+
M3
M1
+
M4
M1
+
M4
t
SWN1
SWN2
LOUT
(3) Recirculation
(1) Energizing
VIN ≥ VOUT
ILOUT
M2
M3
RSWCS
M2
+
M1
+
M1
+
M2
+
M1
+
M1
+
M2
+
M1
+
M1
+
t
M4
M4
M4
M4
M4
M4
M4
M4
M4
Figure 14 4 switches H-Bridge architecture in BUCK-BOOST mode
6.5
Fast Output Discharge Operation Mode - Multi Floating Switches Topology
Multiple light functions can be driven by a single DC/DC converter adopting a Multi Floating Switch (MFS)
topology. In a MFS topology, each LED Function is connected in series and can be independently turned off via a
bypass switch. Because of the series connections, all the functions are driven with the same current . Different
brightness can be achieved with individual PWM duty cycles.
In order to drive different LED functions in this topology, a Buck Boost converter is probably needed. A single stage
buck boost topology has high efficiency buts requires several µF of output capacitance (COUT). The extra voltage
present on this capacitor, when shorting one function to turn it off, may create a current spike in the LEDs that
have to remain on.
The TLD5541-1QV has a dedicated state machine which controls a fast discharge of the output cap to a desired
fraction of the initial output voltage. This Fast Output Discharge feature (F.D.), if carefully configured, limits the
current spike during load jump events preventing LED damage.
An Example of the Multi Floating Switch topology architecture and operation are shown in Figure 15
INITIAL CONDITION
FAST DISCHARGE
FINAL CONDITION
Vout
Disharging
Vout
Initial
Vout
Final
COUT
CIN
COUT
C
I
Disch
OUT
VBAT
DC/DC
LITIX FLEX
DC/DC
LITIX FLEX
DC/DC
LITIX FLEX
F1
OFF
F1
OFF
To VFB
To VFB
To VFB
F1
ON
External MOSFET
Control via µC
External MOSFET
Control via µC
External MOSFET
Control via µC
(A)
(B)
(C)
F2
OFF
F2
ON
F2
ON
External MOSFET
Control via µC
External MOSFET
Control via µC
External MOSFET
Control via µC
Figure 15 Multi Floating Switch topology: operation sequence on 2 Functions: (F1+F2) to (F2)
Data Sheet
27
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
The F.D. operation consists of discharging the capacitor COUT to the final load voltage (Figure 15-B) before the
bypass switch closure. During this fast discharge phase, all the LEDs are off. The external Microcontroller
Software has to take care of the synchronization between the TLD5541-1QV F.D. operation and the bypass
Switches activation.
The discharged energy from COUT is recovered back to the Input capacitor CIN which could cause a small
overshoot on the CIN itself. This feature allows high efficiency designs also when PWM operation with repetitive
Load Jumps is needed.
The F.D. feature is needed when a negative VOUT step is performed, so when one or more LED functions are
switched off. If additional LED functions are turned on, increasing the output voltage, the F.D. does not have to be
used. In MFS topologies, a short interruption of the current is observed during the Load Transitions (either positive
or negative) in all the functions, until VOUT is stable and the device control loop is able to provide the target output
current.
We will refer to any Voltage-Current or Load configuration just before the Load Jump as "Initial" (Figure 15-A),
while we will refer to any value after the system is in the new Load configuration as "Final" (Figure 15-C).
Set the Target Cout discharge voltage
The Target output voltage (VOUTFinal) of an F.D. operation is communicated to the TLD5541-1QV as a fraction of
the VOUT at the beginning of the Jump (VOUTInitial), and not as an absolute Value.
In order to quickly discharge the output Capacitor to a desired Ratio of the initial voltage, two SPI commands have
to be sent to the TLD5541-1QV register MFSSETUP1.
•
•
The first is to write in the MFSSETUP1.LEDCHAIN the Ratio Denominator
The second is to write in the MFSSETUP1 register the Ratio Numerator and the Start Of Multi Floating Switch,
respectively in the LEDCHAIN and SOMFS bitfields
After the second command, as soon as the Chip select is raised the F.D. begins. The final output voltage of the
F.D. operation, after a MFS routine is correctly performed, will be approximately:
RatioNumerator
(4)
VOUTFinal
=
⋅VOUTInitial
RatioDenominator
The MFSSETUP1.LEDCHAIN registers sets both the LED Ratio during F.D and the short circuit threshold. For this
reason both the correct VOUT Ratio and correct short circuit protection voltage have to be set according to the LED
Load. See Table 10 for reference.
To have the correct short circuit protection on a F.D. operation, the first LEDCHAIN value sent via SPI (Ratio
Denominator), should also guarantee an adequate short circuit detection for the Initial Load. The second
LEDCHAIN value (Ratio Numerator + SOMFS) should guarantee correct Short circuit detection for the Final Load.
For more information about short circuit protection, see Chapter 10.2.1.
Example:
If the VFB voltage divider for the Short circuit detection is set like in Table 10.
In order to jump from 6LED(18V) to 2LEDs (6V), the Ratio is 1/3 of initial voltage.
So the 2 SPI commands that have to be sent are:
Spi command 1: set MFSSETUP1 to 0x06 (Ratio Denominator = 6, VShort_LED = 16.8V)
Spi command 2: set MFSSETUP1 to 0x12 (Ratio Numerator+SOMFS = 0x02+0x10, VShort_LED= 4.6V )
Preparation time tprep
:
The TLD5541-1QV enables the user to set a delay between the beginning of the Load Jump and the moment in
which the switching activity will restart to provide output current. This delay is needed to safely close the bypass
Data Sheet
28
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
switches (to short the LEDs) for the new Light configuration, after the Final VOUT is reached and before the normal
switching activity would again raise the output voltage. See Figure 16.
The Preparation time has to be sufficient for the capacitors COUT and CCOMP to be discharged to the desired value.
The COUT discharge time depends heavily on: IDISCH, COUT size, VOUT Initial, VOUTFinal and VIN, so all those values
have to be considered when setting the preparation time. In order to set a preparation time on the TLD5541-1QV,
a SPI command has to be sent to the register MFSSETUP2.MFSDLY).
The Equation (5) below describes the relationship between the switching frequency fSW and the
MFSSETUP2.MFSDLY register value.
1
(5)
tprep
=
⋅
[2 + (MFSDLY )dec
]
fSW
For SPI command details refer to Chapter 12.6.
Fast Discharge Phase
After programming the desired output voltage Ratio via SPI , the right Preparation Time and activating the state
machine (MFSSETUP1.SOMFS= HIGH) the TLD5541-1QV inverts the inductor current IL and keeps it at the switch
current limit ISwLim until the VOUT reaches the desired target.
VSWCS _ boost
(6)
ISwLim
=
RSWCS
Figure 16 displays the relation of inductor current IL and the output voltage VOUT during a fast output discharge
operation mode.
Data Sheet
29
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
External
Mosfet
Closure
I F1
I F2
No current at the Load
during F.O.D.
EOMFS
LED N. FINAL
+ SOMF
LED N. INITIAL
TPREP
SPI COMMANDS
SPI CSN
Break
Low
IL
TPREP
TDISCHARGE
ISwLim
VOUT
VINITIAL
VFINAL
Current
Recovery
Normal Switching
activity F1 on
Fast Output Discharge
Normal Switching
activity F1+F2 on
Figure 16 Fast Output Discharge timing diagram
If the discharge current limit ISwLim needs to be reduced, the MFSSETUP1.ILIM_HALF_MFSbit can be used to cut
it in half (only during the F.D. phase and not in normal operation), see SPI Chapter for further details Chapter 12.6.
Setting the EA_IOUT_MFS bit will reduce (only during the F.D. phase) the saturation current of the error amplifier
A6 that discharges the Comp capacitor.
Once VOUT reaches the desired target, the current recovery phase brings IL from a negative value back to 0 A.
When the current recovery phase has ended, an internal SPI flag (MFSSETUP1.EOMFS) is set to HIGH and the
device stays in “Brake-Low condition” (both Lowside gatedrivers = ON) until the programmed preparation time
(MFSSETUP2.MFSDLY) expires and the TLD5541-1QV starts automatically switching again. Figure 16 displays
one Fast Output Discharge cycle.
The effective Cout discharge current is smaller than the Inductor current and it depends on the application
condition, see Equation (7).
2
⎛
⎞
V
V
V
i
i
o
(7)
⎜
⎜
⎟
⎟
IDISCH
=
⋅IswLim
−
⋅
V +V
2LfSW V +V
o
i
⎝
i
o
⎠
Sequence of operations to perform a Fast Output Discharge
In order to perform a F.D operation, the user has to :
•
•
•
•
Set via SPI an adequate Preparation Time
Send via SPI to MFSSETUP1.LEDCHAINthe Ratio Denominator.
Send via SPI to MFSSETUP1.LEDCHAINthe Ration Numerator + SOMFS
Adjust the Floating switches to the new configuration
Data Sheet
30
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
6.6
Flexible current sense
The flexible current sense implementation enables highside and lowside current sensing.
The Figure 17 displays the application examples for the highside and lowside current sense concept.
VIN
VIN
Highside
Sensing
Lowside
Sensing
FBH
FBL
FBH
FBL
Figure 17 Highside and lowside current sensing - TLD5541-1QV
Data Sheet
31
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
6.7
Programming Output Voltage (Constant Voltage Regulation)
For a voltage regulator, the output voltage can be set by selecting the values RFB1, RFB2 and RFB3 according to the
following Equation (8):
⎛
⎞
⎛
⎞
VFBH − FBL
VFBH − FBL
⎜
⎟
⎟
⎜
⎜
⎟
VOUT = IFBH
+
⋅ RFB1
+
− IFBL ⋅ RFB 3 + VFBH − FBL
(8)
⎜
⎝
⎟
⎠
RFB 2
RFB 2
⎠
⎝
After the output voltage is fixed via the resistor divider, the value can be changed via the Analog Dimming bits
ADIMVAL.
If Analog dimming is performed, due to the variations on the IFBL (IFBL_HSS (P_6.4.9) and IFBL_LSS (P_6.4.40))
current on the entire voltage spanning, a non linearity on the output voltage may be observed. To minimize this
effect RFBx resistors should be properly dimensioned.
VOUT
RFB1
IFBH
FBH
RFB2
IFBL
FBL
RFB3
Figure 18 Programming Output Voltage (Constant Voltage Regulation)
Data Sheet
32
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
6.8
Electrical Characteristics
Table 6
EC Regulator
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Number
Min.
Max.
Regulator:
V
(FBH-FBL) threshold
V(FBH-FBL) 145.5 150
154.5 mV
Tj = 25 °C;
P_6.4.1
ADIM.ADIMVAL=
11110000B;
V
V
(FBH-FBL) threshold
V(FBH-FBL) 144
150
15
156
18
mV
mV
ADIM.ADIMVAL= P_6.4.2
11110000B;
(FBH-FBL) threshold @ analog
V(FBH-
12
ADIM.ADIMVAL= P_6.4.5
00011000B;
dimming 10%
FBL)_10
CalibrationProcedure
not performed
FBH Bias current @ highside
sensing setup
IFBH_HSS
IFBL_HSS
IFBH_LSS
IFBL_LSS
65
17
-7.5
-45
-
110
30
155
43
-2.5
-20
-
µA
µA
µA
µA
V
1)VFBL = 7 V;
FBH - FBL = 150 mV;
1)VFBL = 7 V;
FBH - FBL = 150 mV;
1)VFBL = 0 V;
FBH - FBL = 150 mV;
1)VFBL = 0 V;
FBH - FBL = 150 mV;
P_6.4.8
P_6.4.9
P_6.4.39
P_6.4.40
P_6.9.1
P_6.9.2
P_6.4.10
V
FBL Bias current @ highside
sensing setup
V
FBH Bias current @ lowside
sensing setup
-4
V
FBL Bias current @ lowside
sensing setup
-30
2
V
FBH-FBL High Side sensing
entry threshold
VFBH_HSS_i
1)VFBH1 increasing;
nc
FBH-FBL High Side sensing exit VFBH_HSS_
threshold
-
1.75
-
V
1)VFBH decreasing;
dec
1)
OUT Current sense Amplifier gm IFBxgm
–
890
1.4
91
–
µS
V
Output Monitor Voltage
VIOUTMON 1.33
DBOOST_M 89
AX
1.47
93
VFBH - FBL = 150 mV; P_6.4.11
Maximum BOOST Duty Cycle
%
fsw=300kHZ;
P_6.4.12
Input Current Sense threshold
VIIN1-IIN2
VIIN1-IIN2
46
50
54
mV
–
P_6.4.13
1)
Input Current sense Amplifier gm IIN_gm
–
2.12
1
–
mS
V
P_6.4.14
P_6.4.15
Input current Monitor Voltage
VIINMON
0.95
1.05
1)VIIN1 - IIN2 = 50 mV;
VIIN1 = VVIN(ON) to
55 V;
1)
Switch Peak Over Current
Threshold - BOOST
VSWCS_boo 40
50
60
mV
mV
P_10.8.1
5
st
1)
Switch Peak Over Current
Threshold - BUCK
VSWCS_buck -60
-50
-40
P_10.8.1
6
Soft Start
Soft Start pull up current
ISoft_Start_P 22
26
33
32
µA
V
Soft_Start = 1 V;
P_6.4.19
U
Data Sheet
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
Table 6
EC Regulator (cont’d)
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Typ.
2.6
Unit Note /
Test Condition
Number
Min.
Max.
Soft Start pull down current
ISoft_Start_P 2.2
3.2
µA
V
–
–
Soft_Start = 1 V;
P_6.4.20
P_6.4.21
P_6.4.22
P_6.9.3
D
Soft Start Latch-OFF Threshold VSoft_Start_L 1.65
1.75
0.2
2
1.85
0.3
V
OFF
Soft Start Reset Threshold
VSoft_Start_ 0.1
V
RESET
Soft Start Voltage during
regulation
VSoft_Start_r 1.9
2.1
V
1)No Faults
eg
Oscillator
Switching Frequency
fSW
285
300
315
kHz Tj = 25 °C;
P_6.4.23
R
–
–
FREQ= 37.4 kꢀ;
SYNC Frequency
fSYNC
200
2
–
–
700
–
kHz
V
P_6.4.24
P_6.4.25
SYNC
VSYNC,ON
Turn On Threshold
SYNC
Turn Off Threshold
VSYNC,OFF
ISYNC,H
–
–
0.8
45
18
V
–
P_6.4.26
P_6.4.62
P_6.4.63
SYNC
High Input Current
15
6
30
12
µA
µA
V
SYNC = 2.0 V;
SYNC = 0.8 V;
SYNC
ISYNC,L
V
Low Input Current
Gate Driver for external Switch
Gate Driver undervoltage
threshold VBSTx-VSWNx_UVth VSWNx_UVth
VBSTx
-
3.4
–
4
V
V
BSTx - VSWNx
P_6.4.64
P_6.4.28
P_6.4.29
P_6.4.30
P_6.4.31
P_6.4.32
decreasing;
BSTx - VSWNx = 5 V;
source = 100 mA;
BSTx - VSWNx = 5 V;
sink = 100 mA;
IVCC_EXT = 5 V;
source = 100 mA;
IVCC_EXT = 5 V;
sink = 100 mA;
HSGDx NMOS driver on-state
resistance (Gate Pull Up)
RDS(ON_PU) 1.4
2.3
1.2
2.3
1.2
–
3.7
2.2
3.7
1.8
–
ꢀ
V
I
HS
HSGDx NMOS driver on-state
resistance (Gate Pull Down)
RDS(ON_PD) 0.6
ꢀ
V
I
HS
LSGDx NMOS driver on-state
resistance (Gate Pull Up)
RDS(ON_PU) 1.4
ꢀ
V
I
LS
LSGDx NMOS driver on-state
resistance (Gate Pull Down)
RDS(ON_PD) 0.4
ꢀ
V
I
1)
LS
HSGDx Gate Driver peak
sourcing current
IHSGDx_SRC 380
mA
VHSGDx - VSWNx = 1 V
to 4 V;
V
BSTx - VSWNx= 5 V
1)
HSGDx Gate Driver peak sinking IHSGDx_SNK 410
current
–
–
–
–
mA
mA
P_6.4.33
P_6.4.34
VHSGDx - VSWNx = 4 V
to 1 V;
V
1)
BSTx - VSWNx= 5 V
LSGDx Gate Driver peak
sourcing current
ILSGDx_SRC 370
VLSGDx = 1 V to 4 V;
IVCC_EXT = 5 V;
V
Data Sheet
34
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Regulator Description
Table 6
EC Regulator (cont’d)
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Number
Min.
Max.
1)
LSGDx Gate Driver peak sinking ILSGDx_SNK 550
current
–
mA
P_6.4.35
VLSGDx = 4 V to 1 V;
V
IVCC_EXT = 5 V;
1)
LSGDx OFF to HSGD ON delay tLSOFF-
15
35
30
60
40
75
ns
ns
P_6.4.36
P_6.4.37
HSON_delay
1)
HSGDx OFF to LSGD ON delay tHSOFF-
LSON_delay
1) Not subject to production test, specified by design
Data Sheet
35
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Digital Dimming Function
7
Digital Dimming Function
To change brightness of LED loads without affecting the lighting-color of the LED a digital Dimming function via
PWM (Pulse Width Modulation) is often required.
7.1
Description
PWM dimming is commonly practiced to prevent color shift in the LED light source.
Via Parallel Interface
The PWMI pin detects a pulse width modulated (PWM) signal that disable the gate drivers from delivering output
current.
µC
PWM
Digital dimming
PWMI
+3.3V or +5V
VDD
CSN
SI
SPI
SO
SCLK
VSS AGND
Figure 19 Digital Dimming Overview
Data Sheet
36
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Digital Dimming Function
tACTIVE
VEN/INUVLO
VEN/INUVLOth
t
t
VIVCC_EXT_RTH,d
+VIVCCX_HYST
tPWMI,H
TPWMI
VPWMI
VPWMI,ON
VPWMI,OFF
t
Switching
activity
t
t
ILED
VIOUTMON
200mV
t
Softstart
Normal
Gate ON
Diag ON
Normal
Gate ON
Dim
Normal
Gate ON
Diag ON
Dim
Dim
Power ON
Gate OFF
Diag OFF
Gate OFF
Diag OFF
Gate OFF
Diag OFF
Diagnosis ON
Figure 20 Timing Diagram LED Dimming and Start up behavior example ( VVDD and VVIN stable in the
functional range and not during startup)
Note:In Register REGUSETMON.REGUMODFB the regulation mode can be read. During PWMI = LOW the SPI will
always deliver the Regulation mode which was present at PWMI = HIGH as actual regulation mode, instead
of “no Regulation”.
Data Sheet
37
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Digital Dimming Function
7.2
Electrical Characteristics
Table 7
EC Digital Dimming
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition Number
Min.
Max.
PWMI Input:
PWMI
Turn On Threshold
VPWMI,ON
VPWMI,OFF
IPWMI,H
2
–
–
V
–
P_7.2.1
P_7.2.2
P_7.2.4
P_7.2.5
PWMI
Turn Off Threshold
–
–
0.8
45
18
V
–
PWMI
High Input Current
15
6
30
12
µA
µA
V
V
PWMI = 2.0 V;
PWMI = 0.8 V;
PWMI
IPWMI,L
Low Input Current
Data Sheet
38
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Analog Dimming
8
Analog Dimming
The analog dimming feature allows further control of the output current. This approach is used to:
•
•
Reduce the default current in a narrow range to adjust to different binning classes of the used LEDs.
Adjust the load current to enable the usage of one hardware for several LED types where different current
levels are required.
•
•
Reduce the current at high temperatures (protect LEDs from overtemperature).
Reduce the current at low input voltages (for example, cranking-pulse breakdown of the supply or power
derating).
8.1
Description
The analog dimming feature is adjusting the average load current level via the control of the feedback error
Amplifier voltage (VFBH-FBL).
The current adjustment is done via a 8BIT SPI parameter (LEDCURRADIM.ADIMVAL). Refer to Figure 21.
VFBH-FBL
150mV
Bitcode
b´11110000
8 BIT SPI adjustment
0
Figure 21 Analog Dimming Overview
Analog dimming adjustment during Limp Home state:
To enter in Limp Home state the LHI pin must be HIGH.
Note: If the PWMI and the EN/INUVLO are not set to HIGH, it is not possible to enable switching, even during
Limp Home state.
In Limp Home state the analog dimming control is done via the SET pin. A Resistor divider between
IVCC/IVCC_EXT, SET and GND is used to fix a default load current/voltage value (refer to Figure 22 below).
Data Sheet
39
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Analog Dimming
CIN
> VIN(PO)
> VIVCC_EXT_RTH,d
IVCC
CIVCC
IVCC_ext
VIN
IVCC
EN/INUVLO
Current
Regulation
D2
D1
default output
current/voltage
adjustment
BST1
BST2
SET
RFB
COUT
CBST1 CBST2
M1
M2
M4
HSGD1
SWN1
LOUT
LIMPHOME
FAIL SAFE Circuit
M3
LHI
HIGH
LSGD1
SWCS
Load
PWMI_LH
FAIL SAFE Circuit
SGND
PGND1
PGND2
Set HIGH to
activate output
PWMI
LSGD2
SWN2
HSGD2
VFB
CSN
SI
SO
SPI Writing
disabled during
Limp Home state
FBH
FBL
SCLK
VSS AGND
Figure 22 Limp Home state schematic overview
Using the SET pin to adjust the output current:
The SET pin is ignored if the device is not in Limp Home state.
For the calculation of the output current IOUT the following Equation (9) is used:
VFBH − VFBL
IOUT
=
(9)
RFB
A decrease of the average output current can be achieved by controlling the voltage at the SET pin (VSET) between
0.2V and 1.4V. The mathematical relation is given in the Equation (10) below:
V SET − 200 mV
I OUT
=
(10)
R FB ⋅ 8
If VSET is 200mV (typ.) the LED current is only determined by the internal offset voltages of the comparators.
To assure the switching activity is stopped and IOUT=0, VSET has to be <100mV, see Figure 23
Data Sheet
40
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Analog Dimming
VFBH-FBL
150mV
100mV
0mV
VSET
200mV
1.4V 1.5V
Analog Dimming
Disabled
Analog Dimming Enabled
Figure 23 Analog Dimming Overview
8.2
LED current calibration procedure
The LED current calibration procedure improves the accuracy during analog dimming. In order to be most
effective, this routine has to be performed in the application, when the TLD5541-1QV temperature and the output
voltage are the ones in which the driver has to be accurate. The optimum should be to re-calibrate the output
periodically every time the application has for a sufficent long time PWMI=LOW.
Current calibration procedure:
•
•
•
•
•
•
•
•
Power the Load with a low analog dimming value (for example 10%)
Set PWMI=LOW and disconnect the Load at the same time (to avoid Vout drifts from operating conditions)
Quickly µC enables the calibration routine: DVCCTRL.ENCAL= HIGH
Quickly µC starts the calibration: LEDCURRCAL.SOCAL= HIGH
Waiting time (needed to internally perform the calibration routine) -> aprox. 200µs
TLD5541-1QV will set the FLAG: LEDCURRCAL.EOCAL= HIGH, when calibration routine has finished
Reconnect the load
The Output current is automatically adjusted to a low offset and more accurate analog dimming value
Once the Calibration routine is correctly performed , the output current accuracy with analog dimming = 10%
(LEDCURRADIM.ADIMVAL=24) is 10%.
The Calibration routine is not affecting the accuracy at 100% analog dimming.
The ENCAL Bits affect both device operation and CALIBVAL reading result:
•
ENCAL = HIGH: the calibration result coming from the routine is used by internal circuitry and can be read back
from CALIBVAL
•
ENCAL = LOW: SPI value written in CALIBVAL is used by internal circuitry and can be read back; calibration
routine start is inhibited
As a result, μC can use a stored result from a previously performed calibration to directly impose the desired value
without waiting for a new routine to finish.
Data Sheet
41
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Analog Dimming
OUT H-Bridge
Vint_supply
FBH
+
V_sense_in
FBL
RFB
VFBH-FBL
IOUT_sense
V_sense_out
-
+
Latch
IDC_offset
ADC out
-
to LED
Load
IIN_feedback
ADC CLK
+
-
EA
ADC Latch
8 bit resolution
4 bit calibration
DAC
COMP
Vref_int
2Bit Monitoring
Logic
ADC CLK
Figure 24 LED current Accuracy Calibration Overview
8.3
Electrical Characteristics
Table 8
EC Analog Dimming
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Number
Test Condition
Min.
Typ. Max.
Source current on SET Pin
ISET_source
–
–
1
µA
1)VSET = 0.2 V to
P_8.3.4
1.4V;
1) Specified by design: not subject to production test.
Data Sheet
42
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Linear Regulator
9
Linear Regulator
The TLD5541-1QV features an integrated voltage regulator for the supply of the internal gate driver stages.
Furthermore an external voltage regulator can be connected to the IVCC_EXT pin to achieve an alternative gate
driver supply if required.
9.1
IVCC Description
When the IVCC pin is connected to the IVCC_EXT pin, the internal linear voltage regulator supplies the internal
gate drivers with a typical voltage of 5V and current up to ILIM (P_9.2.2). An external output capacitor with low ESR
is required on pin IVCC for stability and buffering transient load currents. During normal operation the external
MOSFET switches will draw transient currents from the linear regulator and its output capacitor (Figure 25,
drawing A). Proper sizing of the output capacitor must be considered to supply sufficient peak current to the gate
of the external MOSFET switches. A minimum capacitance value is given in parameter CIVCC (P_9.2.4).
Alternative IVCC_EXT Supply Concept:
The IVCC_EXT pin can be used for an external voltage supply to alternatively supply the MOSFET Gate drivers.
This concept is beneficial in the high input voltage range to avoid power losses in the IC (Figure 25, drawing B).
Integrated undervoltage protection for the external switching MOSFET:
An integrated undervoltage reset threshold circuit monitors the linear regulator output voltage. This undervoltage
reset threshold circuit will turn OFF the gate drivers in case the IVCC or IVCC_EXT voltage falls below their
undervoltage Reset switch OFF Thresholds VIVCC_RTH,d (P_9.2.9) and VIVCC_EXT_RTH,d (P_9.2.5).
In Limp Home state the Undervoltage Reset switch OFF threshold for the IVCC has no impact on the switching
activity.
The Undervoltage Reset threshold for the IVCC and the IVCC_EXT pins help to protect the external switches from
excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of the external
logic level N-channel MOSFETs.
A
B
IVCC
Power
IVCC
Internal
VREG
Internal
VREG
VIN
VIN
Power
On Reset
On Reset
External
VREG
IVCC_EXT
IVCC_EXT
Gate Drivers
Gate Drivers
Figure 25 Voltage Regulator Configurations
Data Sheet
43
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Linear Regulator
9.2
Electrical Characteristics
Table 9
EC Line Regulator
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition Number
Min.
Max.
IVCC
Output Voltage
VIVCC
4.8
70
–
5
5.2
V
VIN= 13.5 V;
0.1mA ≤ IIVCC ≤ 50mA;
1)
P_9.2.1
P_9.2.2
P_9.2.3
Output Current Limitation ILIM
90
200
110
350
mA
mV
V
IVCC = 4 V;
VIN = 5 V;
IVCC = 10 mA;
Drop out Voltage (VIN -
VIVCC
VDR
)
I
1) 2)
IVCC Buffer Capacitor
CIVCC
10
–
–
µF
V
P_9.2.4
P_9.2.5
3)
IVCC_EXT Undervoltage VIVCC_EXT_ 3.7
3.9
4.1
Reset switch OFF
V
IVCC_EXT decreasing;
RTH,d
Threshold
3)
IVCC Undervoltage
Reset switch OFF
Threshold
VIVCC_RTH, 3.7
3.9
4.1
V
V
P_9.2.9
P_9.2.6
V
IVCC decreasing;
d
IVCC and IVCC_EXT
Undervoltage Hysterisis
VIVCCX_HY 0.3
0.33
0.36
V
V
IVCC increasing;
IVCC_EXT increasing
ST
1) Not subject to production test, specified by design
2) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum. Use
capacitors with LOW ESR.
3) Selection of external switching MOSFET is crucial. VIVCC_EXT_RTH,d and VIVCC_RTH,d min. as worst case VGS must be
considered.
Data Sheet
44
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
10
Protection and Diagnostic Functions
10.1
Description
The TLD5541-1QV has integrated circuits to diagnose and protect against overvoltage, open load, short circuits
of the load and overtemperature faults. Furthermore, the device provides a 2 Bit information of ILED, IIN by the SPI
to the µC.
In IDLE state, only the Over temperature Shut Down, Over Temperature Warning, IVCC or IVCC_EXT
Undervoltage Monitor, VDD or VEN/INUVLO Undervoltage Monitor are reported according to specifications.
In Figure 26 a summary of the protection, diagnostic and monitor functions is displayed.
Protection and Diagnostic
SPI STD
Diagnosis
Overvoltages
SPI
Open Load
SPI
No output current
OR
Short at the Load
SPI
SPI
Linear Regulators
OFF
(only IVCC disabled
Device
Overtemperature
OR
in case of
Input
overtemperature)
Undervoltage
Monitoring
2BIT data
2BIT data
2BIT data
IOUT
Read-back via
SPI
IIN
Mode Indication
IOUT
IOUTMON
IINMON
KILIS Factor 8
KILIS Factor 20
IIN
Figure 26 Protection, Diagnostic and Monitoring Overview - TLD5541-1QV
Note: A device Overtemperature event overrules all other fault events!
Data Sheet
45
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
10.2
Overvoltage, Open Load, Short circuit protection
The VFB pin measures the voltage on the application output and in accordance with the populated resistor divider,
short to ground, open load and overvoltage thresholds are set. Refer to Figure 28 and Figure 27 for more details.
VFB
Overvoltage
VFB_OVTH = fixed
Open LOAD
VFB_OL,rise = fixed
Normal Operation
VFB_S2G = adjustable
Short
Circuit
e.g. 50V
VOUT
Threshold can be
adjusted via SPI
Figure 27 Definition of Protection Ranges
VIN
CIVCC
IVCC
D2
D1
VOUT
RFB
BST1
BST2
CBST1 CBST2
M1
M2
M4
VVFB_OVTH
VVFB_OL,rise
RVFBH
COUT
HSGD1
SWN1
LOUT
M3
LSGD1
SWCS
RVFBL
VVFB_S2G
RSWCS
SGND
PGND
LSGD2
SWN2
HSGD2
VFB
FBH
FBL
Figure 28 VFB Protection Pin - Overview
10.2.1
Short Circuit protection
The device detects a short circuit if this condition is verified:
The pin VFB falls below the threshold voltage VVFB_S2G for at least 8 clock cycles
•
Data Sheet
46
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
After a short circuit detection, the SPI flag (SHRTLED) in the STD diagnosis register is set to HIGH and the gate
drivers stop delivering output current (Break-Low condition, both LS MOSFETs ON). The Device will auto restart
with the soft start routine described in Chapter 6.2. The dedicated diagnosis flag (SHRTLED) will be cleared after
the next reading cycle of the STD diagnosis.
A voltage divider between VOUT, VFB pin and AGND is used to adjust the application short circuit thresholds
following Equation (12).
RVFBH + RVFBL
Vshort
= VVFB
⋅
(11)
_ led
_ S 2 G
RVFBL
The short circuit threshold voltage VVFB_S2G (P_10.8.1) is set by 4-Bits in the SPI register MFSSETUP1.LEDCHAIN
as shown in Table 10.
The configurable short circuit threshold is especially useful in 2 types of applications:
1) Multifloat switch applications:
Multifloat switch applications are applications with a series connection of LEDs and parallel Transistors to switch
ON and OFF single (or multiple) LEDs in a string. The built in feature “fast output discharge operation mode”
enables such applications but the short circuit threshold has to be adjusted in accordance to the LED changes.
This sincronization is needed to avoid wrong short circuit detection during load step variations.
For this reason the register MFSSETUP1.LEDCHAINselects the short circuit threshold register but is also related
to the “fast dynamic behavior feature”. For more Info on the “fast output discharge operation mode” please refer
to Chapter 6.5.
2) Standard applications which require a large output voltage range:
The adjustable short circuit threshold VVFB_S2G enables applications with a large VOUT operation range.
The Table 10 below displays the relationship between the bitcode and the short circuit threshold voltage VVFB_S2G
based on an example.
Assume that each LED has a typical VF=3.3V. By choosing a resistor divider RVFBH = 1MOhm, RVFBL = 41kOhm,
the application short circuit voltage Vshort_led, will change according to the LEDCHAIN value as shown in Table 10.
The application overvoltage protection is instead not dependent by LEDCHAIN and, based on the Equation (12)
for this particular resistor divider is fixed to 59.3V.
Table 10
Adjustable Short Circuit threshold overview
nled
VOUT
VOUT_OVLO k = RVFBL
/
Vopen_led
Vshort_led (V)
VVFB1,2_S2G(V) Default
LEDCHAIN
(RVFBH + RVFBL
)
(VFB1,2_S2G / k)
Condition
1
3.3
59.3
59.3
59.3
59.3
59.3
59.3
59.3
59.3
59.3
59.3
59.3
59.3
59.3
0.025
54.4
54.4
54.4
54.4
54.4
54.4
54.4
54.4
54.4
54.4
54.4
54.4
54.4
1.5
0.038
0.113
0.188
0.263
0.338
0.413
0.488
0.563
0.638
0.713
0.788
0.863
0.938
2
6.6
0.025
4.6
3
9.9
0.025
7.6
4
13.2
16.5
19.8
23.1
26.4
29.7
33.0
36.3
39.6
42.9
0.025
10.7
5
0.025
13.7
6
0.025
16.8
7
0.025
19.8
8
0.025
22.8
default
9
0.025
25.9
10
11
12
13
0.025
28.9
0.025
32.0
0.025
35.0
0.025
38.1
Data Sheet
47
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
Table 10
Adjustable Short Circuit threshold overview
nled
LEDCHAIN
VOUT
VOUT_OVLO k = RVFBL
/
Vopen_led
V
short_led (V)
V
VFB1,2_S2G(V) Default
Condition
(RVFBH + RVFBL
)
(VFB1,2_S2G / k)
14
15
16
46.2
49.5
52.8
59.3
59.3
59.3
0.025
54.4
54.4
54.4
41.1
1.013
1.088
1.163
0.025
44.2
0.025
47.2
During Limp Home state the short circuit threshold VVFB_S2G is fixed at the default value (VVFB_S2G / VVFB_OVTH),
approx. 1/3 of the fixed overvoltage protection circuit in the application. There is no relationship between the
analog dimming feature at VSET pin and the VVFB_S2G threshold. The customer must take care by adjusting the
default voltage at SET pin to program the VOUT be higher than the default short circuit threshold.
During start-up the TLD5541-1QV ignores the detection of a short circuit or an open load until the soft-start
capacitor reaches 1.75V. To prevent false tripping after startup, a large enough soft-start capacitor must be used
to allow the output to get up to approximately 50% of the final value.
Note:If the short circuit condition disappears, the device will re-start with the soft start routine as described in
Chapter 6.2.
10.2.2
Overvoltage Protection
A voltage divider between VOUT, VFB pin and AGND is used to adjust the Overvoltage protection threshold (refer
to Figure 28).
To fix the overvoltage protection threshold the following Equation (12) is used:
RVFBH + RVFBL
VOUT _ OV _ protected =VVFB _ OVTH
⋅
(12)
RVFBL
If VVFB gets higher than its overvoltage threshold VVFB_OVTH , the SPI flag (OUTOV) in the STD diagnosis set to
HIGH and the gate drivers stop switching for output regulation (Break-Low condition both LS MOSFETs ON).
When VVFB_OVTH- VVFB_OVTH,HYS threshold is reached the device will auto restart. The dedicated diagnosis flag
(OUTOV) will be cleared after the next reading cycle of the STD diagnosis.
If the SWTMOD.OUTOVLATbit is set to HIGH the overvoltage protection is changed into latched behavior and the
µC has to set the DVCCTRL.CLRLATbit to reset the OUTOV flag and restart the switching activities.
10.2.3
Open Load Protection
To reliably detect an open load event, two conditions will be observed:
1) Voltage threshold: VVFB>VVFB_OL,rise
2) output information: V(FBH-FBL)<VFBH_FBL_OL
After an open load error, the SPI flag (OL) in the STD diagnosis is set to HIGH and the gate drivers stop switching
(Break-Low condition). The Device will auto restart with a soft start routine. The dedicated diagnosis flag (OL) will
be cleared after the next reading cycle of the STD diagnosis.
After an Open Load error the TLD5541-1QV is autorestarting the output control accordingly to the implemented
Softstart routine. An Open Load error causes an increase of the output voltage as well. An Overvoltage condition
could be reported in combination with an Open Load error (in general, multiple error detection may happen if more
error detection thresholds are reached during the autorestart funcion, as possible consequence of reactive
behavior at the output node during open load).
The COMP capacitor is discharged during an Open Load condition to prevent spikes if load reconnects. This
measure could artificially generate Short Circuit detections after open loads events.
Data Sheet
48
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
10.3
Input voltage monitoring, protection and power derating
Input overvoltage and undervoltage shutdown levels can both be defined through an external resistor divider, as
shown in Figure 29.
Both INOVLO and EN/INUVLO pin voltages are internally compared to their respective thresholds by means of
hysteretic comparators.
Neglecting the hysteresis, the following equations hold:
⎛
⎞
R1
⎜
⎟
⎟
UV th = 1 +
⋅ EN / INUVLO
(13)
(14)
th
th
⎜
⎝
R2 + R3
⎠
⎛
⎜
⎞
R 1 + R 2
⎟
⎟
OV
PIN
=
1 +
⋅ INOVLO
th
⎜
R 3
⎝
⎠
VOUT ⋅ IOUT
=
(15)
η
⎛
⎞
VOUT ⋅ IOUT
⎜
⎜
⎟
⎟
I IN
⎝
⎠
(16)
(17)
(18)
VIN _ boundary
=
η
V IN 1− IN 2
I IN
=
R IN
VFBH −FBL
IOUT
=
RFB
Figure 29 Input Voltage Protection
Data Sheet
49
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
10.4
Input current Monitoring
The input current can be monitored through an analog output pin and an SPI routine.
The IINMON pin provides a linear indication of the current flowing through the input. The following Equation (19)
is applicable:
VIINMON = I IN ⋅ RIN ⋅ 20
(19)
Note:If the RIN value is choosen in a way that the current limitiation is much bigger than the nominal input current
during the application the current measurement becomes inaccurate. Best results for an accurate current
measurement via the VIINMON pin is to set the current limit only slightly above the specific application related
nominal input current.
Purpose of the input current monitoring routine is to verify if the system is in current limitation.
•
•
The output of the Input Current Sense is compared to the internal precise reference voltage.
The comparator works like a 2 bit window ADC referred to the internal precise reference voltage.
To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready
when CURRMON.EOMON is read HIGH.
The result of the input monitor routine is reported on the CURRMON.INCURR bit.
Figure 30 Input Current Monitoring General Overview
10.5
Output current Monitoring
The output current can be monitored through an analog output pin and an SPI routine.
The IOUTMON pin provides a linear indication of the current flowing through the LEDs. The following
Equation (20) is applicable:
(20)
VIOUTMON = 200 mV + IOUT ⋅ RFB ⋅ 8
Purpose of the SPI current monitor routine is to verify if the system is in loop.
•
•
The output of the Led Current Sense is compared to the output of the Analog Dimming DAC
The comparator works like a 2 bit window ADC around 8 bit DAC output
To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready
when CURRMON.EOMON is read HIGH.
Data Sheet
50
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
When CURRMON.SOMON bit is set to HIGH both input and output current monitor routines are executed in
parallel.
The result of the monitor routine is reported on the CURRMON.LEDCURR bit.
OUT H-Bridge
ADC out
2Bit Monitoring
IOUTMON
Vint_supply
11b
10b
00b 01b
FBH
feedback
Logic
+
V_sense_in
VFBH-FBL
RFB
IOUT_sense
-
FBL
ADC CLK
V_sense_out
+
Latch
IDC_offset
ADC in
ADC out
-
to LED
Load
IIN_feedback
ADC CLK
+
-
ADC Latch
EA
8 bit resolution
4 bit calibration
DAC
COMP
Vref_int
Figure 31 Output Current Monitoring General Overview
Data Sheet
51
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
10.6
Device Temperature Monitoring
A temperature sensor is integrated on the chip. The temperature monitoring circuit compares the measured
temperature to the warning and shutdown thresholds. If the internal temperature sensor reaches the warning
temperature, the temperature warning bit TWis set to HIGH. This bit is not latched (i.e. if the temperature falls
below the warning threshold (with hysteresis), the TWbit is reset to LOW again).
If the internal temperature sensor reaches the shut-down temperature, the Gate Drivers plus the IVCC regulator
are shut down as described in Figure 32 and the temperature shut-down bit: TSDis set to HIGH. The TSDbit is
latched while the Gate Drivers plus the IVCC regulator have an auto restart behavior.
Note:The Device will start up with a soft start routine after a TSD condition disappear.
Tj
TjSD,hyst
TjSD
TjW
TjSD_exit
TjW_exit
TjW,Hyst
t
xSGDx
Gate Drivers
autorestart
Operating
OFF
t
IVCC
5V
IVCC
autorestart
OFF
t
TW bit
1
NO ERROR
NO ERROR
TW bit is reset automatically
0
t
t
TSD error bit
1
0
TSD error bit latched until next reset or CLRLAT
Figure 32 Device Overtemperature Protection Behavior
Data Sheet
52
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
10.7
Electrical Characteristics
Table 11
EC Protection and Diagnosis
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Number
Min.
Max.
Short Circuit Protection
Short to GND
threshold
VVFB_S2G
0.53
0.563
0.59
V
V
VFB decreasing;
P_10.8.1
MFSSETUP1.LEDCHAIN
= 1000B
Temperature Protection:
1)
Thermal Warning
junction
Tj,W
125
140
155
°C
P_10.8.2
temperature
1)
1)
1)
Temperature
warning Hysteresis
Tj,W,hyst
–
10
–
°C
°C
°C
P_10.8.3
P_10.8.4
P_10.8.5
Over Temperature Tj,SD
Shutdown
160
–
175
10
190
–
Over Temperature Tj,SD,hyst
Shutdown
Hysteresis
Overvoltage Protection:
VFB Over Voltage VVFB_OVTH
Feedback
Threshold
1.42
1.46
40
1.50
58
V
P_10.8.6
P_10.8.7
Output Over
VVFB_OVTH,HY 25
mV
Output Voltage
decreasing;
Voltage Feedback
Hysteresis
S
Open Load and Open Feedback Diagnostics
Open Load rising
Threshold
VVFB_OL,rise
1.29
1.34
1.39
22.5
V
V
V
FBH-FBL = 0 V;
FB = 1.4 V;
P_10.8.9
Open Load
VFBH_FBL_OL
–
15
mV
P_10.8.10
reference Voltage
VFBH-FBL
Open Load falling VVFB_OL,fall
Threshold
1.23
1.9
1.28
1.33
V
V
FBH-FBL = 0 V;
P_10.8.11
Input Overvoltage protection
Input Overvoltage VINOVLOth
rising Threshold
2
2.1
62
V
–
–
P_10.8.12
P_10.8.13
Input Overvoltage VINOVLO(hyst) 18
40
mV
Threshold
Hysteresis
1) Specified by design; not subject to production test.
Data Sheet
53
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Protection and Diagnostic Functions
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
54
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Infineon FLAT SPECTRUM Featureset
11
Infineon FLAT SPECTRUM Featureset
11.1
Description
The Infineon FLAT SPECTRUM feature set has the target to minimize external additional filter circuits. The goal
is to provide several beneficial concepts to provide easy adjustments for EMC improvements after the layout is
already done and the HW designed.
11.2
Synchronization Function
The TLD5541-1QV features a SYNC input pin which can be used by a µC pin to define an oscillator switching
frequency. The µC is responsible to synchronize with various devices by applying appropriate SYNC signals to
the dedicated DC/DC devices in the system. Refer to Figure 33
Note: The Synchronization function can not be used when the Spread Spectrum is active.
H-Bridge DCDC
MASTER
BUCK-
BOOST
SYNC
GATE
LOGIC
CONTROL
e.g. 400kHz
Phaseshift A
H-Bridge DCDC
Slave
BUCK-
BOOST
GATE
SYNC1
SYNC2
defined phase shift between
Outputs of different devices
SYNC
µC
LOGIC
INPUT
e.g. 400kHz
Phaseshift B
CONTROL
Figure 33 Synchronization Overview
Data Sheet
55
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Infineon FLAT SPECTRUM Featureset
11.3
Spread Spectrum
The Spread Spectrum modulation technique significantly improves the lower frequency range of the spectrum
(f<30MHz).
By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and also
pass the average limits (average emission limits are -20dB lower than the peak emission limits). By using spread
spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor is important
for the low frequency filter characteristic. This can be an economic benefit if there is a strong requirement for
average limits.
The TLD5541-1QV features a built in Spread Spectrum function which can be enabled (SWTMOD.ENSPREAD) and
adjusted via the SPI interface. Dedicated SPI-Bits are used to adjust the modulation frequency fFM, (P_11.6.3) and
(P_11.6.4) (SWTMOD.FMSPREAD) and the deviation frequency fdev
,
(P_11.6.1) and (P_11.6.2)
(SWTMOD.FDEVSPREAD) accordingly to specific application needs. Refer to Figure 34 for more details.
The following adjustments can be programmed when SWTMOD.ENSPREAD= HIGH:
SWTMOD.FMSPREAD= LOW: 12kHz
SWTMOD.FMSPREAD= HIGH: 18kHz
SWTMOD.FDEVSPREAD= HIGH: ±8% of fSW
SWTMOD.FDEVSPREAD= LOW: ±16% of fSW
Note: The Spread Spectrum function can not be used when the synchronization pin is used.
fSW
fdev
t
1
f
FM
Figure 34 Spread Spectrum Overview
Data Sheet
56
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Infineon FLAT SPECTRUM Featureset
11.4
EMC optimized schematic
Figure 35 below displays the Application circuit with additional external components for improved EMC behavior.
LPI
CIN2
VIN
RIIN
DVS
Alternative
external
VREG supply
CPI1 CPI2
CPI3 CPI4
IVCC_EXT
IVCC
CIVCC
VIN
IIN2
CIN1
D1
D2
LPO
RFB
Rfilter
Cfilter
RM4
BST1
BST2
COUT
DHSG1
RM1
CBST2
R1
R2
R3
M4
IIN1
EN/INUVLO
M1
RVFBH
CBST1
HSGD1
SWN1
CM1
RM2
CM4
RM3
CM3
RHSG1
CPO1 CPO2
CPO3 CPO4
LOUT
RHSG2
M3
RVFBL
DLSG1
INOVLO
COMP
M2
CCOMP
RCOMP
LSGD1
SWCS
CM2
RLSG1
CSOFT_START
RFREQ
DLSG2
RLSG2
DHSG2
SOFT_START
FREQ
RSWCS
4LED in
series /
1A
SGND
PGND1
PGND2
µC SYNC signal
Digital dimminig
SYNC
PWMI
LSGD2
IINMON
IOUTMON
Advanced monitoring via µC
+3.3V or +5V
SWN2
HSGD2
VFB
VDD
CSN
SI
SO
SCLK
FBH
FBL
CFBH-FBL
CFBH
Spread Spectrum ON /OFF via SPI
VSS AGND
CFBL
RSPI
Figure 35 Application Drawing Including Additional Components for an Improved EMC Behavior
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Data Sheet
57
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Infineon FLAT SPECTRUM Featureset
11.5
Electrical Characteristics
Table 12
EC Spread Spectrum
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Number
Min.
Max.
Spread Spectrum Parameters
1)
Frequency Deviation
fdev
fdev
fFM
fFM
–
±8
–
%
P_11.6.1
P_11.6.2
P_11.6.3
P_11.6.4
SWTMOD.FDEVSP
READ= HIGH;
1)
Frequency Deviation
Frequency Modulation
Frequency Modulation
–
–
–
±16
12
–
–
–
%
SWTMOD.FDEVSP
READ= LOW;
1)
kHz
kHz
SWTMOD.FMSPRE
AD= LOW;
1)
18
SWTMOD.FMSPRE
AD= HIGH;
1) Specified by design; not subject to production test.
Data Sheet
58
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
12
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,
SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CSN
indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on
line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo 8/16
counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits.
Otherwise, a TER(i.e. Transmission Error) bit is asserted. In this way the interface provides daisy chain capability
with 16 bit as well as with 8 bit SPI devices.
MSB
MSB
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
SO
SI
CSN
SCLK
time
SPI_16bit.emf
Figure 12-1 Serial Peripheral Interface
12.1
SPI Signal Description
CSN - Chip Select
The system microcontroller selects the TLD5541-1QV by means of the CSN pin. Whenever the pin is in LOW
state, data transfer can take place. When CSN is in HIGH state, any signals at the SCLK and SI pins are ignored
and SO is forced into a high impedance state.
CSN HIGH to LOW Transition
•
•
•
The requested information is transferred into the shift register.
SO changes from high impedance state to HIGH or LOW state depending on the signal level at pin SI.
If the device is in SLEEP mode, the SO pin remains in high impedance state and no SPI transmission will
occur.
•
TERFlag will set the Bit number 10 in the STD diagnosis Frame. This Bit is set to HIGH after an undervoltage
contition, reset via SPI command, on Limp Home state entering or after an incorrect SPI transmission. TER
Flag can be read also direcly on the SO line between the falling edge of the CSN and the first rising edge of
the SCLK according to the Figure 12-2.
Data Sheet
59
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
STDDIAG.TER
SI
SO
OR
1
0
SO
S
SI
SPI
CSN
SCLK
S
SPI_16bitTER .emf
Figure 12-2 Combinatorial Logic for TER bit
CSN LOW to HIGH Transition
•
Command decoding is only done, when after the falling edge of CSN exactly a multiple (0,1, 2, 3, …) of eight
SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the
transmission error bit (TER) is set and the command is ignored.
•
Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in LOW state whenever chip select CSN makes any transition, otherwise the
command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 12.5 for
further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN pin
goes to LOW state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Chapter 12.5 for further information.
12.2
Daisy Chain Capability
The SPI of the TLD5541-1QV provides daisy chain capability. In this configuration several devices are activated
by the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see
Figure 12-3), in order to build a chain. The end of the chain is connected to the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
Data Sheet
60
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
device 1
SPI
device 2
SPI
device 3
SPI
SI
SO SI
SO SI
SO
MO
MI
MCSN
MCLK
SPI_DaisyChain_1.emf
Figure 12-3 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from the SI line is shifted in with each
SCLK. The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is
finished. In single chip configuration, the CSN line must turn HIGH to make the device acknowledge the transferred
data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using
three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices (depending on how
many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must turn HIGH (see
Figure 12-4).
SO device 3
SI device 3
SO device 2
SI device 2
SO device 1
SI device 1
MI
MO
MCSN
MCLK
SPI_DaisyChain_2.emf
Figure 12-4 Data Transfer in Daisy Chain Configuration
Data Sheet
61
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
12.3
Timing Diagrams
tCS(lead)
tCS(lag)
tCS(td)
tSCLK(P )
0.7VDD
0.2VDD
CSN
tSCLK (H)
tSCLK (L)
0.7VDD
0.2VDD
SCLK
SI
tSI (s u)
tSI (h)
0.7VDD
0.2VDD
tSO(en)
tSO(v )
tSO (dis)
0.7V
cc
SO
0.2V
cc
SPI_Timings.emf
Figure 12-5 Timing Diagram SPI Access
Data Sheet
62
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
12.4
Electrical Characteristics
VIN = 8V to 36V, Tj = -40°C to +150°C, all voltages with respect to ground; (unless otherwise specified)
Table 12-1 EC Serial Peripheral Interface (SPI)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Number
Min.
Max.
Input Characteristics (CSN, SCLK, SI) - LOW level of pin
CSN
SCLK
SI
VCSN(L)
VSCLK(L)
VSI(L)
0
0
0
–
–
–
0.8
0.8
0.8
V
V
V
–
P_12.4.1
P_12.4.2
P_12.4.3
–
–
Input Characteristics (CSN, SCLK, SI) - HIGH level of pin
CSN
SCLK
SI
VCSN(H)
VSCLK(H)
VSI(H)
2
–
VDD
VDD
VDD
94
V
–
–
–
P_12.4.4
P_12.4.5
P_12.4.6
P_12.4.7
2
–
V
2
–
V
L-input pull-up current at CSN pin -ICSN(L)
H-input pull-up current at CSN pin -ICSN(H)
L-Input Pull-Down Current at Pin
31
63
μA
V
V
DD = 5 V;
CSN = 0.8 V;
22
45
67
μA
V
V
DD = 5 V;
CSN = 2 V;
P_12.4.8
SCLK
ISCLK(L)
ISI(L)
6
6
12
12
18
18
μA
μA
V
SCLK = 0.8 V;
P_12.4.9
SI
VSI = 0.8 V;
P_12.4.10
H-Input Pull-Down Current at Pin
SCLK
ISCLK(H)
ISI(H)
15
15
30
30
45
45
μA
μA
V
SCLK = 2 V;
P_12.4.11
P_12.4.12
SI
VSI = 2 V;
Output Characteristics (SO)
L level output voltage
H level output voltage
VSO(L)
VSO(H)
0
–
–
0.4
V
V
I
I
SO = -2 mA;
SO = 2 mA;
P_12.4.13
P_12.4.14
VDD
-
VDD
0.4 V
V
DD = 5 V;
Output tristate leakage current
Output tristate leakage current
Timings
ISO(OFF)
ISO(OFF)
-1
–
–
1
1
μA
μA
V
V
CSN = VDD;
SO = 0 V;
P_12.4.15
P_12.4.16
-1
V
V
CSN = VDD;
SO = VDD;
1)
Enable lead time (falling CSN to
rising SCLK)
tCSN(lead) 200
–
–
–
–
–
ns
ns
ns
ns
P_12.4.17
P_12.4.18
P_12.4.19
P_12.4.20
V
1)
DD = 4.5 V;
DD = 4.5 V;
DD = 4.5 V;
DD = 4.5 V;
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag)
200
250
–
–
V
1)
Transfer delay time (rising CSN to tCSN(td)
falling CSN)
–
V
1)
Output enable time (falling CSN to tSO(en)
SO valid)
200
V
CL = 20 pF at SO
pin;
Data Sheet
63
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
Table 12-1 EC Serial Peripheral Interface (SPI) (cont’d)
Parameter Symbol
Values
Typ.
–
Unit Note /
Test Condition
Number
Min.
Max.
1)
Output disable time (rising CSN to tSO(dis)
–
200
ns
P_12.4.21
SO tristate)
V
DD = 4.5 V;
CL = 20 pF at SO
pin;
1)
Serial clock frequency
Serial clock period
fSCLK
–
–
–
–
–
–
–
–
5
MHz
ns
P_12.4.22
P_12.4.24
P_12.4.25
P_12.4.26
P_12.4.27
P_12.4.28
P_12.4.29
V
1)
DD = 4.5 V;
DD = 4.5 V;
DD = 4.5 V;
DD = 4.5 V;
DD = 4.5 V;
DD = 4.5 V;
DD = 4.5 V;
tSCLK(P)
tSCLK(H)
tSCLK(L)
200
75
75
20
20
–
–
V
1)
Serial clock HIGH time
Serial clock LOW time
–
ns
V
1)
–
ns
V
1)
Data setup time (required time SI to tSI(su)
falling SCLK)
–
ns
V
1)
Data hold time (falling SCLK to SI) tSI(h)
–
ns
V
1)
Output data valid time with
capacitive load
tSO(v)
100
ns
V
CL = 20 pF;
1) Not subject to production test, specified by design
Data Sheet
64
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
12.5
SPI Protocol
The relationship between SI and SO content during SPI communication is shown in Figure 12-6. The SI line
represents the frame sent from the µC and the SO line is the answer provided by the TLD5541-1QV. The first SO
response is the response from the previous command.
SI
frame A
frame B
frame C
(previous
response)
response to
frame A
response to
frame B
SO
SPI_SI2SO.emf
Figure 12-6 Relationship between SI and SO during SPI communication
The SPI protocol will provide the answer to a command frame only with the next transmission triggered by the µC.
Although the biggest majority of commands and frames implemented in TLD5541-1QV can be decoded without
the knowledge of what happened before, it is advisable to consider what the µC sent in the previous transmission
to decode TLD5541-1QV response frame completely.
More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows:
SI
write register A
read register A
(new command)
(previous
response)
Standard
diagnostic
register A
content
SO
SPI_RWseq.emf
Figure 12-7 Register content sent back to µC
There are 3 special situations where the frame sent back to the µC doesn't depend on the previously received
frame:
•
•
•
in case an error in transmission happened during the previous frame (for instance, the clock pulses were not
multiple of 8 with a minimum of 16 bits), shown in Figure 12-8
when TLD5541-1QV logic supply comes out of an Undervoltage reset condition (VDD<VDD(UV) as shown in
Figure 12-9 or EN/INUVLO < VEN/INUVLOth
)
in case of a read or write command for a “not used” or “reserved” register (in this case TLD5541-1QV answers
with Standard Diagnosis at the next SPI transmission)
Data Sheet
65
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
frame A
(error in trans .)
(new
command)
SI
(previous
response)
Standard diag +
TER
SO
SPI_SO_TER.emf
Figure 12-8 TLD5541-1QV response after a error in transmission
VDD ≥ VDD(PO)
SI
frame A
frame B
frame C
Standard diag + TER
SO
(SO = „Z“)
response to frame B
SPI _SO_POR.emf
Figure 12-9 TLD5541-1QV response after coming out of Power-On reset at VDD
Data Sheet
66
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
12.6
SPI Registers Overview
15 14
Frame W/R RB ADDR
Write Register in bank 0
ADDR
Read Register in bank 0
ADDR
Read Standard Diagnosis
13
12 11 10
9
8
7
6
5
4
3
2
1
0
Data
SI
SI
SI
1
0
Data
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
x
x
x
x
x
x
x
x
Reading a register needs two SPI frames. In the first frame the read command is sent. In the second frame the
output at SPI signal SO will contain the requested information. The MSB will be HIGH (while in case of standard
diagnosis is LOW). A new command can be executed in the second frame.
12.6.1
Standard Diagnosis
The Standard Diagnosis reports several diagnostic informations and the status of the device and the utility
routines.
The bits UVLORST, TER, VINOVLO, OUTOV, IVCCUVLO, OL and SHRTLED are latched and automatically
cleared after a STD diagnosis reading (default condition if OUTOVLT is not set).
A CLRLAT command resets the diagnostic Latched Flags and Latched protections for the OUTOV, TSD bits,
restarting the switching activity if this was halted due the previously mentioned faults.
Note that the OUTOV has latched behavior only when SWTMOD.OUTOVLAT=1, see Chapter 10.2.2 for further
details.
The TSD bit is always latched and clearable only via explicit CLRLAT command.
The STD bits which are real time status monitors or mirror of internal registers are not cleared after a STD
diagnosis reading or via explicit CLRLAT command:
•
•
•
The STATE bits and TW are real time status flags.
The bits EOMON, EOMFS and EOCAL are mirror of internal register.
The SWRST_BSTUV bit is the logic OR of :
•
•
latched SWRST flag after a DVCSTRL.SWRST command (clearable via STD Diagnosis reading )
real time monitor of gate driver undervolage (VBSTx-VSWNx_UVth)
In standard operating condition (active state, no Limp Home), if no special routines have been executed and no
faults have been detected, the readout of the STD should be 1000H.
15
14
13
12 11 10
9
8
7
6
5
4
3
2
1
0
0
SWRST UVLO STATE TER EO
EOM EOC VINO OUTOV IVCCU OL SHRTL TSD TW
_BSTUV RST MON FS
AL
VLO
VLO
ED
Data Sheet
67
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
SWRST OR VBSTx-VSWNx_UVth Monitor
SWRST_BSTUV 14
r
0B
1B
, no SWRST or undervoltage on the Gate Drivers occured
, there was at least one SWRST since last readout OR an
undervoltage condition at the gate drivers is occurring
UVLORST
STATE
13
r
r
VDD OR VEN/INUVLO Undervoltage Monitor
0B
1B
, there was no VDD OR VEN/INUVLO undervoltage since last readout
, there was at least one VDD undervoltage OR VEN/INUVLO
undervoltage condition since last readout
12:11
Operative State Monitor
00B , (reserved)
01B , Limp Home Mode
10B , Active Mode
11B , Idle Mode
TER
10
9
r
r
Transmission Error
0B
, Previous transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
, Previous transmission failed or first transmission after reset
1B
EOMON
End of LED/Input Current Monitor Routine Bit
0B
, Current monitoring routine not completed, not successfully
performed or never run.
1B
, Current Monitor routine successfully performed (is reset to 0B
when SOMON is set to 1B)
EOMFS
EOCAL
8
7
6
r
r
r
End of MFS Routine Bit
0B
, MFS routine not completed, not successfully performed or
never run.
1B
, MFS routine successfully performed (is reset to 0B when
SOMOFS is set to 1B)
End of Calibration Routine
0B
, Calibration routine not completed, not successfully performed
or never run.
1B
, Calibration routine successfully performed (is reset to 0B when
SOCAL is set to 1B)
VINOVLO
VINOVLO Voltage Monitor
0B
1B
, VINOVLO below VINOVLOth threshold since last readout
, There was at least one VINOVLO overvoltage condition since last
readout
OUTOV
5
4
r
r
Output overvoltage Monitor
0B
1B
, Output overvoltage not detected since last readout
, Output overvoltage was detected since last readout
IVCCUVLO
IVCC or IVCC_EXT Undervoltage Lockout Monitor
0B
, IVCC and IVCC_EXT above VIVCC_RTH,d or VIVCC_EXT_RTH,d
threshold since last readout
1B
, Undervoltage on IVCC or IVCC_EXT occurred since last
readout
Data Sheet
68
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
Open Load in ON state Diagnosis
OL
3
r
0B
1B
, Open Load condition not detected since last readout
, Open Load condition detected since last readout
SHRTLED
TSD
2
1
0
r
r
r
Shorted LED Diagnosis
0B
1B
, Short circuit condition not detected since last readout
, Short circuit condition detected since last readout
Over Temperature Shutdown
0B
1B
, Tj below temperature shutdown threshold
, Overtemperature condition detected since last readout
TW
Over Temperature Warning
0B
1B
, Tj below temperature warning threshold
, Tj exceeds temperature warning threshold
Data Sheet
69
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
12.6.2
Register structure
Table 12-3 describes in detail the available registers with their bit-fields function, size and position
Table 12-2 shows register addresses and summarize bit-field position inside each register
Table 12-2 Register Bank 0
Bit
15 14 13 12 11 10 9 8
W/ R ADDR
7
6
5
4
3
2
1
0
Name
Data
R
B
LEDCURR W/ 0
ADIM
LEDCURR W/ 0
CAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0 0 ADIMVAL
R
1 1 x
0 1 x
1 0 x
x
x
x
SOCAL EOCAL CALIBVAL
R
SWTMOD W/ 0
R
x
x
OUTOV x
LAT
ENSP FMSP FDEVS
READ READ PREAD
DVCCTRL W/ 0
R
ENCAL CLRL SWR IDLE
AT
ST
MFSSETU W/ 0
0 1 EA_IO ILIM_ SOMF EOMFS LEDCHAIN
UT_M HALF S
P1
R
FS
_MFS
MFSSETU W/ 0
P2
CURRMO W/ 0
0
0
0
0
0
0
1
1
1
0
1
1
1 0 MFSDLY
R
0 0 x
1 1 x
x
SOMO EOMO INCURR
LEDCURR
x
N
R
N
N
REGUSET W/ 0
MON
x
x
REGUMODFB
R
A write to a non existing address is ignored, a read to a non existing register is ignored and the STD Diagnosis
Frame is send out.
Table 12-3 Register description
Register name
Field
Bits Type Purpose
7:0 r/w LED Current Configuration Register
LEDCURRADIM
ADIMVAL
00000000B, analog dimming @ 0% of LED current fixed via
RFB
11110000B, (default) analog dimming @ 100% of LED
current fixed via RFB
Data Sheet
70
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
Table 12-3 Register description (cont’d)
Register name
Field
Bits Type Purpose
3:0 r/w
LEDCURRCAL
CALIBVAL
LED Current Accuracy Trimming Configuration Register
LED current calibration value definition, the first bit is the
calibration sign:
0000B, (default) Initial state in the middle of the range
0111B, maximum calibration value positive
1111B, maximum calibration value negative
EOCAL
4
r
End of calibration routine signalling bit:
0B
, (default) calibration routine not completed, not
successfully performed or never run.
, calibration successfully performed (is reset to 0B
when SOCALis set to 1B)
1B
SOCAL
5
0
r/w
r/w
Start of calibration routine signalling bit:
0B
1B
, (default) no calibration routine started
, calibration routine start (autoclear)
SWTMOD
FDEVSPREAD
Switching Mode Configuration Register
Deviation Frequency fDEV definition:
0B
1B
, (default) ±16% of fSW
, ±8% of fSW
FMSPREAD
ENSPREAD
OUTOVLAT
1
2
4
r/w
r/w
r/w
Frequency Modulation Frequency fFM definition:
0B
, (default) 12kHz
1B
, 18kHz
Enable Spread Spectrum feature:
0B
1B
, (default) Spread Spectrum modulation disabled
, Spread Spectrum modulation enabled
Output latch after overvoltage error enable Bit
0B
, (default) gate driver outputs are autorestarting after
an overvoltage event
1B
, gate drivers are latched in brake low condition and bit
is latched after an overvoltage event
DVCCTRL
IDLE
0
r/w
Device Control Register
IDLE mode configuration bit:
0B
1B
, ACTIVE mode (default)
, IDLE mode
SWRST
CLRLAT
ENCAL
1
2
3
r/w
r/w
r/w
Software reset bit:
0B
1B
, (default) normal operation
, execute reset command
Clear Latch bit:
0B
1B
, (default) normal operation
, execute CLRLAT command
Enable automatic output current calibration bit:
0B
1B
, (default) DAC takes CALIBVAL from SPI registers
, DAC takes CALIBVAL from last completed automatic
calibration procedure; SOCAL Bit can be set.
Data Sheet
71
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
Table 12-3 Register description (cont’d)
Register name
Field
Bits Type Purpose
MFSSETUP1
LEDCHAIN
3:0 r/w
Multifloat Switch and LED Count configuration Register
Number of LEDs in series informations bits: change the
V
VFB1,2_S2G threshold and set the MFS jump Initial/Final LED
number
0001B, 1 LED
0010B, 2 LEDs
0011B, 3 LEDs
0100B, 4 LEDs
0101B, 5 LEDs
0110B, 6 LEDs
0111B, 7 LEDs
1000B, (default) 8 LEDs
1001B, 9 LEDs
1010B, 10 LEDs
1011B, 11 LEDs
1100B, 12 LEDs
1101B, 13 LEDs
1110B, 14 LEDs
1111B, 15 LEDs
0000B, 16 LEDs
EOMFS
4
r
End of MFS routine bit:
0B
, (default) MFS routine not completed, not successful
performed or never run.
1B
, MFS routine successfully performed (is reset to 0B
when SOMFSis set to 1B).
SOMFS
5
6
r/w
r/w
Start of MFS routine bit:
0B
1B
, (default) MFS routine not activated
, MFS routine activated
ILIM_HALF
Adjust Current Limit (Switch Peak Over Current Threshold)
during MFS operation:
0B
1B
, (default) Switch Peak Over Current Threshold 100%
, Switch Peak Over Current Threshold 50%
EA_IOUT_MFS
MFSDLY
7
r/w
Bit to decrease the saturation current of the error amplifier
(A6) in current mode control loop only during MFS routine:
0B
1B
, (default) inactive
, active: error amplifier current reduced to 20%
MFSSETUP2
7:0 r/w
Multifloatswitch configuration register 2 (delay time
programming)
00000000B, smallest delay time in respect to fSW
11111111B, largest delay time in respect to fSW
10000000B, (default) delay time in respect to fSW
Data Sheet
72
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
Table 12-3 Register description (cont’d)
Register name
Field
Bits Type Purpose
CURRMON
LEDCURR
1:0
r
Current Monitor Register
Status of the LED Current bits:
00B , (default) LED current between Target and +25%
01B , LED current above +25% of Target
10B , LED current between Target and -25%
11B , LED current below -25% of Target
INCURR
EOMON
3:2
r
r
Status of the Input Current bits:
00B , (default) Input current between 75% and 90% of Limit
01B , Input current between 90% and the Limit
10B , Input current between 60% and 75% of Limit
11B , Input current below 60% of Limit
4
End of LED/Input Current Monitoring bit:
0B
, (default) Current monitoring routine not completed,
not successfully performed or never run.
1B
, Current Monitor routine successfully performed (is
reset to 0B when SOMONis set to 1B)
SOMON
5
r/w
r
Start of LED/Input Current Monitoring bit:
0B
1B
, (default) Current monitor routine not started
, Start of the current monitor routine
REGUSETMON
REGUMODFB
3:2
Regulation Setup And Monitor Register
Feedback of Regulation Mode bits:
01B , (default) Buck
10B , Boost
11B , Buck-Boost
Data Sheet
73
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Application Information
13
Application Information
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 36 Application Drawing - TLD5541-1QV as current regulator
Table 13
BOM - TLD5541-1QV as current regulator (IOUT = 1 A, fSW = 300 kHz)
Manufacturer Part Number
Reference Designator Value
Type
Quantity
D1, D2
CIN1
Schottky Diode
TBD
TBD
Diode
2
1
5
1
1
1
5
2
1
2
1
1
1
1
1
1 µF, 100 V
4.7 µF, 100 V
470 nF, 100 V
22 nF, 16 V
22 nF, 16 V
4.7 µF, 100 V
100 nF, 100 V
10 µF, 16 V
100 nF, 16 V
--
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
Infineon
Coilcraft
Panasonic
Panasonic
Panasonic
X7R
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
IC
CIN2
X7R
Cfilter
X7R
CCOMP
CSOFT_START
COUT1
X7R
X7R
X7R
COUT2 , COUT3
X7R
CIVCC
X7R
CBST1 , CBST2
X7R
IC1
LOUT
Rfilter
RFB
RIN
TLD5541-1QV
10 µH
XAL1010-103MEC Inductor
50 ꢀ, 1%
TBD
TBD
TBD
Resistor
Resistor
Resistor
0.150 ꢀ, 1%
0.003 ꢀ, 1%
Data Sheet
74
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Application Information
Table 13
Reference Designator Value
R1; R2; R3; RPD; REN; xx kꢀ, 1%
BOM - TLD5541-1QV as current regulator (IOUT = 1 A, fSW = 300 kHz)
Manufacturer Part Number
Type
Quantity
Panasonic
TBD
Resistor
13
RPWMI; RSense1; RSense2
;
RSYNC; RSCLK; RSI; RSO;
RCSN
R
VFBL, RVFBH
1.5 kꢀ, 56 kꢀ, 1% Panasonic
TBD
Resistor
Resistor
Resistor
Resistor
Transistor
2
1
1
1
2
RCOMP
0 ꢀ, 1%
Panasonic
Panasonic
Panasonic
Infineon
TBD
RFREQ
37.4 kꢀ, 1%
0.005 ꢀ, 1%
TBD
RSWCS
ERJB1CFR05U
IPG20N10S4L-35
M1 , M2 , M3 , M4
Dual MOSFET :
100 V/35 mꢀ N-ch
Figure 37 Application Drawing - TLD5541-1QV as voltage regulator
Table 14
BOM - TLD5541-1QV as voltage regulator
Manufacturer Part Number
Reference Designator Value
Type
Quantity
D1, D2
CIN1
Schottky Diode
TBD
TBD
X7R
X7R
X7R
X7R
X7R
X7R
Diode
2
1
5
1
1
1
5
1 µF, 100 V
4.7 µF, 100 V
470 nF, 100 V
22 nF, 16 V
22 nF, 16 V
4.7 µF, 100 V
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
EPCOS
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
CIN2
Cfilter
CCOMP
CSOFT_START
COUT1
Data Sheet
75
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Application Information
Table 14
Reference Designator Value
OUT2 , COUT3 100 nF, 100 V
CIVCC
BST1 , CBST2
BOM - TLD5541-1QV as voltage regulator
Manufacturer Part Number
Type
Quantity
C
EPCOS
X7R
Capacitor
Capacitor
Capacitor
IC
2
10 µF, 16 V
100 nF, 16 V
--
EPCOS
X7R
1
C
EPCOS
X7R
2
IC1
Infineon
TLD5541-1QV
1
LOUT
Rfilter
10 µH
Coilcraft
XAL1010-103MEC Inductor
1
50 ꢀ, 1%
xx ꢀ, 1%
0.003 ꢀ, 1%
xx kꢀ, 1%
Panasonic
Panasonic
Panasonic
Panasonic
TBD
TBD
TBD
TBD
Resistor
Resistor
Resistor
Resistor
1
RFB1 , RFB2 , RFB3
3
RIN
1
R1; R2; R3; RPD; REN;
13
RPWMI; RSense1; RSense2
;
RSYNC; RSCLK; RSI; RSO;
RCSN
R
VFBL, RVFBH
1.5 kꢀ, 56 kꢀ, 1% Panasonic
TBD
Resistor
Resistor
Resistor
Resistor
Transistor
2
1
1
1
2
RCOMP
0 ꢀ, 1%
Panasonic
Panasonic
Panasonic
Infineon
TBD
RFREQ
37.4 kꢀ, 1%
0.005 ꢀ, 1%
TBD
RSWCS
ERJB1CFR05U
IPG20N10S4L-35
M1, M2, M3, M4
Dual MOSFET :
100 V/35 mꢀ N-ch
Data Sheet
76
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Application Information
13.1
Further Application Information
Typical Performance Characteristics of Device
TJꢁ=ꢁ25°C,ꢁVIN=12Vꢁunlessꢁotherwiseꢁspecified
IVCCꢁDropoutꢁvsꢁCurrentꢁ
IVCCꢁVoltageꢁvsꢁTemperature
5,20
5,15
5,10
5,05
5,00
4,95
4,90
4,85
4,80
2,5
2
IIVCC=10mA
Tj=ꢀ40°C
1,5
Tj=150°C
Tj=25°C
1
0,5
0
0
10
20
30
40
50
ꢀ40
10
60
110
LDOꢁcurrentꢁ[mA]
Temperatureꢁ[°C]
IVCCꢁLoadꢁregulationꢁ
V(FBHꢀFBL)ꢁThresholdꢁvsꢁVFBH
5,2
5,15
5,1
154
153
152
151
150
149
148
147
146
AnalogꢁDim.ꢁ=ꢁ100%
5,05
5
4,95
4,9
4,85
4,8
0
10
20
30
40
50
0
10
20
30
40
50
60
IIVCC[mA]
VFBHꢁ[V]
V(FBHꢀFBL)ꢁThresholdꢁvsꢁTemp
IOUTMONꢁVoltageꢁvsꢁTemp
1,44
1,43
1,42
1,41
1,4
154
153
152
151
150
149
148
147
146
AnalogꢁDim.=100%,ꢁFBH=0,15V
AnalogꢁDim.=100%,ꢁFBH=12V
AnalogꢁDim.=100%,ꢁFBH=60V
V(FBHꢀFBL) =ꢁꢁ150mV
1,39
1,38
1,37
1,36
ꢀ40
10
60
110
ꢀ40
10
60
110
Temperatureꢁ[°C]
Temperatureꢁ[°C]
Figure 38 Characterization Diagrams 2
Data Sheet
77
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Application Information
TJꢁ=ꢁ25°C,ꢁVIN=12Vꢁunlessꢁotherwiseꢁspecified
IOUTMONꢁVoltageꢁvsꢁV(FBHꢀFBL)
V(IIN1ꢀIIN2)ꢁThresholdꢁvsꢁTemp
1,4
1,2
1
53
52
51
50
49
48
47
VIIN1=8V
VIIN1=13.5V
VIIN1=55V
0,8
0,6
0,4
0,2
0
0
20
40
60
80
100
120
140
ꢀ40
10
60
110
V(FBHꢀFBL) [mV]
Temperatureꢁ[°C]
IINMONꢁVoltageꢁvsꢁTemp
IFBH ,ꢁIFBL vsꢁVFBH
120
100
80
1,04
1,03
1,02
1,01
1
I_FBLꢁ[uA]
I_FBHꢁ[uA]
V(IIN1ꢀIIN2)ꢁ=ꢁ50mV
V(FBHꢀFBL) =ꢁꢁ150mV
60
40
20
0,99
0,98
0,97
0,96
0
ꢀ20
ꢀ40
0
5
10 15 20 25 30 35 40 45 50 55 60
ꢀ40
10
60
110
VFBHꢁ[V]
Temperatureꢁ[°C]
OscillatorꢁFrequencyꢁvsꢁTemp
V(BSTxꢀSWNx)ꢁvsꢁTemp
800
700
600
500
400
300
200
100
4
3,9
3,8
3,7
3,6
3,5
3,4
3,3
3,2
3,1
R_FREQ=61.9ꢁkOhm
R_FREQ=37.4ꢁkOhm
R_FREQ=12.7ꢁkOhm
VBSTxꢀVSWNx_decꢁ[V]
VBSTxꢀVSWNx_incꢁ[V]
ꢀ40
10
60
110
ꢀ40
10
60
110
Temperatureꢁ[°C]
Temperatureꢁ[°C]
Figure 39 Characterization Diagrams 3
Data Sheet
78
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Application Information
TJꢁ=ꢁ25°C,ꢁVIN=12Vꢁunlessꢁotherwiseꢁspecified
LSGDxꢁonꢀstateꢁresistanceꢁvsꢁTemp
HSGDxꢁonꢁresistanceꢁvsꢁTemp
4,5
4
4,5
4
HSGDx_Pullꢀup
3,5
3
3,5
3
HSGDx_Pullꢀdown
LSGDx_PullꢀUp
2,5
2
2,5
2
LSGDx_Pullꢀdown
1,5
1
1,5
1
0,5
0
0,5
0
ꢀ40
10
60
110
ꢀ40
10
60
110
Temperatureꢁ[°C]
Temperatureꢁ[°C]
VCOMP VoltageꢁvsꢁDutyꢁCycle
V(SWCSꢀSGND) TresholdꢁvsꢁTemp
120
100
80
60
40
20
0
60
40
Boost
Buck
DC_Buckꢁ[%]
DC_Boostꢁ[%]
V(SWCSꢀSGND) =0
20
0
ꢀ20
ꢀ40
ꢀ60
0,6
0,8
1
1,2
1,4
1,6
ꢀ40
10
60
110
VCOMPꢁ[V]
Temperatureꢁ[°C]
Figure 40 Characterization Diagrams 3
For further information you may contact http://www.infineon.com/
•
Data Sheet
79
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Package Outlines
14
Package Outlines
0ꢀ9 MAXꢀ
11 x 0ꢀ5 = 5ꢀ5
(0ꢀ65)
0ꢀ1
7
A
0ꢀ5
0ꢀ26
0ꢀ03
6ꢀ8
0ꢀ1
+0ꢀ031)
2)
37
B
0ꢀ05
36
25
0ꢀ13
24
48x
0ꢀ08
48
13
1
12
Index Marking
48x
0ꢀ1
0ꢀ4 x 45°
0ꢀ05
Index Marking
0ꢀ23
(0ꢀ35)
M
A B C
(0ꢀ2)
(5ꢀ2)
(6)
C
0ꢀ05 MAXꢀ
1) Vertical burr 0ꢀ03 maxꢀ, all sides
2) These four metal areas have exposed diepad potential
PG-VQFN-48-29, -31-PO V05
Figure 41 PG-VQFN-48-31 (with LTI)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Data Sheet
80
Rev. 1.0, 2016-05-20
H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Revision History
15
Revision History
Revision
Date
Changes
Released Datasheet
Rev. 1.0
2016-05-20
Data Sheet
81
Rev. 1.0, 2016-05-20
Edition 2016-05-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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