TLD6098-1EP [INFINEON]
LITIX™ Power TLD6098-1EP is a DC-DC boost controller with spread spectrum frequency modulation and with built-in diagnosis and protection features especially designed for LED drivers.;
| 型号： | TLD6098-1EP |
| 厂家： | 
Infineon |
| 描述： | LITIX™ Power TLD6098-1EP is a DC-DC boost controller with spread spectrum frequency modulation and with built-in diagnosis and protection features especially designed for LED drivers. |
| 文件： | 总48页 (文件大小：1094K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
Features
•
Wide input voltage (up to 58 V) and output voltage range
(up to 70 V)
•
Switching frequency range from 100 kHz to 500 kHz and
synchronization at 2.2 MHz with an external clock source
•
•
•
EMC optimized device
Analog adjust input
Overvoltage, Short to ground, overcurrent, open feedback
and overtemperature diagnostic output
Product type Package
Marking
•
•
PMOS gate driver for dimming and protection with
enhanced dimming features
LED current accuracy ±3.5%
TLD6098-1EP PG-TSDSO-14 TLD6098-1
Potential applications
•
•
LED driver for: front light module, rear light module, interior light
Voltage regulator
VS
L1
D1
RFB
MP
CBO
LED1
LED2
IVCC
IN
MN
SWO
IVCC
CIVCC
LED3
LED4
LED5
LED6
LED7
LED8
SWCS
FPWM/FAULT
RSWCS
RFAULT
FBH
FBL
FREQ/SYNC/SPREAD
RFREQ
IVCC
RSETH
RVFBH
SET
VFB
IVCC
RSETL
RVFBL
RDCH
DC/PWMI
COMP
PWMO
GND
RDCL
CCOMP1
RCOMP
CCOMP2
TLD6098-1EP
B2G-1ch.vsdx
Figure 1
Application diagram
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
Description of TLD6098-1EP
Description of TLD6098-1EP
TLD6098-1EP is a multi-topology DC-DC controller designed for LED applications with built-in protection
features to implement a compact LED driver.
The output current is regulated by means of peak current control loop. An internal slope compensation is used
to avoid sub-harmonic oscillation at high duty cycle (e.g. higher than 50%).
The current accuracy is better than 3.5% (with no analog adjustment applied) over the operating temperature
range. A rail to rail current sense amplifier provides flexibility on the topology choice needed to supply LED
string with more than 20 white LED (up to 70 V at output).
The switching frequency can be adjusted from 100 kHz to 500 kHz using an external resistor. A synchronization
with an external clock is also possible. The device incorporates even a spread spectrum modulator to achieve
easy fulfilment of electromagnetic emission standards.
TLD6098-1EP can drive an external PMOS for dimming and protection.
For this purpose the device incorporates even a PWM generator controlled by an analog voltage on DC/PWMI
pin. The generated PWM signal has the duty cycle adjustable from 0 to 100% with 10 bits of resolution and the
frequency range programmable from 150 Hz to 750 Hz. On the same DC/PWMI pin the digital PWM signal can
also be used.
Product validation
Qualified for automotive applications.
Product validation according to AEC-Q100.
Datasheet
2
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
Table of contents
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
4
4.1
4.2
Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soꢀ start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
5.1
5.2
Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Undervoltage protection for the external switching MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
6.1
Switching frequency setup and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Switching frequency setup with external resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Synchronization with external clock (low frequency mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Synchronization with external clock (high frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.1
6.1.2
6.1.2.1
6.2
6.2.1
6.3
7
Analog output adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7.1
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
8.1
8.2
8.2.1
8.3
Dimming functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Digital PWM dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Embedded PWM engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8.3.1
9
9.1
9.2
9.2.1
9.3
9.3.1
9.4
9.4.1
Protections and fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Short to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Output overvoltage and voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Overvoltage on FBH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Datasheet
3
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
Table of contents
9.5
Output overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.5.1
9.6
9.6.1
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
10
11
12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Datasheet
4
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
1 Block diagram
1
Block diagram
VIVCC
LDO
IVCC
IN
Power on
reset
Internal
supply
On/Off logic +
digital PWM
dimming
EN_INT/
PWM_INT
DC/PWMI
Power switch
gate driver
SWO
Embedded
PWM dimming
generator +
fault report
logic
VM_INT
FPWM/FAULT
Slope comp.
Clock
generator
Switch current
error amplifier
DC/DC
SWCS
FREQ/SYNC/SPREAD
switching
regulator and
logic
Thermal
protection
Leading edge
blanking
V
FBH - VFBL
Soft start
Open load and
short to GND
Over
voltage
VFB
VFBH
protection
VM_INT
gm1
VVFB_REF
COMP
SET
FBL
FBH
gm2
x1
Reference
current
V
FBH - VFBL
generation
VFBH
VIVCC
Dimming
switch
gate driver
PWMO
V
FBH - VFBL
EN_INT/
PWM_INT
GND
Block diagram TLD6098-1.vsdx
Figure 2
Block diagram
Datasheet
5
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
2 Pin configuration
2
Pin configuration
1
2
3
4
5
6
7
14
13
12
11
10
9
PWMO
SET
FBH
FBL
VFB
SWO
IVCC
Exposed
Pad
COMP
FPWM/FAULT
IN
SWCS
GND
DC/PWMI
8
FREQ/SYNC/SPREAD
PIN_POS_14.VSDX
Figure 3
Table 1
Pin configuration PG-TSDSO-14
Pin configuration PG-TSDSO-14
Name
Pos.
Description
Direction
PWMO
1
PMOS driver for dimming and protection
Connect to gate of external MOSFET
Output
Pin must be leꢀ open if external MOSFET is not used
SET
2
3
Analog adjustment
Load current adjustment pin
Pin must not be leꢀ open
If analog adjustment is not used, connect to IVCC pin
Input
IVCC
Internal linear voltage regulator
Used for internal biasing and gate drive
Bypass with external capacitor
Pin must not be leꢀ open
Output
Input
COMP
4
5
Compensation
Connect R and C network for stability
FPWM/FAULT
PWM frequency selector/Fault
Input/
Output
Connect external R to set PWM frequency
Faults are reported by raising the voltage on this pin
IN
6
7
8
Supply
Supply for internal biasing
Input
Input
Input
DC/PWMI
PWM adjustment
Set duty cycle of PWM engine or digital input for PWM dimming
FREQ/SYNC/SPREAD
Frequency selector or synchronization
Connect external resistor to GND to set switching frequency
Apply square waveform for synchronization
(table continues...)
Datasheet
6
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
2 Pin configuration
Table 1
(continued) Pin configuration PG-TSDSO-14
Name
GND
Pos.
9
Description
Ground
Direction
–
SWCS
10
Current sense/Power ground
Input
Detects peak current through power switch
Power ground of gate driver of SWO
SWO
VFB
11
12
Switch gate driver
Connect to gate of external switching power n-channel MOSFET
Output
Input
Overvoltage/Voltage loop reference
Connect to resistive voltage divider to set the maximum voltage
at output and the short to ground threshold
FBL
13
14
EP
Voltage feedback negative
Inverting input (-)
Input
Input
–
FBH
Voltage feedback positive
Non inverting input (+)
Exposed pad
Exposed pad
Used only for heat dissipation
Connect to pin 9 (GND)
Datasheet
7
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
3 General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 2
Absolute maximum ratings
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Not subject to production test, specified by design
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
-0.3
Max.
60
Power supply input
voltage
VIN
–
V
–
PRQ-31
Voltage at pin SET
VSET
-0.3
-0.3
-1
–
–
–
–
–
5.5
60
75
75
75
V
V
V
V
V
–
PRQ-44
PRQ-32
PRQ-33
PRQ-34
PRQ-35
Voltage at pin DC/PWMI VDC/PWMI
–
Voltage at pin FBH
Voltage at pin FBL
VFBH
–
VFBL
-1
–
Differential input
VREF(MAX)
-75
VREF(MAX) = VFBH -VFBL
voltage
Differential signal (not
referred to ground)
Current at pin FBH, FBL IFBH, IFBL
-7.5
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
7.5
5.5
0.3
5.5
5.5
mA
V
VFBH - VFBL = 150 mV
PRQ-36
PRQ-37
PRQ-38
PRQ-39
PRQ-40
Voltage at pin VFB
Voltage at pin SWCS
Voltage at pin SWO
VFB
–
–
–
–
VSWCS
V
VSWO
V
Voltage at pin FPWM/
FAULT
VFPWM/FAULT
V
Voltage at pin COMP
VCOMP
-0.3
-0.3
–
–
5.5
5.5
V
V
–
–
PRQ-41
PRQ-42
Voltage at pin FREQ/
SYNC/SPREAD
VFREQ/SYNC
Voltage at pin PWMO
PMOS output voltage
VPWMO
VPMOS
-0.3
-1
–
–
75
10
V
V
–
PRQ-43
VPMOS = VFBH - VPWMO
PRQ-579
Differential signal (Not
referred to ground)
Voltage at pin IVCC
VIVCC
-0.3
–
5.5
V
–
PRQ-45
Temperature
Junction temperature TJ
-40
-40
–
–
150
150
°C
°C
–
–
PRQ-46
PRQ-47
Storage temperature
Tstg
ESD susceptibility
(table continues...)
Datasheet
8
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
3 General product characteristics
Table 2
(continued) Absolute maximum ratings
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Not subject to production test, specified by design
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
-2
Max.
ESD susceptibility
VESD_HBM
–
2
kV
kV
kV
HBM: ESD
PRQ-48
PRQ-49
PRQ-50
susceptibility, Human
Body Model "HBM"
according to AEC
Q100-002
ESD susceptibility
inner pins
VESD_CDM
-0.5
–
–
0.5
CDM: ESD
susceptibility, Charged
Device Model "CDM"
according to AEC
Q100-011
ESD susceptibility
corner pins
VESD_CDM_CR
-0.75
0.75
CDM: ESD
susceptibility, Charged
Device Model "CDM"
according to AEC
Q100-011
Attention:
1.
Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
2.
Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the datasheet. Fault conditions are considered as "outside" normal operating range.
Protection functions are not designed for repetitive operation.
3.2
Functional range
Table 3
Functional range
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
4.5
Max.
58
1)
Extended power supply VIN_EXT
–
V
PRQ-51
input voltage range
Parameter deviations
possible
Power supply input
voltage operating
range
VIN_OP
8
0
–
–
36
70
V
V
–
PRQ-52
Operating voltage at
pin FBH
VFBH_OP
–
PRQ-581
(table continues...)
Datasheet
9
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
3 General product characteristics
Table 3
(continued) Functional range
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
-0.3
Max.
70
Operating voltage at
pin FBL
VFBL_OP
fSWO
–
V
–
–
–
PRQ-53
PRQ-85
PRQ-90
Switching frequency
adjustment range
100
100
–
–
500
500
kHz
kHz
Synchronization low
frequency capture
range
fFREQ/SYNC/
SPREAD(LF)
Synchronization high
frequency capture
range
fFREQ/SYNC/
SPREAD(HF)
2
–
–
2.4
MHz
Hz
–
–
PRQ-132
PRQ-113
PWMO frequency range fPWMO
150
750
1) Not subject to production test, specified by design
Attention: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
3.3
Thermal resistance
Table 4
Thermal resistance
Not subject to production test, specified by design
Parameter
Symbol
Values
Typ.
20.9
Unit Note or condition
P-
Number
Min.
Max.
1)
Junction to case
RthJC
RthJA
RthJA
RthJA
–
–
–
–
–
–
–
–
K/W
PRQ-54
PRQ-55
PRQ-56
PRQ-57
Junction to ambient
Junction to ambient
Junction to ambient
57.2
K/W
K/W
K/W
2) 2s2p
2) 1s0p + 600 mm2
2) 1s0p + 300 mm2
73.2
85.5
1) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and exposed pads
are fixed to ambient temperature) TA = 25°C dissipates 1 W
2) Specified RthJA value is according JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) +
heatsink area at natural convection on FR4 board. The device was simulated on 76.2 x 114.3 x 1.5 mm
board. The 2s2p board has 2 outer copper layers (2 x 70 μm Cu) and 2 inner copper layer (2 x 35 μm
Cu). A thermal via (diameter = 0.3 mm and 25 μm plating) array was applied under the exposed pad and
connected the top layer and the inner layers to bottom layers of JEDEC PCB. TA = 25°C; IC dissipates 1 W
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For further
information visit https://www.jedec.org
Datasheet
10
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
4 Switching regulator
4
Switching regulator
TLD6098-1EP implements a regulator suitable for Boost-to-ground, Boost-to-battery, Buck-to-battery, SEPIC,
Flyback and Cuk configurations.
The device has two distinct control loops:
•
•
A current control loop (always enabled)
A voltage control loop (optional)
If the voltage loop is enabled the device regulates the output current as long as the feedback voltage on
the VFB pin is below the VFB voltage mode ON threshold (VVFB_VM(ON)). The voltage control loop takes over
and regulates the output voltage once the VFB reference voltage VVFB_REF is reached.
The controller generates a PWM signal by sensing the inductor peak current and the output of the internal error
amplifier. The control signal is applied to the internal gate driver connected to SWO pin to drive the external
n-channel MOSFET
4.1
Soꢀ start
The soꢀ start routine has 2 functionalities:
•
•
Limiting the input current and output overshoot
Guaranteeing that the system output reaches the target value in a reasonable time even when being
operated in PWM dimming with low duty cycles
The first rising edge on DC/PWMI pin or the first cycle of the embedded PWM engine enables the soꢀ start
routine.
It is then performed in the following cases:
•
•
•
•
•
At start-up
Aꢀer an overvoltage on FBH pin
Aꢀer an overvoltage on VFB pin
Aꢀer an overtemperature fault
Aꢀer an undervoltage on IVCC pin
The soꢀ start is applied aꢀer a short to ground fault and retriggered every tFAULT in case of continuous presence
of the fault.
The operation of the soꢀ start is conditioned by the analog output adjustment.
During the soꢀ start the switching regulator adjusts the PWM signal to make the voltage between FBH and FBL
evolve from 0 to VREF(100%)in tSS time. The evolution is performed in 15 steps if the analog adjustment is not
applied, otherwise the intended steady-state is reached before the soꢀ start ends.
An ON time extension of the PWM dimming pulses is applied to ensure a reasonable power-up time when a low
duty cycle dimming is applied.
Datasheet
11
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
4 Switching regulator
VIN
VIN(ON)
t
t
VDC/PWMI
V
FBH - VFBL
VREF
VPWM_EXT
t
ON time extension
SWO
Gate driver
enabled
Gate driver enabled
t
t
PWMO
PMOS
OFF
PMOS
OFF
PMOS
OFF
PMOS ON
PMOS ON
soft start timing diagram.vsdx
Figure 4
Soꢀ start timing diagram (the linear waveform of VVFBH-VVFBL is an example of possible
scenario)
The ON time extension is triggered if :
•
The applied PWM dimming signal (or the signal generated by the PWM engine) has an ON time shorter than
tSS during the soꢀ start
and
•
The voltage across FBH and FBL is lower than the reference voltage during PWM extension VPWM_EXT at the
end of the ON time of the PWM signal
The ON time extension lasts as long as the voltage across FBH and FBL reaches the VPWM_EXT.
The VPWM_EXT is limited by the analog output adjustment down to a minimum reference voltage during ON time
extension VPWM_MIN
.
For the first 3 steps of the VREF signal, the VPWM_EXT is higher than VREF
.
If the reference voltage across FBH and FBL adjusted by analog adjustment feature is lower than the VPWM_MIN
the ON time extension ends aꢀer tSS
.
Datasheet
12
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
4 Switching regulator
VREF
VPWM_EXT
VREF(100%)
VREF
VPWM_EXT
VPWM_MIN
t
tSS
VREF evolution during soft-start.vsdx
Figure 5
VREF and VPWM_EXT waveforms during the soꢀ start routine without analog output
adjustment
VREF
VPWM_EXT
Soft start steady state
Adjusted VREF
VREF
VPWM_EXT
VPWM_MIN
t
tSS
VREF evolution during soft-start.vsdx
Figure 6
VREF and VPWM_EXT waveforms during the soꢀ start routine with analog output
adjustment
If the ON time extension ends before tSS elapsed, the ON time extension is retriggered in the following PWM
cycle, in case the voltage between FBH and FBL is once again lower than VPWM_EXT
When the ON time extension ends, the remaining part of the soꢀ start is allowed to evolve during the following
ON time of the PWM dimming signal. In this case the actual duration of soꢀ start could be longer than tSS
.
Datasheet
13
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
4 Switching regulator
4.2
Electrical characteristics
Table 5
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
Regulator
VFB reference voltage VVFB_REF
(voltage loop)
1.568 1.6
144.75 150
1.632
V
–
PRQ-142
Current loop reference VREF(100%)
155.25 mV
Differential signal (not PRQ-66
voltage
referred to ground)
VREF = VFBH - VFBL
VSET = 5 V
1)
Current loop reference VREF(40%)
voltage
54.6
–
60
–
65.4
10
mV
mV
PRQ-67
Differential signal (not
referred to ground)
VSET = 940 mV
Current loop reference VREF(0%)
Differential signal (not PRQ-68
voltage
referred to ground)
VSET = 100 mV
1)
Transconductance
error amplifier voltage
loop
gm1
–
–
0.95
1.6
–
–
mS
mS
PRQ-600
1)
Transconductance
error amplifier current
loop
gm2
PRQ-463
Switch current limit
threshold
VSWCS_TH
80
91
88
100
–
120
–
mV
%
–
PRQ-69
PRQ-70
PRQ-71
Maximum duty cycle in DMAX
adjust. freq. mode
RFREQ/SYNC/
SPREAD = 27 kΩ
Maximum duty cycle
in low frequency sync
mode
DMAX(LF)
–
–
%
fSW = 500 kHz
Maximum duty cycle
in high frequency sync
mode
DMAX(HF)
80
–
2
–
%
fSW = 2.2 MHz
PRQ-289
1)
1)
Soꢀ start time
tSS
1.8
–
2.2
–
ms
V
PRQ-72
Reference voltage
VPWM_EXT
0.8*VRE
PRQ-588
during PWM extension
F1,2
VPWM_EXT > VPWM_MIN
1)
Minimum reference
voltage during PWM
extension
VPWM_MIN
–
31.5
–
mV
PRQ-589
(table continues...)
Datasheet
14
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
4 Switching regulator
Table 5
(continued) Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
800
Input current at pin
FBH
IFBH
IFBL
IFBH
–
–
–
550
μA
μA
μA
VFBH - VFBL = 0.15 V
VFBH = 60 V
PRQ-73
PRQ-74
PRQ-75
Input current at pin
FBL
50
50
70
70
VFBH - VFBL = 0.15 V
VFBH = 60 V
Input current at pin
FBH
VFBH - VFBL = 0.15 V
VFBL = 0 V
Current flows out of
pin
Input current at pin
FBL
IFBL
–
–
50
70
μA
VFBH - VFBL = 0.15 V
VFBL = 0 V
Current flows out of
pin
PRQ-76
1)
Threshold voltage high VFBH_HSS
side sensing
2.55
2.3
2.8
–
V
V
PRQ-267
PRQ-268
VFBH increasing
1)
Threshold voltage low VFBH_LSS
2.1
side sensing
VFBH decreasing
Power supply
undervoltage
shutdown
VIN(OFF)
2.5
–
–
–
5
4.5
5.5
8
V
VIN decreasing
VIN increasing
PRQ-77
PRQ-78
PRQ-426
Power supply
minimum startup
voltage
VIN(ON)
V
Power supply current IIN
–
mA
VDC/PWMI = 0 V
consumption
VSET = VIVCC
RFREQ/SYNC/SPREAD
=
33 kΩ
RFPWM/FAULT = 57 kΩ
no faults detected
Gate driver for external switch
1)
Gate driver peak
output current
ISWO
1
–
–
A
PRQ-79
VSWO increasing 1 V to
4 V
Current flows out of
pin
(table continues...)
Datasheet
15
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
4 Switching regulator
Table 5
(continued) Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
1)
Gate driver peak
output current
ISWO
1
–
–
–
A
PRQ-80
PRQ-81
VSWO decreasing 4 V to
1 V
1)
Gate driver output rise tR_SWO
time
–
–
20
20
ns
CL_SWO = 3.3 nF
VSWO increasing 1 V to
4 V
1)
Gate driver output fall tF_SWO
–
ns
PRQ-82
time
CL_SWO = 3.3 nF
VSWO decreasing 4 V to
1 V
1)
Gate driver high side
resistance
RSWO_HS
RSWO_LS
–
–
1
1
3
3
Ω
PRQ-83
ISWO = -10 mA
1)
Gate driver low side
resistance
Ω
PRQ-196
ISWO = 10 mA
1) Not subject to production test, specified by design
Datasheet
16
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
5 Linear regulator
5
Linear regulator
The device incorporates a linear regulator to generate a 5 V output used to supply the internal gate drivers
and, through IVCC pin, other auxiliary devices on the PCB (for example a microcontroller and resistor dividers).
The maximum output current of the linear regulator is limited to the IVCC output current limit IIVCC
.
If the load on IVCC (gate drivers plus connected devices on PCB) draws more than IIVCC the linear regulator
output voltage decreases.
The linear regulator starts to deliver current to IVCC pin when the input voltage VIN goes above the power supply
minimum start up voltage VIN (ON) for a time longer than IVCC start time tST
A low ESR capacitor has to be connected from IVCC to ground (CIVCC in the figure) to stabilize the output voltage
of the linear regulator.
The ESR of the capacitor CIVCC has to be lower than IVCC buffer capacitor ESR RIVCC(ESR)
.
VS
IN
IVCC
Voltage
regulator
CIVCC
Clock
generator
FREQ/SYNC
DC/PWMI
SWO
Switching
regulator
TLD6098-1EP
Linear regulator on TLD6098-1EP.vsdx
Figure 7
Block diagram of the linear regulator
5.1
Undervoltage protection for the external switching MOSFET
During the ON time of the switching PWM signal, the gate driver has to bias the switching NMOS in deep ohmic
region to avoid the overheating of the MOSFET itself during the conduction time. This is ensured by choosing
a logic level MOSFET with a maximum threshold voltage lower than IVCC undervoltage switch-off threshold
VIVCC_TH_D
.
TLD6098-1EP has an integrated undervoltage reset threshold circuit to disable the gate driver if the VIVCC drops
below the VIVCC_TH_D. The gate driver is then enabled again when the VIVCC goes above the IVCC undervoltage
switch-on threshold VIVCC_TH_I
.
Datasheet
17
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
5 Linear regulator
VIN
VIN(ON)
VIN(OFF)
t
t
VIVCC
VIVCC_TH_I
VIVCC_TH_D
VDC/PWMI
tST
VDC/PWMI(ON)
t
t
VSWO
tSS
tSS
Gate driver
disabled
Gate driver
disabled
Gate driver disabled
Gate driver enabled
Gate driver enbled
VFPWM
Soft start routine
VFPWM/FAULT
t
Timing diagram of linear regulator on TLD6098-1EP.vsdx
Figure 8
Thresholds and timing diagram related to the linear regulator
5.2
Electrical characteristics
Table 6
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
4.85
Max.
5.15
IVCC output voltage
VIVCC
IIVCC
5
V
8 V ≤ VIN ≤ 36 V; 0.1 mA PRQ-58
≤ IIVCC ≤ 40 mA
IVCC output current
limit
51
–
100
mA
8 V < VIN < 13.5 V; VIVCC PRQ-59
< 4.5 V; Current flows
out of pin
IVCC dropout voltage
IVCC start time
VIVCC_DV
tST
–
–
–
–
0.5
V
VIN = 5 V; IIVCC < 20 mA PRQ-60
1)
300
μs
PRQ-285
VIN slew rate higher
than 1 V/10 μs
1)
IVCC buffer capacitor
CIVCC
1
4.7
10
μF
PRQ-61
If embedded PWM
engine is used, 4.7 μF
has to be chosen as a
minimum
(table continues...)
Datasheet
18
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
5 Linear regulator
Table 6
(continued) Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
0.2
1)
IVCC buffer capacitor
RIVCC(ESR)
–
–
Ω
PRQ-62
ESR
Maximum value given
for regulator stability
IVCC undervoltage
switch-off threshold
VIVCC_TH_D
VIVCC_TH_I
3.6
–
–
–
4.0
4.5
V
V
VIVCC decreasing
PRQ-64
PRQ-65
IVCC undervoltage
switch-on threshold
VIVCC increasing
1) Not subject to production test, specified by design
Attention: Select external switching MOSFET with worst case threshold voltage VGS(th) lower than minimum
VIVCC_TH_D
Datasheet
19
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
6 Switching frequency setup and synchronization
6
Switching frequency setup and synchronization
The DC-DC switching frequency is adjusted by a resistor placed from FREQ/SYNC/SPREAD pin to ground or by
providing to this pin a digital clock. The device incorporates also a spread spectrum modulator to reduce the
design effort to fulfill the EMI compliance.
By using a resistor, the switching frequency of the regulator is adjusted in the switching frequency adjustment
range fSWO
.
If an external clock is provided, the device accepts a digital clock in these two working windows:
•
•
Synchronization low frequency capture range fFREQ/SYNC/SPREAD(LF) (low frequency synchronization mode)
Synchronization high frequency capture range fFREQ/SYNC/SPREAD(HF) (high frequency synchronization mode)
Outside these ranges, the device does not recognize a valid clock and then the behavior of the regulator can be
out of specification.
TLD6098-1EP
Spread spectrum
modulator
Clock generator
FREQ/SYNC/SPREAD
DC/DC
Gate
Multiplexer
switching
regulator
SWO
driver
Clock frequency
detector
Oscillator and Synch block-TLD6098-1EP.vsdx
Figure 9
Diagram of switching frequency adjustment and synchronization blocks
6.1
Switching frequency setup with external resistor
The resistor placed on FREQ/SYNC/SPREAD pin adjusts the frequency of the DC-DC and enables or disables the
spread spectrum modulator.
The relationship between the biasing resistor and switching frequency with spread spectrum activated is
1
fSW
=
(1)
1 . 11 · 10−9 · RFREQ/SYNC/SPREAD
The relationship between the biasing resistor and the switching frequency with the spread spectrum not active
is
1
fSW
=
(2)
1 . 11 · 10−10 · RFREQ/SYNC/SPREAD
Datasheet
20
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
6 Switching frequency setup and synchronization
Figure 10
Switching frequency versus RFREQ/SYNC/SPREAD
6.1.1
Electrical characteristics
Table 7
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
288
Max.
378
Switching frequency
fSWO_SSM(OFF)
333
kHz
mA
RFREQ/SYNC/SPREAD
27 kΩ
=
PRQ-277
FREQ/SYNC/SPREAD
output current
IFREQ/SYNC/
SPREAD
–
–
3
VFREQ/SYNC/SPREAD = 0 V PRQ-86
Current flowing out of
pin
FREQ/SYNC/SPREAD
output voltage
VFREQ/SYNC/
SPREAD_SSM(OFF)
0.72
0.8
0.88
V
RFREQ/SYNC/SPREAD
27 kΩ
=
PRQ-87
6.1.2
Spread Spectrum
The spread spectrum modulation technique significantly reduces the electromagnetic harmonics
emission at the lower frequency range of the spectrum (f < 30 MHz).
This technique is enabled by changing the switching frequency over the time. The final result is the movement
over a broad band of the energy associated with the peaks of the electromagnetic harmonics emission.
The switching frequency is modulated with a triangular shape digitalized in 7 steps equally distributed over the
entire frequency span (2 times the frequency deviation fDEV).
Datasheet
21
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
6 Switching frequency setup and synchronization
fSWO
fDEV
fSW_SSM(ON)
fDEV
t
1/fFM
Spread spectrum modulator characteristic.vsdx
Figure 11
Spread spectrum modulator characteristic
6.1.2.1
Electrical characteristics
Table 8
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
288
Max.
378
1)
Average switching
frequency
fSWO_SSM(ON)
333
kHz
PRQ-84
PRQ-88
PRQ-89
PRQ-385
RFREQ/SYNC/SPREAD
=
2.7 kΩ
1)
Modulation frequency fFM
13.5
15
16.5
–
kHz
kHz
V
1.8 kΩ ≤ RFREQ/SYNC/
SPREAD ≤ 9 kΩ
1)
Frequency deviation
fDEV
0.09*fS 0.15*fS
WO
WO
1.8 kΩ ≤ RFREQ/SYNC/
SPREAD ≤ 9 kΩ
FREQ/SYNC/SPREAD
output voltage
VFREQ/SYNC/
SPREAD_SSM(ON)
0.72
0.8
0.88
RFREQ/SYNC/SPREAD =
2.7 kΩ
1) Not subject to production test, specified by design
Datasheet
22
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
6 Switching frequency setup and synchronization
6.2
Synchronization with external clock (low frequency mode)
The switching frequency is synchronized with an external clock source applied on FREQ/SYNC/SPREAD pin if the
frequency is in the synchronization low frequency capture range fFREQ/SYNC/SPREAD(LF) and the duty cycle is in the
synchronization input duty cycle range DCFREQ/SYNC/SPREAD
.
The device detects the external clock source if the voltage on FREQ/SYNC/SPREAD exceeds the two thresholds:
•
•
The synchronization input high voltage VFREQ/SYNC/SPREAD(H) during the positive pulse,
The synchronization input low voltage VFREQ/SYNC/SPREAD(L) during the negative pulse.
VFREQ/SYNC/SPREAD
t
FREQ/SYNC/SPREAD = 1 / fFREQ/SYNC/SPREAD
tFREQ/SYNC/SPREAD(H)
tFREQ/SYNC/SPREAD(ON)
tFREQ/SYNC/SPREAD
DCSWO
=
VFREQ/SYNC/SPREAD(H)
VFREQ/SYNC/SPREAD(L)
t
Timing diagram in synchronization mode.vsdx
Figure 12
Timing diagram when synchronization mode is enabled
6.2.1
Electrical characteristics
Table 9
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
3.0
Max.
Synchronization input VFREQ/SYNC/
high voltage
–
–
V
–
PRQ-91
PRQ-92
PRQ-94
SPREAD(H)
Synchronization input VFREQ/SYNC/
low voltage
–
–
–
0.8
60
V
–
SPREAD(L)
1)
Synchronization input DCFREQ/SYNC/
40
%
duty cycle range
SPREAD
1) Not subject to production test, specified by design
6.3
Synchronization with external clock (high frequency range)
High switching frequency enables a system cost down due to reduced value for the reactive components.
The high frequency synchronization is enabled if the input clock is in the synchronization high frequency
capture range fFREQ/SYNC/SPREAD(HF).
Voltage threshold levels on FREQ/SYNC/SPREAD pin are the same as in the low frequency synchronization
mode.
Datasheet
23
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
7 Analog output adjustment
7
Analog output adjustment
The device adjusts the reference voltage VREF across FBH and FBL pins (thus adjusting the output current) by
monitoring the analog voltage on SET pin (VSET).
The SWO NMOS gate driver is disabled if the voltage applied on the SET pin is lower than SET input voltage no
switching activity VSET(NOSW).
The SET pin has to be connected to a voltage higher than VSET(100%) (e.g. connecting SET pin to IVCC pin) to
exclude the output current adjustment feature.
V
FBH-VFBL
VREF(100%)
VREF(40%)
VREF(0%)
VSET(NOSW) VSET(0%)
VSET(40%)
VSET(100%)
VSET
Gate
driver VREF(0%)
disabled
VREF(100%)
Analog dimming with TLD6098-1EP.vsdx
Figure 13
Relationship between VSET and reference voltage VREF
The SET pin can also be wired to an external thermistor (usually mounted on the LED module) to perform a
thermal protection.
7.1
Electrical characteristics
Table 10
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
2.2
Unit Note or condition
P-
Number
Min.
Max.
1)
SET input voltage
100%
VSET(100%)
–
–
V
PRQ-95
1)
SET input voltage 40% VSET(40%)
–
–
–
940
100
–
–
–
mV
PRQ-429
PRQ-428
PRQ-368
1)
SET input voltage 0%
VSET(0%)
mV
SET input voltage no
switching activity
VSET(NOSW)
50
mV
–
1) Not subject to production test, specified by design
Datasheet
24
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
8 Dimming functions
8
Dimming functions
The TLD6098-1EP offers a dimming input for pulse width modulating (PWM) the output current.
This modulation is beneficial to reduce the average current at output (and then the brightness of the LEDs),
without showing color shiꢀ on the light produced by the LEDs.
The output current modulation is operated by the device as function of the voltage on DC/PWMI pin
•
•
A digital clock signal imposes the duty cycle and the frequency
An analog voltage is translated to a duty cycle and the frequency is adjusted with a resistor on FPWM/
FAULT pin.
Different voltage levels on DC/PWMI pin activates different functions, as described below:
•
•
•
If the voltage is higher than DC/PWMI input voltage high threshold VDC/PWMI(ON) the dimming duty cycle is
set to 100%
If the voltage is in between the two digital thresholds (VDC/PWMI(100%) and VDC/PWMI(0%)), the embedded PWM
dimming function is activated
If the voltage is lower than DC/PWMI input voltage low threshold VDC/PWMI(OFF) the dimming duty cycle is 0%
When a dimming function is activated, the PWM signal controls the switching regulator gate driver and the
PMOS gate driver
To allow fast transitions of the dimming PMOS even at low output voltage, the positive power supply of the
PWMO gate driver is connected to FBH pin if its voltage VFBH is higher than VIVCC, otherwise the gate driver is
supplied by the IVCC pin.
During the ON state of the PWM dimming, the PMOS is biased with a PWMO output voltage ON state VPWMO,ON
(minimum VPWMO,ON cannot go below 0 V).
8.1
Electrical characteristics
Table 11
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
1)
PWMO peak output
current
IPWMO
2
2
5
–
–
mA
PRQ-102
VFBH = 14V
VPWMO increasing
VPWMO(ON) + 0.5 V to
VPWMO(ON) + 3.5 V
CL,PWMO = 3.3 nF
current flows out
of pin
1)
PWMO peak output
current
IPWMO
5
mA
PRQ-103
VFBH = 14V
VPWMO
decreasing VPWMO(OFF)
-
0.5 V to VPWMO(OFF) - 3.5
V
CL,PWMO = 3.3 nF
(table continues...)
Datasheet
25
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
8 Dimming functions
Table 11
(continued) Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
1)
PWMO gate driver
output rise time
tR_PWMO
–
–
2
6
6
μs
PRQ-104
VFBH = 14V
VPWMO increasing
VPWMO(ON) + 0.5 V to
VPWMO(ON) + 3.5 V
CL,PWMO = 3.3 nF
1)
PWMO gate driver
output fall time
tF_PWMO
2
μs
PRQ-105
VFBH = 14 V
VPWMO decreasing
VPWMO(OFF) - 0.5 V to
VPWMO(OFF) - 3.5 V
CPWMO = 3.3 nF
1)
PWMO output voltage VPWMO(ON)
ON state
–
–
VFBH
6.5
-
VFBH - 5 V
PRQ-106
PRQ-107
VFBH > 7.5 V
1)
PWMO output voltage VPWMO(OFF)
VFBH
–
V
OFF state
VFBH = 14 V
1) Not subject to production test, specified by design
8.2
Digital PWM dimming
The TLD6098-1EP has a dedicated input pin to modulate the average current in a LED string with a digital
pattern.
The device recognizes a digital PWM dimming signal on DC/PWMI pin if:
•
•
•
•
The minimum voltage on DC/PWMI is lower than VDC/PWMI(OFF)
The maximum voltage on DC/PWMI is higher than VDC/PWMI(ON)
The maximum frequency on DC/PWMI is less than 1 kHz
No faults are detected
If a valid pattern is recognized and the VDC/PWMI is higher than VDC/PWMI(ON) the NMOS gate driver is enabled and
the voltage of PWMO pin is VPWMO(ON); else the NMOS gate driver is disabled and the voltage of PWMO pin is
VPWMO(OFF)
Datasheet
26
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
8 Dimming functions
8.2.1
Electrical characteristics
Table 12
Electrical Characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
4.0
Max.
DC/PWMI input voltage VDC/PWMI(ON)
high threshold
–
–
V
V
–
–
PRQ-97
PRQ-98
DC/PWMI input voltage VDC/PWMI(OFF)
–
–
0.8
low threshold
DC/PWMI input current IDC/PWMI
DC/PWMI input current IDC/PWMI
–
–
6
–
–
–
200
1
μA
μA
μs
VDC/PWMI = VIN
VDC/PWMI = 0.8 V
–
PRQ-99
PRQ-100
PRQ-101
DC/PWMI minimum ON tDC/PWMI(ON)
–
time
8.3
Embedded PWM engine
The embedded PWM engine helps to reduce the color shiꢀ when a LED string is dimmed down without using
timer or microcontroller. It generates a pulse width modulation (PWM) adjustable in frequency and duty cycle. A
possible application is the daytime running light dimmed down to position light without using microcontroller
or timer.
The embedded PWM dimming function is enabled if the voltage on DC/PWMI pin is in between DC/PWMI input
voltage 0% dimming VDC/PWM_0% and DC/PWMI input voltage 100% dimming VDC/PWM_100%.
This voltage is translated in the duty cycle of the PWM signal with DC/PWMI duty cycle resolution nDC/PWMI
.
DCPWM
100%
0%
VDC/PWMI(OFF)
VDC/PWMI(0%)
VDC/PWMI(100%)
VDC/PWMI(ON)
VDC/PWMI
Digital dimming
Embedded PWM engine working window
Digital dimming
Duty cycle vs PWMI voltage.vsdx
Figure 14
Relationship between VDC/PWMI and dimming duty cycle
If the embedded PWM dimming function is enabled, the behavior of PWMO pin is the following:
•
The PWMO voltage switches between PWMO output voltage ON state VPWMO(ON) and PWMO output voltage
OFF state VPWMO(OFF)
Datasheet
27
Rev.1.10
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LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
8 Dimming functions
•
•
The PWMO switching frequency depends on the resistor value placed on FPWM/FAULT pin
The PWM duty cycle is linearly adjusted with the voltage on DC/PWMI pin
Any faults disables the embedded PWM engine and forces the voltage on PWMO pin to VPWMO(OFF)
.
The resistor connected on FPWM/FAULT is used to:
•
•
•
Adjust the frequency of the embedded PWM engine
Enable two different reactions on FPWM/FAULT pin during the fault report
Enable or disable the voltage control loop
If the resistor on FPWM/FAULT pin is in FPWM/FAULT high resistor range RFPWM/FAULT(H) the device has the
following behavior:
•
•
•
The frequency of PWM engine is adjusted in fPWMO range
In case a fault is detected, it is reported on FPWM/FAULT pin with proper duty cycle
The voltage loop is disabled and the overvoltage is detected with a comparator (detailed information are
described in Protection and fault management chapter)
While if resistor on FPWM/FAULT pin is in FPWM/FAULT low resistor range RFPWM/FAULT(L)
•
•
•
The frequency of PWM engine is adjusted in fPWMO range
The faults are reported on FPWM/FAULT1,2 pin without a specific indication
Voltage regulation loop is enabled and concurrent to current regulation loop
The frequency of embedded PWM generator can be calculated by:
1
fPWMO_HR
=
=
(3)
(4)
7 . 4 · 10−8 · RFPWM/FAULT
for resistor RFPWM/FAULT(H) range
1
fPWMO_LR
7 . 4 · 10−7 · RFPWM/FAULT
for resistor RFPWM/FAULT(L) range.
Datasheet
28
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
8 Dimming functions
Figure 15
Relationship between RFPWM/FAULT and the frequency of PWMO
The table below summarizes the differences between two resistor sets on FPWM/FAULT pin
Table 13
Resistor differences on fault pin
RFPWM/FAULT(H)
RFPWM/FAULT(L)
Fault report
Each fault reported with a dedicated duty The faults are reported by raising the
cycle on FPWM/FAULT
Disabled
voltage on FPWM/FAULT pin until the faulty
status is removed
Voltage loop
Enabled
Datasheet
29
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
8 Dimming functions
8.3.1
Electrical characteristics
Table 14
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
DC/PWMI input voltage VDC/PWMI(0%)
0% dimming
0.965
1
1.035
V
VIVCC = 5 V
VIVCC = 5 V
PRQ-110
PRQ-111
PRQ-433
DC/PWMI input voltage VDC/PWMI(100%) 3.53
100% dimming
3.6
2.5
3.67
3.5
V
DC/PWMI equivalent
pull down resistor
RDC/PWMI
DCPWMO
1.5
8
MΩ
VDC/PWMI = 4 V
1)
PWMO duty cycle
10
12
%
VPWMI = 1.26 V
VIVCC = 5 V
PRQ-112
FPWM/FAULT reference VFPWM/
0.72
–
0.8
–
0.88
3
V
–
PRQ-114
PRQ-115
voltage
FAULT(REF)
FPWM/FAULT output
current
IFPWM/FAULT
mA
Hz
Hz
bit
kΩ
kΩ
VFPWM/FAULT = 0 V
PWMO dimming
frequency
fPWMO
315
315
–
345
345
10
–
375
375
–
RFPWM/FAULT = 3.92 kΩ PRQ-116
RFPWM/FAULT = 39.2 kΩ PRQ-370
PWMO dimming
frequency
fPWMO
1)
DC/PWMI duty cycle
resolution
nDC/PWMI
PRQ-313
1)
FPWM/FAULT high
range resistor
RFPWM/FAULT(H) 18
90
9
PRQ-590
1)
FPWM/FAULT low range RFPWM/FAULT(L) 1.8
–
PRQ-591
resistor
1) Not subject to production test, specified by design
Datasheet
30
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
9
Protections and fault management
The fault conditions are identified by checking the status of PWMO, IVCC and FPWM/FAULT pins.
The device disables the gate driver and reports fault on FPWM/FAULT pin if the following faults are detected:
•
•
•
•
•
Short to ground
Overvoltage on VFB pin
Overtemperature
Overvoltage on FBH pin
Overcurrent
The faults are reported by raising the voltage on FPWM/FAULT pin to VFPWM/FAULT(FAULT)
.
The output waveform of the fault reporting depends on the resistor connected to FPWM/FAULT pin.
The status of FPWM/FAULT pin can be monitored by a microcontroller. In this case a series resistor (10 kΩ
minimum) has to be used between FPWM/FAULT and the input pin of the microcontroller.
The PWMO gate driver biases the PMOS in OFF state to disconnect the load from the DC-DC output during:
•
•
•
•
Overvoltage on VFB pin,
Overvoltage on FBH pin
Overtemperature
Overcurrent
During a short to ground, the PMOS is biased in OFF state during the tS2G and it is biased in ON state every
tFAULT for a (tSS) to detect if the fault has been removed.
9.1
Electrical characteristics
Table 15
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
1)
FPWM/FAULT output
voltage with fault
VFPWM/
FAULT(FAULT)
4
9
–
–
V
PRQ-117
PRQ-133
1)
Fault period
tFAULT
10
11
ms
1) Not subject to production test, specify by design
9.2
Short to ground
The short to ground detection feature protects the LED driver from an excess of current during a short circuit.
This fault is detected if the voltage of VFB pin is lower than short to ground voltage threshold VFB_S2G for a time
longer than short to ground reaction time tS2G_RT
.
Aꢀer a fault time with short to ground tS2G a soꢀ start routine is triggered. The fault is released if the voltage on
VFB pin is higher than (VFB_S2G+VFB_S2G_HYST) at the end of the soꢀ start.
During soꢀ-start routine, the short to ground detection is disabled and the voltage of FPWM/FAULT pin is kept at
VFPWM/FAULT(REF)
.
The reaction to short to ground is:
1.
2.
3.
The voltage on FPWM/FAULT pin is raised to VFPWM/FAULT(FAULT) for tS2G time
Aꢀer a tS2G time the soꢀ-start routine is performed
At the end of soꢀ-start routine, the check on the voltage VVFB is redone
Datasheet
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Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
If the fault is still present, the procedure is repeated, otherwise the driver restarts.
This routine is valid whatever resistor used on FPWM/FAULT pin.
VVFB
VVFB_S2G_HYS
VVFB_S2G
t
tfault
tfault
tS2G
tfault
tSS
VPWM/FAULT
tSS
tSS
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
t
t
VSWO
Gate driver
disabled
Gate driver
disabled
Gate driver
disabled
Gate driver enabled
Gate driver enabled
S2G - TLD6098-1EP.vsdx
Figure 16
Timing diagram during short to ground detection
A short to ground event simultaneous with an overcurrent event is detected once even the voltage on DC/PWMI
pin is lower than VDC/PWMI(OFF)
.
In all the other cases, the short to ground is not detected when the voltage on DC/PWMI pin is lower than
VDC/PWMI(OFF)
.
9.2.1
Electrical characteristics
Table 16
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
7.2
Max.
8.8
1)
Fault time with short to tS2G
ground
8
ms
PRQ-134
PRQ-121
PRQ-119
PRQ-120
Short to ground
reaction time
tS2G_RT
4
–
20
μs
–
Short to ground
voltage threshold
VFB_S2G
93
–
100
5
107
10
mV
mV
Voltage decreasing
1)
Short to ground
VFB_S2G_HYST
voltage hysteresis
1) Not subject to production test, specified by design
9.3
Output overvoltage and voltage regulation
Based on the resistor used on FPWM/FAULT pin the device implements an overvoltage detection with a
comparator or enabling a voltage regulation by using the internal voltage loop.
Datasheet
32
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
If the resistor connected to FPWM/FAULT pin is in the RFPWM/FAULT(H) range, the overvoltage comparator is
enabled with VFB overvoltage threshold VVFB_OV. The fault is detected when the VFB voltage is above this
threshold.
The device reacts by:
•
•
raising the VFPWM/FAULT to VFPWM/FAULT(FAULT) for a fault time with overvoltage tOVFB
disabling the NMOS gate driver for tFAULT
aꢀer tFAULT the voltage of VFB is rechecked and if it is still higher than (VVFB_OV -VVFB_OV,HYS) the routine is
repeated, else the device restarts with a soꢀ-start routine.
VVFB
VVFB_OV
VVFB_OV_HIS
t
t
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
tOVFB
VSWO
tfault
tfault
Gate driver disabled
tfault
Gate driver enabled
Gate driver disabled
Gate driver enabled
Gate driver enabled
t
OVFB-HR TLD6098-1EP.vsdx
Figure 17
Timing diagram during overvoltage detection
The driver works as a voltage regulator with the voltage loop enabled if the resistor connected to FPWM/FAULT
pin is in the RFPWM/FAULT(L) range.
The voltage loop is taking over the regulation when the voltage on VFB pin goes higher than VFB_VM(ON). At this
time the voltage on FPWM/FAULT pin is raised to VFPWM/FAULT(FAULT)
.
On the other side, the device reports the voltage loop is ineffective when the voltage on VFB pin goes below
VFB_VM(OFF) by lowering the voltage on FPWM/FAULT pin to VFPWM/FAULT(REF)
The fault is detected even the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF)
.
.
Datasheet
33
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
VVFB
VVFB_REF
VVFB_VM(ON)
VVFB_VM(OFF)
t
t
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
VSWO
Gate driver enabled
t
OVFB-LR-TLD6098-1EP.vsdx
Figure 18
Timing diagram in voltage regulation
9.3.1
Electrical characteristics
Table 17
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
VFB overvoltage
threshold
VVFB_OV
VVFB_OV_HYS
IVFB
1.568 1.6
1.632
V
Voltage increasing
PRQ-118
PRQ-323
1)
VFB overvoltage
hysteresis
180
200
220
mV
VFB input current
-1
-0.1
1.5
1
μA
V
VFB = 1.6 V
PRQ-122
PRQ-376
VFB Voltage mode ON VVFB_VM(ON)
1.45
1.55
Voltage increasing
threshold
VFB voltage mode OFF VVFB_VM(OFF)
threshold
1.3
3.6
1.35
4
1.4
4.4
V
Voltage decreasing
PRQ-377
PRQ-135
1)
Fault time with
overvoltage
tOVFB
ms
1) Not subject to production test, specified by design
9.4
Overvoltage on FBH pin
The driver has a protection feature to prevent an excess voltage on FBH pin. The report of this fault depends on
the resistor connected to FPWM/FAULT pin.
Datasheet
34
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
The device recognizes an overvoltage on FBH pin fault if the VFBH is higher than FBH overvoltage high threshold
VFBH(H) and the fault is released when it is below the FBH overvoltage low threshold VFBH(L)
With a resistor on FPWM/FAULT pin in RFPWM/FAULT(H) range the device reacts by:
.
•
•
•
Disabling the NMOS gate driver
Raising the voltage of FPWM/FAULT pin to VFPWM/FAULT(FAULT) for tFBH time
Aꢀer tFAULT period, the device checks if VFBH is still higher than VFBH(L)
VVFBH
VVFBH(H)
VVFBH(L)
t
tfault
tFBH
tfault
tfault
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
t
t
VSWO
Gate driver enabled
Gate driver disabled
Gate driver enabled
OV_FBH_HRES_TLD6098-1EP.vsdx
Figure 19
Timing diagram during overvoltage on FBH detection with RFPWM/FAULT(H) used on
FPWM/FAULT pin
With a resistor on FPWM/FAULT pin in RFPWM/FAULT(L) range the device reacts to the fault by:
•
•
•
Disabling the NMOS gate driver
Raising the voltage of FPWM/FAULT pin to VFPWM/FAULT(FAULT)
Aꢀer tFAULT period, the device checks if the voltage on FBH pin is still higher than VFBH(L)
Datasheet
35
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
VVFBH
VVFBH(H)
VVFBH(L)
t
tFAULT
tFAULT
tFAULT
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
t
t
VSWO
Gate driver enabled
Gate driver disabled
Gate driver enabled
OV_FBH_LRES_TLD6098-1EP.vsdx
Figure 20
Timing diagram during overvoltage on FBH detection with RFPWM/FAULT(L) used on
FPWM/FAULT pin
When the fault disappears the device restarts with soꢀ-start routine and lowers the voltage of FPWM/FAULT pin
to VFPWM/FAULT(REF)
.
If the fault appears during the soꢀ-start routine, it interrupts the soꢀ-start for a tFAULT time and then the routine
restarts.
The fault is detected even when the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF)
.
9.4.1
Electrical characteristics
Table 18
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
70
Max.
75
FBH overvoltage upper VFBH(H)
threshold
–
V
VFBH increasing
PRQ-327
PRQ-328
PRQ-329
FBH overvoltage lower VFBH(L)
threshold
65
–
6
–
V
VFBH decreasing
1)
Fault time FBH
tFBH
5.4
6.6
ms
1) Not subject to production test, specified by design
Datasheet
36
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
9.5
Output overcurrent
An output overcurrent event could damage the load if the current exceed the load specification. The output
overcurrent detection increases the system reliability by reducing the load average current.
The output overcurrent is detected when voltage across FBH and FBL is higher than overcurrent detection
threshold VOC_200%
.
The device reacts in overcurrent detection time tOC_200% by rising the voltage of PWMO pin to VPWMO(OFF) and
disabling the NMOS gate driver.
The protection is released when the voltage across VFBH - VFBL drops below VOC_200% - VOC_HYS. At this time the
NMOS gate driver is enabled again and the voltage of PWMO pin evolves as demanded by the dimming features.
A continuously re-triggering of the protection could cause an overheating of the PMOS. Then a timer records
the period in which the device is in over current state. The fault reporting depends on the resistor used on
FPWM/FAULT pin.
With a resistor on FPWM/FAULT pin in RFPWM/FAULT(H) range, the device reacts to an overcurrent by:
•
•
•
•
•
Entering into the overcurrent state
Disabling the NMOS gate driver and raises the voltage on PWMO pin to VPWMO(OFF)
As soon as (VFBH - VFBL) < (VOC_200% - VOC_HYS) the NMOS gate driver is enabled again
PWMO pin is again controlled by the dimming feature
Exiting from the overcurrent state
When the cumulative time in which the device is in overcurrent state reaches the overcurrent detection tOC in a
time window of 8*tFAULT the device:
•
Raises the voltage of FPWM/FAULT pin at VFPWM/FAULT(FAULT) for the overcurrent fault time tFBH-FBL and then
releases the voltage of FPWM/FAULT pin to VFPWM/FAULT(REF) for (tFAULT - tFBH-FBL
)
•
Repeats this sequence 8 times
8*tFAULT time window
VFBH-FBL
VOC_200%
VOC_HYS
VREF
t
8*tFAULT
+
tFAULT
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
tFBH-FBL
Cumulative time > tOC
t
t
t
VPWMO
VPWMO(OFF)
VPWMO(ON)
VSWO
Gate driver enebled
Gate driver disabled
Gate driver enabled
Overcurrent HRES with PMOS.vsdx
Figure 21
System behavior with RFPWM/FAULT(H) during overcurrent detection with PMOS as
dimming/protection element
Datasheet
37
Rev.1.10
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LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
V
FBH-VFBL
VOC_200%
VREF
t
t
VOUT
VIN
8*tFAULT
tFAULT
tOC tFBH-FBL
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
t
t
VSWO
Gate driver enabled
Gate driver disabled
Gate driver enabled
Overcurrent HRES without PMOS.vsdx
Figure 22
System behavior with RFPWM/FAULT(H) during overcurrent detection without PMOS as
dimming/protection element
With a resistor on FPWM/FAULT pin in RFPWM/FAULT(L) range, the device reacts to an overcurrent by:
•
•
•
•
•
Entering into the overcurrent state
Disabling the NMOS gate driver and raises the voltage on PWMO pin to VPWMO(OFF)
As soon as (VFBH - VFBL) < (VOC_200% - VOC_HYS) the NMOS gate driver is enabled again
PWMO pin is again controlled by the dimming feature
Exiting from the overcurrent state
When the cumulative time in which the device is in overcurrent state reaches tOC in a time window of 8*tFAULT
the device:
•
Raises the voltage of FPWM/FAULT pin at VFPWM/FAULT(FAULT) for a time 8*tFAULT and then releases it to VFPWM/
FAULT(REF)
Datasheet
38
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
8*tFAULT time window
VFBH-FBL
VOC_200%
VOC_HYS
VREF
t
8*tFAULT
+
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
Cumulative time > tOC
t
t
t
VPWMO
VPWMO(OFF)
VPWMO(ON)
VSWO
Gate driver enebled
Gate driver disabled
Gate driver enabled
Overcurrent LRES with PMOS-TLD6098-1EP.vsdx
Figure 23
System behavior with RFPWM/FAULT(L) during overcurrent detection with PMOS as
dimming/protection element
V
FBH-VFBL
VOC_200%
VREF
t
t
VOUT
VIN
8*tFAULT
VFPWM/FAULT
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
tOC
t
t
VSWO
Gate driver enabled
Gate driver disabled
Gate driver enabled
Overcurrent LRES without PMOS-TLD6098-EP.vsdx
Figure 24
System behavior RFPWM/FAULT(L) during overcurrent detection without PMOS as
dimming/protection element
Datasheet
39
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
During the overcurrent detection, the tS2G_RT filter time is bypassed. In case of simultaneous short to ground
detection and overcurrent detection, the device reacts to short to ground failure, cumulating the time in which
the device is in overcurrent state. When the cumulated time reaches the tOC, in a time window of 8*tFAULT, the
overcurrent is detected.
The fault is detected even the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF)
.
9.5.1
Electrical characteristics
Table 19
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
280
Max.
Overcurrent detection VOC_200%
threshold
300
–
mV
mV
ms
VFBH- VFBL increasing
PRQ-531
PRQ-532
PRQ-533
1)
Overcurrent detection VOC_HYS
hysteresis
15
–
4
35
1)
Overcurrent detection tOC
3.6
4.4
time
1)
1)
Overcurrent fault time tFBH-FBL
1.8
–
2
–
2.2
2
ms
μs
PRQ-555
PRQ-538
Reaction time during
overcurrent detection
tOC_200%
1) Not subject to production test, specified by design
9.6
Overtemperature
Thermal shutdown is an internal feature designed to prevent the device destruction and it is not intended for
continuous use in normal operation.
If the junction temperature reaches the overtemperature shutdown TJ(SD), the integrated thermal shutdown
function turns off the gate drivers and internal linear voltage regulator.
The junction temperature is checked each tFAULT period, and when it is cooled down to (TJ(SD)-TJ(SD_HYS)) the
device will automatically restart with a soꢀ-start.
Datasheet
40
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
9 Protections and fault management
TJ
TJ(SD)
TJ(SD_HYS)
t
VFPWM/FAULT
tfault
tfault
tfault
tfault
VFPWM/FAULT(FAULT)
VFPWM/FAULT(REF)
t
VIVCC
VIVCC_TH_I
t
VSWO
Gate driver
enabled
Gate driver enabled
Gate driver disabled
Gate driver enabled
Gate driver disabled
t
Overtemperatue-TLD6098-1EP.vsdx
Figure 25
Timing diagram during overtemperature protection
9.6.1
Electrical characteristics
Table 20
Electrical characteristics
VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin;
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
160
Max.
190
1)
Overtemperature
shutdown
TJ(SD)
175
°C
PRQ-336
PRQ-337
1)
Overtemperature
TJ(SD_HYS)
–
10
–
°C
shutdown hysteresis
1) Not subject to production test, specified by design
Datasheet
41
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
10 Application information
10
Application information
Note:
The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device
VS
L1
D1
RFB
MP
CBO
LED1
LED2
IVCC
IN
MN
SWO
IVCC
CIVCC
LED3
LED4
LED5
LED6
LED7
LED8
SWCS
FPWM/FAULT
RSWCS
RFAULT
FBH
FBL
FREQ/SYNC/SPREAD
RFREQ
IVCC
RSETH
RVFBH
SET
VFB
IVCC
RSETL
RVFBL
RDCH
DC/PWMI
COMP
PWMO
GND
RDCL
CCOMP1
RCOMP
CCOMP2
TLD6098-1EP
B2G-1ch.vsdx
Figure 26
Boost to ground application schematic
Datasheet
42
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
10 Application information
LED4
LED3
LED2
LED1
CBO2
VS
L
D
RFB
MP
CBO1
IVCC
CIVCC
IN
MN
SWO
IVCC
SWCS
FPWM/FAULT
RSWCS
RFAULT
FREQ/SYNC/SPREAD
RFREQ
FBH
FBL
IVCC
RSETH
RVFBH
SET
IVCC
RDCH
RSETL
VFB
RVFBL
DC/PWMI
COMP
RDCL
PWMO
GND
CCOMP1
RCOMP
CCOMP2
TLD6098-1EP
B2B-1ch.vsdx
Figure 27
Boost to battery application schematic
Datasheet
43
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
10 Application information
VS
CSEPIC
L1
D
RFB
MP
LED1
LED2
IVCC
IN
L2
CBO
MN
SWO
IVCC
CIVCC
LED3
LED4
LED5
LED6
LED7
LED8
SWCS
FPWM/FAULT
RFAULT
RSWCS
FBH
FREQ/SYNC/SPREAD
RFREQ
IVCC
FBL
RSETH
RVFBH
SET
VFB
IVCC
RSETL
RVFBL
RDCH
DC/PWMI
COMP
PWMO
GND
RDCL
CCOMP1
RCOMP
CCOMP2
TLD6098-1EP
SEPIC-1ch.vsdx
Figure 28
SEPIC application schematic
VS
C1
L1
L2
CBO
ROVH
LED1
LED2
IVCC
CIVCC
D1
IN
MN
SWO
IVCC
IVCC
Q3
LED3
LED4
LED5
LED6
LED7
LED8
SWCS
IVCC
RCML
RCMR
FPWM/FAULT
RSWCS
RFAULT
Q1
Q2
MP
VFB
ROVL
FREQ/SYNC/SPREAD
RPWMO1
RFREQ
IVCC
RSETH
RPWMO2
PWMO
FBL
MPWM
SET
IVCC
RDCH
RSETL
RFB
FBH
GND
DC/PWMI
COMP
RDCL
CCOMP1
RCOMP
CCOMP2
TLD6098-1EP
Cuk-1ch.vsdx
Figure 29
Cuk application schematic
Datasheet
44
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
10 Application information
VS
L1
D1
CBO
IVCC
CIVCC
IN
SWO
M1
IVCC
RLOAD
SWCS
FPWM/FAULT
RSWCS
RFAULT
RVFBH
FREQ/SYNC/SPREAD
RFREQ
VFB
IVCC
RSET
RVFBL
PWMO
SET
IVCC
FBH
FBL
RENABLE
DC/PWMI
COMP
GND
CCOMP1
RCOMP
CCOMP2
TLD6098-1EP
B2G_CV-1ch.vsdx
Figure 30
Constant output voltage boost converter application schematic
Datasheet
45
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
11 Package
11
Package
Figure 31
Package dimensions PG-TSDSO-14
Note:
Green product (RoHS compliant) To meet the world-wide customer requirements for
environmentally friendly products and to be compliant with government regulations the device is
available as a green product. Green products are RoHS-Compliant (i.e. Pb-free finish on leads and
suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages https://www.infineon.com/packages
Datasheet
46
Rev.1.10
2021-09-30
LITIX™ Power TLD6098-1EP
Multitopology single-channel DC-DC controller
12 Revision history
12
Revision history
Document Date of
Description of changes
version
release
Rev.1.10
2021-09-30
•
•
Editorial changes
New application schematics
Rev.1.00
2021-04-16 Initial Datasheet
Datasheet
47
Rev.1.10
2021-09-30
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2021-09-30
Published by
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相关型号：
TLD6098-2ES
LITIX™ Power TLD6098-2ES is a dual-channel DC-DC boost controller with spread spectrum frequency modulation and with built-in diagnosis and protection features specially designed for LED drivers.
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