TLE4473GV55-2 [INFINEON]
Dual Low Drop Voltage Regulator; 双路低压差稳压器型号: | TLE4473GV55-2 |
厂家: | Infineon |
描述: | Dual Low Drop Voltage Regulator |
文件: | 总16页 (文件大小:681K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual Low Drop Voltage Regulator
TLE 4473 GV55-2
Features
• Stand-by output 190 mA; 5 V ± 2%
• Main output: 300 mA, 5 V
tracked to the stand-by output
• Low quiescent current consumption
• Disable function separately for both outputs
• Wide operation range: up to 42 V
• Very low dropout voltage
P-DSO-12
• 2 independent reset circuits
• Watchdog
• Output protected against short circuit
• Wide temperature range: -40 °C to 150 °C
• Overtemperature protection
• Overload protection
Functional Description
The TLE 4473 is a monolithic integrated voltage regulator with two very low drop outputs,
a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum
of 190 mA. The stand-by regulator transforms an input voltage VI in the range of 5.6 V ≤
VI ≤ 42 V to VQ2 = 5.0 V (±2%) output voltage. The main output is tracked to the stand by
output voltage and provides also 5 V. Versions of the device with 5 V/3.3 V and 5 V/2.6 V
are available, please refer to the data sheet TLE 4473 G V53/TLE 4473 G V52. Two
Inhibit Pins allow to use either both output voltages or to disable only Q1 or to switch off
both outputs, the latter causing the current consumption to drop below 1 µA. The
TLE 4473 is designed to supply microprocessor systems and sensors under the severe
conditions of automotive applications and is therefore equipped with additional
protection functions against overload, short circuit and overtemperature. The device
operates in the wide junction temperature range of -40 °C to 150 °C.
Type
Ordering Code
Package
Marking
TLE 4473 GV55-2
on request
P-DSO-12-4
TLE4473GV55-2
Target Data Sheet
1
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
The device features a reset with adjustable power on delay for each of the outputs. In
addition the output for the microcontroller supply comes up with a watchdog in order to
supervise a connected microcontroller
Reset and Watchdog Behavior
The reset output RO2 is in high-state if the voltage on the delay capacitor CD2 is greater
or equal VDU2. The delay capacitor CD2 is charged with the current IDC2 for output
voltages greater than the reset threshold VRT2. If the output voltage gets lower than VRT2
(‘reset condition’) a fast discharge of the delay capacitor CD2 sets in and as soon as VD2
gets lower than VDL2 the reset output RO2 is set to low-level. The time for the delay
capacitor charge is the reset delay time. For the power-on case the charging process of
CD2 starts from 0 V, which leads to the equation:
C
D2 × VDU2
IDC2
tD, on = ----------------------------
(1)
for the power-on reset delay time.
When the voltage on the delay capacitor has reached VDU2 and reset was set to high, the
watchdog circuit is enabled and discharges CD2 with the constant current IDD2
.
If there is no rising edge observed at the watchdog input, CD2 will be discharge down to
VDL2. Then reset output RO2 will be set to low and CD2 will be charged again with the
current IDC2 until VD2 reaches VDU2 and reset will be set high again.
If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period CD2 is charged again and the reset output stays high. After VD2 has reached VDU2
,
the periodical cycle starts again.
The watchdog timing is shown in Figure 1. The maximum duration between two
watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher
capacitances on pin D2 result in longer watchdog trigger times:
TWI,tr
= 0.34 ms/nF × CD2
(2)
max
If the output voltage Q1 decreases below VRT1 (typ. 4.65 V), the external capacitor CD1
is discharged by the reset generator of the main output. If the voltage on this capacitor
drops below VDL1, a reset signal is generated on pin 2 (RO1). If the output voltage rises
above the reset threshold, CD1 will be charged with the constant current IDC1. After the
power-on-reset time the voltage on the capacitor reaches VDU1 and the reset output will
be set high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of CD1 using the above given equation (1) analogous for
Q1.
Target Data Sheet
2
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
VW
Ι
t
t
t
t
t
V
Ι
VQ
TWD, p
VD2
TWI, tr
VDU2
VDL2
tWD, L
VRO2
(VDU2 -VDL2
)
(VDU2 -VDL2 ) (Ι DC2
+
Ι DD2
)
(VDU2 -VDL2 )
TWI, tr
=
CD2; TWD, p
=
CD2
;
tWD, L
=
CD2
Ι DD2
Ι DC2
x
Ι DD2
Ι DC2
AED03099_4473
Figure 1
Watchdog Timing Schedule
Target Data Sheet
3
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
TLE 4473 GV55-2
Q2
4
7
9
I
µC
V
Bat CI
Supply
10
µF
100 nF
Overtemperature
Shutdown
Current and
Saturation
Control,
4.7 kΩ
Bandgap
Overcurrent
Protection
Reset
RO2
WI
3
µC
Reference
Generator
Reset
INH2
Ignition
Inhibit
1
Watchdog
(from µC)
Watchdog
D2 11
100 nF
Q1
6
e.g. Sensor
Supply
10
µF
Current and
Saturation
Control,
4.7 kΩ
e.g. Sensor
Reset
(to µC)
Overcurrent
Reset
RO1 2
Generator
Protection
8
INH1
µC
Inhibit
D1 10
100 nF
12
GND
TLE4473G V55-2_BLO CKDIAG RAM.VSD
Figure 2
Block Diagram with Typical External Components
Target Data Sheet
4
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Application Information
The output voltage is divided by a voltage divider and compared to an internal reference
voltage. A regulation loop controls the Q2 output in order to achieve a stable output
voltage at the Q2 pin. A second regulation loop controls the Q1 output. The reference
voltage for the Q1 is the regulated Q2 potential (tracking regulator).
Figure 2 includes the components needed for a typical application. Maintaining the
stability of the regulation loops requires a capacitor of 10 µF both outputs. A maximum
ESR of 5 Ω is permissible for the Q2 output, while the Q1 output requires a capacitor with
a maximum ESR of 3 Ω. For both output blocking capacitors it is recommended to use
tantalum types in order to stay in the permissible ESR range over the full operating
temperature range.
At the input of the regulator a capacitor is necessary for compensating line influences. A
minimum of 100 nF (ceramic capacitor) is recommended. In addition for compensation
of long input lines of several meters an electrolytic input capacitor of 47 µF … 220 µF
should be placed at the input.
TLE 4473 GV55-2
(P-DSO-12)
WI
RO1
RO2
Q2
1
2
3
4
5
6
12
11
10
9
GND
D2
D1
INH2
INH1
I
N.C.
Q1
8
7
Figure 3
Pin Configuration (top view)
Target Data Sheet
5
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 1
Pin Definitions and Functions
Pin No. Symbol Function
1
2
WI
Watchdog input; input for watchdog pulses, positive edge
triggered.
RO1
Reset and watchdog output for Q1; open collector output.
Connect to pull-up resistor.
3
4
RO2
Q2
Reset output 2; open collector output. Connect to pull-up resistor.
Stand-by regulator output voltage; block to GND with a capacitor
C
Q2 ≥ 10 µF, ESR < 5 Ω at 10 kHz.
5
6
N.C.
Q1
Internally not connected; connect to GND.
Main regulator output voltage; output voltage tracked to Q2
voltage; block to GND with a capacitor CQ1 ≥ 10 µF, ESR < 3 Ω at
10 kHz
7
I
Input voltage; block to ground directly at the IC with a ceramic
capacitor.
8
9
INH1
INH2
Inhibit input 1; low level disables Q1, integrated pull-down resistor.
Inhibit input 2; low level at INH2 and INH1 disables Q2 and Q1,
integrated pull-down resistor.
10
11
D1
Reset Delay 1; connect to ground via a capacitor to set reset delay
for Q1.
D2
Reset Delay 2; connect to ground via a capacitor to set reset delay
and watchdog timing for Q2.
12
GND
Ground; connect to heatslug.
Heatslug
Interconnect heatsink area and GND.
Target Data Sheet
6
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 2
Absolute Maximum Ratings
-40 °C < Tj < 150 °C
Parameter
Symbol
Limit Values Unit
Remarks
Min.
Max.
Input I
Voltage
VI
II
-42
–
45
–
V
–
Current
mA
Internally limited
Stand-by Output Q2
Voltage
VQ2
IQ2
-0.3
–
18
–
V
–
Current
mA
Internally limited
Main Output Q1
Voltage
VQ1
IQ1
-0.3
–
18
–
V
–
Current
mA
Internally limited
Inhibit Input INH1
Voltage
VINH1
IINH1
-42
-2
45
2
V
–
–
Current
mA
Inhibit Input INH2
Voltage
VINH2
IINH2
-42
-2
45
2
V
–
–
Current
mA
Reset Output RO1
Voltage
VRO1
IRO1
-0.3
–
18
–
V
–
Current
mA
Internally limited
Reset Output RO2
Voltage
VRO2
IRO2
-0.3
–
18
–
V
–
Current
mA
Internally limited
Reset Delay D1
Voltage
VD1
ID1
-0.3
-5
7
5
V
–
–
Current
mA
Reset Delay D2
Voltage
VD
ID
-0.3
-5
7
5
V
–
–
Current
mA
Target Data Sheet
7
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 2
Absolute Maximum Ratings (cont’d)
-40 °C < Tj < 150 °C
Parameter
Symbol
Limit Values Unit
Remarks
Min.
Max.
Watchdog Input WI
Voltage
VRADJ
IRADJ
-0.3
-5
7
5
V
–
–
Current
mA
Temperatures
Junction temperature
Storage temperature
Tj
-50
-50
150
150
°C
°C
–
–
Tstg
Table 3
Operating Range
Parameter
Symbol
Limit Values Unit
Remarks
Min.
Max.
42
Input voltage
VI
Tj
5.6
-40
V
–
–
Junction temperature
150
°C
Thermal Resistances P-DSO-12-4
Junction pin
Rthj-pin
–
–
4
K/W
K/W
–
Junction ambient
Rthj-a
Rthj-a
Rthj-a
Rthj-a
115
PCB Heat Sink
Area 0 mm2 1)
Junction ambient
Junction ambient
Junction ambient
–
–
–
100
60
K/W
K/W
K/W
PCB Heat Sink
Area 100 mm2 1)
PCB Heat Sink
Area 300 mm2
1)
48
PCB Heat Sink
Area 600 mm2 1)
1) Package mounted on PCB 80 × 80 × 1.5 mm3; 35µ Cu; 5µ Sn; zero airflow.
Note: In the operating range the functions given in the circuit description are fulfilled.
Integrated protection functions are designed to prevent IC destruction under fault
conditions. Protection functions are not designed for continuous repetitive
operation.
Target Data Sheet
8
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Stand-by Regulator
Output Q2
Output voltage
VQ2
IQ2
4.90 5.0
5.10
550
600
V
1 mA < IQ2 < 190 mA;
6 V < VI < 28 V
Output current
limitation
200
–
300
200
mA VQ2 = 4.5 V
Output drop voltage; VDRQ2
DRQ1 = VI1 - VQ1
mV IQ2 = 100 mA1)
V
Load regulation
Line regulation
∆VQ2,Lo
∆VQ2,Li
–
–
15
5
50
20
mV 1 mA < IQ2 < 190 mA
mV IQ2 = 1 mA;
6 V < VI < 28 V
PowerSupplyRipple PSRR
Rejection
–
65
–
dB fr = 100 Hz;
Vr = 1 Vpp
Current Consumption
Quiescent current;
stand-by
Iq = II - IQ2
Iq
–
–
–
–
–
–
170
–
220
245
280
5
µA IQ2 = 500 µA; Tj = 25 °C;
V
INH1 < VINH1 OFF (Q1 off)
µA IQ2 = 500 µA; Tj = 85 °C;
INH1 < VINH1 OFF (Q1 off)
µA IQ2 = 500 µA;
V
–
VINH1 < VINH1 OFF (Q1 off)
4.5
0.1
0.1
mA IQ2 = 100 mA;
VINH1 < VINH1 OFF (Q1 off)
Quiescent current;
inhibited
Iq
1
µA
µA
V
INH1 = VINH2 = 0 V;
Tj < 85 °C
VINH1 = VINH2 = 0 V
15
Target Data Sheet
9
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics (cont’d)
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Inhibit Input INH2
Turn-on Voltage
Turn-off Voltage
H-input current
VINH2 ON
–
–
2.3
–
V
VQ2 on
VQ2 off
VINH2 OFF 0.65
IINH2 ON -1
–
V
3.2
6
µA
V
INH2 = 5.0 V (see
Page 13)
µA 0 V < VINH2 < 0.8 V
L-input current
IINH2 OFF -1
0.1
1
Watchdog and Reset Timing D2
Charge current
IDC2
IDD2
VDU2
6.5
2.0
1.5
9.0
3.5
12.5 µA VD2 = 1 V
5.0 µA VD2 = 1 V
Discharge current
Upper timing
threshold
1.85 2.4
V
–
Lower timing
threshold
VDL2
0.3
0.4
0.5
V
–
Saturation Voltage
VD2,SAT
TWI,tr
–
–
100
51
mV VQ2 < VRT2
Watchdog trigger
time
34
42
ms CD2 = 100 nF
Reset delay time
TRD2
15
–
20
–
25
ms CD2 = 100 nF
Reset reaction time Trr
5.0
µs
CD2 = 100 nF
Reset Output RO2
Reset switching
threshold
VRT2
4.5
VRT2/VQ2 90
VR2HEAD 200
4.65 4.8
V
–
–
93
96
%
Reset threshold
headroom
350
500
mV VQ2 - VRT2
Reset output
sink current
IRO2
1.6
–
–
–
mA VQ2 = 5 V, VD2 = 0 V;
VRO2 = 0.3 V
Reset output
low voltage
VRO2L
0.15 0.3
V
V
V
Q2 ≥ 1 V;
IRO2 = 1 mA
Reset high voltage VRO2H
4.5
–
–
RRO2,ext = 4.7 kΩ
Target Data Sheet
10
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics (cont’d)
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Main (Tracked) Regulator
Output Q1
Output voltage
VQ1
4.875 5.0
5.125 V
1 mA < IQ1 < 200 mA;
6 V < VI < 28 V
Output voltage
tracking accuracy
∆VQ =
VQ2 - VQ1
-25
-25
350
–
5
25
25
–
mV 1 mA < IQ1 < 200 mA;
6 V < VI < 28 V
Output voltage
tracking accuracy
∆VQ =
VQ2 - VQ1
5
mV 1 mA < IQ1 < 300 mA;
8 V < VI < 28 V
Output current
limitation
IQ1
500
300
mA VQ1 = 4.5 V
Output drop voltage VDRQ1
DRQ1 = VI - VQ1
600
mV IQ1 = 200 mA1)
V
Load regulation
Line regulation
∆VQ1,Lo
∆VQ1,Li
–
–
5
5
50
25
mV 5 mA < IQ1 < 300 mA
mV IQ1 = 5 mA;
6 V < VI < 28 V
PowerSupplyRipple PSRR
Rejection
–
65
–
dB fr = 100 Hz;
Vr = 1 Vpp
Current Consumption
Quiescent current;
Iq = II - IQ1 - IQ2
Iq
–
–
10
20
mA IQ1 = 300 mA;
IQ2 = 500 µA;
VQ1 and VQ2 on
Quiescent current;
Iq = II - IQ1 - IQ2
Iq
250
500
µA IQ2 = IQ1 = 500 µA;
VQ1 and VQ2 on
Inhibit Input INH1
Turn-on Voltage
Turn-off Voltage
H-input current
VINH1 ON
–
–
2.3
–
V
V
VQ1 on
VQ1 off
VINH1 OFF 0.7
IINH1 ON -1
–
3.5
5
µA 3.0 V < VINH1 < 5 V;
(see Page 14)
L-input current
IINH1 OFF -1
0.1
11
1
µA 0 V < VINH1 < 0.8 V
Target Data Sheet
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics (cont’d)
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
Min. Typ. Max.
Reset Timing D1
Charge current
IDC1
4.0
1.6
8.0
1.8
12.0 µA VD1 = 1 V
Upper timing
threshold
VDU1
2.2
V
–
Lower timing
threshold
VDL2
0.3
0.4
0.6
V
–
Saturation Voltage
Reset delay time
VD1,SAT
TRD1
–
–
100
30
mV VQ1 < VRT1
14
–
20
–
ms CD1 = 100 nF
Reset reaction time Trr
10
µs
CD1 = 100 nF
Reset Output RO1
Reset switching
threshold
VRT1
4.5
VRT1/VQ1 90
VR1HEAD 200
4.65 4.8
V
–
–
93
96
%
Reset threshold
headroom
350
500
mV VQ1 - VRT1
Reset output
sink current
IRO1
1.6
–
–
–
mA VQ1 = 5.0 V; VQ2 = 5.0 V;
VD1 = 0 V; VRO1 = 0.3 V
Reset output
low voltage
VRO1L
VRO1H
0.15 0.3
V
V
Q1 ≥ 1 V
RO1 = 1 mA
RRO1,ext = 4.7 kΩ
I
Reset output high
voltage
4.5
–
–
V
1) Drop voltage = VI - VQ (measured when the output voltage has dropped 100 mV from the nominal value
obtained at 13.5 V input)
Target Data Sheet
12
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Typical Performance Characteristics
Output Voltage VQ2 versus
Input Voltage VI
Output Voltage VQ2 versus
Junction Temperature TJ
A
E
D
0
3
3
5
3
. V
S
D
A
E
D
0
3
3
5
2
. V
S
D
8
5 . 1 5
V
V
V
V
R
V
=
=
5 0
5
Ω
Q
2
Q
2
L
o
a
d
2
7
6
5
4
3
2
1
0
V
I N
H
5 . 1 0
5 . 0 5
5 . 0 0
4 . 9 5
4 . 9 0
0
1
2
3
4
5
6
V
8
- 4 0
0
4 0
8 0
° C
1 6 0
V
T
I
Reset Thresholds VRT1, VRT2 versus
Junction Temperature TJ
INH2 Input Current versus
Inhibit Voltage
A
E
D
0
3
3
5
4
. V
S
D
A
E
D
0
3
3
5
1
. V
S
D
4 . 8 0
V
8
µ
A
7
I I N
H
2
4 . 7 5
4 . 7 0
4 . 6 5
4 . 6 0
4 . 5 5
6
5
4
3
2
1
0
- 4 0
0
4 0
8 0
° C
1 6 0
0
1
2
3
4
5
6
V
8
T
V
I N
H
2
Target Data Sheet
13
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
INH1 Input Current versus
Inhibit Voltage
A
E
D
0
3
3
5
0
. V
S
D
8
µ
A
7
I I N
H
1
6
5
4
3
2
1
0
0
1
2
3
4
5
6
V
8
V
I N
H
1
Target Data Sheet
14
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Package Outline
1)
1)
±0.1
±0.1
6.4
7.5
A
=
B
(Mold)
1
5
±0.3
10.3
0.1
0.25 B
5 x
1
12x
0.25
0.4 +0.13
M
C A B
±0.1
5.1
(Metal)
7
12
7
12
Index Marking
1
7.8
6
±0.1
6
1
Heatslug
(Heatslug)
GPS09349
1) Does not include plastic or metal protrusion of 0.15 max. per side
8.1
0.65 MAX.
1
Footprint
hlg09455
Figure 4
P-DSO-12-4 (Plastic Dual Small Outline)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Target Data Sheet
15
Rev. 0.2, 2005-07-26
Edition 2005-07-26
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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