TLE6288R [INFINEON]
Smart 6 Channel Peak&Hold Switch; 聪明的6通道峰值和锁定开关
| 型号： | TLE6288R |
| 厂家： | 
Infineon |
| 描述： | Smart 6 Channel Peak&Hold Switch |
| 文件： | 总23页 (文件大小：1257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r e l i m i n a r y D a t a s h e e t T L E 6 2 8 8 R
TLE 6288 R : Smart 6 Channel Peak&Hold Switch
Features
Product Summary
•
•
•
3 Channel high side with adjustable P&H current control
3 Channel high / low side configurable
Supply voltage
On resistance
Lowside clamping voltage Vcll (max) +55
Highside clamping voltage Vclh (max) -19
Peak current range
Hold current range
Peak time range
VS
4.5 – 5.5
V
Ω
V
V
A
A
Protection
Over Current (current limitation)
Overtemperature
RON 1-6 0.15
Overvoltage (active clamping)
•
•
Diagnosis
Ipk
Ihd
Ip
1.2 - 3.6
0.7 - 2
Over Current
Over Temperature
Open Load (Off-State)
0
- 3.6 ms
Short to Ground (Off-state, lowside configura-
tion)
Fixed off time range
Ifo
100 – 400 µs
Short to Vbb (Off-state, highside configura-
tion)
Interface and Control
16 Bit Serial Peripheral Interface (2bit/CH)
Device programming via SPI
Separate diagnosis output for each CH ( DIAG1 – 6)
General Fault Flag + Overtemperature Flag
Direct parallel control of all channels
P-DSO 36-12
General enable signal to control all channels simultaneously
Ordering Code:
• Low Quiescent Current
• Compatible with 3.3V and 5V Microcontrollers
• Electostatic discharge (ESD) protection of all pins
Application
• Solenoids, Relays and Resistive Loads
• Fast protected Highside Switching (PWM up to >10kHz)
• Peak and Hold Loads (valves, coils)
General description
Fault Reset VDO VCC
The TLE6288 R is a 6-channel (150mΩ)
Smart Multichannel Switch in SPT4 Tech-
CLKProg
DOUT 1
SOUT 1
Channel 1-3
nology. The IC has embedded protection,
IN 1
Highside 150 m
diagnosis and configurable functions.
Logic
DOUT 2
SOUT 2
Channel 1-3 are highside channels with
IN 6
Peak&Hold
Protection
Diagnosis
integrated charge pump and can be pro-
Configuration
DOUT 3 / VB
SOUT 3
grammed individually to do autonomous
DIAG 1
peak and hold current regulation with
PWM. Channel 4-6 (also with integrated
Current
DIAG 5
DOUT 4
SOUT 4
Regulation
charge pump) can be configured to work
as highside Switch or lowside Switch. This
IC can be used to drive standard automo-
tive loads in highside or lowside applica-
tions with switching frequencies up to
10kHz. In addition the TLE6288R can be
used to drive autonomously up to 3 induc-
tive Peak&Hold (valves, coils) loads with
programmable peak and hold current val-
ues.
DIAG 6
Channel 4 -6
Highside/ Lowside
150 mΩ
Overtemp.
DOUT 5
SOUT 5
SCLK
CS
SI
SO
Protection
Diagnosis
Charge-
pump
SPI
DOUT 6
SOUT 6
GND
FSIN
VCP
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1. Block Diagram
Reset
VDO
VCC
VB
DOUT 3 / VB
Vcc
.
Fault
Channel 3
Highside 300 m
Peak&Hold
Ω
Ω
Ω
.
.
.
.
.
.
.
CLKProg
SOUT 3
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
Channel 2
DOUT 2
SOUT 2
Highside 300 m
Peak&Hold
Channel 1
DOUT 1
SOUT 1
Highside 300 m
Peak&Hold
Logic
Driver
Channel 4
DOUT 4
SOUT 4
Highside/ Lowside
300 m
Ω
Diagnosis
DIAG 1
Channel 5
DOUT 5
SOUT 5
Highside/ Lowside
300 m
Ω
DIAG 5
DIAG 6
Channel 6
DOUT 6
SOUT 6
Overtemp.
Highside/ Lowside
Vcc
GND
300 m
Ω
SCLK
Vcc
.
.
CS
.
Charge
pump
SPI
Vcc
SI
GND
.
SO
FSIN
GND
VCP
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2. Functional description
Block diagram will be added
Channel 1..3:
Only High Side Drive with Charge Pump.
Current Control
Default 2.4A peak and 1A hold with adjustable values by SPI
Types of current control are switched by SPI. ( Refer to Fig. 1)
Current regulation: Peak Current Controller with fixed Off-Time
Peak Current, Peak Time, Hold Current and Off-Time can be selected by SPI
to set average and ripple current for a given load
Channel 4..6:
Either High or Low Side Drive is configurable (by SPI)
Open load detection and switch bypassed detection can be deactivated by SPI
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Protection: The TLE6288R has integrated protection functions1 for overload and short circuit (active
current limitation), Overtemperature, ESD at all pins and overvoltage at the power outputs (zener
clamping).
Output Stage Control: Parallel Control and SPI Control
A Boolean operation (either AND or OR) is performed on each of the parallel inputs IN 1..6 and respec-
tive SPI data bits, in order to determine the states of the respective outputs. The type of Boolean op-
eration performed is programmed via the serial interface. Both, parallel inputs and respective SPI da-
tabits are high active.
IN 1…6
Truth table
parallel
Input
SPI
Bit
Output Output
OR
OFF
ON
AND
OFF
OFF
OFF
ON
AND
OR
0
0
1
1
0
1
0
1
Output
Driver
ON
ON
Serial Input bits 6 -11 of command
„Channels on / off „
Each output is independently controlled by an output latch and a common reset line FSIN, which dis-
ables all outputs. A logic high input ‘data bit’ turns the respective output channel ON, a logic low ‘data
bit’ turns it OFF.
Overtemperature Behavior:
Each channel has an overtemperature sensor and is individually protected against overtemperature.
As soon as overtemperature occurs the channel is immediately turned off. In this case here are two
different behavoirs of the affected channel that can be selected by SPI (for all channels generally).
Autorestart: as long as the input signals of the channel remains on (e.g. parallel input high) the chan-
nel turns automatically on again after cooling down.
Latching: After overtemperature shutdown the channel stays off until the this ovetemperature latch is
reset by a new LÆH transition of the input signal.
Note: These overtemperature sensors of the channels are only active if the channel is turned on.
An additional overtemperature sensor is located in the logic of the device. I monitors permanently the
IC temperature. As soon as the IC temperature reaches a specified level an overtemperature fault will
be indicated.
1
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are
considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
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Current Regulator : Peak current control with fixed off-time
Hold only : When the channel is turned on externally (SPI or parallel input) the current rises to the pro-
grammed hold current level. Then the channel is internally turned off and a timer is started for a con-
stant off-time (e.g. 200µs). After this time the channel is internally turned on again until the hold current
level is reached again and so on. This regulation workes automatically until the channel is turned of
externally.
Peak and hold mode with minimum peak time: When the channel is turned on the current rises to the
programmed peak current level. Then the channel is internally turned off, the current regulator changes
to hold current values and a timer is started for a constant off-time. After this time the channel is inter-
nally turned on again until the hold current value is reached and then again turned off for the fixed off
time. This regulation workes automatically until the channel is turned of externally.
Peak and hold mode with programmed peak time: When the channel is turned on the current rises to
the programmed peak current level. Then the channel is internally turned off and a timer is started for a
constant off-time. After this time the channel is internally turned on again until the peak current value is
reached and then again turned off. This works until the programmed peak time is over. Then the cur-
rent regulator changes to hold current values and workes as described under "hold only".
Peak Current, Peak Time, Hold Current and fixed Off-Time can be set via SPI.
To avoid regulation disturbances by current transients during switching (e.g. caused by ESD capacitors
at the outputs) the current regulator has a "leading edge blanking" of typical 20µs in all three regulation
modes. After turning on the DMOS (internally or externally) the current regulation circuit is deactivated
for the first 20µs. This guarantees that switching of the DMOS itself or charging of small capacitors at
the output (e.g. ESD) is not disturbing the current regulation.
Simplified functional block diagram:
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Current Waveforms of the different current control modes
Input Signal
No Regulation Current defined only by load
Ihd
Hold only
tfo
Ipk
Ihd
Peak & Hold
with min. peak time
tfo
tfo
Ipk
Ihd
Peak and Hold
with set peak time
tfo
tp
Fig.1
Current forms of the different current control modes of channel 1-3
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3. Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
SOUT4
DOUT4
DOUT1
SOUT1
SOUT6
DOUT6
SI
_CS
SCLK
CLK Prog
SO
VDO
Package: Power-P-DSO-36
0.65mm Pitch
IN4
IN1
DIAG1
DIAG2
TLE6288 R
(S0999)
DIAG3
DIAG4
DIAG5
28
VCC
27
26
25
24
23
22
21
20
19
Reset
IN6
DIA6/Overtemp
IN3
IN2
IN5
SOUT2
DOUT2
DOUT5
SOUT5
Fault
GND
FSIN
VCP
DOUT3
SOUT3
Pin
Name
Function
Pin Nr. Name
Function
Nr.
SOUT4
DOUT4
DOUT1
SOUT1
IN4
Source Output CH 4 (high / low side)
Drain Output CH 4 (high / low side)
Drain Output CH 1(high side)
Source Output CH 1 (high side)
Control Input Channel 4
SOUT3
DOUT3
VCP
Source Output CH 3 (high side)
Drain Output CH 3(high side)
Charge Pump pin
1
2
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3
FSIN
GND
Fault
IN3
All Channels Enable / Disable
Logic Ground
4
5
IN1
Control Input Channel 1
General Fault Flag
6
DIAG1
DIAG2
DIAG3
DIAG4
DIAG5
Diagnostic Output CH 1
Control Input Channel 3
Control Input Channel 6
Reset pin (+ Standby Mode)
Logic Supply Voltage (5V)
Supply Pin for digital outputs
SPI Serial Data Output
Program pin of SPI Clock
SPI Serial Clock
7
Diagnostic Output CH 2
IN6
8
Diagnostic Output CH 3
Reset
VCC
9
Diagnostic Output CH 4
10
11
12
13
14
15
16
17
18
Diagnostic Output CH 5
VDO
DIAG6/Overtemp Diagnostic Output CH 6 / Overtemp
SO
IN2
Control Input Channel 2
CLKProg
SCLK
IN5
Control Input Channel 5
SOUT2
DOUT2
DOUT5
SOUT5
Source Output CH 2 (high side)
Drain Output CH 2(high side)
Drain Output CH 5 (high / low side)
Source Output CH 5 (high / low side)
SPI Chip Select
CS
SI
SPI Serial Data Input
DOUT6
SOUT6
Drain Output CH 6 (high / low side)
Source Output CH 6 (high / low side)
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4. Pin description:
DOUT 1-3 – Drain of the 3 highside channels. These pins must always be connected to the same
power (battery) supply line.
SOUT 1-3 – Source of the three highside channels. Outputs of the highside channels where the load is
connected.
DOUT 4-6 – Drain pins of the three configurable channels. In highside configuration they must be con-
nected to the same voltage as DOUT 1-3. In lowside configuration they are the output pins and con-
nected to the load.
SOUT 4-6 – Source of the three configurable channels. In highside configuration they are the outputs
and connected to the load. In lowside configuration they must be connected with GND.
IN 1-6 – Parallel input pins for the 6 power outputs. These pins have an internal pull down structure.
GND – Logic ground pin.
FSIN – Disable pin. If the FSIN pin is in a logic low state, it switches all outputs OFF. An internal pull-up
structure is provided on chip.
Reset – Reset pin. When the reset is low all channels are off, the internal biasing is deactivated, all
internal registers are cleared and the supply-current consuption is reduced (standby mode). An internal
pull-up structure is provided on chip.
Fault – General Fault pin. There is a general fault pin (open drain) which shows a high to low transition
as soon as an error is latched into the diagnosis register. When the diagnosis register is cleared this
flag is also reset (high state). This fault indication can be used to generate a µC interrupt.
CLKProg – Programming pin for the SPI Clock signal. This pin can be used to configure the clock sig-
nal input of the SPI. In low state the SPI will read data at the rising clock edge and write data at the
falling clock edge. In high state the SPI will read data at the falling clock edge and write data at the ris-
ing clock edge The pin has an internal pull down structure.
DIAG1..5; DIAG6 / Overtemp. – Parallel diagnostic pins (push-pull) change state according to the in-
put signal of the corresponding channel. As soon as an error occurs at the corresponding channel (
Overload and overtemperature is detected in on state and open load /switch bypass in off state) the
DIAG output shows the inverted input signal. An fault is detected only if it lasts for longer than the fault
filtering time. The fault information is not latched in a register.
If DIAG6 is configured as Overtemperature Flag: This is a general fault pin which shows a high to low
transition as soon as an overtemperature error occurs for any one of the six channels (for longer than
the fault filtering time) or the IC logic. This fault indication can be used to differ between overload and
overtemperature errors in one of the six channels or to detect a general IC overtemperature.
VCP – Pin to connect the external capacitor of the integrated charge pump.
VDO – Supply pin of the push-pull digital output drivers. This pin can be used to vary the high-state
output voltage of the SO pin and the DIAG1-6 pins.
VCC – Logic supply pin. This pin is used to supply the integrated circuitry.
– Chip Select of the SPI
CS
SO – Signal Output of the Serial Peripheral Interface
SI – Signal Input of the Serial Peripheral Interface. The pin has an internal pull down structure.
SCLK – Clock Input of the Serial Peripheral Interface. The pin has an internal pull up structure (if
CLKProg=L) or an pull down structure (if CLKProg=H).
For more details about the SPI see Chapter 9.SPI.
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5. Maximum ratings
No. Parameter
Symbol Value
-0.3 …20
Unit Pin / Comment
1
Power Supply Voltage 1 static VB
dynamic : 1min. 0°C VB
dynamic : Test cond. Fig.1 VB
Power Supply Voltage 2
V
V
V
V
V
DOUT1-3
DOUT1-3
DOUT1-3
VCC, VDO
24
37
2
VCC, VDO - 0.3 ... 7
3a Continuous Drain Source
VDSL
40
DOUT – SOUT
Voltage (lowside configuration)
(channel 4-6)
3b Continuous Source Voltage
(Highside configuration)
VSH
-9 ... VB
V
SOUT - GND
(channel 4-6)
4
Input Voltage
VIN
-0.3 … VCC+ 0.3
V
V
IN1-6, Reset, FSIN, CS,
SCK, SI, CLKProg
5a Output Voltage
VOUT
VOUT
VCP OUT VB +10
-0.3 … VCC+ 0.3
-0.3 … VDO+ 0.3
Fault
5b Output Voltage
5c Output Voltage
V
V
DIAG1-6, SO
VCP ; no voltage must
be applied
6
Operating Temperature
Ta
Tj
Tstg
Pdmax
-40 … +105
-40 … +150
-55 … +150
°C
°C
°C
W
7
8
Storage Temperature
Power Dissipation
(Rthja= 20K/W)
(Rthja= 30K/W)
Reverse Current (1ms)
2,25
1,5
-4
9
Irev
A
V
between DOUT and-
SOUT; Channel 4 to 6
10 ESD (Human Body Model)
C= 100pF, R=1.5kΩ
VESDb
2000
Applied to all terminals 3 times
11 ESD (Machine Model)
C= 200pF, R=0Ω
VESDm
250
V
Applied to all terminals 3 times
12 Single Switch off load Inductance
see Fig.2
Fig.2
DOUT, SOUT
37V
10 times
added after characterisation
(once/ 30sec)
12V
160ms
350ms
Test cond. Fig.1
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6. Electrical Characteristics
VCC = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; VB = 6V to 16V ; Reset = H ; VDO = VCC
(unless otherwise specified)
No. Parameter
Sym- Condition
bol
Value
Unit Pin /
Comment
min typ
max
Power Supply, Reset
1
Power Supply Current 1
Ib
Ch1-Ch6:
Off
10
mA
DOUT1-3
1.1
Power Supply Current 2
Icc
10
50
mA
µA
VCC
1.2
1.3
Power Supply Current 3
in Standby Mode
Icc+Ib
Reset = L
DOUT1-3, VCC
50
µs
1.4
1.5
Minimum Reset Duration tRe-
set,min
Ccp = 10 nF
5
ms
Wake up time after reset twakeup
Power Outputs
2
On Resistance
RDS(ON) ID =2.4A
350
2
mΩ
DOUTx – SOUTx
SOUTx – DOUTx
2.1
VB=10V
ID = -4A
Tj = 150°C
Forward Voltage Revers VRDf
Diode
V
2.2
Peak Current range
Ipk
1.2 --
A
2.3
2.4
3.6
Peak Current accuracy
Ipka
Tj= 25, 150°
Tj=-40
%
15
20
Hold Current range
Ihd
0.7 --
2
A
2.5
2.6
Hold Current accuracy
Ihda
Tj= 25, 150°
Tj=-40
%
15
20
Peak time range
tp
0.8 --
3.6
ms
2.7
Peak time accuracy
Fixed off Time range
tpa
tfo
%
2.8
2.9
20
100 -
-
µs
400
Fixed off Time accuracy
Fixed off Time accuracy
tfoa
100µs
%
%
2.10
2.11
30
20
200µs-
400µs
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VCC = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; VB = 6V to 16V ; Reset = H ; VDO = VCC
(unless otherwise specified)
No. Parameter
Sym- Condition
bol
Value
min typ
Unit Pin /
Comment
max
Output ON Delay time1
Output ON Rise time1
tdON
tr
Fig.3
Fig.3
10
10
µs
µs
2.12
2.13
2.14
Output OFF Delay time1 tdOFF
Fig.3
HS- Mode
LS- Mode
Fig.3
20
20
10
µs
Output OFF Fall time1
Leackage Current
tf
µs
2.15
2.16
2.17
Reset = L
10
µA
Leak Current in OFF
Iloff
-250 µA
SOUT1-6
DOUT4-6
SOUT1-6
(highside configuration)
Leak Current in OFF
Iloff
500
-19
µA
V
2.18
2.19
(lowside configuration)
Output Clamp Voltage
Highside Configuration
Output Clamp Voltage
Lowside Configuration
Current limitation
(Channel 1-3)
Current limitation
(Channel 4-6)
IC Overtemp. Warning
Hysteresis
Vclh
Referes to
GND level
-9
40
4
-14
Vcll
Referes to
GND level
55
6
V
A
A
DOUT4-6
2.20
2.21
2.22
2.23
IDlim1-3
IDlim4-6
3
6
Tot
Thys
160
180
°C
°C
10
Digital Inputs
3
Input Low Voltage
Input High Voltage
VINL
VINH
1
V
all digit. inputs
all digit. inputs
all digit. inputs
IN1-6; CLKProg
Reset; FSIN
3.1
3.2
3.3
3.4
3.5
3.6
2
V
Input Voltage Hysteresis VINHys
100
50
mV
µA
µA
µA
Input Pull Down current
Input Pull Up current
Ipd
Ipu
Ipd
VIN = 5V
VIN = GND
VIN = 5V
20
20
10
100
100
50
50
SPI Input Pull Down
current
20
SI, SCLK
(CLKProg=H)
SPI Input Pull Up current Ipd
VIN = GND
10
20
50
µA
CS;SCLK
3.7
(CLKProg=L)
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VCC = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; VB = 6V to 16V ; Reset = H ; VDO = VCC
(unless otherwise specified)
No. Parameter
Sym- Condition
bol
Value
min typ
Unit Pin /
Comment
max
Digital Outputs
4
SO Low State Output
Voltage
VSOL
VSOH
ISOL=2.5mA
ISOH=-2mA
0.4
V
V
V
SO
4.1
SO High State Output
VDO-
0.4V
SO
4.2
4.3
Voltage
DIAG Low State Output
Voltage
IDIAGL
=
0.4
DIAG1-6
50µA
DIAG High State Output
Voltage
IDIAGH
=
VDO-
0.4V
V
DIAG1-6
4.4
-50µA
Fault Low Output Voltage Vol
Iout= 1mA
0.4
1
V
Fault
Fault
4.5
4.6
Fault Output leak Current Ioh
Output :OFF
µA
V(fault) =5V
Diagnostic Functions
5
VDS(OL) lowside con-
figuration,
5.5
4.5
V
V
5.1
Open Load Detection
Voltage
Vbat=12V
VDS(OL) highside
configura-
tion,
5.2
Open Load Detection
Voltage
Vbat=12V
Id(OL)
Vbat=Vout= 20
100
100
500
µA
5.3
Output Open Load diag-
nosis Current
Fault Filter Time
12V
tf(fault)
Id(SB)
50
200
250
µs
5.4
5.5
µA
Switch Bypass Detec-
tion Current
IDd(lim1-
3)
4
3
6
6
A
A
5.6
5.7
Overload Detection
Threshold (Channel 1-3)
IDd(lim 4-
6)
Overload Detection
Threshold (Channel 4-6)
Input Voltage
tdON
tdOFF
70%
30%
Fig.3 : Turn on/off timings with resistive load
Output Voltage
(Highside configuration)
tf
tr
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VCC = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; VB = 6V to 16V ; Reset = H ; VDO = VCC
(unless otherwise specified)
No. Parameter
Sym Condition
bol
Value
min typ max
Unit Pin /
Comment
SPI Timing
6
fSCK
MHz
Serial Clock Frequency (de-
pending on SO load)
DC
--
5
6.1
Serial Clock Period (1/fclk)
Serial Clock High Time
Serial Clock Low Time
Enable Lead Time
tp(SCK)
tSCKH
tSCKL
200
50
--
--
--
--
--
--
--
--
ns
ns
ns
ns
6.2
6.3
6.4
6.5
50
tleadL
CLKProg=L 200
CLKProg=H 200
(falling edge of
edge of SCLK)
to falling
CS
Enable Lead Time
tleadH
--
--
ns
(falling edge of
edge of SCLK)
to rising
CS
Enable Lag Time (rising edge of tlagL
CLKProg=L 200
CLKProg=H 200
CLKProg=L 20
CLKProg=H 20
CLKProg=L 20
CLKProg=H 20
---
---
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
6.6
6.7
6.8
SCLK to rising edge of
)
CS
Enable Lag Time (falling edge
tlagH
of SCLK to rising edge of
)
CS
Data Setup Time (required time tSUL
SI to rising of SCLK)
Data Setup Time (required time tSUH
--
SI to falling of SCLK)
Data Hold Time (rising edge of tHL
--
SCLK to SI)
Data Hold Time (falling edge of tHH
--
SCLK to SI)
Disable Time
Transfer Delay Time2
tDIS
tdt
--
--
200
--
ns
ns
6.9
200
6.10
(CS high time between two
accesses)
Data Valid Time
tvalid
ns
6.11
CL = 50 pF to 100pF
--
--
--
--
120
150
CL = 220 pF
1)To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay
time tf(fault)max = 200µs.
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7
Diagnostics
detailled description of the diagnosis will be added
8
SPI
The SPI is a Serial Peripheral Interface with 4 digital pins
and an 16 bit shift register. The SPI is used to configure
and program the device, turn on and off channels and to
read detailled diagnostic information.
CS
SCLK
SI
SPI
SO
8.1 SPI Signal Description:
CS - Chip Select. The system microcontroller selects the TLE 6288 R by means of the
pin. When-
CS
ever the pin is in a logic low state, data can be transferred from the µC and vice versa.
CS = H : Any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance
state.
CS = HÆL :
LSB
MSB
•
diagnostic information is transferred from
the diagnosis register into the SPI shift
register.
internal logic registers
CS
SI
SO
•
•
serial input data can be clocked into the
SPI shift register from then on
16 bit SPI shift register
Serial input
Serial output
(diagnosis)
MSB first
data MSB first
CS
SO changes from high impedance state to
logic high or low state corresponding to
the SO bits
diagnosis register
LSB
MSB
CS = L : SPI is working like a shift register. With each clock signal the state of the SI is read into the
SPI shift-register and one diagnosis bit is written out of SO.
CS = LÆH:
•
transfer of SI bits from SPI shift register into the internal logic registers
•
reset of diagnosis register if sent command was valid
To avoid any false clocking the serial clock input pin SCLK should be logic high state (if CKLProg=L;
low state if CLKProg=H) during high to low transition of
.
CS
SCLK - Serial Clock. The serial clock pin clocks the internal SPI shift register of the TLE 6288 R. The
serial input (SI) accepts data into the input SPI shift register on the rising edge of SCLK (if CKLProg=L;
falling edge if CLKProg=H) while the serial output (SO) shifts diagnostic information out of the SPI shift
register on the falling edge (if CKLProg=L; rising edge if CLKProg=H) of serial clock. It is essential that
the SCLK pin is in a logic high state (if CKLProg=L; low state if CLKProg=H) whenever chip select
CS
makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI infor-
mation is read in on the rising edge of SCLK (if CKLProg=L; falling edge if CLKProg=H). Input data is
latched in the SPI shift register and then transferred to the internal registers of the logic.
The input data consist of 16 bit, made up of 4 control bits and 12 data bits. The control word is used to
program the device, to operate it in a certain mode as well as providing diagnostic information (see SPI
Commands).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit (MSB)
first. SO is in a high impedance state until the
pin goes to a logic low state. New diagnostic data will
CS
appear at the SO pin following the falling edge of SCLK (if CKLProg=L; rising edge if CLKProg=H).
Vp2 Page 14 13.01.2003
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8.2 SPI Diagnostics:
As soon as a fault occurs for longer than the fault filtering time, the fault information is latched into the
diagnosis register (and the Fault pin will change from high to low state). A new error on the same
channel will over-write the old error report. Serial data out pin (SO) is in a high impedance state when
is high. If
receives a LOW signal, all diagnosis bits can be shifted out serially. If the sent com-
CS
CS
mand was valid the rising edge of
will reset the diagnosis registers (except the channel OT flag)
CS
and restart the fault filtering time. In case of an invalid command the device will ignore the data bits and
the diagnosis register will not be reset at the rising
edge.
CS
Bit0 and Bit1
is always 1
Diagnostic Serial Data Out SO
MSB
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LSB
Ch.6 Ch.5
Ch.4
Ch.3
Ch.2
Ch.1
IC Overtem-
perature Flag
Channel Overtem-
perature Flag
HH
HL
LH
LL
Normal function
Overload, Shorted Load or Overtemperature
Open Load
Switch Bypassed
Figure 1: Two bits per channel diagnostic feedback plus two overtemperature flags
For Full Diagnosis there are two diagnostic bits per channel configured as shown in Figure 1.
Diagnosis bit0 and bit1 are always set to 1.
Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function.
Overload, Shorted Load or Overtemperature: HL is set when the current limitation gets active, i.e.
there is a overload, short to supply or overtemperature condition. The second reason for this bit combi-
nation is overtemperature of the corresponding channel.
Open load: LH is set when open load is detected (in off state of the channel)
Switch Bypassed:
Short to GND : in lowside configuration LL is set when this condition is detected
Short to Battery : in highside configuration LL is set when this condition is detected
Channel Overtemperature Flag: In case of overtemperature in any output channel in on state the
overtemperature Flag in the SPI diagnosis register is set (change bit 3 from 0 to 1). This Bit can be
used to distinguish between Overload and Overtemperature (both HL combination) and is reset by
switching OFF/ON the affected channel.
In addition the DIAG6 / Ovtertemp pin is set low (if configured as Overtemp.Flag).
IC Overtemperature Flag: When the IC logic tremperature exceeds typ.170° the non-latching IC
Overtemperature Flag will be set in the SPI diagnosis register(change bit 2 from 0 to 1).
In addition the DIAG6 / Ovtertemp pin is set low (if configured as Overtemp.Flag).
8.3
SPI Commands, Values and Parameters:
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The 16 bit SPI is used to program different IC functions
and values, turn on and off the channels and to get de-
tailled diagnosis information. Therefore 4 command bits
and 12 data bits are used.
CS
4 Bits
12 Bits
Data
The following parameters and functional behavior can be
programmed by SPI:
SI
SO
Command
Diagnosis (Ch. 1 to 6)
+ 2 Temp. Flags
Current regulation Mode (mode) : for each of the three
SI command : 4 Command Bits program
the operation mode of Channels 1 to 6.
12 Data Bits configure the device and
give the input information (on or off) for
Channel 1 to 6.
highside channels individually the operation mode can be
set.
a) "no current regulation
b) Current regulation "hold only
c) Current regulation "peak & hold with minimum
peak time
SO diagnosis 16 bit diagnosis information
(two bit per channel) of channels 1 to 6 plus
two Overtemperature Flags
d) Current regulation "peak & hold with pro-
grammed peak time".
Peak Current (Ipk) : for each of the three highside channels individually the peak current value for P&H
current regulation can be programmed. The current range is 1.2A to 3.6A.
Fixed off time of the current regulator (tfo) : for each of the three highside channels (Ch1 - Ch3) indi-
vidually the fixed off time for all modes with current regulation can be programmed from 100µs to
400µs.
Hold Current (Ihd) : for each of the three highside channels(Ch1 - Ch3) individually the hold current
value for P&H and hold only current regulation can be programmed. The current range is 0.7A to 2.0A
Peak Time (tp) : for each of the three highside channels(Ch1 - Ch3) individually the peak time value for
P&H current regulation can be programmed. The time range is 0.8ms to 3.6ms.
Highside / Lowside Configuration ( H/L ) : Each of the three configurable channels (Ch4 – Ch6) can
be programmed for use as Highside Switch or Lowside Switch.
Open load and switch bypassed detection activated or deactivated (OL+SB) : For each of the
three configurable channels(Ch4 – Ch6) the open load and switch bypassed diagnosis can be deacti-
vated. In lowside configuration the open load and the short to GND detection can be deactivated, in
highside configuration the open load and short to battery detection.
Boolean Operation (OR / AND) : For all channels generally the Boolean operation of the parallel input
signal and the SPI bit of the corresponding channel can be defined.
Overtemperature Behavior ( R/L ) : The overtemperature behavior of the channels can be pro-
grammed by SPI. Autorestart or latching overtemperature shutdown can be selected (for all channels
the same behavior).
DIAG6 or Overtemperature Flag (D/F) : With this SPI bit the function of the DIAG6/Overtemp pin is
defined. This output can work as diagnosis output of channel 6 or as Overtemperature Flag.
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8.4
Command Table
No Command
SPI Commands
MSB
1
LSB
X
14 13 12 11 10
9
8
7
6
5
4
3
2
tp
tp
tp
1
1
2
3
Config. Regulator 1
0
0
0
0
1
1
1
0
1
Mode
Mode
Mode
Ch. 6
Ipk
tfo
Ihd
Ihd
Ihd
X
Config. Regulator 2
Config. Regulator 3
1
Ipk
tfo
X
1
Ipk
tfo
DIAG
6
Ch. 5
Ch 4
all all
OL+
OL+
SB
X
OL+ OR/
SB AND
X
H/L
X
H/L
X
H/L
X
R/L
X
D/F
X
X
X
X
X
X
X
X
X
X
X
X
4
5
6
7
Config. Ch1 - Ch6
Set all to Default
Diagnosis only
1
1
1
1
1
0
1
1
0
0
1
0
0
0
1
1
SB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Ch6 Ch5 Ch4 Ch3 Ch2 Ch1
X
Channels on / off
Legend of SPI Command Table:
Mode: Operation mode of the current regulator:
a) no regulation
b) hold only
c) peak&hold with minimum peak time
d) peak&hold with programmed peak time
Ipk : Peak current values
Ihd : Hold current values
tp : Peak time value
1.2A - 3.6A
0.7A - 2A
0.8ms – 3.6ms
100µs – 400µs
tfo : Fixed off time value
H/L : Channel 1-3 in highside or lowside configuration
OL+SB : open load detection and switch bypassed detection activated or deactivated
OR / AND : Boolean Operation (parallel input and corresponding SPI Bit)
R/L : Autorestart or Latching overtemperature behaviour
D/F : DIAG6/Overtemp pin set as Diagnosis output of channel 6 or as Overtemperature Flag
Ch1-Ch6 : On / Off information of the output drivers (high active)
Command description:
Config. Regulator 1-3: With this command the values for for the current regulation and the functional
mode of the channel is written into the internal logic registers.
Config. Ch1- Ch6 : This command writes the configuration data of the three configurable channels (4-
6) and sets the Boolean operation and overtemperature behavior of all channels. It also and sets the
DIAG6/Overtemp. pin to Diagnosis of channel 6 or Overtemperature Flag.
Set all to default : This command sets all internal logic registers back to default settings.
Diagnosis only : When this command is sent the 12 data bits are ignored. The internal logic registers
are not changed.
Channels on/off : With this command the SPI bits for the ON/OFF information of the 6 Channels are
set
Note: Specified control words (valid commands) are executed and the diagnosis register is reset after
the rising CS edge.
Not specified control words are not executed (cause no function) and the diagnosis register is not reset
after the CS = LÆH signal.
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8.5
Mode
Default settings for the internal logic registers:
:no regulation
Peak Current (Ipeak)
Hold Current (Ihold)
Fixed off Time (toff)
Peak Time (tpeak)
AND / OR
:2.4A
:1A
:200µs
:2.8ms
:OR
Autorestart / Latch
Diag6 / Temp. Fault
Highside / Lowside (4-6)
Open load & SB Yes/No (4-6)
Channels 1-6 (ON / OFF)
SPI
:Restart
:Diagnosis channel 6
:Highside
:Yes (diagnosis active)
:OFF
:all 0
8.6
Mode
Bit Assignment:
00
01
10
11
no current regulation
hold only
P&H minimum peak time
P&H with programmed times
Peak Current (Ipk)::
2 Bits
: 1.2A 1.8A
: 0 0 0 1
2.4A
1 0
3.6A
1 1
Hold Current (Ihd)
2 Bits
: 0.7A 1A
: 0 0 0 1
1.4A
1 0
2A
1 1
Fixed off Time (tfo)
2 Bits
: 100µs 200µs 300µs 400µs
: 0 0
0 1
1 0
1 1
Peak Time (tp)
3 Bits
: 0.8
: 000
1.2
1.6
2
2.4
2.8
3.2
3.6 [ms]
111
001
010
011
100
101
110
Boolean operation
1 Bit
: OR
: 0
AND
1
Overtemp. behavior
1 Bit
: Restart
: 0
Latch
1
Diag6 / Overtemp
1 Bit
:Diag6
:0
Overtemp. Flag
1
Highside/Lowside
1 Bit
:Highside
:0
Lowside
1
Open Load & SB (4-6) :Yes
1 Bit :0
No
1
Default settings are pin bold print.
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8.7
SPI Timing Diagrams :
Input Timing Diagram (CLKProg = L)
CS
0.7Vcc
tlagL
tdt
0.2 Vcc
tSCKH
0.7Vcc
0.2Vcc
SCLK
tSCKL
tleadL
tSUL
tHL
0.7Vcc
0.2Vcc
SI
SO Valid Time Waveforms
(CLKProg = L)
Enable and Disable Time Waveforms
CS
0.2 Vcc
0.2 Vcc
SCLK
tvalid
tDis
0.7 Vcc
0.2 Vcc
SO
SO
SO
0.2 Vcc
0.7 Vcc
CS
SCLK
SI
4 control bit
12 data bit
8
C o n t r o l word 11
10
9
9
7
6
5
4
3
3
2
1
0
MSB
LSB
15
14
13
12
11
10
8
7
6
5
4
2
1
0
SO
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Input Timing Diagram (CLKProg = H)
CS
0.7Vcc
tlagH
tdt
0.2 Vcc
tSCKH
tleadH
0.7Vcc
0.2Vcc
SCLK
SI
tSCKL
tHH
tSUH
0.7Vcc
0.2Vcc
SO Valid Time Waveforms
(CLKProg = H)
Enable and Disable Time Waveforms
0.7 Vcc
CS
0.2 Vcc
SCLK
tvalid
tDis
0.7 Vcc
SO
SO
0.2 Vcc
SO
0.7 Vcc
0.2 Vcc
CS
SCLK
4 control bit
C o n t r o l word 11
12 data bit
8
SI
10
10
9
7
7
6
6
5
4
4
3
2
2
1
1
0
LSB
0
MSB
15
14
13
12
11
9
8
5
3
SO
Vp2
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9
Typicel Characteristics
9.1 Zth Diagramm
.
10
Conditions:
R= 3.1 K/W
Tcase = 125°C
Single Channel Operation
D = 0.50
1
Parameters:
0.20
tp ..... Pulse Width
D ..... Duty Cycle
0.10
0.05
0.02
0.1
single
0.01
5
4
3
.
.
.
1 10
1 10
1 10
tp [s]
0.01
0.1
Vp2
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P r e l i m i n a r y D a t a s h e e t T L E 6 2 8 8 R
10 Package
(all dimensions in mm)
P-DSO 36-12
Vp2
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P r e l i m i n a r y D a t a s h e e t T L E 6 2 8 8 R
Published by
Infineon Technologies AG,
Bereichs Kommunikation
St.-Martin-Strasse 76,
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as war-
ranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your
nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives world-
wide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the
types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the ex-
press written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system, or to affect the safety or effective-
ness of that device or system. Life support devices or systems are intended to be implanted in the hu-
man body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reason-
able to assume that the health of the user or other persons may be endangered.
Vp2
Page 23
13.01.2003
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