TLE7183QUXUMA3 [INFINEON]
AC Motor Controller, 0.02A, PQFP48, TQFP-48;
| 型号： | TLE7183QUXUMA3 |
| 厂家： | 
Infineon |
| 描述： | AC Motor Controller, 0.02A, PQFP48, TQFP-48 |
| 文件： | 总28页 (文件大小：932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.1, Jan. 2016
TLE7183QU
3 Phase Driver IC
Automotive Power
TLE7183QU
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1
2
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Assignment TLE7183QU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Default State of Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
5
5.1
Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operation at Vs<12V - Integrated Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Short Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Overcurrent Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Dead Time and Shoot Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Undervoltage Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Overvoltage Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overtemperature Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ERRx pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Shunt Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Phase Voltage Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.3
5.3.1
5.4
5.4.1
6
6.1
6.2
Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Layout Guide Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Sheet
2
Rev. 1.1, 2016-01-28
3 Phase Driver IC
TLE7183QU
1
Overview
Features
•
Compatible with very low ohmic normal level input N-Channel
MOSFETs
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Separate input for each MOSFET
PWM frequency up to 30kHz
Fulfils specification down to 5.5V supply voltage
Optimized Electromagnetic Compatibility (EMC)
TQFP-48 package with exposed heat slug
Control inputs with TTL characteristics
Separate source connection for each MOSFET
Integrated minimum dead time
Shoot through protection
Short circuit protection with 5 fixed detection levels available
Disable and sleep mode features
2-bit error diagnosis
Thermal overload warning for driver IC
Integrated overcurrent warning
Integrated current sense amplifier
0 to 100% duty cycle
Green Product (RoHS compliant)
AEC Qualified
PG-TQFP-48
Description
The TLE7183QU driver IC is designed to control 6 to 12 external MOSFETs forming the converter for high current
3 phase motor drives in the automotive sector. It includes features like short circuit detection, 2-bit error diagnosis
and high output performance. It meets the typical requirements of automotive applications, e.g. full functionality
even at low battery voltages. Its 3 high side and 3 low side output stages are powerful enough to drive MOSFETs
with a gate charge of 400 nC with rise and fall times of approximately 150 ns.
Typical applications are cooling fan, water pump, electro-hydraulic and electric power steering. The TLE7183QU
is designed for a 12 V power net.
Several options are available for the fixed short circuit detection level.
Option
SCD1
Typ. SCD level
Marking
Availability
0.5V
0.75V
1V
TLE7183QU SCD1
TLE7183QU SCD2
TLE7183QU SCD3
TLE7183QU SCD4
TLE7183QU SCD5
please contact Infineon
available
SCD2
SCD3
please contact Infineon
please contact Infineon
available
SCD4
1.5V
2.0V
SCD5
Data Sheet
3
Rev. 1.1, 2016-01-28
TLE7183QU
Block Diagram
2
Block Diagram
CL1
CH1
CB1
CL2
CH2
CB2
VS
Charge Pump 1
Undervoltage detection
Charge Pump 2
Undervoltage detection
GND
___
INH
VDH
Floating HS driver
Short circuit detection
GH1
SH1
ERR1
ERR2
Diagnostic logic
Undervoltage
Overvoltage
Overtemperature
Short circuit
Reset
Floating LS driver
Short circuit detection
ENA1
ENA2
GL1
SL1
Overcurrent
L
E
V
E
L
TP
Floating HS driver
Short circuit detection
GH2
SH2
S
H
I
F
T
E
R
Floating LS driver
Short circuit detection
GL2
SL2
IL1
___
IH1
Input control
Floating HS driver
Short circuit detection
IL2
GH3
SH3
___
Shoot through
protection
IH2
IL3
___
dead time
IH3
Floating LS driver
Short circuit detection
DT
GL3
SL3
AGND
GND
ISP
ISN
Current sense OpAmp
Bias reference buffer
Overcurrent warning
Phase voltage feedback
VTHOC
VRI
VRO
VO
U_fb V_fb
W_fb
Figure 1
Block Diagram
Data Sheet
4
Rev. 1.1, 2016-01-28
TLE7183QU
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment TLE7183QU
SL1
36
GL1
35
VDH
34
CB1
33
GND
32
CL2
31
VS
30
CL1
29
CH1
28
CH2
27
ERR2
26
ERR1
25
___
GND
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
IH2
SH1
GH 1
CB2
GL2
SL2
GH 2
SH2
GH3
SH3
GND
GL3
IL2
___
IH1
IL1
GND
ENA2
ENA1
W_fb
V_fb
TLE7183QU
Topview
U_fb
___
IH3
IL3
1
2
3
4
5
6
7
8
9
10
11
12
___
INH
SL3
GND
VO
ISN
ISP
VRI
VRO
AGND VTHOC
TP
DT
Figure 2
Pin Configuration
Data Sheet
5
Rev. 1.1, 2016-01-28
TLE7183QU
Pin Configuration
3.2
Pin Definitions and Functions
Pin
1
Symbol
Function
SL3
Connection to source low side switch 3
Logic and power ground
2
GND
VO
3
Output of OpAmp for shunt signal amplification
- Input of OpAmp for shunt signal amplification
+ Input of OpAmp for shunt signal amplification
Input of bias reference amplifier
4
ISN
5
ISP
6
VRI
7
VRO
AGND
VTHOC
TP
Output of bias reference amplifier
Analog ground especially for the current sense OpAmp
Threshold voltage for overcurrent detection
test pin, connect to GND of driver IC
Dead time program pin
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DT
INH
Inhibit pin (active low)
IL3
Input for low side switch 3 (active high)
Input for high side switch 3 (active low)
Digital logic representation of the voltage phase U; positive logic
Digital logic representation of the voltage phase V; positive logic
Digital logic representation of the voltage phase W; positive logic
Enable pin (active high)
IH3
U_fb
V_fb
W_fb
ENA1
ENA2
GND
IL1
Enable pin (active high)
Logic and power ground
Input for low side switch 1 (active high)
Input for high side switch 1 (active low)
Input for low side switch 2 (active high)
Input for high side switch 2 (active low)
Error signal 1
IH1
IL2
IH2
ERR1
ERR2
CH2
CH1
CL1
VS
Error signal 2
+ terminal for pump capacitor of charge pump 2
+ terminal for pump capacitor of charge pump 1
- terminal for pump capacitor of charge pump 1
Voltage supply
CL2
GND
CB1
VDH
GL1
SL1
- terminal for pump capacitor of charge pump 2
Logic and power ground
Buffer capacitor for charge pump 1
Connection to drain of high side switches for short circuit detection
Output to gate low side switch 1
Connection to source low side switch 1
Logic and power ground
GND
SH1
GH1
CB2
Connection to source high side switch 1
Output to gate high side switch 1
Buffer capacitor for charge pump 2
Data Sheet
6
Rev. 1.1, 2016-01-28
TLE7183QU
Pin Configuration
Pin
41
42
43
44
45
46
47
48
Symbol
GL2
Function
Output to gate low side switch 2
Connection to source low side switch 2
Output to gate high side switch 2
Connection to source high side switch 2
Output to gate high side switch 3
Connection to source high side switch 3
Logic and power ground
SL2
GH2
SH2
GH3
SH3
GND
GL3
Output to gate low side switch 3
Data Sheet
7
Rev. 1.1, 2016-01-28
TLE7183QU
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Voltages
4.1.1
Supply voltage
VS
-4.0
45
V
with 10Ohm and
1µF
4.1.2
4.1.3
4.1.4
Supply voltage
Supply voltage
VS
VS
-0.3
-0.3
-0.3
45
47
6.0
V
V
V
–
tp<200ms
Voltage range at IHx,ILx,ERRx, VO, DT, VDP
–
VTHOC, ENAx, VRI, VRO
4.1.5
Voltage range at INH
Voltage range at TP
Voltage range at SLx
Voltage range at SHx
Voltage range at GLx
Voltage range at GHx
Voltage difference Gxx-Sxx
Voltage range at VDH
Voltage range at VDH
VINH
VTP
-0.3
-0.3
-7
18.0
2
V
V
V
V
V
V
V
V
V
–
4.1.6
4.1.7
VSL
7
–
4.1.8
VSH
VGL
-7
45
18
55
15
55
55
–
4.1.9
-7
–
4.1.10
4.1.11
4.1.12
4.1.13
VGH
VGS
VVDH
VVDH
-7
–
-0.3
-0.3
-4.0
–
INH=high
INH=high;
with RVDH >70Ω;
200ms, 5x
4.1.14
4.1.15
Voltage range at VDH
Voltage range at VDH
VVDH
VVDH
-0.3
-4.0
28
28
V
V
INH=low
INH=low;
with RVDH >70Ω;
200ms, 5x
4.1.16
4.1.17
4.1.18
4.1.19
4.1.20
4.1.21
4.1.22
4.1.23
4.1.24
4.1.25
Voltage range at CL1
VCL1
VCH1
VDC1
VCL2
VCH2
VCP2
VISI
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-5
25
25
25
25
45
25
5
V
–
–
–
–
–
–
–
–
–
–
Voltage range at CH1, CB1
Voltage difference CH1-CL1
Voltage range at CL2
V
V
V
Voltage range at CH2, CB2
Voltage difference CH2-CL2
Voltage range at ISP, ISN
Output current range at VO
Gate resistor
V
V
V
IVO
-20
2
20
–
mA
Ω
V
RGate
Voltage range at U_fb, V_fb and W_fb VX_fb
-0.3
6
Temperatures
4.1.26
4.1.27
Junction temperature
Storage temperature
Tj
-40
-55
150
150
°C
°C
–
–
Tstg
Data Sheet
8
Rev. 1.1, 2016-01-28
TLE7183QU
General Product Characteristics
Absolute Maximum Ratings (cont’d)1)
40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
4.1.28
4.1.29
Lead soldering temperature
(1/16’’ from body)
Peak reflow soldering temperature2)
Tsol
Tref
–
260
°C
°C
–
–
–
–
–
260
5
Thermal Resistance
4.1.30
Junction to case
RthjC
K/W
W
–
–
Power Dissipation
4.1.31
Power Dissipation (DC) @ TCASE=125°C Ptot
2
ESD Susceptibility
4.1.32
4.1.33
4.1.34
ESD Resistivity3)
VESD
VESD
–
2
kV
V
ESD Resistivity to GND
-500
500
750
CDM4)
CDM4)
ESD Resistivity Pin 1, 12, 13, 24, 25, 36, VESD1, 12, -750
V
37,48 (corner pins) to GND
13, 24, 25, 36,
37, 48
1) Not subject to production test, specified by design.
2) Reflow profile IPC/JEDEC J-STD-020C
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
4) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1
Attention: Stresses above the ones listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Attention: Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the data sheet. Fault conditions are considered as “outside” normal operating
range. Protection functions are not designed for continuous repetitive operation.
4.2
Functional Range
Pos.
4.2.1
Parameter
Symbol
Limit Values
Max.
Unit
Conditions
Min.
Supply voltage1)2)
VS
5.5
5.5
20
28
V
DC
t<1s
4.2.2
4.2.3
Duty cycle3)
D
0
0
100
25
%
–
PWM frequency
fPWM
kHz
Total gate charge
400nC
4.2.4
4.2.5
Quiescent current4)
IQ
–
–
30
30
µA
µA
VS,VDH<20 V
Quiescent current into VDH
IQ_VDH
VDH<20V;
VS pin open
4.2.6
Supply current at Vs
IVs
fPWM=25kHz
QG=250nC:
VS = 5.5V
VS = 14V
VS = 17V
VS = 20V
–
–
175
175
110
110
mA
Data Sheet
9
Rev. 1.1, 2016-01-28
TLE7183QU
General Product Characteristics
Pos.
Parameter
Symbol
Limit Values
Max.
Unit
Conditions
Min.
4.2.7
4.2.8
4.2.9
Supply current at Vs(device
disabled by ENA)
IVs(o)
IVDH
–
60
50
mA
mA
Vs=5.5V..17V
Vs=17V..20V
Currrent into VDH (device not in
sleep mode)
1.5
VVDH=5.5..20V
INH=high
Voltage difference CB2-VDH
VCB2
Tj
-0.3
-40
25
V
Operation mode
4.2.10 Junction temperature
150
°C
1) max ratings for Tj has to be considered as well
2) For proper start up minimum Vs=6.5V is required
3) Duty cycle is referred to the high side input command (IHx); The duty cycles can be driven continuously and fully operational
4) total current consumption from power net (Vs and VDH)
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Default State of Inputs
Table 1
Default State of Inputs
Characteristic
State
Low
Remark
Default state of ILx (if ILx left open)
Default state of IHx (if IHx left open)
Low side MOSFETs off
High side MOSFETs off
Device outputs disabled
Device outputs disabled
Sleep mode, IQ < 30 µA
–
High
Default state of ENA (if ENA1 left open) Low
Default state of ENA (if ENA2 left open) Low
Default state of INH (if INH left open)
Low
Default State of sense amplifier output VO Zero ampere equivalent
(ISP=ISN=0V)
Status of the device and the outputs when Device active and outputs functional
ENA1=ENA2=INH=high
Vs=5.5..28V
Pull up or pull down integrated resistors 30kΩ +/-50%
Ixx, ENA
–
–
Pull down integrated resistor INH
45kΩ +/-50%
Note: The load condition “C=22nF; RLoad=1Ω” in the paragraph “Electrical characteristics / Dynamic charactersitic” means that
RLoad is connected between the output Gxx and the positive terminal of the C. The negative terminal of the C is connected
to GND and the corresponding Sxx. The voltage is measured at the positive terminal of the C.
Data Sheet
10
Rev. 1.1, 2016-01-28
TLE7183QU
Description and Electrical Characteristics
5
Description and Electrical Characteristics
5.1
MOSFET Driver
5.1.1
Output Stages
The six powerful push-pull output stages of the TLE7183QU are floating blocks, each one of them with its own
source pin which can be directly connected to the source pin of an external MOSFET. This enables a perfect
control of each MOSFET’s gate-source voltage even if a current of 200A is driven in the bridge.
All output stages have the same high output power. A single output stage is able to drive a single MOSFET with
400nC gate charge (or two MOSFETs with 200nC) achieving rise and fall times of approx. 150ns.
They can be switched with a frequency of up to 30kHz. The usability at higher frequencies is limited by the
maximum allowed power dissipation, the max. junction temperature and the limited current capabilities of the
charge pump.
Each output stage has its own short circuit detection block. Please see Chapter 5.2.1 for short circuit detection
details.
___
VS
INH
CL1 CH1
CB1 CL2 CH2
Charge Pump 2
VDH
CB2
Charge Pump 1
CB2
UVLO
Undervoltage lock out
Error logic
Reset
+
-
GHx
SHx
ERR1
ERR2
Power On Reset
Undervoltage
Overvoltage
Overtemperature
Short circuit
Over-current
VSCP
ENA1
ENA2
Level
shifter
SCD
SCD
Floating HS driver 3x
CB1
SCD
lock /
unlock
Short Circuit
Detection Level
___
IH1
short circuit filter
IL1
+
-
___
GLx
SLx
Input Logic
ON / OFF
ON / OFF
IH2
Shoot Through
Protection
IL2
VSCP
___
IH3
IL3
Level
shifter
Dead Time
Floating LS driver 3x
DT
GND
Figure 3
Block Diagram of Driver Ouput Stages including Short Circuit Detection
Data Sheet
11
Rev. 1.1, 2016-01-28
TLE7183QU
Description and Electrical Characteristics
5.1.2
Operation at Vs<12V - Integrated Charge Pumps
In 12V automotive applications, correct operation has to be assured also at lower supply voltages, even at 9V. At
low supply voltages conventional bridge drivers provide clearly less than 9V to the gate of an external MOSFET.
However low gate-source voltage increases RDSon of the MOSFET. This leads to an undesired, higher power
dissipation.
The two charge pumps circuitries of TLE7183QU address this problem enabling operation even at lower supply
voltages. Their operational capability does not depend on a specific pulse pattern of the MOSFETs overcoming
duty cycle limitations which are inherent to drivers that use the bootstrap principle instead. Therefore TLE7183QU
supports the complete duty cycle range from 0 to 100%. This simplifies the usabilty in all applications and
especially when used with block wise commutation. The charge pumps are only deactivated if the device is set to
sleep mode using INH.
The first charge pump supplies the low side MOSFETs and the corresponding output stages with sufficient voltage
to assure 10V gate-source voltage even if Vs<10V. In addition it also supplies most of the internal circuitries,
including the second charge pump.
The second charge pump supplies the high side MOSFETs and the corresponding output stages. It is pumped on
the voltage of Vs.
Each charge pump circuitry requires external pump (CPx) and buffer (CBx) capacitors. The output of the first
charge pump is CB1 which is referenced to GND. The output of the second charge pump is CB2 which is
referenced to VDH. VDH and Vs are usually in the same voltage range. The driver is not designed to have
significant higher voltages at VDH compared to Vs. This would lead to reduced supply voltages for the high side
output stages.
The outputs of both charge pumps are regulated. The first charge pump doubles the supply voltage for Vs<8V.
For 8V<Vs<15V, its output is regulated to a typical voltage of 15V. For Vs>15V, its output increases linearly but
does not exceed 25V.
For a proper wake up of the device at VVsWU, it is not permitted to have any PWM patterns at the input pins ILx and
IHx before the charge pumps have ramped up to their final values unless the output stages have been switched
off by setting one of the ENAx pins to low.
The size of the charge pump capacitors (pump capacitors CPx as well as buffer capacitors CBx) can be varied
between 1 µF and 4.7 µF. Yet, larger capacitor values result in higher charge pump voltages and less voltage
ripple on the charge pump buffer capacistors CBx (which supply the internal circuits as well as the external
MOSFETs, pls. see above). Besides the capacitance values the ESR of the buffer capacitors CBx determines the
voltage ripple as well. It is recommended to use buffer capacitors CBx that have small ESR.
Please see also Chapter 5.1.3 for capacitor selection.
5.1.3
Sleep Mode
If the INH pin is set to low, the driver will be set to sleep mode. The INH pin switches off the complete supply
structure of the device and finally leads to an undervoltage shut down of the complete driver. Enabling the device
with the INH pin means to switch on the supply structure. The device will run through power on reset during wake
up. It is recommended to perform a reset using ENAx after wake up to remove possible ERRx signals. Reset is
performed by keeping one or more ENAx pins low until the charge pump voltages have ramped up.
Enabling and disabling with the INH pin is not very fast. Please consider using the ENAx pins to speed things up.
If the TLE7183QU is in sleep mode or if the supply voltage Vs is not available, then the driver IC is not supplied,
the charge pumps are inactive and the charge pump capacitors are discharged. Pin CB2 (+ terminal of buffer
capacitor 2) will decay to GND. If the battery voltage is still applied to VDH (- terminal of buffer capacitor 2) the
buffer capacitor 2 will slowly be charged to battery voltage with reversed polarity compared to the one during
regular operation. Hence, it is important to use a buffer capacitor 2 (CB2) that can withstand both, +25 V in regular
operation mode and -VBAT in sleep mode, e.g. a ceramic capacitor. If there is load dump in sleep mode, then the
negative voltage across CB2 will be clamped to -31 V (CB2 referenced to VDH).
Data Sheet
12
Rev. 1.1, 2016-01-28
TLE7183QU
Description and Electrical Characteristics
5.1.4
Electrical Characteristics
Electrical Characteristics MOSFET drivers - DC Characteristics
VS = 5.5 to 20V, Tj = -40 to +150°C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
–
Typ.
Max.
5.1.1
5.1.2
Low Level Output Voltage
VG_LL
VG_HL
–
–
0.2
13
V
V
I=30mA
High Level Output Voltage, Low
Side
7.5
I=-2mA; Vs=5.5..8V
5.1.3
High Level Output Voltage, High
Side
VG_HL
6.5
–
13
V
I=-2mA; Vs=5.5..8V
5.1.4
5.1.5
High Level Output Voltage
VG_HL
dVG_H
9
–
–
–
13
V
V
I=-2mA; Vs=8..20V
I=-100mA; Vs=20V
High Level Output Voltage
Difference
1.0
5.1.6
5.1.7
Gate Drive Output Voltage (device VG(DIS)
disabled via ENAx)
–
–
–
–
0.2
V
V
Disabled;
Vs=5.5..20V;
I=10mA
Gate Drive Output Voltage
Tj=-40°C
VG_5
UVLO; Vs<=5.5V
1.4
1.2
1.0
Tj=25°C
Tj=150°C
5.1.8
5.1.9
Gate Drive Output Voltage High
Side
Tj=-40°C
Tj=25°C
Tj=150°C
VG_HS
–
–
V
Overvoltage
1.4
1.2
1.0
Gate Drive Output Voltage Low
Side
VG_LS
VI_LL
VI_HL
–
–
–
–
0.2
1.0
–
V
V
V
Overvoltage
5.1.10 Low Level Input Voltage of Ixx,
ENAx
–
–
–
5.1.11 High Level Input Voltage of Ixx,
ENAx
2.0
5.1.12 Low Level Input Voltage of INH
5.1.13 High Level Input Voltage of INH
VI_LL
VI_HL
–
–
0.75
–
V
–
2.1
50
–
V
–
5.1.14 Input Hysteresis of IHx, ILx, ENAx dVI
5.1.15 Input Hysteresis of IHx, ILx, ENAx dVI
–
–
mV
mV
mA
Vs=5.5..8V
Vs=8..20V
100
-1.6
200
-1.0
–-
5.1.16 Output Bias Current SHx
ISHx
-0.3
VSHx=0..(Vs+1);
ILx=low; IHx=high
5.1.17 Output Bias Current SLx
ISLx
-1.6
-1.0
-0.3
mA
VSLx=0..7V;
ILx=low; IHx=high
Data Sheet
13
Rev. 1.1, 2016-01-28
TLE7183QU
Description and Electrical Characteristics
Electrical Characteristics MOSFET drivers - Dynamic Characteristics
VS = 5.5 to 20V, Tj = -40 to +150°C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.1.18 Minimum Internal Dead Time
tDT_MIN
50
–
200
ns
µs
DT pin to GND
(RDT=0Ω)
5.1.19 Programmable Internal Dead Time tDT
0.26
0.64
1.07
2.02
0.41
1.05
1.85
3.82
0.56
1.45
2.63
5.62
RDT=10 kΩ
RDT=47 kΩ
RDT=100 kΩ
RDT=1000 kΩ
5.1.20 Maximum Internal Dead Time
5.1.21 Turn On Current, Peak
tDT_MAX
2.33
–
–
6.35
–
µs
A
DT pin open
IG(on)
IG(on)
IG(off)
tG_rise
-0.8
VGxx-VSxx=0V;
Vs=5.5..8V;
C=22nF;
R
Load=1Ω
5.1.22 Turn On Current, Peak
5.1.23 Turn Off current, Peak
–
–
–
-1.5
1.5
–
–
A
VGxx-VSxx=0V;
Vs=8..20V
C=22nF;
R
Load=1Ω
A
VGxx-VSxx=10V;
Vs=8..20V
C=22nF;
R
Load=1Ω
5.1.24 Rise Time (20-80%)
Tj = -40°C
ns
C=22nF; RLoad=1Ω
400
400
700
150
150
Tj = 25°C
Tj = 150°C
5.1.25 Fall Time (20-80%)
Tj = -40°C
tG_fall
–
ns
C=22nF; RLoad=1Ω
230
230
500
Tj = 25°C
Tj = 150°C
5.1.26 Input Propagation Time (Low on)
5.1.27 Input Propagation Time (Low off)
tP(ILN)
tP(ILF)
90
0
190
100
190
100
–
290
200
290
200
70
ns
ns
ns
ns
ns
C=22nF; RLoad=1Ω
C=22nF; RLoad=1Ω
C=22nF; RLoad=1Ω
C=22nF; RLoad=1Ω
C=22nF; RLoad=1Ω
5.1.28 Input Propagation Time (High on) tP(IHN)
5.1.29 Input Propagation Time (High off) tP(IHF)
90
0
5.1.30 Absolute Input Propagation Time
Difference (all channels turn on)
tP(an)
–
5.1.31 Absolute Input Propagation Time
Difference (all channels turn off)
tP(af)
–
–
–
–
50
ns
ns
C=22nF; RLoad=1Ω
C=22nF; RLoad=1Ω
5.1.32 Absolute Input Propagation Time
Difference (1channel High off - Low
on)
tP(1hfln)
150
5.1.33 Absolute Input Propagation Time
Difference (1channel Low off - High
on)
tP(1lfhn)
–
–
150
ns
C=22nF; RLoad=1Ω
Data Sheet
14
Rev. 1.1, 2016-01-28
TLE7183QU
Description and Electrical Characteristics
Electrical Characteristics MOSFET drivers - Dynamic Characteristics
VS = 5.5 to 20V, Tj = -40 to +150°C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.1.34 Absolute Input Propagation Time
Difference (all channels High off -
Low on)
tP(ahfln)
–
–
150
150
20
ns
C=22nF; RLoad=1Ω
5.1.35 Absolute Input Propagation Time
Difference (all channels Low off -
High on)
tP(alfhn)
–
–
–
–
ns
C=22nF; RLoad=1Ω
5.1.36 Wake Up Time; INH Low to High
tINH_Pen
ms
Driver fully
functional;
Vs=6.5...8V;
ENAx=low;
CPx=CBx=4.7µF
5.1.37 Wake Up Time; INH Low to High
tINH_Pen
tINH_log
tINH_log
–
–
–
–
–
–
10
10
5
ms
ms
ms
Driver fully
functional;
VS=8..20V;
ENAx=low;
CPx=CBx=4.7µF;
5.1.38 Wake Up Time Logic Functions;
INH Low to High
diagnostic, OpAmp
working;
Vs=6.5...8V;
ENAx=low;
CPx=CBx=4.7µF
5.1.39 Wake Up Time Logic Functions;
INH Low to High
diagnostic, OpAmp
working;
VS=8..20V;
ENAx=low;
CPx=CBx=4.7µF
5.1.40 INH Propagation Time to Disable
the Output Stages
tINH_P(O)
tINH_P(O)
tINH_P(IC)
VVsWU
fCP
–
–
10
8
µs
µs
µs
V
Vs=5.5..8V
Vs=8..20V
–
5.1.41 INH Propagation Time to Disable
the Output Stages
–
–
5.1.42 INH Propagation Time to Disable
the entire Driver IC
–
–
300
–
5.1.43 Supply Voltage Vs for Wake Up
6.5
38
–
diagnostic, OpAmp
working;
5.1.44 Charge Pump Frequency
55
72
kHz
–
Data Sheet
15
Rev. 1.1, 2016-01-28
TLE7183QU
5.2
Protection and Diagnostic Functions
Short Circuit Detection
5.2.1
The TLE7183QU provides a short circuit detection for the external MOSFETs. It monitors their drain-source
voltage. It is active as soon as the corresponding input is set to "on" and the dead time has elapsed.
If the drain-source voltage is higher than the short circuit detection level, a timer will be started. After a delay of
about 6 µs all external MOSFETs will be switched off. The ERRx pins will indicate a short circuit. This error is not
self-clearing. The driver has to be reset using one of the ENAx pins.
The short circuit detection level is a fixed setting of the chip. Several options are available and described in
Chapter 5.2.8.
5.2.2
Overcurrent Warning
The TLE7183QU offers the possibility to have a warning at the ERRx pins if a current threshold is reached. (see
Figure 4 ).
The output of the current sense OpAmp is connected to an integrated comparator. It compares the amplified
current sense signal with an external adjustable threshold. After the comparator a blanking time (1.5 µs typ.) is
implemented to avoid false triggering caused by an overshoot of the current sense signal. If the overcurrent
situation is detected, there is a warning at the ERRx pins.
The driver remains in normal operation mode. The overcurrent warning is self-clearing. It will be cleared if the
current drops below the overcurrent limit set on the VTHOC pin. The overcurrent warning is also cleared if the
current commutates from the low side MOSFET to the associated high side MOSFET (no current through the
shunt resistor).
It is up to the user to react on the overcurrent warning by modifying the Ixx patterns to lower the current.
5.2.3
Dead Time and Shoot Through Protection
In bridge applications it has to be assured that the external high side and low side MOSFETs in a single half bridge
are not switched on at the same time. This would lead to a direct connection from battery voltage to GND. The
integrated mechanisms of TLE7183QU preventing this are called shoot through protection and minimum dead
time generation.
The shoot through protection is a locking mechanism which deals with faulty input commands at the Ixx pins. If the
command is given to switch on the high side and the low side MOSFET of a single half bridge at same time, it is
ignored. The driver output stages remain unchanged.
The dead time of a half bridge is the time after the command to switch off a MOSFET has been given during which
the command to switch on the other MOSFET is not executed. A minimum dead time has to be applied because
switching does not happen instantly. If both MOSFETs of a single half bridge start to switch at the same time, both
of them may be on at the same time causing the critical connection from battery voltage to ground. The dead time
assures that a MOSFET is only switched on after the other one has been switched off.
The exact dead time of the bridge is usually set by the PWM generation unit of the µC. The minimum dead time
generation of TLE7183QU assures a minimum dead time if the input signals from the µC are faulty. If the DT pin
is connected to GND, the generated minimum dead time is fixed to 50..200ns .
It can be increased by connecting the DT pin via a dead time resistor RDT to GND - the larger the dead time resistor,
the larger the dead time (please see Programmable Internal Dead Time for details).
5.2.4
Undervoltage Shut Down
The TLE7183QU has an integrated undervoltage shut down, to assure that the behavior of the device is
predictable in all supply voltage ranges.
Data Sheet
16
Rev. 1.1, 2016-01-28
TLE7183QU
If the voltage of a charge pump buffer capacitors CBx reaches the undervoltage shut down level for a minimum
specified filter time, the gate-source voltage of all external MOSFETs will be actively pulled to low. In this situation
the short circuit detection of this output stage is deactivated to avoid a latching shut down of the driver.
If the charge pump buffer voltage recovers, the status of the output stages will match the input patterns again. This
allows an operation of the motor in case of undervoltage shut down without a reset by the µC.
Undervoltage shut down will not occur if VS > 6 V, QG < 250 nC, fPWM < 25 kHz, and the charge pump capacitors
CPx, CBx = 4.7 µF.
5.2.5
Overvoltage Shutdown
The TLE7183QU has an integrated overvoltage shut down to avoid destruction of the IC at high supply voltages.
The voltages at the pins Vs and VDH are monitored. The external MOSFETs will be switched off if one or both of
them exceed the overvoltage shut down level for more than the specified filter time. In addition, the overvoltage
condition will lead to a shut down of the charge pumps and a discharge of the charge pump capacitors. This results
in an undervoltage condition which will be indicated at the ERRx pins. During overvoltage shut down the external
MOSFETs and the charge pumps remain off until a reset is performed.
5.2.6
Overtemperature Warning
If the junction temperature is exceeding typ. 170°C, an overtemperature warning is reported at the ERRx pins.
However the driver IC will continue to operate in order not to disturb the application.
This warning is self-clearing and will be cleared if the junction temperature cools down again. It is up to the user
to protect the device from overtemperature destruction.
5.2.7
ERRx pins
The TLE7183QU has two status pins to provide diagnostic feedback to a µC. The outputs of these pins are 5V
push pull stages which are either high or low. Table 2 contains an overview. Some errors require a full reset of the
driver using one of the ENAx pins to return to normal operation. Please see Table 3 for details.
If multiple errors occur at the same time, only the one with the highest priority listed in Table 4 is reported. If the
device is disabled using one of the ENAx pins, only the errors Undervoltage and Overtemperature Warning are
reported. Other errors are not reported.
Table 2
Overview of Error Conditions
ERR1
Low
ERR2
Low
Driver conditions
no errors
High
High
Low
Low
Overtemperature Warning or Overvoltage Shut Down
Undervoltage Shut Down
High
High
Short Circuit Detection or Overcurrent Warning
Table 3
Behavior at different Error Conditions
Error condition
restart behavior
Shuts down...
Short Circuit Detection
Overcurrent Warning
Latch, reset must be performed at ENAx pin All external Power -MOSFETs
Self clearing
Nothing
Undervoltage Shut Down Auto restart
Overvoltage Shut Down
Overtemperature Warning Self clearing
All external Power -MOSFETs
Latch, reset must be performed at ENAx pin All external Power -MOSFETs
Nothing
Note:Errors do NOT lead to sleep mode. Sleep mode is only initiated with the INH pin. The latch and restart
behavior allows to distinguish between the different combined error types reported at the ERRx pins.
Data Sheet
17
Rev. 1.1, 2016-01-28
TLE7183QU
Table 4
Prioritization of Errors
Priority
Error
1
2
3
4
Short Circuit Detection
Undervoltage Shut Down
Overvoltage Shut Down
Overtemperature Warning
Overcurrent Warning
5.2.8
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 5.5 to 20V, Tj = -40 to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Overtemperature
5.2.1
5.2.2
Overtemperature Warning
Tj(OW)
150
–
170
20
190
–
°C
°C
–
–
Hysteresis for Overtemperature
Warning
dTj(OW)
Overcurrent warning
5.2.3
5.2.4
5.2.5
5.2.6
Overcurrent Threshold
Overcurrent Threshold
VTHOC
VTHOC
2
–
–
–
–
4.5
4.8
50
5
V
Vs=5.5..8V
2
V
Vs=8..20V
Input Offset Voltage of OC Comp VOCOF
-50
-5
mV
mV
–
–
Input Offset Voltage Temperature VIO
Drift of OC Comp1)
5.2.7
5.2.8
5.2.9
Overcurrent Warning Threshold
Hysteresis
dVTHOC
dVTHOC
25
50
1.0
–
mV
mV
µs
Vs=5.5..8V
Vs=8..20V
Overcurrent Warning Threshold
Hysteresis
80
–
Filter Time of Overcurrent Warning tOC
1.5
3.0
Short Circuit Protection
5.2.10 Filter Time of Short Circuit
Protection
5.2.11 Maximum Duty Cycle for no SCD2) DySCDmax
tSCP(off)
4.5
–
6.8
–
9
6
µs
%
default
fPWM=20kHz at IHx
or ILx and at static
applied SC
5.2.12 Minimum Duty Cycle for Periodic
SCD2)
DySCDmin
13
–
–
%
V
fPWM=20kHz at IHx
or ILx and at static
applied SC
5.2.13 Short Circuit Detection Level SCD1 VSCP1(off)
0.3
0.5
0.65
please contact
Infineon
5.2.14 Short Circuit Detection Level SCD2 VSCP2(off)
5.2.15 Short Circuit Detection Level SCD3 VSCP3(off)
0.6
0.75
1.0
0.9
V
V
–
0.85
1.15
please contact
Infineon
Data Sheet
18
Rev. 1.1, 2016-01-28
TLE7183QU
Electrical Characteristics - Protection and diagnostic functions (cont’d)
VS = 5.5 to 20V, Tj = -40 to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.2.16 Short Circuit Detection Level SCD4 VSCP4(off)
1.35
1.5
1.65
V
V
please contact
Infineon
5.2.17 Short Circuit Detection Level SCD5 VSCP5(off)
ERRx pins
1.8
2.0
2.2
–
5.2.18 High Level Output Voltage of ERRx VOHERR
5.2.19 Low Level Output Voltage of ERRx VOLERR
4.0
–
–
–
5.2
0.4
200
V
I= -0.2mA
I= 0.2mA
–
-0.1
V
5.2.20 Propagation Time Difference ERR1 tPD(ERR)
ns
to ERR2
5.2.21 Rise Time ERRx (20 - 80 %)
5.2.22 Fall Time ERRx (80 - 20 %)
Over- and undervoltage
tr(ERR)
tf(ERR)
50
50
–
–
600
400
ns
ns
CLOAD=100pF
CLOAD=100pF
5.2.23 Overvoltage Shut Down
5.2.24 Overvoltage Filter Time
5.2.25 Undervoltage Shut Down CB1
5.2.26 Undervoltage Shut Down CB2
VOV(off)
tOV
28
–
33
V
on Vs and/or VDH
30
6.75
3.9
–
–
65
µs
V
–
VUV1
VUV2
VDUV
–
8.25
5.7
–
CB1 to GND
CB2 to VDH
–
–
V
5.2.27 Undervoltage Shut Down
Hysteresis of CB1 and CB2
1.0
V
5.2.28 Undervoltage Filter Time
tUV
1
–
3
µs
–
Reset and Enable
5.2.29 Reset Time to clear ERRx
Registers
tRes1
2.0
–
–
–
–
–
–
–
µs
µs
µs
µs
µs
–
–
–
–
–
5.2.30 Low Time of ENAx Signal without tRes0
0.5
2.0
0.5
1.0
Reset
5.2.31 ENAx Propagation Time (High --> tPENA_H-L
–
Low)
5.2.32 ENAx Propagation Time (Low --> tPENA_L-H
–
High)
5.2.33 Return Time to Normal Operation tAR
at Auto-Restart
–
1) Not subject to production test; specified by design
2) Parameters describe the behavior of the internal SCD circuit. Therefore only internal delay times are considered. In
application dead-/ delay times determined by application circuit (switching times of MOSFETs, adjusted dead time) have
to be considered as well.
Data Sheet
19
Rev. 1.1, 2016-01-28
TLE7183QU
5.3
Shunt Signal Conditioning
The TLE7183QU incorporates a fast and precise operational amplifier for conditioning and amplification of the
current sense shunt signal. A reference bias buffer is integrated to provide an adjustable bias reference for the
three OpAmps. The voltage divider connected to the VRI pin should be less than 50 kOhm. If required at all, the
filtering capacitor should be less than 1.2 µF. The gain of the OpAmp can be adjusted by external resistors within
a range of 5 to 15.
If V(ISP) equals V(ISN), VO provides the reference voltage VRO. Using a voltage divider VRO is usually set to half
of the regulated voltage to allow bi-directional current sensing. The additional buffer permits the adaptation of the
reference bias to different µC I/O voltages.
The output of the I-DC link Opamp VO is not short-circuit proof.
5V
RVRI
VRI
RVRI
CVRI
TLE7183QU
+
VRO
Bias
Reference
-
Rfb
to Error
logic
Rs
Rs
ISP
+
OC
Comp
blanking
time
1.5µs
I-DC Link
OpAmp
Rshunt
overcurrent
-
ISN
Rfb
5V
adjustable
overcurrent
limit
VTHOC
VO
to ADC
Figure 4
Shunt Signal Conditioning Block Diagram and Overcurrent Limitation
For overcurrent warning, please see Chapter 5.2.2.
Data Sheet
20
Rev. 1.1, 2016-01-28
TLE7183QU
5.3.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
VS = 5.5 to 20V, Tj = -40 to +150°C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
100
Typ.
500
Max.
5.3.1
5.3.2
Series Resistors
RS
1000
–
Ω
Ω
–
–
Feedback Resistor
Rfb
2000
7500
Limited by the Output Voltage
Dynamic Range
5.3.3
5.3.4
Resistor Ratio (Gain Ratio)
Rfb/RS
5
–
–
15
–
–
–
Steady State Differential Input
Voltage Range across VIN1)
VIN(ss)
-400
400
mV
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
Transient Differential Input Voltage VIN(tr)
Range across VIN
-800
-800
-800
-800
–
–
–
–
–
1
800
mV
mV
mV
mV
mV
–
Input Differential Voltage (ISP -
ISN)
VIDR
800
–
Input Voltage (Both Inputs - GND) VLL
(ISP - GND) or (ISN -GND)
1500
2000
+/-5
Vs=5.5..8V
Vs=8..20V
Input Voltage (Both Inputs - GND) VLL
(ISP - GND) or (ISN -GND)
Input Offset Voltage of the I-DC link VIO
OpAmp
RS=500Ω; VCM=0V;
VO=1.65V;
VRI=1.65V
5.3.10 Input Offset Voltage Temperature VIO
–
1
2
mV
RS=500Ω; VCM=0V;
VO=1.65V;
Drift of the I-DC link OpAmp2)
VRI=1.65V
5.3.11 Input Offset Voltage of the
Reference Buffer
VIO
1
1
+/-5
2
mV
mV
–
5.3.12 Input Offset Voltage Temperature VIO
–
Drift of the Reference Buffer2)
5.3.13 Input Range at VRI
VIO
IIB
1.2
–
–
–
2.8
–
V
–
5.3.14 Input Bias Current (ISx to GND)
5.3.15 High Level Output Voltage of VO
-300
4.8
µA
V
VCM=0V; VO=open
VOH
5.2
VRI=1.65V/2.5V;
IOH=-3mA
5.3.16 Low Level Output Voltage of VO
VOL
VOR
-0.1
–
0.2
V
V
VRI=1.65V/2.5V;
IOH=3mA
5.3.17 Output Voltage of VO3)
VRI= 2.5V,
VIN(SS)=0V;
Gain=15;
2.42
1.58
2.50
1.65
2.58
1.73
VRI=1.65V
5.3.18 Temperature Drift of Output
Voltage of VO3)
VO
0
–
32
mV
mA
VIN(SS)=0V;
Gain=15
5.3.19 Guaranteed Output Current
Capability
5.3.20 Differential Input Resistance2)
IGOC
RI
-5
–
5
–
100
–
–
–
–
kΩ
–
5.3.21 Common Mode Input apacitance2) CCM
10
pF
10kHz
Data Sheet
21
Rev. 1.1, 2016-01-28
TLE7183QU
Electrical Characteristics - Current sense signal conditioning (cont’d)
VS = 5.5 to 20V, Tj = -40 to +150°C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.3.22 Common Mode Rejection Ratio at CMRR
80
100
–
db
–
DC
CMRR =
20*Log((Vout_diff/Vin_diff) *
(Vin_CM/Vout_CM))
5.3.23 Common Mode Suppression4) with CMS
CMS = 20*Log(Vout_CM/Vin_CM)
Freq =100kHz
–
–
db
VIN=360mV*
sin(2*π*freq*t);
Rs=500Ω;
Rfb=7500Ω;
VRI=1.65/2.5V
62
43
33
Freq = 1MHz
Freq = 10MHz
5.3.24 Slew Rate
dV/dt
AOL
3
10
–
–
V/µs
dB
Gain>= 5;
RL=1.0kΩ;
CL=500pF
5.3.25 Large Signal Open Loop Voltage
Gain (DC)
80
100
–
5.3.26 Unity Gain Bandwidth
5.3.27 Phase Margin 2)
GBW
10
–
20
50
–
–
MHz
°
RL=1kΩ; CL=100pF
ΦM
Gain>= 5;
RL=1kΩ; CL=100pF
5.3.28 Gain Margin 2)
5.3.29 Bandwidth
AM
–
12
–
–
–
db
RL=1kΩ; CL=100pF
BWG
1.6
MHz
Gain=15;
RL=1kΩ;
CL=500pF;
Rs=500Ω
5.3.30 Output Settle Time to 98% 1)
tset
–
1
1.8
µs
Gain=15;
RL=1kΩ;
CL=500pF;
0.3<VO< 4.8V;
Rs=500Ω
5.3.31 Output Rise Time 10% to 90% 1)
5.3.32 Output Fall Time 90% to 10%1)
tIrise
–
–
–
–
1
1
µs
µs
Gain=15;
RL=1kΩ;CL=500pF;
0.3<VO< 4.8V;
Rs=500Ω
tIfall
Gain=15;
RL=1kΩ;CL=500pF;
0.3<VO< 4.8V;
Rs=500Ω;
1) Input current and output amplifier characteristics:
"Output signal must be amplified and available at 2µs after input signal change (Gain 5...15)
2) Not subject to production test; specified by design
3) calculated out of 5.3.9, 5.3.10, 5.3.11 and 5.3.12
4) Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external
resistors.
Data Sheet
22
Rev. 1.1, 2016-01-28
TLE7183QU
5.4
Phase Voltage Feedback
The TLE7183QU incorporates a fast conversion of the phase voltages to logic signals. The threshold values are proportional
to VDH. The outputs are 5V push pull stages. If they are not used they can be left open.
5V
-
S
+
40% VDH
SHx
X_fb
VDH
R
+
-
60% VDH
3x voltage feedback
Figure 5
Block Diagram Phase Voltage Feedback
5.4.1
Electrical Characteristics
Electrical Characteristics - Phase Voltage Feedback
VS = 5.5 to 20V, Tj = -40 to +150°C, fPWM < 25kHz, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Low Level Threshold
High Level Threshold
VILfb
VIHfb
35
40
45
% of
VDH
VDH>5.5V
5.4.1
5.4.2
VSHX decreasing
55
60
65
% of
VDH
VDH>5.5V
VSHX decreasing
5.4.3
5.4.4
5.4.5
High Level Output Voltage of X_fb
Low Level Output Voltage of X_fb
VOHfb
VOLfb
tPDfb
4.0
-0.1
–
–
–
–
5.2
0.2
110
V
I= -0.5mA
I= 0.5mA
V
Propagation Delay Time incl. Rise or
Fall Time
ns
CLOAD<100pF
5.4.6
Matching of Propagation Delay Time
tdPDfb
–
–
30
ns
Data Sheet
23
Rev. 1.1, 2016-01-28
TLE7183QU
Application Description
6
Application Description
In the automotive sector there are more and more applications requiring high performance motor drives, such as
electro-hydraulic or electric power steering. In these applications 3 phase motors, synchronous and
asynchronous, are used, combining high output performance, low space requirements and high reliability.
VBAT=12V
RVS
10 Ω
CVS
4.7µF
to sub µC or
ASIC
RVdh
___
CH1
INH ENA2
ENA1
VDH
CCP1
VS
4.7µF
CC
1µF
CB
1000µF
CL1
CB1
RG
GH1
CCB1
4.7µF
CC
1µF
SH1
CB
1000µF
CH2
RG
CC
CCP2
4.7µF
GH2
SH2
1µF
CL2
CB2
CB
1000µF
RG
CCB2
4.7µF
GH3
SH3
U_fb
V_fb
TLE7183QU
W_fb
ERR1
ERR2
RG
GL1
SL1
IL1
___
IH1
µC
or
digital
ASIC
RG
GL2
SL2
IL2
___
IH2
IL3
___
IH3
RG
GL3
SL3
DT
RDT
VRO
5V
VRI
Rfb
5V
ISP
RS
RS
Shunt
VTHOC
VO
ISN
Rfb
ADC
GND
GND
TP
AGND
P-GND
Figure 6
Application Circuit
Note:This is a very simplified example of an application circuit. The function must be verified in the real application.
Data Sheet
24
Rev. 1.1, 2016-01-28
TLE7183QU
Application Description
6.1
Layout Guide Lines
Please refer also to the simplified application example.
•
•
•
Three separate bulk capacitors CB should be used - one per half bridge
Three separate ceramic capacitors CC should be used - one per half bridge
Each of the 3 bulk capacitors CB and each of the 3 ceramic capacitors CC should be assigned to one of the half
bridges and should be placed very close to it
•
•
The components within one half bridge should be placed close to each other: high side MOSFET, low side
MOSFET, bulk capacitor CB and ceramic capacitor CC (CB and CC are in parallel) and the shunt resistor form
a loop that should be as small and tight as possible. The traces should be short and wide
The three half bridges can be seperated but if there is one common GND referenced shunt resistor for the three
half bridges the sources of the three low side MOSFETs should be close to each other and close to the
common shunt resistor
•
•
•
VDH is the sense pin used for short circuit detection; VDH should be routed (via Rvdh) to the common point
of the drains of the high side MOSFETs to sense the voltage of the drain high side
CB2 is the buffer capacitor of charge pump 2; its negative terminal should be routed to the common point of
the drains of the high side MOSFETs as well - this connection should be low inductive / resistive
Additional R-C snubber circuits (R and C in series) can be placed to attenuate/suppress oscillations during
switching of the MOSFETs, there may be one or two snubber circuits per half bridge, R (several Ohm) and C
(several nF) must be low inductive in terms of routing and packaging (ceramic capacitors)
the exposed pad on the backside of the package should be connected to GND
•
6.2
Further Application Information
•
For further information you may contact http://www.infineon.com/
Data Sheet
25
Rev. 1.1, 2016-01-28
TLE7183QU
Package Outlines
7
Package Outlines
11 x 0.5 = 5.5
12°
H
0.5
12°
0.2 MIN.
0.08
48x
C
C
SEATING PLANE COPLANARITY
0.15
0.05
0.6
0.22
M
0.08
A-B D C 48x
(1)
9
0.2 A-B D 48x
0.2 A-B D H 4x
1)
7
52)
D
Exposed Diepad
A
B
48
1
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Exposed pad for soldering purpose
Figure 7
PG-TQFP-48
Green Product
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Dimensions in mm
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet 26
Rev. 1.1, 2016-01-28
TLE7183QU
Revision History
8
Revision History
Version
Date
Changes
1.1
2016-01-28
- package adjustments
- replaced misleading term ERRx with ERRx
1.0
2011-09-09
Data Sheet
Data Sheet
27
Rev. 1.1, 2016-01-28
Edition 2016-01-28
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2016.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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