TLE7233EMXUMA1 [INFINEON]
Buffer/Inverter Based Peripheral Driver, 0.5A, PDSO24, SSOP-24;
| 型号： | TLE7233EMXUMA1 |
| 厂家： | 
Infineon |
| 描述： | Buffer/Inverter Based Peripheral Driver, 0.5A, PDSO24, SSOP-24 驱动 光电二极管 接口集成电路 |
| 文件： | 总33页 (文件大小：933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.2, May 2014
TLE7233EM
SPIDER - 4 channel low-side driver with limp home
Automotive Power
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Voltage and current naming definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
5
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
6.2
6.3
6.4
7
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1
7.2
7.3
7.4
8
8.1
8.2
Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Open Load Diagnosis timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical Characteristics Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1
9.2
9.3
9.4
9.5
10
11
12
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Data Sheet
2
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
TLE7233EM
1
Overview
Features
•
•
•
•
•
•
•
•
•
4 channel low-side relay driver
8-bit SPI for diagnostics and control
SPI providing Daisy Chain Capability
Limp Home functionality
Very wide range for digital Supply Voltage
Four input pins provide flexible and straightforward PWM operation
Stable behavior at Under Voltage
Green Product (RoHS compliant)
AEC Qualified
PG-SSOP-24-4
Table 1
Product Summary
Digital supply voltage
VDD
3.0 V ... 5.5 V
4.5 V ... 5.5 V
2.2 Ω
Analog supply voltage
VDDA
RDS(ON)
ON State resistance at Tj = 150°C for each channel
Nominal load current
ID (nom,min) 470 mA
ID (OVL,max) 950 mA
ID (STB,max) 1 µA
Overload switch off threshold
Output leakage current per channel at 25 °C
Drain to Source clamping voltage
SPI clock frequency
VDS(AZ)
fSCLK
41 V
5 MHz
Diagnostic Features
•
•
•
•
Latched diagnostic information via SPI
Over temperature monitoring
Over load detection in ON state
Open load detection in OFF state
Type
Package
Marking
TLE7233EM
TLE7233EM
PG-SSOP-24-4
Data Sheet
3
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Overview
Protection Functions
•
•
•
•
Short circuit
Over load
Over temperature
Electrostatic discharge (ESD)
Application
•
•
All types of resistive, inductive and capacitive loads
Especially designed for driving relays in automotive applications
Description
The TLE7233EM is a four channel low-side relay switch (1 Ω per channel) in PG-SSOP-24-4 package providing
embedded protective functions. It is especially designed as a relay driver for automotive applications. The 8 bit
serial peripheral interface (SPI) is provided for control and diagnostics of the device and the loads. The SPI
interface provides daisy-chain capability.
The TLE7233EM is equipped with four input pins that can be individually routed to the output control of their
corresponding channel and therefore offer complete flexibility in design and PCB layout. The input multiplexer is
controlled via SPI.
A limp home pin (LHI) provides a simple use of the input pins; this enables a direct connection between the input
pins and their corresponding outputs. The limp home function works also with VDDA only in order to ensure
functionality even without the digital supply.
The device provides many diagnostics of the load enabling both open load and short circuit detection. The SPI
diagnostic bits indicate any eventual latched fault condition.
Each output stage is protected against short circuit. In case of over load, the affected channel switches off.
Temperature sensors are available for each channel in order to protect the device against over temperature.
The power transistors are made of N-channel vertical power MOSFETs. The inputs are CMOS compatible and are
referenced to Ground. The device is monolithically integrated in Smart Power Technology.
Data Sheet
4
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Block Diagram
2
Block Diagram
VDD
VDDA
RST
OUT0
OUT1
OUT2
OUT3
IN0
IN1
input logic
input register
SPI
IN2
IN3
temperature
sensor
control,
diagnostic
and
protective
functions
LHI
short circuit
detection
CS
SCLK
SI
gate
control
SO
open load
detection
diagnosis register
GND
Overview_EM.emf
Figure 1
Block Diagram TLE7233EM
Data Sheet
5
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Block Diagram
2.1
Voltage and current naming definition
Following figure shows all the terms used in this data sheet, with associated convention for positive values.
IDDA
VBAT
VDDA
VDD
RST
IN3
IDD
IRST
IIN 3
IIN 2
IIN 1
IIN 0
ILHI
ICS
VDDA
VDD
VRST
VIN3
VIN2
VIN 1
VIN0
VLHI
VCS
VSCLK
IN2
IN1
ID0
ID1
ID2
ID3
IN0
OUT0
OUT1
OUT2
OUT3
VDS0
LHI
VDS1
VDS2
CS
ISCLK
ISI
SCLK
SI
VDS3
ISO
VSI
SO
GND
IGND
VSO
Terms_EM.emf
Figure 2
Terms
In all tables of electrical characteristics is valid: channel related symbols without channel number are valid for each
channel separately (e.g. VDS specification is valid for VDS0 … VDS3).
All SPI register bits are marked as follows: PARAMETER(e.g. IN0). In SPI register description, the values in bold
letters (e.g. 0) are default values.
Data Sheet
6
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
(top view )
n.c.
n.c.
1
24
n.c.
SCLK
SO
2
23
22
21
20
19
18
17
16
15
14
13
OUT3
OUT2
VDD
GND
VDDA
LHI
3
4
SI
5
IN3
GND
IN2
IN1
IN0
CS
6
25
SUB
7
8
9
OUT1
OUT0
n.c.
10
11
12
exposed pad
(bottom )
RST
n.c.
n.c.
PG -SSOP -24.emf
Figure 3
Pin Configuration
3.2
Pin Definitions and Functions
1)
Pin
Symbol
I/O
Function
Power Supply
5
VDD
VDDA
GND
SUB
-
-
-
-
Digital Supply Voltage; Connected to 5 V Voltage with Reverse
protection Diode and Filter against EMC
7
Analog Supply Voltage; Positive supply voltage for power switches gate
control
6,19
25
Ground; common ground for digital, analog and power. Both pins need to
be connected to ground
Substrate; shorted to die pad, must be used for thermal connection and
connected to ground
Power Stages
10
OUT0
OUT1
OUT2
OUT3
O
O
O
O
Output Channel 0; Drain of power transistor channel 0
Output Channel 1; Drain of power transistor channel 1
Output Channel 2; Drain of power transistor channel 2
Output Channel 3; Drain of power transistor channel 3
9
4
3
Inputs
Data Sheet
7
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Pin Configuration
1)
Pin
16
Symbol
IN0
I/O
Function
I
I
I
I
I
I
PD Control Input; Digital input 3.3 V or 5 V. In case of not used keep open.
PD Control Input; Digital input 3.3 V or 5 V. In case of not used keep open.
PD Control Input; Digital input 3.3 V or 5 V. In case of not used keep open.
PD Control Input; Digital input 3.3 V logic. In case of not used keep open.
PD Limp Home; Digital input 3.3 V or 5 V. In case of not used keep open.
PD Reset input pin; Digital input 3.3 V or 5 V. Low active
17
IN1
18
IN2
20
IN3
8
LHI
14
RST
SPI
15
CS
I
PU SPI Chip Select; Digital input 3.3 V or 5 V. Low active
PD Serial Clock; Digital input 3.3 V or 5 V.
PD Serial Data In; Digital input 3.3 V or 5 V.
Serial Data Out; Digital input 3.3 V or 5 V.
23
SCLK
SI
I
21
I
22
SO
O
Others
1,2,11, n.c.
12,13,
-
not connected; pin not used
24
1) O: Output, I: Input,
PD: pull-down resistor integrated,
PU pull-up resistor integrated
Data Sheet
8
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
TJ = -40 °C to +150 °C; VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V.
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Power Supply
4.1.1
4.1.2
Digital supply voltage
Analog supply voltage
VDD
-0.3
-0.3
5.5
5.5
V
V
–
–
VDDA
Power Stages
4.1.3
4.1.4
Load current
ID
-0.5
–
0.5
36
A
V
–
–
Output voltage for short circuit protection VD
(single pulse)
4.1.5
4.1.6
Voltage at power transistor
VDS
EAS
–
41
V
active clamped
2)
mJ
–
Maximum energy dissipation one
channel
single pulse
–
–
65
30
T
I
J(0) = 85 °C
D(0) = 0.35 A
J(0) = 150 °C
D(0) = 0.25 A
J(0) = 150 °C
D(0) = 0.25 A
J(0) = 150 °C
D(0) = 0.17 A
single pulse
T
I
EAR
T
I
repetitive (1 · 104 cycles)
repetitive (1 · 106 cycles)
–
–
18
13
T
I
Logic Pins
4.1.7
Voltage at input pins
VIN0..3
VLHI
VRST
VCS
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
5.5
5.5
V
V
V
V
V
V
V
–
–
–
–
–
–
–
4.1.8
Voltage at LHI pin
3)
3)
3)
3)
3)
4.1.9
Voltage at reset pin
V
V
V
V
V
DD + 0.3
4.1.10
4.1.11
4.1.12
4.1.13
Voltage at chip select pin
Voltage at serial clock pin
Voltage at serial input pin
Voltage at serial output pin
DD + 0.3
DD + 0.3
DD + 0.3
DD + 0.3
VSCLK
VSI
VSO
Temperatures
4.1.14
4.1.15
Junction Temperature during operation TJ
-40
-55
150
150
°C
°C
–
–
Storage Temperature
TSTG
Data Sheet
9
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
General Product Characteristics
Absolute Maximum Ratings (cont’d)1)
TJ = -40 °C to +150 °C; VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V.
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
ESD Susceptibility
4.1.16 ESD Resistivity
VESD
kV
HBM4)
OUTn vs. GND
all other pins
-4
-2
4
2
1) Not subject to production test, specified by design.
2) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse
3) VDD + 0.3 V < 5.5 V
4) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001-2010
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
3.0
4.5
–
Max.
5.5
4.2.1
4.2.2
4.2.3
Digital supply voltage
Analog supply voltage
VDD
V
–
–
–
VDDA
5.5
V
Digital supply current all channels IDD(ON)
100
µA
ON
4.2.4
4.2.5
Analog supply current all channels IDDA(ON)
ON
–
3
–
mA
µs
–
Analog supply turn-ON time
tDDA(ON)
15
V
DDA = 0V to 5V
(linear)
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
10
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
General Product Characteristics
4.3
Thermal Resistance
Note:This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
–
Max.
1) 2)
4.3.6
4.3.7
4.3.8
4.3.9
Junction to Case, bottom
Junction to Case, top
RthJC,back
RthJC,top
RthJPin
–
–
–
–
4
K/W
K/W
K/W
K/W
–
1) 2)
–
35
15
–
–
1) 2)
Junction to Pin (6,7,18 or 19)
–
–
1) 3)
Junction to Ambient
(1s0p, min. footprint)
RthJA,min
95
–
1) 4)
4.3.10 Junction to Ambient
(1s0p + 300mm2 Cu)
RthJA,300
RthJA,600
RthJA,2s2p
–
–
–
52
45
33
–
–
–
K/W
K/W
K/W
–
1) 5)
4.3.11 Junction to Ambient
(1s0p + 600mm2 Cu)
–
1) 6)
4.3.12 Junction to Ambient (2s2p)
–
1) Not test subject to production test, specified by design
2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).
TA = 85 °C. Ch0 to Ch3 are dissipating 1 W power (0.25 W each).
3) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70 µm thickness.
TA = 85 °C. Ch0 to Ch3 are dissipating 1 W power (0.25 W each).
4) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 300 mm2
and 70 µm thickness. TA = 85 °C. Ch0 to Ch3 are dissipating 1 W power (0.25 W each).
5) Specified RthJA value is according to JEDEC JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600 mm2
and 70 µm thickness. TA = 85°C. Ch0 to Ch3 are dissipating 1 W power (0.25 W each).
6) Specified RthJA value is according to JEDEC JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
TA = 85°C. Ch0 to Ch3 are dissipating 1 W power (0.25 W each).
Data Sheet
11
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Power Supply
5
Power Supply
The TLE7233EM is supplied by two power supply lines VDD and VDDA. The digital power supply line VDD is designed
to be functional at a very wide voltage range. The analog power supply VDDA supports 5 V supply.
Power-on reset functions have been implemented for both supply lines. After start-up of the power supply, all SPI
registers are reset to their default values and the device remains in idle mode. Capacitors between VDD and GND
pins, and VDDA and GND pins are recommended.
A reset pin is available. At low logic level at this pin, all registers are set to their default values and the quiescent
supply currents are minimized.
The VDD supply line is used for the I/O buffer circuits of the SPI pins, therefore the voltage on the SO pin is always
related to this supply voltage. A capacitor between VDD and and GND pin is recommended.
To enable the Daisy chain functionality it is necessary to have VDD and VDDA in the specified functional range.
The device provides a sleep mode to minimize current consumption, which also resets the register banks. It is
controlled by a low active reset pin (RST) which disables the device and minimize the current consumption. The
table below gives an overview of the different power modes.
Table 2
Power mode State Description
Power modes1)
RST
VDD
VDDA
SCLK LHI
(low active)
SLEEP
IDLE
Device at minimum current consumption
low
X
X
0 Hz
0 Hz
low
low
Device operational, all channels OFF no
diagnosis activated
high
ON
ON
LIMP HOME Device in Limp home mode
ON
X
X
ON
ON
X
high
Device operational with enabled channels and high
diagnostic currents active
ON
5 MHz low
(max)
1) low: pin input is digital low,
high: pin input is digital high,
X: pin state don’t care,
ON: voltage on this analog supply pin is in the specified functional range
Data Sheet
12
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Power Supply
5.1
Limp Home Mode
The TLE7233EM offers the capability of driving dedicated channels during eventual fail-safe operation of the
system. This limp home mode is activated by a high signal at pin LHI. In this mode, the SPI registers are reset and
the input pins are directly routed to their corresponding channels, see Table 3 for details.
Furthermore, the SPI is ignored and all input pins are referred to VDDA in order to ensure a defined operation mode
if the digital supply or the microcontroller fail.
A high signal on LHI overrides a Reset signal on RST. In case of a limp home during sleep the device will therefore
wake up and enter the limp home mode.
During Limp home mode any SPI transmission will receive a TER flag.
After limp home operation all registers are reset and the device enters in sleep mode following low logic RST state,
or returns to ON state (all channels OFF with diagnostic currents active). Next SPI transmission will receive a TER
Flag.
Input
controlled
Output
IN0
IN1
IN2
IN3
OUT0
OUT1
OUT2
OUT3
Table 3
Routing during limp home mode
Data Sheet
13
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Power Stages
6
Power Stages
The TLE7233EM is a four channel low-side relay switch.
The power stages are made of N-channel vertical power MOSFET transistors.
6.1
Input Circuit
The TLE7233EM has four input pins, which can be configured to be used for control of the output stages. The INn
parameter of the SPI provide the following operation modes (see Figure 5):
•
channel is in off mode without diagnosis
(if all channels are programmed to this mode, the device goes into idle mode)
channel is switched according to signal level at input pin INn
channel is switched on with active diagnosis
•
•
•
channel is switched off with active diagnosis
Figure 4 shows the input circuit of TLE7233EM.
IN
IIN
InputStage.emf
Figure 4
Input signal conditioning circuit on all input and limp home pins
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses. After power-on reset, the device enters idle mode.
Data Sheet
14
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Power Stages
Channel 0
OFF
IN0
&
ON
OFF
D0
INx0
LHI
Channel 1
OFF
IN1
&
ON
OFF
D1
INx1
INx2
LHI
LHI
LHI
OFF
Channel 2
IN2
&
ON
OFF
D2
Channel 3
OFF
IN3
&
ON
OFF
D3
INx3
InputLogic_EM.emf
Figure 5
Input Multiplexer
6.2
Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance
intends to continue driving the current. The voltage clamping is necessary to prevent destruction of the device,
see Figure 6 for details. Nevertheless, the maximum allowed load inductance is limited.
VBAT
L,
RL
ID
OUT
VDS
VDS(CL)
GND
OutputClamp.emf
Figure 6
Output Clamp Implementation
Data Sheet
15
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Power Stages
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE7233EM.
This energy can be calculated with following equation:
V
BAT – VDS(CL)
⎛
⎞
RL ⋅ ID
L
RL
--------------------------------------
------
E = VDS(CL)
⋅
⋅ ln 1 – -------------------------------------- + ID
⋅
⎜
⎟
RL
V
BAT – VDS(CL)
⎝
⎠
Following equation simplifies under the assumption of RL = 0:
⎛
⎞
⎟
⎠
VBAT
2
1
2
--
E = LID ⋅ 1 – --------------------------------------
⎜
V
BAT – VDS(CL)
⎝
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
6.3
Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the IN bits of the serial peripheral
interface SPI. The switching times tON and tOFF are designed equally.
CS
SPI: ON
SPI: OFF
t
tON
tOFF
VDS
80%
20%
t
SwitchOn.emf
Figure 7
Switching a Resistive Load
In input direct drive mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to
SPI OFF command respectively. Please refer to Chapter 9.3 for details on operation modes.
The listed switching times are not valid, when switching to or from stand-by mode.
Data Sheet
16
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Power Stages
6.4
Electrical Characteristics Power Stages
VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V, TJ = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, TJ = 25 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Power Supply
6.4.1
6.4.2
Digital supply voltage
VDD
3.0
–
–
–
5.5
V
–
Digital supply current all channels IDD(ON)
ON
100
µA
V
DD = VDDA = 5 V
VRST = VCS = VDD
SCLK = 0 V
VIN = 0 V
fSCLK = 0 Hz
V
6.4.3
6.4.4
Digital supply idle current
Digital supply sleep current
IDD(idle)
–
–
20
µA
µA
V
RST = VCS = high
IDD(sleep)
V
RST = 0 V
–
–
–
–
–
–
1
2
5
TJ = 25 °C 1)
TJ = 85 °C 1)
TJ = 150 °C
6.4.5
Digital power-on reset threshold
voltage
VDD(PO)
VDDA
–
–
3.0
V
–
6.4.6
6.4.7
Analog supply voltage
4.5
–
–
–
5.5
3
V
–
–
Analog supply current all channels IDDA(ON)
mA
ON
6.4.8
6.4.9
Analog supply idle current
IDDA(idle)
µA
V
CS = VDD
VSI = 0 V
SCLK = 0 V
V
–
–
–
–
–
–
25
50
100
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
Analog supply sleep current
IDDA(sleep)
µA
V
V
V
CS = VDD
RST = 0 V
–
–
–
–
–
–
1
3
5
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
6.4.10 Analog power-on reset threshold
voltage
VDDA(PO)
–
–
4.5
–
Output Characteristics
6.4.11 On-State resistance per channel
RDS(ON)
Ω
ID = 250 mA
TJ = 25 °C 1)
TJ = 150 °C
–
–
1.0
2.0
–
2.2
2)
6.4.12 Nominal load current
ID(nom)
470
500
–
mA
–
Data Sheet
17
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Power Stages
VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V, TJ = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, TJ = 25 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
6.4.13 Output leakage current
(per channel)
ID(OFF)
µA
VDS = 13.5 V
–
–
–
–
–
–
1
2
5
TJ = 25 °C 1)
TJ = 85 °C 1)
TJ = 150 °C
6.4.14 Output clamping voltage
VDS(CL)
41
–
54
V
–
Input Pin Characteristics
6.4.15 L level of pin
IN & LHI
VIN(L)
VIN(H)
0
–
0.7
5.5
80
V
–
–
6.4.16 H level of pin
IN & LHI
2.0
3
–
V
6.4.17 L-input pull-down current through IIN(L)
12
40
–
µA
µA
–
V
DD = 5 V 1)
VIN = 0.6 V
VDD = 5 V
pin
6.4.18 H-input pull-down current through IIN(H)
10
0
80
pin
VIN = 5 V
6.4.19 L level of pin RST
6.4.20 H level of pin RST
VRST(L)
VRST(H)
0.2*
VDD
–
0.4*
–
VDD
–
–
VDD
6.4.21 L-input pull-down current through IRST(L)
3
12
40
80
µA
µA
V
V
DD = 5 V 1)
RST = 0.6 V
pin RST
6.4.22 H-input pull-down current through IRST(H)
10
80
V
V
DD = 5 V
RST = 5 V
pin RST
Timings
6.4.23 Sleep wake-up time
6.4.24 Reset duration
twu(sleep)
tRST(L)
tON
–
1
5
–
–
–
200
–
µs
µs
µs
–
–
V
6.4.25 Turn-on time
60
BAT = 13.5 V
VDS = 20% VBAT
ID = 250 mA,
resistive load
6.4.26 Turn-off time
tOFF
10
–
60
µs
VBAT = 13.5 V
VDS = 80% VBAT
ID = 250 mA,
resistive load
1) Not subject to production test, specified by design
2) calculated value based on following parameters:
all channels on with equal load current, RDS(ON) = RDS(ON,150°C) , TA = 85 °C, TJ,max = 150 °C, Rth = RthJA(2s2p)
Data Sheet
18
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Protection Functions
7
Protection Functions
Note:The device provides embedded protective functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in this data sheet. Fault conditions are considered as
“outside” normal operating range. Protection functions are not designed for continuous repetitive operation.
7.1
Over Load Protection
The TLE7233EM is protected against over load or short circuit of the load. After time tOFF(OVL), the over loaded
channel nswitches off and therefore the corresponding diagnostics flag Dnis set. The channel can be switched
on after clearing the diagnostics flag as described in chapter 8. Please refer to Figure 8 for details.
IN
t
tOFF(OVL)
ID0
ID0 ( OVL)
t
IN0 = 01b
D0 = 0b
IN0 = 00b
D0 = 0b
IN0 = 01b
D0 = 1b
OverLoad .emf
Figure 8
Shut Down at Over Load on channel 0
7.2
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel nto switch off to prevent destruction. Then
the according diagnostics flag Dnis set. The channel can be switched on after clearing the diagnosis flag and a
junction temperature decrease of ΔTJ. Please refer to Chapter 8 for information on diagnostics features.
7.3
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode of the power transistor causes increased power dissipation.
The reverse current through the intrinsic body diode of the power transistor has to be limited by the connected
load. The VDD and VDDA supply pins must be externally protected against reverse polarity. The over temperature
and over load protection are not active during reverse polarity.
Data Sheet
19
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Protection Functions
7.4
Electrical Characteristics Protection
VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V, TJ = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, TJ = 25 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Over Load Protection
7.4.1
7.4.2
Over load detection current
Over load shut-down delay time
ID(OVL)
0.5
5
–
–
0.95
60
A
–
–
tOFF(OVL)
µs
Over Temperature Protection
7.4.3
7.4.4
Thermal shut down temperature
Thermal hysteresis
TJ(SC)
150
–
1701)
10
–
–
°C
–
1)
ΔTJ
K
–
1) Not subject to production test, specified by design
Data Sheet
20
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Diagnostic Features
8
Diagnostic Features
The SPI of TLE7233EM provides diagnosis information about the device and about the load. The diagnosis
information of the protective functions of channel nis latched in the diagnosis flag Dn. The open load diagnosis of
channel nis latched in the diagnosis flag OLn. Both flags are cleared by INn= 00B which disables the diagnosis
current ID(PD) (a small pull down current) as well.
Following table shows possible failure modes and the according protective and diagnostic action.
j
Failure Mode
Comment
Open Load
Diagnosis, when channel nis switched on:
or short circuit to GND INn= 01B: if input pin is high: none
INn= 10B: none
Diagnosis, when channel nis switched off:
INn= 00B: none, diagnosis flags are cleared and the diagnosis current is switched off
INn= 01B: if input pin is low, according to voltage at the output pin, the flag OLnis set
after time td(OL)
INn= 11B: according to voltage level at the output pin, the flag OLnis set after time td(OL)
Over temperature
When over temperature occurs, the affected channel nis switched off. The according
diagnosis flag Dnis set.
The diagnosis flags are latched until they have been cleared by INn= 00B. The over
temperature detection is active in ON-state as well as OFF-state.
Over Load
(Short Circuit)
When over load is detected at channel n, the affected channel is switched off after time
tOFF(OVL) and the dedicated diagnosis flag Dnis set.
The diagnosis flags are latched until they have been cleared by INn= 00B.
8.1
Open Load Diagnosis timing
The TLE7233EM offers an open load diagnosis for each channel in OFF mode.
The time td(OL) is applied to filter short time events.
Open Load occures here
Open Load occures here
IN
IN
VDS
t
t
t
VDS
VDS(OL)
VDS(OL)
td(OL)
td(OL)
t
OLn
=
1b
OLn = 1b
OpenLoad.emf
Figure 9
Open Load timing
Data Sheet
21
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Diagnostic Features
8.2
Electrical Characteristics Diagnostic
VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V, TJ = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, TJ = 25 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
OFF State Diagnosis
8.2.1
8.2.2
8.2.3
Open load detection threshold
voltage
VDS(OL)
1.0
30
30
–
–
–
2.5
V
–
Output pull-down diagnosis current ID(PD)
per channel
100
200
µA
µs
V
DS = 13.5 V
Open load diagnosis delay time
td(OL)
–
ON State Diagnosis
8.2.4
8.2.5
Over load detection current
Over load detection delay time
ID(OVL)
0.5
5
–
–
0.95
60
A
–
–
tOFF(OVL)
µs
Data Sheet
22
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Serial Peripheral Interface (SPI)
9
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
CS MSB
MSB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
SO
SI
CS
SCLK
time
SPI.emf
Figure 10 Serial Peripheral Interface
The SPI protocol is described in Chapter 9.3. It is reset to the default values after power-on reset.
9.1
SPI Signal Description
CS - Chip Select:
The system micro controller selects the TLE7233EM by means of the CS pin. Whenever the pin is in low state,
data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO
is forced into a high impedance state.
CS High to Low transition:
•
•
The diagnosis information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. The transmission error flag is set after any kind of reset, so a reset
between two SPI commands is indicated. For details, please refer to Figure 11. This information stays
available to the first rising edge of SCLK.
Data Sheet
23
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Serial Peripheral Interface (SPI)
TER
SI
SO
OR
1
0
SO
S
SI
SPI
CS
SCLK
S
TER .emf
Figure 11 Transmission Error Flag on SO Line
CS Low to High transition:
Data from shift register is transferred into the input matrix register only, when after the falling edge of CS exactly
a multiple (1, 2, 3, …) of eight SCLK signals have been detected.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. Please refer to Chapter 9.3 for further information.
SO - Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to
Chapter 9.3 for further information.
9.2
Daisy Chain Capability
The SPI of TLE7233EM provides daisy chain capability. In this configuration several devices are activated by the
same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 12),
which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and
MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each
device in the chain.
Data Sheet
24
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Serial Peripheral Interface (SPI)
device 1
SPI
device 2
SPI
device 3
SI
SO SI
SO SI
SO
MO
SPI
MI
MCS
MCLK
SPI_DasyChain.emf
Figure 12 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the CS line must transit from low to high to make the device accept the transferred data. In
daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using three
devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must
transit from low to high (see Figure 13).
SO device 3
SI device 3
SO device 2
SI device 2
SO device 1
SI device 1
MI
MO
MCS
MCLK
time
SPI_DasyChain2.emf
Figure 13 Data Transfer in Daisy Chain Configuration
9.3
SPI Protocol
The SPI protocol of the TLE7233EM provides two registers. The input register and the diagnosis register. The
diagnosis register contains four pairs of diagnosis flags, the input register contains the input multiplexer
configuration. After power-on reset, all register bits are cleared to 0.
SI
7
6
5
4
3
2
1
0
IN3
IN2
IN1
IN0
Data Sheet
25
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Serial Peripheral Interface (SPI)
Field
Bits
Type Description
Input Register Channel n
00B Idle Mode:
Fast channel switched off.
INn
(n = 3-0)
7:6,
5:4,
3:2,
1:0
W
Diagnosis flags are cleared.
Diagnosis current is disabled.
01B Input Direct drive mode:
Channel is switched according to signal at corresponding input pin.
Diagnosis current is enabled in OFF-state. See Figure 5 for details.
10B ON Mode:
Channel is switched on.
Diagnosis current is enabled.
11B OFF Mode:
Channel is switched off.
Diagnosis current is enabled.
Data Sheet
26
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Serial Peripheral Interface (SPI)
SO
Reset Value: 100H
CS1)
7
6
5
4
3
2
1
0
TER
OL3
D3
OL2
D2
OL1
D1
OL0
D0
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
Field
Bits
Type Description
R Transmission Error
TER
CS
0
1
Previous transmission was successful (modulo 8 clocks received).
Previous transmission failed or first transmission after reset.
OLn
(n = 3-0)
7, 5, 3, R
1
Open Load Flag of channel n
0
Normal operation.
1
Open load has occurred in OFF state.
Dn
(n = 3-0)
6, 4, 2, R
0
Diagnosis Flag of channel n
0
Normal operation.
1
Over load or over temperature switch off has occurred in ON state.
9.4
Timing Diagrams
tCS(lead)
tCS(lag)
tCS(td)
tSCLK(P )
0.5VDD
0.2VDD
CS
tSCLK (H)
tSCLK (L)
0.5VDD
0.2VDD
SCLK
SI
tSI (s u)
tSI (h)
0.5VDD
0.2VDD
tSO(en)
tSO(v )
tSO (dis )
0.5VDD
0.2VDD
SO
Figure 14 Timing Diagram
Data Sheet
27
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Serial Peripheral Interface (SPI)
9.5
Electrical Characteristics SPI
VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V, TJ = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, TJ = 25 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Input Characteristics (CS, SCLK, SI)
9.5.1
L level of pin
CS
SCLK
SI
0
–
0.2*
VDD
–
–
–
VCS(L)
VSCLK(L)
VSI(L)
9.5.2
H level of pin
0.5*VDD
–
VDD
–
CS
SCLK
SI
VCS(H)
VSCLK(H)
VSI(H)
9.5.3
9.5.4
L-input pull-up current through CS ICS(L)
H-input pull-up current through CS ICS(H)
5
3
17
15
40
40
µA
µA
V
CS = 0 V
CS = 2 V
1)
V
1)
9.5.5
L-input pull-down current through
pin
3
12
80
µA
SCLK
SI
ISCLK(L)
ISI(L)
V
SCLK = 0.6 V
VSI = 0.6 V
9.5.6
H-input pull-down current through
10
40
80
µA
pin
SCLK
SI
ISCLK(H)
ISI(H)
V
SCLK = 5 V
VSI = 5 V
Output Characteristics (SO)
9.5.7
9.5.8
L level output voltage
H level output voltage
VSO(L)
VSO(H)
0
–
–
0.4
V
–
I
I
SO = -2 mA
VDD-
VDD
SO = 1.5 mA
0.5 V
9.5.9
Output tristate leakage current
ISO(OFF)
-10
–
10
µA
V
CS = VDD
Timings
9.5.10 Serial clock frequency
9.5.11 Serial clock period
9.5.12 Serial clock high time
9.5.13 Serial clock low time
fSCLK
0
–
–
–
–
–
5
–
–
–
–
MHz
ns
–
–
–
–
–
tSCLK(P)
tSCLK(H)
tSCLK(L)
tCS(lead)
200
50
50
250
ns
ns
9.5.14 Enable lead time (falling CS to
rising SCLK)
ns
9.5.15 Enable lag time (falling SCLK to
rising CS)
tCS(lag)
tCS(td)
250
250
20
–
–
–
–
–
–
ns
ns
ns
–
–
–
9.5.16 Transfer delay time (rising CS to
falling CS)
9.5.17 Data setup time (required time SI to tSI(su)
falling SCLK)
Data Sheet
28
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Serial Peripheral Interface (SPI)
VDD = 3.0 V to VDDA, VDDA = 4.5 V to 5.5 V, TJ = -40 °C to +150 °C
All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
typical values: VDD = 5.0 V, VDDA = 5.0 V, TJ = 25 °C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
20
–
Typ.
Max.
9.5.18 Data hold time (falling SCLK to SI) tSI(h)
–
–
–
ns
ns
–
9.5.19 Output enable time (falling CS to
SO valid)
tSO(en)
tSO(dis)
tSO(v)
200
CL = 50 pF 1)
9.5.20 Output disable time (rising CS to
SO tri-state)
–
–
–
–
200
100
ns
ns
CL = 50 pF 1)
CL = 50 pF 1)
9.5.21 Output data valid time with
capacitive load
1) Not subject to production test, specified by design.
Data Sheet
29
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Application Information
10
Application Information
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 15 shows a simplified application circuit. VDDA and VDD need to be reverse protected. Also the Resistors at
the digital pins are for reverse polarity protection.
VBAT
VDDA
C1
VDD
RST
IN3
IN2
IN1
IN0
LHI
CS
VDDA
VDD
C2
Loads
R10 C3
Discrete
Limp
home
or PWM
signal
R9
R8
R7
R6
R5
R4
R3
circuit
OUT0
OUT1
OUT2
OUT3
Watch
dog
SCLK
SI
SPI uC
R2
R1
SO
GND
Application _EM.emf
Figure 15 Application Diagram
Note:This is a very simplified example of an application circuit. The function must be verified in the real application.
C1,C2,C3 are recommended to be 4.7 nF and all Resistors can be 1 kΩ.
For further information you may contact http://www.infineon.com/
Data Sheet
30
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Package Outlines
11
Package Outlines
0.35 x 45˚
2x
1)
±0.1
3.9
0.1 C D
0.08
Seating Plane
C
C
0.65
2)
±0.05
±0.2
0.25
6
M
M
0.2
D
0.2
C A-B D 24x
D
Bottom View
A
24
1
12
13
1
12
24
13
B
±0.25
6.4
0.1 C A-B 2x
±0.1
8.65
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-4-PO V01
Figure 16 PG-SSOP-24-4 (Plastic Green Shrink Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Dimensions in mm
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet 31
Rev. 1.2, 2014-05-09
SPI Driver for Enhanced Relay Control
SPIDER - TLE7233EM
Revision History
12
Revision History
Version
Date
Changes
Page 7, VDDA , description added
Rev. 1.2
2014-05-09
Page 10, 4.2.3 IDD(ON) max. limit changed from 0.5 mA to 100 µA
Page 10, 4.2.4 IDDA(ON) max. limit changed from 5 mA to 3 mA
Page 14, 6.1 cross references to Figure 4 and Figure 5 changed
Page 17, 6.4.2 IDD(ON) max. limit changed from 0.5 mA to 100 µA
Page 17, 6.4.3 IDD(idle) max. limit changed from 40 µA to 20 µA at TJ = 150 °C
Page 17, 6.4.4 IDD(sleep) max. limit changed from 5 µA to 1 µA at TJ = 25 °C
Page 17, 6.4.4 IDD(sleep) max. limit changed from 5 µA to 2 µA at TJ = 85 °C
Page 17, 6.4.4 IDD(sleep) max. limit changed from 20 µA to 5 µA at TJ = 150 °C
Page 17, 6.4.7 IDDA(ON) max. limit changed from 5 mA to 3 mA
Page 17, 6.4.8 IDDA(idle) max. limit changed from 25 µA to 50 µA at TJ = 85 °C
Page 17, 6.4.8 IDDA(idle) max. limit changed from 25 µA to 100 µA at TJ = 150 °C
Page 17, 6.4.9 IDDA(sleep) max. limit changed from 5 µA to 1 µA at TJ = 25 °C
Page 17, 6.4.9 IDDA(sleep) max. limit changed from 5 µA to 3 µA at TJ = 85 °C
Page 17, 6.4.9 IDDA(sleep) max. limit changed from 20 µA to 5 µA at TJ = 150 °C
Page 18, 6.4.14 VDS(CL) max. limit changed from 52 V to 54 V and footnote 3)
removed
Page 18, 6.4.15 VIN(L) max. limit changed from 0.9 V to 0.7 V
Page 18, 6.4.16 VIN(H) min. limit changed from 2.2 V to 2.0 V
Page 18, 6.4.25 tON min. limit added
Page 18, 6.4.26 tOFF min. limit added
Figure 9 “Open Load timing” on Page 21 updated
Page 22, 8.2.2 ID(PD), min. limit added
Figure 14 “Timing Diagram” on Page 27 updated
Rev. 1.1
Rev. 1.0
2012-03-27
2012-02-29
Figure 2 LHI pin added
4.3 RthJSP changed to RthJC
4.3 JEDEC JESD51-2,-3 changed to JEDEC JESD51-2,-7
6.4 IDD(sleep) changed to IDDA(sleep)
6.4 IL changed to ID
Datasheet released
Data Sheet
32
Rev. 1.2, 2014-05-09
Edition 2014-05-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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