TLE7368 [INFINEON]
Next Generation Micro Controller Supply; 下一代微控制器供应
| 型号： | TLE7368 |
| 厂家： | 
Infineon |
| 描述： | Next Generation Micro Controller Supply |
| 文件： | 总39页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.1, November 2007
TLE7368
Next Generation Micro Controller Supply
Automotive Power
TLE7368
Table of Contents
Table of Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions TLE7368G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
5
Detailed Internal Circuits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Buck Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Buck Regulator Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High Side Driver Supply and 100% Duty Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electromagnetic Emission Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Buck Converter Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage Tracking Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Up and Power Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Stand-by Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device Enable Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Monitoring Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Watchdog Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
6
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Choosing Components for the Buck Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Setting up LDO1, LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Setting up of LDO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Setting up the Stand-by Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Stand-by Regulator’s Output Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1
6.2
6.3
6.4
6.4.1
7
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Sheet
2
Rev. 1.1, 2007-11-08
Next Generation Micro Controller Supply
TLE7368
1
Overview
Features
•
•
•
•
High efficient next generation microcontroller power supply system
Wide battery input voltage range < 4.5 V up to 45 V
Operating temperature range Tj = -40 °C to +150 °C
Pre-regulator for low all over power loss:
Integrated current mode Buck converter 5.5 V/2.5 A
Post-regulators, e.g. for system and controller I/O supply:
– LDO1: 5 V ±2%, 800 mA current limit
– LDO2: 3.3 V ±2% or 2.6V ±2% (selectable output), 700 mA
current limit
•
P-DSO-36-12
•
•
•
Integrated linear regulator control circuit to supply controller cores:
– LDO3 control for an external NPN power stage: 1.5 V ±2%
Post-regulators for off board supply:
– 2 Tracking regulators following the main 5 V, 105 mA and 50 mA
Stand-by regulator with lowest current consumption:
– Linear voltage regulator as stand-by supply for e.g.
memory circuits
– Hardware selectable output voltages as 1.0 V or 2.6 V, 30 mA
– Independent battery input, separated from Buck regulator input
Hardware controlled on/off logic
•
•
PG-DSO-36-24
Undervoltage detection:
– Undervoltage reset circuits with adjustable reset delay time at power up
– Undervoltage monitoring circuit on stand-by supply
Window watchdog circuit
•
•
•
•
•
•
•
Overcurrent protection on all regulators
Power sequencing on controller supplies
Overtemperature shutdown
Packages: Low Rthja power P-DSO-36-12; small exposed pad PG-DSO-36-24
PG-DSO-36-24 only: Green Product (RoHS compliant)
AEC Qualified
Type
Package
Marking
Remark
TLE7368G
P-DSO-36-12
TLE7368 G
–
TLE7368E
PG-DSO-36-24
TLE7368 E
RoHS compliant
Data Sheet
3
Rev. 1.1, 2007-11-08
TLE7368
Overview
Description
The TLE7368 device is a multifunctional power supply circuit especially designed for Automotive powertrain
systems using a standard 12 V battery. The device is intended to supply and monitor next generation 32-bit
microcontroller families (13 µm lithography) where voltage levels such as 5 V, 3.3 V or 1.5 V are required.
The regulator follows the concept of its predecessor TLE6368/SONIC, where the output of a pre-regulator feeds
the inputs of the micro’s linear supplies. In detail, the TLE7368 cascades a Buck converter with linear regulators
and voltage followers to achieve lowest power dissipation. This configuration allows to power the application even
at high ambient temperatures.
The step-down converter delivers a pre-regulated voltage of 5.5 V with a minimum peak current capability of 2.5 A.
Supplied by this step down converter two low drop linear post-regulators offer 5 V and 3.3 V (2.6 V) with high
accuracy. The current capability of the regulators is 800 mA and 700 mA. The 3.3 V (2.6 V) linear regulator does
have its own input allowing to insert a dropper from the Buck output to reduce the on chip power dissipation if
necessary. For the same reason, reduction of on chip power dissipation, the 1.5 V core supply follows the concept
of integrated control circuit with external power stage.
Implementing the on board and microcontroller supplies in this way described, allows operation even at high
ambient temperatures.
The regulator system contains the so called power sequencing function which provides a controlled power up
sequence of the three output voltages.
In addition to the main regulators the inputs of two voltage trackers are connected to the 5.5 V Buck converter
output voltage. Their protected outputs follow the main 5 V linear regulator with high accuracy and are able to drive
loads of 50 mA and 105 mA.
To monitor the output voltage levels of each of the linear regulators two independent undervoltage detection
circuits are available. They can be used to implement the reset or an interrupt function.
For energy saving reasons, e.g. while the motor is turned off, the TLE7368 offers a stand-by mode. The stand by
mode can be enabled and disabled either by battery or the microcontroller. In this stand-by mode just the stand-
by regulator remains active and the current drawn from battery is reduced to a minimum for extended battery
lifetime. A selection pin allows to configure the output voltages of the stand-by regulator to the application’s needs.
The input of the stand-by regulator is separated from the high power input of the pre-/post-regulator system.
The TLE7368 is based on Infineon’s Power technology SPT™ which allows bipolar, CMOS and power DMOS
circuitry to be integrated on the same monolithic chip/circuitry.
Data Sheet
4
Rev. 1.1, 2007-11-08
TLE7368
Block Diagram
2
Block Diagram
INT.BIASING,
BST
SW
CHARGE PUMP
IN
PWM
CONTROLLER
5.5V
TLE 7368
FB/L_IN
Q_T1
TEMPERATURE
SENSE
Q_T2
EN_µC
EN_IGN
ENABLE
≥ 1
Q_LDO1
5.0V
RESET
(WINDOW
RO_1
RT
COMPARATOR)
IN_LDO2
Q_LDO2
2.6/3.3V
1.5V
TIMING
SEL_LDO2
RESET
(WINDOW
COMPARATOR)
RO_2
DRV_EXT
FB_EXT
WDO
WINDOW
WATCHDOG
WDI
IN_STBY
Q_STBY
1.0/2.6V
STANDBY
MONITOR
MON_STBY
SEL_STBY
GND_A
GND_P
Figure 1
Block Diagram
Data Sheet
5
Rev. 1.1, 2007-11-08
TLE7368
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
GND
GND_A
RT
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND_A
MON_STBY
IN_STBY
Q_STBY
DRV_EXT
FB_EXT
Q_LDO1
FB/L_IN
BST
GND_A
RT
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
MON_STBY
IN_STBY
Q_STBY
N.C.
2
2
RO_1
3
RO_1
RO_2
N.C.
3
RO_2
4
4
IN_LDO2
Q_LDO2
Q_T1
5
5
N.C.
6
IN_LDO2
Q_LDO2
Q_T1
6
DRV_EXT
FB_EXT
Q_LDO1
FB/L_IN
BST
7
7
Q_T2
8
8
EN_uC
EN_IGN
SEL_STBY
C1-
9
Q_T2
9
TLE 7368 G
SW
10
11
12
13
14
15
16
17
18
EN_uC
EN_IGN
SEL_STBY
C1-
10
11
12
13
14
15
16
17
18
SW
SW
WDO
SW
C2-
WDI
WDO
C1+
SEL_Q2
IN
C2-
WDI
C2+
C1+
SEL_Q2
N.C.
CCP
GND_P
GND_A
IN
C2+
IN
CCP
IN
TLE 7368 E
GND_A
GND_P
IN
GND
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions TLE7368G
Pin
Pin
Symbol
GND_A
RT
Function
(TLE7368G) (TLE7368E)
1
1
Analog ground connection;
Connect to heatslug resp. exposed pad.
Reset and watchdog timing pin;
2
2
Connect a ceramic capacitor to GND to determine the time base for the
reset delay circuits and the watchdog cycle time
3
4
3
4
–
RO_1
RO_2
N.C.
Reset output Q_LDO1;
Open drain output, active low.
Connect an external 10 kΩ pull-up resistor to microcontroller I/O
voltage.
Reset output Q_LDO2 and FB_EXT;
Open drain output, active low.
Connect an external 10 kΩ pull-up resistor to microcontroller I/O
voltage
5
Internally not connected; Connect to GND_A
Data Sheet
6
Rev. 1.1, 2007-11-08
TLE7368
Pin Configuration
Pin
Pin
Symbol
Function
(TLE7368G) (TLE7368E)
6
7
5
IN_LDO2
LDO2 input;
Connect this pin straight to the Buck converter output or add a dropper
in between to reduce power dissipation on the chip.
6
Q_LDO2
Voltage regulator 2 output;
3.3 V or 2.6 V, depending on the state of SEL_LDO2.
Block to GND with capacitor for stable regulator operation; selection of
capacitor CQ_LDO2 according to Chapter 4.4 and Chapter 6.
8
7
8
9
Q_T1
Q_T2
EN_uC
Tracking regulator 1 output;
Block to GND with capacitor for stable regulator operation; selection of
capacitor CQ_T1 according to Chapter 4.4 and Chapter 6.
9
Tracking regulator 2 output;
Block to GND with capacitor for stable regulator operation; selection of
capacitor CQ_T2 according to Chapter 4.4 and Chapter 6.
10
Enable input microcontroller;
High level enables / low level disables the IC except the stand-by
regulators;
Integrated pull-down resistor
11
12
10
11
EN_IGN
Enable input ignition line;
High level enables / low level disables the IC except the stand-by
regulators;
Integrated pull-down resistor
SEL_STBY Selection input for stand-by regulator;
Connect to GND to select 2.6 V output voltage for Q_STBY;
Connect straight to Q_STBY to select 1.0 V output voltage for Q_STBY
13
14
15
16
17
12
13
14
15
16
C1-
Charge pump negative #1;
Connect a ceramic capacitor 100 nF, to C1+
C2-
Charge pump negative #2;
Connect a ceramic capacitor 100 nF, toC2+
Charge pump positive #1;
Connect a ceramic capacitor 100 nF, to C1-
Charge pump positive #2;
Connect a ceramic capacitor 100 nF, to C2-
Charge pump output;
Connect a ceramic capacitor, 220 nF, to GND;
Used for internal IC supply, do not use for other circuitry.
C1+
C2+
CCP
18
17
GND_P
Power ground;
Exclusive GND connection of charge pump;
Connect this pin to the power ground star point on the PCB.
–
18, 19
GND_A
IN
Analog ground connection;
Connect to exposed pad.
19, 20
20, 21, 22
Buck regulator input;
Connect to a pi-filter (or if not used to battery) with short lines; connect
filter capacitors in any case with short lines; connect a small ceramic
directly at the pin; For details refer to Chapter 6.
Interconnect the pins.
21
–
N.C.
Internally not connected; Connect to GND_A.
Data Sheet
7
Rev. 1.1, 2007-11-08
TLE7368
Pin Configuration
Pin
Pin
Symbol
Function
(TLE7368G) (TLE7368E)
22
23
SEL_LDO2 Selection input LDO2;
Connect to GND to select 2.6 V output voltage for LDO2;
Connect straight to Q_LDO2 to select 3.3 V output voltage for LDO2.
23
24
24
25
WDI
Window Watchdog input;
Apply a watchdog trigger signal to this pin
WDO
Window Watchdog output;
Open drain output, active low,
connect external 10 kΩ pull-up resistor to microcontroller I/O voltage
25, 26
27
26, 27
28
SW
Buck power stage’s output;
Connect both pins directly, on short lines, to the Buck converter circuit,
i.e. the catch diode and the Buck inductance
BST
Bootstrap driver supply input;
Connect the buck power stage’s driver supply capacitor to the SW pins;
For capacitor selection please refer to Chapter 6.
28
29
FB/L_IN
Q_LDO1
Buck converter feedback input plus input for LDO1 and trackers;
Connect the output of the buck converter circuit with short lines to these
pins; For Buck output capacitor selection please refer to Chapter 6.
29
30
Voltage regulator 1 output;
5 V output; Block to GND with capacitor for stable regulator operation;
Selection of capacitor CQ_LDO1 according to Chapter 4.4 and
Chapter 6.
30
31
31
32
FB_EXT
External regulator feedback input;
Feedback input of control loop for the external power stage regulator.
Connect to the emitter of the regulating transistor; Block to GND with
capacitor for stable regulator operation; Selection of capacitor
CQ_FB_EXT according to Chapter 4.4 and Chapter 6.
DRV_EXT
Bipolar power stage driver output;
Connect the base of an external NPN transistor directly to this pin;
Regarding choice of the external power stage refer to Chapter 6.
32, 33
34
–
33
N.C.
Q_STBY
Internally not connected; Connect to GND_A.
Stand-by regulator output;
Output voltage depending on the state of SEL_STBY; Block to GND
with capacitor for stable regulator operation; Selection of capacitor
CQ_STBY according to Chapter 4.4 and Chapter 6.
35
34
IN_STBY
Input to stand-by regulator;
Always connect the reverse polarity protected battery line to this pin;
Input to all IC internal biasing circuits;
Block to GND directly at the IC with ceramic capacitor; For proper
choice of input capacitors please refer to Chapter 6.
36
–
35
36
MON_STBY Monitoring output for stand-by regulator; power fail active low
output with special timing, open drain, connect external pull-up resistor.
GND_A
Analog ground connection;
Connect to exposed pad.
Data Sheet
8
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Stand-by Regulator Input IN_STBY
4.1.1
4.1.2
Voltage
Current
VIN_STBY
IIN_STBY
-0.3
–
45
–
V
A
–
Limited internally
Selection Input SEL_STBY
4.1.3
4.1.4
4.1.5
Voltage
Voltage
Current
VSEL_STBY
VSEL_STBY
ISEL_STBY
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Buck Regulator Inputs IN
4.1.6
4.1.7
4.1.8
Voltage
Voltage
Current
VIN
VIN
IIN
V
-0.3
–
SW - 0.3
45
45
–
V
V
A
–
–
Limited internally
Watchdog Input WDI
4.1.9
4.1.10
4.1.11
Voltage
Voltage
Current
VWDI
VWDI
IWDI
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Watchdog Output WDO
4.1.12
4.1.13
4.1.14
Voltage
Voltage
Current
VWDO
VWDO
IWDO
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Charge Pump Positive C<1+, 2+>
4.1.15
4.1.16
Voltage
Current
VC<1+, 2+>
IC<1+, 2+>
-0.3
–
18
–
V
mA
–
–
Charge Pump Negative C<1-, 2->
4.1.17
4.1.18
Voltage
Current
VC<1-, 2->
IC<1-, 2->
-0.3
–
5.5
–
V
mA
–
–
Charge Pump Output CCP
4.1.19
4.1.20
Voltage
Current
VCCP
ICCP
-0.3
–
18
–
V
mA
–
–
Reset Output RO_1
4.1.21
4.1.22
4.1.23
Voltage
Voltage
Current
VRO_1
VRO_1
IRO_1
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Data Sheet
9
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Absolute Maximum Ratings (cont’d)1)
Tj = -40 °C to +150 °C; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Reset Output RO_2
4.1.24
4.1.25
4.1.26
Voltage
Voltage
Current
VRO_2
VRO_2
IRO_2
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Reset Timing RT
4.1.27
4.1.28
4.1.29
Voltage
Voltage
Current
VRT
VRT
IRT
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Tracking Regulator Outputs Q_T<1..2>
4.1.30
4.1.31
Voltage
Voltage
VQ_T<1..2>
VQ_T<1..2>
-5
-5
40
35
V
V
V
FB/L_IN = 5.5V
off mode;
FB/L_IN = 0V
V
4.1.32
Current
IQ_T<1..2>
–
–
A
Limited internally
Enable Ignition EN_IGN
4.1.33
4.1.34
Voltage
Current
VEN_IGN
IEN_IGN
-0.3
–
45
–
V
mA
–
–
Enable Micro EN_uC
4.1.35
4.1.36
4.1.37
Voltage
Voltage
Current
VEN_uC
VEN_uC
IEN_uC
-0.3
-0.3
-5
5.5
6.2
5
V
V
mA
–
t < 10 s2)
–
Voltage Regulator Outputs Q_LDO<1..2>
4.1.38
4.1.39
4.1.40
4.1.41
4.1.42
Voltage
Voltage
Voltage
Voltage
Current
VQ_LDO1
VQ_LDO2
VQ_LDO<1..2> -0.3
VQ_LDO<1..2> -0.3
-0.3
-0.3
V
V
5.5
6.2
–
FB/L_IN + 0.3
IN_LDO2 + 0.3 V
V
–
–
–
V
V
A
t < 10 s2)
IQ_LDO<1..2>
–
Limited internally
Selection Input SEL_LDO2
4.1.43
4.1.44
4.1.45
Voltage
Voltage
Current
VSEL_LDO2
VSEL_LDO2
ISEL_LDO2
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
External Driver Output DRV_EXT
4.1.46
4.1.47
4.1.48
Voltage
Voltage
Current
VDRV_EXT
VDRV_EXT
IDRV_EXT
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
External Regulator Feedback Input FB_EXT
4.1.49
4.1.50
4.1.51
Voltage
Voltage
Current
VFB_EXT
VFB_EXT
IFB_EXT
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Data Sheet
10
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Absolute Maximum Ratings (cont’d)1)
Tj = -40 °C to +150 °C; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Feedback and Post-Regulators Input FB/L_IN
4.1.52
4.1.53
4.1.54
Voltage
Voltage
Current
VFB/L_IN
VFB/L_IN
IFB/L_IN
V
-0.3
–
Q_LDO1 - 0.3 18
V
V
A
–
–
18
–
Limited internally
Linear Regulator 2 Input IN_LDO2
4.1.55
4.1.56
4.1.57
Voltage
Voltage
Current
VIN_LDO2
VIN_LDO2
IIN_LDO2
V
-0.3
–
Q_LDO2 - 0.3 18
V
V
A
–
–
18
–
Limited internally
Bootstrap Supply BST
4.1.58
4.1.59
4.1.60
Voltage
Voltage
Current
VBST
VBST
IBST
V
-0.3
–
SW - 0.3
V
51
–
SW + 5.5
V
V
A
–
–
Limited internally
Buck Power Stage SW
4.1.61
4.1.62
4.1.63
Voltage
Voltage
Current
VSW
VSW
ISW
-2
-2
–
VIN + 0.3
45
–
V
V
A
–
–
Limited internally
Stand-by Regulator Output Q_STBY
4.1.64
4.1.65
4.1.66
Voltage
Voltage
Current
VQ_STBY
VQ_STBY
IQ_STBY
-0.3
-0.3
–
5.5
6.2
–
V
V
A
–
t < 10 s2)
Limited internally
Monitoring Output MON_STBY
4.1.67
4.1.68
4.1.69
Voltage
Voltage
Current
VMON_STBY -0.3
VMON_STBY -0.3
5.5
6.2
–
V
V
A
–
t < 10 s2)
IMON_STBY
–
Limited internally
Temperatures
4.1.70
4.1.71
Junction Temperature
Storage Temperature
Tj
Tstg
-40
-50
150
150
°C
°C
–
–
ESD-Protection (Human Body Model)
4.1.72
Electrostatic discharge
voltage
VESD
-2
2
kV
Human Body Model
(HBM)3)
ESD-Protection (Charged Device Model)
4.1.73
Electrostatic discharge
VESD
-500
-750
500
750
V
V
Charged Device
Model (CDM)4)
voltage to GND
4.1.74
Electrostatic discharge
voltage, corner pins to GND
VESD
Charged Device
Model (CDM)4)
1) Not subject to production test, specified by design.
2) Exposure to those absolute maximum ratings for extended periods of time (t > 10 s) may affect device reliability.
3) According to JEDEC standard EIA/JESD22-A114-B (1.5 kΩ, 100 pF)
4) According to EIA/JESD22-C101 or ESDA STM5.3.1
Data Sheet
11
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
VIN_STBY 3.0
Max.
45
45
1)
1)
4.2.1
4.2.2
4.2.3
Stand-by input voltage
Buck input voltage
Peak to peak ripple voltage at
FB/L_IN
V
V
mVpp
VIN
4.5
0
VFB/L_IN
150
–
4.2.4
Junction temperature
Tj
-40
150
°C
–
1) At minimum battery voltage regulators with higher nominal output voltage will not be able to provide the full output voltage.
Their outputs follow the battery with certain drop.
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
P-DSO-36-12
4.3.1
Junction to ambient
RthJA
RthJA
–
–
49
39
–
–
K/W
K/W
Footprint only1)
4.3.2
Junction to ambient
Junction to ambient
Junction to case
Heat sink area
300mm2 1)
4.3.3
4.3.4
RthJA
RthJC
–
–
32
–
–
K/W
K/W
Heat sink area
600mm2 1)
–
4.4
PG-DSO-36-24
4.3.5
Junction to ambient
RthJA
RthJA
–
–
54
42
–
–
K/W
K/W
Footprint only1)
4.3.6
Junction to ambient
Junction to ambient
Junction to case
Heat sink area
300mm2 1)
4.3.7
4.3.8
RthJA
RthJC
–
35
–
K/W
Heat sink area
600mm2 1)
–
–
5.6
–
K/W
1) Worst case regarding peak temperature; zero airflow; mounted on FR4; 80 × 80 × 1.5 mm3; 35µ Cu; 5µ Sn
Data Sheet
12
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
4.4
Electrical Characteristics
Electrical Characteristics
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
Pos.
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
Buck Regulator
4.4.1
4.4.2
Switching frequency
Current transition
rise/fall time
280
–
370
50
425
–
kHz
ns
–
f
tr, I
1); slope magnitude 1 A; fixed
internally
4.4.3
4.4.4
Power stage on
resistance
Power stage peak
current limit
RON, Buck
Ipeak, SW
–
–
–
280
4.6
mΩ
–
2.5
A
VIN = 5.0 V;
V
SW ramped down from 5.0 V
to 3.7 V;
V
FB/L_IN = 5.0 V
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
Buck converter output VFB/L_IN
5.4
5.4
–
–
6.0
6.4
4.5
–
V
I
Buck = 2.0 A2)
voltage
Buck converter output VFB/L_IN
–
V
I
Buck = 100 mA2)
voltage
Buck converter, turn on VIN, on
–
V
VIN increasing
VIN decreasing
threshold
Buck converter, turn off VIN, off
3.5
450
–
–
V
threshold
Buck converter On/off VIN, hyst
500
–
550
mV
V
VIN, hyst = VIN, on - VIN, off
hysteresis
Bootstrap undervoltage VBST_UV, on
VSW
+
Bootstrap voltage increasing
lockout, turn on
5.0
threshold
4.4.11
4.4.12
Bootstrap undervoltage VBST_UV, off
VSW
+
–
–
–
1
V
V
Bootstrap voltage decreasing
lockout, turn off
3.2
threshold
Bootstrap undervoltage VBST_UV, hyst 0.2
VBST_UV, hyst
=
lockout, hysteresis
V
BST_UV, on - VBST_UV, off
Charge Pump
4.4.13
Charge pump voltage VCCP
9
9
–
–
15
V
V
C
C
C
C1 = 100 nF;
C2 = 100 nF;
CCP = 220 nF
4.4.14
Charge pump voltage VCCP
13.5
VIN = 4.5 V;
CC1 = 100 nF;
CC2 = 100 nF;
CCCP = 220 nF
4.4.15
Charge pump switching fCCP
1.0
–
2.5
MHz
–
frequency
Data Sheet
13
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
Voltage Regulator Q_LDO1
4.4.16
4.4.17
4.4.18
Output voltage
Output current limitation IQ_LDO1, lim
Drop voltage
VQ_LDO1
4.9
800
–
–
–
–
5.1
1600 mA
400
400
V
1 mA < IQ_LDO1 < 700 mA3)
Q_LDO1 = 4.0 V
Q_LDO1 = 500 mA;
FB/L_IN = 5.0 V;3) 4)
Q_LDO1 = 250 mA;
VIN = 4.5 V;3) 4)
V
Vdr, Q_LDO1
mV
mV
I
V
4.4.19
–
–
I
4.4.20
4.4.21
Load regulation
Power supply ripple
rejection
∆VQ_LDO1
PSRRQ_LD O1 26
–
60
–
120
–
mV/A –
dB
V
FB/L_IN = 5.6 V;
V
FB/L_IN, ripple pp = 150 mV;
f
FB/L_IN, ripple = 370 kHz;
I
Q_LDO1 = 250 mA;
C
Q_LDO1 = 4.7 µF, X7R1)
1) 5)
4.4.22
4.4.23
Output capacitor
Output capacitor
CQ_LDO1
ESR
CQ_LDO1
1
0
–
–
470
2
µF
Ω
at 10 kHz1)
Voltage Regulator Q_LDO2
4.4.24
4.4.25
4.4.26
4.4.27
Output voltage
VQ_LDO2
3.23
700
–
–
–
–
–
3.37
V
SEL_LDO2 = Q_LDO2;
IN_LDO2 = FB/L_IN;
1 mA < IQ_LDO2 < 500 mA
Output current limitation IQ_LDO2, lim
1400 mA
SEL_LDO2 = Q_LDO2;
IN_LDO2 = FB/L_IN;
V
Q_LDO2 = 2.8 V
Drop voltage
Drop voltage
Vdr, Q_LDO2
400
400
mV
SEL_LDO2 = Q_LDO2;
CCP = 9 V;
Q_LDO2 = 500 mA;4) 6)
SEL_LDO2 = Q_LDO2;
CCP = 9 V;
Q_LDO2 = 250 mA;
VIN = 4.5 V;4) 6)
mV/A 3.3 V mode
1 mA < IQ_LDO2 < 650 mA
V
I
Vdr, Q_LDO2
–
mV
V
I
4.4.28
4.4.29
Load regulation
Output voltage
∆VQ_LDO2
–
–
–
80
VQ_LDO2
2.56
2.67
V
SEL_LDO2 = GND;
IN_LDO2 = FB/L_IN;
1 mA < IQ_LDO2 < 500 mA
4.4.30
4.4.31
Output current limitation IQ_LDO2, lim
700
–
–
–
1400 mA
SEL_LDO2 = GND;
IN_LDO2 = FB/L_IN;
V
Q_LDO2 = 2.0 V
Drop voltage
Vdr, Q_LDO2
400
mV
SEL_LDO2 = GND;
CCP = 9 V;
Q_LDO2 = 500 mA;4)6)
V
I
Data Sheet
14
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
4.4.32
Drop voltage
Vdr, Q_LDO2
–
–
400
mV
SEL_LDO2 = GND;
CCP = 9 V;
Q_LDO2 = 250 mA;
VIN = 4.5 V;4)6)
mV/A 2.6 V mode
1 mA < IQ_LDO2 < 650 mA
V
I
4.4.33
4.4.34
Load regulation
∆VQ_LDO2
–
–
–
65
–
Power supply ripple
rejection
PSRRQ_LDO2 26
dB
V
IN_LDO2 = 5.6 V;
V
IN_LDO2, ripple pp = 150 mV;
f
IN_LDO2, ripple = 370 kHz;
I
Q_LDO2 = 250mA;
C
Q_LDO2 = 4.7 µF ceramic
X7R1)
–
4.4.35
Selector Pull-down
resistor
Output capacitor
Output capacitor
RSEL_LDO2
CQ_LDO2
ESR
CQ_LDO2
0.7
1.2
1.9
MΩ
1)5)
4.4.36
4.4.37
1
0
–
–
470
2
µF
Ω
at 10 kHz;1)
External Voltage Regulator Control
4.4.38
4.4.39
4.4.40
4.4.41
Driver current limit
Feedback voltage
Feedback input current IFB_EXT
Load regulation
IDRV_EXT, lim 75
VFB_EXT 1.51
–
–
–
–
150
1.55
–
mA
V
µA
V
–
–
FB_EXT = 1.2 V
-250
∆VFB_EXT
–
20
mV/A VFB/L_IN = 5.4 V;
V
CCP = 9.0 V;
I
FB_EXT = 100 µA to 1 A;7)
1)5)7)
4.4.42
4.4.43
Output capacitor
Output capacitor
CFB_EXT
ESR
CFB_EXT
4.7
0
–
–
–
0.1
µF
Ω
at 10 kHz;1)
Voltage Tracker Q_T1
4.4.44
Output voltage tracking ∆VQ_T1
-10
–
10
mV
0 mA < IQ_T1 < 105 mA
accuracy to Q_LDO1
4.4.45
4.4.46
Output current limitation IQ_T1
120
–
–
–
240
400
mA
mV
V
Q_T1 = 4.0 V
Drop voltage
Vdr, Q_T1
I
Q_T1 = 105 mA;
V
FB/L_IN = 5.3 V;
Q_LDO1 = 5.0 V4)
V
4.4.47
Power supply ripple
rejection
PSRRQ_T1
26
–
–
dB
V
V
FB/L_IN = 5.6 V;
FB/L_IN, ripple pp = 150 mV;
f
FB/L_IN, ripple = 370 kHz;
Q_LDO1 = 5.0 V;
V
I
Q_T1 = 100 mA;
C
Q_T1 = 4.7µF ceramic X7R;1)
1)5)
4.4.48
4.4.49
Output capacitor
Output capacitor
CQ_T1
ESR CQ_T1
4.7
0
–
–
–
3
µF
Ω
at 10 kHz;1)
Data Sheet
15
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
Voltage Tracker Q_T2
4.4.50
Output voltage tracking ∆VQ_T2
-10
–
10
mV
0 mA < IQ_T2 < 50 mA;
accuracy to Q_LDO1
4.4.51
4.4.52
Output current limitation IQ_T2
60
–
–
–
110
400
mA
mV
V
Q_T2 = 4.0 V
Drop voltage
Vdr, Q_T2
I
Q_T2 = 50 mA;
V
FB/L_IN = 5.3 V;
Q_LDO1 = 5.0 V4)
V
4.4.53
Power supply ripple
rejection
PSRRQ_T2
26
–
–
dB
V
V
FB/L_IN = 5.6 V;
FB/L_IN, ripple pp = 150 mV;
f
FB/L_IN, ripple = 370 kHz;
Q_LDO1 = 5.0 V;
V
I
Q_T2 = 40 mA;
C
Q_T2 = 4.7 µF ceramic X7R;1)
1)5)
4.4.54
4.4.55
Output capacitor
Output capacitor
CQ_T2
ESR CQ_T2
4.7
0
–
–
–
3
µF
Ω
at 10 kHz;1)
Stand-by Regulator
4.4.56
4.4.57
4.4.58
Output voltage
VQ_STBY
VQ_STBY
VQ_STBY
0.93
0.93
2.51
1.02
1.02
2.62
1.08
1.08
2.73
V
V
V
VIN_STBY > 3 V;
100 µA < IQ_STBY < 10 mA;
SEL_STBY = Q_STBY
Output voltage
Output voltage
V
IN_STBY > 4.5 V;
Q_STBY = 30 mA;
SEL_STBY = Q_STBY
I
V
IN_STBY > 3.0 V;
100 µA < IQ_STBY < 10 mA;
SEL_STBY = GND
4.4.59
4.4.60
4.4.61
Selector pull-up current ISEL_STBY
Output current limitation IQ_STBY, lim
-2
31
–
-5
–
–
-10
90
5
µA
mA
V/A
SEL_STBY = GND
V
Q_ STBY = 0.5 V
Q_STBY = 100µA to 10 mA
IN_STBY > 4.5 V;
SEL_STBY = Q_STBY
Q_STBY = 1.0V
Q_STBY = 100µA to 10 mA
IN_STBY > 4.5 V;
Load regulation
∆VQ_ STBY
I
V
V
–
–
–
10
V/A
I
V
SEL_STBY = GND
V
Q_STBY = 2.6V
4.4.62
4.4.63
Line regulation
∆VQ_ STBY
–
–
5
–
mV/V –
dB
Power supply ripple
rejection
PSRRQ_STBY 60
V
IN_STBY, ripple pp = 500 mV;
f
IN_STBY, ripple = 100 Hz;
I
Q_STBY = 5 mA;
C
Q_STBY = 1 µF ceramic X7R;1)
1) 5)
4.4.64
Output capacitor
CQ_STBY
0.47
–
2
µF
Data Sheet
16
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
0
Typ.
–
Max.
0.5
4.4.65
Output capacitor
ESR
CQ_STBY
Ω
at 10 kHz;1)
Device Enable Blocks and Quiescent Current
4.4.66
Ignition turn on
VEN_IGN, on
–
–
–
4.0
–
V
V
Device operating
threshold
4.4.67
Ignition turn off
threshold
VEN_IGN, off
2.0
Only stand-by regulators are
active if VEN_IGN < VEN_IGN, off
and VEN_uC < VEN_uC, off
4.4.68
Ignition pull-down
resistor current
IEN_IGN
-100
–
–
µA
VEN_IGN = 13.5 V
4.4.69
4.4.70
Turn on threshold
Turn off threshold
VEN_uC, on
VEN_uC, off
–
0.8
–
–
2.0
–
V
V
Device operating
Only stand-by regulators are
active if VEN_IGN < VEN_IGN, off
and VEN_uC < VEN_uC, off
4.4.71
4.4.72
Pull-down resistor
current
IEN_uC
-30
–
–
–
–
µA
µA
V
EN_uC = 5 V
Quiescent current
Quiescent current
Quiescent current
Iq =IIN_STBY - -120
V
EN_uC = VEN_IGN = 0 V;
IQ_STBY
SEL_STBY = Q_STBY;
MON_STBY = H;
I
Q_STBY = 100 µA; Tj < 125 °C
4.4.73
4.4.74
Iq =IIN_STBY - -130
–
–
–
–
µA
µA
VEN_uC = VEN_IGN = 0 V;
IQ_STBY
SEL_STBY = GND;
MON_STBY = H;
I
Q_STBY = 100 µA; Tj < 125 °C
Iq, IN
-10
V
EN_uC = VEN_IGN = 0 V;
V
IN_STBY = 0 V;
Tj < 125 °C
Reset Generator RO_1 Monitoring Q_LDO1
4.4.75
4.4.76
4.4.77
4.4.78
4.4.79
4.4.80
4.4.81
Undervoltage Reset
VURT Q_LDO1, 4.50
de
–
–
–
–
–
–
–
4.75
4.90
220
5.65
5.60
180
0.4
V
V
V
V
Q_LDO1 decreasing;
FB/L_IN = open;
Q_LDO1 increasing
threshold on Q_LDO1
Undervoltage Reset
threshold on Q_LDO1
Undervoltage Reset
hysteresis
Overvoltage Reset
threshold on Q_LDO1
Overvoltage Reset
threshold on Q_LDO1
VURT Q_LDO1, 4.55
in
V
VURO_1, hyst 100
mV
V
–
VORT Q_LDO1, 5.40
in
V
V
–
Q_LDO1 increasing
Q_LDO1 decreasing
VORT Q_LDO1, 5.25
de
V
Overvoltage Reset
hysteresis
VORO_1, hyst 80
mV
V
RO_1, Reset output low VRO_1, low
–
I
RO_1 = -10 mA;
voltage
VQ_LDO1 > 2.5 V
Data Sheet
17
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
4.4.82
RO_1, Reset output low VRO_1, low
–
–
0.25
V
V
V
IN_STBY = 3.0 V;
Q_LDO1 = 2.5V;
voltage
I
RO_1 = -500 µA;
4.4.83
RO_1, Reset output
leakage
IRO_1, high
-1
–
1
µA
VRO_1 = 5.0 V
4.4.84
4.4.85
Reset delay time base Tcycle
41.6
0.33
50
1.0
62.5
4.7
µs
nF
C
–
RT = 1 nF
Reset timing capacitor CRT
range
4.4.86
4.4.87
Reset delay time RO_1 tRD, RO_1
–
2
160
–
–
10
Tcycle
µs
–
Undervoltage Reset
tUVRR, RO_1
Voltage step at Q_LDO1 from
5.00 V to 4.48 V
reaction time
4.4.88
Overvoltage Reset
reaction time
tOVRR, RO_1
20
–
80
µs
Buck converter operating;
Voltage step at Q_LDO1 from
5.00 V to 5.67 V
Reset Generator RO_2 Monitoring Q_LDO2 and FB_EXT
4.4.89
Undervoltage Reset
VURT Q_LDO2, 3.135
de
–
3.230
–
V
SEL_LDO2 = Q_LDO2;
threshold on Q_LDO2
V
Q_LDO2 decreasing;
IN_LDO2 = open
V
4.4.90
Undervoltage Reset
headroom on Q_LDO2
VURT Q_LDO2, 55
head
117.5
mV
SEL_LDO2 = Q_LDO2;
VURT Q_LDO2, head
= VQ_LDO2 - VURT Q_LDO2, de
;
V
Q_LDO2 @ IQ_LDO2 = 500 mA
4.4.91
Undervoltage Reset
hysteresis Q_LDO2
VURO_2, hyst 15
–
55
mV
SEL_LDO2 = Q_LDO2;
VURO_2, hyst
= VURT Q_LDO2, in - VURT Q_LDO2, de
4.4.92
4.4.93
4.4.94
4.4.95
Overvoltage Reset
VORT Q_LDO2, 3.70
in
–
–
–
–
3.85
3.80
200
V
SEL_LDO2 = Q_LDO2;
threshold on Q_LDO2
VQ_LDO2 increasing
Overvoltage Reset
threshold on Q_LDO2
Overvoltage Reset
hysteresis
Undervoltage Reset
threshold on Q_LDO2
VORT Q_LDO2, 3.55
de
V
SEL_LDO2 = Q_LDO2;
V
Q_LDO2 decreasing
VORO_2, hyst 50
mV
V
SEL_LDO2 = Q_LDO2;
VURT Q_LDO2, 2.485
de
2.560
SEL_LDO2 = GND;
V
V
Q_LDO2 decreasing;
IN_LDO2 = open
4.4.96
4.4.97
Undervoltage Reset
VURT Q_LDO2, 47
head
–
–
–
mV
mV
SEL_LDO2 = GND;
VURT Q_LDO2, head
headroom on Q_LDO2
= VQ_LDO2 - VURT Q_LDO2, de
;
V
Q_LDO2 @ IQ_LDO2 = 500 mA
Undervoltage Reset
hysteresis Q_LDO2
VURO_2, hyst 15
60
SEL_LDO2 = GND;
VURO_2, hyst
= VURT Q_LDO2, in - VURT Q_LDO2, de
Data Sheet
18
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
4.4.98
4.4.99
Overvoltage Reset
VORT Q_LDO2, 2.85
in
–
3.0
V
SEL_LDO2 = GND;
Q_LDO2 increasing
SEL_LDO2 = GND;
Q_LDO2 decreasing
SEL_LDO2 = GND;
threshold on Q_LDO2
V
Overvoltage Reset
threshold on Q_LDO2
VORT Q_LDO2, 2.73
de
–
–
–
2.95
120
V
V
4.4.100 Overvoltage Reset
hysteresis Q_LDO2
4.4.101 Undervoltage Reset
threshold on FB_EXT
VORO_2, hyst 50
mV
V
VURT FB_EXT, 1.425
de
1.480
V
V
FB_EXT decreasing;
FB/L_IN = 5 V
or VQ_LDO2 = 3.3/2.6 V
4.4.102 Undervoltage Reset
VFB_EXT
-
40
60
–
mV
VFB/L_IN = 5 V
headroom on FB_EXT VURT FB_EXT,
or VQ_LDO2 = 3.3/2.6 V;
V
FB_EXT @ IFB_EXT = 1 A
de
4.4.103 Undervoltage Reset
hysteresis FB_EXT
4.4.104 Overvoltage Reset
threshold on FB_EXT
4.4.105 Overvoltage Reset
threshold on FB_EXT
4.4.106 Overvoltage Reset
hysteresis FB_EXT
VURO_2, hyst 15
–
–
–
–
–
–
–
45
mV
V
–
VORT FB_EXT, 1.65
in
1.72
1.67
120
0.4
0.25
1
V
V
–
FB_EXT increasing
FB_EXT decreasing
VORT FB_EXT, 1.55
de
V
VORO_2, hyst 50
mV
V
4.4.107 RO_2, Reset output low VRO_2, low
–
I
RO_2 = -10 mA;
Q_LDO2 > 2.0 V
RO_2 = -500 µA;
Q_LDO2 = 1V
RO_2 = 5.0 V
voltage
V
4.4.108 RO_2, Reset output low VRO_2, low
–
V
I
voltage
V
V
4.4.109 RO_2, Reset output
leakage
IRO_2, high
-1
µA
4.4.110 Reset delay time RO_2 tRD, RO_2
–
2
160
–
–
10
Tcycle
µs
–
4.4.111 Undervoltage Reset
tUVRR, RO_2
tUVRR, RO_2
tOVRR, RO_2
Voltage step on Q_LDO2 from
reaction time
V
Q_LDO2, nom to
V
URT Q_LDO2, de, min - 20 mV
4.4.112 Undervoltage Reset
reaction time
2
–
–
10
80
µs
µs
Voltage step on FB_EXT from
V
FB_EXT, nom to
URT FB_EXT, de, min - 20 mV
V
4.4.113 Overvoltage Reset
reaction time
20
Buck converter operating;
Voltage step on Q_LDO2 from
V
Q_LDO2, nom to
ORT Q_LDO2, in, max + 20 mV
V
4.4.114 Overvoltage Reset
reaction time
tOVRR, RO_2
20
–
80
µs
Buck converter operating;
Voltage step on FB_EXT from
V
V
FB_EXT, nom to
ORT FB_EXT, in, max + 20 mV
Data Sheet
19
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
Monitoring Block
4.4.115 MON_STBY,
VMON,Q_STBY, 0.90
de
–
–
–
V
IN_STBY = 3.0 V;
Threshold on Q_STBY
SEL_STBY = Q_STBY;
V
V
Q_STBY decreasing;
IN_STBY = 3.0 V;
4.4.115a MON_STBY headroom VMON,Q_STBY, 10
–
mV
SEL_STBY = Q_STBY;
head
V
Q_STBY decreasing;
4.4.116 MON_STBY hysteresis VMON_STBY,
10
–
–
30
mV
V
SEL_STBY = Q_STBY
hyst
4.4.117 MON_STBY,
Threshold on Q_STBY
VMON,Q_STBY, 2.36
de
2.50
V
IN_STBY = 3.0 V;
SEL_STBY = GND;
Q_STBY decreasing;
SEL_STBY = GND
V
4.4.118 MON_STBY hysteresis VMON_STBY,
20
–
–
–
50
mV
V
hyst
4.4.119 MON_STBY,
Monitoring output low
voltage
4.4.120 MON_STBY time delay tMON_ STBY
VMON_ STBY,
0.4
I
MON_STBY1 < 10 mA;
IN_STBY > 3.0 V
V
low
–
3
8
–
–
6
tRD,
RO_1
see diagram in section
“Monitoring Circuit” on
Page 28
4.4.121 Monitor reaction time
tRR, MON_STBY
µs
–
Data Sheet
20
Rev. 1.1, 2007-11-08
TLE7368
General Product Characteristics
Electrical Characteristics (cont’d)
VIN = VIN_STBY = 13.5 V, Tj = -40 °C to +150 °C,
V
CCP = 9.0 V; SEL_STBY = Q_STBY; all voltages with respect to ground.
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
Window Watchdog
4.4.122 H-input voltage
VWDI, high
VWDI, low
–
–
–
2.0
–
V
V
–
–
threshold
4.4.123 L-input voltage
threshold
0.8
4.4.124 WDI pull-up resistor
4.4.125 Watchdog cycle time
RWDI
TWD
60
–
–
100
2
512
140
–
–
kΩ
Tcycle
TWD
connected to Q_LDO2
–
–
4.4.126 Window duration (OW, tWD, W
CW, FW)
4.4.127 Window duration (IW) tWD, IW
–
–
32
32
–
–
TWD
–
4.4.128 Window watchdog
tWD, start
TWD Watchdog will start/initialized if
WDI is kept low for this period
and RO_2 is released
initialization time
4.4.129 Watchdog output low
voltage
4.4.130 Watchdog output
leakage current
VWDO,low
IWDO,leak
–
–
–
–
0.4
1
V
IWDO = 2 mA
µA
WDO state = High
Thermal Shutdown
1) 8)
1)
4.4.131 Overtemperature
Tj, shtdwn
160
15
175
–
190
30
°C
shutdown
4.4.132 Overtemperature
shutdown hysteresis
∆T
K
1) Specified by design, not subject to production test.
2) Tested according to measurement circuit 1.
3) VCCP supplied externally with a voltage according to the actual value of VCCP measurement.
4) Vdr, Q_LDO1 = VFB/L_IN - VQ_LDO1; Vdr, Q_LDO2 = VIN_LDO2 - VQ_LDO2; Vdr, T<1, 2> = VFB/L_IN - VQ_T<1, 2>
5) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum.
6) Measured when VQ_LDO2 has dropped 100 mV from its nominal value obtained at VIN_LDO2 = 5.4 V.
7) External power transistor type: Fairchild KSH200.
8) Permanent operation of the device above 150 °C degrades lifetime; please refer to quality information.
Data Sheet
21
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
5
Detailed Internal Circuits Description
In the following the main circuit blocks of the TLE7368, namely the Buck converter, the linear regulators, the
trackers, the charge pump, the enable and reset circuits and the watchdog are described in more detail.
5.1
Buck Regulator
The TLE7368’s DC to DC converter features all the functions necessary to implement a high efficient, low emission
Buck regulator with minimum external components. The step down regulator in the TLE7368 follows a concept
similar to the one of its predecessor, TLE6368, which allows operation over a battery voltage range from as low
as 4.5 V up to a maximum of 45 V at peak currents of 2.5 A at minimum. Figure 3 shows the block diagram of the
converter with its major components, i.e. the internal DMOS power stages, the high side driver including its supply
scheme, the power stage slope control circuit for reduced EME, the current mode control scheme and various
protection circuits for safe converter operation.
5.1.1
Buck Regulator Control Scheme
The step down converter’s control method is based upon the current mode control scheme. Current mode control
provides an inherent line feed forward, cycle by cycle current limiting and ease of loop compensation. No external
compensation components are needed to stabilize the loop, i.e. the operation of the Buck converter. The slope
compensation circuit in addition to the current sense amplifier and the error amplifier prevents instabilities/sub
harmonic oscillations at duty cycles higher than 0.5. The cycle by cycle current limiting feature supports also a soft
start feature during power up. Additional implemented current blanking prevents faulty DMOS turn off signals
during switching operation.
5.1.2
High Side Driver Supply and 100% Duty Cycle Operation
The supply concept of the Buck converter’s power stage driver follows the Bootstrapping principle. A small external
capacitor, placed between pins SW and BST, is used to provide the necessary charge at the gate of the power
stage. The capacitor is refreshed at each switching cycle while the power stage is turned off resulting in the ability
to power the gate at the next turn on of the power stage.
In cases where the input/battery voltage approaches the nominal Buck converter output voltage, the duty cycle of
the converter increases. At the point where the power stage is statically turned on (100% duty cycle) a refresh of
the Bootstrap capacitor as described above is not possible. In this case the charge pump helps to accomplish the
gate over drive in order to keep the power stage turned on with low Rdson. With decreasing input voltage, shortly
before switching to 100% duty cycle, the device operates in pulse skipping mode. In this mode the device appears
to be operating at much lower frequencies with very small duty cycles. In real, the device is doing a few 100% duty
cycle periods followed by a period with a duty cycle smaller than 1.
Data Sheet
22
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
Figure 3
Buck Converter Block Diagram
5.1.3
Electromagnetic Emission Reduction
The Buck DMOS power stage is implemented as multiple cells. This allows to control the slope of the power
stage’s current at turn on/off by sequentially turning on/off the cells, achieving a smooth turn on/off and therefore
avoiding high frequency components in the electromagnetic emissions to the battery line. The current slope control
is adjusted internally, the typical current slew rate is 50 ns/A.
Data Sheet
23
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
5.1.4
Charge Pump
The charge pump serves as support circuit for the Buck converter’s high side driver supply, the linear regulators
drive circuits for low drop operation and the internal device biasing blocks. In order to guarantee full device
operation at battery voltages as allow as even 4.5 V, the concept of a voltage tripler is chosen for the charge pump.
It operates at a switching frequency of typical 2 MHz utilizing three small external capacitors, two pumping caps
and one storage capacitor. The CCP circuit is equipped with a current limit function which avoids destruction in
case of a short of one of the external CCP capacitors. The charge pump’s output, CCP, is designed to supply the
circuitry described above, it should not be used as e.g. driver rail for external on board/PCB circuits.
5.1.5
Buck Converter Protection Circuits
Besides the circuits mandatory for the Buck converter operation additional protection circuits are foreseen which
help preventing false operation of the device. Undervoltage lockouts are foreseen at the battery input line1) and
the high side driver supply rail to ensure the device operates only with proper voltages present. The overvoltage
shutdown at the Buck converter output provides a safe high side shutdown for the case where the Buck control
loop becomes messed up due to non predictable circumstances. At overtemperatures the thermal shutdown circuit
disables the Buck converter until the device cools down to be enabled again.
5.2
Linear Regulators
The TLE7368 features three linear voltage regulator circuits, two fully integrated DMOS low drop voltage
regulators and one integrated linear control circuit to operate with an external NPN power stage.
Integrated linear regulator one (LDO1) offers a 5 V output and the second integrated linear regulator (LDO2) can
be configured with pin SEL_LDO2 either for 2.6 V or for 3.3 V. With SEL_LDO2 tied to GND 2.6 V will adjust at
the output of LDO2, SEL_LDO2 being connected to Q_LDO2 gives the 3.3 V option. The external regulator will
adjust its output to 1.5 V with the emitter of the NPN power stage directly connected to pin FB_EXT, by using a
voltage divider, higher output voltages can be achieved.
The regulators are designed for low drop operation and offer high output voltage accuracies to meet the needs of
current and next generation 32-bit microcontroller families. Additionally all regulators feature a short circuit
protection, i.e. the integrated regulators contain a output current limit function whereas the control circuit for the
external NPN power stage limits the maximum base current.
For low on chip power dissipation the input of LDO1 is internally directly connected to the Buck converter output
(FB/L_IN). LDO2’s input is on purpose externally accessible at IN_LDO2. This allows the insertion of a drop
element between the Buck converter output and IN_LDO2 to split the power dissipation and avoid high losses on
the TLE7368. Similar for the external NPN power stage regulator, the collector of the NPN can be either connected
directly to the Buck converter output or a drop element can be inserted in between to split power dissipation.
5.3
Voltage Tracking Regulators
For off board/off PCB supplies, i.e. sensors, two voltage tracking regulators are incorporated in the TLE7368. Their
outputs follow the output of the main 5 V regulator, Q_LDO1, within a tight tolerance of ±10 mV. The tracking
regulators are implemented with bipolar PNP power stages for improved ripple rejection to reduce emission when
lead off board. Both tracker outputs can withstand short circuits to GND and battery in a range of -5 V to +40 V.
When shorted to lower levels than the nominal output voltage level the current limit function prevents excessive
current draw.
1) Not shown in the schematic, Figure 3.
Data Sheet
24
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
5.4
Power Up and Power Down Sequencing
In a supply system with multiple outputs the sequence of enabling the individual regulators is important. Especially
32-bit microcontrollers require a defined power up and power down sequencing. Figure 4 shows the details for
the power up and power down sequence of the TLE7368.
At power up, the first circuit block to be enabled is the charge pump as it is mandatory for the other circuits to
operate. With the charge pump reaching its nominal value, the Buck converter starts to power up its output. Also
the output voltage the linear regulators are enabled. The three linear regulators power up simultaneously. The 5 V
regulator acts as the master, the 3.3 V/2.6 V regulator and the 1.5 V regulator follow. As the 5 V regulator powers
up also the tracking regulators follow. The ramp if the increasing output voltage of each line is determined by the
connected output capacitance, the load current and the current limit of the regulator under consideration. In
addition an integrated supervision circuit ensures the following two conditions during power-up:
-0.3 V < (VQ_LDO1 - VQ_LDO2) < 3.1 V and
-0.3 V < (VQ_LDO2 - VFB_EXT
(1)
(2)
)
The power down sequence is practically vice versa to the start up procedure. With the battery decreasing to zero
the charge pump and Buck regulator will stop to operate at the minimum battery threshold, the Buck output voltage
will fall down and so will the outputs of the linear regulators.
In the event where the device is disabled, EN_IGN = low and EN_uC = low, the charge pump, the Buck converter
and the linear regulators are disabled immediately.
The linear regulators’ outputs are not discharged actively in any case of power down. Diode circuitry (i.e. Schottky
diodes) might be necessary to avoid violation of certain microcontrollers’ sequencing requirements.
Data Sheet
25
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
VIN
VIN, on
VIN, off
t
VCCP
VCCP, ok
t
t
t
t
t
t
VBST
VBST, on
VSW
VFB/L_IN
*)
VQ_LDO1
VQ_LDO2
VFB_EXT
VQ_T<1,2>
*) drop depending on
application / setup
*)
*)
VQ_LDO1
-0.3 < (Q_LDO1-Q_LDO2) < 3.1V
Linear regulators not actively
discharged at power down; externa
Schottky diodes required to meet
uC”s sequencing requirements
VQ_LDO2
*)
*)
-0.3 < ( Q_LDO2 - FB_EXT)
t
t
VQ_LDO1
Figure 4
Power Sequencing of the TLE7368
Data Sheet
26
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
5.5
Stand-by Regulator
The intention of the stand-by or keep alive regulator is to supply e.g. external memory even with the main
microcontroller supply being disabled. Therefore the state of the stand-by regulator is not controlled by the enable
block, but it is active all the time. The stand-by regulator starts to operate as soon as the battery voltage increases
above its operating threshold. The current consumption during single operation of the stand-by regulator is
reduced to a minimum. It can be configured for output voltages as either 1.0 V or 2.6 V through the SEL_STBY pin.
5.6
Overtemperature Protection
At junction temperatures between 160 °C and 190 °C, which can be caused by e.g. excessive power dissipation
or increased ambient temperatures, the overtemperature protection kicks in and disables the Buck converter. With
the Buck converter disabled the linear regulators will most likely not be able to keep up their output voltage and a
system reset can be expected. Due to the drop in power dissipation the junction temperature will decrease. The
built in hysteresis circuit ensures that the junction temperature cools down by a certain temperature delta before
the Buck converter is enabled again.
5.7
Device Enable Function
The device enable block controls the operation of the Buck converter as well as of the linear regulators and tracker
blocks. Two external signal inputs determine the state of those blocks, a high voltage input EN_IGN and a low
voltage input EN_uC. Internally the two signals are logic OR-ed which means that with either signal the Buck and
linear regulators can be turned on or held active, provided that the battery voltage is above its minimum operating
range. In order to turn off the regulator blocks, the signals on both inputs, EN_IGN and EN_uC must be lower than
their deactivating threshold. The stand-by regulator’s operation is not affected by the device enable block.
5.8
Reset Function
The Reset concept of the TLE7368 is chosen to support multiple microcontroller platforms. Two open drain
outputs, i.e. the Reset outputs, RO_1 and RO_2, indicate the states of the different regulators. Figure 5 gives the
details on the Reset timing. RO_1 is tied to LDO1 and will indicate whenever its output, Q_LDO1, is crossing the
under- or overvoltage threshold. The second Reset output, RO_2, turns low whenever one of the two outputs,
Q_LDO2 or FB_EXT, are crossing their under- and overvoltage thresholds. At power up in order to avoid a faulty
microcontroller start, a so called Reset delay function, i.e. the Reset release delay, is implemented. This delay until
the reset is released, counted from the time where the regulator outputs cross the threshold, is determined by a
small external delay capacitor at pin RT.
The power up reset delay time tRD is directly proportional to the capacitance CRT within the capacitance range of
0.33 nF … 4.7 nF:
t
RD = 160 × 50 µs × CRT/nF
(3)
For the tolerance calculation please refer to the parameters 4.4.77, 4.4.78 and 4.4.79. In order to find the worst
case limits of tRD the capacitance tolerance should be taken into account.
The Reset generators within the TLE7368 are supplied from multiple sources, VIN_STBY, VCCP, VFB_L/IN,
VQ_LDO1 and VQ_LDO2, to fulfill next generation microcontroller requirements during power up and power down.
Data Sheet
27
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
VFB/L_IN
t
VORT Q_LDO1, in
VQ_LDO1 VORT Q_LDO1, de
VURT Q_LDO1, in
VURT Q_LDO1, de
< tOVRR, RO_1
< tUVRR, RO_1
tRD, RO_1
t
tRD, RO_1
tRD, RO_1
tUVRR, RO_1
tUVRR, RO_1
*)
VRO_1
t
VORT Q_LDO2, in
VQ_LDO2 VORT Q_LDO2, de
VURT Q_LDO2, in
VFB_EXT
VURT Q_LDO2, de
< tOVRR, RO_2
< tUVRR, RO_2
VORT FB_EXT, in
VORT FB_EXT, de
VURT FB_EXT, in
VURT FB_EXT, de
< tUVRR, RO_2
< tOVRR, RO_2
t
tRD, RO_2
tRD, RO_2
tRD, RO_2
tOVRR, RO_2
tRD, RO_2
**)
VRO_2
tUVRR, RO_2
tOVRR, RO_2
tUVRR, RO_2
t
*) pulled to e.g. Q_LDO1 by 10kOhm **) pulled to e.g. Q_LDO2 by 10kOhm
Figure 5
Reset Timing TLE7368
Data Sheet
28
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
5.9
Monitoring Circuit
The monitoring block within the TLE7368 detects an undervoltage at the stand-by regulator output and is able to
distinguish between two different undervoltage situations. When the stand-by output gets back into regulation after
an undervoltage event, the timing on the MON_STBY output signal indicates the kind of undervoltage scenario
which has happened before. The behavior of the monitoring block is also described in Figure 6 and Figure 7
below.
In case of an undervoltage at the stand-by regulator with the 5 V regulator LDO1 in regulation (which means that
RO_1 = HIGH) the monitoring circuit has basically a power fail functionality which means that the MON_STBY
output will be LOW just as long as the undervoltage at the stand-by output occurs. As soon as Q_STBY is coming
back into regulation MON_STBY turns high again.
When the 5 V regulator is out of regulation (RO_1 = LOW), e.g. in case of EN_uC = EN_IGN = LOW, the
MON_STBY will turn LOW again if an undervoltage event happens at Q_STBY. The difference to the scenario
described above is now that when Q_STBY gets back into regulation the toggling of the MON_STBY output to
HIGH is coupled with the 5 V Reset line, RO_1, turning HIGH. In detail, the MON_STBY line turns high delayed
by tMON_STBY after the Reset line RO_1 had gone high.
MON = High
VQ_STBY < V
VQ_STBY < VMON, Q_STBY, de
aMnOdN, Q_STBY, de
and
RO_1 = High
RO_1 = Low
Monitor timing
= don’t care
VQ_STBY > VMON, Q_STBY, in
VQ_STBY > VMON, Q_STBY, in
and
and
RO_1 = High
RO_1 = High
MON = Low
MON = Low
VQ_STBY > VMON, Q_STBY, in
and
RO_1 = Low
Monitor timing
= no delay*)
Monitor timing
= delay**)
VQ_STBY < VMON, Q_STBY, de
and
RO_1 = Low
*) power fail functionionality
**) power on reset functionality
Figure 6
Stand by Monitor State Diagram
Data Sheet
29
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
VIN
VIN_STBY
VQ_STBY
t
t
VMON, Q_STBY, in
VMON, Q_STBY, de
< tRR, MON_STBY1
t
t
t
*)
VRO_1
tMON_STBY
tRR, MON_STBY
tRR, MON_STBY
tRR, MON_STBY
*)
VMON_STBY
Power on reset functionality, with RO_1
low during under voltage at Q_STBY
Power fail functionality, w/o delay, with
RO_1 high during under voltage at Q_STBY
*) output pulled to e.g. Q_LDO1 by 10kOhm
Figure 7
Stand by Monitor Timing Diagram
Data Sheet
30
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
5.10
Watchdog Circuit
Always
Ignore
WDO = LOW
Window
Trigger During
Closed Window
No Trigger During
Open Window
Always
Trigger
Closed
Open
Window
Window
No Trigger
AEA03533.VSD
Figure 8
Window Watchdog State Diagram
Principle of Operation:
A Window Watchdog is integrated in the TLE7368 to monitor a microcontroller. The Window Watchdog duty cycle
consists of an "Open window" and a "Closed window". The microcontroller that is being monitored has to send a
periodic falling edge trigger signal to the watchdog input pin WDI within the "Open Window". If a trigger signal is
not sent or if it is sent during the "Closed Window", then Watchdog Output (WDO) switches from high to low
signaling a potential microcontroller fault has occurred. The watchdog cycle time TWD is derived from the time base
T
Cycle. An external capacitor connected between pins RT and GND determines TCycle
.
Initialization:
The Watchdog is switched off per default and activated by pulling WDI to low at least for the time tWD,start after RO_2
has turned to high. Watchdog input pin WDI has an integrated pull-up resistor RWDI connected to Q_LDO2. If WDI
transitions to high before tWD,start has elapsed, then the watchdog will not start operation. To initialize the Watchdog
the watchdog input WDI should transition to high within the "Ignore Window". The WDI signal may also transition
to high during the following "Open Window", but sufficient time must be left for a falling edge transition before the
end of the "Open Window". The watchdog function is turned off following a RO_2 reset, and must be reinitialized
to be turned back on.
Normal Operation:
Please refer to Figure 8.
The Watchdog starts operating in the "Ignore Window" state for a duration of tWD,IW. Within the "Ignore Window"
the microcontroller is given time to initialize. Any signal to watchdog input WDI within the "Ignore Window" is
ignored. After time tWD,IW, the watchdog transitions from the "Ignore Window" state to the "Open Window" state for
a maximum duration of tWD,W. Within the "Open Window" a valid trigger signal must be applied to the watchdog
Data Sheet
31
Rev. 1.1, 2007-11-08
TLE7368
Detailed Internal Circuits Description
input WDI. A valid trigger signal is a falling edge from VWDI,high to VWDI,low. After receiving a valid trigger signal within
the "Open Window" the watchdog immediately terminates the "Open Window" and enters the "Closed Window"
state. The "Closed Window" has a fixed duration tWD,W. During normal operation a trigger signal should not be
applied during the "Closed Window. After the "Closed Window" time tWD,W an the watchdog returns back to the
"Open Window" state. Within the "Open Window", a valid trigger signal must be applied to the watchdog input WDI.
In normal operation, the watchdog continues to cycle between the "Open Window" and "Closed Window" state. If
reset signal RO_2 is asserted and transitions to a low state, then the watchdog needs to be reinitialized as
described in the Initialization section. The watchdog output WDO stays high as long as the watchdog input WDI
is triggered correctly.
Valid Trigger Signal:
Please refer to Figure 9.
Watchdog input WDI is periodically sampled with a period of TWD. A valid trigger signal is a falling edge from
VWDI,high to VWDI,low. To improve immunity against noise or glitches on the WDI input, at least two high samples
followed two low samples are required for a valid trigger signal. For example, if the first three samples (two HGH
one LOW) of the trigger pulse at pin WDI are inside the closed window and only the fourth sample (the second
LOW sample) is taken in the open window then the watchdog output WDO will remain High.
Invalid Triggering:
Please refer to Figure 8 and Figure 9.
No trigger signal detected during the "Open Window" or a trigger signal detected during the "Closed Window", is
considered invalid triggering. Watchdog output WDO switches to low for a duration of tWD,W immediately after no
valid trigger during the "Open Window" or immediately if a trigger signal is detected during the "Closed Window".
Fault Operation:
If a capacitor failure on the watchdog timing pin RT causes a short circuit to GND, then the internal oscillator stops
operating. Without oscillator operation there is no time reference for the watchdog so it does not know when the
"Closed Window" period has ended. Thus, every second trigger signal on watchdog input WDI generates a
watchdog failure causing WDO to switch from high to low. An open circuit at pin RT also causes WDO to switch
from high to low.
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Figure 9
Window Watchdog Input Signal Validation
Data Sheet
32
Rev. 1.1, 2007-11-08
TLE7368
Application Information
6
Application Information
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
C1
C2
CCP
BST
INT.BIASING,
Battery
Input
CHARGE PUMP
IN
5.5V
PWM
CONTROLLER
5.5V
SW
TLE 7368
FB/L_IN
Q_T1
5V, to sensor
5V, to sensor
5V
TEMPERATURE
SENSE
Q_T2
EN_µC
from µC
ENABLE
≥ 1
EN_IGN
from IGN
Q_LDO1
5.0V
RESET
(WINDOW
RO_1
RT
to µC
IN_LDO2
Q_LDO2
COMPARATOR)
e.g. 3.3V
2.6/3.3V
1.5V
TIMING
SEL_LDO2
RESET
(WINDOW
COMPARATOR)
RO_2
to µC
DRV_EXT
FB_EXT
e.g. 1.5V
WINDOW
WDO
WDI
to µC
from µC
WATCHDOG
IN_STBY
Keep Alive
Input
Q_STBY
e.g. 1.5V
1.0/2.6V
MON_STBY
STANDBY
MONITOR
to µC
SEL_STBY
GND_P
GND_A
Figure 10 Application Diagram, Example
Note:This is a very simplified example of an application circuit. The function must be verified in the real application.
Data Sheet
33
Rev. 1.1, 2007-11-08
TLE7368
Application Information
This section intends to give hints for correct set up of the IC, i.e. to avoid misbehavior caused by the influence of
other PCB board circuits and shows also how to calculate external components, power loss, etc.
6.1
Choosing Components for the Buck Regulator
Stable operation of the Buck converter is ensured when choosing the external passive components according to
the characteristics given below:
•
•
•
Buck inductance: 18 µH < LBuck < 220 µH
Buck output capacitor: CBuck > 20 µF
ESR of Buck output capacitor: ESR_CBuck < 150 mΩ
6.2
Setting up LDO1, LDO2
The linear regulators LDO1 and LDO2 need to be connected to appropriate output capacitors in order to keep the
regulation loop stable and avoid oscillations. The essential parameters of the output capacitor are the minimum
capacitance and the equivalent series resistance (ESR). The required ranges for each output are specified in
Chapter 4.4 (Electrical Characteristics). Tantalum capacitors as well as multi layer ceramic capacitors are
suitable for LDO1 and LDO2.
Table 1
No.
1
LDO2 Output Voltage Configuration
SEL_LDO2
GND
Q_LDO2
Q_LDO2
2.6 V
3.3 V
2
6.3
Setting up of LDO3
LDO3 consists of an integrated regulator which needs to be equipped with an external power transistor (NPN-
Type). Suitable NPN power transistors types are e.g. KSH 200 from Fairchild semiconductor or NJD 2873T4 from
ON semiconductor. The most important parameters to be checked when choosing the external transistor are the
‘current gain bandwidth product’ (fT), the ‘DC current gain’ (hFE) and the thermal resistance of the package.
Darlington type transistors should not be used. For stability of the regulation loop a multi layer ceramic capacitor
of min. 4.7 µF must be connected to the LDO3 output voltage (Emitter of the external power transistor). In order
to improve suppression load current steps an additional capacitor of tantalum type can be connected in parallel.
In case LDO3 voltage is not needed the external NPN transistor can be spared. For this configuration the pins
‘DRV_EXT’ and ‘FB_EXT’ should be directly connected to each other in order to ensure correct operation of
Reset 2. Also in this case a small ceramic capacitor of 220 nF connected from pin ‘FB_EXT’ to GND is
recommended in order to avoid oscillations of the regulation loop LDO3.
Data Sheet
34
Rev. 1.1, 2007-11-08
TLE7368
Application Information
6.4
Setting up the Stand-by Regulator
The stand by regulator provides an output current up to 30 mA sourced via linear regulation directly from Battery
even when the main regulator is disabled. This low quiescent current regulator is commonly used as supply for
stand by memory. The output voltage can be selected as 1.0 V or 2.6 V. For stability of the regulation loop the
output Q_STBY should be connected via a ceramic capacitor (470 nF to 2 µF) to GND.
6.4.1
Stand-by Regulator’s Output Voltage Configuration
The stand by regulator provides an output voltage of nominal 1.0 V or 2.6 V which is associated with an
appropriate stand-by monitoring threshold. The output voltage level is selected by the SEL_STBY configuration.
Connecting SEL_STBY to GND results in a voltage level of 2.6 V at Q_STBY, while connecting SEL_STBY with
Q_STBY leads to 1.0 V configuration. An integrated pull-up current ensures that the system will turn in the lower
stand-by voltage mode in case of open mode at the SEL_STBY pin. However the SEL_STBY pin should be
connected either to Q_STBY or to GND in order to select the appropriate Q_STBY voltage level. Intermediate
voltage levels at SEL_STBY should be avoided.
Table 2
Stand-by Regulator’s Output Voltage Configuration
No.
1
2
SEL_STBY
GND
Q_STBY
Q_STBY
2.6 V
1.0 V
Data Sheet
35
Rev. 1.1, 2007-11-08
TLE7368
Package Outlines
7
Package Outlines
1)
±0.15
11
B
2.8
±0.1
1.1
±0.1
15.74
6.3
(Heatslug)
Heatslug
0.65
0.1 C 36x
±0.15
0.95
0.25 +0.13
M
0.25 A B C
±0.3
14.2
0.25 B
17 x 0.65 = 11.05
36
19
Bottom View
19
36
Index Marking
1 x 45˚
Heatslug
1
18
1
10
13.7-0.2
1)
±0.1
15.9
A
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Stand off
GPS09181
Figure 11 P-DSO-36-12 (Plastic - Dual Small Outline Package)
You can find all of our packages, sorts of packing and others in our
Dimensions in mm
Rev. 1.1, 2007-11-08
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
36
TLE7368
Package Outlines
0.35 x 45˚
1)
7.6-0.2
12˚
+0.09
0.23
0.65
±0.2
±0.3
0.7
0.1
36x
C
C
10.3
SEATING PLANE
D
17 x 0.65 = 11.05
2)
±0.08
0.33
M
0.17 A-B C
36x
D
Bottom View
A
36
19
19
36
Exposed Diepad
1
18
B
18
1
Index Marking
7
1)
12.8-0.2
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
GPS01153
Figure 12 PG-DSO-36-24 (Plastic Green - Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
Data Sheet
37
Rev. 1.1, 2007-11-08
TLE7368
Revision History
8
Revision History
Rev Date
Changes
1.1 2007-11-08 • Final datasheet for both versions, TLE7368G and TLE7368E.
•
•
•
•
•
•
•
Page 3, Overview: Updated package pictures.
Page 3, Overview: Updated table: Status Final/Target removed.
Page 12, Thermal resistance table: Inserted values for version TLE7368E.
Page 12, Thermal resistance table: Updated values for version TLE7368G.
4.4.72/4.4.73: Condition described more precise: Inserted “MON_STBY = H”.
Figure 9: Modified graph for better description of the window watchdog function.
Chapter 5.10 Watchdog: Revised phrasing for better understanding
1.0 2007-08-13 • Final Datasheet Version TLE7368G; Target Datasheet Version TLE7368E
0.61 2006-12-18 • Target Datasheet
Data Sheet
38
Rev. 1.1, 2007-11-08
Edition 2007-11-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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