TLE75080-ESH_技术文档

TLE75080-ESH

SPIDER+ 12V

SPI Driver for Enhanced Relay Control

Package

Marking

PG-TSDSO-24

TLE75080ESH

1

Overview

Applications

•

High-side switches for 12 V in automotive or industrial applications such

as lighting, heating, motor driving, energy and power distribution

•

Especially designed for driving relays, LEDs and motors.

V_{BA TT}

V_DD

R_VDD

C_VDD

C_VS

V_{BA TT1}

V_{BA TT2}

IN0_LH

IN1_LH

VDD

VS

GPO

IN0

R_IN

VS1

IN1

OUT0_HS

OUT2_HS

OUT4_HS

OUT6_HS

IDLE

R_IDLE

R_LH

Z_VS

LI MP HO ME

VS2

OUT1_HS

OUT3_HS

OUT5_HS

OUT7_HS

GPO

GPI

CSN

SCLK

SI

R_CSN

R_SCLK

R_SI

SO

R_SO

GND

Application_8HS.emf

Figure 1

TLE75080-ESH Application Diagram

Datasheet

www.infineon.com

1

Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Overview

Basic Features

•

16-bit serial peripheral interface for control and diagnosis

Daisy Chain capability SPI also compatible with 8-bit SPI devices

2 CMOS compatible parallel input pins with Input Mapping functionality

Cranking capability down to V_S= 3.0 V (supports LV124)

Digital supply voltage range compatible with 3.3 V and 5 V microcontrollers

Bulb Inrush Mode (BIM) to drive 2 W lamps and electronic loads

Two internal PWM Generators for µC offload

Two independent battery feeds (V_S1, V_S2) for high-side channels

Very low quiescent current (with usage of IDLE pin)

Limp Home mode (with usage of IDLE and IN pins)

Green Product (RoHS compliant)

AEC Qualified

Protection Features

•

Reverse battery protection on V_Swithout external components

Short circuit to ground and battery protection

Stable behavior at under voltage conditions (“Lower Supply Voltage Range for Extended Operation”)

Over Current latch OFF

Thermal shutdown latch OFF

Overvoltage protection

Loss of ground protection

Loss of battery protection

Electrostatic discharge (ESD) protection

Diagnostic Features

•

Latched diagnostic information via SPI register

Over Load detection at ON state

Open Load detection at OFF state using Output Status Monitor function

Output Status Monitor

Input Status Monitor

Open Load detection at ON state

Application Specific Features

•

Fail-safe activation via Input pins in Limp-Home Mode

SPI with Daisy Chain capability

Safe operation at low battery voltage (cranking)

2 W lamps, 5 W lamps with two channels in parallel mode and enhanced capacitive loads driving capability

(Bulb Inrush Mode)

•

Two independent internal PWM generators to drive e.g. LEDs

Two supply pins for different battery feeds (each pin is the power drain of four high-side channels)

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Overview

Description

The TLE75080-ESH is an eight channel high-side power switch in PG-TSDSO-24 package providing embedded

protective functions. It is specially designed to control relays and LEDs in automotive and industrial

applications.

A serial peripheral interface (SPI) is utilized for control and diagnosis of the loads as well as of the device. For

direct control and PWM there are two input pins available connected to two outputs by default. Additional or

different outputs can be controlled by the same input pins (programmable via SPI).

Table 1

Product Summary

Parameter

Symbol

V_S

Values

Analog supply voltage

3.0 V … 28 V

Digital supply voltage

V_DD

3.0 V … 5.5 V

Minimum overvoltage protection

V_S(AZ)

R_DS(ON)

I_L(NOM)

E_AR

42 V (see Chapter 8.5 for details)

Maximum on-state resistance at T_J= 150 °C

Nominal load current (T_A= 85 °C, all channels)

Maximum Energy dissipation - repetitive

Maximum Source to Ground clamping voltage

Maximum overload switch OFF threshold

Maximum total quiescent current at T_J≤ 85 °C

Maximum SPI clock frequency

2.2 Ω

330 mA

10 mJ @ I_L(EAR)= 220 mA

V_OUT(CL)

I_L(OVL0)

I_SLEEP

f_SCLK

-16 V

2.3 A

5 µA

5 MHz

Detailed Description

The TLE75080-ESH is an eight channel high-side switch providing embedded protective functions. The output

stages incorporate eight high-side switches (typical R_DS(ON)at T_J= 25°C is 1 Ω). Driving a load from high-side

offers the possibility to perform Open Load at ON diagnosis.

The 16-bit serial peripheral interface (SPI) is utilized to control and diagnose the device and the loads. The SPI

interface provides daisy chain capability in order to assemble multiple devices (also devices with 8 bit SPI) in

one SPI chain by using the same number of microcontroller pins.

This device is designed for low supply voltage operation, therefore being able to keep its state at low battery

voltage (V_S≥ 3.0 V). The SPI functionality, including the possibility to program the device, is available only

when the digital power supply is present (see Chapter 6 for more details).

The TLE75080-ESH is equipped with two input pins that are connected to two outputs, making them

controllable even when the digital supply voltage is not available. With the Input Mapping functionality it is

possible to connect the input pins to different outputs, or assign more outputs to the same input pin. In this

case more channels can be controlled with one signal applied to one input pin.

In Limp Home mode (Fail-Safe mode) the input pins are directly routed to channels 2 and 3. When IDLE pin is

“low”, it is possible to activate the two channels using the input pins independently from the presence of the

digital supply voltage.

The device provides diagnosis of the load via Open Load at ON state, Open Load at OFF state (with

DIAG_OSM.OUTn bits) and short circuit detection. For Open Load at OFF state detection, a internal current

source I_OLcan be activated via SPI.

Each output stage is protected against short circuit. In case of Overload, the affected channel switches OFF

when the Overload Detection Current I_L(OVLn)is reached and can be reactivated via SPI. In Limp Home mode

operation, the channels connected to an input pin set to “high” restart automatically after Output Restart time

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Overview

t_RETRY(LH)is elapsed. Temperature sensors are available for each channel to protect the device against Over

Temperature.

The power transistors are built by N-channel power MOSFET with one central chargepump . The inputs are

ground referenced TTL compatible. The device is monolithically integrated in Smart Power Technology.

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Block Diagram and Terms

2

Block Diagram and Terms

2.1

Block Diagram

VS1

VS2

VS

VDD

temperature

sensor

Over Load

detection

power supply

Open Load at

ON

Power mode

control

IDLE

Output Status

Monitor

IN0

IN1

Limp Home

high-side

gate control

control,

diagnostic

and

protective

functions

OUT7_HS

OUT6_HS

OUT5_HS

OUT4_HS

input register

Bulb Inrush

Mode

OUT3_HS

OUT2_HS

OUT1_HS

OUT0_HS

PWM generator

CSN

SCLK

SI

SPI

SO

diagnosis

register

GND

BlockDiagram_8HS.emf

Figure 2

Block Diagram of TLE75080-ESH

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Block Diagram and Terms

2.2

Terms

Figure 3 shows all terms used in this data sheet, with associated convention for positive values.

V_S

I_VS

VS

I_VDD

I_{ID LE}

I_VS1

VDD

IDLE

VS1

V_DD

V_{ID LE}

V_DS6V_DS4V_DS2V_DS0V_S1

I_{L_S0}

I_{L_S2}

I_{L_S4}

I_{L_S6}

OUT0_HS

OUT2_HS

OUT4_HS

OUT6_HS

V_OUT0

I_IN0

I_IN1

IN0

IN1

V_IN0

V_IN1

V_OUT2

V_OUT4

V_OUT6

I_{VS 2}

VS2

V_DS7V_DS5V_DS3V_DS1V_S2

I_CSN

I_SCLK

I_SI

I_{L_S1}

I_{L_S3}

I_{L_S5}

I_{L_S7}

CSN

SCLK

SI

OUT1_HS

OUT3_HS

OUT5_HS

OUT7_HS

V_CSN

V_SCLK

V_SI

V_OUT1

V_OUT3

V_OUT5

I_SO

SO

V_SO

V_OUT7

GND

I_GND

Terms_8HS.emf

Figure 3

Voltage and Current definition

In all tables of electrical characteristics the channel related symbols without channel numbers are valid for

each channel separately (e.g. V_DSspecification is valid for V_DS0... V_DS7).

Furthermore, parameters relative to output current can be indicated without specifying whether the current

is going into the Drain pin or going out of the Source pin, unless otherwise specified. For instance, nominal

output current can be indicated in the following ways: I_L(NOM)I_{L_HS(NOM)}I_{L_S(NOM)}

All SPI registers bits are marked as follows: ADDR.PARAMETER(e.g. HWCR.RST) with the exception of the

bits in the Diagnosis frames which are marked only with PARAMETER(e.g. UVRVS).

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

(top view)

CSN

SCLK

SI

1

2

3

24

23

22

21

20

19

18

17

16

15

14

13

VDD

IN0

IN1

SO

GND

4

5

IDLE

VS

6

7

OUT1_HS

n.c.

OUT0_HS

n.c.

25

SUB

OUT2_HS

VS1

8

9

OUT3_HS

VS2

OUT4_HS

10

11

12

OUT5_HS

OUT6_HS

n.c.

OUT7_HS

n.c.

PinOut_8HS.emf

Figure 4

Pin Configuration TLE75080-ESH in PG-TSDSO-24

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Pin Configuration

3.2

Pin Definitions and Functions

Symbol

I/O

Function

Power Supply Pins

20

VS

–

Analog supply V_S

Positive supply voltage for power switches gate control (incl.

protections)

9

VS1

VS2

–

Analog supply V_S1

Positive supply voltage for power switches drain current (channels 0,

2, 4 and 6)

16

Analog supply V_S2

Positive supply voltage for power switches drain current (channels 1,

3, 5 and 7)

24

5

VDD

GND

–

Digital supply V_DD

Supply voltage for SPI with support function to V_S

Ground

Ground connection

SPI Pins

1

CSN

SCLK

SI

I

Chip Select

“low” active, integrated pull-up to V_DD

2

3

4

I

Serial Clock

“high” active, integrated pull-down to ground

I

Serial Input

“high” active, integrated pull-down to ground

SO

O

Serial Output

“Z” (tri-state) when CSN is “high”

Input and Stand-by Pins

21

23

22

IDLE

I

Idle mode

power mode control, “high” activates Idle mode, integrated pull-down

to ground

IN0

Input pin 0

connected to channel 2 by default and in Limp Home mode, “high”

active, integrated pull-down to ground

IN1

Input pin 1

connected to channel 3 by default and in Limp Home mode, “high”

active, integrated pull-down to ground

Power Ouput Pins

6

OUT0_HS

O

Source of high-side power transistor (channel 0)

Source of high-side power transistor (channel 2)

Source of high-side power transistor (channel 4)

Source of high-side power transistor (channel 6)

Source of high-side power transistor (channel 7)

8

OUT2_HS

OUT4_HS

OUT6_HS

OUT7_HS

10

11

14

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Pin Configuration

15

Symbol

I/O

O

Function

OUT5_HS

OUT3_HS

OUT1_HS

Source of high-side power transistor (channel 5)

Source of high-side power transistor (channel 3)

Source of high-side power transistor (channel 1)

17

O

19

O

Not Connected pins / Cooling Tab

7, 12, 13, 18

25

n.c.

–

Not Connected, internally not bonded

GND

Exposed pad

It is recommended to connect it to PCB ground for cooling and EMC -

not usable as electrical GND pin. Electrical ground must be provided

by pin 5.

Datasheet

9

Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 2

Absolute Maximum Ratings ¹⁾

T_J= -40 °C to +150 °C

all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Voltage ranges specifed for V_Sapply also to V_S1and V_S2(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Supply Voltages

Analog Supply voltage

Digital Supply voltage

V_S

-0.3

–

28

5.5

42

V

–

P_4.1.1

P_4.1.2

P_4.1.3

V_DD

–

2)

Supply voltage for load dump V_S(LD)

protection

Supply voltage for short circuit V_S(SC)

protection (single pulse)

0

–

28

16

V

–

P_4.1.4

P_4.1.5

3)

Reverse polarity voltage

-V_S(REV)

T_J(0)= 25 °C

t ≤ 2 min

See Chapter 11 for

general setup.

R_L= 70 Ω on all

channels

Current through VS pin

Current through VDD pin

Power Stages

I_VS

-10

-50

–

10

mA

t ≤ 2 min

P_4.1.7

P_4.1.8

I_VDD

Load current

|I_L|

–

I_L(OVL0)

A

V

single channel

P_4.1.9

Voltage at power transistor

V_DS

-0.3

-16

42

–

P_4.1.10

P_4.1.11

Power transistor source voltage V_{OUT_S}

V_{OUT_D}

+0.3

Power transistor drain voltage V_{OUT_D}

(V_{OUT_S}≥ 0 V)

V_{OUT_S}- –

0.3

42

50

V

–

P_4.1.12

P_4.1.59

P_4.1.13

Power transistor drain voltage V_{OUT_D}

(V_{OUT_S}< 0 V)

-0.3

–

V

4)

Maximum energy dissipation

single pulse

E_AS

mJ

T_J(0)= 25 °C

I

_L(0)= 2*I_L(EAR)

4)

Maximum energy dissipation

single pulse

E_AS

–

25

mJ

P_4.1.14

T_J(0)= 150 °C

I_L(0)= 400 mA

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

General Product Characteristics

Table 2

Absolute Maximum Ratings (cont’d)¹⁾

T_J= -40 °C to +150 °C

all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Voltage ranges specifed for V_Sapply also to V_S1and V_S2(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

4)

Maximum energy dissipation

E_AR

–

10

mJ

P_4.1.15

repetitive pulses - I_L(EAR)

T_J(0)= 85 °C

I_L(0)= I_L(EAR)

2*10⁶cycles

IDLE pin

Voltage at IDLE pin

Current through IDLE pin

Input Pins

V_IDLE

I_IDLE

-0.3

5.5

V

–

P_4.1.23

P_4.1.25

P_4.1.26

-0.75

-10.0

0.75

2.0

mA

–

t ≤ 2 min.

Voltage at input pins

Current through input pins

SPI Pins

V_IN

I_IN

-0.3

5.5

V

–

P_4.1.28

P_4.1.30

P_4.1.31

-0.75

-10.0

0.75

2.0

mA

–

t ≤ 2 min.

Voltage at chip select pin

V_CSN

-0.3

5.5

V

–

P_4.1.33

P_4.1.34

P_4.1.35

P_4.1.37

P_4.1.38

P_4.1.39

P_4.1.41

P_4.1.42

P_4.1.43

P_4.1.58

P_4.1.45

Current through chip select pin I_CSN

-0.75

-10.0

-0.3

0.75

2.0

mA

V

–

t ≤ 2 min.

Voltage at serial clock pin

V_SCLK

5.5

Current through serial clock pin I_SCLK

-0.75

-10.0

-0.3

0.75

2.0

mA

V

–

t ≤ 2 min.

Voltage at serial input pin

V_SI

5.5

Current through serial input pin I_SI

Voltage at serial output pin SO V_SO

-0.75

-10.0

-0.3

0.75

2.0

mA

V

–

t ≤ 2 min.

V_DD+0.3

0.75

Current through serial output

pin SO

I_SO

-0.75

mA

Current through serial output

pin SO

I_SO

-2.0

10.0

mA

t ≤ 2 min.

P_4.1.46

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

T_J

-40

-55

–

150

°C

–

P_4.1.48

P_4.1.49

T_stg

5)

ESD Susceptibility HBM

OUT pins vs. V_Sor GND

V_ESD

-4

-2

–

4

2

kV

P_4.1.50

P_4.1.51

HBM

5)

ESD Susceptibility HBM

other pins

HBM

Datasheet

11

Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

General Product Characteristics

Table 2

Absolute Maximum Ratings (cont’d)¹⁾

T_J= -40 °C to +150 °C

all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Voltage ranges specifed for V_Sapply also to V_S1and V_S2(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

6)

ESD Susceptibility CDM

Pin 1, 12, 13, 24 (corner pins)

V_ESD

-750

–

750

V

P_4.1.52

P_4.1.54

CDM

6)

ESD Susceptibility CDM

-500

–

500

V

CDM

1) Not subject to production test, specified by design.

2) For a duration of t_on= 400 ms; t_on/t_off= 10%; limited to 100 pulses

3) Device is mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; the Product

(Chip+Package) was simulated on a 76.2 *114.3 *1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

4) Pulse shape represents inductive switch off: I_L(t) = I_L(0) x (1 - t / t_pulse); 0 < t < t_pulse

5) ESD susceptibility, Human Body Model “HBM” according to AEC Q100-002

6) ESD susceptibility, Charged Device Mode “CDM” according to AECQ100-011 Rev D

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

4.2

Functional Range

Table 3

Functional range

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Supply Voltage Range for

Normal Operation

V_S(NOR)

7

18

V

–

P_4.2.1

P_4.2.2

P_4.2.3

Upper Supply Voltage Range V_S(EXT,UP)

for Extended Operation

18

3

–

28

7

Parameter

deviation possible

Lower Supply Voltage Range V_S(EXT,LOW)

Parameter

for Extended Operation

deviation possible

Junction Temperature

Logic supply voltage

T_J

-40

3

–

150

5.5

°C

V

–

P_4.2.4

P_4.2.5

V_DD

Note:

Within the functional or operating range, the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the Electrical Characteristics

table.

Datasheet

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Rev. 1.10

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TLE75080-ESH

SPIDER+ 12V

General Product Characteristics

4.3

Thermal Resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 4

Thermal Resistance

Parameter

Symbol

Values

Typ.

3

Unit Note or

Test Condition

Number

Min.

Max.

1)

Junction to Soldering Point R_thJSP

–

5

K/W

P_4.3.4

measured to

exposed pad (pin 25)

1)2)

Junction to Ambient

R_thJA

–

28

–

K/W

P_4.3.5

1) not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product

(Chip+Package) was simulated on a 76.2 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

4.3.1

PCB set up

70µm

1.5mm

35µm

0.3mm

Zth_PCB_2s2p.emf

Figure 5

2s2p PCB Cross Section

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

General Product Characteristics

Figure 6

PC Board for Thermal Simulation with 600 mm2 Cooling Area

Figure 7

PC Board for Thermal Simulation with 2s2p Cooling Area

Datasheet

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Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

General Product Characteristics

4.3.2

Thermal Impedance

8 Channels High-side

100

10

1

2s2p

1s0p - 600 mm²

1s0p - 300 mm²

1s0p - footprint

0.1

0.0001

0.001

0.01

0.1

1

10

100

1000

Time [s]

Figure 8

Typical Thermal Impedance. PCB setup according Chapter 4.3.1

8 Channels High-side

100.00

1s0p - Tamb = 105°C

90.00

80.00

70.00

60.00

50.00

40.00

30.00

0

100

200

300

400

500

600

700

Area [mm²]

Figure 9

Typical Thermal Resistance. PCB setup 1s0p

Datasheet

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TLE75080-ESH

SPIDER+ 12V

Control Pins

5

Control Pins

The device has three pins (IN0, IN1 and IDLE) to control directly the device without using SPI.

5.1

Input pins

TLE75080-ESH has two input pins available. Each input pin is connected by default to one channel (IN0 to

channel 2, IN1 to channel 3). Input Mapping Registers MAPIN0 and MAPIN1 can be programmed to connect

additional or different channels to each input pin, as shown in Figure 10. The signals driving the channels are

an OR combination between OUT register status, PWM Generators (according to PWM Generator Output

Mapping status), IN0 and IN1 (according to Input Mapping registers status). See Chapter 7.5 for further

details.

IN1

Limp Home mode

(default )

I_IN1

&

MAPIN1

8

IN0

Limp Home mode

Channel 7

Channel 6

(default )

I_IN0

Channel 5

OR

Channel 4

8

Channel 3

Channel 2

Channel 1

&

Channel 0

MAPIN0

OUT

8

OR

8

InputMapping_8ch.emf

Figure 10 Input Mapping

The logic level of the input pins can be monitored via the Input Status Monitor Register (INST). The Input

Status Monitor is operative also when TLE75080-ESH is in Limp Home mode. If one of the Input pins is set to

“high” and the IDLE pin is set to “low”, the device switches into Limp Home mode and activates the channel

mapped by default to the input pins. See Chapter 6.1.5 for further details.

5.2

IDLE pin

The IDLE pin is used to bring the device into Sleep mode operation when is set to “low” and all input pins are

set to “low”.When IDLE pin is set to “low” while one of the input pins is set to “high” the device enters Limp

Home mode.

To ensure a proper mode transition, IDLE pin must be set for at least t_IDLE2SLEEP(P_6.3.54, transition from “high”

to “low”) or t_SLEEP2IDLE(P_6.3.53, transition from “low” to “high”).

Setting the IDLE pin to “low” has the following consequences:

•

All registers in the SPI are reset to default values

Datasheet

16

Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Control Pins

•

V_DDand V_SUndervoltage detection circuits are disabled to decrease current consumption (if both inputs

are set to “low”)

No SPI communication is allowed (SO pin remains in high impedance state also when CSN pin is set to

“low”) if both input pins are set to “low”

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SPIDER+ 12V

Control Pins

5.3

Electrical Characteristics Control Pins

Table 5

Electrical Characteristics: Control Pins

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

IDLE pin

L-input level

H-input level

L-input current

H-input current

Input Pins

V_IDLE(L)

V_IDLE(H)

I_IDLE(L)

I_IDLE(H)

0

0.8

5.5

20

V

–

P_5.3.1

P_5.3.2

P_5.3.3

P_5.3.4

2.0

5

V

–

12

28

μA

V_IDLE= 0.8 V

V_IDLE= 2.0 V

14

45

L-input level

H-input level

L-input current

H-input current

V_IN(L)

V_IN(H)

I_IN(L)

0

0.8

5.5

20

V

–

P_5.3.5

P_5.3.6

P_5.3.7

P_5.3.8

2.0

5

V

–

12

28

μA

V_IN= 0.8 V

V_IN= 2.0 V

I_IN(H)

14

45

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SPIDER+ 12V

Power Supply

6

Power Supply

The TLE75080-ESH is supplied by four supply voltages:

•

V_S(analog supply voltage used also for the logic)

V

_S1(analog supply voltage used as drain for channels 0, 2, 4 and 6)

_S2(analog supply voltage used as drain for channels 1, 3, 5 and 7)

V_DD(digital supply voltage)

The V_Ssupply line is connected to a battery feed and used, in combination with V_DDsupply, for the driving

circuitry of the power stages. In situations where V_Svoltage drops below V_DDvoltage (for instance during

cranking events down to 3.0 V), an increased current consumption may be observed at VDD pin.

V_Sand V_DDsupply voltages have an undervoltage detection circuit, which prevents the activation of the

associated function in case the measured voltage is below the undervoltage threshold. More in detail:

•

An undervoltage on both V_Sand V_DDsupply voltages prevents the activation of the power stages and any

SPI communication (the SPI registers are reset)

An undervoltage on V_DDsupply prevents any SPI communication. SPI read/write registers are reset to

default values.

An undervoltage on V_Ssupply forces the TLE75080-ESH to drain all needed current for the logic from V_DD

supply. All channels are disabled, and are enabled again as soon as V_S≥ V_S(OP)

.

Figure 11 shows a basic concept drawing of the interaction between supply pins VS and VDD, the output stage

drivers and SO supply line.

VS1

CP

GD

HS

Ch. 0,2,4,6

VS

I_VS

VS2

VREG

VDD

GD

UVR

VDD

I_VDD

HS

UVR

VS

Ch. 1,3,5,7

SO

SPI

SupplyConcept_8HS.emf

Figure 11 TLE75080-ESH Internal Power Supply concept

When 3.0 V ≤ V_S≤ V_DD- V_SDIFFTLE75080-ESH operates in “Cranking Operative Range” (COR). In this condition the

current consumption from VDD pin increases while it decreases from VS pin where the total current

consumption remains within the specified limits. Figure 12 shows the voltage levels at VS pin where the

device goes in and out of COR. During the transition to and from COR operative region, I_VSand I_VDDchange

between values defined for normal operation and for COR operation. The sum of both current remains within

limits specified in “Overall current consumption” section (see Table 8).

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SPIDER+ 12V

Power Supply

V_S

V_DD+ V_SDIFF

V_DD

V_DD- V_SDIFF

3.0 V

t

COR

(no)

yes

(no)

t

I_VS

Supply transition

I_VDD

t

SupplyConcept_COR.emf

Figure 12 “Cranking Operative Range”

Furthermore, when V_S(UV)≤ V_S≤ V_S(OP)it may be not possible to switch ON a channel that was previously OFF.

All channels that are already ON keep their state unless they are switched OFF via SPI or via INn pins. An

overview of channel behavior according to different V_Sand V_DDsupply voltages is shown in Table 6 (the table

is valid after a successful power-up, see Chapter 6.1.1 for more details).

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SPIDER+ 12V

Power Supply

Table 6

Device capability as function of V_Sand V_DD

V_DD≤ V_DD(UV)

V_DD= V_DD(LOP)

V_DD> V_DD(LOP)

(V_DD(UV)= P_6.3.25)

(V_DD(LOP)= P_6.3.24)

V_S≤ 3.0 V

channels cannot be

controlled

channels cannot be

controlled

channels cannot be

controlled

3.0 V = V_S(UV),max

(P_6.3.1)

SPI registers reset

SPI registers available

SPI communication not

available (f_SCLK= 0 MHz)

SPI communication

possible (f_SCLK= 1 MHz)

(P_10.4.34)

SPI communication

possible (f_SCLK= 5 MHz)

(P_10.4.22)

Limp Home mode not

available

Limp Home mode available Limp Home mode available

(channels are OFF) (channels are OFF)

3.0 V < V_S≤ V_S(OP)

(V_S(OP)= P_6.3.2)

channels cannot be

controlled by SPI

channels can be switched channels can be switched

ON and OFF (SPI control)¹⁾ON and OFF (SPI control)¹⁾

(R_DS(ON)deviations possible) (R_DS(ON)deviations possible)

SPI registers reset

SPI registers available

SPI communication not

available (f_SCLK= 0 MHz)

SPI communication

possible (f_SCLK= 1 MHz)

(P_10.4.34)

SPI communication

possible (f_SCLK= 5 MHz)

(P_10.4.22)

Limp Home mode

available¹⁾(R_DS(ON)

deviations possible)

Limp Home mode

available¹⁾(R_DS(ON)

deviations possible)

Limp Home mode

available¹⁾(R_DS(ON)

deviations possible)

V_S≥ V_S(OP)

channels cannot be

controlled by SPI

channels can be switched channels can be switched

ON and OFF ON and OFF

(small R_DS(ON)dev. possible (small R_DS(ON)dev. possible

when V_S= V_S(EXT,LOW)when V_S= V_S(EXT,LOW)

)

SPI registers reset

SPI registers available

SPI communication not

available (f_SCLK= 0 MHz)

SPI communication

possible (f_SCLK= 5 MHz)

(P_10.4.22)

SPI communication

possible (f_SCLK= 5 MHz)

(P_10.4.22)

Limp Home mode available Limp Home mode available Limp Home mode available

(small R_DS(ON)dev. possible (small R_DS(ON)dev. possible (small R_DS(ON)dev. possible

when V_S= V_S(EXT,LOW)

)

when V_S= V_S(EXT,LOW)

)

when V_S= V_S(EXT,LOW))

1) undervoltage condition on V_Smust be considered - see Chapter 6.2.1 for more details

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SPIDER+ 12V

Power Supply

6.1

Operation Modes

TLE75080-ESH has the following operation modes:

•

Sleep mode

Idle mode

Active mode

Limp Home mode

The transition between operation modes is determined according to following levels and states:

•

logic level at IDLE pin

logic level at INn pins

OUT.OUTn bits state

HWCR.ACT bit state

HWCR_PWM.PWM0 and HWCR_PWM.PWM1 bits state

The state diagram including the possible transitions is shown in Figure 13. The behaviour of TLE75080-ESH as

well as some parameters may change in dependence from the operation mode of the device. Furthermore,

due to the undervoltage detection circuitry which monitors V_Sand V_DDsupply voltages, some changes within

the same operation mode can be seen accordingly.

The operation mode of the TLE75080-ESH can be observed by:

•

status of output channels

status of SPI registers

current consumption at VDD pin (I_VDD

)

current consumption at VS pin (I_VS)

The default operation mode to switch ON the loads is Active mode. If the device is not in Active mode and a

request to switch ON one or more outputs comes (via SPI or via Input pins), it will switch into Active or Limp

Home mode, according to IDLE pin status. Due to the time needed for such transitions, output turn-on time

t_ONwill be extended due to the mode transition latency.

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SPIDER+ 12V

Power Supply

init

IDLE = „high“

IDLE = „low“

INn = „low“

Sleep

INn = „high“

& IDLE = „low“

INn = „low“

& V_DD< V_DD(UV)

IDLE = „low“

& INn = „low“

Idle

Limp Home

HWCR.ACT= 0

& OUT.OUTn = 0

& HWCR_PWM.PWMn = 0

& INn = „low“

IDLE = „high“

Active

IDLE = „low“

& INn = „high“

HWCR.ACT= 1

or OUT.OUTn = 1

or HWCR_PWM.PWMn = 1

or INn = „high“

OpModesLED.emf

Figure 13 Operation Mode state diagram

Table 7 shows the correlation between device operation modes, V_Sand V_DDsupply voltages, and state of the

most important functions (channels operativity, SPI communication and SPI registers).

Table 7

Device function in relation to operation modes, V_Sand V_DDvoltages

Operation Function

Mode

Undervoltage

condition on V_S

V_DD≤ V_DD(UV)

Undervoltage

condition on V_S

V_DD> V_DD(UV)

V_Snot in

undervoltage

V_Snot in

undervoltage

V_DD>V_DD(UV)

1)

V

_DD≤ V_DD(UV)

Sleep

Channels

SPI comm.

SPI registers

Channels

not available

reset

not available

reset

not available

reset

not available

reset

Idle

not available

reset

not available

✓

not available

reset

not available

SPI comm.

SPI registers

Channels

✓

Active

not available

reset

not available

✓

✓ (IN pins only)

not available

reset

✓

SPI comm.

SPI registers

✓

Limp Home Channels

SPI comm.

not available

reset

not available

✓ (read-only)

✓ (read-only)²⁾

✓ (IN pins only)

not available

reset

✓ (IN pins only)

✓ (read-only)

✓ (read-only)²⁾

SPI registers

1) see Chapter 6.2.1 for more details

2) see Chapter 6.1.5 for a detailed overview

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SPIDER+ 12V

Power Supply

6.1.1

Power-up

The Power-up condition is satisfied when one of the supply voltages (V_Sor V_DD) is applied to the device and the

INn or IDLE pins are set to “high”. If V_Sis above the threshold V_S(OP)or if V_DDis above the threshold V_DD(LOP)the

internal power-on signal is set.

6.1.2

Sleep mode

When TLE75080-ESH is in Sleep mode, all outputs are OFF and the SPI registers are reset, independently from

the supply voltages. The current consumption is minimum. See parameters I_VDD(SLEEP)and I_VS(SLEEP), or

parameter I_SLEEPfor the whole device.

6.1.3

Idle mode

In Idle mode, the current consumption of the device can reach the limits given by parameters I_VDD(IDLE)and

I_VS(IDLE), or by parameter I_IDLEfor the whole device. The internal voltage regulator is working. Diagnosis

functions are not available. The output channels are switched OFF, independently from the supply voltages.

When V_DDis available, the SPI registers are working and SPI communication is possible. In Idle mode the ERRn

bits are not cleared for functional safety reasons.

6.1.4

Active mode

Active mode is the normal operation mode of TLE75080-ESH when no Limp Home condition is set and it is

necessary to drive some or all loads. Voltage levels of V_DDand V_Sinfluence the behavior as described at the

beginning of Chapter 6. Device current consumption is specified with I_VDD(ACTIVE)and I_VS(ACTIVE)(I_ACTIVEfor the

whole device). The device enters Active mode when IDLE pin is set to “high” and one of the input pins is set to

“high” or one OUT.OUTn bit is set to “1”. If HWCR.ACT is set to “0”, the device returns to Idle mode as soon as

all inputs pins are set to “low” and OUT.OUTn bits are set to “0”. If HWCR.ACT is set to “1”, the device remains

in Active mode independently of the status of input pins and OUT.OUTn bits. An undervoltage condition on

V_DDsupply brings the device into Idle mode, if all input pins are set to “low”. Even if the registers MAPIN0 and

MAPIN1 are both set to “00_H” but one of the input pins INn is set to “high”, the device goes into Active mode.

6.1.5

Limp Home mode

TLE75080-ESH enters Limp Home mode when IDLE pin is “low” and one of the input pins is set to “high”,

switching ON the channel connected to it. SPI communication is possible but only in read-only mode (SPI

registers can be read but cannot be written). More in detail:

•

UVRVS and LOPVDD are set to “1”

MODE bits are set to “01_B” (Limp Home mode)

TER bit is set to “1” on the first SPI command after entering Limp Home mode. Afterwards it works

normally

•

OLON and OLOFF bits is set to “0”

ERRn bits work normally

DIAG_OSM.OUTn bits can be read and work normally

All other registers are set to their default value and cannot be programmed as long as the device is in Limp

Home mode

See Table 6 for a detailed overview of supply voltage conditions required to switch ON channels 2 and 3 during

Limp Home. All other channels are OFF.

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SPIDER+ 12V

Power Supply

A transmission of SPI commands during transition from Active to Limp Home mode or Limp Home to Active

mode may result in undefined SPI responses.

6.1.6

Definition of Power Supply modes transition times

The channel turn-ON time is as defined by parameter t_ONwhen TLE75080-ESH is in Active mode or in Limp

Home mode. In all other cases, it is necessary to add the transition time required to reach one of the two

aforementioned Power Supply modes (as shown in Figure 14).

init

t_SLEEP2IDLE

t_IDLE2SLEEP

t_LH2SLEEP

t_SLEEP2LH

Sleep

t_ON

t_ACTIVE2SLEEP

Channel ON

Idle

Limp Home

t_ON

t_ACTIVE2IDLE

t_IDLE2ACTIVE

t_LH2ACTIVE

t_ACTIVE2LH

Active

OpModesTimings.emf

Figure 14 Transition Time diagram

6.2

Reset condition

One of the following 3 conditions resets the SPI registers to the default value:

•

V_DDis not present or below the undervoltage threshold V_DD(UV)

IDLE pin is set to “low”

a reset command (HWCR.RST set to “1”) is executed

–

ERRn bits are not cleared by a reset command (for functional safety)

UVRVS and LOPVDD bits are cleared by a reset command

In particular, all channels are switched OFF (if there are no input pin set to “high”) and the Input Mapping

configuration is reset.

6.2.1

Undervoltage on V_S

Between V_S(UV)and V_S(OP)the undervoltage mechanism is triggered. If the device is operative and the supply

voltage drops below the undervoltage threshold V_S(UV), the logic set the bit UVRVS to “1”. As soon as the supply

voltage VS is above the minimum voltage operative threshold V_S(OP), the bit UVRVS is set to “0” after the first

Standard Diagnosis readout. Undervoltage condition on VS influences the status of the channels, as described

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SPIDER+ 12V

Power Supply

in Table 6. Figure 15 sketches the undervoltage behavior (the “V_S- V_DS” line refers to a channel which is

programmed to be ON).

V_S

V_S(OP)

V_S(HYS)

V_S(UV)

t

V_S- V_DS

t

UVRVS

1

0

1

t

Supply_UVRVS.emf

Figure 15 V_SUndervoltage Behavior

6.2.2

Low Operating Power on V_DD

When V_DDsupply voltage is in the range indicated by V_DD(LOP), the bit LOPVDD is set to “1”. As soon as V_DD

_DD(LOP)the bit LOPVDD is set to “0” after the first Standard Diagnosis readout.

>

V

If V_DDsupply voltage is not present, a voltage applied to pins CSN or SO can supply the internal logic (not

recommended in normal operation due to internal design limitations).

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SPIDER+ 12V

Power Supply

6.3

Electrical Characteristics Power Supply

Table 8

Electrical Characteristics Power Supply

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C, all voltages with respect to ground, positive currents

flowing as described in Figure 3 (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

VS pin

Analog supply undervoltage V_S(UV)

shutdown

1.5

–

3.0

V

OUTn = ON

from V_DS≤ 1 V

to UVRVS = 1_B

R_L= 50 Ω

P_6.3.1

Analog supply minimum

operative voltage

V_S(OP)

–

4.0

OUT.OUTn = 1_B

from UVRVS = 1_B

to V_DS≤ 1 V

R_L= 50 Ω

P_6.3.2

1)

Undervoltage shutdown

hysteresis

V_S(HYS)

–

1

–

3

V

P_6.3.3

P_6.3.4

1)

Analog supply current

consumption in Sleep mode

with loads

I_VS(SLEEP)

0.1

µA

V_IDLEfloating

V

_INnfloating

V_CSN= V_DD

T_J≤ 85 °C

1)

Analog supply current

consumption in Sleep mode

with loads

I_VS(SLEEP)

–

0.1

–

µA

P_6.3.63

V_IDLEfloating

V

_INnfloating

V_CSN= V_DD

T_J≤ 85 °C

VS = 13.5 V

Analog supply current

consumption in Sleep mode

with loads

I_VS(SLEEP)

–

0.1

–

20

µA

V_IDLEfloating

V_INnfloating

P_6.3.5

P_6.3.6

V

_CSN= V_DD

T_J= 150 °C

Analog supply current

consumption in Idle mode

with loads

I_VS(IDLE)

2.2

mA

IDLE = “high”

V

_INnfloating

f_SCLK= 0 MHz

HWCR.ACT = 0_B

OUT.OUTn = 0_B

DIAG_IOL.OUTn =

0_B

V_CSN= V_DD

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SPIDER+ 12V

Power Supply

Table 8

Electrical Characteristics Power Supply (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C, all voltages with respect to ground, positive currents

flowing as described in Figure 3 (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Analog supply current

consumption in Idle mode

with loads (COR)

I_VS(IDLE)

–

0.3

mA

IDLE = “high”

_INnfloating

P_6.3.7

V

f_SCLK= 0 MHz

HWCR.ACT = 0_B

OUT.OUTn = 0_B

DIAG_IOL.OUTn =

0_B

V_CSN= V_DD

V_S≤ V_DD- 1 V

Analog supply current

consumption in Active mode

with loads - channels OFF

I_VS(ACTIVE)

–

7.7

5.0

mA

IDLE = “high”

V_INnfloating

P_6.3.10

P_6.3.14

f

_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 0_B

DIAG_IOL.OUTn =

0_B

V_CSN= V_DD

Analog supply current

consumption in Active mode

with loads - channels OFF

(COR)

I_VS(ACTIVE)

IDLE = “high”

V_INnfloating

f

_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 0_B

DIAG_IOL.OUTn =

0_B

V_CSN= V_DD

V_S≤ V_DD- 1 V

Analog supply current

I_VS(ACTIVE)

–

8.7

mA

IDLE = “high”

P_6.3.18

consumption in Active mode

with loads - channels ON

V_INnfloating

f_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 1_B

DIAG_IOL.OUTn =

0_B

DIAG_OLONEN.M

UX = 0100_B

V_CSN= V_DD

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Table 8

Electrical Characteristics Power Supply (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C, all voltages with respect to ground, positive currents

flowing as described in Figure 3 (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

2.3

Unit Note or

Test Condition

Number

Min.

Max.

Analog supply current

consumption in Active mode

with loads - channels ON

(COR)

I_VS(ACTIVE)

–

5.0

mA

IDLE = “high”

_INnfloating

P_6.3.22

V

f_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 1_B

DIAG_IOL.OUTn =

0_B

V_CSN= V_DD

V_S≤ V_DD- 1 V

VDD pin

Logic Supply Operating

voltage

V_DD(OP)

V_DD(LOP)

V_DD(UV)

3.0

1

–

5.5

4.5

3.0

V

f_SCLK= 5 MHz

P_6.3.23

P_6.3.24

P_6.3.25

Logic Supply Lower

Operating Voltage

–

Undervoltage shutdown

V_SI= 0 V

V

_SCLK= 0 V

V_CSN= 0 V

SO from “low” to

high impedance

1)

Logic supply current in

Sleep mode

I_VDD(SLEEP)

–

0.1

2.5

µA

P_6.3.26

V_IDLEfloating

V_INnfloating

V

_CSN= V_DD

T_J≤ 85 °C

Logic supply current in

Sleep mode

I_VDD(SLEEP)

–

10

µA

V_IDLEfloating

P_6.3.27

P_6.3.28

V

_INnfloating

V_CSN= V_DD

T_J= 150 °C

Logic supply current in Idle I_VDD(IDLE)

0.3

mA

IDLE = “high”

mode

V_INnfloating

f_SCLK= 0 MHz

HWCR.ACT = 0_B

OUT.OUTn = 0_B

V_CSN= V_DD

Logic supply current in Idle I_VDD(IDLE)

–

2.2

mA

IDLE = “high”

P_6.3.29

mode (COR)

V_INnfloating

f

_SCLK= 0 MHz

HWCR.ACT = 0_B

OUT.OUTn = 0_B

V_CSN= V_DD

V_S≤ V_DD- 1 V

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SPIDER+ 12V

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Table 8

Electrical Characteristics Power Supply (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C, all voltages with respect to ground, positive currents

flowing as described in Figure 3 (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Logic supply current in

Active mode - channels OFF

I_VDD(ACTIVE)

–

0.3

mA

IDLE = “high”

_INnfloating

P_6.3.30

V

f_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 0_B

V_CSN= V_DD

Logic supply current in

Active mode - channels OFF

(COR)

I_VDD(ACTIVE)

–

2.7

mA

IDLE = “high”

V_INnfloating

P_6.3.33

f

_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 0_B

V_CSN= V_DD

V_S≤ V_DD- 1 V

Logic supply current in

Active mode - channels ON

I_VDD(ACTIVE)

–

0.3

3.5

mA

IDLE = “high”

V_INnfloating

f_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 1

V_CSN= V_DD

P_6.3.35

P_6.3.66

Logic supply current in

Active mode - channels ON

(COR)

I_VDD(ACTIVE)

IDLE = “high”

V_INnfloating

f

_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 1_B

DIAG_IOL.OUTn =

0_B

DIAG_OLONEN.M

UX = 0100_B

V_CSN= V_DD

V_S≤ V_DD- 1 V

Overall current consumption

1)

Overall current

I_SLEEP

–

5

µA

P_6.3.40

consumption in Sleep mode

V_IDLEfloating

I_VS(SLEEP)+ I_VDD(SLEEP)

V

_INnfloating

_CSN= V_DD

T_J≤ 85 °C

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Power Supply

Table 8

Electrical Characteristics Power Supply (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C, all voltages with respect to ground, positive currents

flowing as described in Figure 3 (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

1)

Overall current

I_SLEEP

–

5

µA

P_6.3.64

consumption in Sleep mode

I_VS(SLEEP)+ I_VDD(SLEEP)

V_IDLEfloating

V_INnfloating

V

_CSN= V_DD

T_J≤ 85 °C

V_S= 13.5 V

Overall current

consumption in Sleep mode

I_SLEEP

–

30

µA

V_IDLEfloating

V_INnfloating

V_CSN= V_DD

P_6.3.41

P_6.3.42

I_VS(SLEEP)+ I_VDD(SLEEP)

T_J= 150 °C

Overall current

I_IDLE

2.5

mA

IDLE = “high”

consumption in Idle mode

I_VS(IDLE)+ I_VDD(IDLE)

V_INnfloating

f_SCLK= 0 MHz

HWCR.ACT = 0_B

OUT.OUTn = 0_B

DIAG_IOL.OUTn =

0_B

V_CSN= V_DD

Overall current

consumption in Active mode

- channels OFF

I_ACTIVE

–

8

9

–

mA

mV

IDLE = “high”

V_INnfloating

P_6.3.45

P_6.3.62

P_6.3.52

f_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 0_B

DIAG_IOL.OUTn =

0_B

I_VS(ACTIVE)+ I_VDD(ACTIVE)

V_CSN= V_DD

Overall current

consumption in Active mode

- channels ON

I_ACTIVE

–

IDLE = “high”

V_INnfloating

f_SCLK= 0 MHz

HWCR.ACT = 1_B

OUT.OUTn = 1_B

DIAG_IOL.OUTn =

0_B

I_VS(ACTIVE)+ I_VDD(ACTIVE)

V_CSN= V_DD

1)

Voltage difference between V_SDIFF

V_Sand V_DDsupply lines

200

Timings

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Power Supply

Table 8

Electrical Characteristics Power Supply (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C, all voltages with respect to ground, positive currents

flowing as described in Figure 3 (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

200

Unit Note or

Test Condition

Number

Min.

Max.

1)

Sleep to Idle delay

t_SLEEP2IDLE

–

400

µs

P_6.3.53

from IDLE pin to

TER + INST

register = 8680_H

(see

Chapter 10.6.1 for

details)

1)

Idle to Sleep delay

t_IDLE2SLEEP

–

100

200

µs

P_6.3.54

from IDLE pin to

Standard

Diagnosis = 0000_H

(see Chapter 10.5

for details)

externalpull-down

SO to GND

required

1)

Idle to Active delay

Active to Idle delay

t_IDLE2ACTIVE

–

100

200

µs

P_6.3.55

P_6.3.56

P_6.3.57

P_6.3.58

from INn or CSN

pins to MODE = 10_B

1)

t_ACTIVE2IDLE

from INn or CSN

pins to MODE = 11_B

1)

Sleep to Limp Home delay t_SLEEP2LH

Limp Home to Sleep delay t_LH2SLEEP

300

+t_ON

600

+t_ON

from INn pins

to V_DS= 10% V_S

1)

200

400

+t_OFF

from INn pins to

Standard

Diagnosis = 0000_H

(see

Chapter 10.6.1 for

details). External

pull-down SO to

GND required

1)

Limp Home to Active delay t_LH2ACTIVE

–

50

100

µs

P_6.3.59

from IDLE pin to

MODE = 10_B

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Power Supply

Table 8

Electrical Characteristics Power Supply (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C, all voltages with respect to ground, positive currents

flowing as described in Figure 3 (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

50

Unit Note or

Test Condition

Number

Min.

Max.

1)

Active to Limp Home delay t_ACTIVE2LH

–

100

µs

P_6.3.60

from IDLE pin to

TER + INST

register = 8683_H

(IN0 = IN1 = “high”)

or 8682_H(IN1 =

“high”, IN0 =

“low”) or 8681_H

(IN1 = “low”, IN0 =

“high”) (see

Chapter 10.5 for

details)

1)

Active to Sleep delay

t_ACTIVE2SLEEP

–

50

100

µs

P_6.3.61

from IDLE pin to

Standard

Diagnosis = 0000_H

(see

Chapter 10.6.1 for

details). External

pull-down SO to

GND required.

1) Not subject to production test - specified by design

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Power Stages

7

Power Stages

The TLE75080-ESH is an eight channels high-side relay switch. The power stages are built by N-channel lateral

power MOSFET transistors.

The supply voltages V_S1and V_S2can be connected to any potential between ground and V_S. A charge pump is

connected to the output MOSFET gate.

7.1

Output ON-state resistance

The ON-state resistance R_DS(ON)depends on the supply voltage as well as the junction temperature T_J.

7.1.1

Switching Resistive Loads

When switching resistive loads the following switching times and slew rates can be considered.

INn /

OUT.OUTn

t_ON

t_OFF

t

t_DELAY(ON)

t_DELAY(OFF)

V_DS

90% of V_S

70%

70% of V_S

dV /

dt_OFF

dV /

dt_ON

30%

30% of V_S

10% of V_S

t

SwitchON .emf

Figure 16 Switching a Resistive Load

7.1.2

Inductive Output Clamp

When switching off inductive loads, the voltage across the power switch rises to V_DS(CL)potential, because the

inductance intends to continue driving the current. The potential at Output pin is not allowed to go below

V_OUT(CL). The voltage clamping is necessary to prevent device destruction.

Figure 17 shows a concept drawing of the implementation. Nevertheless, the maximum allowed load

inductance is limited. The clamping structure protects the device in all operative modes (Sleep, Idle, Active,

Limp Home).

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Power Stages

V_S

High-side

Channel

VSn

V_DS

V_DS(CL)

I_{L_ S}

V_OUTn

OUTn

V_OUT(CL)

L,

R_L

I_L

GND

PowerStage_HS.emf

Figure 17 Output Clamp concept

7.1.3

Maximum Load Inductance

During demagnetization of inductive loads, energy has to be dissipated in the TLE75080-ESH. Equation (7.1)

and Equation (7.2) can be used for high-side switches :

R_LI_L

V_OUTS(CL)

--------------------------

R_L

L

R_L

æ

ö

ø

--------------------------

V_OUTS(CL)

------

E = (V_S– V_OUTS(CL)

)

ln 1 –

è

+ I_L

(7.1)

(7.2)

R_LI_L

V_OUT(CL)

-----------------------

R_L

L

æ

ö

ø

-----------------------

------

E = (V_S– V_OUT(CL)

)

ln 1 –

+ I_L

è

V_OUT(CL)

R_L

The maximum energy, which is converted into heat, is limited by the thermal design of the component. The

E_ARvalue provided in Table 2 assumes that all channels can dissipate the same energy when the inductances

connected to the outputs are demagnetized at the same time.

7.2

Inverse Current Behavior

During inverse current (V_OUTn> V_Sn) the affected channels stays in ON- or in OFF- state. Furthermore, during

applied inverse currents the ERRn bit can be set if the channel is in ON-state and the over temperature

threshold is reached.

The general functionality (switch ON and OFF, protection, diagnostic) of unaffected channels is not influenced

by inverse currents applied to other channels. Parameter deviations are possible especially for the following

ones (Over Temperature protection is not influenced):

•

Switching capability: t_ON, t_OFF, dV/dt_ON, -dV/dt_OFF

Protection: I_L(OVL0), I_L(OVL1)

Diagnostic: V_OUT(OL), I_L(OL)

Reliability in Limp Home condition for the unaffected channels is unchanged.

Note:

No protection mechanism like temperature protection or over load protection is active during

applied inverse currents. Inverse currents cause power losses inside the DMOS, which increase the

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Power Stages

overall device temperature. This could lead to a switch OFF of unaffected channels due to Over

Temperature

7.3

Switching Channels in parallel

In case of appearance of a short circuit with channels in parallel, it may happen that the two channels switch

OFF asynchronously, therefore bringing an additional thermal stress to the channel that switches OFF last. In

order to avoid this condition, it is possible to parametrize in the SPI registers the parallel operation of two

neighbour channels (bits HWCR.PAR). When operating in this mode, the fastest channel to react to an Over

Load or Over Temperature condition will deactivate also the other. The inductive energy that two channels

can handle once set in parallel is lower than twice the single channel energy (see P_7.6.11). It is possible to

synchronize the following couples of channels:

•

channel 0 and channel 2 → HWCR.PAR (0) set to “1”

channel 1 and channel 3 → HWCR.PAR (1) set to “1”

channel 4 and channel 6 → HWCR.PAR (2) set to “1”

channel 5 and channel 7 → HWCR.PAR (3) set to “1”

The synchronization bits influence only how the channels react to Over Load or Over Temperature conditions.

Synchronized channels have to be switched ON and OFF individually by the micro-controller.

7.4

“Bulb Inrush Mode” (BIM)

Although TLE75080-ESH is optimized for relays and LED, it may be necessary to use one or more of the outputs

to drive small lamps (typically 2 W) or electronic loads with a big input capacitor. In such operative conditions,

at the switch ON an inrush current may appear, reaching the overload current threshold which latches the

channel OFF (see Chapter 8.1 for further details). In normal operation the device waits until the

microcontroller sends an SPI command to clear the latches (register HWCR_OCL) allowing the channel to turn

ON again. Usually this delay is too long to transfer enough energy to the load.

If the corresponding bit BIM.OUTn is set to “1”, in case the channel reaches the overload current threshold or

the overtemperature threshold and latches OFF, it restarts automatically after a time t_INRUSH, allowing the load

to go out of the inrush phase. A time diagram is shown in Figure 18. As shown, the counter starts when the

channel is switched ON. Every channel switch OFF (independently from the entity controlling the channel - see

Figure 19 for further details) resets the bit BIM.OUTn to “0”.

While BIM.OUTn bits are set to “1”, ERRn bits may be also set to “1” but this doesn’t latch the channel OFF.

An internal timer set the bit BIM.OUTn back to “0” after 40 ms (parameter t_BIM) to prevent an excessive thermal

stress to the channel, especially in case of short circuit at the output.

TLE75080-ESH allows a per-channel selection of Bulb Inrush Mode (BIM) in order to be fully flexible without

any additional reliability risk.

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Power Stages

INn

OUT.OUTn

t

BIM.OUTn

t_{BI M}

I_Ln

I_L(OVL0)

I_L(OVL1)

t

t_INRUSH

t_OVLIN

ERRn

0

1

0

1

0 1

1

t

PowerStage_BIM.emf

Figure 18 Bulb Inrush Mode (BIM) operation

7.5

Automatic PWM Generator

The TLE75080-ESH has two independent automatic PWM generator implemented. Each PWM generator can

be assigned to one or more channels, and can be programmed with a different duty cycle and frequency.

Both PWM generator refer to a base frequency f_INTgenerated by an internal oscillator. This base frequency can

be adjusted using HWCR_PWM.ADJ bits as described in Table 9.

Table 9

bit content

0000_B

0001_B

0010_B

0011_B

0100_B

0101_B

0110_B

0111_B

1000_B

1001_B

1010_B

1011_B

1100_B

1101_B

1110_B

1111_B

HWCR_PWM.ADJ coefficients overview

absolute delta to f_INT

(reserved)

-37.2%

relative delta between steps

(reserved)

-5.2%

-5.1%

-5.9%

-5.5%

-4.6%

-5.1%

-5.8%

–

-31.9%

-26.9%

-21.0%

-15.5%

-10.9%

-5.8%

–

+4.3%

+4.6%

+5.1%

+5.6%

+6.1%

+6.8%

+7.6%

+8.9%

+14.0%

+19.5%

+25.6%

+32.4%

+40.0%

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Power Stages

For each PWM generator 4 parameters can be set:

•

duty cycle (bits PWM_CR0.DC for PWM Generator 0)

–

8 bits are available to achieve 0.39% duty cycle resolution

when the micro-controller programs a new duty cycle, the PWM generator waits until the previous cycle

is completed before using the new duty cycle (this happens also when the duty cycle is either 0% or

100% - the new duty cycle is taken with the next PWM cycle)

–

the maximum duty cycle achievable is 99.61% (PWM_CR0.DC set to “11111111_B”). It is possible to

achieve 100% by setting PWM_CR0.FREQ to “11_B”

•

frequency (bits PWM_CR0.FREQ for PWM Generator 0)

–

with 2 bits is possible to select the divider for f_INTto achieve the needed duty cycle

00_B= f_INT/ 1024 (when f_INT= 102.4 kHz the corresponding PWM frequency is 100 Hz)

01_B= f_INT/ 512 (corresponding to 200 Hz)

10_B= f_INT/ 256 (corresponding to 400 Hz)

channel output control and mapping registers PWM_OUT and PWM_MAP)

–

any channel can be mapped to each PWM Generator

together with 2 parallel input it is possible to have 4 independent PWM groups of channels with low

effort from the point of view of micro-controller resources and SPI data traffic

Figure 19 expands the concept shown in Figure 10 adding the PWM Generators.

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Power Stages

IN1

Limp Home mode

(default )

I_IN1

&

MAPIN1

8

IN0

Limp Home mode

(default )

Channel 7

Channel 6

I_IN0

Channel 5

OR

Channel 4

8

Channel 3

Channel 2

Channel 1

&

Channel 0

MAPIN0

OUT

8

OR

8

PWM_OUT

PWM Gen. 0

PWM_MAP

PWM Gen. 1

8

&

8

OR

8

PWM_Mapping.emf

Figure 19 PWM Generator Mappings

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Power Stages

7.6

Electrical Characteristics Power Stages

Table 10 Electrical Characteristics: Power Stage

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Output Characteristics

1)

On-State Resistance

R_DS(ON)

I_L(NOM)

–

1.0

1.8

330

–

Ω

P_7.6.1

P_7.6.2

P_7.6.3

T_J= 25 °C

On-State Resistance

2.2

T_J= 150 °C

I_L= I_L(EAR)= 220 mA

1)

Nominal load current

(all channels active)

500²⁾³⁾mA

T_A= 85 °C

T_J≤ 150 °C

1)

Nominal load current

(all channels active)

I_L(NOM)

–

260

470

220

P_7.6.4

P_7.6.5

P_7.6.8

T_A= 105 °C

T_J≤ 150 °C

1)

Nominal load current

(half of channels active)

I_L(NOM)

T_A= 85 °C

T_J≤ 150 °C

1)

Load current for maximum I_L(EAR)

energy dissipation -

repetitive

–

mA

T_A= 85 °C

T_J≤ 150 °C

(all channels active)

1)

Inverse current capability

per channel

-I_L(IC)

–

I_L(EAR)mA

P_7.6.9

No influences on

switching

functionality of

unaffected

channels -

parameter

deviations

possible

1)

Maximum energy

E_AR

–

15

mJ

P_7.6.11

dissipation repetitive pulses

- 2*I_L(EAR)

(two channels in parallel)

T_J(0)= 85 °C

I

_L(0)= 2*I_L(EAR)

2*10⁶cycles

HWCR.PAR = “1”

for affected

channels

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Power Stages

Table 10 Electrical Characteristics: Power Stage (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Power stage voltage drop at V_DS(OP)

–

1

V

R_L= 50 Ω

P_7.6.15

low battery

V_S= V_S(OP),max

V_S1= V_S(OP),max

V_S2= V_S(OP),max

refer to Figure 17

Drain to Source Output

clamping voltage

V_DS(CL)

42

46

–

55

V

I_L= 20 mA

V_S= V_Sn= 36 V

P_7.6.16

P_7.6.18

Source to Ground Output

clamping voltage

V_OUT(CL)

-25

-16

I_L= 20 mA

V_S= V_Sn= 7 V

1)

Output leakage current

(each channel)

T_J≤ 85 °C

I_L(OFF)

–

0.01

0.5

µA

P_7.6.47

V_IN= 0 V or floating

V_DS= 28 V

V

_{OUT_S}= 1.5V

OUT.OUTn = 0

T_J≤ 85 °C

1)

Output leakage current

(each channel)

T_J= 150 °C

I_L(OFF)

0.1

5

µA

P_7.6.49

V_IN= 0 V or floating

V

_DS= 28 V

_{OUT_S}= 1.5V

OUT.OUTn = 0

T_J= 150 °C

Timings

Turn-ON delay

(from INn pin or bit to V_OUT

10% V_S)

t_DELAY(ON)

t_DELAY(OFF)

t_ON

1

6

4

8

µs

R_L= 50 Ω

V_S= 13.5 V

Active mode or

Limp Home mode

P_7.6.35

P_7.6.36

P_7.6.37

P_7.6.38

=

Turn-OFF delay

(from INn pin or bit to V_OUT

90% V_S)

6

12

35

R_L= 50 Ω

V_S= 13.5 V

Active mode or

Limp Home mode

Turn-ON time

(from INn pin or bit to V_OUT

90% V_S)

15

R_L= 50 Ω

V_S= 13.5 V

Active mode or

Limp Home mode

Turn-OFF time

(from INn pin or bit to V_OUT

10% V_S)

t_OFF

R_L= 50 Ω

V_S= 13.5 V

Active mode or

Limp Home mode

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Power Stages

Table 10 Electrical Characteristics: Power Stage (cont’d)

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

0

Unit Note or

Test Condition

Number

Min.

Max.

Turn-ON/OFF matching

t_ON- t_OFF

-10

10

µs

R_L= 50 Ω

P_7.6.39

V_S= 13.5 V

Active mode or

Limp Home mode

Turn-ON slew rate

V_DS= 30% to 70% V_S

dV/dt_ON

0.7

1.3

1.9

V/µs R_L= 50 Ω

V_S= 13.5 V

Active mode or

Limp Home mode

V/µs R_L= 50 Ω

P_7.6.40

P_7.6.41

Turn-OFF slew rate

-dV/dt_OFF

V_DS= 70% to 30% V_S

V_S= 13.5 V

Active mode or

Limp Home mode

1)

Bulb Inrush Mode

restart time

t_INRUSH

t_BIM

–

40

–

µs

P_7.6.42

P_7.6.43

Active mode

1)

Bulb Inrush Mode

reset time

40

ms

Active mode

PWM Generator

Internal reference frequency f_INT

80

-15

–

102

–

125

15

kHz

%

HWCR_PWM.ADJ P_7.6.44

= 1000_B

1)

Internalreferencefrequency f_INT(VAR)

variation

P_7.6.56

1)

Internal reference frequency t_SYNC

5

10

µs

P_7.6.45

synchronization time

HWCR_PWM.ADJ

= 1000_B

1) Not subject to production test - specified by design

2) If one channel has I_L(NOM),maxapplied, the remaining channels must be underloaded accordingly so that T_J< 150°C

3) I_L(NOM),maxcan reach I_L(OVL1),min

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Protection Functions

8

Protection Functions

8.1

Over Load Protection

The TLE75080-ESH is protected in case of over load or short circuit of the load. There are two over load current

thresholds (see Figure 20):

•

I

_L(OVL0)between channel switch ON and t_OVLIN

I_L(OVL1)after t_OVLIN

Every time the channel is switched OFF for a time longer than 2 * t_SYNCthe over load current threshold is set

back to I_L(OVL0)

.

INn

OUT.OUTn

t

I_L(OVL0)

I_L(OVL)

I_{L(OVL 1)}

t

t_OVLIN

OverLoadStep.emf

Figure 20 Over Load current thresholds

In case the load current is higher than I_L(OVL0)or I_L(OVL1), after time t_OFF(OVL)the over loaded channel is switched

OFF and the according diagnosis bit ERRn is set. The channel can be switched ON after clearing the protection

latch by setting the corresponding HWCR_OCL.OUTn bit to “1”. This bit is set back to “0” internally after de-

latching the channel. Please refer to Figure 21 for details.

INn

OUT.OUTn

t

I_Ln

I_L(OVLn)

t_OFF(OVL)

t

ERRn

0

1

0

t

SPI command to set

HWCR_OCL.OUTn = 1_b

t

HWCR_OCL.OUTn

0

1

0

t

OverLoad.emf

Figure 21 Latch OFF at Over Load

8.2

Over Temperature Protection

A temperature sensor is integrated for each channel, causing an overheated channel to switch OFF to prevent

destruction. The according diagnosis bit ERRn is set (combined with Over Load protection). The channel can

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SPIDER+ 12V

Protection Functions

be switched ON after clearing the protection latch by setting the corresponding HWCR_OCL.OUTn bit to “1”.

This bit is set back to “0” internally after de-latching the channel.

8.3

Over Temperature and Over Load Protection in Limp Home mode

When TLE75080-ESH is in Limp Home mode, channels 2 and 3 can be switched ON using the input pins. In case

of Over Load, Short Circuit or Over Temperature the channels switch OFF. If the input pins remain “high”, the

channels restart with the following timings:

•

10 ms (first 8 retries)

20 ms (following 8 retries)

40 ms (following 8 retries)

80 ms (as long as the input pin remains “high” and the error is still present)

If at any time the input pin is set to “low” for longer than 2*t_SYNC, the restart timer is reset. At the next channel

activation while in Limp Home mode the timer starts from 10 ms again. See Figure 22 for details. Over Load

current thresholds behave as described in Chapter 8.1.

IN0

IN1

t

I_L2

I_L3

0

1

0

1

8

1

8

1

8

t_RETRY0(LH)

t_RETRY1(LH)

t_RETRY2(LH)

t_RETRY3(LH)

t_RETRY0(LH)

t

10 ms

20 ms

40 ms

80 ms

10 ms

LHrestart.emf

Figure 22 Restart timer in Limp Home mode

8.4

Reverse Polarity Protection

In Reverse Polarity (also known as Reverse Battery) condition, High-Side channels have Reversave™

functionality. Each ESD diode of the logic and supply pins contributes to total power dissipation. Channels

with Reversave™ functionality are switched ON almost with the same R_DS(ON)(see parameter R_DS(REV)). The

reverse current through the channels has to be limited by the connected loads. The current through digital

power supply V_DDand input pins has to be limited as well (please refer to the Absolute Maximum Ratings listed

on Chapter 4.1).

Note:

No protection mechanism like temperature protection or current limitation is active during reverse

polarity.

8.5

Over Voltage Protection

In the case of supply voltages between V_S(SC)and V_S(LD)the output transistors are still operational and follow

the input pins or the OUT register.

In addition to the output clamp for inductive loads as described in Chapter 7.1.2, there is a clamp mechanism

available for over voltage protection for the logic and all channels, monitoring the voltage between VS and

GND pins (V_S(AZ)).

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Protection Functions

8.6

Electrical Characteristics Protection

Table 11 Electrical Characteristics Protection

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Over Load

Over Load detection current I_L(OVL0)

1.3

1.7

2.3

A

T_J= -40 °C

1)

P_8.8.19

P_8.8.20

1.25

1.55

T_J= 25 °C

T_J= 150 °C

Over Load detection current I_L(OVL0)

Over Load detection current I_L(OVL1)

1

1.45

0.95

0.85

2

A

P_8.8.21

P_8.8.22

P_8.8.23

0.7

0.65

1.3

T_J= -40 °C

1)

T_J= 25 °C

Over Load detection current I_L(OVL1)

0.5

0.8

1.25

260

A

T_J= 150 °C

1)

P_8.8.24

P_8.8.5

Over Load threshold switch t_OVLIN

110

170

µs

delay time

1)

Over Load shut-down delay t_OFF(OVL)

4

7

11

µs

P_8.8.26

time

BIM.OUTn=HWCR

.PAR=0_B

Over Temperature and Over Voltage

Thermal shut-down

temperature

T_J(SC)

150

42

175¹⁾

50

220¹⁾

60

°C

V

P_8.8.7

P_8.8.8

Over voltage protection

V_S(AZ)

I_VS= 10 mA

Sleep mode

Reverse Polarity

1)

On-State Resistance during R_DS(REV)

Reverse Polarity

(High-Side channels )

–

1.0

1.8

–

Ω

P_8.8.11

P_8.8.12

V_S= -V_S(REV)

I_L= I_L(EAR)

T_J= 25 °C

1)

On-State Resistance during R_DS(REV)

Reverse Polarity

(High-Side channels )

V_S= -V_S(REV)

I_L= I_L(EAR)

T_J= 150 °C

Timings

1)

Restart time in Limp Home t_RETRY0(LH)

mode

7

10

20

40

80

13

ms

P_8.8.13

P_8.8.14

P_8.8.15

P_8.8.16

Restart time in Limp Home t_RETRY1(LH)

mode

14

28

56

26

Restart time in Limp Home t_RETRY2(LH)

mode

52

Restart time in Limp Home t_RETRY3(LH)

104

mode

Datasheet

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SPIDER+ 12V

Protection Functions

1) Not subject to production test - specified by design

Datasheet

46

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TLE75080-ESH

SPIDER+ 12V

Diagnosis

9

Diagnosis

The SPI of TLE75080-ESH provides diagnosis information about the device and the load status. Each channel

diagnosis information is independent from other channels. An error condition on one channel has no

influence on the diagnostic of other channels in the device (unless configured to work in parallel, see

Chapter 7.3 for more details).

9.1

Over Load and Over Temperature

When either an Over Load or an Over Temperature occurs on one channel, the diagnosis bit ERRn is set

accordingly. As described in Chapter 8.1 and Chapter 8.2, the channel latches OFF and must be reactivated

setting corresponding HWCR_OCL.OUTn bit to “1”.

9.2

Output Status Monitor

The device compares each channel V_OUTwith V_OUT(OL)and sets the corresponding DIAG_OSM.OUTn bits

accordingly. The bits are updated every time DIAG_OSM register is read.

•

V_OUT> V_OUT(OL)→ DIAG_OSM.OUTn = “1”

A diagnosis current I_OLin parallel to the power switch can be enabled by programming the DIAG_IOL.OUTn

bit, which can be used for Open Load at OFF detection. Each channel has its dedicated diagnosis current

source. If the diagnosis current I_OLis enabled or if the channel changes state (ON → OFF or OFF → ON) it is

necessary to wait a time t_OSMfor a reliable diagnosis. Enabling I_OLcurrent sources increases the current

consumption of the device. Even if an Open Load is detected, the channel is not latched OFF.

See Figure 23 for a timing overview (the values of DIAG_IOL.OUTn refer to a channel in normal operation

properly connected to the load).

INn

OUT.OUTn

t

Output voltage

comparator

0

x

1

x

0

t

t_ON+ t_OSM

t_OFF+ t_OSM

SPI readout of

DIAG_OSM.OUTn

t

DIAG_OSM.OUTn

x

1

x

0

OutStatMon_timings.emf

Figure 23 Output Status Monitor timing

Output Status Monitor diagnostic is available when V_S= V_S(NOR)and V_DD≥ V_DD(UV)

.

Due to the fact that Output Status Monitor checks the voltage level at the outputs in real time, for Open Load

in OFF diagnostic it is necessary to synchronize the reading of DIAG_OSM register with the OFF state of the

channels.

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Diagnosis

Figure 24 shows how Output Status Monitor is implemented at concept level.

V_S

High-side

Channel

V_OUT> V_OUT(OL)à DIAG_OSM.OUTn = „1"

VSn

V_DS

I_OL

DIAG_OSM.OUTn

OUTn

V_OUTn

V_OUT(OL)

R_OL

I_OL

GND

OutStatMon_HS.emf

Figure 24 Output Status Monitor - concept

In Standard Diagnosis the bit OLOFF represents the OR combination of all DIAG_OSM.OUTn bits for all

channels in OFF state which have the corresponding current source I_OLactivated.

9.3

Open Load at ON

Each channel has the possibility of Open Load at ON diagnosis, which can be controlled programming

DIAG_OLONEN.MUX bits. By default after a reset Open Load at ON diagnosis is not active. The device

compares I_{L_Sn}with I_L(OL)and sets the DIAG_OLON.OUTn accordingly:

•

I_{L_Sn}< I_L(OL)→ DIAG_OLON.OUTn = “1” if V_Sn> V_OUT(OL)

9.3.1

Open Load at ON - direct channel diagnosis

When DIAG_OLONEN.MUX bits are programmed with a value corresponding to a channel (0000_B→ 0111_B), the

internal multiplexer checks for Open Load at ON condition on the selected channel. It is recommended that

the channel is ON for at least t_ONbefore activating the diagnosis. After a time t_OLONSETthe corresponding

DIAG_OLON.OUTn bit for the selected channel is available. All the other bits in the DIAG_OLON register are

set to default (“0_B”). The bits are updated every time the register is read.

When a channel is selected, the corresponding DIAG_OLON.OUTn bit content is mirrored also in the Standard

Diagnosis (bit OLON). In case of several register readouts in sequence the register content is updated at every

read request from micro-controller. See Figure 25 for further details.

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Diagnosis

INn

OUT.OUTn

t

DIAG_OLONEN.MUX

1111

≠ 1111 (ch. n)

t

I_Ln

I_L(OL)

t_OLONSW

t_ON

t_OLONSET

DIAG_OLON.OUTn

0

1

0

t

SPI readout of

DIAG_OLON.OUTn

OpenLoadON_direct.emf

Figure 25 Open Load at ON timings (direct channels diagnosis)

9.3.2

Open Load at ON - diagnosis loop

When DIAG_OLONEN.MUX bits are programmed with the value 1010_B, the device starts a diagnosis loop

where all channels are checked for Open Load at ON. The internal multiplexer is controlled by the internal

logic, therefore there is no need for the micro-controller to send any additional command.

First the internal logic checks all channels which are directly driven by the micro-controller and not configured

to be driven by the internal PWM generator, then the internal logic checks all channels which are configured

to be driven by the internal PWM generator.

•

Diagnosis sequence for channels driven directly by the micro-controller

–

First channel checked: channel 0. It is recommended that the channels are ON at least t_ONbefore

activating the diagnosis loop.

After a time t_OLONSET+ t_SYNCthe diagnosis for the first channel is completed (DIAG_OLON.OUTn bit is

updated)

The internal multiplexer is set to the next channel. After a time t_OLONSW+ t_SYNCthe diagnosis is completed

(DIAG_OLON.OUTn bit is updated) for the currently selected channel. This step is repeated for all

remaining directly driven channels.

–

If one channel is OFF when the diagnosis is performed, the corresponding DIAG_OLON.OUTn is set to

“0_B”

•

Diagnosis sequence for channels driven by the internal PWM Generators (see Chapter 7.5)

–

These channels are diagnosed only after all channels directly driven by micro-controller are checked

Channels mapped to PWM Generator 0 are diagnosed first

After a time t_OLONSETthe channel activation (switch ON) is the trigger event to perform Open Load at ON

diagnosis for the first channel

–

After a time t_ONMAX+ t_OLONSWthe diagnosis for the first channel is completed (DIAG_OLON.OUTn bit is

updated)

The internal multiplexer is set to the next channel. After a time t_OLONSWthe diagnosis is completed

(DIAG_OLON.OUTn bit is updated) for the currently selected channel. This step is repeated for all

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Diagnosis

remaining PWM generator driven channels.

If the channel is in OFF state during the PWM period, the internal logic waits for the ON state to perform

the diagnosis. After a time t_ONMAX+ t_OLONSWthe diagnosis for that channel is completed.

–

The minimum ON time for a reliable diagnosis is > t_ONMAX+ t_OLONSW. If the ON time is < t_ONMAX+ t_OLONSWthe

corresponding DIAG_OLON.OUTn is set to “0_B”.

When the loop finishes, DIAG_OLONEN.MUX bits are set back to 1111_B(default value) and DIAG_OLON.OUTn

bits store the last diagnosis loop result. It is necessary to start another diagnosis loop to update the register

content.

Figure 26 shows the timing in case of channels driven directly by micro-controller, while Figure 27 represents

the case with channels driven by internal PWM Generators.

DIAG_OLONEN.MUX

1111

1010

1111

t

I_L0

Ch. 0

(ON)

DIAG_OLON.OUT0

0

t_OLONSET

t

Ch. 1 (ON in

Open Load)

I_L(OL)

I_L1

t

DIAG_OLON.OUT1

1

t

t_OLONSW

I_L7

Ch. 7 (OFF)

t

DIAG_OLON.OUT7

0

t

t_OLONSWt_OLONSWt_OLONSWt_OLONSWt_OLONSWt_OLONSW

OpenLoadON_loop_ext_8ch.emf

Figure 26 Open Load at ON timings (diagnosis loop - channels driven by micro-controller directly)

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Diagnosis

DIAG_OLONEN.MUX 1111

1010

t

PWM Generator

t

Multiplexer switch

for diagnosis

(not allowed)

Allowed

(not allowed)

t_OLONSWt_ONMAX

Allowed

t_OLONSW

t_ONMAX

DIAG_OLON.OUTn

(updated)

t

t_OLONSW

DIAG_OLON.OUTn+1

DIAG_OLON.OUTn+2

DIAG_OLON.OUTn+3

(updated)

t

t_OLONSW

(updated)

t

t_OLONSW

(updated)

t_OLONSW

OpenLoadON_loop_int.emf

Figure 27 Open Load at ON timings (diagnosis loop - channels driven by internal PWM Generators

9.3.3

OLON bit

The OLON bit can assume the following values:

•

“0” = no Open Load at ON state detected, or the channel is OFF when the diagnosis is performed

“1” = Open Load at ON state detected

According to the setting of DIAG_OLONEN.MUX different information are reported in the Standard Diagnosis.

•

DIAG_OLONEN.MUX set to 0000_B→ 0111_B: The OLON bit shows the Open Load at ON state diagnosis

performed on the selected channel. The information is updated at every Standard Diagnosis readout.

DIAG_OLONEN.MUX set to 1010_B: the OLON bit shows the “OR” combination of all bits in DIAG_OLON

register. The information is updated while the diagnosis loop is running.

DIAG_OLONEN.MUX set to 1111_B: the OLON bit shows the result of the latest diagnosis loop performed. It

is necessary to start another diagnosis loop to update the information.

DIAG_OLONEN.MUX set to any other value: The OLON bit is set to “0”. These values of

DIAG_OLONEN.MUX bits are reserved and should not be used in the application.

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SPIDER+ 12V

Diagnosis

9.4

Electrical Characteristics Diagnosis

Table 12 Electrical Characteristics Diagnosis

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Output Status Monitor

1)

2)

Output Status Monitor

comparator settling time

t_OSM

–

20

µs

V

P_9.5.1

P_9.5.3

P_9.5.5

Output Status Monitor

threshold voltage

V_OUT(OL)

I_OL

3

3.3

85

3.6

100

Output diagnosis current

70

µA

V

_OUT= 3.3 V

1)

Open Load equivalent

resistance

R_OL

30

40

–

300

76

kΩ

P_9.5.6

P_9.5.7

Open Load at ON

1)

Open Load at ON Diagnosis t_ONMAX

waiting time before mux

activation

58

µs

1)

Open Load at ON Diagnosis t_OLONSET

settling time

–

1

–

1

20

10

6

40

20

10

–

µs

P_9.5.8

P_9.5.9

P_9.5.10

P_9.5.11

P_9.5.12

Open Load at ON Diagnosis t_OLONSW

channel switching time

µs

Open Load detection

threshold current

I_L(OL)

mA

T_J= -40 °C

1)

Open Load detection

threshold current

6

T_J= 25 °C

T_J= 150 °C

Open Load detection

threshold current

6

10

1) Not subject to production test - specified by design

2) Output status detection voltages are referenced to ground (GND pin)

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

10

Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines:

SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of

CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted

out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo

8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits.

Otherwise a TER bit is asserted. In this way the interface provides daisy chain capability with 16 bit as well as

with 8 bit SPI devices.

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

SO

SI

CSN

SCLK

time

SPI_16bit.emf

Figure 28 Serial Peripheral Interface

10.1

SPI Signal Description

CSN - Chip Select

The system microcontroller selects the TLE75080-ESH by means of the CSN pin. Whenever the pin is in “low”

state, data transfer can take place. When CSN is in "high" state, any signals at the SCLK and SI pins are ignored

and SO is forced into a high impedance state.

CSN “high” to “low” Transition

•

The requested information is transferred into the shift register.

SO changes from high impedance state to "high" or “low” state depending on the logic OR combination

between the transmission error flag (TER) and the signal level at pin SI. This allows to detect a faulty

transmission even in daisy chain configuration.

•

If the device is in Sleep mode, SO pin remains in high impedance state and no SPI transmission occurs.

TER

SI

SO

OR

1

0

SO

S

SI

SPI

CSN

SCLK

S

SPI _TER.emf

Figure 29 Combinatorial Logic for TER bit

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Serial Peripheral Interface (SPI)

CSN “low” to "high" Transition

•

Command decoding is only done, when after the falling edge of CSN exactly a multiple (1, 2, 3, …) of eight

SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the

transmission error bit (TER) is set and the command is ignored.

Data from shift register is transferred into the addressed register.

SCLK - Serial Clock

This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the

falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the

serial clock. It is essential that the SCLK pin is in “low” state whenever chip select CSN makes any transition,

otherwise the command may be not accepted.

SI - Serial Input

Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling

edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to

Chapter 10.5 for further information.

SO Serial Output

Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN

pin goes to “low” state. New data appears at the SO pin following the rising edge of SCLK.

Please refer to Chapter 10.5 for further information.

10.2

Daisy Chain Capability

The SPI of TLE75080-ESH provides daisy chain capability. In this configuration several devices are activated by

the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see

Figure 30), in order to build a chain. The end of the chain is connected to the output and input of the master

device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the

SCLK line of each device in the chain.

device 1

SPI

device 2

SPI

device 3

SPI

SI

SO SI

SO

MO

MI

MCSN

MCLK

SPI_DaisyChain_1.emf

Figure 30 Daisy Chain Configuration

In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK.

The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is finished.

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Serial Peripheral Interface (SPI)

In single chip configuration, the CSN line must turn “high” to make the device acknowledge the transferred

data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using

three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices (depending on

how many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must turn “high” (see

Figure 31).

SO device 3

SI device 3

SO device 2

SI device 2

SO device 1

SI device 1

MI

MO

MCSN

MCLK

SPI_DaisyChain_2.emf

Figure 31 Data Transfer in Daisy Chain Configuration

10.3

Timing Diagrams

t_CSN(lead)

t_CSN(lag)

t_CSN(td)

t_{SCLK(P )}

V_CSN(H)

V_CSN(L)

CSN

t_{SCLK (H)}

t_{SCLK (L)}

V_SCLK(H)

V_SCLK(L)

SCLK

SI

t_{SI (s u)}

t_{SI (h)}

V_{SI (H)}

V_{SI (L)}

t_SO(en)

t_{SO(v )}

t_{SO (dis )}

V_SO(H)

V_SO(L)

SO

SPI _Timings.emf

Figure 32 Timing Diagram SPI Access

Datasheet

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Serial Peripheral Interface (SPI)

10.4

Electrical Characteristics

V_DD= 3 V to 5.5 V, V_S= 7 V to 18 V, T_J= -40 °C to +150 °C (unless otherwise specified)

Typical values: V_DD= 5 V, V_S= 13.5 V, T_J= 25 °C

Table 13 Electrical Characteristics Serial Peripheral Interface (SPI)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Input Characteristics (CSN, SCLK, SI) - “low” level of pin

CSN

SCLK

SI

V_CSN(L)

V_SCLK(L)

V_SI(L)

0

–

0.8

V

–

P_10.4.1

P_10.4.2

P_10.4.3

–

Input Characteristics (CSN, SCLK, SI) - “high” level of pin

CSN

V_CSN(H)

V_SCLK(H)

V_SI(H)

2

–

V_DD

V

–

P_10.4.4

P_10.4.5

P_10.4.6

SCLK

SI

Input Pull-Up Current at Pin CSN

L-input pull-up current at CSN pin -I_CSN(L)

H-input pull-up current at CSN pin -I_CSN(H)

L-Input Pull-Down Current at Pin

30

20

60

40

90

65

μA

V_DD= 5 V

P_10.4.7

P_10.4.8

V

_CSN= 0.8 V

V_DD= 5 V

_CSN= 2 V

V

SCLK

I_SCLK(L)

I_SI(L)

5

12

20

μA

V_SCLK= 0.8 V

V_SI= 0.8 V

P_10.4.9

SI

P_10.4.10

H-Input Pull-Down Current at Pin

SCLK

I_SCLK(H)

I_SI(H)

14

28

45

μA

V_SCLK= 2 V

V_SI= 2 V

P_10.4.11

P_10.4.12

SI

Output Characteristics (SO)

L level output voltage

H level output voltage

V_SO(L)

V_SO(H)

0

–

0.4

V

I_SO= -1.5 mA

I_SO= 1.5 mA

P_10.4.13

P_10.4.14

V_DD- 0.4 –

V_DD

Output tristate leakage current

Timings

I_SO(OFF)

-1

–

1

μA

V_CSN=V_DD

V_SO= 0 V

P_10.4.15

P_10.4.16

V_CSN=V_DD

V_SO= V_DD

1)

Enable lead time (falling CSN to t_CSN(lead)200

rising SCLK)

–

ns

P_10.4.17

P_10.4.18

V_DD= 4.5 V or V_S

> 7 V

1)

Enable lag time (falling SCLK to

rising CSN)

t_CSN(lag)

200

V_DD= 4.5 V or V_S

> 7 V

Datasheet

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Serial Peripheral Interface (SPI)

Table 13 Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

1)

Transfer delay time (rising CSN to t_CSN(td)

250

–

ns

P_10.4.19

falling CSN)

V_DD= 4.5 V or V_S

> 7 V

1)

Output enable time (falling CSN to t_SO(en)

SO valid)

–

200

ns

P_10.4.20

P_10.4.21

V_DD= 4.5 V or V_S

> 7 V

C_L= 20 pF at SO

1)

Output disable time (rising CSN to t_SO(dis)

ns

SO tristate)

V_DD= 4.5 V or V_S

> 7 V

C_L= 20 pF at SO

1)

Serial clock frequency

Serial clock period

f_SCLK

–

5

MHz

ns

P_10.4.22

P_10.4.23

P_10.4.24

P_10.4.25

P_10.4.26

P_10.4.27

P_10.4.28

V_DD= 4.5 V or V_S

> 7 V

1)

t_SCLK(P)

t_SCLK(H)

t_SCLK(L)

200

75

20

–

V_DD= 4.5 V or V_S

> 7 V

1)

Serial clock “high” time

Serial clock “low” time

–

ns

V_DD= 4.5 V or V_S

> 7 V

1)

–

ns

V_DD= 4.5 V or V_S

> 7 V

1)

Data setup time (required time SI t_SI(su)

to falling SCLK)

–

ns

V_DD= 4.5 V or V_S

> 7 V

1)

Data hold time (falling SCLK to SI) t_SI(h)

–

ns

V_DD= 4.5 V or V_S

> 7 V

1)

Output data valid time with

capacitive load

t_SO(v)

100

ns

V_DD= 4.5 V or V_S

> 7 V

C_L= 20 pF at SO

1)

Enable lead time (falling CSN to t_CSN(lead)

rising SCLK)

1

–

μs

P_10.4.29

P_10.4.30

P_10.4.31

V_DD= V_S= 3.0 V

1)

Enable lag time (falling SCLK to

rising CSN)

t_CSN(lag)

1

V_DD= V_S= 3.0 V

1)

Transfer delay time (rising CSN to t_CSN(td)

1.25

falling CSN)

V_DD= V_S= 3.0 V

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 13 Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

1)

Output enable time (falling CSN to t_SO(en)

SO valid)

–

1

μs

P_10.4.32

V_DD= V_S= 3.0 V

C_L= 20 pF at SO

1)

Output disable time (rising CSN to t_SO(dis)

–

1

P_10.4.33

SO tristate)

V_DD= V_S= 3.0 V

C_L= 20 pF at SO

1)

Serial clock frequency

Serial clock period

f_SCLK

–

1

MHz

μs

P_10.4.34

P_10.4.35

P_10.4.36

P_10.4.37

P_10.4.38

P_10.4.39

P_10.4.40

V_DD= V_S= 3.0 V

1)

t_SCLK(P)

t_SCLK(H)

t_SCLK(L)

1

–

V_DD= V_S= 3.0 V

1)

Serial clock “high” time

Serial clock “low” time

375

100

–

ns

V_DD= V_S= 3.0 V

1)

–

ns

V_DD= V_S= 3.0 V

1)

Data setup time (required time SI t_SI(su)

to falling SCLK)

–

ns

V_DD= V_S= 3.0 V

1)

Data hold time (falling SCLK to SI) t_SI(h)

–

ns

V_DD= V_S= 3.0 V

1)

Output data valid time with

capacitive load

t_SO(v)

500

ns

V_DD= V_S= 3.0 V

C_L= 20 pF at SO

1) Not subject to production test, specified by design

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

10.5

SPI Protocol

The relationship between SI and SO content during SPI communication is shown in Figure 33. SI line

represents the frame sent from the µC and SO line is the answer provided by TLE75080-ESH.

SI

frame A

frame B

frame C

(previous

response)

response to

frame A

response to

frame B

SO

SPI_SI2SO.emf

Figure 33 Relationship between SI and SO during SPI communication

The SPI protocol provides the answer to a command frame only with the next transmission triggered by the

µC. Although the biggest majority of commands and frames implemented in TLE75080-ESH can be decoded

without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous

transmission to decode TLE75080-ESH response frame completely.

More in detail, the sequence of commands to “read” and “write” the content of a register looks as follows:

SI

write register A

read register A

(new command)

(previous

response)

Standard

diagnostic

register A

content

SO

SPI_RWseq.emf

Figure 34 Register content sent back to µC

There are 3 special situations where the frame sent back to the µC is not related directly to the previous

received frame:

•

in case an error in transmission happened during the previous frame (for instance, the clock pulses were

not multiple of 8 with a minimum of 16 bits), shown in Figure 35

when TLE75080-ESH logic supply comes out of Power-On reset condition or after a Software Reset, as

shown in Figure 36

in case of command syntax errors

–

“write” command starting with “11” instead of “10”

“read” command starting with “00” instead of “01”

“read” or “write” commands on registers which are “reserved” or “not used”

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

frame A

(error in transmission )

SI

(new command)

SO

(previous response )

Standard diagnostic + TER

SPI_SO_TER.emf

Figure 35 TLE75080-ESH response after a error in transmission

V_DD≥ V_DD(PO)

SI

frame A

frame B

frame C

INST register + TER

(8680h)

SO

(SO = „Z“)

response to frame B

SPI _SO_POR.emf

Figure 36 TLE75080-ESH response after coming out of Power-On reset at V_DD

frame A

(syntax or addressing error )

SI

(new command)

SO

(previous response )

Standard diagnostic

SPI_SO_SyntaxError.emf

Figure 37 TLE75080-ESH response after a command syntax error

A summary of all possible SPI commands is presented in Table 14, including the answer that TLE75080-ESH

sends back at the next transmission.

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 14 SPI Command summary¹⁾

Requested Operation

Read Standard Diagnosis

Write 10 bit register

Frame sent to SPIDER+ (SI pin)

Frame received from SPIDER+ (SO

pin) with the next command

0xxxxxxxxxxxxx01_B

(“xxxxxxxxxxxx_B” = don´t care)

0ddddddddddddddd_B

(Standard Diagnosis)

10aaaacccccccccc_B

where:

0ddddddddddddddd_B

(Standard Diagnosis)

“aaaa_B” = register address ADDR0

“cccccccccc_B” = new register

content

Read 10 bit registers

Write 8 bit register

01aaaaxxxxxxxx10_B

where:

“aaaa_B” = register address ADDR0

“xxxxxxxx_B” = don´t care

10aaaacccccccccc_B

where:

“aaaa_B” = register address ADDR0

“cccccccccc_B” = register content

10aaaabbcccccccc_B

0ddddddddddddddd_B

where:

(Standard Diagnosis)

“aaaa_B” = register address ADDR0

“bb_B” = register address ADDR1

“cccccccc_B” = new register content

Read 8 bit registers

01aaaabbxxxxxx10_B

where:

10aaaabbcccccccc_B

where:

“aaaa_B” = register address ADDR0

“bb_B” = register address ADDR1

“xxxxxx_B” = don´t care

“aaaa_B” = register address ADDR0

“bb_B” = register address ADDR1

“cccccccc_B” = register content

1) “a” = address bits for ADDR0 field, “b” = address bit for ADDR1 field, “c” = register content, “d” = diagnostic bit

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

10.6

SPI Registers Overview

10.6.1

Standard Diagnosis

Table 15 Standard Diagnosis

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Default

0

UVR LOP MODE

VS VDD

TER OL OL

ON OFF

ERR

7800_H

Field

Bits

Type

Description

V_SUndervoltage Monitor

UVRVS

14

r

0_BNo undervoltage condition on V_Sdetected (see Chapter 6.2.1

for more details)

1_B(default) There was at least one V_SUndervoltage condition

since last Standard Diagnosis readout

LOPVDD

MODE

13

r

V_DDLower Operating Range Monitor

0_BV_DDis above V_DD(LOP)

1_B(default) There was at least one “V_DD= V_DD(LOP)” condition since

last Standard Diagnosis readout

12:11

Operative Mode Monitor

00_B(reserved)

01_BLimp Home Mode

10_BActive Mode

11_B(default) Idle Mode

TER

10

r

Transmission Error

0_BPrevious transmission was successful

(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)

1_B(default) Previous transmission failed

The first frame after a reset is TER set to “high” and the INST

register. The second frame is the Standard Diagnosis with TER set to

“low” (if there was no fail in the previous transmission).

OLON

9

Open Load at ON state Diagnosis

0_B(default) No Open Load at ON detected

1_BOpen Load at ON detected

See Chapter 9.3.3 for a detailed explanation

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

Field

Bits

Type

Description

OLOFF

8

r

Open Load in OFF Diagnosis

0_B(default) All channels in OFF state (which have

DIAG_IOL.OUTn bit set to “1”) have V_{OUT_S}< V_{OUT_S(OL)}

1_BAt least one channel in OFF state (with DIAG_IOL.OUTn bit set

to “1”) has V_{OUT_S}> V_{OUT_S(OL)}

Channels in ON state are not considered

ERRn

n = 7 to 0

n:0

r

Over Load / Over Temperature Diagnosis of channel n

0_B(default) No failure detected

1_BOver Temperature or Over Load

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

10.6.2

Register structure

The register banks the digital part have following structure:

Table 16 Register structure - all registers (with the exclusion of PWM_CR0 and PWM_CR1)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

r = 0 r = 1 ADDR0

w = 1 w = 0

ADDR1

DATA

XXXX_H

Table 17 Register structure - PWM_CR0 and PWM_CR1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Default

r = 0 r = 1 ADDR0

w = 1 w = 0

DATA

XXXX_H

Table 18 summarizes the available registers with their addresing space and size

Table 18 Register addressing space

Register name ADDR0 ADDR1 Size Type Purpose

OUT

n = 7 to 0

0000_B

00_B

n

r/w

Power output control register

bits OUT.OUTn

0_B(default) Output is OFF

1_BOutput is ON

BIM

0000_B

0001_B

01_B

00_B

8

r/w

Bulb Inrush Mode

bits BIM.OUTn

0_B(default) Output latches OFF in case of errors

1_BOutput restarts automatically in case of errors

MAPIN0

n

Input Mapping (Input Pin 0)

n = 7 to 0

bits MAPIN0.OUTn

0_B(default) The output is not connected to the input

1_BThe output is connected to the input pin

Note: Channel 2 has the corresponding bit set to “1” by

default

Datasheet

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TLE75080-ESH

SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 18 Register addressing space (cont’d)

Register name ADDR0 ADDR1 Size Type Purpose

MAPIN1

0001_B

01_B

n

r/w

Input Mapping (Input Pin 1)

n = 7 to 0

bits MAPIN1.OUTn

0_B(default) The output is not connected to the input

1_BThe output is connected to the input pin

Note: Channel 3 has the corresponding bit set to “1” by

default

INST

0001_B

10_B

8

r

Input Status Monitor

bit TER

0_BPrevious transmission was successful

(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)

1_B(default) Previous transmission failed

bits INST.RES(6:2) - reserved

bits INST.INn(1:0)

0_B(default) The input pin is set to “low”

1_BThe input pin is set to “high”

First register transmitted after a reset of the logic

DIAG_IOL

n = 7 to 0

0010_B

00_B

01_B

10_B

n

8

r/w

Open Load diagnostic current control

bits DIAG_IOL.OUTn

0_B(default) Diagnosis current not enabled

1_BDiagnosis current enabled

DIAG_OSM

n = 7 to 0

r

Output Status Monitor

bits DIAG_OSM.OUTn

0_B(default) V_{OUT_S}< V_{OUT_S(OL)}

1_BV_{OUT_S}> V_{OUT_S(OL)}

DIAG_OLON

Open Load at ON monitor

bits DIAG_OLON.OUTn

0_B(default) normal operation or diagnosis performed

on channel OFF

1_BOpen Load at ON detected

This feature is active only on

Datasheet

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TLE75080-ESH

SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 18 Register addressing space (cont’d)

Register name ADDR0 ADDR1 Size Type Purpose

DIAG_OLONEN 0010_B

11_B

8

r/w

Open Load at ON diagnostic control

bits (7:4) - reserved

bits DIAG_OLONEN.MUX(3:0)

0000_BOpen Load at ON diagnostic active on channel 0

0001_BOpen Load at ON diagnostic active on channel 1

0010_BOpen Load at ON diagnostic active on channel 2

0011_BOpen Load at ON diagnostic active on channel 3

0100_BOpen Load at ON diagnostic active on channel 4

0101_BOpen Load at ON diagnostic active on channel 5

0110_BOpen Load at ON diagnostic active on channel 6

0111_BOpen Load at ON diagnostic active on channel 7

1000_B(reserved)

1001_B(reserved)

1010_BOpen Load at ON diagnosis loop start

1011_B(reserved)

1100_B(reserved)

1101_B(reserved)

1110_B(reserved)

1111_B(default) Open Load at ON diagnostic not active

HWCR

0011_B

00_B

8

r/w

Hardware Configuration Register

bit HWCR.ACT(7) (Active Mode)

0_B(default) Normal operation or device leaves Active

Mode

1_BDevice enters Active Mode

(see Chapter 6.1 for a description of the possible

operative mode transitions)

bit HWCR.RST(6) (Reset)

0_B(default) Normal operation

1_BExecute Reset command (self clearing)

bits HWCR.PAR(3:0) (channels operating in parallel)

0_B(default) Normal operation

1_Btwo neighbour channels have Over Load and Over

Temperature synchronized (see Chapter 7.3 for

more details)

bits 5:4 - reserved (default: 0_B)

HWCR_OCL

0011_B

01_B

n

w

Output Clear Latch

n = 7 to 0

bits HWCR_OCL.OUTn

0_B(default) Normal operation

1_BClear the error latch for the selected output

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 18 Register addressing space (cont’d)

Register name ADDR0 ADDR1 Size Type Purpose

HWCR_PWM

0011_B

10_B

8

r/w

PWM Configuration Register

bits HWCR_PWM.ADJ(7:4)

0000_B(reserved)

0001_Bbase frequency f_INT- 37.2%

0010_Bbase frequency f_INT- 31.9%

0011_Bbase frequency f_INT- 26.9%

0100_Bbase frequency f_INT- 21.0%

0101_Bbase frequency f_INT- 15.5%

0110_Bbase frequency f_INT- 10.9%

0111_Bbase frequency f_INT- 5.8%

1000_B(default) base frequency f_INT

1001_Bbase frequency f_INT+ 4.3%

1010_Bbase frequency f_INT+ 8.9%

1011_Bbase frequency f_INT+ 14.0%

1100_Bbase frequency f_INT+ 19.5%

1101_Bbase frequency f_INT+ 25.6%

1110_Bbase frequency f_INT+ 32.4%

1111_Bbase frequency f_INT+ 40.0%

bits HWCR_PWM.PWM1(1)

0_B(default) PWM Generator 1 not active

1_BPWM Generator 1 active

bits HWCR_PWM.PWM0(0)

0_B(default) PWM Generator 0 not active

1_BPWM Generator 0 active

bits HWCR_PWM.RES(3:2) - reserved

PWM_CR0

0100_B

–

10

r/w

PMW Generator Configuration 0

bits PWM_CR0.FREQ(9:8)

00_B(default) internal clock divided by 1024

01_Binternal clock divided by 512

10_Binternal clock divided by 256

11_B100% duty cycle

bits PWM_CR0.DC(7:0) (resolution: 0.39%)

00000000_B, PWM generator is OFF

11111111_B, PWM generator is ON (99.61% duty cycle)

PWM_CR1

0101_B

–

10

r/w

PMW Generator Configuration 1

bits PWM_CR1.FREQ(9:8)

00_B(default) internal clock divided by 1024

01_Binternal clock divided by 512

10_Binternal clock divided by 256

11_B100% duty cycle

bits PWM_CR1.DC(7:0) (resolution: 0.39%)

00000000_B, PWM generator is OFF

11111111_B, PWM generator is ON (99.61% duty cycle)

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 18 Register addressing space (cont’d)

Register name ADDR0 ADDR1 Size Type Purpose

PWM_OUT

1001_B

00_B

8

r/w

PWM Generator Output Control

bits PWM_OUT.OUTn

0_B(default) The selected output is not driven by one of

the two PWM Generators

1_BThe selected output is connected to a PWM

Generator

PWM_MAP

1001_B

01_B

8

r/w

PWM Generator Output Mapping

bits PWM_MAP.OUTn

0_B(default) The selected output is connected to PWM

Generator 0

1_BThe selected output is connected to PWM Generator

1

It is necessary to set the PWM_OUT register to activate the

PWM Generator control for the outputs.

10.6.3

Register summary

All registers with addresses not mentioned in Table 19 and Table 20 have to be considered as “reserved”.

“Read” operations performed on those registers return the Standard Diagnosis. The column “Default”

indicates the content of the register (8 or 10 bits) after a reset.

Table 19 Addressable registers (basic functions)

15

14 13-10

9

8

7

6

5

4

3

2

1

0

Default

r = 0 r = 1 0000

w = 1 w = 0

00

01

OUT.OUTn

00_H

04_H

08_H

r = 0 r = 1 0001

w = 1 w = 0

MAPIN0.OUTn

MAPIN1.OUTn

r = 0 r = 1 0001

w = 1 w = 0

0

1

0001

10

00

TER

(reserved)

INST.INn

00_H

r = 0 r = 1 0010

w = 1 w = 0

DIAG_IOL.OUTn

0

1

0010

01

00

DIAG_OSM.OUTn

00_H

r = 0 r = 1 0011

w = 1 w = 0

HWC HWC (reserved)

R.ACT R.RST

HWCR.PAR

r = 0 r = 1 0011

w = 1 w = 0

01

HWCR_OCL.OUTn

00_H

Table 20 Addressable registers (advanced functions)

15 14 13-10

9

8

7

6

5

4

3

2

1

0

Default

r = 0 r = 1 0000

w = 1 w = 0

01

BIM.OUTn

00_H

Datasheet

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TLE75080-ESH

SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 20 Addressable registers (advanced functions)

15

14 13-10

9

8

7

6

5

4

3

2

1

0

Default

r = 0 r = 1 0010

w = 1 w = 0

10

11

10

DIAG_OLON.OUTn

00_H

r = 0 r = 1 0010

w = 1 w = 0

(reserved)

DIAG_OLONEN.MUX

0F_H

r = 0 r = 1 0011

w = 1 w = 0

HWCR_PWM.ADJ

(reserved)

HWC HWC 80_H

R_PW R_PW

M.PW M.PW

M1

M0

r = 0 r = 1 0100

w = 1 w = 0

PWM_CR0.FR PWM_CR0.DC

EQ

000_H

00_H

r = 0 r = 1 0101

w = 1 w = 0

PWM_CR1.FR PWM_CR1.DC

EQ

r = 0 r = 1 1001

w = 1 w = 0

00

PWM_OUT.OUTn

r = 0 r = 1 1001

w = 1 w = 0

01

PWM_MAP.OUTn

00_H

10.6.4

SPI command quick list

A summary of the most used SPI commands (read and write operations on all registers) is shown in Table 21

Table 21 SPI command quick list

Register

OUT

“read” command”

4002_H

“write” command

80XX_H

content written

XX_H= xxxxxxxx_B

–

BIM

4102_H

81XX_H

MAPIN0

4402_H

84XX_H

MAPIN1

4502_H

85XX_H

INST

4602_H

n.a. (read-only)

88XX_H

DIAG_IOL

DIAG_OSM

DIAG_OLON

DIAG_OLONEN

HWCR

4802_H

XX_H= xxxxxxxx_B

–

4902_H

n.a. (read-only)

8AXX_H

4A02_H

XX_H= xxxxxxxx_B

0XX_H= 00xxxxxxxx_B

1XX_H= 01xxxxxxxx_B

2XX_H= 10xxxxxxxx_B

3XX_H= 11xxxxxxxx_B

4B02_H

8BXX_H

4C02_H

8CXX_H

HWCR_OCL

HWCR_PWM

PWM_CR0

4D02_H

8DXX_H

4E02_H

8EXX_H

5002_H

90XX_H

91XX_H

92XX_H

93XX_H

Datasheet

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SPIDER+ 12V

Serial Peripheral Interface (SPI)

Table 21 SPI command quick list (cont’d)

Register

“read” command”

“write” command

94XX_H

content written

0XX_H= 00xxxxxxxx_B

1XX_H= 01xxxxxxxx_B

2XX_H= 10xxxxxxxx_B

3XX_H= 11xxxxxxxx_B

XX_H= xxxxxxxx_B

PWM_CR1

5402_H

95XX_H

96XX_H

97XX_H

PWM_OUT

PWM_MAP

6402_H

6502_H

A4XX_H

A5XX_H

XX_H= xxxxxxxx_B

Datasheet

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SPIDER+ 12V

Application Information

11

Application Information

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

V_{BA TT}

V_DD

R_VDD

C_VDD

C_VS

V_{BA TT1}

V_{BA TT2}

IN0_LH

IN1_LH

VDD

VS

GPO

IN0

R_IN

VS1

IN1

OUT0_HS

OUT2_HS

OUT4_HS

OUT6_HS

IDLE

R_IDLE

R_LH

Z_VS

LI MP HO ME

VS2

OUT1_HS

OUT3_HS

OUT5_HS

OUT7_HS

GPO

GPI

CSN

SCLK

SI

R_CSN

R_SCLK

R_SI

SO

R_SO

GND

Application_8HS.emf

Figure 38 TLE75080-ESH Application Diagram

Note:

This is a very simplified example of an application circuit. The function must be verified in the real

application.

Table 22 Suggested Component values

Reference

Value

Purpose

R_IN

4.7 kΩ

Protection of the micro-controller during Over Voltage and Reverse Polarity

Guarantee TLE75080-ESH channels OFF during Loss of Ground

R_IDLE

4.7 kΩ

Protection of the micro-controller during Over Voltage and Reverse Polarity

Guarantee TLE75080-ESH channels OFF during Loss of Ground

R_CSN

R_SCLK

R_SI

500 Ω

100 Ω

Protection of the micro-controller during Over Voltage and Reverse Polarity

Logic supply voltage spikes filtering

R_SO

R_VDD

Datasheet

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TLE75080-ESH

SPIDER+ 12V

Application Information

Table 22 Suggested Component values (cont’d)

Reference

C_VDD

Value

100 nF

68 nF

Purpose

Logic supply voltage spikes filtering

Analog supply voltage spikes filtering

C_VS

Z_VS

P6SMB30 Protection of device during Over Voltage. Zener diode

10 nF Protection of TLE75080-ESH against ESD and BCI

C_OUT

11.1

Further Application Information

•

Please contact us for information regarding the Pin FMEA

For further information you may contact http://www.infineon.com/

Datasheet

72

Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Package Outlines

12

Package Outlines

Figure 39 PG-TSDSO-24 Package drawing

Figure 40 TLE75080-ESH Package pads and stencil

Datasheet

73

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TLE75080-ESH

SPIDER+ 12V

Package Outlines

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Datasheet

74

Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Revision History

13

Revision History

Page or Item

Changes since previous revision

Rev. 1.10, 2020-09-02

All

Package name updated

Table 2

Updated ESD susceptibility footnotes for HBM and CDM

Updated backcover

Rev.1.00, 2017-11-23

All

Datasheet released

TLE75080-ESH

LED package

Datasheet

75

Rev. 1.10

2020-09-02

TLE75080-ESH

SPIDER+ 12V

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

2.1

2.2

Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

3.1

3.2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4

4.1

4.2

4.3

4.3.1

4.3.2

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5

Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

IDLE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Electrical Characteristics Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1

5.2

5.3

6

6.1

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Definition of Power Supply modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Undervoltage on V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Low Operating Power on V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.2

6.2.1

6.2.2

6.3

7

7.1

7.1.1

7.1.2

7.1.3

7.2

7.3

7.4

7.5

7.6

Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Output ON-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Inductive Output Clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Maximum Load Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Inverse Current Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Switching Channels in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

“Bulb Inrush Mode” (BIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Automatic PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8

Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Over Temperature and Over Load Protection in Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1

8.2

8.3

8.4

8.5

8.6

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9

Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.1

9.2

9.3

9.3.1

9.3.2

9.3.3

9.4

Over Load and Over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Output Status Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Open Load at ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Open Load at ON - direct channel diagnosis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Open Load at ON - diagnosis loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

OLON bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10

10.1

10.2

10.3

10.4

10.5

10.6

10.6.1

10.6.2

10.6.3

10.6.4

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Standard Diagnosis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

SPI command quick list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

11

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.1

Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

12

13

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Datasheet

77

Rev. 1.10

2020-09-02

Please read the Important Notice and Warnings at the end of this document

Trademarks of Infineon Technologies AG

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2020-09-02

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

Except as otherwise explicitly approved by Infineon

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Technologies in

a written document signed by

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Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.


型号：	TLE75080-ESH
厂家：	Infineon
描述：	TLE75080-ESH 是采用 PG-TSDSO-24-21 封装的八通道高边电源开关，提供嵌入式保护功能。它专门用于控制汽车和工业应用中的继电器和 LED。利用串行外设接口(SPI)控制和诊断设备的负载。对于直接控制和 PWM，在默认情况下有两个输入引脚连接到两个输出。可通过相同的输入引脚(可通过 SPI 编程)控制其他或不同的输出。开关电源开关继电器
文件：	总78页 (文件大小：2363K)
中文：	中文翻译
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