TLE8203EXUMA1 [INFINEON]
Consumer Circuit, BCDMOS, PDSO36, DSO-36;
| 型号： | TLE8203EXUMA1 |
| 厂家： | 
Infineon |
| 描述： | Consumer Circuit, BCDMOS, PDSO36, DSO-36 CD 光电二极管 商用集成电路 |
| 文件： | 总33页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Data Sheet, Rev. 1.0, February 2009
TLE 8203E
Mirror Power IC
Automotive Power
TLE 8203E
Table of Contents
Table of Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
4.2
4.3
5
Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
5.2
5.3
6
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sleep-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reverse Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1
6.2
6.3
6.4
7
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status Register Address Selection and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PWM Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1
7.2
7.3
7.4
7.5
7.6
8
8.1
8.2
Power-Outputs 4-6 (Bridge Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
9.1
9.2
Power-Output 7 (Mirror Heater Driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10
10.1
10.2
Power-Outputs 8 and 10 (Lamp drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11
11.1
Logic In- and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12
12.1
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13
14
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Final Data Sheet
2
Rev. 1.0, 2009-02-04
Mirror Power IC
TLE 8203E
TLE 8203E
1
Overview
Features
•
Three half-bridges ( 1 x 0.7Ω ; 2 x 1.3Ω RDSON(MAX) @ TJ=150°C ) for
mirror position
•
•
High-side switch ( 0.17Ω RDSON(MAX) @ TJ=150°C ) for mirror defrost
Two high-side switches ( 0.8Ω RDSON(MAX) @ TJ=150°C ) for 5 W and
10 W lamps
•
•
•
•
•
•
•
•
•
•
•
•
Current sense analog output with multiplexer
All outputs with short circuit protection and diagnosis
Over-temperature protection with warning
Open load diagnosis for all outputs
Charge pump-Output for n-channel MOSFET reverse-polarity protection
Very low current consumption in sleep mode
Standard 16-bit SPI for control and diagnosis
Over- and Under-voltage Lockout
DSO package with exposed pad for low thermal resistance
Part of scalable door family products
Green Product (RoHS compliant)
AEC Qualified
PG-DSO-36-50
Functional Description
The TLE 8203E is an Application Specific Standard Product for automotive mirror control applications. It includes
the power stages necessary to drive mirror loads such as mirror position, mirror defrost and 5W or 10W lamp, i.e.
turn signal. It is a monolithic die based on Infineon’s smart mixed technology SPT which combines bipolar and
CMOS control circuitry with DMOS power devices.
The short circuit and over-temperature protection and detailed diagnosis offered meet the automotive application
safety requirements. The current sense output mprove system reliability and performance. The standard SPI
interface saves microcontroller I/O lines while still providing flexible control of the power stages and a detailed
diagnosis.
Type
Package
Marking
TLE 8203E
PG-DSO-36-50
TLE8203E
Final Data Sheet
3
Rev. 0.9, 2009-01-23
TLE 8203E
Block Diagram
2
Block Diagram
Vs
GO CP
Charge-
pump
Vcc
Biasing
SPI
RevPol
OUT4
MOS driver
INH
CSN
CLK
Fault-
Detect
OUT5
OUT6
DI
DO
PWM1
PWM2
Logicand Latch
LogicIN
current
OUT7
ISO
sense MUX
OUT8
OUT10
GND
Figure 1
Block Diagram
Final Data Sheet
4
Rev. 1.0, 2009-02-04
TLE 8203E
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
*1'
287ꢀꢆ
287ꢀꢇ
96
ꢄ
ꢉꢇ
ꢉꢆ
ꢉꢁ
ꢉꢉ
ꢉꢈ
ꢉꢄ
ꢉꢅ
ꢈꢊ
ꢈꢃ
ꢈꢂ
ꢈꢇ
ꢈꢆ
ꢈꢁ
ꢈꢉ
ꢈꢈ
ꢈꢄ
ꢈꢅ
ꢄꢊ
*1'
QF
ꢈ
ꢉ
287ꢀꢁ
96
ꢁ
,1+
ꢆ
287ꢀꢂ
287ꢀꢂ
96
3:0ꢀꢄ
3:0ꢀꢈ
,62
ꢇ
ꢂ
ꢃ
287ꢀꢃ
QF
9''
'2
ꢊ
ꢄꢅ
ꢄꢄ
ꢄꢈ
ꢄꢉ
ꢄꢁ
ꢄꢆ
ꢄꢇ
ꢄꢂ
ꢄꢃ
&3
&/.
&61
',
96
287ꢀꢄꢅ
QF
*2
QF
QF
QF
QF
QF
QF
QF
*1'
*1'
Figure 2
Pin Configuration PG-DSO-36-50
3.2
Pin Definitions and Functions
Pin
Symbol
Function
cooling GND
tab
Cooling Tab; internally connected to GND;
To reduce thermal resistance, place cooling areas and thermal vias on PCB.
1, 18,
19, 36
GND
Ground; internally connected to cooling tab (exposed pad).
2
3
OUT5
OUT6
VS
Power-Output of Half-Bridge output 5; DMOS half-bridge (mirror position).
Power-Output of Half-Bridge output 6; DMOS half-bridge (mirror position).
Power Supply; needs decoupling capacitors to GND. > 47 µF electrolytic in parallel
with 100 nF ceramic is recommended. All VS pins must be connected externally.
4, 26,
30, 33
5
6
7
INH
Inhibit; active low. Sets the device in sleep mode with low current consumption
when left open or pulled to LOW. Has an internal pull-down current source.
PWM1
PWM2
Logic Input for Direct Power Stage Control; direct input to control the high-side
switches selected by the SPI xsel1 bits in control register CtrlReg01.
Logic Input for Direct Power Stage Control; direct input to control the switches
selected by the SPI xsel2 bits in control register CtrlReg11.
Final Data Sheet
5
Rev. 1.0, 2009-02-04
TLE 8203E
Pin Configuration
Pin
Symbol
Function
8
ISO
Current Sense Output; Mirrors the current of the high-side switch selected by the
current sense multiplexer control bits ISx.
9
VDD
Logic Supply Voltage; needs decoupling capacitors to GND (pin 1). 10 µF
electrolytic in parallel with 10 nF ceramic is recommended.
10
DO
Serial Data Output; Transfers data to the master when the chip is selected by
CSN = LOW. Data transmission is synchronized by CLK, DO state is changed on
the rising edge of CLK. The most significant bit (MSB) is transferred first. The pin is
tristated as long as CSN = HIGH.
11
12
CLK
CSN
Serial Data Clock Input; Receives the clock signal from the master and clocks the
SPI shift register. Has an internal pull-down current source.
Serial Port Chip Select Not Input; SPI communication is enabled by pulling CSN
to LOW. CLK must be LOW during the transition of CSN. The CSN-pin has an
internal pull-up current source.
13
DI
Serial Data Input; Receives serial data from the master when the chip is selected
by CSN = LOW. Data transmission is synchronized by CLK. Data are accepted on
the falling edge of CLK. The LSB is transferred first. The DI-pin has an internal
pull-down current source.
14
GO
Gate Out; Charge pump output to drive the gate of external n-channel MOSFET for
reverse polarity protection.
15, 16 N.C
20, 21 N.C
Not Connected
Not Connected
Not Connected
Not Connected
22
24
25
N.C
N.C
OUT10
Power-Output of High-Side Switch output 10; DMOS high-side switch (lamp
driver
27
CP
Charge Pump; pin for optional external charge-pump reservoir capacitor. 3.3 nF to
VS is recommended.
28
29
N.C
OUT8
Not Connected
Power-Output of High-Side Switch output 8; DMOS high-side switch (lamp
driver)
31, 32 OUT7
Power Output of High-Side Switch output 7; DMOS high-side switch (mirror heat)
Power-Output of Half-Bridge output 4; DMOS half-bridge (sum of mirror position).
Not Connected
34
35
OUT4
N.C.
Final Data Sheet
6
Rev. 1.0, 2009-02-04
TLE 8203E
General Product Characteristics
4
General Product Characteristics
Absolute Maximum Ratings
4.1
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Voltages
4.1.1
4.1.2
4.1.3
4.1.4
Supply voltage
VS
VDD
-0.3
-0.3
-0.3
-16
40
5.5
5.5
VS + 5
V
V
V
V
–
–
–
–
Logic supply voltage
Logic input- and output voltages
Voltage at GO-pin
VGO
Temperatures
4.1.5
4.1.6
Junction Temperature
Storage Temperature
Tj
Tstg
-40
-50
150
150
°C
°C
–
–
ESD Susceptibility
2)
2)
4.1.7
ESD capability of power stage output
and VS pins vers. GND
VESD
–
–
4
2
kV
kV
4.1.8
ESD capability of logic pins and ISO pin VESD
vers. GND
1) Not subject to production test, specified by design.
2) Human Body Model according to JEDEC EIA/JESD22-A114-B (1.5kΩ, 100 pF)
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Final Data Sheet
7
Rev. 1.0, 2009-02-04
TLE 8203E
General Product Characteristics
4.2
Operating Range
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
4.2.1
4.2.2
4.2.3
4.2.4
Supply voltage range for
normal operation
Extended supply voltage range
for operation
Logic supply voltage range for
normal operation
Extended logic supply voltage
range for operation
VS
8
20
V
V
V
V
–
VS(ext)
VDD
5
40
(Limit Values
Deviations possible)
–
4.75
4.75
5.25
5.5
VDD(ext)
(Limit Values
Deviations possible)
4.2.5
4.2.6
SPI clock frequency
Junction temperature
fCLK
Tj
–
-40
2
150
MHz
°C
–
–
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
–
–
Typ.
5
25
Max.
–
–
1)
4.3.1
4.3.2
Junction to Case
Junction to Ambient
RthjC
RthjA
K/W
K/W
1) 2)
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer
Final Data Sheet
8
Rev. 1.0, 2009-02-04
TLE 8203E
Monitoring Functions
5
Monitoring Functions
5.1
Power Supply Monitoring
The power supply Voltage VS is monitored for over- and under-voltage.
•
Under Voltage
If the supply voltage VS drops below the switch off voltage VUV OFF, all output transistors are switched off and
the power supply fail bit PSF is set. The error is not latched, i.e. if VS rises again and reaches the switch on
voltage VUV ON, the power stages are restarted and the error bit is reset.
•
Over Voltage
If the supply voltage VS rises above the switch off voltage VOV OFF, all output transistors are switched off and
the power supply fail bit (bit 7 of the SPI diagnosis word) is set. The error is not latched, i.e. if VS falls again
and reaches the switch on voltage VOV ON, the power stages are restarted and the error is reset.
5.1.1
Characteristics Power Supply Monitoring
Electrical Characteristics: Power Supply Monitoring
Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
–
4.0
–
21
20
0.5
Typ.
–
–
0.25
–
–
1
Max.
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
UV-Switch-ON voltage
UV-Switch-OFF voltage
UV-ON/OFF-Hysteresis
OV-Switch-OFF voltage
OV-Switch-ON voltage
OV-ON/OFF-Hysteresis
VUVON
VUVOFF
VUVHY
VOVOFF
VOVON
VOVHY
5.2
5.0
–
25
24
–
V
V
V
V
V
V
VS increasing
VS decreasing
VUVON - VUVOFF
VS increasing
VS decreasing
V
OVOFF - VOVON
5.2
Temperature Monitoring
Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the
measured temperature to the warning and shutdown thresholds. If one or more temperature sensors reach the
warning temperature, the temperature warning bit TW is set to HIGH. This bit is not latched (i.e. if the temperature
falls below the warning threshold (with hysteresis), the TW bit is reset to LOW again).
If one or more temperature sensors reach the shut-down temperature, the outputs are shut down as described in
the next paragraph and the temperature shut-down bit TSD is set to HIGH. The shutdown is latched (i.e. the output
stages remain off and the TSD bit set high until a SRR command is sent or a power-on reset is performed).
If one or more temperature sensors reaches the shutdown threshold, all outputs are switched off.
Final Data Sheet
9
Rev. 1.0, 2009-02-04
TLE 8203E
Monitoring Functions
5.2.1
Characteristics Temperature Monitoring
Electrical Characteristics: Temperature Monitoring
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, INH = High; all outputs open, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
120
–
Typ.
145
30
Max.
170
–
200
5.2.1
5.2.2
5.2.3
Thermal warning junction temperature1) TjW
°C
K
°C
–
–
–
Temperature warning hysteresis1)
∆TjW
TjSD
Thermal shutdown junction
150
175
temperature1)
5.2.4
5.2.5
5.2.6
Thermal switch-on junction temperature1) TjSO
120
–
jSD/TjW 1.05
–
30
1.20
170
–
–
°C
K
–
–
–
–
Temperature shutdown hysteresis1)
Ratio of SD to W temperature1)
∆TjSD
T
1) Not subject to production test, specified by design.
5.3
Current Sense
A current proportional to the output current that flows from the selected power output to GND is provided at the
ISO (I sense out) pin. The output selection is done via the SPI. The sense current can be transformed into a voltage
by an external sense resistor and provided to an A/D converter input (see Chapter 12).
5.3.1
Characteristics Current Sense
Electrical Characteristics: Current Sense
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit Conditions
Min.
Typ.
Max.
HS4 (Register IS = 011)
5.3.1
5.3.2
5.3.3
Output voltage range
Current sense ratio
Current sense accuracy
VISO4
kILIS4
kILISacc4
0
–
–
–
3
–
10
V
–
%
V
DD = 5 V
ILIS = IOUT/IISO
OUT > 1.5 A
1000
–
k
;
;
I
HS7 (Register IS = 100)
5.3.4
5.3.5
5.3.6
Output voltage range
Current Sense Ratio for HS7
Current Sense accuracy
VISO7
kILIS7
kILISacc7
0
–
–
–
3
–
10
V
–
%
V
DD = 5 V
ILIS = IOUT/IISO
OUT > 2 A
2000
–
k
I
Final Data Sheet
10
Rev. 1.0, 2009-02-04
TLE 8203E
Power Supply
6
Power Supply
6.1
General
The TLE 8203E has two power domains: All power drivers are connected to the supply voltage VS which is
connected to the automotive 12 V board-net. The internal logic part is supplied by a separate Voltage VDD = 5 V.
The advantage of this system is that information stored in the logic remains intact in the event of short-term failures
in the supply voltage VS. The system can therefore continue to operate after VS has recovered, without having to
be reprogrammed.
A rising edge on VDD triggers an internal Power-On Reset (POR) to initialize the IC at power-on. All data stored
internally is deleted, and the outputs are switched to high-impedance status (tristate).
6.2
Sleep-Mode
The TLE 8203E can be put in a low current-consumption mode by setting the input INH to LOW. The INH pin has
an internal pull-down current source. In sleep-mode, all output transistors are turned off and the SPI is not
operating. When enabling the IC by setting INH from L to H, a Power-On Reset is performed as described above.
6.3
Reverse Polarity
The TLE 8203E requires an external reverse polarity protection. The gate-driver (charge-pump output) for an
external n-channel logic-level MOSFET is integrated. The gate voltage is provided at pin GO which should be
connected as shown in the application diagram.
6.4
Electrical Characteristics
Electrical Characteristics: Power Supply
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Current Consumption
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Supply current
IS
IDD
–
–
–
–
–
1.0
2.5
2.5
0.2
3
7.0
10
5
1
6
mA
mA
µA
µA
µA
–
Logic supply current
Supply quiescent current
Logic quiescent current
Total quiescent current
SPI not active
IS_Q
IDD_Q
S_Q + IDD_Q
INH = L;
VS = 14 V;
V
OUTX = 0 V;
I
Tj < 85 °C
Charge Pump-output for Reverse-Polarity Protection FET (GO)
6.4.6
6.4.7
6.4.8
Gate-Voltage
Setup-time
Reverse leakage current
V
tGO
IlkGO
GO - VS
5
–
–
–
–
–
8
1
5
V
ms
µA
IGO = 50 µA
–
VS = 0 V;
V
GO = -14 V
Final Data Sheet
11
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
7
SPI
7.1
General
The SPI is used for bidirectional communication with a control unit. The TLE 8203E acts as SPI-slave and the
control unit acts as SPI-master. The 16-bit control word is read via the DI serial data input. The status word
appears synchronously at the DO serial data output. The communication is synchronized by the serial clock input
CLK.
Standard data transfer timing is shown in Figure 3. The clock polarity is data valid on falling edge. CLK must be
low during CSN transition. The transfer is MSB first.
The transmission cycle begins when the chip is selected with the chip-select-not (CSN) input (H to L). Then the
data is clocked through the shift register. The transmission ends when the CSN input changes from L to H and the
word which has been read into the shift register becomes the control word. The DO output switches then to tristate
status, thereby releasing the DO bus circuit for other uses. The SPI allows to parallel multiple SPI devices by using
multiple CSN lines. The SPI can also be used with other SPI-devices in a daisy-chain configuration.
CSN High to Low & rising edge of SCLK: SDO is enabled. Status information is transfered to Output Shift Register
CSN
time
CSN Low to High: Data from Shift-Register is transfered to Output Driver Logic
CLK
DI
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14
actual Data
new Data
15 14
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SDI: Data will be accepted on the falling edge of CLK-Signal
previous Status
actual Status
15 14
DO
EF 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 0
SDO: State will change on the rising edge of CLK-Signal
Figure 3
SPI Standard Data Transfer Timing
7.2
Register Address
The 16-bit SPI frame is composed of an addressable block, an address-independent block and a 2-bit address as
shown in Figure 4.
The control word transmitted from the master to the TLE 8203E is executed at the end of the SPI transmission
(CSN L -> H) and remains valid until a different control word is transmitted or a power on reset occurs. At the
beginning of the SPI transmission (CSN H -> L), the diagnostic data currently valid are latched into the SPI and
transferred to the master. For Status Register address handling, please refer to Section 7.4.
Final Data Sheet
12
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
CSN
bit
time
15
14 13
12 11
10
9
8
7
6
5
4
3
2
1
0
Input data
Data for selected register address
Register
Address
DI
generic data
output data
Data from selected register address
DO
generic data
Figure 4
SPI Structure
7.3
SPI Bit Definitions
Control - Word
7.3.1
Table 1
Input (Control) Data Register
CtrlReg 01
Bit
CtrlReg 00
Mirror Heat Control
CtrlReg 10
CtrlReg 11
PWM1 Input Select
Mirror and Lamp-driver PWM2 Input Select
Control
15
14
13
12
11
10
9
8
7
6
x
x
x
x
x
x
HS7sel1
HS8sel1
x
HS10sel1
x
x
x
LS4ON
HS4ON
LS5ON
HS5ON
LS6ON
HS6ON
HS8ON
x
HS7sel2
HS8sel2
x
HS10sel2
x
x
x
HS7ON
Testmode = 0
Testmode = 0
Testmode = 0
x
x
OpL7ON
Testmode = 0
HS10ON
x
OpL8ON
OpL10ON
Address - Independent Data
5
4
3
2
IS_2
IS_1
IS_0
SRR
IS_2
IS_1
IS_0
SRR
IS_2
IS_1
IS_0
SRR
IS_2
IS_1
IS_0
SRR
Address - Bits
1
0
RA_1 = 0
RA_0 = 0
RA_1 = 0
RA_0 = 1
RA_1 = 1
RA_0 = 0
RA_1 = 1
RA_0 = 1
Note:Testmode is entered when the Testmode bits are set to High. Otherwise set to Low for normal operation.
Final Data Sheet
13
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
Table 2
Control Bit
LSxON
HSxON
xsel1
Control Bit Definitions
Definition
Low-side switch no. x is turned ON (OFF) if this bit is set to HIGH (LOW).
High-side switch no. x is turned ON (OFF) if this bit is set to HIGH (LOW).
Power switch x is selected to be switched by the PWM1 input.
Power switch x is selected to be switched by the PWM2 input
xsel2
OpLxON
The pull-up current for open-load detection on output 4, 5 and 6 are switched on (off) if this bit is
set to HIGH (LOW).
IS_x
The output for the current sense multiplexer is selected by these bits:
IS_2
IS_1
IS_0
Power stage selected for current sense
0
0
0
0
0
0
1
1
0
0
1
0
1
0
x
x
x
HS4
1
HS7
all others
no output selected (IISO = 0)
SRR
Status Register Reset. If set to high, the error bits of the selected status register are reset after
transmission of the data in the next SPI frame (see Chapter 7.4).
RA_x
Register Address, selects the control-register address for the current SPI transmission and the
status-register address for the next SPI transmission.
7.3.2
Diagnosis
Table 3
Output (Status) Data Register
StatReg 01
Bit
StatReg 00
Lock and Mirror Heat
StatReg 10
Mirror and Lamp-driver Mirror and Lamp-driver
Overload Open Load
StatReg 11
Lock and Mirror Heat
Overload
Open Load
valid for input data RA = valid for input data RA = valid for input data RA = valid for input data RA =
00
01
10
11
15
14
13
12
11
10
9
8
7
6
x
x
x
x
x
x
x
x
x
x
x
x
LS4OvL
HS4OvL
LS5OvL
HS5OvL
LS6OvL
HS6OvL
HS8OvL
x
LS4OpL
x
LS5OpL
x
LS6OpL
x
HS8OpL
x
HS7OvL
HS7OpL
x
x
x
x
x
x
HS10OvL
x
HS10OpL
x
Address - Independent Data
5
4
3
PSF
TSD
TW
PSF
TSD
TW
PSF
TSD
TW
PSF
TSD
TW
Error Flags
Final Data Sheet
14
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
Table 3
Output (Status) Data Register (cont’d)
Bit
StatReg 00
StatReg 01
StatReg 10
StatReg 11
Lock and Mirror Heat
Lock and Mirror Heat
Open Load
Mirror and Lamp-driver Mirror and Lamp-driver
Overload
EF_11
EF_10
Overload
EF_11
EF_01
Open Load
EF_10
EF_01
2
1
0
EF_11
EF_10
EF_00
EF_01
EF_00
EF_00
Note:x-bits are set to low
Table 4
Status Bit
LSxOvL
Status Bit Definitions
Definition
Low-Side switch Over Load. Set to HIGH if low-side switch no. x is shut down due to overcurrent
or overtemperature or crosscurrent.
HSxOvL
LSxOpL
High-Side switch Over Load. Set to HIGH if high-side switch no. x is shut down due to
overcurrent or overtemperature or crosscurrent.
Low-Side switch open load. Set to HIGH if open load (undercurrent) is detected in low-side
switch x.
HSxOpL
PSF
High-Side switch Open Load. Set to HIGH if open load is detected in high-side switch x.
Power Supply Fail. Set to HIGH if the Voltage at the VS pin is below the VS undervoltage
threshold or above the VS overvoltage threshold.
TSD
TW
EF_xy
N.C.
All powerstages are shut down due to overtemperature.
One or more powerstages have reached the warning temperature.
Error Flag for StatReg xy. Set to HIGH if any bit is set to HIGH StatReg xy.
Not connected. These bits may be used for test-mode purposes. They are set to fixed LOW in
normal operation.
7.4
Status Register Address Selection and Reset
The SPI is using a standard shift-register concept with daisy-chain capability. Any data transmitted to the SPI will
be available to the internal logic part at the end of the SPI transmission (CSN L -> H). To read a specific register,
the address of the register is sent by the master to the SPI in a first SPI frame. The data that corresponds to this
address is transmitted by the SPI DO during the following (second) SPI frame to the master. The default address
for Status Register transmission after Power-ON Reset is 00.
The Status-Register-Reset command-bit is executed after the next SPI transmission. The three bits RA_0, RA_1
and SRR act as command to read and reset (or not reset) the addressed Status-Register. This is also explained
in Figure 5.
The TSD status bit is not part of the addressable data but of the address independent data. When any of the status
registers is reset, the TSD bit is reset, too.
Final Data Sheet
15
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
CSN
SI
x x x x x
x x x x x
0
x
0
x
1
x
x x x x x
x x x x x
1
x
1
x
0
x
x x x x x
x x x x x
0
x
1
x
1
x
StatReg10 is reset
SO
after CSN
L->H
Status Register 01 is transferred to
SPI master, but not reset after
transmission
Status Register 10 is transferred to
SPI master, and reset after
transmission
Com-
ment
After Power-ON Reset, Status
Register 00 is sent by default
t
Figure 5
Status Register Addressing and Reset
7.4.1
Error-Flag
In addition to the 16 bits transferred from the TLE 8203E to the SPI master, an additional Error Flag (EF) is
transmitted at the DO pin. The EF status is shown on the DO pin after CSN H -> L, before the first rising edge at
CLK, as shown in Figure 6.
The Error flag is set to H if any of the Status Registers contains an error message (i.e. EF = EF_00 or EF_01 or
EF_10 or EF_11).
CSN
CLK
DO
Z
EF
bit15
bit14
bit13
bit12
CSN
CLK
DO
Z
EF
Z
Figure 6
Error Flag Transmission on DO during Standard SPI Transmission (top), or without Additional
SPI Transmission, CLK Low (bottom)
Final Data Sheet
16
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
7.5
Electrical Characteristics
Electrical Characteristics: SPI-Timing
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
100
100
–
Typ.
–
–
–
–
–
–
–
–
Max.
–
–
25
25
–
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
CSN lead time
CSN lag time
Fall time for CSN, CLK, DI, DO
Rise time for CSN, CLK, DI, DO
DI data setup time
DI data hold time
DI data valid time
DO data setup time
DO data hold time
tlead
tlag
tf
tr
tSU
th
tv
tDOsetup
tDOhold
tnodata
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
–
40
40
–
0
50
5
–
50
60
–
–
–
7.5.10 No-data-time between SPI
commands
7.5.11 Clock frequency
–
1)
1)
fCL
–
40
–
–
2
60
MHz
%
7.5.12 Duty cycle of incoming clock at CLK –
1) SPI Timing is not subject to production test - specified by design. SPI functional test is performed at 5 MHz CLK frequency.
Timing specified with an external load of 30 pF at pin [DO].
WQRGDWD
&61
WOHDG
WU
WI
WODJ
WOHDG
WODJ
&/.
',
W68
WK
QRWꢀGHILQHG
06%
/6%
/6%
W'2VHWXS
W'2VHWXS
W'2KROG
'2
)ODJ
06%
Figure 7
Timing Diagram
7.6
PWM Inputs
The PWM inputs PWM1 and PWM2 are direct power stage control inputs that can be used to switch on and off
one or more of the power transistors with a PWM signal supplied to this pin. The setting of the SPI Registers
CtrlReg_01 and CtrlReg_11 defines which of the power stages will be controlled by the PWM inputs. If the
selection-bits of power Stage x, xsel1 and xsel2 are LOW, the power stage x is controlled only via the SPI control
bit xON. If the selection bit xsel1 is HIGH and the control bit xON is also high, the power stage x is controlled by
the PWM1 pin (xsel2 and PWM2, respectively). The behavior is shown in the principal schematic and in Table 5
below. In terms of power dissipation due to switching loss, a PWM frequency below 200 Hz is recommended.
Final Data Sheet
17
Rev. 1.0, 2009-02-04
TLE 8203E
SPI
CSN
DI
S
P
I
xON
CLK
DO
xsel1
xsel2
x
{HS7, HS8, HS10}
&
&
&
1
1
PWM1
Gate
driver
&
OUT x
PWM2
power
control logic of power transistor x
transistor x
Figure 8
PWM Input and SPI Control Registers
Table 5
Truth Table for PWM Inputs
xON
0
1
1
1
1
1
1
1
xsel1
xsel2
PWM1
PWM2
Power Stage x
OFF
ON
OFF
ON
OFF
ON
ON
ON
OFF
x
0
1
1
0
0
1
1
1
x
0
0
0
1
1
1
1
1
x
x
0
1
x
x
1
x
0
x
x
x
x
0
1
x
1
0
1
Final Data Sheet
18
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs)
8
Power-Outputs 4-6 (Bridge Outputs)
Protection and Diagnosis
8.1
8.1.1
Short Circuit of Output to Ground or Vs
The low-side switches are protected against short circuit to supply and the high-side switches against short to
GND.
If a switch is turned on and the current rises above the shutdown threshold ISD for longer than the shutdown delay
time tdSD, the output transistor is turned off and the corresponding diagnosis bit is set. During the delay time, the
current is limited to ISC as shown in Figure 9.
ISC
short to Vs
OUTx
ISD
IOUT
tdSD
short to GND
t
Figure 9
Short Circuit Protection
The delay time is relatively short (typ. 25 µs) to limit the energy that is dissipated in the device during a short circuit.
This scheme allows high peak-currents as required in motor-applications.
The output stage stays off and the error bit set until a status register reset is sent to the SPI or a power-on reset
is performed.
8.1.2
Cross-Current
If for instance HS4 is ON and LS4 is OFF, you can turn OFF HS4 and turn ON LS4 with the same SPI command.
To ensure that there is no overlap of the switching slopes that would lead to a cross current, the dead-time H to L
and L to H is specified.
In the control registers, it is also possible to turn ON high- and low-side switches of the same half-bridge (e.g.
LS4ON = H and HS4ON = H). To prevent a cross-current through the bridge, such a command is not executed.
Instead, both switches are turned OFF and the Over-Load bit is set High for both switches (e.g. LS4OvL = H and
HS4OvL = H).
8.1.3
Open Load
Open-load detection in ON-state is implemented in the low-side switches of the bridge outputs: When the current
through the low side transistor is lower than the reference current IOCD in ON-state for longer than the open-load
detection delay time tdOC, the according open-load diagnosis bit is set. The output transistor, however, remains
ON. The open load error bit is latched and can be reset by the SPI status register reset or by a power-on reset.
As an example, if a motor is connected between outputs OUT 4 and OUT 5 with a broken wire as shown in
Figure 10, the resulting diagnostic information is shown in Table 6.
Final Data Sheet
19
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs)
HS1
LS1
OUT 4
OUT 5
Open Load
Motor
HS2
LS2
Figure 10 Open Load Example
Table 6
Open Load Diagnosis Example
Control
Diagnostic Information
Motor
Connected
Motor
Remark on Open Load
Disconnected Detection
LS4
ON
HS4
ON
LS5
ON
HS5
ON
Motor Rotation LS4
LS5
OpL
LS4
OpL
LS5
OpL
OpL
0
1
0
0
0
1
0
0
1
0
1
0
motor off
clock-wise
counter clock-
wise
0
0
0
0
0
0
0
1
0
0
0
1
not detectable
detected
detected
0
1
1
0
0
1
1
0
brake high
brake low
0
1
0
1
0
1
0
1
not detectable
not detectable
8.2
Electrical Characteristics
Electrical Characteristics: OUT4 (Driver for mirror xy and halfbridge for fold)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Static Drain-Source ON-Resistance
8.2.1 High- and low-side switch
RDSON4
–
–
0.3
0.4
–
Ω
Ω
I
OUT = ±1 A;
Tj = 25 °C
0.7
IOUT = ±1 A
Tj = 150 °C
Switching Times
8.2.2
8.2.3
8.2.4
8.2.5
High-side ON delay-time
tdONH4
tdOFFH4
tdONL4
tdOFFL4
–
–
–
–
50
25
50
25
100
50
100
50
µs
µs
µs
µs
VS = 14 V;
resistive load of
14 Ω, see
High-side OFF delay time
Low-side ON delay-time
Low-side OFF delay time
Figure 11 and
Figure 12
8.2.6
Dead-time H to L
tDHL4
3
–
–
µs
t
dONL4 - tdOFFH4
Final Data Sheet
20
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs)
Electrical Characteristics: OUT4 (Driver for mirror xy and halfbridge for fold) (cont’d)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
tdONH4 - tdOFFL4
Min.
3
Typ.
Max.
8.2.7
Dead-time L to H
tDLH4
–
–
µs
Short Circuit Protection
8.2.8
8.2.9
Over-current shutdown threshold ISD4
3
10
–
4
25
6
8
50
–
A
µs
A
high- and low-
side
Shutdown delay time
tdSD4
ISC4
8.2.10 Short Circuit current1)
Open Load Detection
8.2.11 Detection current
8.2.12 Delay time
IOCD4
tdOC4
12
200
25
350
45
600
mA
µs
low-side
Leakage Current
8.2.13 OFF-state output current
1) Not subject to production test - specified by design.
IOUT4_leakage
–
–
10
µA
VOUT = 0.2 V
Electrical Characteristics: OUT 5, 6 (driver for mirror x-y position)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Un Conditions
it
Min.
Typ.
Max.
Static Drain-Source ON-Resistance
8.2.14 High- and low-side switch
RDSON56
–
–
0.5
0.8
–
Ω
Ω
I
OUT = ±0.5 A;
Tj = 25 °C
OUT = ±0.5 A
Tj = 150 °C
1.3
I
Switching Times
8.2.15 High-side ON delay time
8.2.16 High-side OFF delay time
8.2.17 Low-side ON delay time
8.2.18 Low-side OFF delay time
8.2.19 Dead-time H to L
8.2.20 Dead-time L to H
Short Circuit Protection
tdONH56
tdOFFH56
tdONL56
tdOFFL56
tDHL56
–
–
–
–
3
3
50
25
50
25
–
100
50
100
50
–
µs VS = 14 V;
resistive load of
µs
µs
µs
µs
µs
25 Ω, see Figure 11
and Figure 12
t
t
dONL56 - tdOFFH56
dONH56 - tdOFFL56
tDLH56
–
–
8.2.21 Over-current shutdown threshold
8.2.22 Shutdown delay time
8.2.23 Short Circuit current1)
Open Load Detection
ISD56
tdSD56
ISC56
1.25
10
–
1.5
25
3.0
3.0
50
–
A
µs
A
high- and low-side
8.2.24 Detection current
8.2.25 Delay time
IOCD56
tdOC56
12
200
25
350
40
600
mA low-side
µs
Final Data Sheet
21
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 4-6 (Bridge Outputs)
Electrical Characteristics: OUT 5, 6 (driver for mirror x-y position) (cont’d)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Un Conditions
it
Min.
Typ.
Max.
Leakage Current
8.2.26 OFF-state output current
1) Not subject to production test - specified by design.
IOUT56_leakage
–
–
10
µA VOUT = 0.2 V
CSN
ON -> OFF
high-side OFF
delay time
OUTx
OFF
tdOFFH
10%
tDHL
90%
OFF
low-side ON
OUTx
tdONL
delay time
OFF -> ON
Figure 11 Timing Bridge Outputs High to Low
CSN
OFF
low-side OFF
delay time
90%
OUTx
tdOFFL
ON -> OFF
tDLH
OFF -> ON
high-side ON
delay time
OUTx
OFF
tdONH
10%
Figure 12 Timing Bridge Outputs Low to High
Final Data Sheet
22
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Output 7 (Mirror Heater Driver)
9
Power-Output 7 (Mirror Heater Driver)
Output 7 is a high-side switch intended to drive ohmic loads like the heater of an exterior mirror.
9.1
Protection and Diagnosis
9.1.1
Short Circuit of Output to Ground
If the high-side switch is turned on and the current rises above the shutdown threshold ISD for longer than the
shutdown delay time tdSD, the output transistor is turned off and the corresponding diagnosis bit is set. During the
delay time, the current is limited to ISC as shown in Figure 13.
ISC
OUT 7
ISD
IOUT
tdSD
short to GND
t
Figure 13 Short Circuit Protection
The output stage stays off and the error bit set until a status register reset is sent to the SPI or a power-on reset
is performed.
9.1.2
Open Load
For the high-side switches, an open-load in OFF-state scheme is used as shown in Figure 10. The output is pulled
up by a current source IOpL. In OFF-state, the output voltage is monitored and compared to the threshold VOpL. If
the voltage rises above this threshold, the open-load signal is set to high. This is equivalent to comparing the load
resistance to the value VOpL / IOpL. The open load error bit is latched and can be reset by the SPI status register
reset or by a power-on reset.
The pull-up current can be switched on and off by the OpLxON bits. This bit should be set to LOW (i.e. pull-up
current switched off) if an output is used to drive LEDs because they may emit light if biased with the pull-up
current.
Final Data Sheet
23
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Output 7 (Mirror Heater Driver)
OpL7ON
IOpL
Gate
driver
OUT 7
switch ON HS7
HS7OpL
high-side
switch 7
1
&
+
-
Filter
RLoad
+
VOpL
-
Figure 14 Open Load in OFF-state Scheme
9.2
Electrical Characteristics
Electrical Characteristics: OUT 7(mirror heater driver)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Static Drain-source ON-Resistance
9.2.1 High-side switch
RDSON7
–
–
0.07
0.1
–
Ω
Ω
I
OUT = 2.5 A;
Tj = 25 °C
0.17
IOUT = 2.5 A
Tj = 150 °C
Switching Times
9.2.2
9.2.3
9.2.4
9.2.5
Turn-ON delay time
tdONH7
trise7
tdOFFH7
tfall7
–
–
–
–
5
15
40
40
10
µs
µs
µs
µs
VS = 14 V;
resistive load of
10 Ω, see
Output rise-time
Turn-OFF delay time
Output fall-time
15
20
5
Figure 15
Short Circuit Protection
9.2.6
9.2.7
9.2.8
Over-current shutdown threshold ISD7
6.25
10
–
8
25
12
11
50
–
A
µs
A
–
–
–
Shutdown delay time
tdSD7
ISC7
Short Circuit current1)
Open Load Detection
9.2.9 Pull-up current
IOpL7
100
–
300
µA
VOUT = 4 V
Final Data Sheet
24
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Output 7 (Mirror Heater Driver)
Electrical Characteristics: OUT 7(mirror heater driver) (cont’d)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
9.2.10 Detection Threshold
9.2.11 Delay time
VOpL7
tdOC7
2
–
–
–
4
200
V
µs
–
–
Leakage Current
9.2.12 OFF-state output current
1) Not subject to production test - specified by design.
IOUT7_leakage
–
–
5
µA
VOUT = GND
PWM
tFALL
tRISE
PWM
90%
90%
OUT7
tdON
tdOFF
10%
10%
Figure 15 Timing OUT 7
Final Data Sheet
25
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 8 and 10 (Lamp drivers)
10
Power-Outputs 8 and 10 (Lamp drivers)
Outputs 8 and 10 are a high-side switches intended to drive ohmic loads 5 W or 10 W lamp (bulb) loads.
10.1
Protection and Diagnosis
10.1.1
Short Circuit of Output to Ground
The high-side switches Out 8 and 10 are protected against short to GND.
Short Circuit during Switch-on
During switch-on of an output a current and voltage level is used to check for a short circuit. If a switch is turned
on and the short circuit condition is valid after tdSDon8 the output transistor is turned off and the corresponding
diagnosis bit is set. A short circuit condition is valid if the current rises above the shutdown threshold ISD8 and the
voltage at the output stays below VSD8. During the delay time, the current is limited to ISC8 as shown in Figure 16
ISC8
OUT 8, 10
IOUT
ISD8
IOUT
tdSDon8
short to GND
VOUT
t
VSD8
VOUT
Figure 16 Short Circuit Protection during Switch-on
Final Data Sheet
26
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 8 and 10 (Lamp drivers)
Short Circuit in On-state
If a switch is already on and the current rises above the shutdown threshold ISD for longer than the shutdown delay
time tdSD the output transistor is turned off and the corresponding diagnosis bit is set. This is independent of the
voltage Vout. See Figure 17.
ISC8
OUT 8, 10
IOUT
ISD8
IOUT
tdSD8
short to GND
t
Figure 17 Short Circuit Protection in On-state
10.1.2
Open Load
For the high-side switches, an open-load in OFF-state scheme is used as shown in Figure 18. The output is pulled
up by a current source IOpL. In OFF-state, the output voltage is monitored and compared to the threshold VOpL. If
the voltage rises above this threshold, the open-load signal is set to high. This is equivalent to comparing the load
resistance to the value VOpL / IOpL. The open load error bit is latched and can be reset by the SPI status register
reset or by a power-on reset.
The pull-up current can be switched on and off by the OpLxON bits. This bit should be set to LOW (i.e. pull-up
current switched off) if an output is used to drive LEDs because they may emit light if biased with the pull-up
current.
OpLxON
IOpL
Gate
driver
OUT x
switch ON HSx
HSxOpL
high-side
switch
1
&
+
-
Filter
RLoad
+
-
VOpL
Figure 18 Open Load in OFF-state Scheme
Final Data Sheet
27
Rev. 1.0, 2009-02-04
TLE 8203E
Power-Outputs 8 and 10 (Lamp drivers)
10.2
Electrical Characteristics
Electrical Characteristics: OUT 8, 10 (Lamp drivers)
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Static Drain-Source ON-Resistance
10.2.1 High-side switch
RDSON8,10
–
–
0.4
0.5
–
Ω
Ω
I
OUT = +0.5 A;
Tj = 25 °C
0.8
IOUT = +0.5 A
Tj = 150 °C
Switching Times
10.2.2 Turn-ON delay time
10.2.3 Output rise-time
10.2.4 Turn-OFF delay time
10.2.5 Output fall-time
tdONH8,10
trise8,10
tdOFFH8,10
tfall8,10
–
5
–
7
5
15
30
50
30
µs
µs
µs
µs
VS = 14 V;
resistive load of
25 Ω, see
10
25
15
Figure 15
Short Circuit Protection
10.2.6 Over-current shutdown threshold
10.2.7 Over-current shutdown threshold
voltage
ISD8,10
VSD8,10
1.8
1.5
2.9
2.5
3.5
3.3
A
V
–
–
10.2.8 Short circuit current1)
10.2.9 Shutdown delay time
10.2.10 Shutdown delay time
Open Load Detection
ISC8,10
tdSDon8,10
tdSD8,10
–
125
10
4.2
200
25
–
350
60
A
µs
µs
–
at switching-on
in on-state
10.2.11 Pull-up current
10.2.12 Detection Threshold
10.2.13 Delay time
IOpL8,10
VOpL8,10
tdOC8,10
100
2
–
–
–
–
250
4
200
µA
V
µs
V
–
–
OUT = 4 V
Leakage Current
10.2.14 OFF-state output current
1) Not subject to production test - specified by design.
IOUT810_leakage
–
–
5
µA
V
OUT = GND
PWM
tFALL
tRISE
PWM
90%
90%
OUT 8, 10
tdON
tdOFF
10%
10%
Figure 19 Timing OUT 8, 10
Final Data Sheet
28
Rev. 1.0, 2009-02-04
TLE 8203E
Logic In- and Outputs
11
Logic In- and Outputs
The threshold specifications of the logic inputs are compatible to both 5 V and 3.3 V standard CMOS micro
controller outputs. The logic output DO is a 5 V CMOS output.
11.1
Electrical Characteristics
Electrical Characteristics: Diagnostics
VS = 8 V to 20 V; VDD = 4.75 V to 5.25 V, Tj = -40 °C to +150 °C; INH = High; all outputs open, all voltages with
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Inhibit Input
11.1.1 H-input voltage threshold
11.1.2 L-input voltage threshold
11.1.3 Hysteresis of input voltage
11.1.4 Pull-down current
VIH
VIL
VIHY
IIINH
–
1
100
–
–
–
–
–
2
–
600
50
V
V
mV
µA
VIN rising
VIN falling
–
V
IINH = 2 V
Logic Inputs DI, CLK, CSN, PWM1 and PWM2
11.1.5 H-input voltage threshold
11.1.6 L-input voltage threshold
11.1.7 Hysteresis of input voltage
11.1.8 Pull-up current at pin CSN
11.1.9 Pull-down current at pins PWM1,
PWM2, DI, CLK
VIH
VIL
VIHY
IICSN
IInput
–
1
100
-50
10
–
–
–
-25
25
2
–
600
-10
50
V
V
mV
µA
µA
VIN rising
VIN falling
–
V
V
CSN = 1 V
Input = 2 V
11.1.10 Input capacitance at pin CSN, DI, CI
–
10
15
pF
0 V < VDD < 5.25 V
CLK, PWM1, PWM21)
Logic Output DO
11.1.11 H-output voltage level
VDOH
VDD
-
VDD
-
–
V
I
I
SDOH = 1 mA
1.0
0.7
11.1.12 L-output voltage level
11.1.13 Tri-state leakage current
VDOL
IDOLK
–
-10
0.2
–
0.4
10
V
µA
SDOL = -1.6 mA
CSN = VDD;
V
0 V < VSDO < VDD
11.1.14 Tri-state input capacitance1)
CDO
–
10
15
pF
VCSN = VDD;
0 V < VDD < 5.25 V
1) Not subject to production test, specified by design.
Final Data Sheet
29
Rev. 1.0, 2009-02-04
TLE 8203E
Application Information
12
Application Information
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
12.1
Application Diagram
VBATT_1
VBATT_2
TLE8458
IPD 30N03S2L-07
VCC
VS
22
µF
100
nF
10
100
nF
µF
< 40V
100kΩ
47uF //
LIN
2 x 100 nF
3.3nF
LIN
EN
TxD
RxD
220
pF
WK
GND
GO
Vs
CP
RxD
TxD GPIO 3
VDD
VDD
INH
XC866
TLE 8203E
OUT 4
GPIO 1
GPIO 2
SCLK
SDI
mirror-x
OUT 5
M
CSN
CLK
DI
mirror-y
OUT 6
M
DO
SDO
PWM1
PWM2
ISO
TIMER 1
TIMER 2
A/D
OUT 7
mirror-heat
Rsense
700
Ω
OUT 8
OUT 10
DIG_GND
POWER_GND
Figure 20 Application Example for Mirror Control
Final Data Sheet
30
Rev. 1.0, 2009-02-04
TLE 8203E
Package Outlines
13
Package Outlines
0.35 x 45˚
1)
7.6-0.2
+0.09
0.23
0.65
C
0.2
0.3
0.7
10.3
0.1 36x
SEATING PLANE
C
D
17 x 0.65 = 11.05
2)
0.08
0.33
M
0.17 A-B C
36x
D
Bottom View
A
36
19
19
36
Ejector Mark
Exposed Diepad
Index Marking
1
18
18
1
X
B
1)
12.8-0.2
Index Marking
Exposed Diepad Dimensions
Package Leadframe
PG-DSO-36-24, -41, -42 A6901-C001
X
7
7
Y
5.1
5.1
PG-DSO-36-38
PG-DSO-36-38
PG-DSO-36-50
A6901-C003
A6901-C007 5.2 4.6
A6901-C008 6.0 5.4
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
3) Distance from leads bottom (= seating plane) to exposed diepad
PG-DSO-36-24, -38, -41, -42, -50-PO V09
Figure 21 PG-DSO-36-50 (Plastic Dual Small Outline Package)
Green Product ( RoHS compliant )
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
Final Data Sheet
31
Rev. 1.0, 2009-02-04
TLE 8203E
Revision History
14
Revision History
0.9
Version
1.0
Date
03.02.09
Changes
Final Data Sheet Release
Final Data Sheet
32
Rev. 1.0, 2009-02-04
Edition 2009-02-04
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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