TLE8261-2E [INFINEON]
Universal System Basis Chip; 通用系统基础芯片
| 型号： | TLE8261-2E |
| 厂家： | 
Infineon |
| 描述： | Universal System Basis Chip |
| 文件： | 总83页 (文件大小：1450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.0, May 2009
TLE8261-2E
Universal System Basis Chip
HERMES
Rev. 1.0
Automotive Power
TLE8261-2E
Table of Contents
Table of Contents
1
2
HERMES Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
4.1
4.2
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
State Machine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
5.2
5.3
5.4
6
Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal Voltage Regulator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal Voltage Regulator Modes with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
6.2
6.3
6.4
6.5
7
External Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External Voltage Regulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External Voltage Regulator State by SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
7.2
7.3
7.4
7.5
8
High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
High-speed CAN Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CAN Cell Mode with SBC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPLIT Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1
8.2
8.3
8.4
8.5
8.6
9
WK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Wake-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1
9.2
9.3
10
Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.1
10.2
10.3
11
Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Modes with SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1
11.2
11.3
11.4
Data Sheet
2
Rev. 1.0, 2009-05-26
TLE8261-2E
Table of Contents
11.5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12
Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Limp Home output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Activation of the Limp Home Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Release of the Limp Home Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.1
12.2
12.3
12.4
12.5
12.6
V
cc1µC undervoltage time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13
13.1
13.2
Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Configuration select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Config Hardware Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
14
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Corrupted data in the SPI data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI Input Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SPI Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SPI Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.1
14.2
14.3
14.4
14.5
14.6
14.7
15
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ZthJA Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Hints for SBC Factory Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
15.1
15.2
15.3
16
17
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Data Sheet
3
Rev. 1.0, 2009-05-26
Universal System Basis Chip
HERMES
TLE8261-2E
Rev. 1.0
1
HERMES Overview
Scalable System Basis Chip Family
•
•
•
•
•
•
Eight products for complete scalable application coverage
Complete compatibility (hardware and software) across the family
TLE8264-2E (3LIN), TLE8263-2E (2LIN) - 3 Limp Home outputs
TLE8264E (3LIN), TLE8263E (2LIN) - 1 Limp Home output
TLE8262-2E (1LIN), TLE8261-2E (no LIN) - 3 Limp Home outputs
TLE8262E (1LIN), TLE8261E (no LIN) - 1 Limp Home output
Basic Features
•
•
•
•
•
•
•
•
•
•
•
Very low quiescent current in Stop and Sleep Modes
Reset input, output
PG-DSO-36-38
Power on and scalable undervoltage reset generator
Standard 16-bit SPI interface
Overtemperature and short circuit protection
Short circuit proof to GND and battery
One universal wake-up input
Wide input voltage and temperature range
Cyclic wake in Stop Mode
Green Product (RoHS compliant)
AEC Qualified
Description
The devices of the SBC family are monolithic integrated circuits in an enhanced power package with identical
software functionality and hardware features except for the number of LIN cells. The devices are designed for
CAN-LIN automotive applications e.g. body controller, gateway applications.
To support these applications, the System Basis Chip (SBC) provides the main functions, such as HS-CAN
transceiver for data transmission, low dropout voltage regulators (LDO) for an external 5 V supply, and a 16-bit
Serial Peripheral Interface (SPI) to control and monitor the device. Also implemented are a Time-out or a Window
Watchdog circuit with a reset feature, Limp Home circuitry output, and an undervoltage reset feature.
The devices offer low power modes in order to support application that are connected permanent to the battery.
A wake-up from the low power mode is possible via a message on the buses or via the bi-level sensitive
monitoring/wake-up input as well as from the SPI command. Each wake-up source can be inhibited.
The device is designed to withstand the severe conditions of automotive applications.
Type
Package
Marking
TLE8261-2E
PG-DSO-36-38
TLE8261-2E
Data Sheet
4
Rev. 1.0, 2009-05-26
TLE8261-2E
HERMES Overview
HS CAN Transceiver
•
•
•
•
•
•
•
•
•
Compliant to ISO 11898-2 and 11898-5 as well as SAE J2284
CAN data transmission rate up to 1 MBaud
Supplied by dedicated input VccHSCAN
Low power mode management
Bus wake-up capability via CAN message
Excellent EMC performance (very high immunity and very low emission)
Bus pins are short circuit proof to ground and battery voltage
8 kV ESD gun test on CANH / CANL / SPLIT
Bus failure detection
Voltage Regulators
•
•
•
•
Low-dropout voltage regulator
V
V
V
cc1µC, 200 mA, 5 V 2% for external devices, such as microcontroller and RF receiver
cc2, 200 mA, 5 V 2% for external devices or the internal HS CAN cell
cc3, current limitation by shunt resistor (up to 400 mA with 220 mΩ shunt resistor), 5 V 4% with external PNP
transistor; for example: to supply additional external CAN transceivers
•
Vcc1µC, undervoltage Time-out
Supervision
•
•
•
•
•
Reset output with integrated pull-up resistor
Time-out or Window Watchdog, SPI configured
Watchdog Timer from 16 ms to 1024 ms
Check sum bit for Watchdog configuration
Reset due to Watchdog failure can be inhibited with Test pin (SBC SW Development Mode)
Interrupt Management
•
•
Complete enabling / disabling of interrupt sources
Timing filter mechanism to avoid multiple / infinite Interrupt signals
Limp Home
•
•
•
•
•
•
Open drain Limp Home outputs
Dedicated internal logic supply
Maximum safety architecture for Safety Operation Mode
Configurable Fail-Safe behavior
Dedicated side indicators signal 1.25Hz 50% duty cycle
Dedicated PWM signal 100Hz 20% duty cycle
Data Sheet
5
Rev. 1.0, 2009-05-26
TLE8261-2E
Block Diagram
2
Block Diagram
The simplified block diagram illustrates only the basic elements of the SBC devices. Please refer to the information
for each device in the product family for more specific hardware configurations.
VS
VS
VS
VS
Vcc1µC
Vcc2
GND
Vcc3
Vint.
Vint.
SDI
SDO
CLK
CSN
SBC
SPI
LH_PL/test
STATE
Limp
MACHINE
Limp home
LHO_SI
Home
INT
Interrupt
Control
RO
RESET
GENERATOR
VCCHSCAN
Vs
WK
WK
WAKE
TxD CAN
RxD CAN
REGISTER
CAN cell
CAN_H
SPLIT
CAN_L
Block diagram_TLE8261-2E.vsd
GND
Figure 1
Simplified Block Diagram
Data Sheet
6
Rev. 1.0, 2009-05-26
TLE8261-2E
Pin Configuration
3
Pin Configuration
3.1
Pin Assignments
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RO
CSN
CLK
SDI
SDO
GND
n.c.
Vs
Vs
n.c.
LH_PL/Test
Limp home
WK
LH_SI
n.c.
GND
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
RxDCAN
TxDCAN
GND
CANL
SPLIT
CANH
2
3
TLE8261-2E
DSO 36 - Exposed Pad
4
5
6
7
8
9
Exposed
Die
10
11
12
13
14
Pad
Vcc3shunt
Vcc3
base
GND
Vcc3REF
INT 15
Vcc1
16
µC
Vcc2 17
18
VccHSCAN
Pinout_8261_2E.vsd
Figure 2
Pin Configuration
Data Sheet
7
Rev. 1.0, 2009-05-26
TLE8261-2E
Pin Configuration
3.2
Pin Definitions and Functions
Pin
1
Symbol
RO
Function
Reset Input/Output; open drain output, integrated pull-up resistor; active low.
2
CSN
SPI Chip Select Not Input; CSN is an active low input; serial communication is
enabled by pulling the CSN terminal low; CSN input should be set to low only when
CLK is low; CSN has an internal pull-up resistor and requires CMOS logic level
inputs.
3
4
CLK
SDI
SPI Clock Input; clock input for shift register; CLK has an internal pull-down resistor
and requires CMOS logic level inputs.
SPI Data Input; receives serial data from the control device; serial data transmitted
to SDI is a 16-bit control word with the Least Significant Bit (LSB) transferred first:
the input has a pull-down resistor and requires CMOS logic level inputs; SDI will
accept data on the falling edge of the CLK signal.
5
SDO
SPI Data Output; this tri-state output transfers diagnostic data to the control device;
the output will remain tri-stated unless the device is selected by a low on Chip Select
Not (CSN).
6
7
8
GND
n.c.
Vs
Ground
Not connected
Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure
to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected.
9
Vs
Power Supply Input; block to GND directly at the IC with ceramic capacitor. Ensure
to have no current flow from PIN8 to PIN9. PIN8 and PIN9 can be directly connected.
10
11
12
13
14
15
n.c.
Not connected
Vcc3 shunt
Vcc3 base
GND
Vcc3REF
INT
PNP Shunt; External PNP emitter voltage.
PNP Base; External PNP base voltage.
Ground
External PNP Output Voltage
Interrupt Output, configuration Input; used as wake-up flag from SBC Stop Mode
and indicating failures. Active low. Integrated pull up. During start-up used to set the
SBC configuration. External Pull-up sets config 1/3, no external Pull-up sets config
2/4.
16
17
Vcc1 µc
Vcc2
Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external
capacitor.
Voltage Regulator Output; 5 V supply; to stabilize block to GND with an external
capacitor.
18
19
20
21
22
23
24
25
26
VccHSCAN
CANH
SPLIT
CANL
GND
TxDCAN
RxDCAN
n.c.
Supply Input; for the internal HS CAN cell.
CAN High Line; High in dominant state.
Termination Output; to support recessive voltage level of the bus lines.
CAN Low Line; Low in dominant state.
Ground
CAN Transmit Data Input; integrated pull-up resistor.
CAN Receive Data Output
Not connected
n.c.
Not connected
Data Sheet
8
Rev. 1.0, 2009-05-26
TLE8261-2E
Pin Configuration
Pin
27
28
29
30
31
32
33
Symbol
n.c.
n.c.
n.c.
n.c.
GND
n.c.
LH_SI
Function
Not connected
Not connected
Not connected
Not connected
Ground
Not connected
Limp Home side indicator; Side indicators 1.25Hz 50% duty cycle output; Open
drain. Active LOW.
34
WK
Monitoring / Wake-Up Input; bi-level sensitive input used to monitor signals
coming from, for example, an external switch panel; also used as wake-up input;
35
36
Limp Home
LH_PL/Test
Fail-Safe Function Output; Open drain. Active LOW.
SBC SW Development Mode entry; Connect to GND for activation; Integrated pull-
up resistor. Connect to VS or leave open for normal operation.
Limp Home Pulsed Light output: Brake/rear light 100Hz 20% duty cycle output;
Open drain. Active LOW.
EDP
-
Exposed Die Pad; For cooling purposes only, do not use it as an electrical ground.1)
1) The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the PCB. The exposed
die pad is not connected to any active part of the IC and can be left floating or it can be connected to GND for the best EMC
performance.
Data Sheet
9
Rev. 1.0, 2009-05-26
TLE8261-2E
State Machine
4
State Machine
4.1
Block Description
First battery connection
(POR)
AND
config0 not active
Condition / event
SBC action
SBC Init mode
(256ms max after reset relaxation)
Vcc1
on
Vcc2/3
off
WD
conf
SPI cmd
SPI cmd
CAN
inact
L.H.
inact
SPI cmd
reset (initiated by SBC)
SBC SW Flash mode
SBC Normal mode
Vcc1
on
Vcc2/3
on/off
WD
Vcc1
Vcc2/3
on/off
WD
conf
WD trig
WD trig
fixed
on
CAN
CAN
conf
L.H.
act/inact
L.H.
act/inact
Tx/Rx
SPI cmd
SPI cmd
OR
SPI cmd
SPI cmd
WD failed
NOT reset clamped
(high or low)
OR
SBC Sleep mode
SBC Stop mode
NOT undervoltage
at Vcc1
Detection of falling edge at reset
pin (any mode)
Vcc2/3
off
WD
off
Vcc1
off
WD trig
Vcc1
Vcc2/3
on/off
WD
OR
WK event stored
LH entry condition
stored
SPI cmd
undervoltage reset at VCC1µC
(any mode)
fixed/off
on
CAN
Wakable/
off
L.H.
act/inact
CAN
wakable/
off
OR
L.H.
act/inact
Restart entry
condition stored
Wake up event
SBC Restart mode
First battery connection
1st (config1) or 2nd (config3) WD trig
(POR)
AND
failure
Vcc1
Vcc2/3
on/off
Reset
act.
Init mode not successful
Config 1/3:
in Normal / Stop / SW Flash mode
config0
on
Config 1/3:
Reset clamped LOW (any
mode)
Reset clamped HIGH during restart/ init
L.H.
act/inact
CAN
waked or off
SBC SW Development
mode
Vcc1
Vcc2/3
WD
CAN, WK Wake-up
OR
Release of over temperature at Vcc1
mode set mode set mode set
(Wake-up event stored)
(LH entry condition stored)
L.H.
CAN
mode set mode set
SBC Fail-Safe mode
SBC Factory Flash mode
Config 2/4:
Reset clamped HIGH during Restart
or Init mode
1st (config2) or 2nd (config4) WD trig failure
in Normal / Stop / SW Flash mode
Vcc1
Vcc2/3
off
WD
off
Vcc1
ext.
Vcc2/3
off
WD
off
off
Config 2/4:
Reset clamped LOW (any
mode)
Vcc1 over temperature shutdown
OR
L.H.
act
CAN
L.H.
CAN
off
sleep
inact.
V
S > VUV_ON & Undervoltage time
out on VCC1
Power mode managment8261.vsd
Figure 3
Power Mode Management
Data Sheet
10
Rev. 1.0, 2009-05-26
TLE8261-2E
State Machine
4.2
State Machine Description
The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash,
Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test
pin and via three mode select bits MS2..0, within the SPI. Additionally, the SBC allows five configurations,
accessed via two external pins and one SPI bit.
4.2.1
Configuration Description
Table 1 provides descriptions and conditions for entry to the different configurations of the SBC.
Table 1 SBC Configuration
Configuration Description
Test pin INT Pin WD to
LH bit
config 0
config 1
Software Development Mode
0V
n.a
External
pull-up
n.a
0
After missing the WD trigger for the first time, the state of Vcc1µC Open / VS
remain unchanged, LH pin is active, SBC in Restart Mode
config 2
config 3
After missing the WD trigger for the first time, Vcc1µC turns OFF,
No ext.
0
1
LH pin is active, SBC in Fail-Safe Mode
pull-up
After missing the WD trigger for the second time, the state of
External
pull-up
V
cc1µC remain unchanged, LH pin is active, SBC in Restart
Mode
config 4
After missing the WD trigger for the second time, Vcc1µC turns
No ext.
pull-up
1
OFF, LH pin is active, SBC in Fail-Safe Mode
In SBC SW Development Mode, Config 1 to 4 are accessible.
4.2.2
SBC Power ON Reset (POR)
At VS > VUVON, the SBC starts to operate, by reading the test pin and then by turning ON Vcc1µC. When Vcc1µC
reaches the reset threshold VRT1, the reset output remains activated for tRD1 and the SBC enters then the Init Mode.
In the event that Vs decreases below VUVOFF, the device is completely disabled. For more details on the disable
behavior of the SBC blocks, please refer to the chapter specific to each block.
4.2.3
SBC Init Mode
At entering the SBC Init Mode, the SBC starts to read the Test pin. The SBC starts-up in SBC Init Mode, and, after
powering-up, waits for the microcontroller to finish its startup and initialization sequences. Vcc2/3 are OFF and the
Watchdog is configurable but not active. CAN is inactive and Limp Home output is inactive. From this transition
mode, the SBC can be switched via SPI command to the desired operating mode, SBC Normal or Software Flash
Mode. If the SBC does not receive any SPI command, or receive wrong SPI command (i.e. not send the device
to SBC Normal or SBC SW Flash Mode) within a 256 ms time frame after the reset relaxation, it will enter into SBC
Restart Mode and activate the Limp Home output.
Note:In Init Mode it is recommended to send one SPI command that sets the device to Normal Mode, triggers the
watchdog the first time and sets the required watchdog settings.
Data Sheet
11
Rev. 1.0, 2009-05-26
TLE8261-2E
State Machine
4.2.4
SBC Normal Mode
SBC Normal Mode is used to transmit and receive CAN messages. In this mode, Vcc1µC is always “ON” Vcc2 and
V
cc3 can be turned-on or off by SPI command. In Normal Mode the watchdog needs to be triggered. It can be
configured via SPI, window watchdog and time-out watchdog is possible (default value is time-out 256 ms). All the
wake-up sources can be inhibited in this mode. The Limp Home output can be enabled or disabled via SPI
command. Via SPI command, the SBC can enter Sleep, Stop or Software Flash Mode. A reset is triggered by the
SBC when entering the Software Flash Mode. It is recommended to send at first SPI command the watchdog
setting. Please refer to Chapter 12.4.
4.2.5
SBC Sleep Mode
During SBC Sleep Mode, the lowest power consumption is achieved by having the main and external voltage
regulators switched-off. As the microcontroller is not supplied, the integrated Watchdog is disabled in Sleep Mode.
The last Watchdog configuration is not stored. The CAN module is in Wake-capable or OFF modes and the Limp
Home output is unchanged, as before entering the Sleep Mode. If a wake-up appears in this mode, the SBC goes
into Restart Mode automatically. In Sleep Mode, not all wake-up sources should be inhibited, this is required to
not program the device in a mode where it can not wake up. If all wake sources are inhibited when sending the
SBC to Sleep Mode, the SBC does not go to Sleep Mode, the microcontroller is informed via the INT output, and
the SPI bit “Fail SPI” is set. The first SPI output data when going to SBC Normal Mode will always indicate the
wake up source, as well as the SBC Sleep Mode to indicate where the device comes from and why it left the state.
Note:Do not change the transceiver settings in the same SPI command that sends the SBC to Sleep Mode.
4.2.6
SBC Stop Mode
The Stop Mode is used as low power mode where the µC is supplied. In this mode the voltage regulator Vcc1µC
remains active. The other voltage regulator (Vcc2/3) can be switched on or off.
The watchdog can be used or switched off. If the watchdog is used the settings made in Normal Mode are also
valid in Stop Mode and can not be changed.
The CAN is not active. It can be selected to be off or used as wake-up source. If all wake up sources are disabled,
(CAN, WK, cyclic wake) the watchdog can not be disabled, the SBC stays in Normal Mode and the watchdog
continues with the old settings.
If a wake-up event occurs the INT pin is set to low. The µC can react on the interrupt and set the device into Normal
Mode via SPI. There is no automatic transition to SBC Normal Mode.
There are 4 Options for SBC Stop Mode
•
•
•
•
WD on (the watchdog needs to be served as in Normal Mode
WD off (special sequence required see Chapter 10.2.4)
Cyclic Wake up with acknowledge (interrupt is sent after set time and needs to be acknowledged by SPI read)
Cyclic Wake-up, Watchdog off (interrupt is sent after set time)
Cyclic Wake-Up Feature
SBC Stop Mode supports the cyclic wake-up feature. By default, the function is OFF. It is possible to activate the
cyclic wake-up via “Cyclic WK on/off” SPI bit. This feature is useful to monitor battery voltage, for example, during
parking of the vehicle or for tracking RF data coming via the RF receiver. The Cyclic Wake-up feature sends an
interrupt via the pin INT to the µC after the set time. The cyclic wake-up feature shares the same clock as the
Watchdog. The time base set in the SPI for the Watchdog will be used for the cyclic wake-up. The timer has to be
set before activating the function. With the cyclic wake-up feature the watchdog is not working as known from the
other modes. In the case that both functions (Watchdog and cyclic wake-up) are selected, the cyclic wake-up is
activated and each interrupt has to be acknowledged by reading the SPI Wake register before the next Cyclic
Wake-Up comes. Otherwise, the SBC goes to SBC Restart Mode.
Data Sheet
12
Rev. 1.0, 2009-05-26
TLE8261-2E
State Machine
4.2.7
SBC Software Flash Mode
SBC Software Flash Mode is similar to SBC Normal Mode regarding voltage regulators. In this mode, the Limp
Home output can be set to active LOW via SPI and the communication on CAN is activated to receive flash data.
The Watchdog configuration is fixed to the settings used before entering the SBC SW Flash Mode. When the
device comes from SBC Normal Mode, a reset is generated at the transition.
From the SBC Software Flash Mode, the SBC goes into SBC Restart Mode, the config setting has no influence
on the behavior. A mode change to SBC Restart Mode can be caused by a SPI command, a time-out or Window
Watchdog failure or an undervoltage reset. When leaving the SBC Software Flash Mode a reset is generated.
4.2.8
SBC Restart Mode
They are multiple reasons to enter the SBC Restart Mode and multiple SBC behaviors described in Table 2.
In any case, the purpose of the SBC Restart Mode is to reset the microcontroller.
•
•
From SBC SW Flash Mode, it is used to start the new downloaded code.
From SBC Normal, SBC Stop Mode and SBC SW Flash Mode it is reached in case of undervoltage on Vcc1µC
or due to incorrect Watchdog triggering.
,
•
•
•
From SBC Sleep Mode it is used to ramp up Vcc1µC after wake
From SBC Init Mode, it is used to avoid the system to remain undefined.
From SBC Fail-safe Mode it is used to ramp up Vcc1µC after wake or cool down of Vcc1µC.
From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode. The delay time tRDx is programmable
by the “Reset delay” SPI bit. The Reset output (RO) is released at the transition. SBC Restart Mode is left
automatically by the SBC without any microcontroller influence. The first SPI output data will provide information
about the reason for entering Restart Mode. The reason for entering Restart Mode is stored and kept until the
microcontroller reads the corresponding “LH0..2” or “RM0..1” SPI bits. In case of a wake up from Sleep Mode the
wake source is seen at the interrupt bits (Configuration select 000), an interrupt is not generated.
Entering or leaving the SBC Restart Mode will not result in deactivation of the Limp Home output (if activated).
The first SPI output data when going to SBC Normal Mode will always indicate the reason for the SBC Restart
event.
Data Sheet
13
Rev. 1.0, 2009-05-26
TLE8261-2E
State Machine
Table 2
SBC Restart Mode Entry Reasons and Actions
SBC Mode and Configuration Entering reason
Actions
LH output
ON
Mode
Config
Vcc1µC
remains ON LOW
RO
SPI Out Bits
LH 0..2
n.a
Init Mode time-out
Reset low from
outside
Init Mode
n.a.
Unchanged
remains ON LOW
RM 0..1
config 1/3 Reset clamped
ON
unchanged
ON
remains ON LOW
ramping up LOW
LH 0..2
RM 0..1
LH 0..2
n.a
undervoltage reset
config 1
OFF after 1st
ON after 2nd
OFF after 1st
RM 0..1 after 1st
LH 0..2 after 2nd
config 3
config 4
n.a.
WD trigger failure
remains ON LOW
Normal1)
RM 0..1 after 1st2)
Reset low from
outside
Unchanged
remains ON LOW
RM 0..1
config 1/3 Reset clamped
ON
remains ON LOW
remains ON LOW
remains ON LOW
remains ON LOW
LH 0..2
RM 0..1
RM 0..1
RM 0..1
n.a
n.a
n.a
undervoltage reset
SPI cmd
WD trigger failure
unchanged
unchanged
unchanged
Software Flash
Sleep
Reset low from
outside
config 1/3 Reset clamped
n.a.
Unchanged
remains ON LOW
RM 0..1
ON
remains ON LOW
ramping up LOW
ramping up LOW
LH 0..2
WK bits register
RM 0..1
n.a
n.a
config 1
Wake-up event
undervoltage reset
unchanged
unchanged
ON
LH 0..2
OFF after 1st
ON after 2nd
OFF after 1st
RM 0..1 after 1st
LH 0..2 after 2nd
config 3
config 4
n.a.
WD trigger failure
remains ON LOW
Stop1)
RM 0..1 after 1st2)
Reset low from
outside
Unchanged
remains ON LOW
RM 0..1
config 1/3 Reset clamped
ON
ON
unchanged
remains ON LOW
ramping up LOW
ramping up LOW
LH 0..2
LH 0..2
RM 0..1
Fail-Safe
n.a.
n.a
Wake-up event
undervoltage reset
Software
Development
Mode
Reset low from
outside
config 1/3 Reset clamped
n.a.
Unchanged
remains ON LOW
RM 0..1
LH 0..2
ON
remains ON LOW
1) Config 2 will never enter Restart Mode in case of WD failure but directly Fail-Safe Mode
2) Goes to Fail-Safe Mode after the second consecutive failure
Data Sheet
14
Rev. 1.0, 2009-05-26
TLE8261-2E
State Machine
4.2.9
SBC Fail-Safe Mode
In SBC Fail-Safe Mode, all voltage regulators are OFF and the transceivers are in Wake-Capable Mode. The Limp
Home output is active.
Conditions to enter the SBC Fail-Safe Mode are:
•
•
•
•
Watchdog trigger failure in configuration 2 or 4
V
cc1µC undervoltage time-out in any configuration if VS is above VLHUV range.
Temperature shutdown of Vcc1µC in any configuration.
Reset clamped in Config. 2/4
In case of Vcc1µC overtemperature shutdown, the SBC will latch and wait to cool down below the thermal hysteresis,
and will go back to SBC Restart Mode.
In case of a wake-up event, the SBC will go to SBC Restart Mode (not in case of Vcc1µC overtemperature
shutdown), storing the wake-up event and resetting the Watchdog trigger failure counter. The first SPI output data
when going to SBC Normal Mode will always indicate the reason for the SBC Fail-Safe Mode.
4.2.10
SBC Software Development Mode
If the Test pin is connected to GND (Config 0 active) during powering-up, the SBC enters SBC Software
Development Mode. SBC Software Development Mode is a super set of the other modes so it is possible to use
all the modes of the SBC with the following difference. In SBC Software Development Mode, no reset is generated
and VCC1µC is not switched off due to Watchdog trigger failure. If a Watchdog trigger failure occurs, it will be
indicated by the INT output (reset bit). The SBC Fail-Safe Mode or SBC Restart Mode are not reached in case of
wrong Watchdog trigger but the other reasons to enter these modes are still valid.
4.2.11
SBC Factory Flash Mode
In this mode, the SBC is completely powered OFF and the microcontroller is supplied externally. The mode is
detected when VCC1µC is powered from external and the voltage on Vs is not powered from external. The current
flow out of Vs must be limited to the maximum rating. The external supply voltage should be below the absolute
maximum rating stated in Chapter 5.1. The reset can be driven by an external circuit, or pulled high with a pull-up
resistor.
Note:Please respect the absolute maximum ratings when the device is in SBC Factory Flash Mode.
Data Sheet
15
Rev. 1.0, 2009-05-26
TLE8261-2E
General Product Characteristics
5
General Product Characteristics
5.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter
Symbol
Limit Values
Unit Test Conditions
Min.
Max.
Voltages
5.1.1 Supply Voltage
VS
dVS/dt
Vcc1µC/2/3 -0.3
VCANH/L
-0.3
-0.5
40
5
5.5
40
40
V
–
5.1.2 Supply Voltage Slew Rate
5.1.3 Regulator Output Voltage
5.1.4 CAN Bus Voltage (CANH, CANL)
V/µs –
V
V
V
–
–
-27
-40
5.1.5 Differential Voltage CANH, CANL, SPLIT VdiffESD
CANH-CANL<|40 V|;
CANH-SPLIT<|40 V|
CANL-SPLIT<|40 V|;
5.1.6 Input Voltage at VCCHSCAN
5.1.7 Voltage at SPLIT, WK
5.1.8 Voltage at LH_PL/Test
5.1.9 Voltage at Vcc3base, Vcc3shunt, Vcc3REF
5.1.10 Voltage at Limp Home (LH, LH_SI pin) VLH
VCCHSCAN -0.3
VSPLIT -27
VTest,max -0.3
5.5
40
40
40
40
V
V
V
V
V
V
–
–
–
–
–
Vcc3base
-0.3
-0.3
-0.3
5.1.11 Logic Voltages Input Pin (SDI, CLK,
VI
VCC1µC
+
+
0 V < VS < 28 V
CSN, TxDCAN)
0.3V
0 V < VCC1µC < 5.5 V
5.1.12 Logic Voltage Output PIN (SDO, RO,
INT, RxDCAN)
VDRI,RD
-0.3
VCC1µC
V
0 V < VS < 28 V
0.3V
0 V < VCC1µC < 5.5 V
Currents
5.1.13 Reverse current on pin Vs
-500
–
mA VS < VCC
IVS
Temperatures
5.1.14 Junction Temperature
5.1.15 Storage Temperature
ESD Susceptibility
Tj
Tstg
-40
-55
150
150
°C
°C
–
–
5.1.16 Electrostatic Discharge Voltage at
VESD
VESD
-6
-2
6
kV
kV
V
2) HBM (100 pF via
CANH, CANL, SPLIT versus GND
1.5 kΩ)
5.1.17 Electrostatic Discharge Voltage
2
2) HBM (100 pF via
1.5 kΩ)
3)
5.1.18 Electrostatic Discharge CDM
Corner Pins (Pin 1, 18, 19, 36)
VESD_CDM -750
_C
750
500
3)
Electrostatic Discharge CDM
VESD_CDM -500
V
1) Not subject to production test; specified by design
2) ESD susceptibility Human Body Model “HBM” according to JESD22-A114
3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Data Sheet
16
Rev. 1.0, 2009-05-26
TLE8261-2E
General Product Characteristics
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
5.2
Functional Range
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
VUV OFF
Max.
28
5.2.1
5.2.2
Supply Voltage
Supply Voltage
VS
VS
V
V
After VS rising above
1)
VUV ON
;
2)
VUV OFF
40
t
= 400 ms
pulse
40 V load dump;
Ri = 2Ω
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
SPI Clock Frequency
SPI Clock Frequency
Junction Temperature
Undervoltage “OFF”
Undervoltage “ON
fclkSPI
fclkSPI
Tj
VUV OFF
VUV ON
VS_LH
–
–
-40
3
4.5
5.5
4
1
150
4
5.5
40
MHz
MHz
°C
V
V
V
3)VS > 5.5 V
If VUV ON> VS> VUV OFF;
–
1)
-
-
1)
Supply Voltage for Limp Home
Output Active
Pull up to VS
RLHO = 40kΩ
1) In the case Vs < VUVOFF, the SBC is switched OFF and will restart in INIT Mode at next Vs rising.
2) During load dump, the others pins remains in their absolute maximum ratings
3) Not subject to production test, specified by design
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
17
Rev. 1.0, 2009-05-26
TLE8261-2E
General Product Characteristics
5.3
Thermal Characteristics
Pos.
5.3.1
Parameter
Symbol
Limit Values
Unit
Test Conditions
Min.
–
Typ.
Max.
Junction Ambient
RthJA_1L
RthJA_4L
RthJSP
40
K/W
K/W
K/W
1) 3) 300 mm2
cooling area
Junction Ambient
–
25
5
2) 3)2s2p + 600 mm2
cooling area
3)
5.3.2
Junction to Soldering Point
–
–
Thermal Prewarning and Shutdown Junction Temperatures;
3)
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
V
CC1µC, Thermal Pre-warning
ON Temperature
CC1µC, Thermal Prewarning
Hysteresis
TjPW
120
145
25
170
–
°C
K
-
3)
3)
3)
3)
3)
3)
V
∆TPW
–
VCC1µC,
V
CC2 Thermal Shutdown
TjSDVcc
∆TSDVcc
150
–
185
35
200
–
°C
K
Temperature
VCC1µC, VCC2 Thermal Shutdown
Hysteresis
VCC1µC, Ratio of SD to PW
Temperature
CAN Transmitter Thermal
Shutdown Temperature
CAN Transmitter Thermal
Shutdown Hysteresis
TjSDVcc/
–
1.20
–
–
–
TjPW
TjSDCAN
150
–
200
–
°C
K
∆TCAN
10
1) Specified Rthja value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 single layer. The product (chip +
package) was simulated on a 76.4 x 114.3 x 1.5 mm board.
2) According to Jedec JESD51-2,-5,-7 at natural convection on 2s2p board for 2W. Board: 76.2x114.3x1.5mm³ with 2 inner
copper layers (35µm thick)., with thermal via array under the exposed pad contacted the first inner copper layer and
600mm2 cooling are on the top layer (70µm)
3) Not subject to production test; specified by design;
Data Sheet
18
Rev. 1.0, 2009-05-26
TLE8261-2E
General Product Characteristics
5.4
Current Consumption
VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit
Test Condition
Min.
Typ.
Max.
Normal Mode;
5.4.1
5.4.2
Current Consumption for IVS_logic
–
–
2
mA
SBC Normal Mode
Internal Logic
ICC1µC = ICC2 = 0mA;
CAN OFF mode;
Additional current
Consumption for CAN Cell
IVS_CAN
–
–
–
–
10
mA
mA
CAN Normal Mode;
Recessive state; VCC2
connected to VCCHSCAN
V
TxD = Vcc1µC
;
without RL
12
75
CAN Normal Mode;
dominant state; VCC2
connected to VCCHSCAN
V
TxD = low;
without RL;
Stop Mode
5.4.3
Current Consumption
IVS
–
58
µA
µA
SBC Stop Mode;
Vs = 13.5 V;
V
V
CC1µC“ON”;
CC2/3“OFF”
CAN wake capable;
Tj = 25°C
65
70
85
90
Tj = 85°C1)
–
–
SBC Stop Mode;
Vs = 13.5 V;
V
V
CC1µC/2“ON”;
CC3“OFF”
CAN wake capable;
Tj = 25°C
78
100
Tj = 85°C1)
Data Sheet
19
Rev. 1.0, 2009-05-26
TLE8261-2E
General Product Characteristics
5.4
Current Consumption (cont’d)
VS = 5.5 V to 28 V; all outputs open; Without VCC3; Tj = -40 °C to +150 °C; all voltages with respect to ground;
positive current defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit
Test Condition
Min.
Typ.
Max.
Sleep Mode
5.4.4
5.4.5
Current consumption, all IVS_sleep_
–
28
40
µA
SBC Sleep Mode;
Tj = 25°C
Wake Up Sources
SBC
available.
Vs = 13.5 V;
V
CC1µC/2/3“OFF”
CAN wake capable;
32
12
50
–
Tj = 85°C1)
Quiescent Current
Reduction when Wake
Capable CAN Cell
Disabled
IVS_sleep_
CAN
5
µA
1)SBC Sleep Mode;
Tj = 25°C;
VS = 13.,5 V;
V
CC1µC/2/3“OFF”
CAN OFF
1) Not subject to production test; specified by design
Data Sheet
20
Rev. 1.0, 2009-05-26
TLE8261-2E
Internal Voltage Regulator
6
Internal Voltage Regulator
6.1
Block Description
VCC1µC
Vs
VCC2
Vref
1
State
Machine
Overtemperature
Bandgap
Shutdown
Reference
INH
1
Vref
Charge
Pump
INTERNAL REGULATOR DIAGRAM.VSD
GND
Figure 4
Functional Block Diagram
The internal voltage regulators are dual low-drop voltage regulators that can supply loads up to ICC1µC/2_max. An
input voltage up to VSMAX is regulated to Vcc1µC/2_nom = 5.0 V with a precision of 2%. Due to its integrated reset
circuitry, featuring two SPI configurable power-on timing (tRDx) and three SPI configurable output voltages (VRTx
)
monitoring, the device is well suited for microcontroller supply. The design enables stable operation even with
ceramic output capacitors down to 470nF, with ESR < 1 Ω @ f = 10 kHz. The device is designed for automotive
applications, therefore it is protected against overload, short circuit, and overtemperature conditions. Figure 4
shows the functional block diagram. If the VS voltage is lower than VUV_OFF, the DMOS of the voltage regulator is
switched to high impedance. The body diodes of the DMOS might go into conduction when VCC1µC or VCC2 > VS
(no reverse protection).
6.2
Internal Voltage Regulator Modes
It is possible to turn Vcc1µC via SBC Modes and Vcc2 activity ON or OFF via SPI command or by entering SBC
modes. The limiting current for the both regulators is ICC1µC_max/ICC2
.
6.3
Internal Voltage Regulator Modes with SBC Mode
Depending on the SBC Mode in use, Vcc1µC and Vcc2 can be either ON or OFF by definition, Vcc2 can be also turned
ON or OFF, via SPI. Table 3 identifies the possible states of the voltage regulators, based on the various SBC
modes.
Data Sheet
21
Rev. 1.0, 2009-05-26
TLE8261-2E
Internal Voltage Regulator
Table 3
SBC Mode
Internal Voltage Regulators States
Vcc1µC
Vcc2
INIT Mode
ON
ON
OFF
ON
ON
ON
OFF
OFF
ON
OFF
unchanged
ON
Normal Mode
Sleep Mode
Restart Mode
Software Flash Mode
Stop Mode
OFF
OFF
OFF
ON
OFF
Fail-Safe Mode
6.4
Application information
Timing Diagram
6.4.1
Figure 5 shows the ramp up and down of the VS, and the dependency of Vcc1µC. At the first ramp up from SBC Init
Mode, the reset threshold VRT and time tRO are set to the default value. See Chapter 10.1
Vs
VUV ON
VUV OFF
t
t
Vcc1µC
VRTx,r
VRTx,f
GND
RO
SBC OFF
SBC Init
Any mode
SBC OFF
t
Figure 5
Ramp up / Down of Main Voltage Regulator
An undervoltage time-out on Vcc1µC is implemented. Refer to Chapter 12 for more information on this function.
6.4.2
Under voltage detection at Vcc2
The Vcc2 voltage regulator integrates an under voltage detection. When Vcc2 voltage goes below VUV_VCC2, the
failure is indicated by an interrupt and the failure is reported into the diagnosis frame of the SPI.
Data Sheet
22
Rev. 1.0, 2009-05-26
TLE8261-2E
Internal Voltage Regulator
6.5
Electrical Characteristics
VS = 5.5 V to 28 V; CCC1µC = CCC2 = 470 nF; all outputs open; SBC Normal Mode;
Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless
otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
Voltage Regulator; Pin Vcc1 µC
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
Output Voltage
Line Regulation
Load Regulation
VCC1µC
4.9
–
5.0
–
5.1
20
50
–
V
0 mA <ICC1µC<200 mA;
5.5 V < VS < 28 V;
mV 6 V < VS < 16 V;
CC1µC = 0 A
∆VCC1µC,Li
∆VCC1µC,Lo
PSRR
I
–
–
mV 5 mA <ICC1µC<200 mA;
VS = 6 V
Power Supply Ripple
Rejection
Output Current Limit
–
40
–
dB
Vr = 1 Vpp;
fr = 100 Hz;1)
Icc1µC max
200
500
mA
Vcc1µC = 4.5 V;
power transistor thermally
monitored;
6.5.6
Drop Voltage
VDR Vcc1µC
–
–
0.5
V
V
I
CC1µC = 150 mA; 2)
Voltage Regulator; Pin Vcc2
6.5.7
6.5.8
6.5.9
6.5.10
6.5.11
Output Voltage
Line Regulation
Load Regulation
VCC2
4.9
–
5.0
–
5.1
20
50
–
0 <ICC2<200 mA;
5.5 V < VS < 28 V;
∆VCC2,Li
∆VCC2,Lo
PSRR
Icc2
mV 6 V < VS < 16 V;
I
CC2 = 0 A;
–
–
mV 5 mA <ICC2<200 mA;
VS = 6 V
Power Supply Ripple
Rejection
Output Current Limit
–
40
–
dB
Vr = 1 Vpp;
fr = 100 Hz;1)
200
500
mA
Vcc2 = 4.5 V;
power transistor thermally
monitored;
6.5.12
6.5.13
Drop Voltage
Under voltage detection
on Vcc2
VDR_Vcc2
VUV_VCC2
–
4.5
–
4.65
0.5
4.8
V
V
I
CC2 = 150 mA;2)
VCC2 falls until INT = LOW
1) specified by design; not subject to production test.
2) Measured when the output voltage has dropped 100 mV from the nominal Value obtained at Vs = 13.5 V. Specified drop
voltage for Vs > 4 V.
Data Sheet
23
Rev. 1.0, 2009-05-26
TLE8261-2E
External Voltage Regulator
7
External Voltage Regulator
7.1
Block Description
V
cc3 is activated via SPI. The external voltage regulator circuitry is designed to drive an external PNP transistor to
increase output current flexibility. Four pins are used: VS, Vcc3base, Vcc3shunt and Vcc3ref. One transistor is tested
during production. An input voltage up to VSMAX is regulated to VQ,nom = 5.0 V with a precision of ±4%. The output
current of the transistor is monitored via an external shunt resistor. The state of Vcc3 is reported in the diagnostic
SPI register. When battery voltage is below the minimum operating battery voltage Vs < VVextUV, the external
voltage regulator switches off. Figure 7 shows the behavior during this phase. The shunt is used for overcurrent
limitation. If this feature is not needed, connect pins Vcc3shunt and Vs together.
Since the junction temperature of the external PNP transistor cannot be read, it cannot be protected against over
temperature by the SBC, and so the thermal behavior has to be checked by the application.
VS
Vcc3shunt
Vcc 3base
Vcc 3ref
RBE
VS-VCC3shunt
>
ICC3base
Vshunt_threshold
+
-
VREF
State machine
External voltage diagram .vsd
Figure 6
Functional Block Diagram
7.2
External Voltage Regulator Mode
It is possible to turn the Vcc3 ON or OFF via SPI command, depending on the SBC modes. Table 4 identifies the
possible states, based on the different SBC modes.
7.3
External Voltage Regulator State by SBC Mode
Table 4 shows the possible states of the Vcc3 external voltage regulator as a function of the SBC mode.
Table 4
External Voltage Regulator State by SBC Mode
SBC Mode
INIT Mode
Vcc3
OFF
Normal Mode
Sleep Mode
ON
OFF
OFF
Restart Mode
SW Flash Mode
Stop Mode
Unchanged
ON
ON
OFF
OFF
Fail-Safe Mode
OFF
Data Sheet
24
Rev. 1.0, 2009-05-26
TLE8261-2E
External Voltage Regulator
7.4
Application Information
Timing information
7.4.1
Figure 7 shows the typical timing, ramp up and ramp down of the External Voltage Regulator, in regards to the VS
pin.
Vs
VVextUV
VUV_OFF
t
Vcc3
Vcc3
SPI
GND
t
Undervoltage Managment vcc 3.vsd
Figure 7
Supply Voltage Management
7.4.2
External Components
During production test, the listed parameter are tested with the PNP transistor MJD253 from ON semi.
Characterization is done with the BCP52-16 from Infineon (ICC3<200 mA). Other PNP transistors can be used.
Function must be checked in the application.
Figure 8 shows the hardware set up used.
VS
VCC3
RSHUNT
T1
ICC3
C2
C1
Vcc3shunt
Vcc3ref
VS
Vcc3base
RBE
VS-VCC3shunt
>
ICC3base
Vshunt_threhold
+
-
VREF
State machine
External voltage diagram_appli_note.vsd
Figure 8
Hardware Set Up
Data Sheet
25
Rev. 1.0, 2009-05-26
TLE8261-2E
External Voltage Regulator
Table 5
Device
C2
RSHUNT
T1
Bills of material for the VCC3 function
Vendor
Murata
-
Reference / Value
10µF/10V GCM31CR71AA106K
220mΩ
MJD253
ON semi
7.4.3
Calculation of RSHUNT
The maximum current ICC3max where the limit starts and the bit ICC3>ICC3max is set is determined by the shunt
resistor RShunt and the Output Current Shunt Voltage Threshold Vshunt_threshold
.
The resistor can be calculated as following
U
shunt_threshold
R
= --------------------------------------
SHUNT
I
CC3max
7.4.4
Unused Pins
In case the Vcc3 is not used in the application, it is recommended to connect the unused pins of Vcc3 as followed.
Connect Vcc1shunt to Vs. (It is also possible to leave the pin open)
Leave Vcc3base open
Leave Vcc3ref open
Do not enable the Vcc3 via SPI as this leads to increased current consumption.
Data Sheet
26
Rev. 1.0, 2009-05-26
TLE8261-2E
External Voltage Regulator
7.5
Electrical Characteristics
VS = 5.5 V to 28 V; SBC Normal Mode; all outputs open;
Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into pin; unless
otherwise specified.
Pos.
Parameter
Symbol Limit Values
Unit
Test Condition
Min.
Typ.
Max.
Parameters independent from test set-up
7.5.1
External Regulator
Control Drive Current
Capability
Icc3base 20
70
mA
V
CC3base = 28V
7.5.2
7.5.3
Input Current Vcc3ref
Icc3ref
10
25
25
50
50
µA
µA
V
V
cc3ref = 5 V
cc3shunt = VS
Input Current Vcc3 Shunt Icc3shunt 10
Pin
7.5.4
7.5.5
7.5.6
7.5.7
V
CC3 Undervoltage
VCC3,UV 4.0
VCC3,UV, 20
4.25
100
110
-
4.5
250
130
5
V
–
Detection
V
CC3 Undervoltage
mV
mV
µs
detection hysteresis
hys
1)
Output Current Shunt
Voltage Threshold
Current increase
regulation reaction time
Vshunt_thr 88
eshold
trIinc
-
V
cc3 = 6V to 0V;
I
CC3base,50% = 20mA
Figure 9
cc3 = 0V to 6V; ICC3base,50%
= 20mA Figure 9
CC3base = VS
Tj = 25°C
CC3ref = 5V
Tj = 25°C
CC3shunt = VS
Tj = 25°C
7.5.8
Current decrease
trIdec
-
-
-
5
5
2
5
µs
V
regulation reaction time
7.5.9
Leakage current ofVcc3base Icc3base_lk
-
µA
µA
µA
V
when Vcc3 disabled
7.5.10
7.5.11
Leakage current of Vcc3ref Icc3ref_lk -2
0
-
V
when Vcc3 disabled
Leakage current of
Icc3shunt_l
k
-
V
V
cc3shunt when Vcc3
disabled
7.5.12
7.5.13
7.5.14
Base to emitter resistor
RBE
50
100
-
200
5.5
-
kΩ
V
V
V
CC3base = VS - 0.3V
CC3 OFF
External regulator
minimum Vs voltage
External regulator
minimum Vs voltage
hysteresis
VVextUV 4.5
VVextUVhy
s
-
0.2
V
Parameters dependent on the test set-up, according to the Figure 8
7.5.15
External Regulator Output Vcc3
4.8
5
5.2
V
0 mA <ICC3<400 mA;
5.5 V < VS < 28 V;2)
Voltage
7.5.16
7.5.17
Load Regulation
Line Regulation
∆VCC3,Lo
∆VCC3,Li
-
-
-
-
50
50
mV
mV
2 mA <ICC3<200 mA;
6 V < VS <16 V;
1) Threshold at which the current limitation starts to operate.
2) Tolerance includes load regulation and line regulation.
Data Sheet
27
Rev. 1.0, 2009-05-26
TLE8261-2E
External Voltage Regulator
Timing diagram for regulator reaction time “current increase regulation reaction time” and “current decrease
regulation reaction time”
VCC3
t
ICCbase
ICC3base,50%
trlinc
trldec
t
Figure 9
Regulator Reaction Time
Data Sheet
28
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
8
High Speed CAN Transceiver
8.1
Block Description
VccHSCAN
VCC1µC
SPI Mode
Control
RTD
Driver
CANH
CANL
Output
Stage
TxDCAN
Temp.-
Protection
+
timeout
To SPI diagnostic
VccHS CAN
RxD Diag
VCC1µC
RxDCAN
MUX
Receiver
R SPLIT
SPLIT
GND
Vs
Wake
Receiver
V SPLIT
can block .vsd
Figure 10 Functional Block Diagram
8.2
High-speed CAN Description
The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode data
transmission (up to 1 Mbaud) and reception in automotive and industrial applications. It works as an interface
between the CAN protocol controller and the physical bus lines compatible to ISO/DIS 11898-2 and 11898-5 as
well as SAE J2284.
The CAN transceiver offers low power modes to reduce current consumption. This supports networks with partially
powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is implemented.
It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks,
clamp15/30 applications).
A wake-up from the CAN Wake capable Mode is possible via a message on the bus. Thus, the microcontroller can
be powered down or idled and will be woken up by the CAN bus activities.
Refer to Figure 11 for a description of the matching of the transceiver modes with the SBC mode.
The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support
12 V applications.
Data Sheet
29
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
8.2.1
CAN Normal Mode
To transfer the CAN transceiver into the CAN Normal Mode, an SPI word must be sent. This mode is designed for
normal data transmission/reception within the HS CAN network. It can be accessed in Normal Mode of the SBC,
as well as in SBC Software Flash Mode, and SBC Software Development Mode.
Transmission
The signal from the microcontroller is applied to the TxDCAN input of the SBC. The bus driver switches the
CANH/L output stages to transfer this input signal to the CAN bus lines.
Reduced Electromagnetic Emission
To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically.
Reception
Analog CAN bus signals are converted into digital signals at RxD via the differential input receiver. In CAN Normal
and CAN Receive Only Mode, the split pin is used to stabilize the Recessive Common Mode signal. The RxD pin
is diagnosed and the detected failure is reported to the SPI diagnostic register.
8.2.2
CAN Wake Capable Mode
This mode, which can be used in SBC Stop, Sleep, Restart and Normal Modes by programming via SPI and is
automatically accessed in SBC Fail-Safe Mode, is used to monitor bus activities. A wake up signal on the bus
results in different behavior of the SBC, as described in Table 6. After wake-up the transceiver can be switched
to CAN Normal Mode for communication. To enable the CAN wakeable mode after a wake via CAN, the CAN
transceiver must be switched to CAN Normal Mode, CAN Receive Only Mode or CAN Off, before switching to CAN
Wakeable Mode again.
Table 6
SBC Mode
Action Due to a CAN Wake Up
SBC Mode after wake
Vcc1µC
INT
RxD
Int. Bit
WK CAN
Sleep Mode
Stop Mode
Restart Mode
Fail-Safe Mode
Normal Mode
Restart Mode
Stop Mode
Restart Mode
Restart Mode
Normal Mode
Ramping up
ON
Ramping up / ON
Ramping up
ON
HIGH
LOW1)
HIGH
HIGH
LOW1)
LOW
LOW
LOW
LOW
LOW
1
1
1
1
1
1) When not masked via SPI
Wake-Up in SBC Sleep Mode
Wake-up is possible via a CAN message (filtering time t > tWU), it automatically transfers the SBC into the SBC
Restart Mode and from there to Normal Mode the RxD pins in set to LOW, see Figure 11. The microcontroller is
able to detect the low signal on RxD and to read the wake source out of the “Wake Register Interrupt” register
(000) via SPI. No Interrupt is generated when coming out of Sleep Mode.
Data Sheet
30
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
CAN_H
CAN_L
WAKE
Communication
starts
PATTERN
BUS
WAIT
BUS
OFF
t
t
Vdiff
Vcc1µC/
HSCAN
tWU
t
RxD
CAN Wake
CAN Waked
CAN Normal mode
capable mode
t
SPI command
RO
tROx
SBC Restart
SBC Sleep mode
SBC Normal mode
t
Application with sleep .vsd
Figure 11 Timing during Transition from Sleep to Normal Mode
Wake-Up in SBC Stop Mode
In SBC Stop Mode, if a wake-up is detected, it is signaled by the INT output and by the “WK CAN” SPI bit. It is
also signaled by RxDCAN put to low. The microcontroller should set the device to SBC Normal Mode, there is no
automatic transition to Normal Mode. In Normal Mode the transceiver can be enabled via SPI.
Wake-Up in SBC Restart or SBC Fail-Safe Mode
In SBC Restart or SBC Fail-Safe Mode, if a wake-up is detected, it is signaled by the “WK CAN” SPI bit.
Wake-Up in SBC Normal Mode
In SBC Normal Mode, if a wake-up is detected, it is signaled by the “WK CAN” SPI bit and INT output, and RxD
remains LOW.
Data Sheet
31
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
8.2.3
CAN OFF Mode
CAN OFF Mode, which can be accessed in the SBC Stop, Sleep, Restart and Normal modes, and automatically
accessed in SBC Init and Factory Flash modes, is used to completely stop CAN activities. In CAN OFF Mode, a
wake up event on the bus will be ignored.
8.2.4
CAN Receive Only Mode
In CAN Receive Only Mode (RxD only), the driver stage is de-activated but reception is still operational. This mode
is accessible by an SPI command.
8.2.5
CAN Cell in Disabled State
During disable state, when Vs < VUV_OFF, the CAN cell does not have enough supply voltage. In this state, the
CANH and CANL pins are set to high impedance, to guarantee passive behavior. The maximum current that can
flow in the CANH and CANL pins in this mode are specified by ICANH,lk and ICANL,lk
.
8.3
CAN Cell Mode with SBC Mode
Table 7 shows all the CAN modes accessible to the current SBC Mode. Automatic transition from one CAN mode
to an other is only allowed in the same column.
.
Table 7
HS CAN States, Based on SBC modes
SBC Mode
INIT Mode
CAN Mode
OFF
Normal Mode
Stop Mode
Sleep Mode
Restart Mode
Fail-Safe Mode
SW Flash Mode
OFF
OFF
OFF
OFF
Wake capable
Normal
Wake capable
Wake capable
Wake capable
Wake capable
Normal
Receive only
8.3.1
SBC Normal Transition to Sleep or Stop Mode
During the transition from SBC Normal to Sleep or Stop Modes, the receiver module is deactivated and replaced
by the low power mode receiver for wake-up capability. The next message can be only a wake-up call. It is possible
to set the SBC directly from SBC Normal Mode (with CAN Normal Mode) to SBC Sleep or Stop Mode, but this is
not recommended, because a wake pattern on the CAN network that could occurs during SPI communication
could get lost. It is preferable, in SBC Normal Mode to first send the CAN transceiver into CAN Wake Capable
Mode, and then set the entire device to SBC Sleep or Stop Mode. In the unlikely case that the device would see
a wake up call during the transmission order “SBC go to sleep”, the device will store this event and bypass the
“SBC go to sleep” command to go back into SBC Restart Mode.
Do not change the Transciever setting with the same SPI command that is used to sent the device to Sleep Mode.
8.3.2
Transition from SBC Sleep to other Modes
In SBC Sleep Mode, a wake-up on the CAN cell will set the SBC to Restart Mode automatically if the CAN Wake
Capable Mode of the SBC is selected via SPI. Figure 11 shows the typical timing.
Data Sheet
32
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
8.4
Failure Detection
All failures are reported in the SPI diagnostic encoder, the TxD time-out is reported as TxD shorted to GND. In
case of local failure and Bus Dominat Clamped failure, the transceiver is automatically switched to the CAN
Receive only Mode.
8.4.1
TxD Time-out Feature
If the TxD signal is dominant for a time t > tTxD, the TxD time-out function deactivates the transmission of the signal
at the bus. This is implemented to prevent the bus from being blocked permanently due to an error. The
transmission is released after switching the CAN to Active Mode via SPI. Refer to Figure 12.
TxD Time-out
SPI setting: CAN
Interrupt
TxDCAN
Normal Mode
VCC1µC
GND
t
t
Vdiff
tTxD_TO
Txd timeout .vsd
Figure 12 TxD Time-out diagram
8.4.2
Bus Dominant Clamping
If the HS CAN bus signal in dominant for a time t > tBUS_TO, a bus dominant clamping is detected. The CAN
transceiver is switched to Receive Only Mode. The failure is signaled via SPI. If the bits are not masked the INT
pin is set to low. For operation the transceiver needs to be switched back to Normal Mode via SPI.
8.4.3
TxD to RxD Short Circuit Feature
Similar to the TxD time-out, a TxD to RxD short circuit would also block the bus communication. To avoid this, the
CAN transceiver provides TxD to RxD short circuit detection. In this case, it is recommended to switch OFF the
SBC HS CAN supply (e.g. Vcc2) via SPI command to prevent disturbances on the CAN bus. This failure is reported
into the diagnostic frame of the SPI. The INT pin is set LOW if not disabled via SPI. The transmitter is automatically
inhibited and goes back to normal operation after a SPI command.
8.4.4
Overtemperature
The driver stages are protected against overtemperature. Exceeding the shutdown temperature results in
deactivation of the CAN transceiver. The CAN transceiver is activated gain after cooling down, the device stays in
CAN Active Mode. To avoid a bit failure after cooling down, the signals can be transmitted again only after a
dominant to recessive edge at TxD.
Figure 13 shows how the transmission stage is deactivated and activated again. First, an overtemperature
condition causes the CAN transceiver to be deactivated. After the overtemperature condition is no longer present,
the transmission is released automatically after the TxD bus signal has changed to recessive level.
Data Sheet
33
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
Failure
Overtemp
ON
Overtemperature
OFF
t
t
TxDCAN
VCC1µC
GND
Vdiff
R
Dominant
D
Recessive
t
Figure 13 Release of the Transmission after Overtemperature
8.4.5
Permanent RxD Recessive Clamping
If the RxD signal is permanently recessive (such as shorted to Vcc1µC), although there is a message sent on the
bus, the host microcontroller of this transceiver could start a message at any time because the bus appears to be
idle. To prevent this node from disturbing communication on the bus, the SBC offers permanent RxD recessive
clamping. If the RxD signal is permanently recessive, the failure is diagnosed and the transmitter is deactivated
as long as the error occurs. The transmitter is reactivated after an SPI command.
8.4.6
VccHSCAN Undervoltage
The CAN transceiver cell has no dedicated under voltage detection and use the VCC2 or VCC3 under voltage
circuitry. The µC can switch of the CAN in case of undervoltage.
8.4.7
Bus failures
In case one of the following bus failures is detected by the SBC the interrupt bit CAN BUS is set to “1” and an
interrupt is generated, if not masked. The CAN transceiver does not change the mode due to a detected bus
failure.
Bus Failures
•
•
•
•
•
•
CANH short to GND
CANH short to Vs
CANH short to Vcc
CANL short to GND
CANL short to Vs
CANL short to Vcc
A short of CANH to CANL is detected by the microcontroller as the signal sent on TxD is not received on RxD.
8.5
SPLIT Circuit
SPLIT circuitry is activated during CAN Normal and Receive Only Mode and de-activated (SPLIT pin high ohmic)
during CAN Wake Capable and OFF Modes. The SPLIT pin is used to stabilize the recessive common mode signal
in Normal Mode and RxD Only Mode. This is achieved with a stabilized voltage of 0.5 x VccHSCAN typical at SPLIT.
A correct application of the SPLIT pin is shown in Figure 14. The SPLIT termination for the left and right nodes is
implemented with two 60 Ω resistors and one 10 nF capacitor. The center node in this example is a stub node and
the recommended value for the split resistances is 1.5 kΩ.
Data Sheet
34
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
In the case the application doesn’t request the SPLIT pin feature, the pin has to be left open.
CANH
CANH
60Ohm
60Ohm
TLE 6251 DS
TLE 8264
CAN
Bus
split
termination
split
termination
SPLIT
SPLIT
10nF
10nF
60Ohm
60Ohm
CANL
CANL
10nF
1,5 kOhm
split
1,5 kOhm
termination
at stub
CANH
SPLIT
CANL
TLE 6251 G
NERR
Figure 14 Application example for the SPLIT Pin
.
Data Sheet
35
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
8.6
Electrical Characteristics
4.75 V < VccHSCAN < 5.25 V; VS = 5.5 V to 28 V; RL = 60 Ω; CAN Normal Mode; Tj = -40 °C to +150 °C; all voltages
with respect to ground; positive current flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
CAN Bus Receiver
8.6.1
8.6.2
Differential Receiver
Vdiff,rd_N
–
0.80
0.90
–
V
V
V
diff = VCANH - VCANL
Threshold Voltage,
recessive to dominant
edge
CAN Normal Mode
Differential Receiver
Threshold Voltage,
dominant to recessive
edge
Vdiff,dr_N 0.50
0.60
Vdiff = VCANH - VCANL
CAN Normal Mode
8.6.3
8.6.4
Common Mode Range
Differential Receiver
Hysteresis
CMR
Vdiff,hys_N
-12
–
–
110
12
–
V
mV
–
CAN Normal Mode
8.6.5
8.6.6
8.6.7
CANH, CANL Input
Resistance
Differential Input
Resistance
Wake-up Receiver
Threshold Voltage,
recessive to dominant
edge
Ri
10
20
–
20
40
0.8
30
kΩ
kΩ
V
Recessive state
Rdiff
60
Recessive state
Vdiff, rd_W
1.15
CAN Wake Capable Mode
8.6.8
8.6.9
Wake-up Receiver
Threshold Voltage,
dominant to recessive
edge
Wake-up Receiver
Differential Receiver
Hysteresis
Vdiff, dr_W 0.4
0.7
–
–
V
CAN Wake Capable Mode
CAN Wake Capable Mode
Vdiff,
–
120
mV
hys_W
Data Sheet
36
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
8.6
Electrical Characteristics (cont’d)
4.75 V < VccHSCAN < 5.25 V; VS = 5.5 V to 28 V; RL = 60 Ω; CAN Normal Mode; Tj = -40 °C to +150 °C; all voltages
with respect to ground; positive current flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Typ.
Max.
CAN Bus Transmitter
8.6.10
8.6.11
CANH/CANL Recessive
Output Voltage
VCANL/H 2.0
–
–
3.0
50
V
CAN Normal Mode
no load
CANH, CANL Recessive Vdiff_r_N -500
mV
CAN Normal Mode
V
TxD = Vcc1µC;
Output Voltage Difference
no load
Vdiff = VCANH - VCANL
8.6.12
8.6.13
8.6.14
8.6.15
CANL Dominant Output
Voltage
VCANL
0.5
–
–
–
–
2.25
4.5
3.0
3.0
V
V
V
V
CAN Normal Mode
V
TxD = 0 V;
V
ccHSCAN = 5 V
CANH Dominant Output VCANH
2.75
CAN Normal Mode
V
TxD = 0 V;
ccHSCAN = 5 V
Voltage
V
CANH, CANL Dominant
Output Voltage Difference
Vdiff = VCANH - VCANL
CANH, CANL Dominant
Output Voltage Difference
Vdiff = VCANH - VCANL
Vdiff_d_N 1.5
CAN Normal Mode
V
TxD = 0 V;
ccHSCAN = 5 V
V
Vdiff_d_N 1.5
CAN Normal Mode
V
V
TxD = 0 V;
ccHSCAN = 5 V
RL = 50Ω
8.6.16
8.6.17
8.6.18
CANH Short Circuit
Current
CANL Short Circuit
Current
ICANHsc -200
ICANLsc 50
-80
80
2
-50
200
–
mA
mA
µA
CAN Normal Mode
V
CANHshort = 0 V
CAN Normal Mode
V
CANLshort = 18 V
Leakage Current
ICANH,lk
ICANL,lk
–
VS = VccHSCAN = 0 V;
0 V < VCANH,L< 5 V
SPLIT Termination Output; Pin SPLIT
8.6.20
8.6.21
8.6.22
SPLIT Output Voltage
VSPLIT
0.3 ×
0.5 ×
0.7 ×
V
CAN Normal Mode
VccHSCAN VccHSCAN VccHSCAN
-500 µA < ISPLIT < 500 µA
Leakage Current
ISPLIT
-5
–
0
5
–
µA
Ω
CAN Wake capable Mode;
-27 V < VSPLIT < 40 V
1)
SPLIT Output Resistance RSPLIT
600
–
Receiver Output RxD
8.6.23
HIGH level Output Voltage VRxD,H
0.8 ×
–
–
–
V
V
CAN Normal Mode
I
RxD(CAN) = -2 mA;
VCC1µC
8.6.24
LOW Level Output
Voltage
VRxD,L
–
0.2 ×
Vcc1µC
CAN Normal Mode
RxD(CAN) = 2 mA;
I
Transmission Input TxD
8.6.26
HIGH Level Input Voltage VTD,H
–
–
–
0.7 ×
V
V
CAN Normal Mode
recessive state
CAN Normal Mode
dominant state
Threshold
Vcc1µC
8.6.27
LOW Level Input Voltage VTD,L
0.3 ×
Vcc1µC
–
Threshold
Data Sheet
37
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
8.6
Electrical Characteristics (cont’d)
4.75 V < VccHSCAN < 5.25 V; VS = 5.5 V to 28 V; RL = 60 Ω; CAN Normal Mode; Tj = -40 °C to +150 °C; all voltages
with respect to ground; positive current flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
–
Typ.
0.12 ×
Vcc1µC
Max.
–
1)
8.6.28
8.6.29
TxD Input Hysteresis
VTD,hys
RTD
mV
TxD Pull-up Resistance
20
40
80
kΩ
–
Dynamic CAN-Transceiver Characteristics
8.6.30
Min. Dominant Time for
tWU
0.75
–
3
5
µs
ns
CAN Wake capable Mode
Bus Wake-up
8.6.31
Propagation Delay
TxD-to-RxD LOW
(recessive to dominant)
td(L),TR
150
255
CAN Normal Mode
CL = 47 pF;
RL = 60 Ω;
V
ccHSCAN = 5 V;
C
RxD = 15 pF
8.6.32
Propagation Delay
TxD-to-RxD HIGH
(dominant to recessive)
td(H),TR
–
150
255
ns
CAN Normal Mode
CL = 47 pF;
RL = 60 Ω;
V
ccHSCAN = 5 V;
RxD = 15 pF
C
8.6.33
8.6.34
8.6.35
Propagation Delay
td(L),T
td(H),T
td(L),R
–
–
–
50
120
120
135
ns
ns
ns
CAN Normal Mode
CL = 47 pF;
TxD LOW to bus dominant
RL = 60 Ω;
V
ccHSCAN = 5 V
Propagation Delay
TxD HIGH to bus
recessive
50
CAN Normal Mode
CL = 47 pF;
RL = 60 Ω;
V
ccHSCAN = 5 V
Propagation Delay
bus dominant to RxD LOW
100
CAN Normal Mode
CL = 47 pF;
RL = 60 Ω;
V
ccHSCAN = 5 V;
CRxD = 15 pF
8.6.36
Propagation Delay
bus recessive to RxD
HIGH
td(H),R
–
100
135
ns
CAN Normal Mode
CL = 47 pF;
RL = 60 Ω;
V
ccHSCAN = 5 V;
RxD = 15 pF
C
8.6.37
8.6.38
TxD Permanent Dominant tTxD_TO
0.3
0.6
0.6
1.0
1.0
ms
ms
CAN Normal Mode
Time-out
Bus Dominant Time-out
tBUS_TO 0.3
CAN Normal Mode1)
1) Not subject to production test; specified by design.
Data Sheet
38
Rev. 1.0, 2009-05-26
TLE8261-2E
High Speed CAN Transceiver
VTxD
Vcc1µC
GND
t
t
VDIFF
td(L),T
td(H),T
V diff, rd_N
V diff, dr_N
td(L),R
td(H),R
td(L),TR
t
d(H),TR
VRxD
Vcc1µC
0.8 x V cc1µC
0.2 x V cc1µC
GND
t
CAN dynamic characteristics.vsd
Figure 15 Timing Diagrams for Dynamic Characteristics
Data Sheet
39
Rev. 1.0, 2009-05-26
TLE8261-2E
WK Pin
9
WK Pin
9.1
Block Description
Internal supply
IPU_MON
IWK
State
machine
IPD_MON
Wake.vsd
Figure 16 Functional Block Diagram
The internal voltage regulator (Vcc1µC) and the entire SBC can wake up by changing the wake input voltage. The
WK input pin is a bi-level sensitive input. This means that both transitions, HIGH to LOW and LOW to HIGH, result
in a wake-up. The filtering time is tWK, f.The wake-up capability can be enabled or disabled via SPI command. In
case of reverse polarity, no special protection must be set if the absolute maximum rating is respected. When the
SBC is below the minimum VUVOFF, (SBC OFF Mode) the pin WK is at high impedance; a wake event will be
ignored.
The state of the WK pin (low or high) can always be read in Normal Mode, Stop Mode and SW Flash Mode at the
bit WK State. When setting the bit “WK PIN on/off” to 1, the device wakes up from Sleep Mode with a high to low
or low to high transition. From Fail-Safe Mode the device will always go to Restart Mode with a high to low or low
to high transition. If the bit “WK PIN on/off” is set to 1 in Normal, Stop or SBC SW Flash Mode the interrupt bits
“WK 0 WK pin” and/or “WK 1 WK pin” are set in case of a change on the WK pin and an interrupt is generated if
not masked. With the bits “WK 0 WK pin” and “WK 1 WK pin” the interrupt for low to high transition and high to low
transition can be masked separately.
9.2
Wake-Up Timing
Figure 17 shows typical wake-up timing and parasitic filtering. The filtering time is tWK, f.. This is used to avoid a
parasitic wake-up due to EMC disturbances. Specifically, the voltage transition on pin WK must be higher than the
V
WK,TH and longer than tWK,f to be understood as a wake-up signal.
Data Sheet
40
Rev. 1.0, 2009-05-26
TLE8261-2E
WK Pin
VWK
VWK,th
VWK,th
t
tWK,f
No Wake Event
tWK,f
Wake Event
Wake Pin Diagram .vsd
Figure 17 Wake-up Timing
9.2.1
Transition from Normal to Sleep Mode.
The SBC can not be sent from Normal Mode to Sleep Mode with uncleared interrupt in the WK interrupt bits “WK
0 WK pin” and “WK 1 WK pin”. This is implemented to avoid that a wake information from the WK pin gets lost
during the transition from Normal to Sleep Mode. If a wake up appears during the µC sets the SBC to Sleep Mode,
the SBC will wake up directly after going to Sleep Mode. There is no difference if the bits “WK 0 WK pin” or “WK
1 WK pin” bit were set during the transition or were just not cleared before sending the SPI command for Sleep
Mode, the SBC will wake-up after entering the Sleep Mode. Therefore it always needs to be ensured that the bits
are cleared before sending the SBC to Sleep Mode.
Data Sheet
41
Rev. 1.0, 2009-05-26
TLE8261-2E
WK Pin
9.3
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground; positive current defined flowing into
pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit
Test Condition
Min.
Typ.
Max.
9.3.1
WK Input Threshold
Voltage
VWK,th
2
3
4
V
–
9.3.2
9.3.3
9.3.4
Input Hysteresis
WK Filter Time
Input Current
VI, hys.
tWK, f
IWK
0.1
10
-2
–
–
–
0.7
25
2
V
µs
µA
–
V
WK = 0 V;
WK > 5V
V
9.3.5
9.3.6
WK pin pull up current
WK pin pull down current I PD_MON
I PU_MON -30
–
–
-3
30
µA
µA
V
V
WK = 3.8 V
WK = 2 V
3
Data Sheet
42
Rev. 1.0, 2009-05-26
TLE8261-2E
Supervision Functions
10
Supervision Functions
Reset Function
10.1
10.1.1
Description
The reset output pin RO provides information to the microcontroller, for example, in the event that the output
voltage has fallen below the undervoltage threshold VRT1/2/3. When connecting the SBC to battery voltage, the
reset signal remains LOW initially. When the output voltage Vcc1µC has reached the reset threshold VRT1,r, the reset
output RO remains LOW for the reset delay time trd1. After that the RO is released to HIGH. A reset can also occur
due to faulty Watchdog refresh.See Chapter 10.2. The reset threshold as well as the reset delay time can be
adjusted via SPI. The RO pin has an integrated pull-up resistor.
10.1.2
Reset diagnosis
The RO pin is diagnosed for both short circuit to Vccx and GND. Depending on the configuration, in case of RO
failure, the SBC goes to SBC Fail-Safe or Restart Mode and activate the Limp Home output.
In case of short circuit to GND, it is detected in any SBC mode except SBC Restart Mode. At the falling edge of
the RO, when supposed to be HIGH, the SBC enters automatically the SBC Restart Mode. If after the trd and RO
relaxation, the RO pin is still LOW, then the SBC detects the clamping to LOW failure. The microcontroller is in
permanent reset.
In case of short circuit to Vccx, the SBC cannot detect the short circuit before a reset should occur. So reset
clamped is detected when the SBC goes to SBC Restart Mode or during Init Mode.
10.1.3
Reset Timing
VCC
VRTx
t < tRR
undervoltage
t
tCW
tOW
tRD1
tCW
tLW
tRDx
tLW
tCW
tOW
SPI
RO
SPI
Init
WD
Trigger
WD
Trigger
SPI
Init
t
t
tRR
SBC Init
SBC Normal
SBC Restart
SBC Normal
Res_per_8264.vsd
Figure 18 Reset Timing Diagram
Data Sheet
43
Rev. 1.0, 2009-05-26
TLE8261-2E
Supervision Functions
10.1.4
Reset from Outside
If the reset pin RO is pulled to low from outside while no reset low is issued by the SBC, the device goes to Restart
Mode. In Restart Mode an reset is issued by the SBC, the RO pin is set to low for the time tRD1 or tRD2. If the RO
pin is pulled to low for longer time Reset clamped is detected.
10.2
Watchdog
Two different Watchdogs are possible in the SBC. It can be either a Window Watchdog or a Time-out Watchdog.
The Watchdog can also be inhibited in SBC Stop Mode and SBC SW Flash Mode via SPI. The Watchdog timing
is programmed via SPI command. As soon as the Watchdog is activated, the timer starts running and the
Watchdog must be served. Please refer to Table 8 to match the SBC Modes with the Watchdog Modes.
The default setting for the Watchdog is Time-out Watchdog with a 256 ms timer. The long open window allows the
microcontroller to run its initialization sequences and then to trigger the Watchdog via the SPI.
The Watchdog is served by a SPI bit and should toggle with the correct frequency. The default value is a 0, so the
first trigger bit must be a 1.
In case of a Watchdog reset, the Watchdog immediately starts with a long open window when entering SBC
Normal Mode. With the reset the watchdog bit is set to 0, so the first watchdog trigger after reset is a change to 1.
In SBC Software Development Mode, no reset is generated due to watchdog failure, if a watchdog failure occurs
it is indicated by the SPI Reset bit and via INT pin. All watchdog modes are accessible in regards to the normal
operation modes.
Table 8
SBC Mode
INIT Mode
Watchdog Functionality by SBC Modes
Watchdog Mode
Remarks
Watchdog Programmable;
Watchdog is not active.
INIT Mode should be left in less than 256 ms (see
Chapter 12)
Normal Mode
WD Programmable;
Time-out or Window Watchdog
–
Software Flash Mode
Stop Mode
Mode is fixed
SBC retains the set-up as in the mode before entering
the Software Flash Mode
SBC retains the set up as in the mode before entering
the Stop Mode
Mode is fixed
Sleep Mode
Fail-Safe Mode
Restart Mode
OFF
OFF
OFF
SBC does not retain the set-up.
SBC does not retain the set-up
SBC will start default Watchdog setting (256ms
Time-out Watchdog) when entering Normal Mode.
Data Sheet
44
Rev. 1.0, 2009-05-26
TLE8261-2E
Supervision Functions
10.2.1
Time-out Watchdog
The Time-out Watchdog is an easier and less secure type of watchdog. Compared to the Window Watchdog there
is no closed window existing. The watchdog trigger can be done any time within the watchdog time.
A watchdog trigger is detected as a write access to the “WD Refresh” within the SPI control word. The bit needs
to be toggle (transition HIGH to LOW or LOW to HIGH) within the watchdog window. The trigger is accepted when
the CSN input becomes HIGH.
A correct watchdog trigger starts a new window. The period is selected via the Window Watchdog timing bit field
in the range of 16 ms to 1024 ms. For the safe trigger area the tolerance of the oscillator has to be taken into
consideration, so the safe trigger time is below 90% of the programmed Watchdog time. It is possible to refresh
the Watchdog with any SPI programming with the mode selection Normal, Stop, SW Flash or Read Only.
Should the trigger signal not meet the window, depending on the configuration, the SBC will go to SBC Restart
Mode or to Fail-Safe Mode. A watchdog reset is created by setting the reset output RO low. In config 1 and config
3 the watchdog starts again in Normal Mode with the default watchdog setting (256ms Time-out Watchdog). The
watchdog failure can be read at the bits RM0, RM1, LH0, LH1, LH2 via SPI.
10.2.2
Window Watchdog
A Watchdog trigger is detected as a write access to the “WD Refresh” within the SPI control word. The bit needs
to be toggle (transition HIGH to LOW or LOW to HIGH) in the open window. The trigger is accepted when the CSN
input becomes HIGH.
A correct Watchdog trigger results in starting the Window Watchdog by a closed window with a width of typically
50% of the selected Window Watchdog reset period. This period, selected via the Window Watchdog timing bit
field, is in the range of 16 ms to 1024 ms. This closed window is followed by an open window, with a width of typical
50% of the selected period. From now on, the microcontroller must serve the Watchdog by periodically toggling
the Watchdog bit. This bit toggling access must meet the open window. The tolerance of the oscillator has to be
taken into consideration, so the safe window to trigger the Watchdog is from 55% to 90% of the programmed
Window Watchdog time. It is possible to refresh the Watchdog with any SPI programming with the mode selection
Normal, Stop, SW Flash or Read Only. A correct Watchdog service immediately results in starting the next closed
window (see Figure 19, safe trigger area).
Should the trigger signal not meet the open window, depending on the configuration the SBC will go to SBC
Restart Mode or to Fail-Safe Mode. A watchdog reset is created by setting the reset output RO low (see
Figure 20). In config 1 and config 3 the watchdog starts again in Normal Mode with the default watchdog setting
(256ms Time-out Watchdog). The watchdog failure can be read at the bits RM0, RM1, LH0, LH1, LH2 via SPI.
Data Sheet
45
Rev. 1.0, 2009-05-26
TLE8261-2E
Supervision Functions
Window Watchdog Timing (SPI)
tWD
tCWmax
tOWmax
tCWmin
tOWmin
Un-
closed window
open window
uncertainty
certainty
t / [tWDPER
]
safe trigger area
0.45
0.55
0.9
1.0
1.1
Wd1_per .vsd
Figure 19 Window Watchdog Definitions
tCW
tOW
tLW
tCW
tCW
tOW
tCW
tOW
tLW
tCW
tOW
tCW+tOW
tLW
WD
Refresh
bit
tWDR
t
t
RO
Watchdog
timer reset
normal
Time-out
(too long)
normal
operation
timeout
normal
operation
(too short)
operation
Wd2_per.vsd
Figure 20 Window Watchdog Timing Diagram for config 1 and config 3
10.2.3
Changing the Watchdog Settings
The settings of the watchdog can be changed during the operation of the watchdog. The change is done with a
SPI programming into the Watchdog Configuration Register. The new setting is programmed together with a valid
watchdog trigger according to the old settings. The timer with the new settings starts with this SPI command. The
toggling of the “WD Refresh” bit needs to be continued (transition HIGH to LOW or LOW to HIGH) with the new
settings.
If the new settings were not valid, the watchdog will continue with the old settings and generate a “Wrong WD Set”
interrupt.
Data Sheet
46
Rev. 1.0, 2009-05-26
TLE8261-2E
Supervision Functions
10.2.4
Inhibition of the watchdog
During SBC Stop Mode and SBC SW Flash Mode, it is possible to deactivate the watchdog. To avoid unwished
deactivation of the watchdog, a special protocol has to be followed, prior deactivating the watchdog. Please refer
to Figure 21. In the case the exact process below is not respected, the SBC remains in the previous state, and an
interrupt is generated (if not inhibited), and the Wrong WD set bit in the SPI is set.
When the microcontroller requests the SBC to go back to SBC Normal Mode, the Watchdog is reactivated. The
watchdog settings that were valid before entering Stop Mode with watchdog off are valid. The watchdog timer
starts with entering Normal Mode. In case window watchdog was selected the watchdog starts with a closed
window. When setting the WD Refresh bit to 0 for the command that sends the device to Normal Mode the first
watchdog trigger is a change to 1. As in Stop Mode the watchdog settings can not be changed, it is also not
possible to change the watchdog settings with the command that sets the SBC from Stop Mode into Normal Mode.
First battery connection
(POR)
AND
config0 not active
SBC Init mode
(256ms max after reset relaxation)
WD conf
WD not active
SPI cmd
WD trig
SBC Normal mode
WD conf
Cyclic WK
ON / OFF
WD active
SPI cmd =
SBC SW Flash mode
&,WD OFF
SPI cmd =
SBC Normal mode
& WD OFF
& WD Trigger
SBC Normal mode
WD active
SPI cmd =
SBC SW Flash mode
&,WD OFF
& WD Trigger
SPI cmd =
SBC Stop mode
& WD OFF
& WD Trigger
SBC Stop mode
SBC SW Flash mode
WD OFF
Cyclic WK
ON / OFF
WD OFF
inhibition of the WD .vsd
Figure 21 Inhibition of the watchdog
During SBC Stop Mode, when the cyclic wake feature is used and the watchdog is not disabled, it is necessary
that the microcontroller acknowledges the interrupt by reading the SPI Wake register before the next Cyclic Wake
occures. Otherwise, a reset is performed by setting the SBC to SBC Restart Mode.
Data Sheet
47
Rev. 1.0, 2009-05-26
TLE8261-2E
Supervision Functions
10.3
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol Limit Values
Unit
Test Condition
Min.
Typ.
Max.
Reset Generator; Pin RO
10.3.1
Reset Threshold Voltage, VRT1,f
4.5
4.6
3.5
3.6
3.2
4.65
4.75
3.65
3.75
3.35
4.75
4.85
3,75
3,85
3.45
V
V
V
V
V
default setting, Vcc falling
default setting, Vcc rising
SPI option;Vcc falling
SPI option; Vcc rising
VRT1,r
VRT2,f
VRT2,r
VRT3,f
SPI option;VS ≥ 4 V; Vcc
falling
VRT3,r
3.3
3.45
3.55
V
SPI option; VS ≥ 4 V, Vcc
rising
default setting1)
SPI option;1)
SPI option; VS ≥ 4 V 1)
-
Reset Threshold Voltage VRT1_HR 250
–
–
–
100
–
–
–
200
mV
V
V
Headroom
VRT2_HR 1.25
VRT3_HR 1.55
10.3.2
10.3.3
Reset Threshold
Hysteresis
VRT,hys
20
mV
Reset Low Output Voltage VRO
–
0.2
0.4
V
V
I
RO = 1 mA for
CC1µC = VRT1/2/3
RO = 200 µA for
RT1/2/3> VCC1µC ≥ 1 V
IRO = -20µA
V
;
I
V
10.3.4
Reset High Output
Voltage
VRO
0.7 x
VCC1µC
–
VCC1µC
+ 0.3 V
10.3.5
10.3.6
Reset Pull-up Resistor
Reset Reaction Time
RRO
tRR
10
4
20
10
40
26
kΩ
µs
V
V
RO = 0 V
CC1µC < VRT1/2
to RO = L
10.3.7
Reset Delay Time
tRD1
tRD2
4.5
5.0
5.5
ms
µs
default SPI setting;
after Power-On-Reset
450
500
550
SPI setting option
2)default setting
–
Watchdog Generator
10.3.8
Internal Oscillator
10.3.9
Long Open Window
tLW
–
256
0
–
ms
%
Internal Oscillator
tolerance
fCLKSBC -10
10
1) Headroom between actual output voltage on VCC1µC and Reset Threshold Voltage for falling Vcc.
2) Specified by design; not subject to production test. Tolerance defined by internal oscillator tolerance fCLKSBC
.
Data Sheet
48
Rev. 1.0, 2009-05-26
TLE8261-2E
Interrupt Function
11
Interrupt Function
11.1
Interrupt Description
The interrupt pin has a general purpose function to point out to the microcontroller either a wake up, a failure
condition or the switch on of a voltage regulator. Table 9 shows the possible interrupt sources in the device, and
Figure 22 gives the hardware set-up. The interrupt function is designed to inform the microcontroller of any wake-
up event, overtemperature or overtemperature pre-warning as well as other failures. These events turn the INT
pin to active LOW. All interrupt sources can be masked via a SPI bit, then no interrupt is generated for this event.
For failures on under-voltage the interrupt is dual-sensitive. This means that an interrupt is generated when the
failure appears, as well as when the failure disappears. For failures on over-temperature, communication failures
and voltage regulator over current and undervoltage, the dedicated SPI interrupt bit indicated first the interrupt
source and then the state of the device. So, the bit is set to failure 1 at the event, and remains latched at least until
the microcontroller reads the bit. For the SBC failure (Wrong WD Setting, Reset, Fail SPI) and wake events, the
INT indicates only an event and the bit is cleared with a dedicated SPI read.
The INT pin is released when an SPI read is done to Interrupt Register 000 with a “Read Only” command, or after
interrupt time out tINTTO. If the interrupt cause was a wake event, the interrupt bit can be read in Interrupt Register
000 and the bit is cleared. If it was an other interrupt source the bit INT is set, and interrupt register 001 and 010
need to be read. With a “Read Only“command the event triggered interrupt bits are cleared. The INT bit will be set
to “0” when all bits in interrupt register 001 and 010 are set to “0”. If an interrupt is masked (bit set to “0”) only the
interrupt does not occur, the interrupt bit in the SPI is shown.
Figure 22 shows a simplified diagram of the INT output. In Init Mode before RO goes high the INT pin is used to
set the configuration of the device to config 1/3 or config 2/4, see Chapter 13.
Vcc1µC
R
IN T
INT
Time
Interrupt logic
out
INTERRUPT BLOCK.VSD
Figure 22 Interrupt Block Diagram
Table 9
Interrupt sources
Interrupt sources
INT Activation
SPI bit
State
Temperature
Over temperature pre-warning VCC1µC
Over temperature VCC2
Over temperature HS CAN
Communication failure
CAN Failure
Rising
Rising
Rising
OTP VCC1µC
OT VCC2
OT HSCAN
Event /
State
Rising
CAN Failure 1..0
CAN Bus
Event/
State
Voltage regulator
Data Sheet
49
Rev. 1.0, 2009-05-26
TLE8261-2E
Interrupt Function
Table 9
Interrupt sources
Interrupt sources
INT Activation
SPI bit
State
Undervoltage at VCC2 (except during switch off1))
Undervoltage at VCC3(except during switch off1))
Over current at VCC3 (except during inhibition)
Voltage at VCC2 (during switch on1))
Voltage at VCC3 (during switch on1))
SBC Failure
Rising and falling UV_VCC2
Rising and falling UV_VCC3
Event /
State
Rising
Rising
Rising
ICC3 > ICC3MAX
UV_VCC2
UV_VCC3
Event
SPI data corrupted
Rising
Rising
Rising
SPI Fail
Reset
Wrong WD set
Reset (SBC SW Development only)
Wrong watchdog setting
Wake
Event
Wake at CAN
Wake at WK
Cyclic WK
Rising
Rising
Rising
WK CAN
WK WK pin 1..0
Cyclic WK
Event
1) When VCC2/3 is switched off no interrupt is generated due to the undervoltage at VCC2/3. When switching on VCC2/3 an
interrupt is generated when the command is sent to the SBC via SPI.
11.1.1
Interrupt for switching on Vcc2 and Vcc3
The Interrupt for Vcc2 and Vcc3 are generated when the SPI command for switching on the voltage regulator is
executed. The interrupt bit is set to “1“ and can be cleared with a Read Only command after the under voltage
threshold is reached. If the Read Only is done before the reset threshold is reached, the interrupt bit can not be
cleared as the undervoltage condition is still present. In this case a second interrupt can be issued for releasing
the undervoltage condition.
In case of a short to GND on Vcc2 or Vcc3 the interrupt for switching on the voltage regulator is issued, but the
µC can not clear the interrupt bit as the voltage regulator does not reach the undervoltage threshold.
11.1.2
Example of Interrupt Events and Read-out
The examples show single interrupt events. SPI read is done with “Read Only”. The shown interrupts are not
masked. Watchdog trigger is not shown in the examples.
The interrupt UV_Vcc2 that is generated by switching on VCC2 is shown in Figure 23. The interrupt is sensitive on
rising event only.
Data Sheet
50
Rev. 1.0, 2009-05-26
TLE8261-2E
Interrupt Function
Rising event(Vcc2 above limit) is shown
Vcc2 switched off
by SPI
Vcc2 switched on
by SPI
Vcc2
INT pin
SPI DI programming
Read Only
optional
required
optional
Mode Select Bits 111
Conf. Select 000
Conf. Select 001
Conf. Select 002
INT bit
0
X
X
0
1
X
X
1
X
X
X
0
0
X
UV_VCC2
Interrupt_SwitchOn_VCC2.vsd
Figure 23 Interrupt Vcc2 switch-on.
Data Sheet
51
Rev. 1.0, 2009-05-26
TLE8261-2E
Interrupt Function
The interrupt UV_Vcc2 that is generated by an under-voltage on VCC2 is shown in Figure 24. The interrupt is
sensitive on rising and falling event and the interrupt bit also shows the state of the device and function.
Undervoltage
on Vcc2
Falling event(Vcc2 below limit), rising event(Vcc2
above Limit) as well as state is shown
Vcc2
INT pin
SPI DI programming
Read Only
required
optional
required
optional
Mode Select Bits 111
Conf. Select 000
Conf. Select 001
Conf. Select 002
INT bit
1
X
X
1
X
X
X
1
1
X
1
X
X
1
X
X
X
0
0
X
UV_VCC2
Interrupt_UV_VCC2.vsd
Figure 24 Interrupt VCC2 under-voltage.
The interrupt OT_Vcc2 that is generated by an over temperature on VCC2 is shown in Figure 25. The interrupt is
sensitive on rising event and the interrupt bit also shows the state of the device and function.
Overtemperature
on Vcc2
Rising event(apperance of overtemperature) is
shown, as well as the state.
OT_VCC2
INT pin
SPI DI programming
Read Only
required
optional
Mode Select Bits 111
Conf. Select 000
Conf. Select 001
Conf. Select 002
INT bit
1
X
X
1
X
X
X
1
1
X
X
0
0
X
OT_VCC2
Interrupt_OT_VCC2.vsd
Figure 25 Interrupt Vcc2 Over Temperature.
Data Sheet
52
Rev. 1.0, 2009-05-26
TLE8261-2E
Interrupt Function
11.2
Interrupt Timing
Figure 26 illustrates the interrupt timing. The INT output is set LOW as soon as an interrupt condition occurs. The
INT pin is released after a SPI interrupt buffer read out command, that is performed with a Read Only command
(111) to register (000). In case consecutive interrupt sources are indicated before the SPI read out, only one INT
LOW will be raised but the SPI read out will indicate the interrupt sources. A time-out feature is implemented. The
INT pin can be active LOW only for the time tINTTO. Afterwards, the INT pin is released but the INT source is still
valid or present in the SPI register. Between two activations of the INT, there is at least a delay of tINTTO. If an
interrupt occurs in the meantime, the information is stored and the INT will go LOW after tINTO. The INT pulse width
is at minimum tINT
.
interrupt source 1
active
inactive
t
interrupt source 2
active
inactive
t
INT output
t
INT
tINTTO
tINT TO
tINTTO
t
tINTTO
interupt timing.vsd
SPI read out
SPI read out
SPI read out
SPI read out
Figure 26 Interrupt Timing
11.3
Interrupt Modes with SBC Modes
The interrupt function is possible only in SBC Normal and Stop Mode.
After an SBC Restart Mode, all interrupt sources are enabled.
11.4
Interrupt Application Information
By default, all interrupt sources are activated. Please refer to the dedicated chapter for the definition of the
interrupt.
The INT output is active for at least tINT, even if the corresponding interrupt register is read out immediately after
the interrupt event occurs.
If no SPI read is done after the interrupt is generated (INT pin low) the INT output becomes active (INT pin high)
again after tINTTO
.
If two interrupt cases occur after each other and the SPI read (with read-only) is done after the second interrupt
case, both interrupt bits are cleared. Although the interrupt bits for both interrupt cases are cleared the second
interrupt will be issued by INT pin Low. This can lead to an interrupt where all interrupt bits are read as “0”.
Data Sheet
53
Rev. 1.0, 2009-05-26
TLE8261-2E
Interrupt Function
11.5
Electrical Characteristics
.
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin unless otherwise specified.
Pos.
Parameter
Symbol Limit Values
Unit
Test Condition
Min.
Typ.
Max.
Interrupt output; Pin INT
11.5.1
11.5.2
11.5.3
11.5.4
Interrupt delay Time-out
INT pulse width
INT Low Output Voltage VINTOL
INT High Output Voltage VINTOH
tINTTO
tINT
5.4
10
–
0.7 x
VCC1µC
6
–
0.2
–
6.6
–
0.4
ms
µs
V
−
1)
I
I
INT = 1 mA
INT = -20µA
VCC1µC
V
+ 0.3 V
11.5.5
INT Pull-up Resistor
RINT
10
20
40
kΩ
V
INT = 0 V
Configuration select; Pin INT
11.5.6
11.5.7
11.5.8
INT Config LOW input
VCFGLO 0.3 x
–
–
V
–
–
–
voltage
Vcc1µC
INT Config HIGH input
voltage
INT Config pull down
VCFGHI
RCFG
–
–
0.7 x
Vcc1µC
–
V
–
250
kΩ
1) Not subject to production test, specified by design.
Data Sheet
54
Rev. 1.0, 2009-05-26
TLE8261-2E
Limp Home
12
Limp Home
12.1
Description
The Limp Home outputs are a very useful way to control safety critical functions independent of the microcontroller,
such as turning on or off critical load during a microcontroller failure.
12.2
Limp Home output
The Limp Home output is an active LOW open drain transistor, please refer to Figure 27; therefore, it is necessary
to connect at least an external pull-up resistor at.
The Limp Home output is activated due to a failure condition or via SPI, see Chapter 12.3. If Vs is below VLHUV
,
the Limp Home cannot be activated and remains as a high impedance.
Limp home
Limp home logic
LIMP HOME.VSD
Figure 27 Limp Home block diagram
12.2.1
Limp Home side indicators output
The LH_SI output is similar to the Limp Home output. The output is pulsed to fLHSI frequency with dSI and designed
to provide the side indicators frequency. The LH_SI function is active when the Limp Home is active.
Limp home
LH_SI
Limp home logic
LIMP HOME_LHSI.VSD
Figure 28 Limp Home LH_SI block diagram
12.2.2
LH_PL (Pulsed Light) output
The LH_PL/Test pin is an output pin shared with the Test pin function. During SBC Init Mode, the pin is used as
an input, in all other modes, the pin is an output.
The output is pulsed to fLHPL frequency with a duty cycle of dPL (20% LOW, 80% high impedance), designed to dim
the 27W stop lights into an 5W rear light. Refer to Figure 29. The LH_PL function is activated when the Limp Home
is active. In SBC Init Mode, the LH_PL is inhibited, to avoid a wrong set of the SBC into SBC Software development
Mode.
Data Sheet
55
Rev. 1.0, 2009-05-26
TLE8261-2E
Limp Home
T test
VS
SBC Init
mode
RLH_ PL
LH_PL / test
T LH_PL
Limp home
LH_PL_test.vsd
Figure 29 LH_PL/ Test block diagram
12.2.3
Test Pin
The Test pin is used to set the SBC chip into SBC Software Development Mode. When the Test pin is connected
to GND, the SBC starts in SBC Software Development Mode. When the pin is left open, or connected to Vs the
SBC starts into normal operation. Please refer to Figure 3. The Test pin has an integrated pull-up resistor
(switched ON only during SBC Init Mode) to prevent the SBC device from starting in SBC Software Development
Mode during normal life of the vehicle, as for example when the battery has been disconnected. To avoid
disturbance, the Test pin is monitored during the Init Mode (from the time VS > VUVON until Init Mode is left). If the
pin is low for the Init Mode time, Software Development Mode is reached. The mode is stored during the complete
time where VS is above VUVOFF. It means to leave Software Development Mode, the SBC must go back to SBC
OFF mode.
Data Sheet
56
Rev. 1.0, 2009-05-26
TLE8261-2E
Limp Home
12.3
Activation of the Limp Home Output
The reason to activate the Limp Home pins and the consequences are listed in Table 10 and Table 11.
Table 10
Limp Home, Function of the SBC Mode
SBC Mode
INIT Mode
Limp Home Outputs
OFF
Normal Mode
OFF
ON via SPI
ON if it was ON until the successful Watchdog
setting and deactivation via SPI.
Stop Mode
Sleep Mode
Restart Mode
Fail-Safe Mode
SW Flash Mode
Unchanged
Unchanged
Unchanged
ON
Unchanged
Table 11
Automatic Activation of Limp Home Output
Reason
SBC Mode
INIT Mode
Normal Mode
INIT time-out (tINITTO
)
1st Watchdog failure (config 1/2)
2nd Watchdog failure (config 3/4)
Restart Mode
Reset output permanent short circuit to Vcc1µC
Reset output permanent short circuit to GND
V
cc1µC undervoltage time-out
If previously turned ON in SBC Normal Mode, via SPI command
cc1µC thermal shutdown
Any mode
V
12.4
Release of the Limp Home Output
When Limp Home is activated via SPI command, then it is released via SPI command. This is useful for diagnosis
purpose for example.
Otherwise, the Limp Home outputs are released only in SBC Normal Mode with the following conditions: After the
device has been set to SBC Restart Mode, automatically entering SBC Normal Mode, a successful Watchdog
trigger must be sent via SPI. At this point, the Limp Home outputs remain active. Then the microcontroller needs
to send by SPI command the deactivation of the Limp Home.
12.5
Vcc1µC undervoltage time-out
A Vcc1µC undervoltage time-out condition is given, when
1) the Vcc1µC output voltage is below the reset threshold (VRT1, VRT2, VRT3),
2) VS is higher then the threshold (VSthUV1, VSthUV2, VSthUV3) and
3) the condition is valid longer then the Vcc1µC under voltage time-out (tVcc1UVTO).
A Vcc1µC undervoltage time-out will sent the device into Fail-Safe Mode. Limp Home output stag will be activated
(for Vs > VLHUV
)
Figure 30 gives an example of the Limp Home output activation, due to a Vcc1µC undervoltage time-out.
Data Sheet
57
Rev. 1.0, 2009-05-26
TLE8261-2E
Limp Home
Vs
VSthUVx
Vcc1µC
t
t
VRTx
VRTx
GND
RO
tVcc1UVTO
SBC Sleep
SBC Restart
SBC Normal
SBC Restart
SBC Fail safe
t
tRR
tRDx
Wake Up
Limp home
GND
t
undervoltage time out.vsd
Figure 30
Vcc1µC undervoltage time-out timing
Data Sheet
58
Rev. 1.0, 2009-05-26
TLE8261-2E
Limp Home
12.6
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin unless otherwise specified.
Pos.
Parameter
Symbol Limit Values
Unit
Test Condition
Min.
Typ.
Max.
Limp Home;
12.6.1
Watchdog edge count
nLH
–
1
–
–
With SPI set.
difference to set Limp
Home activated
2
0.2
Default Setting
ILH = 1mA
12.6.2
12.6.3
Limp Home low output
voltage (active)
Limp Home high output
current (inactive)
INIT Time-out
Vcc1µC under voltage
Time-out
VLHLO
ILHHI
–
0
–
0.4
2
V
–
µA
VLH = 28V
1)
12.6.4
12.6.5
tINITTO
tVcc1UVTO 900
256
1024
–
ms
ms
1150
12.6.6
Vs threshold for Vcc1µC
under voltage Time-out
(Vs needs to be above, to
activate Vcc1µC under
voltage Time-out)
VSthUV1 5.3
–
6.3
V
V
RT1 default setting
VSthUV2 4.3
VSthUV3 4.0
–
–
5.3
5.0
V
V
V
V
RT2 SPI option
RT3 SPI option
12.6.7
12.6.8
Threshold for Limp Home VLHUV
4.5
–
–
5.5
–
V
V
–
–
minimum Vs
Limp Home Vs voltage
VLHUVhys
0.2
hysteresis
LH _SI;
12.6.9
Limp Home side indicator fLHSI
1.125
–
1.25
50
1,375
–
Hz
%
–
–
frequency
12.6.10 Limp Home side indicator
duty cycle
dSI
LH_PL/Test
12.6.11 HIGH Level Input Voltage VTest,HI
–
–
3
V
–
Threshold
12.6.12 Input Hysteresis
VTest,hys 100
300
–
700
–
mV
V
–
–
12.6.13 LOW Level Input Voltage VTest,LO
1
Threshold
12.6.14 Pull-up Resistor
RTest
fLH_PL
dPL
20
90
-
40
80
110
-
kΩ
Hz
%
V
LH_PL/Test = 0V
SBC Init Mode
–
12.6.15 Limp Home pulsed light
frequency
100
20
12.6.16 Limp Home pulsed light
–
duty cycle
1) Not subject to production test, specified by design.
Data Sheet
59
Rev. 1.0, 2009-05-26
TLE8261-2E
Configuration Select
13
Configuration Select
13.1
Configuration select
The Configuration select is used to set the device for two different SBC behaviors; please refer to Chapter 4.2.1
for detailed information. Depending on the requirements of the application, the Vcc1µC is switched off and the device
goes to Fail-Safe Mode in case of watchdog fail (1 or 2 fail) or reset clamped. To turn Vcc1µC OFF (Config 2/4), the
INT pin is not connected to a pull up resistor externally. In case the Vcc1µC is not switched off (Config 1/3) the INT
pin is connected to Vcc1µC with a pull up resistor. The configuration is only read during Init Mode, after that the
configuration is stored.
13.2
Config Hardware Descriptions
In Init Mode before the RO pin goes high the INT pin is pulled to low with a weak pull down resistor RCFG, the pull
up resistor RINT is switched off. When Vcc1µC is high, above the reset threshold VRT1 and before the RO pin goes
high the level on the INT pin is monitored to select the configuration. With RO going high in Init Mode the pull up
resistor RINT is switched on.
Figure 31 gives the electrical equivalents to the configuration function of the INT pin.
Vcc1µC
Configuration logic
RINT
INT
Time
Interrupt logic
out
RCFG
INTERRUPT BLOCK_CONFIG.VSD
Figure 31 Config Logic Diagram
Electrical characteristics are listed in chapter Chapter 11.5
Data Sheet
60
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14
Serial Peripheral Interface
14.1
SPI Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK
supplied by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 32).
The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After
the CSN input returns from LOW to HIGH, the word that has been read in becomes the new control word. The
SDO output switches to tri-state status (high impedance) at this point, thereby releasing the SDO bus for other use.
The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted out of
the output register after every rising edge on CLK. The number of received input clocks is supervised by a
modulo-16 operation and the Input / Control Word is discarded in case of a mismatch. This error is flagged in the
following SPI output by a “HIGH” at the data output (SDO pin, bit FO) before the first rising edge of the clock is
received. The SPI of the SBC is not daisy chain capable.
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
CLK
time
Actual data
New data
0 1
FI
-
SDI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FI
+ +
time
SDI: will accept data on the falling edge of CLK signal
Actual status
New status
0
+
1
+
FO
-
SDO
FO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
time
SDO: will change state on the rising edge of CLK signal
Figure 32 SPI Data Transfer Timing
14.2
Corrupted data in the SPI data input
When the microcontroller send a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI
command can be either a number of bits different of 16, the mode selection (MS2..0) = 000 or requesting to go to
an SBC mode which is not allowed by the state machine, for example from SBC Stop Mode to SBC SW Flash
Mode. In that case, an interrupt is generated (if not inhibited) and the bit SPI Fail is set. Since the SPI data is
corrupted, the next SPI output data will remain the former one (the information is then repeated).
Data Sheet
61
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.3
SPI Input Data
MSB
LSB
Input
Data
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WD
CS2
CS1
CS0
MS2
MS1 MS0
refresh
Mode Selection
Bits
Configuration Select
000
Configuration Registers
WK 1 WK 0
WK
000
001
Res. Res. Res.
Res. Res. Res.
not valid
Restart
SW Flash
Normal
Sleep
WK pin WK pin
CAN
001
010
011
Wrong
WD set
Fail
ICC3
>
UV
UV
OT
OT
OTP
Reset
SPI ICC3max Vcc3
VCC2 VCC2
Vcc1µC
HS CAN
INTERRUPT
MASK
CAN CAN
CAN
Bus
010
011
Res. Res. Res. Res. Res. Res.
failure failure
1
0
Reserved
Cyclic
100
101
110
111
100
101
110
111
WK PIN
On/off
WD to
LH
L.H.
VCC2
VCC3 Reset
On/off Delay
WK
RT1
RT0
On/off On/Off
On/off
CAN CAN
Stop
Res.
CHK
Res. Res.
Res. Res. Res. Res.
1
0
REGISTER
Ti.
Window/Time out Watchdog
Timing Bit Position: 10 .. 6
WD
Set to
1
Fail safe
Read Only
Out /
Win.
SUM On/Off
Reserved
SPI data input TLE8261.vsd
Figure 33 16-Bit SPI Input Data / Control Word
Data Sheet
62
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.4
SPI Output Data
MSB
LSB
Output
Data
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CS2
CS1
CS0
MS2
MS1 MS0
WK
Mode Selection
Bits
Configuration Select
000
Configuration Registers
state
Cyclic WK 1 WK 0
WK
000
001
INT
Res.
Res. Res. Res.
Init
WK WK pin WK pin
CAN
001
010
011
Wrong
WD set
Fail ICC3
>
UV
UV
OT
OT
OTP
Reset
Status or
Restart
SW Flash
Normal
Sleep
SPI ICC3max Vcc3
VCC2
VCC2
Vcc1µC
HS CAN
INTERRUPT
event
CAN CAN
CAN
Bus
010
011
Res. Res. Res. Res. Res. Res.
failure failure
1
0
Reserved
Cyclic
100
101
110
111
100
101
110
111
WK PIN
On/off
WD to
LH
L.H.
VCC2
VCC3 Reset
On/off Delay
WK
RT1
RT0
On/off On/Off
On/off
CAN CAN
Stop
Res.
CHK
Res. Res.
Res. Res. Res. Res.
1
0
REGISTER
Ti.
Window/Time out Watchdog
Timing Bit Position: 10 .. 6
WD
Set to
1
Fail Safe
Reserved
Out /
Win.
SUM On/Off
Res. RM1 RM0 LH 2 LH 1 LH 0 Test 2 Test 1 Test 0
SPI_Settings_out_TLE8261.vsd
14.5
SPI Data Encoding
14.5.1
WD Refresh bit / WK state
The WD Refresh bit is used to trigger the Watchdog. The first trigger should be a 1, and then a 0. For more details,
please refer to Chapter 10.2.
The WK state bit gives the voltage level at the WK pin. A 1 indicates a high level, a 0 a low level.
Data Sheet
63
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.5.2
SBC Configuration Setting and Read Out
14.5.2.1 Mode selection bits and configuration select
Table 12 lists the encoding of the possible SBC mode. Except SBC Restart and Init Mode which are most of time
entered automatically, all others SBC mode are accessible on request of the microcontroller. The microcontroller
should send the correct mode selection bits to set the SBC in the respective mode. The output indicates the SBC
mode where the SBC currently is or was, depending on the situation.
Table 12
Mode Selection Bits
MS2 MS1 MS0 Data Input
Data Output
Not valid (the complete SPI word is ignored) Show the device was in Init previous SPI data
0
0
0
0
0
1
Set the SBC to SBC Restart Mode.
(In SW Flash mode only)
Show the device was in Restart previous SPI
data
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
Set the SBC to Software Flash Mode
Set the SBC to SBC Normal Mode
Set the SBC to SBC Sleep Mode
Set the SBC to SBC Stop Mode
Set the SBC to SBC Fail-Safe Mode
(In SBC Software Development mode only)
Show the device is SBC Software Flash Mode
Show the device is in SBC Normal Mode
Show the device was in SBC Sleep Mode
Show the device is in SBC Stop Mode
Show the device was in SBC Fail-Safe Mode
1
1
1
Set the SBC to Read Only SPI access. The Reserved
configuration register needs to be selected.
The SPI information on SDO is provided in
the same SPI frame. No write access is
done in this mode.
Bit 15 (Watchdog) has to be served
correctly.
Table 13 lists the eight possible configuration selection. Some are related to event or state of the different part of
the SBC, others are used to configure the SBC in the application specific set up.
Table 13
Configuration Select Encoder (for Data Input and Output)
CS2
0
0
0
0
1
1
1
1
CS1 CS0 Configuration Register Select
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Wake Register Interrupt
SBC Failure Interrupt
Communication Failure Interrupt
Reserved
SBC Configuration Register
Communication Setup Register
Watchdog Configuration Register
Limp Home / Diagnosis Register
Data Sheet
64
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.5.2.2 Interrupt Register Encoder
Table 14 lists all interrupts the SBC can generates. The microcontroller should read the correct register to release
the INT pin. By default, all interrupt sources are enabled. The microcontroller can decide to inhibit a specific
interrupt source.
Table 14
CS Bit Name
Interrupt Register encoder 1)
Default Default Data Input
Value Value
(OUT)
Data Output
(INPUT)
Configuration select 000 (Wake register interrupt)
000 WK CAN
1
0
Interrupt enabled (1) disabled Wake on CAN (1)
(0) for wake event on CAN
WK 1 WK pin
WK 0 WK pin
11
00
Interrupt enabled (1) disabled Wake on WK pin
(0) for wake pin event.
00 No interrupt
00 No wake
10 Interrupt for a LOW to HIGH
10 Interrupt for a LOW to HIGH transition on WK
transition on WK
01 Interrupt for HIGH to LOW
01 Interrupt for HIGH to LOW
transition on WK
transition on WK
11 Interrupt for both HIGH to
LOW and LOW to HIGH on WK
11 Interrupt for both HIGH to
LOW and LOW to HIGH on WK
Cyclic WK
INT
n.a
n.a
0
0
n.a
n.a
Cyclic WK (1)
Indicates that there is a status
bit or uncleared event in
configuration select 001 and/or
010. If set read the two register
Data Sheet
65
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
Table 14
CS
Interrupt Register encoder (cont’d)1)
Bit Name
Default Default Data Input
Data Output
Value
Value
(OUT)
(INPUT)
Configuration select 001 (SBC Failure interrupt)
001 OTP_Vcc1µC
OT_HSCAN
OT_Vcc2
1
1
1
1
0
0
0
0
Interrupt enabled (1) disabled Vcc1µC temperature pre warning
(0) for temperature pre-warning (1)
Interrupt enabled (1) disabled HS CAN temperature shutdown
(0) for temperature shutdown
(1)
Interrupt enabled (1) disabled Vcc2 temperature shutdown (1)
(0) for temperature shutdown
Interrupt enabled (1) disabled Undervoltage detection on Vcc3
(0) for undervoltage detection (1)
or due to back to normal voltage
UV_Vcc3
SPI Fail
Reset
1
1
0
0
Interrupt enabled (1) disabled SPI input corrupted data (1)
(0) for SPI corrupted data.
Interrupt enabled (1) disabled Reset (1)
(0) for reset information
(only in SBC Software
Development Mode)
(only in SBC Software
Development Mode)
Wrong WD set
1
1
1
0
0
0
Interrupt enabled (1) disabled Incorrect WD programming for
(0) for incorrect Watchdog
setting
data output
UV Vcc2
Interrupt enabled (1) disabled Under voltage detected at Vcc2
(0) for undervoltage detection at
Vcc2
I
CC3 > ICC3max
Interrupt enable (1) disabled (0) Over current detected at Vcc3
for over current at Vcc3
Configuration select 010 (Communication failure interrupt)
010 CAN failure 1
n.a
1
0
0
Interrupt enabled (1) disabled CAN failure Refer to Table 15
(0) for CAN failure
CAN failure 0
CAN Bus
1
0
Interrupt enabled (1) disabled CAN bus failure detected (1)
(0) for CAN bus failure
1) A value of 0 will set the SBC into the opposite state.
Data Sheet
66
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.5.2.3 CAN failure encoder
Table 15 describes the encoding of the possible internal CAN failures.
Table 15
CAN Failure Encoder
CAN 1 Failure
CAN 0 Failure
Fault
0
0
1
1
0
1
0
1
No failure
TxD shorted to GND or bus dominant clamped
RxD shorted to Vcc
TxD shorted to RxD
14.5.2.4 Configuration encoder
Table 16 lists the configuration register of the SBC. The microcontroller can change the settings. If no settings are
changed the default values are used. The current value can be read on the SPI Data Out.
Table 16
Configuration Encoder
Configuration Bit Name
Select
Default Default State
Value Value
(INPUT) (OUT)
Configuration select 100 (SBC Configuration Register)
100
RT10
01
01
Reset threshold setting. Please refer to Table 17
Reset delay
1
1
Long reset window
V
cc3 ON /OFF
0
0
1
0
0
V
cc3 is activated (1)
The wake pin will wake the SBC
cc2 is activated (1)
WK pin ON / OFF 1
V
LH ON / OFF
cc2 On / Off
0
0
V
Limp Home output state. Activated (1) when entry
condition is met.
Cyclic WK On /
Off
0
1
0
1
Activation (1) of the cyclic wake
WD to LH
Watchdog failure to Limp Home active.
0 = only one Watchdog failure brings to Limp Home
activated.
1 = two consecutive Watchdog failures bring to Limp
Home activated.
Data Sheet
67
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
Table 16
Configuration Encoder
Configuration Bit Name
Select
Default Default State
Value Value
(INPUT) (OUT)
Configuration select 101 (SBC communication set up register)
CAN 1.0
00
00
The CAN cell is in:
00 = CAN OFF
01 = CAN is Wake Capable
10 = CAN Receive Only Mode
11 = CAN Normal Mode
Configuration select 110 (SBC Watchdog register)
110
Ti. Out / Win.
Set to 1
WD ON / OFF
CHK SUM
1
1
1
1
1
1
1
1
Time-out Watchdog is activated
Bit is reserved and fix set to “1”. Set to 1 in SW.
Watchdog is activated
Check sum of the bit 13...6
In case the CHK SUM is wrong, the device remains in
previous valid state.
CHKSUM = Bit13 ⊕ … ⊕ Bit6
Configuration select 111 (Limp Home / Diagnosis register)
111
-
Reserved for input
For output, refer to Table 19, Table 20 and Table 21
14.5.2.5 Reset encoder
Table 17 lists the three possible reset thresholds. Please also refer to Chapter 10.3 to get the exact voltage
threshold.
Table 17
Reset Encoder
RT1
RT0
Threshold Selected
0
0
1
1
0
1
0
1
Not Valid. Device remains at previous threshold
VRT1 (default setting at SBC Init),
VRT2
VRT3
14.5.2.6 SBC Watchdog encoder
Table 18 list the 32 possible watchdog timer.
Table 18
Bit 10...6
00000
00001
00010
...
Watchdog Encoder
Decimal calculation (ms)
Timer (ms)
16
32
48
0
1
2
(n+1) × 16
n = decimal value of
setting
...
15
...
01111
256 (default setting)
Data Sheet
68
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
Table 18
Bit 10...6
10000
10001
...
Watchdog Encoder
Decimal calculation (ms)
Timer (ms)
304
352
16
17
...
n × 48 - 464
...
11110
11111
30
31
976
1024
14.5.3
SBC Diagnostic encoder
The SBC offers diagnostics information. The encoding of the different possible failures are listed in the following
table. The description apply only to data output.
14.5.3.1 Reason for restart and reset
Reason for reset, without activation of the Limp Home and the way it is encoded are summed up in Table 19. The
bits are cleared by reading the register with Read-Only command. When coming from Sleep Mode or Fail Safe
Mode the bits are cleared.
Table 19
Reason to Enter SBC Restart Mode without Limp HomeLimp Home activation
RM1
RM0
Cause for entering SBC Restart Mode
0
0
1
1
0
1
0
1
No reset has occurred or Limp Home activated
Undervoltage on Vcc1µC
First Watchdog failure (config 3 and 4) or no acknowledge of the Cyclic Wake-up
SPI command in SBC Software Flash Mode or reset low from outside
Data Sheet
69
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.5.3.2 Limp Home failure encoder
Table 20 describes the encoding of all possible reason to activate automatically the Limp Home output. Bits are
set back to “000” when switching Limp Home off via SPI.
Table 20
LH2
0
Limp Home Failure Diagnosis
LH1
0
LH0
0
Failure1)
No failure
0
0
1
Vcc1µC undervoltage Time-out
0
0
1
1
1
0
0
1
0
One Watchdog failure (config 1 and 2)
Two consecutive Watchdog failures (config 3 and 4)
INIT Mode Time-out
1
1
0
1
1
0
Temperature shutdown at Vcc1µC
Reset clamped
1
1
1
Reserved
14.5.3.3 Test pin and failure to Limp Home configuration read out
The SBC allows to read the hardware setting of the configuration that is done via the INT pin, as well as the test
pin and the WD to LH bit. Table 21 describes the encoding of these informations.
Table 21
Test2
Test pin and SBC Configuration
Test1
Test0
Test Read Out1)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
V
V
V
V
cc1µC remains ON in SBC Restart Mode after one Watchdog failure (config 1)
cc1µC is OFF in SBC Fail-Safe Mode after one Watchdog failure (config 2)
cc1µC remains ON in SBC Restart Mode after two Watchdog failures (config 3)
cc1µC is OFF in SBC Fail-Safe Mode after two Watchdog failures (config 4)
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
1
1
1
0
1
1
1
0
1
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
Software Development Mode. In case of watchdog failure Vcc1µC remains ON, no
reset is generated and Restart Mode or Fail-Safe Mode are not entered.
1) Refer also to Chapter 4.2.1
Data Sheet
70
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.6
SPI Output Data
14.6.1
First SPI output data
Since the SPI output data is sent when the SBC is receiving data, the output data are dependent of the previous
SPI command, if no Read Only command is used. Under some conditions there is no “previous command”.
Table 22 gives the first SPI output data that is sent to the microcontroller when entering SBC Normal Mode,
depending on the mode where the SBC was before receiving the first SPI command.
.
Table 22
First SPI output data frame
Previous SBC mode
Sleep mode
Fail-Safe mode
Mode selection bits (MS2...0) Configuration select (CS 2..0)
Sleep mode
Wake Register interrupt1)
Limp Home register1)
Fail-Safe mode
Restart mode
Restart mode when failure and config 1 / 3
Limp Home register1)
Restart mode when microcontroller has sent Restart mode
to Restart mode
SBC Configuration Register
SBC Init mode
Init mode
SBC Configuration Register
1) This does not clear the bits. It will be reset when the microcontroller requests the read out
Data Sheet
71
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.6.2
Read Only command
In the Mode Selection Bits a Read Only can be selected. The Read Only access clears the INT bits that are
selected in the Configuration Select (some interrupt bits show a state, and can not be cleared with a SPI read).
With this SPI command no write access is done to the SBC, and the mode of the SBC is not changed. The
watchdog can also be triggered with a Read Only command.
The Read Only command delivers the information requested with the Configuration Select in the same SPI
command on the SDO pin. As all other SPI commands deliver the requested information with the next SPI
command.
Figure 34 shows an example of a Read Only access. The bits are shown with LSB first, on the left side in
difference to the register description.
DI
DI
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
MS0 MS1 MS2 CS0
CS1
CS2
MS0 MS1 MS2 CS0
CS1
CS2
Mode Selection
WD
Mode Selection
WD
Configuration Select
Configuration Select
Configuration Registers
Configuration Registers
refresh
refresh
Bits
1
Bits
1
1
1
0
0
0
x
x
x
x
x
x
x
x
1
0
1
1
1
x
x
x
x
x
x
x
x
DO
DO
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
MS0 MS1 MS2 CS0
CS1
CS2
MS0 MS1 MS2 CS0
CS1
CS2
Mode Selection
WK
Mode Selection
WK
Configuration Select
Configuration Select
Configuration Registers
Configuration Registers
state
state
Bits
1
Bits
1
1
0
0
0
0
x
x
x
x
x
x
x
x
1
0
1
0
0
x
x
x
x
x
x
x
x
TIME
Figure 34 Read Only Command
Figure 35 shows an example of an SPI write access in normal mode for comparison. The requested information
is sent out with the next SPI command.
DI
DI
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
MS0 MS1 MS2 CS0
CS1
CS2
MS0 MS1 MS2 CS0
CS1
CS2
Mode Selection
WD
Mode Selection
WD
Configuration Select
Configuration Select
Configuration Registers
Configuration Registers
refresh
refresh
Bits
1
Bits
1
1
0
0
0
0
x
x
x
x
x
x
x
x
1
0
1
1
1
x
x
x
x
x
x
x
x
DO
DO
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
x
7
x
8
9
10 11 12 13 14 15
MS0 MS1 MS2 CS0
CS1
CS2
MS0 MS1 MS2 CS0
CS1
CS2
Mode Selection
WK
Mode Selection
WK
Configuration Select
Configuration Select
Configuration Registers
Configuration Registers
state
state
Bits
1
Bits
1
1
0
1
0
0
x
x
x
x
x
x
x
x
1
0
0
0
0
x
x
x
x
x
x
x
x
TIME
Figure 35 Write Command
Data Sheet
72
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.7
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit
Test Condition
Min.
SPI Interface; Logic Inputs SDI, CLK and CSN
Typ.
Max.
14.7.1
14.7.2
14.7.3
14.7.4
14.7.5
14.7.6
H-input Voltage Threshold VIH
–
–
–
0.7 x
V
–
–
VCC1µC
L-input Voltage Threshold VIL
0.3 x
VCC1µC
–
V
1)
Hysteresis of input
Voltage
VIHY
0.12 x
VCC1µC
40
40
10
V
–
Pull-up Resistance at pin RICSN
20
80
80
-
kΩ
kΩ
pF
V
V
CSN = 0.7 × VCC1µC
CSN
Pull-down Resistance at RICLK/SDI 20
SDI/CLK = 0.2 × VCC1µC
pin SDI and CLK
Input Capacitance
at pin CSN, SDI or CLK
CI
–
-1)
Logic Output SDO
14.7.7
14.7.8
14.7.9
H-output Voltage Level
L-output Voltage Level
Tri-state Leakage Current ISDOLK
VSDOH
V
CC1µC - VCC1µC - –
V
I
I
DOH = -1.6 mA
DOL = 1.6 mA
0.4
–
0.2
0.2
VSDOL
0.4
10
15
V
-10
–
–
µA
pF
VCSN = VCC1µC;
0 V < VDO < VCC1
14.7.10 Tri-state Input
Capacitance
CSDO
10
1)
Data Input Timing1)
14.7.11 Clock Period
tpCLK
tCLKH
tCLKL
tbef
250
125
125
125
250
250
125
100
50
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
14.7.12 Clock High Time
14.7.13 Clock Low Time
14.7.14 Clock Low before CSN
Low
14.7.15 CSN Setup Time
tlead
tlag
14.7.16 CLK Setup Time
14.7.17 Clock Low after CSN High tbeh
14.7.18 SDI Set-up Time
14.7.19 SDI Hold Time
tDISU
tDIHO
Data Sheet
73
Rev. 1.0, 2009-05-26
TLE8261-2E
Serial Peripheral Interface
14.7
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Pos.
Parameter
Symbol
Limit Values
Unit
Test Condition
Min.
Typ.
Max.
14.7.20 Input Signal Rise Time
at pin SDI, CLK and CSN
14.7.21 Input Signal Fall Time
at pin SDI, CLK and CSN
trIN
tfIN
tfIN
–
–
50
50
10
ns
ns
µs
–
–
–
–
–
–
–
14.7.22 Delay Time for Mode
Change from Normal
Mode to Sleep Mode
14.7.23 CSN High Time
tCSN(high) 10
–
–
µs
-
Data Output Timing 1)
14.7.24 SDO Rise Time
14.7.25 SDO Fall Time
14.7.26 SDO Enable Time
14.7.27 SDO Disable Time
14.7.28 SDO Valid Time
trSDO
tfSDO
tENSDO
tDISSDO
tVASDO
–
–
–
–
–
30
30
–
–
–
80
80
50
50
60
ns
ns
ns
ns
ns
CL = 100 pF
CL = 100 pF
low impedance
high impedance
CL = 100 pF
1) Not subject to production test; specified by design
23
CSN
14
15
16
17
12
13
CLK
DI
18
LSB
19
MSB
not defined
26
27
28
DO
Flag
LSB
MSB
Figure 36 SPI Timing Diagram
Note:Numbers in drawing correlate to the last 2 digits of the Pos. number in the Electrical Characteristics table.
Data Sheet
74
Rev. 1.0, 2009-05-26
TLE8261-2E
Application Information
15
Application Information
Note:The following information is given only as a hint for the implementation of the device and should not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
VDD
IC2
VS
T1
VBAT
VIO
D1
R1
VCC
VBAT
C3
C12
GND
C1
C2
IC3
VCC
C13
GND
VCC3ref
VS
VCC3shunt VCC3base
VS
VDD
Vcc1µC
C9
C10
R12
TLE8261-2
VDD
CSN
CLK
SDO
SDI
CSN
CLK
SDI
µC
SDO
TxD LIN 1
RxD LIN 1
TxD LIN 1
RxD LIN1
LOGIC
State
Machine
TxD CAN
RxD CAN
TxD CAN
RxD CAN
VBAT
S1
INT
RO
INT
VSS
Reset
VS
VDD
WK
VCC2
WK
VBAT
R9
C7
R10
R5
CAN cell
C14
VCCHSCAN
VBB
VDD
C11
CS
SCLK
SI
VS
CANH
SPLIT
CANL
CANH
CANL
SO
R7
R8
Limp Home
IC1
LHI
IN0
IN1
IN2
IN3
IN4
IN5
C8
T2
VS
LH_SI
LH_PL/Test
T3
GND
DEVICE GROUND
VS
GND
D5
S2
T4
Application _information
_TLE8261 -2E.vsd
Figure 37 Application Example for a Body Controller Module
Data Sheet
75
Rev. 1.0, 2009-05-26
TLE8261-2E
Application Information
Note:This is a very simplified example of an application circuit and bill of material. The function must be verified
in the actual application.
Table 23
Ref.
Bills of material
Option Vendor
Value
Purpose
Capacitance
C1
Y
68µF optional depending on
application
100nF
10µF ceramic cap low ESR
22nF 50V
47nF OEM dependent
10µF
Cut off battery spike
Kemet
Murata
C2
C3
C7
C8
C9
Y
N
Y
Y
Y
EMC
Stability of the VCC3
EMC
Improve SPLIT pin stability
Buffer of the VCC1µC depending on load.
(µC)
C10
C11
C12
C13
C14
N
N
Y
Y
Y
100nF
Stability of the VCC1µC
10µF CAN transceiver dependent
Buffering of the VCC2 for CAN Transceiver
Improve stability of the logic
Improve stability of the logic
Improve stability of the logic
100nF
100nF
100nF
Resistance
R1
N
220mΩ
VCC3 current measurement for ICC3
400mA max
R5
R7
R8
R9
R10
R12
Y
Y
Y
Y
Y
Y
1kΩ
Wetting current of the switch
CAN bus termination
CAN bus termination
Limit the WK pin current in ISO pulses
Insulation of the VDD supply
Set config 1/3. If not connected config 2/4
is selected
60Ω / OEM dependent
60Ω / OEM dependent
10kΩ
500Ω
47kΩ
Data Sheet
76
Rev. 1.0, 2009-05-26
TLE8261-2E
Application Information
Table 23
Ref.
Bills of material
Option Vendor
Value
Purpose
Active components
T1
N
ON Semi MJD253
Power element of VCC3
Infineon
BCP52-16
Alternative power element of VCC3, current
limit to be adapted R1 to be changed.
T2
T3
T4
D1
µC
IC1
IC2
IC3
N
N
N
N
N
Y
Y
Y
Infineon
Infineon
Infineon
Infineon
Infineon
Infineon
Infineon
Infineon
BCR191W
BCR191W
BCR191W
BAS 3010A
XC2xxx
SPOC - BTS5672E
TLE 6254-3G
TLE 6251DS
High active Limp Home
High active Limp Home
High active Limp Home
Reverse polarity protection
micro-controller
high side switches
Low speed CAN
High speed CAN
Data Sheet
77
Rev. 1.0, 2009-05-26
TLE8261-2E
Application Information
15.1
ZthJA Curve
60
50
40
30
20
10
0
Zth-JA(Ch4; 600)
Zth-JA(Ch4; 300)
Zth-JA(Ch4; 100)
Zth-JA(Ch4; footprint)
0,00001 0,0001
0,001
0,01
0,1
1
10
100
1000
10000
time (s)
Zthja curves.vsd
Figure 38 ZthJA Curve, Function of Cooling Area
300mm² cooling area 100mm² cooling area
minimum footprint
600mm² cooling area
PCB set up.vsd
Figure 39 Board Set-up
Board set-up is done according to JESD 51-3, single layer FR4 PCB 70 µm.
Data Sheet 78
Rev. 1.0, 2009-05-26
TLE8261-2E
Application Information
15.2
Hints for SBC Factory Flash Mode
The mode is used during production of the module to flash the µC. The idea is that the µC is not supplied from the
SBC but from an external 5V power supply. The reset of the µC that is connected to the RO pin of the SBC can
be driven from an external source and the SBC does not give a reset signal. Also no interrupt at the pin INT and
no signal on the SPI SDO pin is generated by the SBC. The SPI pins can be driven externally.
The mode is reached by applying 5V to the VCC1µC pin and no voltage to the Vs pin. The Vs pin will show a voltage
of about 4.5V because of the internal diode from VCC1µC to Vs. The current drawn at Vs must not exceed the
maximum rating of Ivs,max = -500mA. The function is designed for ambient temperature.
In case the Vs was supplied before going to FF Mode, the voltage on pin Vs must be set below 3 V before applying
5V to VCC1µC (discharging the C)
Not
supplied
Not
supplied
Reset
signal
5V
Vs
VCC1
µC
VBAT
C
IVS
Internal
supply
VDD
CSN
CLK
SDO
CSN
CLK
SDI
The current
flowing to other
devices from
Vs should be
limited to not
exceed the
maximum
µC
SDI
SDO
Other
Devices
TxD LIN1
RxD LIN1
TxD LIN2
RxD LIN2
TxD LIN3
RxD LIN3
TxD CAN
RxD CAN
TxD LIN1
RxD LIN1
TxD LIN2
RxD LIN2
TxD LIN3
RxD LIN3
TxD CAN
ratings.
RxD CAN
INT
Reset
INT
RO
VSS
Application_FF_Mode_2.vsd
Figure 40 Application Hint for Factor Flash Mode
Data Sheet
79
Rev. 1.0, 2009-05-26
TLE8261-2E
Application Information
Table 24
Pin
PIN in Factory Flash Mode
Level
Comment
Vs
typ. 4.5V
Voltage output from SBC. No voltage applied from
external.
Vcc1µC
RO
INT
5V 2%
To be applied from external
Can be driven from external
Pull-up resistor
Pull-up resistor
High impedance
High impedance
Pull-down resistor
Pull-up resistor
Can be driven from external if required
Can be driven from external if required
Can be driven from external if required
Can be driven from external if required
Can be driven from external if required
Can be driven from external if required
LH
SDO
CLK, SDI
CSN
TxDCAN, TxDLIN1,
TxDLIN2, TxDLIN3
Pull-up resistor
RxDCAN, RxDLIN1,
RxDLIN2, RxDLIN3
High impedance
Can be driven from external if required
15.3
ESD Tests
Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) have been performed. The results
and test condition is available in a test report. The values for the test are listed in Table 25 below.
Table 25
Performed Test
ESD “Gun test”
Result
Unit
kV
Remarks
positive pulse1)
ESD at pin CANH, CANL, > 8
BUSx, Vs versus GND
ESD at pin CANH, CANL, < -8
BUSx, Vs versus GND
kV
negative pulse
1) ESD susceptibility “ESD GUN” contact discharge (R=330Ohm C=150pF) (DIN EN 61000-4-2) tested according LIN EMC
1.3 Test Specification and ICT EMC Evaluation of CAN Transceiver. Tested by external test house (IBEE Zwickau, EMC
Test report Nr. 06-02-09a)
Data Sheet
80
Rev. 1.0, 2009-05-26
TLE8261-2E
Package Outline
16
Package Outline
0.35 x 45˚
1)
7.6-0.2
+0.09
0.23
0.65
0.2
0.3
0.7
0.1
36x
C
C
10.3
SEATING PLANE
D
17 x 0.65 = 11.05
2)
0.08
0.33
M
0.17 A-B C
36x
D
Bottom View
A
36
19
19
36
Exposed Diepad
Ejector Mark
1
18
18
1
Index Marking
Ex
B
1)
12.8-0.2
Index Marking
Exposed Diepad Dimensions4)
Package
Leadframe
Ex Ey
PG-DSO-36-24, -41, -42 A6901-C001
7
7
5.1
5.1
PG-DSO-36-38
PG-DSO-36-38
PG-DSO-36-50
A6901-C003
A6901-C007 5.2 4.6
A6901-C008 6.0 5.4
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
3) Distance from leads bottom (= seating plane) to exposed diepad
4) Excluding the mold flash allowance of 0.3 max per side
PG-DSO-36-24, -38, -41, -42, -50-PO V09
Figure 41 PG-DSO-36-38 (Leadframe A6901-003);)
Note:For the SBC product family the package PG-DSO-36-38 with the leadframe A6901-C003 is used.
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations, the Universal System Basis Chip is available as a green product. Green products are
RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-
020).
For information about packages and types of packing, refer to the
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
Data Sheet
81
Rev. 1.0, 2009-05-26
TLE8261-2E
Revision History
17
Revision History
Version Date
Parameter Changes
First Rev. of Data Sheet
1.0
2009-05-25
Data Sheet
82
Rev. 1.0, 2009-05-26
Edition 2009-05-26
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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