TLE92108-232QX_技术文档

TLE92108-232QX

Multiple MOSFET Driver IC

1

Overview

Features

•

Eight half-bridge gate drivers for external N-channel MOSFETs

Control of reverse battery protection MOSFET

Adaptive MOSFET gate control

–

Improved electromagnetic emission

Reduced switching losses in PWM mode

•

24-bit Serial Peripheral Interface

Two current sense amplifiers with configurable gain

–

High-side and low-side capable for protection and diagnosis

•

Drain-source monitoring for short circuit detection

Overtemperature warning and shutdown

Timeout watchdog

Detailed off-state diagnostic (open load, short circuit to battery or short circuit to GND) via SPI

Three PWM inputs

–

High-side and low-side PWM capable

Active free-wheeling

Up to 25 kHz PWM frequency

•

Low current consumption in sleep mode

Configurable low-side 1-4 brake with short circuit detection in sleep mode and normal mode

Configurable VS overvoltage detection in sleep mode

Leadless power package with support of optical lead tip inspection

Green Product (RoHS compliant)

AEC Qualified

Potential applications

•

Seat control and extended functions (steering column adjustment, gas pedal adjustment)

Power lift gate

Central door lock

Body control module (cargo cover, washer pump, window lift, rear wiper ...)

Datasheet

www.infineon.com

Rev. 1.0

2019-08-29

1

TLE92108-232QX

Multiple MOSFET Driver IC

Overview

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100.

Description

The TLE92108-232QX is a Multi-MOSFET driver IC dedicated to control up to sixteen n-channel MOSFETs. It

includes eight half-bridges for DC motor control applications such as automotive power seat control or other

applications.

A 24-bit Serial Peripheral Interface (SPI) is used to configure the TLE92108-232QX and to control the half-

bridges. It also allows the read out of the status registers for diagnostic purpose.

The TLE92108-232QX offers a wide range of diagnostic features such as the monitoring of the supply voltage,

the charge pump voltage, temperature warning and over-temperature shutdown. Each gate driver monitors

independently its external MOSFET drain-source voltage for fault conditions.

The device is housed in a VQFN-48 with exposed pad supporting lead tip inspection. The package provides a

good thermal performance and minimizes the required PCB space.

Type

Package

Marking

TLE92108-232QX

PG-VQFN-48

TLE92108-232QX

Datasheet

2

Rev.1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Table of contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

Voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

3.1

3.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

4.2

4.3

5

5.1

5.2

5.2.1

5.2.2

5.2.3

5.3

5.4

5.5

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Fail Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Electrical characteristics: supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Electrical characteristics: logic inputs PWMx, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Electrical characteristics charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6

5.6.1

5.6.2

5.6.3

6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.3

6.3.1

6.3.2

6.3.3

6.3.3.1

6.3.3.2

6.3.3.3

6.3.3.4

6.3.3.5

6.3.3.6

6.3.4

6.3.4.1

6.3.4.2

6.3.5

6.3.6

6.4

Floating gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

MOSFET control with bridge driver in active mode (BD_PASS = 0 and EN = High) . . . . . . . . . . . . . . . 25

Static activation with bridge driver in active mode (BD_PASS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Static activation of a high-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Static activation of a low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Turn-off of the high-side and low-side MOSFETs of a half-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PWM operation with bridge driver in active mode (BD_PASS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Determination of the active and free-wheeling MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Configuration in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PWM operation with adaptive gate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

High-side PWM with adaptive gate control, motor operating as load . . . . . . . . . . . . . . . . . . . . . . 37

Low-side PWM with adaptive gate control, motor operating as load . . . . . . . . . . . . . . . . . . . . . . 44

High-side PWM with adaptive gate control, motor operating as generator . . . . . . . . . . . . . . . . . 45

Low-side PWM with adaptive gate control, motor operating as generator . . . . . . . . . . . . . . . . . 47

Status bits for regulation of turn-on and turn-off delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Precharge and predischarge phases with EN_DEEP_AD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

PWM operation without adaptive gate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PWM operation without adaptive gate control, AGC[1:0] = (0,0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PWM operation without adaptive gate control, AGC[1:0] = (0,1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PWM operation at high and low duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Gate driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Passive discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Datasheet

3

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

6.5

6.6

Bridge driver in passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Electrical characteristics gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7

7.1

7.2

7.3

7.4

7.5

7.5.1

7.5.2

7.5.3

7.6

Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Safe switch (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Drain-source voltage monitoring with bridge driver in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Drain-source voltage monitoring with bridge driver in passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Cross-current protection and drain-source overvoltage blank time . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Drain-source overvoltage blank time in bridge driver active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Mapping of cross-current protection and blank times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

OFF-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

V_Sovervoltage and undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

V_Sundervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

V_Sovervoltage with bridge driver in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

V_Sovervoltage with bridge driver in passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.7

7.8

7.8.1

7.8.2

7.8.3

7.8.4

7.8.5

7.9

7.10

7.11

7.11.1

7.11.2

7.11.3

7.11.4

7.11.5

7.12

V

_DDundervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Charge pump undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Switching parameters of MOSFETs in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Timeout watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Unidirectional and bidirectional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Gain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

High-side and low-side setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

CSO outputs capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Electrical characteristics protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

8

Serial Peripheral Interface - SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

SPI protocol with independent slave selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Global Error Flag (GEF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SPI error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Daisy chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

SPI electrical characteristics: timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

8.1

8.2

8.3

8.4

8.5

8.6

9

9.1

9.1.1

9.1.2

9.2

Register specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

General Control Registers and Protection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Half-bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

General status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.2.1

10

11

12

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Datasheet

4

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Block diagram

2

Block diagram

Temperature warning

and shutdown

Charge Pump

DH

GH1

SH1

CSIN1

VS

VCP

UV & OV

Detection

VDS

Monitoring

GL1

GH2

SH2

GL2

EN

Internal Supply

VDD

GH3

SH3

Control Logic

SDI

SDO

SCLK

24-bit SPI

GL3

GH4

CSN

SH4

GL4

PWM1

PWM2

PWM3

PWMx

Mapping

GH5

SH5

EN

MOSFET

Control

GL5

GH6

Watchdog

Diagnostic

SH6

GL6

GH7

SH7

GL7

GH8

SH8

Protections

CS Gain Config.

GL8

Prog. Gain

SL

CSIP1

CSIN1

CSO1

CSO2

CSA1

Prog. Gain

CSIP2

CSIN2

CSA2

GND

Figure 1

Block diagram

Datasheet

5

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Block diagram

2.1

Voltage and current definition

Figure 2 shows terms used in this datasheet, with associated convention for positive value.

V_S

I_S

VS

I_CSIPx

I_CSOx

CSIPx

CSINx

I_CSINx

I_CP

I_CPCxP

I_CPCxN

I_DH

I_GHx

I_SHx

V_CSIPx

V_CSINx

V_CP

V_CPCxP

V_CPCxN

V_DH

V_GHx

V_SHx

V_GLx

V_SL

CSOx

PWMx

VDD

V_CSOx

V_{PWM x}

V_DD

V_SDO

V_SDI

V_CSN

V_SCLK

I_{PWM x}

I_DD

CP

CPCxP

CPCxN

DH

I_SDO

SDO

SDI

MULTIPLE GATE

DRIVER

I_SDI

I_CSN

CSN

SCLK

I_SCLK

GHx

SHx

I_EN

I_GLx

EN

GLx

SL

V_EN

I_SL

GND

I_GND

Figure 2

Voltage and current definition

Datasheet

6

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Pin configuration

3

Pin configuration

3.1

Pin assignment

GH3 37

SH3 38

CSIP1 39

24 SH6

23 GH6

22 CSN

21 SDO

CSIN1 40

PWM2 41

GL4 42

GL3 43

GL2 44

GL1 45

PWM1 46

GH2 47

SH2 48

20 EN

19 GL5

18 GL6

17 GL7

16 GL8

15 SL

14 SH7

13 GH7

Figure 3

Pin configuration TLE92108-232QX

Datasheet

7

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Pin configuration

3.2

Pin definitions and functions

Table 1

Pin configuration TLE92108-232QX

Symbol

Function

1

GH1

Gate high-side 1

Analog I/O pin to turn on/off high-side MOSFET 1. Connect to the gate of high-

side MOSFET 1.

2

SH1

Source high-side 1

Connection to source of high-side MOSFET 1.

3

4

5

PWM3

CP

PWM input 3

Charge Pump Output

VS

Supply Voltage

Device supply voltage. Connect this pin to the supply (battery) voltage with a

reverse battery protection circuit.

6

CPC1N

CPC1P

CPC2P

CPC2N

DH

Negative connection to Charge Pump Capacitor 1

Positive connection to Charge Pump Capacitor 1

Positive connection to Charge Pump Capacitor 2

Negative connection to Charge Pump Capacitor 2

7

8

9

10

Drain input for high-sides

Input for the drains of high-side MOSFETs. Refer to Chapter 7.3.

11

12

13

14

15

GH8

SH8

GH7

SH7

SL

Gate high-side 8

Source high-side 8

Gate high-side 7

Source high-side 7

Source low-side

Common connection to the source of the low-side MOSFETs.

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

GL8

Gate low-side 8

GL7

Gate low-side 7

GL6

Gate low-side 6

GL5

Gate low-side 5

EN

Enable input with internal pull-down

Serial Data Output

SDO

CSN

GH6

SH6

GH5

SH5

CSIP2

CSIN2

SCLK

CSO2

Chip Select Not with internal pull-up

Gate high-side 6

Source high-side 6

Gate high-side 5

Source high-side 5

Non-Inverting input of the Current Sense Amplifier 2

Inverting input of the Current Sense Amplifier 2

Serial Clock Input with internal pull-down

Current Sense Amplifier Output 2

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Pin configuration

Table 1

31

Pin configuration TLE92108-232QX

Symbol

VDD

Function

Logic supply

32

GND

CSO1

SDI

Ground connection

33

Current Sense Amplifier Output1

Serial Data Input with internal pull-down

Gate high-side 4

34

35

GH4

36

SH4

Source high-side 4

37

GH3

Gate high-side 3

38

SH3

Source high-side 3

39

CSIP1

CSIN1

Non-inverting input of the Current Sense Amplifier 1

40

Inverting input of the Current Sense Amplifier 1 . This pin can be used as

reference for the high-side MOSFET drain if CSA1 is configured as high-side. Refer

to Chapter 7.3

41

42

43

44

45

46

47

48

PWM2

GL4

PWM input 2

Gate low-side 4

Gate low-side 3

Gate low-side 2

Gate low-side 1

PWM input 1

GL3

GL2

GL1

PWM1

GH2

SH2

E.P.

Gate high-side 2

Source high-side 2

Exposed pad

For cooling purpose only, do not use as electrical GND¹⁾.

1) The exposed pad at the bottom of the package allows better power dissipation from TLE92108-232QX via the PCB.

The exposed pad must be left floating or connected to GND (recommended) for best EMC and thermal performance.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General product characteristics

4

General product characteristics

4.1

Absolute maximum ratings

Table 2

Absolute maximum ratings¹⁾

T_j= -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Voltages

Supply voltage

V_S

-0.3

–

40

V

–

P_4.1.1

P_4.1.2

PWM input voltages (PWMx)

V_PWMx

V_DD

0.3

+

|I |< 10 mA

Logic input voltages (SDI, SCLK, V_SDI, V_SCLK

CSN, EN)

,

-0.3

–

V_DD

0.3

V

|I |< 10 mA

P_4.1.3

P_4.1.4

P_4.1.5

P_4.1.21

V

_CSN, V_EN

Voltage range and SDO

V_SDO

V_DD

0.3

|I |< 10 mA

Voltage range at CSIPx and

CSINx

V_CSIP, V_CSIN-8.0

40

–

Differential input voltage range V_CSIDiff

-8.0

8.0

CSIPx - CSINx

Voltage range at DH

Voltage range at SL

Voltage range at SHx

Voltage range at GHx

Voltage range at GLx

V_DH

V_SL

V_SH

V_GH

V_GL

-0.3

-8.0

-0.3

–

40

6.0

48

24

16

V

–

P_4.1.6

P_4.1.7

P_4.1.8

P_4.1.9

P_4.1.10

P_4.1.11

Voltage difference between GLx V_{GS_LS}

and SL

2)

Voltage difference between GHx V_{GS_HS}

and SHx

-1.0

–

16

V

P_4.1.23

P_4.1.12

P_4.1.22

Voltage range at charge pump V_CP

pins CP

V_S-0.3

V_CP-0.3

V_S+15

–

Voltage range at charge pump V_CPCx

pins CPC1N, CPC1P, CPC2N,

CPC2P

V_CP+0.3 V

Logic supply voltage

Voltage at CSOx

V_DD

-0.3

–

5.5

V

–

P_4.1.13

P_4.1.14

V_CSOx

V_DD+

0.3

Temperatures

Junction temperature

Storage temperature

T_j

-40

-55

–

150

°C

–

T_stg

P_4.1.16

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General product characteristics

Table 2

Absolute maximum ratings¹⁾(cont’d)

T_j= -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

ESD susceptibility

ESD susceptibility all pins

V_ESDHBM1

-2

-4

–

2

4

kV

HBM³⁾

P_4.1.17

P_4.1.18

ESD susceptibility of VS and DH V_ESDHBM2

pins versus GND

ESD susceptibility all pins

V_ESDCDM1

V_ESDCDM2

-500

-750

–

500

750

V

CDM⁴⁾

P_4.1.19

P_4.1.20

ESD susceptibility pin corner

pins

1) Not subject to production test, specified by design.

2) _{GS_GH}may be between -1.0 and -0.3V only if the current injected into SHx is below 4 mA

V

3) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF).

4) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101.

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

4.2

Functional range

Table 3

Functional range

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Numbe

r

Min.

Max.

Supply voltage range for

normal operation

V_S(nor)

V_S(ext)

6.0

–

28

V

–

P_4.2.1

Extended supply voltage

range

5.5

28

–

6

V

¹⁾Parameter

deviations

possible

¹⁾Parameter

deviations

possible

1)

P_4.2.7

Extended supply voltage

range

V_S(ext)

–

V_{SOV_OFF2}

V

P_4.2.2

P_4.2.3

(max)

Supply voltage transients dV_S/dt -10

10

V/µs

slew rate

Logic supply voltage

SPI logic input voltage

V_DD

V_SDI

3.0

0

–

5.5

V

–

P_4.2.4

P_4.2.5

,

V_DD

V_SCLK

V_CSN

,

Junction temperature

T_j

-40

–

150

°C

–

P_4.2.6

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General product characteristics

1) Not subject to production test, specified by design.

Note:

Within the functional or operating range, the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the Electrical Characteristics

table.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General product characteristics

4.3

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 4

Thermal resistance

Parameter

Symbol

Values

Typ.

4.4

Unit Note or

Test Condition

Number

Min.

Max.

1)

Junction to case

R_thJC

R_thJA

–

K/W

1)2)

Junction to ambient

–

27

1) Not subject to production test, specified by design.

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 mm Cu,

2 × 35 mm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

5

General description

5.1

Power supply

The Multiple MOSFET Driver IC requires two power supplies: V_Sand V_DD

_DDsupplies the I/O buffers (including the SPI pins) and the internal voltage regulator for the logic. V_DDallows

the flexibility of a 3.3 V or a 5.0 V logic interface.

.

V

V_Ssupplies the charge pump for the MOSFET gate drivers. The V_Spin must be connected to the battery through

a reverse battery protection.

Both supplies are separated so that the information stored in the logic remains intact in the event of voltage

drop on V_S. V_DDand V_Sshould be decoupled with ceramic capacitors connected close to the supply and ground

planes.

5.2

Operation modes

EN = High

Sleep Mode

EN = Low

Low current

consumption

Gate Drivers OFF

Normal Mode

EN = High

EN = Low

Watchdog continuously

retriggered

Watchdog Error

Fail Safe Mode

EN = High

1. GENSTAT register is cleared

2. WDTRIG bit set to 1

3. WDTRIG bit set to 0 within the watchdog period

FS = 1

External MOSFETs

are turned OFF

Figure 4

State diagram

Note:

The state diagram is valid for V_Sand V_DDwithin the nominal operating range. For V_Sand V_DDoutside

of the nominal range, refer to Chapter 7.8, respectively Chapter 5.2.2.

5.2.1

Normal mode

The TLE92108-232QX enters Normal Mode by setting EN pin to High and waiting for the SPI setup time t_{SET_SPI}

.

In normal mode, the MOSFET gate drivers are enabled and can be configured through the SPI interface,

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

provided that the voltages applied to V_DDand V_Sare within the operating range. The watchdog must be

retriggered correctly in order to stay in Normal Mode (see Chapter 7.10).

5.2.2

Sleep mode

The Multiple MOSFET Driver IC enters Sleep Mode by setting EN pin to Low. The transition to the sleep mode

1)

is delayed by t_DSLEEP(max tCCP of active half-bridges + 3 µs) in order to actively turn-off the external

MOSFETs. In this mode, the internal regulator and the internal circuitry are deactivated, and the SPI registers

are reset.

The current consumption of V_DDis reduced to I_{DD_Q}. The current consumption of V_Sis reduced to I_SQor I_SQ

I_{SQ_BRAKE}

+

.

The V_Scurrent consumption is I_SQif:

•

PASS_MOD = 00_Band PASS_VDS = 0_Bwhile entering sleep mode

and V_Snever drops below V_{SLEEP_SET}after entering sleep mode

•

The V_Scurrent consumption is I_SQ+ I_{SQ_BRAKE}if:

PASS_MOD = 01_B, 10_B, 11_Bor PASS_VDS = 1_Bwhile entering sleep mode

or V_Shas recovered from a voltage below V_{SLEEP_SET}(i.e. V_Shas ramped up from a voltage below V_{SLEEP_SET}

or V_Shas dropped below V_{SLEEP_SET}

•

)

The internal resistors R_GGNDbetween GHx/GLx and GND are activated to discharge the gate of the external

MOSFETs.

Note:

If EN is set to Low for a duration shorter than (t_{ENL_FILT}, 8 µs max.), and EN is set to High again, then

device does not go in sleep mode and the registers are not reset. The half-bridges are reactivated

according to the settings of the control registers when EN is High.

5.2.3

Fail Safe Mode

In case of watchdog error (see Chapter 7.10), the device enters Fail Safe Mode, FS bit is set (see Global status

byte) and the external MOSFETs are actively discharged with the static discharge current (Chapter 6.2) during

the max. configured tHBxCCP active (Chapter 7.5.1). Then the bridge driver is set to passive mode (the passive

discharge path is activated,Chapter 6.4, all external MOSFETs are latched off, and the charge pump is

deactivated). To resume Normal Mode the microcontroller must execute the following sequence²⁾:

1. Clear GENSTAT register.

2. Write WDTRIG bit to 1 (GENCTRL1) within the watchdog period.

3. Write WDTRIG bit to 0 within the watchdog period³⁾.

In fail safe mode, the control registers are frozen to their default value, at the exception of WDTRIG, CCSO,

PASS_VDS, PASS_MOD, CSA1L, CSA2L. Any write command (except for WDTRIG bit) or clear command

(except for GENSTAT) will be discarded in this mode and sets SPIE bit (Global status byte).

A clear command to GENSTAT in fail safe mode does not reset any failure flag reported by this status register.

1) SPI Frames are ignored during t_DSLEEP

.

2) The exit sequence must be strictly followed to leave fail safe mode. If a SPI frame not belonging to the sequence is added, then the

device stays in fail safe mode and the microcontroller must restart the complete sequence to enter normal mode.

3) During Fail Safe Mode, the charge pump is deactivated and CPUV is set. Therefore, recovering from Fail Safe Mode, GENSTAT must

be cleared again at the end of the Fail Safe exit sequence to re-activate of the gate drivers.

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

The control and status registers can be read in this mode before the start of the exit sequence without SPIE bit

being set.

5.3

Reset behavior

The following events trigger a Power On Reset:

V_DDundervoltage reset:

If V_DD< V_{DD PoffR}the digital block is deactivated and the outputs are switched off. The digital block is reset once

V_DD> V_{DD POR}. Then NPOR bit (negated power-on reset bit, see Global status byte) is reset to 0 to report the

reset condition.

Reset on EN pin:

If the EN pin is pulled low, the logic content is reset and the device enters sleep mode. Once the device enters

Normal Mode (after t_{SET_SPI}with EN = high and V_DD> V_{DD POR}), the NPOR bit is reset to 0 to report the reset

condition.

NPOR is set to 1 when GENSTAT is cleared.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

5.4

Charge pump

A dual-stage charge pump supplies the gate drivers for the high-side and low-side MOSFETs. It requires three

external capacitors connected between CPC1N and CPC1P, CPC2N and CPC2P, VS and CP.

C_CP≥ 470 nF

C_CP1

C_CP2

VS

CP

Single/dual stage

charge pump

Precharge

Logic

Figure 5

Charge pump

CPSTGA = 0 (default, see GENCTRL2), the device operates with the dual-stage charge pump.

If CPSTGA = 1 (GENCTRL2), the device switches automatically to single-stage or dual-stage charge pump

automatically:

•

If V_S> V_{CPSO DS}: the TLE92108-232QX switches from a dual-stage to a single-stage charge pump.

If V_S< V_{CPSO SD}: the TLE92108-232QX switches from single-stage to dual-stage charge pump.

The operation with the single-stage charge pump reduces the current consumption from the VS pin.

5.5

Frequency modulation

A modulation of the charge pump frequency can be activated to reduce the peak emission. The modulation

frequency can be selected based on the resolution bandwidth of the peak detector during EMC testing.

The modulation frequency is set by the control bit FMODE in GENCTRL1

•

FMODE = 0: No modulation.

FMODE = 1: Modulation frequency = 15.6 kHz (default).

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

5.6

Electrical characteristics

5.6.1

Electrical characteristics: supply

Table 5

Electrical characteristics: supply

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Current consumption, EN = LOW)

Supply quiescent current

I_SQ

–

2

5

µA

T_j< 85°C, V_S= 13.5 V P_5.5.1

PASS_MOD=00_B,

PASS_VDS=0_B

I_SQ2

–

7

T_j< 85°C, V_S< 25 V P_5.5.61

PASS_MOD=00_B,P

ASS_VDS=0_B

Additional supply quiescent I_{SQ_BRAKE}

current, brake enabled

7.5

T_j< 85°C,

P_5.5.60

V_S= 13.5 V ¹⁾

PASS_MOD=01_Bor

10_Bor 11_Bor

PASS_VDS=1_B

Logic Supply quiescent

current

I_{DD_Q}

–

1

3

8

µA

T_j< 85°C

P_5.5.3

Total quiescent current

I_{DD_Q}+ I_SQ

T_j< 85°C, V_S= 13.5 V P_5.5.5

PASS_MOD=00_B,

PASS_VDS

EN Low filter time

t_DSLEEP

–

Max.

tCCP +

3 µs

µs

²⁾³⁾BD_PASS = 0

P_5.5.49

2)

EN Low filter time

VS for LS1-4 setting

t_{ENL_FILT}

1

–

8

µs

V

P_5.5.51

P_5.5.63

V_{SLEEP_SET}

5.5

Current consumption, EN = HIGH

Supply current

I_S1

–

45

83

55

mA

HBxVDSTH = 001_B, P_5.5.6

BD_PASS = 0,

I_CP= 0 mA

Supply current

I_S2

100

8 V < V_S< 28 V

P_5.5.7

HBxVDSTH = 001_B,

BD_PASS = 0,

I_CP= -12 mA,

dual stage CP

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

Table 5

Electrical characteristics: supply (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

55

Unit Note or

Test Condition

Number

Min.

Max.

Supply current

I_S3

–

70

mA

18 V < V_S< 28 V

HBxVDSTH = 001_B,

BD_PASS = 0,

P_5.5.56

I

_CP= -12 mA²⁾,

single stage CP

Supply current

I_S4

–

55

70

V_S= 6 V,

P_5.5.57

HBxVDSTH = 001_B,

BD_PASS = 0,

I

_CP= - 6 mA²⁾

Supply current

I_{S_BD_PASS}

I_DD1

–

10

3

20

4

mA

HBxMODE=00_B,

BD_PASS = 1

P_5.5.54

P_5.5.8

Logic supply current

SPI not active,

CSA1 and CSA2 off,

all I_PDDiagoff,

BD_PASS=0

Logic supply current

I_DD2

–

3

2

3.8

2.8

mA

⁴⁾Additional VDD P_5.5.52

current per CSA on,

VCSOx = 4.5 V,

LS shunt, CCSO = 1

CSAxL = 0,

I_PDDiagoff

I_DD3

⁴⁾Additional VDD P_5.5.55

current per CSA on,

CCSO = 0,

VCSOx = 4.5 V,

LS shunt,

CSAxL = 0,

I

_PDDiagoff

Logic supply current

I_DD4

–

6

7

mA

⁵⁾Additional VDD P_5.5.58

current per CSA on,

VCSOx = 4.5 V,

HS shunt,

VSOVTH = 1

CSAxL = 1,

I

_PDDiagoff

I_DD5

4.2

5.2

⁵⁾Additional VDD P_5.5.59

current per CSA on,

VSOVTH = 0,

VCSOx = 4.5 V,

HS shunt,

CSAxL = 1,

I_PDDiagoff

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

Table 5

Electrical characteristics: supply (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

1.5

Unit Note or

Test Condition

Number

Min.

Max.

Additional logic supply

current pull-down

I_{DD_PDDiag}

–

2

mA

Additional VDD

current when all

P_5.5.53

I_PDDiagare on

VS with active bridge driver (BD_PASS = 0)

UV switch ON voltage

UV switch OFF voltage

UV ON/OFF hysteresis

V_{SUV ON}

V_{SUV OFF}

V_{SUV HY}

–

5.5

5.0

–

V

V_Sincreasing

V_Sdecreasing

V_{SUV ON}- V_{SUV OFF}

V_Sincreasing

P_5.5.11

P_5.5.12

P_5.5.13

P_5.5.14

4.0

–

4.5

0.5

–

2)

OV switch OFF voltage

VSOVTH = 0

V_{SOV OFF1}

19

21

OV switch ON voltage

VSOVTH = 0

V_{SOV ON1}

V_{SOV OFF2}

V_{SOV ON2}

V_{SOV HY}

18

29

28

–

20

31

30

V

V_Sdecreasing

V_Sincreasing

V_Sdecreasing

P_5.5.15

P_5.5.16

P_5.5.17

OV switch OFF voltage

VSOVTH = 1

OV switch ON voltage

VSOVTH = 1

2)

OV ON/OFF hysteresis

–

1

–

V

V_{SUV ON}- V_{SUV OFF}

1)

P_5.5.18

P_5.5.47

P_5.5.48

P_5.5.50

VS undervoltage filter time t_{VSUV_FILT}

7

10

16

13

19.2

µs

2)

VS overvoltage filter time

t_{VSOV_FILT}

t_{D_CPVSOV}

7

CP turn-off delay after VS

overvoltage detection

12.8

VDD

V_DDPower-On-Reset

V_DDPower-Off-Reset

V_DDPower-On-Reset

V_{DD POR}

2.40

2.30

–

2.60

2.50

0.1

2.80

2.70

–

V

V_DDincreasing

V_DDdecreasing

V_{DD POR}- V_{DD POffR}

P_5.5.19

P_5.5.20

P_5.5.21

V_{DD POffR}

V_{DD POR HY}

2)

Hysteresis

1) Additional quiescent current if VS drops below V_{SLEEP_SET}

.

2) Not subject to production test, specified by design.

3) Max. cross-current protection time of the active half-bridges.

4) Parameter independent of VSOVTH.

5) Parameter independent of CCSO.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

5.6.2

Electrical characteristics: logic inputs PWMx, EN

Table 6

Electrical characteristics: PWMx, EN

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

EN high voltage

EN low voltage

EN hysteresis

V_ENH

V_ENL

0.7 ×

V_DD

–

V

–

P_5.5.22

P_5.5.23

P_5.5.24

–

0.3 ×

V_DD

–

1)

V_ENHY

–

0.12 ×

–

V_DD

EN pull-down resistor

PWMx high voltage

R_{PD_EN}

V_PWMH

30

40

–

50

–

kΩ

–

P_5.5.25

P_5.5.26

0.7 ×

V

V_DD

PWMx low voltage

PWMx hysteresis

V_PWML

–

0.3 ×

V_DD

V

–

P_5.5.27

P_5.5.28

P_5.5.29

1)

V_PWMHY

–

0.12 ×

V_DD

–

V

PWMx pull-down resistor

R_{PD_PWMx}

30

40

50

kΩ

–

1) Not subject to production test, specified by design.

5.6.3

Electrical characteristics charge pump

Table 7

Electrical characteristics: charge pump

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

250

Unit

Note or

Test Condition

Number

Min.

–

Max.

3)

Charge Pump Frequency

Output Voltage VCP vs. VS

f_CP

–

kHz

V

P_5.5.30

P_5.5.31

V_CPmin

8.5

–

V_S= 6 V,

I

_CP= - 6 mA

8 V < V_S< 28 V,

_CP= - 12 mA

18 V < V_S< 28 V,

_CP= - 12 mA

Regulated output voltage

VCP vs. VS, CPSTGA = 0

V_CP1

11

12

10

15

40

60

40

17

80

100

80

V

P_5.5.32

P_5.5.41

P_5.5.34

P_5.5.35

P_5.5.36

I

Regulated output voltage

VCP vs. VS, CPSTGA = 1

V_CP2

V

I

Turn-on time, CPSTGA = 0

t_{ON_VCP1}

t_{RISE_VCP1}

t_{ON_VCP2}

µs

8 V < V_S< 28 V

(25%)^1)2)3)4)

Rise time, CPSTGA = 0

8 V < V_S< 28 V

(25%-75%)^1)2)3)4)

Turn-on time, CPSTGA = 1

18 V < V_S< 28 V

(25%)^1)2)3)5)

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TLE92108-232QX

Multiple MOSFET Driver IC

General description

Table 7

Electrical characteristics: charge pump

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

60

Unit

Note or

Test Condition

Number

Min.

Max.

Rise time, CPSTGA = 1

t_{RISE_VCP2}

10

100

µs

V

18 V < V_S< 28 V

P_5.5.37

P_5.5.38

P_5.5.42

P_5.5.43

P_5.5.44

P_5.5.45

P_5.5.39

(25%-75%)^1)2)3)5)

Charge Pump Undervoltage V_CPUV1

(referred to VS)

5.5

7

6

6.5

8

CPUVTH = 0,

VCP falling

Charge Pump Undervoltage V_CPUV2

(referred to VS)

7.5

17

16.5

0.5

64

–

V

CPUVTH = 1,

VCP falling

Automatic switch over dual V_{CPSO DS}

to single stage charge pump

16

15.5

–

18

17.5

–

V

CPSTGA = 1

³⁾CPSTGA = 1,

Automatic switch oversingle V_{CPSO SD}

to dual stage charge pump

V

Charge pump switch over

hysteresis

V_{CPSO HY}

V

_{CPSO DS}- V_{CPSO SD}

3)

Charge Pump Undervoltage t_CPUV

Filter Time

51

–

77

µs

mA

Charge pump minimum

output current

I_CPOC1

I_CPOC2

-12

²⁾³⁾⁴⁾V_S= 13.5 V;

CPSTGA = 0

²⁾³⁾⁵⁾V_S= 18 V;

CPSTGA = 1

Charge pump minimum

output current

–

1) Parameter dependent on the capacitance C_CP.

2) _CPC1= C_CPC2= 220 nF, C_CP= 470 nF, I_CP= 0 mA.

C

3) Not subject to production test, specified by design.

4) Dual stage charge pump.

5) Single stage charge pump.

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Multiple MOSFET Driver IC

Floating gate drivers

6

Floating gate drivers

The TLE92108-232QX integrates sixteen floating gate drivers capable of controlling a wide range of n-channel

MOSFETs. They are configured as eight high-sides and low-sides, building eight half-bridges.

This section describes the MOSFET control by the gate drivers.

After power-on reset, the bridge driver is in passive mode (default value of BD_PASS = 1 and all

HBxMODE=00_B). Refer to Chapter 6.4 and Chapter 6.5.

The bridge driver is in active mode by setting BD_PASS to 0. Chapter 6.1, Chapter 6.2 and Chapter 6.3

describes the static and PWM control in active mode.

Attention: It is highly recommended to have all HBxMODE bits set to 00_Bor 11_Bbefore setting BD_PASS to

0 in order to avoid wrong drain-source overvoltage detection.

Table 8

EN

Operating modes of the gate driver

BD_PASS HBxMODE[1:0] Gate driver

Comment

Chapter

High

0

x

Active¹⁾

Chapter 6.1

Chapter 6.2

Chapter 6.3

High

1

One HBxMODE =

01_Bor 10_B

Active¹⁾

Equivalent to EN=High and

BD_PASS = 0

Chapter 6.1

Chapter 6.2

Chapter 6.3

High

Low

1

x

All HBxMODE=00_BPassive

or 11_B

Chapter 6.5

x

Passive

Chapter 6.5

1) Provided that no VS overvoltage, VS undervoltage, CP undervoltage or overtemperature failure are detected, and

TLE92108-232QX is not in Fail Safe Mode.

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Multiple MOSFET Driver IC

Floating gate drivers

CP

DH /

CSIN1

GHx

SHx

Highside

Gate-Driver

V_DSMONTH

Current-Steering

DACs

VSHH

High-Speed

Comparators

VSHL

VCP

GLx

Lowside

Gate-Driver

V_DSMONTH

Current-Steering

DACs

SL

Figure 6

Block diagram - Gate driver for one half-bridge

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Multiple MOSFET Driver IC

Floating gate drivers

6.1

MOSFET control with bridge driver in active mode (BD_PASS = 0 and EN = High)

Depending on the configuration bits HBxMODE[1:0] (HBMODE, Table 9 and Table 11), each high-side and low-

side MOSFETs can be:

•

deactivated

activated (statically, no PWM)

activated in PWM mode (Chapter 6.3, PWMSET)

Table 9

Half-bridge mode selection

HBxMODE[1:0]¹⁾Configuration of HSx/LSx¹⁾

00_B

01_B

10_B

LSx and HSx MOSFETs are actively kept OFF (default)

LSx MOSFET is ON (static or PWM, refer to Table 11), HSx MOSFET is actively kept OFF

HSx MOSFET is ON (static or PWM, refer to Table 11), LSx MOSFET is actively kept OFF

Reserved - LSx and HSx MOSFETs are actively kept OFF

11_B

1) x = 1 … 8.

6.2

Static activation with bridge driver in active mode (BD_PASS = 0)

In this section, we consider the static activation of the high-side and low-side MOSFET of the half-bridge x,

x = 1…8. Refer to Table 11 for the setting of a high-side or low-side in the static or PWM operation.

If HBx is not mapped to any activated PWM channel, the low-side or high-side MOSFET of HBx is statically

activated (no PWM) by setting HBxMODE[1:0] to respectively (0,1) or (1,0).

The configured cross-current protection and the Drain-Source overvoltage blank times for the Half-Bridge x

are noted t_{HBxCCP Active}and t_{HBxBLANK Active}(refer to Chapter 7.5).

The charge and discharge currents applied to the static controlled Half-Bridge x are noted ICHGSTx

(ST_ICHG).

IHARDOFF is the maximum current that the gate drivers can sink. It corresponds to the discharge current when

IDCHGx[4:0] = 31_D(See PWM_IDCHG_ACT). This current is used to the keep a MOSFET off, when the opposite

MOSFET of the same half-bridge is being turned on. This feature avoids parasitic cross-current conduction.

ICHGSTx is the current sourced, respectively sunk, by the gate driver to turn-on the high-side x or low-side x.

ICHGSTx is configured in the control register ST_ICHG.

Table 10

Static charge and discharge currents

ICHGSTx[3:0]¹⁾

Nom. charge current

[mA]²⁾

Nom. discharge current Max. deviation to typ.

[mA]³⁾

1.0

values

0000_B

0001_B

0010_B

0011_B

0100_B

0101_B

1.0

+/- 60%

+/- 60 %

+/- 38 %

2.0

2.8

4.5

5.7

8.0

9.4

12.5

17.8

14.2

19.7

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Multiple MOSFET Driver IC

Floating gate drivers

Table 10

Static charge and discharge currents

ICHGSTx[3:0]¹⁾

Nom. charge current

[mA]²⁾

Nom. discharge current Max. deviation to typ.

[mA]³⁾

26.0

32.0

39.5

46.8

54.7

62.5

70.6

78.5

87.0

95.0

values

0110_B

0111_B

1000_B

1001_B

1010_B

1011_B

1100_B

1101_B

1110_B

23.9

30.0

37.1

44.3

52.3

60.2

68.3

76.8

86.0

96.0

+/- 38 %

+/- 28 %

+/- 25 %

1111_B

1) Refer to ST_ICHG

2) V_S≥ 8V and V_GS≤ V_GS(ON)1if ICHGSTx ≤ 7_D, V_S≥ 8V and V_GS≤ V_GS(ON)2if ICHGSTx ≥ 8_D

3) V_GS≥ V_GS(OFF)1if ICHGSTx ≤ 7_D, V_GS≥ V_GS(OFF)2if ICHGSTx ≥ 8_D

IHOLD is the hold current used to keep the gate of the external MOSFETs in the desired state. This parameter

is configurable with the IHOLD control bit in GENCTRL2.

If IHOLD = 0:

•

the MOSFETs are kept ON with the current I_CHG8(12.5 mA typ.)

the MOSFETs are kept OFF with the current I_DCHG8(14.2 mA typ.)

If IHOLD = 1:

•

the MOSFETs are kept ON with the current I_CHG12(23.9 mA typ.)

the MOSFETs are kept with the current I_DCHG12(26.0 mA typ.)

The static discharge current is applied to turn off the MOSFETs when the bridge driver is in active mode

when the following failures occur:

•

V_Sundervoltage/overvoltage

Overtemperature

V

_DSovervoltage

Charge pump undervoltage

Overcurrent if OCEN = 1

6.2.1

Static activation of a high-side MOSFET

Turn-on with cross-current protection

If LSx is ON (HBxMODE[1:0] = 01_B), before the activation of HSx (HBxMODE[1:0] = 10_B) then the high-side

MOSFET is turned on after a cross-current protection time (refer to Figure 7):

•

after the CSN rising edge and for the duration t_{HBxCCP Active}:

–

the high-side MOSFET is kept OFF with the current -ICHGSTx

the gate of the low-side MOSFET is discharged with the current -ICHGSTx

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Multiple MOSFET Driver IC

Floating gate drivers

•

at the end of t_{HBxCCP Active}and for the duration t_{HBxBLANK Active}+ t_FVDS:

–

the gate of the high-side MOSFET is charged with the current ICHGSTx

low-side MOSFET is kept OFF with the current -IHARDOFF (hard off phase)

at the end of t_FVDS

:

–

the drive current of the high-side MOSFET is reduced to IHOLD

the drive current of the low-side MOSFET is set to -IHOLD

SPI Frame accepted

Turn on HSx

CSN

Previous State

HSx OFF

LSx ON

Æ

New State

HSx ON

LSx OFF

t

VS

tHBxCCP

Active

tHBxBLANK

Active

IGHx

tFVDS

ICHGSTx

HSx

GHx

0

t

IGHx

HSx internal

drive signal

SHx

ICHGSTx

LSx

GLx

SL

IHOLD

-IHOLD

IGLx

t

-ICHGSTx

IGLx

t

-ICHGSTx

LSx internal

drive signal

IHOLD

-IHOLD

t

-ICHGSTx

Hard off

-IHARDOFF

Figure 7

Turn-on of a high-side MOSFET with cross-current protection

Note:

The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are

executed with a delay of up to 3 µs after the CSN rising edge.

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Multiple MOSFET Driver IC

Floating gate drivers

Turn-on without cross-current protection

If LSx is OFF (HBxMODE[1:0] = 00_B), before the activation of HSx (HBxMODE[1:0] = 10_B), then the high-side

MOSFET is turned on without cross-current protection (refer to Figure 8):

•

after the CSN rising edge and for a duration t_{HBxBLANK Active}+ t_FVDS:

–

the gate of the high-side MOSFET is charged with the current ICHGSTx

the low-side MOSFET is kept OFF with the current -IHARDOFF

•

at the end of t_FVDS

:

–

the drive current of the high-side MOSFET is reduced to IHOLD

the drive current of the low-side MOSFET is set to -IHOLD

SPI Frame accepted

Turn on HSx

CSN

Previous State

HSx OFF

LSx OFF

Æ

New State

HSx ON

LSx OFF

t

tHBxBLANK

Active

IGHx

tFVDS

ICHGSTx

0

t

HSx internal

drive signal

ICHGSTx

VS

IHOLD

-IHOLD

t

HSx

GHx

IGHx

IGLx

0

SHx

t

LSx

GLx

SL

IGLx

LSx internal

drive signal

IHOLD

-IHOLD

t

Hard off

-IHARDOFF

Figure 8

Turn-on of a high-side MOSFET without cross-current protection

Note:

The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are

executed with a delay of up to 3 µs after the CSN rising edge.

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Multiple MOSFET Driver IC

Floating gate drivers

6.2.2

Static activation of a low-side MOSFET

The description of the static activation of a low-side x differs from the description of Chapter 6.2.1 only by

exchanging high-side x and low-side x.

6.2.3

Turn-off of the high-side and low-side MOSFETs of a half-bridge

When the TLE92108-232QX receives a SPI to turn-off both the high-side and low-side MOSFETs of the half-

bridge x (HBxMODE[1:0] = (0,0) or (1,1)):

•

the gate of HSx and LSx are discharged with the current -ICHGSTx for the duration t_{HBxCCP Active}(Figure 9)

at the end of t_{HBxCCP Active}, the drive current of HSx and LSx are reduced to -IHOLD

SPI Frame accepted

Turn off HSx and LSx

VS

CSN

HSx

t

GHx

IGHx

SHx

0

LSx

t

GLx

-ICHGSTx

IGLx

SL

HSx internal

drive signal

tHBxCCP

IHOLD

-IHOLD

t

-ICHGSTx

IGLx

LSx internal

drive signal

t

-IHOLD

-ICHGSTx

Figure 9

Turn-off of the high-side and low-side MOSFETs of a half-bridge

Note:

The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are

executed with a delay of up to 3 µs after the CSN rising edge.

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Multiple MOSFET Driver IC

Floating gate drivers

6.3

PWM operation with bridge driver in active mode (BD_PASS = 0)

The TLE92108-232QX integrates three PWM channels. The pins PWM1,PWM2 and PWM3 provide the PWM

signal for each PWM channel.

One half-bridge can be mapped to one of the PWM channels according to the settings of the control registers

HBMODE and PWMSET (see Table 11):

•

PWMxEN in PWMSET, enables or disables the PWM channel x

The control bits PWMx_HB[2:0] in PWMSET select the half-bridge

The control bits HBMODE[1:0] (HBMODE) of the half-bridge selected by PWMx_HB[2:0] configures the low-

side or the high-side MOSFET in PWM mode

Example: the following bits must be set to map the low-side of HB3 to the PWM channel 2 (start sequence with

PWM):

1. Set HB3MODE[1:0] to (0,0): HB3 is in high impedance

2. Set PWM2_HB[2:0] to (0,1,0) and set PWM2EN to 1 (HB3 stays in high impedance, independently from the

signal present at the PWM2 pin)

3. Set HB3MODE[1:0] to (0,1): PWM2 is applied to the low-side of HB3

Table 11

PWMxEN¹⁾

PWM channel settings

PWMx_HB[2:0] HByMODE[1:0]²⁾PWMx channel setting¹⁾

1)

0_B

don’t care

000_B

don’t care

00_B

no PWM operation

don’t care

no PWM operation on the selected HB

no PWM operation on the selection HB

Low-side of HB1 is mapped to PWMx

Low-side of HB2 is mapped to PWMx

Low-side of HB3 is mapped to PWMx

Low-side of HB4 is mapped to PWMx

Low-side of HB5 is mapped to PWMx

Low-side of HB6 is mapped to PWMx

Low-side of HB7 is mapped to PWMx

Low-side of HB8 is mapped to PWMx

High-side of HB1 is mapped to PWMx

High-side of HB2 is mapped to PWMx

High-side of HB3 is mapped to PWMx

High-side of HB4 is mapped to PWMx

High-side of HB5 is mapped to PWMx

High-side of HB6 is mapped to PWMx

High-side of HB7 is mapped to PWMx

High-side of HB8 is mapped to PWMx

don’t care

11_B

1_B

01_B

001_B

01_B

010_B

01_B

011_B

01_B

100_B

01_B

101_B

01_B

110_B

01_B

111_B

01_B

000_B

10_B

001_B

10_B

010_B

10_B

011_B

10_B

100_B

10_B

101_B

10_B

110_B

10_B

1_B

111_B

10_B

1) x = 1…3

2) the half-bridge y is selected by the PWMx_HB[2:0] bits

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Multiple MOSFET Driver IC

Floating gate drivers

Note:

An SPI error is reported if one half-bridge is mapped to several activated PWM channels. In this case

the external MOSFETs of the impacted half-bridge are turned-off and the corresponding status bit

(HBxPWME) of the HBVOUT_PWMERR register is set.

6.3.1

Determination of the active and free-wheeling MOSFET

An active free-wheeling is automatically implemented when a half-bridge is activated in PWM mode to reduce

the power dissipation of the free-wheeling (FW) MOSFET: If the active MOSFET is OFF, the opposite (free-

wheeling) MOSFET of the same half-bridge is actively turned on. See Figure 11, Figure 12, Figure 13,

Figure 14, .

If EN_GEN_CHECK = 0: the PWM MOSFET is considered as the active MOSFET and the opposite MOSFET of the

same half-bridge is considered as the free-wheeling MOSFET.

If EN_GEN_CHECK = 1: At the end of the cross-current protection times (tHBxCCP Active, tHBxCCP FW) of each

MOSFET (both MOSFETs are supposed to be off) the device detects which MOSFET of the half-bridge is the

active MOSFET and which MOSFET is the FW MOSFET (Figure 10).

•

If VSHx > V_SHH: The high-side MOSFET is the FW MOSFET and the low-side MOSFET is the active MOSFET

If VSHx < V_SHL: Then the low-side MOSFET is the FW MOSFET and the high-side MOSFET is the active MOSFET

If V_SHL< VSHx < V_SHH: No clear distinction between the FW MOSFET and the active MOSFET. The MOSFET to

be turned on is considered as the active MOSFET.

HS and LS off

Freewheeling through

high-side MOSFET body diode

VSHx > VS – V_SHH

HS and LS are off

Freewheeling through

low-side MOSFET body diode

VSHx < V_SHL

HS = FW MOSFET

LS = Active MOSFET

LS = FW MOSFET

HS = Active MOSFET

CP

DH or

CSIN1

DH or

CSIN1

GHx

Highside

Gate-Driver

SHx

VSHH

High-Speed

Comparators

High-Speed

Comparators

VSHL

VCP

GLx

Lowside

Gate-Driver

SL

Figure 10 Detection principle of the active and freewheeling MOSFET

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Multiple MOSFET Driver IC

Floating gate drivers

Note:

The PWM signal is applied to the MOSFET selected by HBxMODE[1:0], independently from the free-

wheeling and the active MOSFET.

It is not possible to determine the active or FW MOSFET if the PWM on-time is shorter than tHBxCCP

FW, or if the PWM-off-time is shorter than tHBxCCP Active (Refer to Chapter 6.3.5). In this case, the

PWM MOSFET is considered as the active MOSFET. In other words, it is assumed that the motor

operates as load.

Figure 11, Figure 12 show examples of free-wheeling and active MOSFET when the motor operates as load.

VS

PWM

HS1

Active

MOSFET

Time

VOUT1

VOUT2

HS2 OFF

PWM

Time

AFW

OUT1

OUT2

M

LS1: FW

MOSFET

LS2 ON

AFW: Active Free-wheeling

LS1 ON

Current Flow PWM = High

Current Flow PWM = Low

Figure 11 Active freewheeling on HB1: PWM1EN = 1. PWM applied to HS1 (HB1MODE[1:0] = 10_B).

The motor operates as load: HS1 is the active MOSFET, LS1 is the FW MOSFET.

VS

PWM

Time

HS2

FW MOSFET

VOUT2

AFW

AFW AFW

HS1 ON

LS1 OFF

Time

VOUT1

M

OUT1

OUT2

LS2

Active MOSFET

PWM

AFW: Active Free-wheeling

HS2 ON

Current Flow PWM = High

Current Flow PWM = Low

Figure 12 Active freewheeling on HB2: PWM1EN = 1. PWM applied to LS2 (HB2MODE[1:0] = 01_B).

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Multiple MOSFET Driver IC

Floating gate drivers

The motor operates as load: LS2 is the active MOSFET, HS2 is the FW MOSFET.

Figure 13 and Figure 14 show examples of free-wheeling and active MOSFET when the motor operates as

generator.

VS

PWM

HS1: FW

MOSFET

Time

VOUT1

VOUT2

HS2 OFF

PWM

AFW

Time

OUT1

OUT2

M

LS1: Active

MOSFET

LS2 ON

AFW: Active Free-wheeling

HS1 ON

Current Flow PWM = High

Current Flow PWM = Low

Figure 13 Active freewheeling on HB1: PWM1EN = 1. PWM applied to HS1 (HB1MODE[1:0] =

10_B).The motor operates as generator: LS1 is the active MOSFET, HS1 is the FW MOSFET.

VS

PWM

Time

HS2

Active MOSFET

VOUT2

HS1 ON

LS1 OFF

AFW

AFW AFW

Time

VOUT1

M

OUT1

OUT2

LS2

FW MOSFET

PWM

Current Flow PWM = High

Current Flow PWM = Low

AFW: Active Free-wheeling

LS2 ON

Figure 14 Active freewheeling on HB2: PWM1EN = 1. PWM applied to LS2 (HB2MODE[1:0] = 01_B).

The motor operates as generator: HS2 is the active MOSFET, LS2 is the FW MOSFET.

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Multiple MOSFET Driver IC

Floating gate drivers

6.3.2

Configuration in PWM mode

The following sections describe the different control schemes in PWM mode. They differ during the pre-charge

and pre-discharge phases (Figure 15):

•

Adaptive gate control (AGC[1:0] = (1,0) or (1,1), GENCTRL2): in this mode a pre-charge current and a pre-

discharge current are applied to the gate of the PWM MOSFET. These currents are used to regulate the

effective turn-on and turn-off delays to the respective target values. Refer to Chapter 6.3.3.

•

No adaptive gate control (AGC[1;0] = (0,0)): in this mode, the pre-charge and pre-discharge phases are

deactivated. Refer to Chapter 6.3.4.1.

No adaptive gate control (AGC[1;0] = (0,1)). In this mode:

–

the pre-charge phase is deactivated

during the pre-discharge phase, the gate of the PWM MOSFET mapped to the PWM channel x, x = 1…3,

is discharged with the configured current IPCHGINIT (Refer to PWM_PCHG_INIT and Chapter 6.3.4.2)

Synchronized

PWMz

t

IGS

PWM MOSFET

Precharge

Post-charge

tPCHGx

Predischarge

ICHGMAXx

IPRECHGx

tPDCHGx

ICHGx

0

t

tHBxCPP

- IDCHGx

tBLANK for PWM MOSFET

Cross-current

protection

Symmetrization

- IPREDCHGx

tHBxCPP

delay

tHBxCPP for symmetry

PWM_Control_Scheme_Overview_AFW.emf

Figure 15 PWM overview showing pre-charge, pre-discharge and post charge phases, AGC[1:0] = 10_B

or 11_B, POCHGDIS = 1_B.

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6.3.3

PWM operation with adaptive gate control

This section describes the MOSFETs control during high-side or low-side PWM operation when the adaptive

gate control is enabled (AGC[1:0] = (1,0) or (1,1), GENCTRL2).

Note:

Unless otherwise specified, the description of the regulation of the pre-charge and pre-discharge

currents are applicable for

Refer to Chapter 6.3.1 for the definition of the active and of the freewheeling MOSFET according to the setting

of AGC.

Assumption: a high-side or low-side MOSFET driver is mapped to the PWM channel z, z = 1,2 or 3.

Refer to Figure 16 for high-side PWM and Figure 19 for low-side PWM for the description of the switching

phase.

The TLE92108-232QX adapts the pre-charge current, respectively the pre-discharge current, in order to match

the effective turn-on delay (t_DON) and turn-off delay (t_DOFF) to the configured values.

The configured turn-on and turn-off delays of the respective PWM MOSFETs are set by the registers

TDON_OFF1, TDON_OFF2, TDON_OFF3.

The effective turn-on and turn-off delays of the respective active MOSFETs are read out from the status

registers EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3.

Table 12

Abbreviation

Suffix x

Abbreviations for adaptive turn-on and turn-off phases in PWM configuration

Definition

Related to the half-bridge x (x = 1 … 8)

Suffix z

Related to the PWM channel z (z = 1,2 or 3)

Gate-Source voltage of high-side MOSFET x

VGS_HSx

IGS_HSx

Gate current of high-side MOSFET x

IGS_HSx is positive when the current flows out of GHx.

VGS_LSx

IGS_LSx

Gate-Source voltage of low-side MOSFET x

Gate current of low-side MOSFET x

IGS_LSx is positive when the current flows out of GLx.

tHBxCCP ACTIVE

Active cross-current protection time of HBx. See control registers CCP_BLK1,

CCP_BLK2_ACT, PWM_ICHGMAX_CCP_BLK3_ACT and Chapter 7.5.

tHBxBLANK ACTIVE Active Drain-source overvoltage blank time of HBx. See control registers CCP_BLK1,

CCP_BLK2_ACT, PWM_ICHGMAX_CCP_BLK3_ACT and Chapter 7.5.

tHBxCCP FW

Freewheeling cross-current protection time of HBx. See control registers CCP_BLK1,

CCP_BLK2_FW, PWM_ICHGMAX_CCP_BLK3_FW and Chapter 7.5

tHBxBLANK FW

Freewheeling drain-source overvoltage blank time of HBx. See control registers

CCP_BLK1, CCP_BLK2_FW, PWM_ICHGMAX_CCP_BLK3_FW and Chapter 7.5

PWMz

External PWM signal applied to the input pin PWMz.

ICHGMAXz

Maximum drive current of the half-bridge mapped to PWM channel z during the pre-

charge and pre-discharge phases. See control registers

PWM_ICHGMAX_CCP_BLK3_ACT and PWM_ICHGMAX_CCP_BLK3_FW

ICHGMAXz is also the drive current for the post-charge phase

IPRECHGz and IPREDCHGz are limited to ICHGMAXz.

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Multiple MOSFET Driver IC

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Table 12

Abbreviations for adaptive turn-on and turn-off phases in PWM configuration

Abbreviation

IPRECHGz

Definition

Pre-charge current sourced by the gate driver mapped to the PWM channel z during

tPCHGz.

Internal and self-adaptive parameter (if AGC = (1,0) or (1,1), GENCTRL2)

IPRECHGz is clamped between I_CHG0and ICHGMAXz.

IPCHGINITz

IPREDCHGz

Initial value of IPRECHGz. Refer to PWM_PCHG_INIT

Pre-discharge-current sunk by the gate driver mapped to the PWM channel z during

tPDCHGz.

Internal and self-adaptive parameter. (AGC = (1,0) or (1,1), GENCTRL2)

IPREDCHGz is clamped between I_DCHG0and IDCHGMAXz.

IPDCHGINITz

ICHGz

Initial value of IPREDCHGz. Refer to PWM_PDCHG_INIT

Current sourced by the gate driver mapped to the PWM channel z during the charge

phase. See control register PWM_ICHG_ACT.

IDCHGz

ICHGFWz

tPCHGz

Current sunk by the gate driver mapped to the PWM channel z during the discharge

phase. See control register PWM_IDCHG_ACT.

Current source or sunk by the gate driver to turn on / turn off the freewheeling MOSFET

of the half-bridge mapped to the PWM channel z. See PWM_ICHG_ACT.

Duration of the pre-charge phase of PWM channel z.

tPCHGz is configurable by SPI. See control register TPRECHG, configuration bits

TPCHGz[1:0].

tPDCHGz

tDONz

Duration of the pre-discharge phase of PWM channel z.

tPDCHGz is configurable by SPI. See control register TPRECHG, configuration bits

TPDCHGz[1:0].

Turn-on delay of the PWM MOSFET mapped to the PWM channel z:

•

for high-side PWM: time between the end of the cross-current protection and when

VSHx increases to V_SHL(Figure 17).

•

for low-side PWM: time between the end of the cross-current protection and when

VSHx decreases to V_SHH

.

tDOFFz

Turn-off delay of the PWM MOSFET mapped to the PWM channel z:

•

for high-side PWM: time between the end of the symmetrization delay (t_HBxCCP) and

when VSHx decreases to VSHH (Figure 18).

for low-side PWM: time between the end of the symmetrization delay (t_HBxCCP) and

when VSHx increases to VSHL.

IHOLD

Hold current sourced or sunk by the gate driver to keep the MOSFET in the desired

state. See IHOLD control bit in GENCTRL2.

IHARDOFF

TFVDS

IHARDOFF is the maximum current that the gate drivers can sink. It corresponds to the

discharge current when IDCHGx[4:0] = 31_D(100 mA typ.).

Drain-Source overvoltage filter time. See GENCTRL2.

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Multiple MOSFET Driver IC

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6.3.3.1 High-side PWM with adaptive gate control, motor operating as load

The following section describes the MOSFET control when the PWM signal is applied to the high-side MOSFET

of one half-bridge while the motor operates .

Assumption: the PWM channel z, z = 1,2 or 3, is applied to the high-side MOSFET of the half-bridge x, x = 1 … 8.

Current Flow PWMz = High

VS

Current Flow PWMz = Low

HSx: Active

MOSFET

IDS_HSx

HSx

IGS_HSx

HSy OFF

PWMz

VGS_HSx

SHx

SHy

M

LSx: FW

MOSFET

LSx

IGS_LSx

LSy ON

VGS_LSx

Figure 16 PWM channel z is mapped to high-side x, motor operating as load

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External

PWMz

Synchronized

intern. PWMz

t

tPWM_SYNCH

Charge

phase

Postcharge Phase

IGS_HSx

tPCHGx

ICHGMAXx

IPRECHGx

ICHGx

0

t

tHBxBLANK Active

tHBxCCP FW

HSx internal

drive signal

tFVDS

ICHGMAXx

IPRECHGx

IHOLD

ICHGx

t

0

-

IHOLD

VGS_HSx

t

tRISEx

VSHx

VS

VSHH

tDONx

VSHL

IDS_HSDx

IMOTOR

t

IGS_LSx

-

ICHGFWx

LSx internal

drive signal

IHOLD

tFVDS

t

-

IHOLD

-

IHOLD

-

ICHGFWx

Hard off

-

IHARDOFF

Figure 17 Adaptive turn-on, high-side PWM, AGC[1:0] = (1,0) or (1,1), motor operating as load

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Adaptive turn-on during high-side PWM

The turn-on of the high-side MOSFET is done in four phases (Refer to Figure 17):

1. Cross-current protection phase: The cross-current protection tHBxCCP FW starts at the rising edge of the

internal PWMz signal¹⁾. During tHBxCCP FW, the low-side MOSFET x is turned off with the discharge current

- ICHGFWx, while the high-side MOSFET x is kept off. .

2. Pre-charge: Once tHBxCCP FW has elapsed, the gate of the high-side MOSFET x is pre-charged with the

current IPRECHGz for a duration tPCHGz. IPRECHGz²⁾is an internal parameter, which is self-adaptive (see

next phase).

3. Charge: After tPCHGz, the charge current is decreased from IPRECHGz down to ICHGz. The effective

tDONz³⁾is measured and compared to the configured tDONz for the automatic adaptation of IPRECHGz

(see Adaptive control of pre-charge current). The charge phase ends up when V_SHxreaches V_SHH

.

4. Post-charge: After the charge phase, the control signal for the charge current of HSx is increased by one

current step every 62.5 ns typ. to ICHGMAXx.

Note:

The postcharge phase is deactivated by setting POCHGDIS to 1. Refer to GENCTRL2.

Adaptive control of pre-charge current

Refer to Chapter 6.3.6 for information on the pre-discharge currents.

The pre-charge current IPRECHGz is a self-adaptive parameter if AGC[1:0] = (1,0) or (1,1) (see GENCTRL2). It is

applied during tPCHGz (see TPRECHG). The TLE92108-232QX adapts IPRECHGz to match the effective tDONz

to the configured value.

IPRECHGz is clamped between I_CHG0(1 mA typ.) and ICHGMAXz (see PWM_ICHGMAX_CCP_BLK3_ACT).

IPRECHGz is initialized to min(IPCHGINITz, ICHGMAXz) (refer to PWM_PCHG_INIT) when the TLE92108-232QX

receives an SPI command setting PWMz_EN to 1 (see PWMSET).

The following adaptive schemes can be selected:

AGCFILT = 0 (GENCTRL2): No filter is applied

•

If the effective tDONz is longer than the configured tDONz, then IPRECHGz is increased during the next pre-

charge phase.

If the effective tDONz is shorter than the configured tDONz, then IPRECHGz is decreased during the next

pre-charge phase.

The pre-charge current is increased or decreased by one, respectively by two current steps (Chapter 6.3.6)

if the control bit IPCHGADT in the control register GENCTRL1 is set to 0 respectively 1.

AGCFILT = 1: The filter is applied

•

If the effective tDONz of the last two PWM cycles are longer than the configured tDONz, then IPRECHGz is

increased during the next pre-charge phase.

1) The external PWMz signal is synchronized with the internal device clock, resulting in the delay t_{PWM_SYNCH}between the internal and

the external PWMz signals.

2) IPRECHGz is clamped between ICHGMAXz and I_CHG0

.

3) The effective tDON can be read out. Refer to EFF_TDON_OFF1,EFF_TDON_OFF2, EFF_TDON_OFF3

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•

If the effective tDONz of the last two PWM cycles are shorter than the configured tDONz, then IPRECHGz

is decreased during the next pre-charge phase.

The pre-charge current is increased or decreased by one, respectively by two current steps (Chapter 6.3.6)

if the control bit IPCHGADT in the control register GENCTRL1 is set to 0 respectively 1.

If none of the two cases are applicable, then IPRECHGz is unchanged during the next pre-charge phase.

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External

PWMz

t

tPWM_SYNCH

Synchronized

intern. PWMz

IGS_HSx

Discharge phase

tPDCHGx

t

0

- IDCHGx

- IPREDCHGx

tHBxCCP FW for

symmetrisation

tHBxCCP Active for cross current

protection

HSx internal

drive signal

IHOLD

0

t

-

IHOLD

- IDCHGx

- IHOLD

- IDCHGx

- IPREDCHGx

Hard off

-

IHARDOFF

tFVDS

VGS_HSx

t

tFALLx

VSHx

tDOFFx

VS

VSHH

VSHL

IDS_HSDx

IMOTOR

t

IGS_LSx

ICHGFWx

tHBxBLANK FW

LSx internal

drive signal

tFVDS

ICHGFWx

IHOLD

t

-

IHOLD

Figure 18 Adaptive turn-off, high-side PWM, AGC[1:0] = (1,0) or (1,1), motor operating as load

Adaptive turn-off during high-side PWM

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The turn-off of the high-side MOSFET is done in four phases (Refer to Figure 18):

1. Turn-off delay time for symmetrization of the PWM signal: The turn-off of HSx is delayed by tHBxCCP FW

after the falling edge of the internal PWMz signal¹⁾, in order to compensate the distortion caused by the

cross-current protection time at turn-on.

2. Pre-discharge: once tHBxCCP FW for symmetrization has elapsed, the gate of the high-side MOSFET x is

pre-discharged with the current - IPREDCHGz for a duration tDPCHGz. IPREDCHGz is a device internal

parameter, which is self-adaptive (See next phase).

3. Discharge: After tPREDCHGz, the pre-discharge current is decreased in absolute value from IPREDCHGz²⁾

down to IDCHGz. The effective tDOFF³⁾is measured and compared to the configured tDOFFz for the

automatic adaptation of IPREDCHGz (see Adaptive control of pre-discharge current). The discharge

phase ends up at expiration of tHBxCCP active for cross-current protection.

4. Cross-current protection phase: The cross-current protection is concurrent to the pre-discharge and

discharge of the high-side MOSFET. The cross-current protection phase starts when the turn-off delay for

symmetrization ends up. It has the duration tHBxCCP active. During tHBxCCP active, the low-side

MOSFETx is kept OFF. When tHBxCCP active has elapsed, the gate of the low-side MOSFET x is charged with

the current ICHGFWz until the end of tFVDS, provided that V_SHx< V_SHL

.

Adaptive control of pre-discharge current

Refer to Chapter 6.3.6 for information on the pre-discharge currents.

The pre-discharge current IPREDCHGz is a self-adaptive parameter if AGC[1:0] = (1,0) or (1,1) (see GENCTRL2).

The TLE92108-232QX adapts the IPREDCHGz to match the measured t_DOFFzto the configured value.

IPREDCHGz is clamped between I_DCHG0(1 mA typ.) and ICHGMAXz (see PWM_ICHGMAX_CCP_BLK3_ACT).

IPREDCHGz is initialized to min(IPDCHGINITz, ICHGMAXz) (refer to PWM_PDCHG_INIT) when the TLE92108-

232QX receives a SPI command setting PWMz_EN to 1 (see PWMSET)

The pre-discharge current is increased or decreased by one, respectively by two current steps (Chapter 6.3.6)

if the control bit IPCHGADT in the control register GENCTRL1 is set to 0 respectively 1.

The following adaptive schemes can be selected:

AGCFILT = 0 (GENCTRL2): No filter is applied

•

If the effective tDOFFz is longer than the configured tDOFFz, then IPREDCHGz is increased during the next

pre-discharge phase

If the effective tDOFFz is shorter than the configured tDOFFz, then IPREDCHGz is decreased during the next

pre-discharge phase

The pre-charge current is increased or decreased by one, respectively by two current steps (Chapter 6.3.6)

if the control bit IPCHGADT in the control register GENCTRL1 is set to 0 respectively 1.

AGCFILT = 1: The filter is applied

1) The external PWMz signal is synchronized with the internal device clock, resulting in the delay t_{PWM_SYNCH}between the internal and

the external PWMz signals.

2) IPREDCHGz is clamped between ICHGMAXz and I_DCHG0

.

3) The effective tDOFF can be read out. Refer to EFF_TDON_OFF1,EFF_TDON_OFF2, EFF_TDON_OFF3.

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•

If the effective tDOFFz of the last two PWM cycles are longer than the configured tDOFFz, then IPREDCHGz

is increased during the next pre-charge phase.

If the effective tDOFFz of the last two PWM cycles are shorter than the configured tDOFFz, then

IPREDCHGz is decreased during the next pre-charge phase.

•

If none of the two cases are applicable, then IPRECHGz is unchanged during the next pre-charge phase.

The pre-charge current is increased or decreased by one, respectively by two current steps if the control

bit IPCHGADT is set to 0 respectively 1.

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6.3.3.2 Low-side PWM with adaptive gate control, motor operating as load

The following section describes the MOSFET control when the PWM signal is applied to the low-side MOSFET

of one half-bridge.

Assumption: the PWM channel z, z = 1,2 or 3, is applied to the low-side MOSFET of the half-bridge x, x = 1 … 8

(Figure 19).

Current Flow PWM = High

VS

Current Flow PWM = Low

HSx: FW MOSFET

IGS_HSx

HSy ON

VGS_HSx

SHy

SHx

M

LSx: Active MOSFET

IDS_LSx

LSx

IGS_LSx

LSy OFF

PWMz

VGS_LSx

Figure 19 PWM Channel z is mapped to low-side x, motor operating as load

The description of the control of the PWM half-bridge differs from the description of Chapter 6.3.3.1 only by

exchanging high-side x and low-side x and the thresholds V_SHHand V_SHL

.

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6.3.3.3 High-side PWM with adaptive gate control, motor operating as generator

The control scheme during high-side PWM in generator mode (refer to Figure 20) is equivalent to low-side

MOSFET in load mode with the complementary signal of the external PWM input.

The turn-on, turn-off delay times and the rise and fall times are applied and measured for the active MOSFET.

Current Flow PWMz = High

Current Flow PWMz = Low

VS

HSx: FW

MOSFET

IDS_HSx

HSx

PWMz

IGS_HSx

HSy OFF

VGS_HSx

SHx

SHy

M

LSx: Active

MOSFET

LSx

IGS_LSx

LSy ON

VGS_LSx

Figure 20 PWM input z is mapped to high-side x, the motor operating as generator

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External

PWMz

t

tPWM_SYNCH

Synchronized

intern. PWMz

IGS_LSx

Discharge phase

tPDCHGx

t

0

- IDCHGx

- IPREDCHGx

tHBxCCP FW for

symmetrisation

tHBxCCP Active for cross current

protection

LSx internal

drive signal

IHOLD

0

t

-

IHOLD

- IDCHGx

- IHOLD

- IDCHGx

- IPREDCHGx

Hard off

-

IHARDOFF

tFVDS

VGS_LSx

t

VSHx

tDOFFx tFALLx

VS

VSHH

VSHL

t

IDS_LSDx

- IMOTOR

IGS_HSx

ICHGFWx

t

tHBxBLANK FW

HSx internal

drive signal

tFVDS

ICHGFWx

IHOLD

t

-

IHOLD

Figure 21 Adaptive turn-on, high-side PWM, AGC[1:0] = (1,0) or (1,1), motor operating as generator

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6.3.3.4 Low-side PWM with adaptive gate control, motor operating as generator

The control scheme during high-side PWM in generator mode (refer to Figure 20) is equivalent to low-side

PWM in load mode with the complementary signal of the external PWM input.

The turn-on, turn-off delay times and the rise and fall times are applied and measured for the active MOSFET.

Current Flow PWM = High

VS

Current Flow PWM = Low

HSx: Active MOSFET

IGS_HSx

HSy ON

VGS_HSx

SHy

SHx

M

LSx: FW MOSFET

IDS_LSx

LSx

IGS_LSx

LSy OFF

PWMz

VGS_LSx

Figure 22 PWM input z is mapped to low-side x, the motor operating as generator

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Multiple MOSFET Driver IC

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External

PWMz

Synchronized

intern. PWMz

t

tPWM_SYNCH

Charge

phase

Postcharge Phase

IGS_LSx

tPCHGx

ICHGMAXx

IPRECHGx

ICHGx

0

t

tHBxBLANK Active

tHBxCCP FW

LSx internal

drive signal

tFVDS

ICHGMAXx

IPRECHGx

IHOLD

ICHGx

t

0

-

IHOLD

VGS_LSx

VSHx

t

tRISEx

VSHH

VS

VSHH

tDONx

VSHL

IDS_LSDx

t

- IMOTOR

IGS_HSx

-

ICHGFWx

HSx internal

drive signal

tFVDS

IHOLD

t

-

IHOLD

-

IHOLD

-

ICHGFWx

Hard off

-

IHARDOFF

Figure 23 Adaptive turn-off with high-side PWM, AGC[1:0] = (1,0) or (1,1), motor operating as

generator

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6.3.3.5 Status bits for regulation of turn-on and turn-off delay times

The control bits TDREGx (GENSTAT) indicate if tDONx and tDOFFx of the PWM channel x using the adaptive

gate control scheme (AGC[1:0] = 10_Bor 11_B) is in regulation.

The PWM channel is considered in regulation if one of the following conditions are met:

•

the effective turn-on and turn-off delays are equal to the configured delays for at least eight consecutive

PWM cycles

•

the error between the effective and configured delay changes its sign at least three times during the last

8 PWM cycles

6.3.3.6 Precharge and predischarge phases with EN_DEEP_AD = 1

This section is valid if EN_DEEP_AD = 1. Enabling this feature leads to a lower granularity of the resulting

precharge and and predischarge currents.

This principle is illustrated with an example during the precharge phase on Figure 24. The same principle is

applied to the predischarge phase.

If EN_DEEP_AD = 1:

•

The precharge phase can be divided in two parts, during which different precharge current steps are

applied

•

The predischarge phase can be divided in two parts, during which different predischarge current steps are

applied

The device exits the “deep adaptation mode” if t_DON, respectively t_DOFF, cannot be regulated and the resolution

of the precharge time cannot be further divided. Then, one single current step is applied during the precharge

time (Figure 25).

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TDON adaptation

with two current

steps (IPCHGADT =

1)

Current i+2

No

3 consecutive sign changes of (TDON

EFF- TDON TARGET) or No error for 3

consecutive PWM cycles

Current i

Yes

tPCHG

TDON adaptation

with one current step

i+1

i

No: TDON EFF =

TDON TARGET

3 consecutive sign changes

of (TDON EFF- TDON

TARGET)

tPCHG

Yes

i+1

i

Precharge phase splitted in 2

sub-phases

50% 50%

tPCHG

Yes

TDON EFF = TDON

TARGET

No

Precharge splitted:

75%-25% if TDON EFF > TDON TARGET

25%-75% if TDON EFF < TDON TARGET

i+1

i

i+1

i

or

25%

75%

tPCHG

25%

tPCHG

Yes

TDON EFF = TDON

TARGET

No

Precharge splitted:

E.g 87.5%-12.5%

Etc...

Figure 24 Example of precharge current modulation during the precharge phase, EN_DEEP_AD = 1

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tPCHG = 250 ns

TDON adaptation

with two current

steps (IPCHGADT =

1)

Current i+2

No

3 consecutive sign changes of (TDON

EFF- TDON TARGET) or No error for 3

consecutive PWM cycles

Current i

Yes

tPCHG

TDON adaptation

with one current step

i+1

i

No

3 consecutive sign changes

of (TDON EFF- TDON

TARGET)

tPCHG

Yes

Time modulation entered

Precharge phase splitted in 2

sub-phases

i+1

i

50% 50%

tPCHG

Yes

TDON EFF = TDON

TARGET

No

Precharge splitted:

75%-25% if TDON EFF > TDON TARGET

25%-75% if TDON EFF < TDON TARGET

i+1

i

i+1

i

or

25%

75%

tPCHG

25%

Yes

tPCHG

No

TDON EFF = TDON TARGET

1) Exit time modulation: the resolution of

tPCHG cannot be further divided: one

single current is applied during tPCHG

Figure 25 Criteria to exit the time modulation, EN_DEEP_AD = 1

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Multiple MOSFET Driver IC

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6.3.4

PWM operation without adaptive gate control

The adaptive gate control is disabled if AGC[1:0] is set to (0,0) or (0,1). The effective turn-on and turn -off delays

of the PWM MOSFETs are not regulated. Two modes can be selected.

The target turn-on and turn-off delay times of PWM MOSFETs (configured in TDON_OFF1,

TDON_OFF2,TDON_OFF3) are no longer regulated. Nevertheless the status registers EFF_TDON_OFF1,

EFF_TDON_OFF2, EFF_TDON_OFF3 still report the effective turn-on and turn-off times of the PWM MOSFET.

6.3.4.1 PWM operation without adaptive gate control, AGC[1:0] = (0,0)

When AGC[1:0] = (0,0) (see GENCTRL2), the control of the gate drivers in PWM mode differs from the

description of Chapter 6.3.3, PWM operation with adaptive gate control, only by the suppression of the pre-

charge and pre-discharge phases.

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Multiple MOSFET Driver IC

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6.3.4.2 PWM operation without adaptive gate control, AGC[1:0] = (0,1)

When AGC[1:0] = (0,1) (see GENCTRL2), the control of the gate drivers in PWM mode differs from the

description of Chapter 6.3.4.1, PWM operation without adaptive gate control, AGC[1:0] = (0,0), only by the

addition of a pre-discharge phase. During tPDCHGz, the gate of the PWM MOSFET mapped to the PWM channel

z is discharged with the current -IPDCHGINITz (Refer to PWM_PDCHG_INIT).

Refer to Figure 26 for the turn-off of the PWM MOSFET with high-side PWM.

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Multiple MOSFET Driver IC

Floating gate drivers

PWMz

t

IGS_HSx

Discharge phase

tPDCHGz

t

0

- IDCHGz

- IPDCHGINITz

tHBxCCP for symmetrisation

tHBxCCP for cross current protection

HSx internal

drive signal

IHOLD

0

t

-

IHOLD

- IDCHGz

- IHOLD

- IDCHGz

- IPDCHGINITz

Hard off

-

IHARDOFF

tFVDS

VGS_HSx

t

tFALLz

VSHx

tDOFFz

VS

VSHH

VSHL

IDS_HSDx

IMOTOR

t

IGS_LSx

ICHGMAXz

tHBxBLANK

LSx internal

drive signal

tFVDS

ICHGMAXz

IHOLD

t

-

IHOLD

Figure 26 High-side PWM operation - turn-off without adaptive gate control, AGC[1:0] = (0,1)

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Multiple MOSFET Driver IC

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6.3.5

PWM operation at high and low duty cycles

This section describes the internal PWM signal of the active and FW MOSFET when the motor operates as load

or generator. In particular, at low and high duty cycles, the active free-wheeling is disabled.

Note:

It is recommended to clear EN_GEN_CHECK (EN_GEN_CHECK to 0) at very high and very low duty

cycles: tON > tHBxCCP FW and tOFF < tHBxCCP active. Under these conditions, a generator mode

cannot be correctly detected. The control scheme of the active MOSFET and of the freewheeling

MOSFET can therefore be inverted.

The device cannot measure the switching times tDON, tDOFF, tRISE and tFALL at very high and very

low duty cycles: tON > tHBxCCP FW and tOFF < tHBxCCP active.

General case, motor operating as load, tON > tHBxCCP FW and tOFF > tHBxCCP active

Figure 27 shows the internal control signals of the PWM MOSFETs and the freewheeling MOSFET while the

motor operates as load :

•

tON is longer than the FW cross-current protection time (tHBxCCP FW)

tOFF is longer than the active cross-current protection time (tHBxCCP Active)

tHBxCCP3

active

tHBxCCP2

FW (sym)

tHBxCCP1

FW

External PWMx signal

tON

time

Control signal for

Active MOSFET

Control signal for

free-wheeling MOSFET

time

Figure 27 Internal signals for PWM operation - General case tON > tHBxCCP FW, tOFF > tHBxCCP

active, motor operating as load

General case, motor operating as generator, tOFF > tHBxCCP FW and tON > tHBxCCP active

Figure 28 shows the internal control signals of the PWM MOSFETs and the freewheeling MOSFET while the

motor operates as generator:

•

tOFF is longer than the FW cross-current protection time (tHBxCCP FW)

tON is longer than the active cross-current protection time (tHBxCCP Active)

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Multiple MOSFET Driver IC

Floating gate drivers

External PWMx

signal

tOFF

time

tHBxCCP3

active

tHBxCCP2

FW (sym)

tHBxCCP1

FW

Inverted ext.

PWMx signal

time

Control signal for

Active MOSFET

Control signal for

free-wheeling MOSFET

time

Figure 28 Internal signals for PWM operation - General case: tOFF > tHBxCCP FW, tON > tHBxCCP

active, motor operating as generator

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Multiple MOSFET Driver IC

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High duty cycle: tOFF < tHBxCCP active

No distinction between active MOSFET and FW MOSFET is possible, when the OFF-time of the external PWM

signal is shorter than the configured active cross-current protection time. Therefore the PWM MOSFET

(selected by HBxMODE[1:0]) is controlled as the active MOSFET. In other words, it is assumed that the motor

operates as load. The control signal of the PWM MOSFET is shifted by one FW cross-current protection time

compared to the external PWM signal. The MOSFET opposite to the PWM MOSFET stays OFF (passive FW). Refer

to Figure 29.

tHBxCCP2

FW (sym)

tHBxCCP1

FW

External PWMx signal

time

tOFF

Control signal for

PWM MOSFET

time

Control signal for

MOSFET opposite

to PWM MOSFET

time

Figure 29 Internal signals for PWM operation at high duty cycle, tOFF < tHBxCCP active

Low duty cycle: tON < tHBxCCP FW

No distinction between active MOSFET and FW MOSFET is possible, when the ON-time of the external PWM

signal is shorter than the configured FW cross-current protection time. Therefore the PWM MOSFET (selected

by HBxMODE[1:0]) is controlled as the active MOSFET. In other words, it is assumed that the motor operates

as load. The control signal of the PWM MOSFET is shifted by one cross-current protection time compared to

the external PWM signal. The MOSFET opposite to the PWM MOSFET stays off (passive FW). Refer to Figure 30.

tHBxCCP

FW2 (sym)

tHBxCCP

Active 3

tHBxCCP

FW 1

External PWMx signal

time

tON

Control signal for

PWM MOSFET

time

Control signal for

MOSFET opposite

time

to PWM MOSFET

Figure 30 Internal signals for PWM operation at low duty cycle, tON < tHBxCCP FW

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Multiple MOSFET Driver IC

Floating gate drivers

6.3.6

Gate driver current

Each gate driver is able to source and sink currents from 1.0 mA to 100 mA, with 32 steps according to

Figure 31 and Figure 32.

The charge and discharge currents of the active and the FW MOSFETs are configured separately by:

•

The REG_BANK bit (GENCTRL1)

The control registers PWM_ICHG_ACT, PWM_IDCHG_ACT, PWM_ICHG_FW

The charge current of the active MOSFETs are configured by PWM_ICHG_ACT (REG_BANK = 0)

The discharge current of the active MOSFETs are configured by PWM_IDCHG_ACT (REG_BANK = 0)

The charge and discharge current of the FW MOSFET are configured by PWM_ICHG_FW (REG_BANK = 1)

100

90

80

70

60

50

40

30

20

10

0

5

10

15

20

25

30

ICHGx[4:0]dec

Figure 31 Configurable charge currents in PWM operation

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Multiple MOSFET Driver IC

Floating gate drivers

Table 13

Charge currents in PWM operation

ICHGx[4:0], ICHGxFW[4:0],

IPCHGINITx[4:0]

Nom. charge current

[mA]¹⁾

Max. deviation to nominal

values [%]

00000_B

00001_B

00010_B

00011_B

00100_B

00101_B

00110_B

00111_B

01000_B

01001_B

01010_B

01011_B

01100_B

01101_B

01110_B

01111_B

10000_B

10001_B

10010_B

10011_B

10100_B

10101_B

10110_B

10111_B

11000_B

11001_B

11010_B

11011_B

11100_B

11101_B

11110_B

11111_B

1.0

+/- 60 %

+/- 38 %

+/- 28 %

+/- 25 %

1.5

2.0

3.2

4.5

6.3

8.0

10.3

12.5

15.1

17.8

20.8

23.9

27.0

30.0

33.5

37.1

40.7

44.3

48.3

52.3

56.2

60.1

64.2

68.3

72.5

76.8

81.4

86.0

91.0

96.0

100

1) V_S≥ 8V and V_GS≤ V_GS(ON)1if ICHGx/ICHGxFW ≤ 14_D, V_S≥ 8V and V_GS≤ V_GS(ON)2if ICHGx/ICHGxFW ≥ 15_D

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Multiple MOSFET Driver IC

Floating gate drivers

100

90

80

70

60

50

40

30

20

10

0

5

10

15

20

25

30

IDCHGx[4:0]dec

Figure 32 Configurable discharge currents in PWM operation

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Multiple MOSFET Driver IC

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Table 14

Discharge currents in PWM operation

IDCHGx[4:0], IDCHGxFW[4:0],

IPDCHGINITx[4:0]

Nom. charge current

[mA]¹⁾

Max. deviation to nominal

values [%]

00000_B

00001_B

00010_B

00011_B

00100_B

00101_B

00110_B

00111_B

01000_B

01001_B

01010_B

01011_B

01100_B

01101_B

01110_B

01111_B

10000_B

10001_B

10010_B

10011_B

10100_B

10101_B

10110_B

10111_B

11000_B

11001_B

11010_B

11011_B

11100_B

11101_B

11110_B

11111_B

1.0

+/- 60 %

+/- 38 %

+/- 28 %

+/- 25 %

1.9

2.8

4.3

5.7

7.5

9.4

11.8

14.2

17.0

19.7

22.9

26.0

29.0

32.0

35.8

39.5

43.1

46.8

50.8

54.7

58.6

62.5

66.6

70.6

74.6

78.5

82.8

87.0

91.0

95.0

100

1) V_GS≥ V_GS(OFF)1if IDCHGx ≤ 14_D, V_GS≥ V_GS(OFF)2if IDCHGxFW ≥ 15_D

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Multiple MOSFET Driver IC

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6.4

Passive discharge

Resistors (R_GGND) between the gate of GHx and GND, and between GLx and GND, ensure that the external

MOSFETs are turned off, when EN = Low or when V_DD< V_DDPOffR

.

During normal mode with BD_PASS bit reset (GENCTRL2) without failure causing the deactivation of the gate

drivers, these pull-down resistors are switched off. The MOSFET are actively kept off with the discharge

current IHOLD.

During normal mode with failure leading to the deactivation of the gate drivers (charge pump undervoltage,

VS undervoltage and overvoltage, thermal shutdown) or in fail safe mode, R_GGNDare activated, independently

from the setting of BD_PASS.

Gate driver power down

The gate driver is deactivated in normal mode with BD_PASS set to 1 and all HBxMODE[1:0]=00 or 11. The

current consumption of the VS input is reduced to I_{S_BD_PASS}and R_GGNDare activated.

6.5

Bridge driver in passive mode

The low-side MOSFETs LS1, LS2, LS3 and LS4 can be controlled when the bridge driver in the passive mode. All

the other MOSFETs kept off by the passive discharge.

The bridge driver is in passive mode:

•

If BD_PASS = 1 in normal mode and all HBxMODE[1:0]=00_Bor 11_B.

In sleep mode (EN = Low).

If V_DD< V_{DD POffR}

.

When the bridge driver is in passive mode, then the state of the low-side MOSFETs LS1-LS4 is configured by

PASS_MOD.¹⁾

•

If PASS_MOD[1:0] = 00_B: LS1, LS2, LS3 and LS4 are off (passive discharge).

If PASS_MOD[1:0] = 01_B: LS1, LS2, LS3 and LS4 are on (static brake).

If PASS_MOD[1:0] = 10_B: LS1, LS2, LS3 and LS4 are turned on if V_S> V_{SOV PASS OFF}(overvoltage brake). The

PWM3 pin is pulled down by an internal open drain (R_{PWM3_OD}).

•

If PASS_MOD[1:0] = 11_B: LS1, LS2, LS3 and LS4 are turned on if PWM1 = High and V_S> V_{SOV PASS OFF}

(overvoltage brake conditioned by PWM1). The PWM3 pin is pulled down by an internal open drain

(R_{PWM3_OD}).

LS1, LS2, LS3 and LS4 MOSFETs with an input capacitor up to 10 nF are turned on within t_{ON_BD_PASS}

.

The setting of LS1-LS4 according to PASS_MOD in sleep mode or if V_DD< V_{DD POffR}is valid only if V_Sstays above

_{SLEEP_SET}. If V_Sdrops below V_{SLEEP_SET}, then LS1-LS4 behave as if PASS_MOD = 10_B, the latter setting is kept

V

even after a V_Srecovery. Note that the quiescent current is changed accordingly.

1) If BD_PASS = 0, the setting by PASS_MOD[1:0] is effective only when EN= 0 or VDD < VDD POffR

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Multiple MOSFET Driver IC

Floating gate drivers

6.6

Electrical characteristics gate driver

The electrical characteristics related to the gate driver are valid for V_CP> V_S+ 8.5 V.

Table 15

Electrical characteristics: gate drivers

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C

V_CP> V_S+ 8.5 V, all voltages with respect to ground. Positive current flowing into pin except for I_GLxand I_GHx

(unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Comparators

SHx High Threshold

SHx Low Threshold

SHx comparator delay

MOSFET Driver Output

V_SHH

V_SHL

t_SHx

V_S- 2.5

–

5

V_S- 2.0

2.5

V

P_6.5.1

P_6.5.2

P_6.5.26

2

–

V

Referred to GND

1)

30

ns

High Level Output Voltage

GHx vs. SHx and GLx vs. SL,

CPSTGA= 0

V_GH1

10

–

12

V

V_S> 8 V

P_6.5.3

C_Load= 10 nF

I_CP= - 12 mA²⁾

High Level Output Voltage

GHx vs. SHx and GLx vs. SL,

CPSTGA= 0

V_GH3

7

–

V

V_S> 6.0 V

P_6.5.5

C_Load= 10 nF

I

_CP= - 6 mA²⁾

High Level Output Voltage

GHx vs. SHx and GLx vs. SL,

CPSTGA= 1

V_GH4

10

–

12

V

¹⁾V_S> 18 V,

P_6.5.6

C

_Load= 10 nF I_CP= -

12 mA²⁾

Charge current

Discharge current

I_CHG0

0.4

5.0

21.6

72

1.0

8.0

30.0

96

1.6

mA

ICHG = 0_D

P_6.5.30

P_6.5.31

P_6.5.33

P_6.5.35

P_6.5.36

P_6.5.37

P_6.5.39

C_Load= 10 nF

V_GS≤ V_GS(ON)1

I_CHG6

11.0

38.4

120

-0.4

-5.8

-23.0

ICHG = 6_D

C_Load= 10 nF

V

_GS≤ V_GS(ON)1

ICHG = 14_D

_Load= 10 nF

I_CHG14

I_CHG30

I_DCHG0

I_DCHG6

I_DCHG14

C

V_GS≤ V_GS(ON)1

ICHG = 30_D

C_Load= 10 nF

V

_GS≤ V_GS(ON)2

IDCHG = 0_D

_Load= 10 nF

_GS≥ V_GS(OFF)1

IDCHG = 6_D

_Load= 10 nF

-1.6

-13.0

-41.0

-1.0

-9.4

-32.0

C

V

C

V_GS≥ V_GS(OFF)1

IDCHG = 14_D

C_Load= 10 nF

V_GS≥ V_GS(OFF)1

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Multiple MOSFET Driver IC

Floating gate drivers

Table 15

Electrical characteristics: gate drivers (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C

V_CP> V_S+ 8.5 V, all voltages with respect to ground. Positive current flowing into pin except for I_GLxand I_GHx

(unless otherwise specified).

Parameter

Symbol

Values

Typ.

-95

Unit Note or

Test Condition

Number

Min.

Max.

Discharge current

I_DCHG30

-119

-71

mA

IDCHG = 30_D

_Load= 10 nF

P_6.5.41

C

V_GS≥ V_GS(OFF)2

1)

Passive discharge

resistancebetweenGHx/GLx

and GND

R_GGND

10

20

30

kΩ

P_6.5.11

1)

Resistor between SHx and R_SHGND

GND

10

–

20

22

30

40

kΩ

P_6.5.12

P_6.5.13

Low RDSON mode

R_ONCCP

Ω

V_S= 13.5 V

V_CP= V_S+ 14 V

I_CHG= I_DCHG= 31

(max)

Gate Drivers Dynamic Parameters

External MOSFET gate-to-

source voltage - ON

V_GS(ON)1

V_GS(ON)2

V_GS(OFF)1

V_GS(OFF)2

9

7

–

2

5

V

¹⁾V_S≥ 8V

ICHGx ≤ 14_D

¹⁾V_S≥ 8V

ICHGx ≥ 15_D

P_6.5.50

P_6.5.51

P_6.5.53

External MOSFET gate-to-

source voltage - ON

External MOSFET gate-to-

source voltage - OFF

¹⁾IDCHGx ≤ 14_D

External MOSFET gate-to-

source voltage - OFF

¹⁾IDCHGx ≥ 15_D

1)

PWM synchronization delay t_{PWM_SYNCH}50

–

150

300

600

1200

150

300

600

1200

ns

P_6.5.46

P_6.5.18

P_6.5.19

P_6.5.20

P_6.5.21

P_6.5.22

P_6.5.23

P_6.5.24

P_6.5.25

Pre-charge time

Pre-discharge time

t_PCHG00

t_PCHG01

t_PCHG10

t_PCHG11

t_DPCHG00

t_DPCHG01

100

200

400

800

100

200

400

800

125

250

500

1000

125

250

500

1000

¹⁾TPCHG = 00_B

¹⁾TPCHG = 01_B

¹⁾TPCHG = 10_B

¹⁾TPCHG = 11_B

¹⁾TDPCHG = 00_B

¹⁾TDPCHG = 01_B

¹⁾TDPCHG = 10_B

¹⁾TDPCHG = 11_B

1) Not subject to production test, specified by design.

2) ICHGx[4:0] = 11111_B(100 mA typ.)

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Multiple MOSFET Driver IC

Protections and diagnostics

7

Protections and diagnostics

7.1

Reverse polarity protection

The output of the charge pump (CP pin) can be used to supply an external n-channel MOSFET, building an

active reverse polarity protection. Refer to Figure 50.

7.2

Safe switch (optional)

The output of the charge pump (CP pin) can be used to supply an optional external n-channel MOSFET,

operating as safe switch. The safe switch can be actively turned off for example by the microcontroller or a

safety logic, in order to disconnect the MOSFET supply, independently from the TLE92108-232QX. Refer to

Figure 50.

7.3

Drain-source voltage monitoring with bridge driver in active mode

When EN =High and BD_PASS = 0 (bridge driver in active mode), voltage comparators monitor the activated

MOSFETs to protect the high-side MOSFETs and low-side MOSFETs against a short circuit respectively to

ground and to the battery during ON-state.

If a Drain-Source overvoltage is detected, the corresponding half-bridge is latched off.

If HBxD = 0, x =1..8 (VDS1 and VDS2): The half-bridge x is latched off if the voltage difference between DH and

VSHx exceeds the threshold voltage configured by VDS1, and VDS2 (see Table 16).

If HBxD = 1, x =1..8 (see VDS1 and VDS2): The half-bridge x is latched off if the voltage difference between CSIN1

and VSHx exceeds the threshold voltage configured by VDS1, and VDS2 (see Table 16).

Short circuits of low-side MOSFETs to VS are detected by monitoring the voltage difference between VSHx and

SL (see Table 16).

Table 16

HBxVDSTH¹⁾[2:0]

Drain-Source overvoltage threshold, EN = High, BD_PASS= 0

Drain-Source overvoltage threshold for HSx and LSx¹⁾(typical)

000_B

001_B

010_B

011_B

100_B

101_B

110_B

150 mV

200 mV (default)

250 mV

300 mV

400 mV

500 mV

600 mV

2 V

111_B

1) x = 1 … 8.

Attention: HBxVDSTH[2:0] = 111_B(2 V threshold) is dedicated for the diagnostic in off-state. It is highly

recommended to select another drain-source overvoltage threshold once the routine of the

diagnostic in off-state has been performed to avoid additional current consumption from VS

and from the charge pump.

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Multiple MOSFET Driver IC

Protections and diagnostics

The device reports a Drain-Source overvoltage error if both conditions are met:

•

After expiration of the blank time.

If the Drain-Source voltage monitoring exceeds the configured threshold for a duration longer than the

configured filter time (refer to Table 17 and GENCTRL2 TFVDS bits).

Note:

Exception with static activated MOSFETs when the short circuit is applied before the expiration of

the blank time: the MOSFETs are turned off after the blank time + 2 x t_FVDS

Table 17

TFVDS[1:0]

00_B

Drain-Source overvoltage filter time

Drain-Source overvoltage filter time (typical)

0.5 µs (default)

01_B

1 µs

2 µs

3 µs

10_B

11_B

If a short circuit is detected by the Drain-Source voltage monitoring:

•

The impacted half-bridge is latched off.

–

The discharge current is according to the settings of ST_ICHG, as if the MOSFET was previously

statically activated.

•

The corresponding bit in the status register DSOV is set.

The VDSE in Global Status Register Global status byte is set.

If a Drain-Source overvoltage is detected for one of the MOSFETs, then the status register DSOV must be

cleared in order to re-enable the faulty half-bridge.

7.4

Drain-source voltage monitoring with bridge driver in passive mode

LS1 to LS4 can be activated when the bridge driver is in passive mode (refer to Chapter 6.5).

A drain-source overvoltage monitoring of LS1, LS2, LS3 and LS4 MOSFETs is enabled if PASS_VDS is set.

The drain-source monitoring (VSHx - VSL, x = 1 to 4) is ignored for t_{BLK_BD_PASS}(blank time) after beginning of

the activation of LS1, LS2, LS3 and LS4 MOSFETs.

The drain-source monitoring filter time is t_{DSMON_FILT_BD_PASS}and the VDS threshold is V_{VDSMON_BD_PASS}(370 mV

typ).

If a drain-source overvoltage is detected, then:

•

The LS1, LS2, LS3 and LS4 MOSFETs are turned off.

PASS_VDSOV and the corresponding status bit in DSOV are set.

LS1-4 can be reactivated by clearing DSOV. Clearing DSOV also clears PASS_VDSOV.

7.5

Cross-current protection and drain-source overvoltage blank time

All gate drivers feature a cross-current protection time and a Drain-Source overvoltage blank times.

The cross-current protection avoids the simultaneous activation of the high-side and the low-side MOSFETs

of the same half-bridge.

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During the blank time, the drain-source overvoltage detection is disabled, to avoid a wrong fault detection

during the activation phase of a MOSFET.

Notes

1. The setting of the cross-current protection and of the blank times may be changed by the microcontroller only

if all PWMx_EN bits are reset, x = 1 … 3.

2. Changing the Drain-Source overvoltage of a half-bridge x (HBx) in on-state (HBxMODE[1:0]=(0,1) or (1,0)) may

result in a wrong VDS overvoltage detection on HBx. Therefore it is highly recommended to change this

threshold when HBxMODE[1:0]=(0,0) or (1,1).

7.5.1

Cross-current protection

Four pairs of cross-current protection and blank times ((tCCPx, tBLANKx), x = 1…4) can be mapped to each

half-bridge with the control register CCP_BLK1.

The cross-current protection time of the active MOSFET of the FW MOSFETs are set independently.

•

The cross-current protection times of the active MOSFETs are configured by the control bits TCCPx_ACT

(CCP_BLK2_ACT, PWM_ICHGMAX_CCP_BLK3_ACT) and CCP_BLK1

•

The cross-current protection times of the free-wheeling MOSFETs are configured by the control bits

TCCPx_FW (CCP_BLK2_FW, PWM_ICHGMAX_CCP_BLK3_FW) and CCP_BLK1

Table 18

Cross-current protection time

TCCPx_ACT[2:0],

Cross-current protection time tCCPx_ACT/tCCPx_FW, x = 1…4 (typical)

TCCPx_FW[2:0],x = 1…4

000_B

001_B

010_B

011_B

100_B

101_B

110_B

111_B

375 ns

625 ns

1 µs

1.5 µs

2 µs (default)

3 µs

4 µs

16 µs¹⁾

1) When applying a cross-current protection time of 16 µs to a half-bridge, the max. drive current used for this half-

bridge must be set below 30 mA to avoid an overheating of the gate driver.

7.5.2

Drain-source overvoltage blank time in bridge driver active mode

A configurable blank time (refer to Table 19) for the Drain-Source monitoring is applied at the turn-on of the

MOSFETs. During the blank time, a Drain-Source overvoltage error is masked.

The blank time of the active MOSFET of the FW MOSFETs are set independently:

•

The blank times of the active MOSFETs are configured by the control bits TBLANKx_ACT (CCP_BLK2_ACT,

PWM_ICHGMAX_CCP_BLK3_ACT) and CCP_BLK1

•

The blank times of the free-wheeling MOSFETs are configured by the control bits TBLANKx_FW

(CCP_BLK2_FW, PWM_ICHGMAX_CCP_BLK3_FW) and CCP_BLK1

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Half-bridges in PWM mode

If the detection of the generator mode is disabled (EN_GEN_CHECK = 0):

•

The blank time of the PWM MOSFET starts at the expiration of the cross-current protection time of the FW

MOSFET (tHBxCCP FW). Refer to Figure 33.

•

The blank time of the FW MOSFET starts after expiration of the cross-current protection time at turn-off of

the PWM MOSFET (tHBxCCP Active). Refer to Figure 33.

PWM

t

IGS_PWM

MOSFET

Post-charge

tPCHGz

ICHGMAXz

tPDCHGz

IPRECHGz

ICHGz

0

t

- IDCHGz

tBLANK for

PWM MOSFET

tHBxCPP

Active

- IPREDCHGz

tHBxCPP for

symmetrisation

tHBxCPP FW

IGS Freewheeling

MOSFET

ICHGFWz

t

tBLANK for

freewheeling MOSFET

-

ICHGFWz

Figure 33 Blank time for half-bridges in PWM oper^Ga^E
Nt^Ci^Ho^EC
Kn, detection of generator mode disabled

tBLANK PWM AGC

EN

0 emf

(EN_GEN_CHECK = 0)

If the detection of the generator mode is enabled (EN_GEN_CHECK = 1):

•

The blank time of the Active MOSFET starts at the expiration of the cross-current protection time of the FW

MOSFET (tHBxCCP FW). Refer to Figure 34 and Figure 35.

•

The blank time of the FW MOSFET starts after expiration of the cross-current protection time at turn-off of

the Active MOSFET (tHBxCCP Active). Refer to Figure 34 and Figure 35.

PWM

t

IGS_Active

MOSFET

Post-charge

tPCHGz

ICHGMAXz

tPDCHGz

IPRECHGz

ICHGz

0

t

- IDCHGz

tBLANK active for

PWM MOSFET

- IPREDCHGz

tHBxCPP FW for

symmetrisation

tHBxCPP FW

tHBxCPP Active

IGS Freewheeling

MOSFET

ICHGFWz

t

tBLANK for

freewheeling MOSFET

-

ICHGFWz

Figure 34 Blank time for half-bridges in PWM operation, detection of generator mode enabled

(EN_GEN_CHECK = 1), motor operating as load

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PWM

t

Inverted

PWM

t

IGS_Active

MOSFET

Post-charge

tPCHGz

ICHGMAXz

IPRECHGz

tPDCHGz

ICHGz

0

t

- IDCHGz

tBLANK for

Active MOSFET

- IPREDCHGz

tHBxCPP FW for

symmetrisation

tHBxCPP FW

tHBxCPP Active

IGS Freewheeling

MOSFET

ICHGFWz

t

tBLANK for

freewheeling MOSFET

-

ICHGFWz

Figure 35 Blank time for half-bridges in PWM operation, detection of generator mode enabled

(EN_GEN_CHECK = 1), motor operating as generator

For statically activated half-bridges, the blank time starts:

•

Case 1: At expiration of the active cross-current protection (Figure 7), if the opposite MOSFET was

previously activated.

•

Case 2: Right after the decoding of the SPI command to turn on a MOSFET, if the half-bridge was in high

impedance (Figure 8).

The blank times can be configured with the control registers CCP_BLK2_ACT and

PWM_ICHGMAX_CCP_BLK3_ACT

for

the

active

MOSFETs

and

CCP_BLK2_FW

and

PWM_ICHGMAX_CCP_BLK3_FW for the freewheeling MOSFETs.

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Table 19

Drain-source overvoltage blank time

TBLANKx[2:0], x = 1…4

Drain-Source overvoltage blank time tBLANKx, x = 1…4 (typical)

000_B

001_B

010_B

011_B

100_B

101_B

110_B

111_B

625 ns

1 µs

1.25 µs

1.5 µs

2 µs (default)

3 µs

4 µs

16 µs¹⁾

1) When applying a blank time of 16 µs to a half-bridge, the max. drive current used for this half-bridge must be set

below 30 mA , to avoid an overheating of the gate driver.

Note:

The blank time is implemented at every new activation of a MOSFET, including a recovery from VS

undervoltage, VS overvoltage.

7.5.3

Mapping of cross-current protection and blank times

One of the pairs of cross-current protection and blank times are mapped to each half-bridge according to

Table 20, by configuring the control register CCP_BLK1.

Table 20

Mapping of tCCP and tBLANK to the half-bridges

HBxCCPBLK[1:0], x =1..8

tCCP and tBLANK applied to HBx

(tCCP1,tBLANK1) are mapped to HBx¹⁾

(tCCP2,tBLANK2) are mapped to HBx

(tCCP3,tBLANK3) are mapped to HBx

(tCCP4,tBLANK4) are mapped to HBx

00_B

01_B

10_B

11_B

1) Example: (tHBxCCP, tHBxBLANK) = (tCCP1, tBLANK1), x = 1 … 4.

7.6

OFF-state diagnostic

In order to support the off-state diagnostic, the gate driver of each MOSFET provides pull-up (450 µA typ.) and

a pull-down currents (1250 µA typ.) at the SHx pins when the driver driver is active (BD_PASS = 0). Under these

conditions, the pull-up current sources are active.

Attention: The off-state diagnostic is possible only when the bridge driver is active (BD_PASS=0) and the

corresponding half-bridge is off (HBxMODE = 00b or 11b).

The pull-down current of each gate driver are activated by the control bits HBxIDIAG (HBIDIAG register).

During the off-state diagnostic routine performed by the microcontroller, the drain-source overvoltage

threshold of the relevant half-bridges must be set to 2 V nominal. Refer to Table 16. Once the routine is

finished, it is highly recommended to decrease the drain-source overvoltage threshold to a lower value,

avoiding additional current consumption from the VS input.

The following failures can be detected:

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•

MOSFET short circuit to GND.

MOSFET short circuit the battery.

Open load (disconnected motor).

The status of the output voltages VOUTx, with x = 1 … 8, can be read back with status bit HBxVOUT (register

HBVOUT_PWMERR) when the corresponding half-bridge is in off-state (HBxMODE[1:0] = 00 or 11).

Note:

HBxVOUT = 0 if the half-bridge x is not in off-state (HBxMODE[1:0] = (0,1) or (1,0)).

Refer to Application information, Chapter 10 for off-state diagnostic when the shunt resistor is in the motor

phase.

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7.7

Temperature monitoring

Temperature sensors are integrated in the device. The temperature monitoring circuit compares the

measured temperature to the warning and shutdown thresholds.

Temperature warning

If the temperature sensor reaches T_jW, then TW is set (see GENSTAT). This bit is latched and reset by clearing

GENSTAT if the thermal warning condition has disappeared. The outputs stages however remain activated.

Refer to Figure 36.

Temperature shutdown

If the temperature sensor reaches T_jSDall gate drivers are latched off, the charge pump is deactivated ; the

SUPE bit (Supply Error bit, see Global status byte), TSD (Thermal Shutdown bit) and CPUV (Charge Pump

Undervoltage) are set (see GENSTAT). All outputs remain deactivated until the temperature shutdown

condition has disappeared and GENSTAT is cleared. See Figure 36.

The discharge current is according to the settings of ST_ICHG, as if the MOSFET was previously statically

activated.

To resume normal functionality of the gate drivers (in the event the overtemperature condition disappears, or

to verify if the failure still exists) the microcontroller shall clear GENSTAT.

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T_j

T_jSD

T_jW

t

Gate Driver x

Gate drivers are switched off if

ON

T

_jSDis reached, can be reactivated

if TSD bit is cleared

High Z

no error

TW error bit

High

TW is latched, can be

cleared via SPI

Low

t

no error

TSD error bit

High

TSD is latched, can be

cleared via SPI

Low

t

no error

Figure 36 Overtemperature behavior

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7.8

V_Sovervoltage and undervoltage shutdown

The power supply rails V_Sand V_DDare monitored for supply fluctuations. The V_Ssupply is monitored for under-

and over-voltage conditions whereas the V_DDsupply is monitored for under-voltage conditions.

7.8.1

V_Sundervoltage

If V_Sdrops below V_{SUV OFF}, then all external MOSFETs are latched off, however, the logic information remains

intact and uncorrupted provided that V_DD> V_{DD POR}

.

SUPE (Supply Error bit, see Global status byte), VSUV and CPUV bits (see GENSTAT), are set and latched.

The VSUV bit is reset by clearing GENSTAT to re-enable the MOSFETs.

The VSUV bit is reset if the following conditions are fulfilled:

•

V_S> V_{SUV ON}(See Figure 37).

The TLE92108-232QX receives a clear command to GENSTAT.

7.8.2

V_Sovervoltage with bridge driver in active mode

If V_Srises above the switch-off voltage (V_{SOV OFF1}if VSOVTH= 0, V_{SOV OFF2}if VSOVTH= 1) all external MOSFETs are

latched off, and the charge pump is deactivated. SUPE bit (see Global status byte) , VSOV bit (V_Sover-voltage

bit, see GENSTAT), and CPUV bit are set and latched. If V_Sdecreases below V_{SOV ON},then the charge pump is

reactivated automatically. The VSOV bit must be reset to re-enable the MOSFETs.

The VSOV bit is reset if the following conditions are fulfilled:

•

V_S< V_{SOV ON}(See Figure 37).

The TLE92108-232QX receives a clear command to GENSTAT.

The discharge current is according to the settings of ST_ICHG, as if the MOSFET was previously statically

activated.

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V_S

V_{SOV HY}

V_{SOV OFF}

V_{SOV ON}

V_{SUV HY}

V_{SUV ON}

V_{SUV OFF}

t

SPI command:

Clear GENSTAT

SPI command

Clear GENSTAT

VSUV / SUPE error bit

VSOV / SUPE error bit

High

Lo w

High

Lo w

t

MOSFET

reactivated

MOSFET

reactivated

MOSFET

ON

OFF

t

Figure 37 Output behavior during Over- and Undervoltage V_Scondition

7.8.3

V_Sovervoltage with bridge driver in passive mode

When the bridge driver is in passive mode (refer to Chapter 6.5):

•

If PASS_MOD[1:0] = 10_B: LS1, LS2, LS3 and LS4 are turned on if VS > V_{SOV PASS OFF}(overvoltage brake). The

PWM3 pin is pulled down by an internal open drain (R_{PWM3_OD}).

•

If PASS_MOD[1:0] = 11_B: LS1, LS2, LS3 and LS4 are turned on if VS > V_{SOV PASS OFF}and PWM1 = High

(overvoltage brake conditioned upon PWM1). The PWM3 pin is pulled down by an internal open drain

(R_{PWM3_OD}).

7.8.4

V_DDundervoltage

If the V_DDlogic supply decreases below the undervoltage threshold, V_{DD POffR}, the SPI interface shall no longer

be functional. The digital block will be reset and the gate drivers are switched off.The undervoltage reset is

released once V_DDvoltage is above the undervoltage threshold, V_{DD POR}

.

7.8.5

Charge pump undervoltage

The voltage of the charge pump output (VCP) is monitored in order to ensure a correct control of the external

MOSFETs.

If VCP falls below the configured charge pump undervoltage threshold:

•

The external MOSFETs are actively discharged for the duration tHBxCCP with the current ICHGSTx, then

the gate drivers are turned off.

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•

CPUV (GENSTAT), SUPE bits (Global status byte) and the Global Error Flag (Chapter 8.2) are set and

latched.

The CPUV and SUPE bits are reset and the normal operation is resumed if GENSTAT is cleared, and VCP >

VCPUV.¹⁾

Notes

1. A charge pump undervoltage event is reported after a power-on reset, when the charge time of the capacitor

connected to VCP exceeds t_CPUV

.

2. The charge pump is is deactivated after a VS undervoltage, a VS overvoltage and a thermal shutdown,

causing a charge pump undervoltage condition. Consequently CPUV and SUPE bits are set together with

VSOV, VSUV or TSD bits (see GENSTAT).

7.9

Switching parameters of MOSFETs in PWM mode

The effective switching parameters of the active MOSFETs (EN_GEN_CHECK =1) or of the PWM MOSFET

(EN_GEN_CHECK =0) can be read out with dedicated status registers:

•

The turn-on and turn off delays, noted tDON and tDOFF, are reported by the status register

EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3.

•

The rise and fall times, noted tRISE and tFALL, are reported by the status register TRISE_FALL1,

TRISE_FALL2, TRISE_FALL3.

Refer to Chapter 6.3 for the definition of tDON, tDOFF, tRISE and tFALL.

If tHBxBLANK active has elapsed in motor mode, before the measurement of the effective tDON , the device

reports an effective tDON corresponding to tHBxBLANK active.

If tHBxCCP active has elapsed while EN_GEN_CHECK =0²⁾, before the measurement of the effective tDOFF, the

device reports an effective tDOFF corresponding to tHBxCCP active.

7.10

Timeout watchdog

An integrated timeout watchdog supervises the integrity of the communication with the microcontroller.

The watchdog period is programmable by the WDPER bit (refer to GENCTRL1).

After a Power-On Reset, the watchdog timer starts and the microcontroller must invert the logic value of the

WDTRIG bit of the control register GENCTRL1. The default value of WDTRIG is 0. A correct trigger of the

watchdog immediately resets the watchdog counter and starts the next cycle.

A watchdog failure is reported by the device if:

•

The watchdog trigger bit is not served within the watchdog period (watchdog timeout event). See

Figure 38³⁾.

•

The microcontroller writes the WDTRIG bit with the same value. In other words, if the WDTRIG value is 0

and the microcontroller re-writes WDTRIG to 0, or the WDTRIG is 1, and the microcontroller re-writes

WDTRIG to 1, then a watchdog error is reported.

1) Recovering from VS under/overoltage and thermal shutdown, CPUV bit can be cleared only after 64 µs

2) If EN_GEN_CHECK= 1 and tDOFF cannot be measured until the expiration of tHBxCCP, then the device considers that the motor

operate as as generator

3) WDMON[1:0] (GENSTAT) is not reset after a WD timeout when the WD period is configured to 50 ms

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If a watchdog failure is detected, then the FS bit (see Global Status Byte) is set and latched, and the control

registers are frozen to their default values. Consequently all external MOSFETs are actively turned off.

In order to resume normal operation, the microcontroller must: 1. clear GENSTAT. 2. Set WDTRIG to 1 within

the watchdog period, 3. Set WDTRIG to 0 within the watchdog period¹⁾.

The watchdog period is configurable by SPI to T_WDPER1or T_WDPER2(refer to WDPER).

Monitoring the watchdog timer

The status bits WDMON[1:0] report the relative position of the watchdog timer to the watchdog period. Refer

to Table 21 and Figure 38. This allows the detection of a potential latent failure associated to the watchdog

timer: the microcontroller can indeed verify that the watchdog timer is running.

Table 21

Monitoring of the watchdog timer

WDMON[1:0]

Position of the watchdog timer

00_B

01_B

10_B

11_B

watchdog timer is between [0%, 25%[ of the watchdog period

watchdog timer is between [25%, 50%[ of the watchdog period

watchdog timer is between [50%, 75%[ of the watchdog period

watchdog timer is between [75%, 100%[ of the watchdog period

WD Timer / WD Period

WD trigger

WD timeout

WD trigger

100%

75%

50%

25%

0%

t

00_B

01_B

00_B

01_B

10_B11_B

00_B

01_B

10_B

11_B

00_B

WDMON[1:0]

Figure 38 Example of watchdog monitoring and watchdog timeout

1) The exit sequence must be strictly followed to leave fail safe mode. If a SPI frame not belonging to the sequence is added (incl. a

read command), then the device stays in fail safe mode and the microcontroller must restart the complete sequence to enter

normal mode.

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Disabling the watchdog

The watchdog is enabled by default.

It is disabled only if the following SPI sequence is sent:

•

First frame: Set UNLOCK bit to ‘1’ (GENCTRL1). Note: UNLOCK is automatically reset to ‘0’ at the end of the

following frame.

•

Following frame: Set WDDIS bit to ‘1’ (GENCTRL2).

The watchdog is directly re-enabled by setting WDDIS to ‘0’.

7.11

Current sense amplifier

Two current sense amplifiers allow to monitor the motor currents. The differential input stage measures the

voltage drop across an external shunt resistor.

The input common mode range allows current sensing in high-side, in low-side configuration or in the motor

phase.

7.11.1

Unidirectional and bidirectional operation

The current sense amplifiers (CSA) can work either as unidirectional or bi-directional CSA. See CSD1 and CSD2.

Unidirectional operation CSDx = 0

In unidirectional operation, the CSAx, x = 1 or 2, is optimized to measure the current flowing through the

external shunt resistor when VCSIPx ≥ VCSINx.

VCSOx = V_{REF Unidir}+ (VCSIPx - VCSINx + V_OS) x G_DIFF, provided that VCSOx is in the linear range^{1) 2)}

.

Bidirectional operation CSDx = 1

In bidirectional operation, the CSAx, x = 1 or 2, measures the current flowing through the external shunt

resistor in both directions: VCSIPx ≥ VCSINx or VCSIPx ≤ VCSINx.

The output CSOx works at half-scale range: VCSOx = V_{REF Bidir}+ (VCSIPx - VCSINx + V_OS) x G_DIFFprovided that

VCSOx is in the linear range ²⁾.

When the current sense amplifiers are deactivated (VS undervoltage, VS overvoltage, CP undervoltage or

Overtemperature, or CSAx_OFF = 1), CSOx is pulled Low (between GND to 150 mV)

7.11.2

Gain configuration

The gain of the current sense amplifier is configurable by the configuration bits CSAGx bits. Refer to Table 22

and GENCTRL1.

Table 22

CSAGx[1:0]

00_B

Configuration of the current sense amplifier gain

Typical current sense amplifier gain G_DIFF

10 V/V

20 V/V

01_B

1) Valid if 0.5 V ≤ VCSOx ≤ VDD - 0.5 V.

2) VCSOx is clamped between VDD and GND.

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Table 22

CSAGx[1:0]

10_B

Configuration of the current sense amplifier gain

Typical current sense amplifier gain G_DIFF

40 V/V

80 V/V

11_B

7.11.3

High-side and low-side setting

The CSA can be used either in high-side configuration or in low-side configuration within the specified

common mode range.

The control bits CSA1L and CSA2L (HBIDIAG) optimize the VDD current consumption by informing the device

about the common mode voltage of the CSA inputs:

•

CSAxL must be set to 0 if the shunt is in low-side configuration (i.e. connected to GND or to an output with

an activated low-side).

•

CSAxL must be set to 1 if the shunt is in high-side configuration (i.e.connected to VS or to an output with an

activated high-side).

Notes

1. A proper information from the CSA output is not ensured if the external shunt resistor is in high-side

configuration while its CSAxL bit is set to 0.

2. The external shunt resistor may be in low-side configuration while its CSAxL bit is set to 1. The current

consumption from VDD is however higher than if CSAxL is set to 0.

7.11.4

Overcurrent detection

A comparator at CSOx detects overcurrent conditions. The overcurrent threshold is configurable with the

OCTHx bits. Refer to Table 23 for unidirectional operation and Table 24 for bidirectional operation.

Table 23

OCTHx[1:0]

00_B

Overcurrent detection thresholds in unidirectional operation (CSDx = 0)

Typical Overcurrent Detection Threshold

V_CSOx> V_DD/2

01_B

V_CSOx> V_DD/2+ V_DD/10

10_B

V_CSOx> V_DD/2+ 2 x V_DD/10

V_CSOx> V_DD/2+ 3 x V_DD/10

11_B

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CSOx unidirectional overcurrent detection threshold

VCSOx

VDD

OCTHx[1:0]

(1,1)

VDD / 2 + 3 x VDD / 10

VDD / 2 + 2 x VDD / 10

V_{OCTH4 Unidir}

V_{OCTH3 Unidir}

(1,0)

(0,1)

(0,0)

VDD / 2 + VDD / 10

VDD / 2

V_{OCTH2 Unidir}

V_{OCTH1 Unidir}

V_{REF Unidir}= VDD/5

0V

Figure 39 Overcurrent detection thresholds in unidirectional operation (CSDx = 0)

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Table 24

OCTHx[1:0]

00_B

Overcurrent detection thresholds in bidirectional operation (CSDx = 1)

Typical Overcurrent Detection Threshold

V_CSOx> V_DD/2 + 2 x V_DD/20 or V_CSOx< V_DD/2 -2 x V_DD/20

V_CSOx> V_DD/2 + 4 xV_DD/20 or V_CSOx< V_DD/2 - 4 x V_DD/20

V_CSOx> V_DD/2+ 5 xV_DD/20 or V_CSOx< V_DD/2 - 5 x V_DD/20

V_CSOx> V_DD/2+ 6 x V_DD/20 or V_CSOx< V_DD/2 - 6 x V_DD/20

01_B

10_B

11_B

VCSOx

VDD

CSOx bidirectional overcurrent detection threshold

OCTHx[1:0]

V_{OCTH4 BidirH}

V_{OCTH3 BidirH}

V_{OCTH2 BidirH}

VDD / 2 + 6 x VDD / 20

VDD / 2 + 5 x VDD / 20

VDD / 2 + 4 x VDD / 20

(1,1)

(1,0)

(0,1)

V_{OCTH1 BidirH}(0,0)

VDD / 2 + 2 x VDD / 20

V_{REF Bidir}= VDD /2

V_{OCTH1 BidirL}(0,0)

VDD / 2 - 2 x VDD / 20

V_{OCTH2 BidirL}

V_{OCTH3 BidirL}

V_{OCTH4 BidirL}

(0,1)

VDD / 2 - 4 x VDD / 20

VDD / 2 - 5 x VDD / 20

VDD / 2 - 6 x VDD / 20

(1,0)

(1,1)

0V

Figure 40 Overcurrent detection thresholds in bidirectional operation (CSDx = 1)

It is possible to program the device behavior when an overcurrent condition is detected:

•

OCEN bit = 0 (see GENCTRL1): the device only reports the overcurrent event (OC, OC1 or OC2 in GENSTAT

and Global Error Flag are set), without any change of the gate driver states

–

If the overcurrent condition is not present for more than t_FOC, then the overcurrent status bits are

automatically cleared by the device.

•

OCEN bit = 1 (see GENCTRL1): the device reports the overcurrent event (OC, OC1 or OC2 in GENSTAT and

Global Error Flag are set) and turns off all MOSFETs with their static discharge current.

–

The MOSFETs can be reactivated by clearing GENSTAT or by resetting the OCEN bit.

The overcurrent status bits are reset only if the overcurrent condition is no longer present and the

microcontroller clears GENSTAT.

The overcurrent filter time is configurable (refer to t_FOC) by the control bits OCxFILT(refer to HBIDIAG).

_FOCrefers to the output of the current sense amplifier. The CSO settling time (2 µs max, t_SET) and the analog

propagation delay (< 1 µs) are not taken into account by the overcurrent filter time.

t

7.11.5

CSO outputs capacitor

The capacitor directly connected to CSOx (CCSOx) must be between 10 pF and 400 pF (refer to Chapter 10).

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Multiple MOSFET Driver IC

Protections and diagnostics

The control bit CCSO (see PWM_IDCHG_ACT, PWM_PDCHG_INIT) optimizes the VDD current consumption for

CCSOx < 100 pF or CCSOx > 100 pF.

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Multiple MOSFET Driver IC

Protections and diagnostics

7.12

Electrical characteristics protections and diagnostics

The specified drain-source monitoring thresholds, the overcurrent thresholds and the electrical

characteristics related to the current sense amplifiers are valid for V_CP> V_S+ 8 V

Table 25

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C

_CP> V_S+ 8 V

All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Electrical characteristics:

V

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Watchdog

Watchdog period 1

Watchdog period 2

T_WDPER1

T_WDPER2

40

50

60

ms

¹⁾WDPER = 0

¹⁾WDPER = 1

P_7.11.52

P_7.11.53

160

200

240

Off-state Open load diagnosis

1)

Pull-up diagnosis current

I_PUDiag

-630

900

2.5

-450

1250

3.0

-270

1600

–

µA

P_7.11.1

P_7.11.2

P_7.11.77

Pull-down diagnosis current I_PDDiag

Diagnosis current ratio

I_{Diag_ratio}

Ratio

I_PDDiag/I_PUDiag

Drain source monitoring threshold

Drain-source monitoring

thresholds

V_VDSMONTH00.12

V_VDSMONTH10.16

V_VDSMONTH20.20

V_VDSMONTH30.24

V_VDSMONTH40.32

V_VDSMONTH50.40

V_VDSMONTH60.48

V_VDSMONTH71.6

0.15

0.20

0.25

0.30

0.40

0.50

0.60

2.0

0.18

0.24

0.30

0.36

0.48

0.62

0.72

2.4

V

HBxVDSTH[2:0] = P_7.11.3

000_B

Drain-source monitoring

thresholds

HBxVDSTH[2:0] = P_7.11.4

001_B

Drain-source monitoring

thresholds

HBxVDSTH[2:0] = P_7.11.5

010_B

Drain-source monitoring

thresholds

HBxVDSTH[2:0] = P_7.11.6

011_B

Drain-source monitoring

thresholds

HBxVDSTH[2:0] = P_7.11.7

100_B

Drain-source monitoring

thresholds

HBxVDSTH[2:0] = P_7.11.8

101_B

Drain-source monitoring

thresholds

HBxVDSTH[2:0] = P_7.11.9

110_B

Drain-source monitoring

thresholds

HBxVDSTH[2:0] = P_7.11.54

111_B

Drain-source monitoring blank time

DS monitoring blank time

t_{DSMON_BLK0}500

t_{DSMON_BLK1}0.8

t_{DSMON_BLK2}

625

1

850

1.2

1.5

ns

µs

TBLANKx[2:0] = P_7.11.10

000_B

1)

TBLANKx[2:0] = P_7.11.11

1)

001_B

1

1.25

TBLANKx[2:0] = P_7.11.12

1)

010_B

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Multiple MOSFET Driver IC

Protections and diagnostics

Table 25

Electrical characteristics: (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C

V_CP> V_S+ 8 V

All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

1.5

Unit Note or

Test Condition

Number

Min.

Max.

DS monitoring blank time

t_{DSMON_BLK3}1.2

t_{DSMON_BLK4}1.6

t_{DSMON_BLK5}2.4

t_{DSMON_BLK6}3.2

t_{DSMON_BLK7}12.8

1.8

µs

TBLANKx[2:0] = P_7.11.13

011_B

1)

2

2.4

3.6

TBLANKx[2:0] = P_7.11.57

1)

100_B

3

TBLANKx[2:0] = P_7.11.58

1)

101_B

4

4.8

TBLANKx[2:0] = P_7.11.59

1)

110_B

16

19.2

TBLANKx[2:0] = P_7.11.60

1)

111_B

Drain-source monitoring filter time

DS monitoring filter time

t_{DSMON_FILT0}0.4

0.5

1

0.85

1.4

2.4

3.6

µs

TFVDS[1:0] =

00_B

P_7.11.14

P_7.11.15

P_7.11.16

P_7.11.17

1)

t_{DSMON_FILT1}0.8

t_{DSMON_FILT2}1.6

t_{DSMON_FILT3}2.4

TFVDS[1:0] =

1)

01_B

2

TFVDS[1:0] =

1)

10_B

3

TFVDS[1:0] =

1)

11_B

Cross-current protection time

Cross current protection

time

t_HBxCCP0

300

500

0.8

1.2

1.6

2.4

3.2

12.8

375

625

1

450

750

1.2

1.8

2.4

3.6

4.8

19.2

ns

µs

THBxCCP[2:0] = P_7.11.18

000_B

1)

Cross current protection

time

t_HBxCCP1

t_HBxCCP2

t_HBxCCP3

t_HBxCCP4

t_HBxCCP5

t_HBxCCP6

t_HBxCCP7

THBxCCP[2:0] = P_7.11.19

1)

001_B

Cross current protection

time

THBxCCP[2:0] = P_7.11.20

1)

010_B

Cross current protection

time

1.5

2

THBxCCP[2:0] = P_7.11.21

1)

011_B

Cross current protection

time

THBxCCP[2:0] = P_7.11.22

1)

100_B

Cross current protection

time

3

THBxCCP[2:0] = P_7.11.23

1)

101_B

Cross current protection

time

4

THBxCCP[2:0] = P_7.11.24

1)

110_B

Cross current protection

time

16

THBxCCP[2:0] = P_7.11.25

1)

111_B

Bridge driver passive mode: BD_PASS = 1 and all HBxMODE[1:0] = 00_Bor 11_B, or EN = Low or V_DD< V_{DD POR}

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Multiple MOSFET Driver IC

Protections and diagnostics

Table 25

Electrical characteristics: (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C

V_CP> V_S+ 8 V

All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

V_{SOV PASS OFF}28

Max.

Passive V_Sovervoltage

31.5

35

V

V_Sincreasing

PASS_MOD=10_B

1)

P_7.11.66

P_7.11.67

Passive V_Sovervoltage

V_{SOV PASS HY}

1

2.5

4

V

hysteresis

PWM3 open drain resistance R_{PWM3_OD}

4

-

5.5

4.5

7

kΩ

P_7.11.68

P_7.11.69

Passive turn-on time

Passive Turn-off time

Passive LS gate voltage

t_{ON_BD_PASS}

t_{OFF_BD_PASS}

V_{GLx_BRAKE}

10

µs

¹⁾Cap = 10 nF,

VCap = 5 V,

VS > 8 V

¹⁾Cap = 10 nF,

VCap down to

1.5 V, VS > 8 V

-

0.7

–

2

µs

V

P_7.11.70

P_7.11.71

5

2

10

VGLx - VSL,

x = 1 to 4, VS > 8 V

1)

Passive turn-on blank time t_{BLK_BD_PASS}

6

10

µs

V

P_7.11.72

P_7.11.73

PWM1 high voltage, bridge V_{PWM1H_BD_P}0.5

1.3

2.0

driver passive

ASS

1)

Passive VDS filter time

t_{DSMON_FILT_B}0.5

1

2

µs

V

P_7.11.74

P_7.11.75

D_PASS

Passive drain-source

monitoring thresholds

V_{VDSMON_BD_}0.30

0.37

0.44

PASS_VDS=1_B

PASS

Current sense amplifier

Operating common mode

input voltage range referred

to GND (CSIPx - GND) or

(CSINx - GND)

V_CM

-2.0

–

28

V

P_7.11.26

P_7.11.27

Common Mode Rejection

Ratio

CMRR

69

75

81

–

dB

CSAG = (0,0)

CSAG = (0,1)

CSAG = (1,0)

CSAG = (1,1)

DC to 50 kHz

V

_CM= -2 … 28 V

1)

V

= V_CSINx

CSIPx

Settling time to 98%

t_SET

–

1500

–

2000

5000

ns

P_7.11.28

P_7.11.65

Settling time to 98% after

gain change

t_{SET_GAIN}

¹⁾After gain

change from CSN

rising edge

Input Offset voltage

V_OS

-1.5

9.9

0

1.5

mV

V/V

P_7.11.29

P_7.11.30

Current Sense Amplifier DC G_DIFF10

10

10.1

CSAG = (0,0)

Gain (uncalibrated)

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Multiple MOSFET Driver IC

Protections and diagnostics

Table 25

Electrical characteristics: (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C

V_CP> V_S+ 8 V

All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

20

Unit Note or

Test Condition

Number

Min.

Max.

Current Sense Amplifier DC G_DIFF20

Gain (uncalibrated)

19.8

20.2

V/V

%

CSAG = (0,1)

CSAG = (1,0)

CSAG = (1,1)

P_7.11.31

P_7.11.32

P_7.11.33

Current Sense Amplifier DC G_DIFF40

Gain (uncalibrated)

39.6

79.2

-0.5

0.5

40

80

–

40.4

80.8

0.5

Current Sense Amplifier DC G_DIFF80

Gain (uncalibrated)

Gain drift

G_DRIFT

¹⁾Gain drift after P_7.11.34

calibration

1)

CSOx single ended output

voltage range (linear range)

V_CSOx

–

V_DD

-

V

P_7.11.35

0.5

Reference voltage for

unidirectional CSAx

V_{REF Unidir}

V_{REF Bidir}

-1%

V_DD/5 +1%

V_DD/2 +1%

V

CSDx = 0

_CSIPx= V_CSINx

CSDx = 1

_CSIPx= V_CSINx

P_7.11.36

P_7.11.37

V

Reference voltage for

bidirectional CSAx

V

Overcurrent detection

Overcurrent filter time

t_FOC

4

7

40

85

6

8

µs

OCxFILT = 00_B

OCxFILT = 01_B

OCxFILT = 10_B

P_7.11.38

10

50

100

13

60

115

OCxFILT = 11_B

1)2)

OC threshold, unidirectional V_{OCTH1 Unidir}-4%

OC threshold, unidirectional V_{OCTH2 Unidir}-4%

OC threshold, unidirectional V_{OCTH3 Unidir}-4%

V_DD/2 +4%

V_DD/2 + +4%

V

CSDx = 0,

OCTH[1:0]= 00_B

P_7.11.39

P_7.11.40

P_7.11.41

CSDx = 0,

OCTH[1:0]= 01_B

V

_DD/10

V_DD/2 + +4%

CSDx = 0,

2x

OCTH[1:0]= 10_B

V

_DD/10

OC threshold, unidirectional V_{OCTH4 Unidir}-4%

V_DD/2 + +4%

3x

V

CSDx = 0,

OCTH[1:0]= 11_B

P_7.11.42

P_7.11.43

P_7.11.44

P_7.11.45

V

_DD/10

High OC threshold,

bidirectional

V_{OCTH1 BidirH}-4%

V_{OCTH2 BidirH}-4%

V_{OCTH3 BidirH}-4%

V_DD/2 + +4%

2x

CSDx = 1,

OCTH[1:0]= 00_B

V

_DD/20

High OC threshold,

bidirectional

V_DD/2 + +4%

4x

CSDx = 1,

OCTH[1:0]= 01_B

V

_DD/20

High OC threshold,

bidirectional

V_DD/2 + +4%

5x

CSDx = 1,

OCTH[1:0]= 10_B

V

_DD/20

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Multiple MOSFET Driver IC

Protections and diagnostics

Table 25

Electrical characteristics: (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C

V_CP> V_S+ 8 V

All voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

High OC threshold,

bidirectional

V_{OCTH4 BidirH}-4%

V_{OCTH1 BidirL}-4%

V_{OCTH2 BidirL}-4%

V_{OCTH3 BidirL}-4%

V_{OCTH4 BidirL}-4%

V_DD/2 + +4%

6x

V

CSDx = 1,

OCTH[1:0]= 11_B

P_7.11.46

V

_DD/20

Low OC threshold,

bidirectional

V_DD/2 - +4%

2x

CSDx = 1,

OCTH[1:0]= 00_B

P_7.11.61

P_7.11.62

P_7.11.63

P_7.11.64

V

_DD/20

Low OC threshold,

bidirectional

V_DD/2 - +4%

4x

CSDx = 1,

OCTH[1:0]= 01_B

V

_DD/20

Low OC threshold,

bidirectional

V_DD/2 - +4%

5x

CSDx = 1,

OCTH[1:0]= 10_B

V

_DD/20

Low OC threshold,

bidirectional

V_DD/2 - +4%

6x

CSDx = 1,

OCTH[1:0]= 11_B

V

_DD/20

Thermal warning and shutdown

Thermal warning junction

temperature

T_jW

120

160

–

140

180

10

160

200

–

°C

See Figure 36¹⁾P_7.11.48

See Figure 36¹⁾P_7.11.49

Thermal shutdown junction T_jSD

temperature

1)

Thermal shutdown

hysteresis

T_jHYS

P_7.11.50

1)

Ratio of T_jSDto T_jW

T_jSD/ T_jW

–

7

1.20

10

–

P_7.11.51

1)

Thermal warning filter time t_{jW_FILT}

13

µs

P_7.11.55

1)

Thermal shutdown filter

time

t_{jSD_FILT}

10

P_7.11.56

1) Not subject to production test, specified by design.

2) _FOCrefers to the output of the current sense amplifier. The CSO settling time (2 µs max, t_SET) and the analog

propagation delay (< 1 µs)are not taken into account by the overcurrent filter time.

t

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

8

Serial Peripheral Interface - SPI

The 24-bit Serial Peripheral Interface (SPI) enables the communication between the microcontroller and the

TLE92108-232QX. It allows to configure and control the device, and to read out the status registers for

diagnostic purpose.The MOSFET driver IC acts as a SPI-slave while the microcontroller acts as a SPI-master.

The interface has a serial data input pin (SDI) to transfer data to the device, a serial data output pin (SDO) for

reading data back from the device, and a serial clock pin (SCLK) for clocking data into and out of the device. A

chip select pin (CSN) enables or disables the serial interface.

The SPI frame starts with the falling edge of CSN. During the falling edge of CSN, SCLK must be low (Clock

Polarity CPOL = 0). Received data on SDI are shifted in on the falling edge of SCLK. Transmitted data by SDO

are shifted out on the rising edge of SCLK (Clock Phase CPHA = 1). Refer to Figure 42.

The Most Significant Bit (MSB, bit 23) is shifted in/out first.

Write and clear commands are executed at the rising edge of CSN.

The SPI protocol supports both independent slave selection and daisy chain configurations.

8.1

SPI protocol with independent slave selection

With individual slave selection, the microcontroller controls the CSN pin of each SPI slave individually

(Figure 41).

Microcontroller

TLE9210x

SPI

Device2

SPI

Device3

SPI

SDI

SDO

SDI2

SDO2 SDI3

SDO3

MCSN1

MCSN2

MCSN3

MCLK

MOSI

MISO

Figure 41 Individual slave selection with three slave devices

A SPI communication consists of 24-bit frame (Figure 42):

•

SDI receives one address byte followed by two data bytes.

SDO transmits the Global Error Flag and the Global Status Byte followed by two response bytes.

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

CSN high to low: SDO is enabled . Status information transferred to output shift register

CSN

time

CSN low to high: data from shift register is transferred to output functions

SCLK

SDI

time

MSB

23 22 21 20 19 18 17

Actual data

LSB

New data

23+ 22+

4

3

2

1

0

SDI: will accept data on the falling edge of SCLK signal

MSB

GEF 23 22 21 20 19 18 17

LSB

Actual status

New status

SDO

GEF+ 23+ 22+

time

4

3

2

1

0

SDO will change state on the rising edge of SCLK signal

Figure 42 SPI Data Transfer

The MSB of the address byte must be set to ‘1’.

The address byte specifies (see Figure 43):

•

the target register (A[4:0])

the type of operation:

•

For control registers:

–

•

Read only: OP bit¹⁾= ‘0’

Read and write: OP bit = ‘1’

For status registers:

–

Read only: OP bit = ‘0’

Read and clear: OP bit = ‘1’

With individual slave selection, the Last Address Byte Token (LABT) must be set to ‘1’.

In-frame response

The SPI protocol incorporates an in-frame response: The content of the addressed register is shifted out by

SDO within the same SPI frame. This feature reduces the SPI bus load during the read out of the control or

status registers.

1) OP bit is the least significant bit of the address byte, see Figure 43

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

Address Byte

Data High Byte

SDI

Data Low Byte

MSB

23

LSB

0

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LABT

= 1

1

A4

A3

A2

A1

A0

OP

D15 D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

Response corresponding to the incoming address byte

Response High Byte

SDO

Global Status Byte

LSB

0

Response Low Byte

MSB

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

NPOR

SUPE VDSE OC SPIE R15 R14 R13 R12 R11 R10 R9 R8

0

FS

TE

R7 R6 R5 R4 R3 R2 R1 R0

Time

MSB is sent first in SPI message

Figure 43 In-frame response with individual slave selection

8.2

Global Error Flag (GEF)

The Global Error Flag (GEF) is reported on SDO between the CSN falling edge and the first SCLK rising edge.

GEF is set if a fault condition is detected or if the device comes from a Power On Reset (POR). It is therefore

possible to have a quick device diagnostic without any SPI clock pulse (Figure 44).

CSN

time

0

SCLK

time

0

SDI

time

High Impedance

Global Error Flag

SDO

time

Figure 44 GEF - Diagnostic with 0-clock cycle

8.3

Global status byte

The SDO shifts out during the first eight SCLK cycles the Global Status Byte. This register provides an overview

of the device status. The following error conditions are reported in this byte:

•

Fail Safe (FS bit).

Temperature error (TE bit): logical OR combination between Thermal Warning (TW) and Thermal

shutdown (TSD).

•

Negated Power ON Reset (NPOR bit, refer to Chapter 5.3 for reset conditions).

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

•

Supply Error (SUPE bit): logical OR combination between VS undervoltage shutdown (VSUV), VS

overvoltage shutdown (VSOV) and charge pump undervoltage (CPUV).

•

VDS monitoring Error (VDSE bit): logical OR combination between the bits of the DSOV register.

Overcurrent (OC bit): logical OR combination between OC1 and OC2 status bits (GENSTAT register).

SPI protocol Error (SPIE bit).

Note:

The Global Error Flag is a logic OR combination of every bit of the Global Status Byte and of TDREGx:

GEF = (FS) OR (TE) OR (NOT(NPOR)) OR (SUPE) OR (VDSE) OR (OC) OR (SPIE) OR (NOT(TDREGx) AND

(PWMx_EN =1) AND (NOT (MSKTDREG))), x = 1 ... 3.

The following table shows how failures are reported in the Global Status Byte and the error Flag:

Table 26

Failure reported in the global status byte and global error flag

Type of Error

Failure reported in the Global

Status Byte

Global Error Flag

Fail safe

FS = 1

1

Thermal error

TE = 1

Power ON reset

NPOR = 0

SUPE = 1

VDSE = 1

OC = 1

SPIE = 1

-

Supply error

Drain source voltage monitoring

Overcurrent

SPI protocol error

TDREGx, x = 1 ... 3¹⁾(see GENSTAT)

1 if MSKTDREG = 0²⁾

0 if MSKTDREG = 1²⁾

No error and no power ON reset

SPIE = 0

OC = 0

0

VDSE = 0

SUPE= 0

NPOR = 1

TE = 0

FS = 0

TDREGx = 0,

1) See status register GENSTAT.

2) See control register GENCTRL2.

Note:

The default value (after Power ON Reset) of NPOR is 0, therefore the default value of GEF is 1.

In fail safe mode, the control registers are frozen to their default value, with the exception of the WDTRIG bit

(refer to Chapter 5.2.3). Any write access (except for WDTRIG bit) in fail safe mode will be discarded and the

SPIE bit will set.

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

8.4

SPI error detection

The SPI incorporates an error flag in the Global Status Byte (SPIE) to supervise and preserve the data integrity.

If an SPI protocol error is detected during a given frame, the SPIE bit is set in the next SPI communication.

The SPIE bit is set in the following error conditions:

•

The number of SCLK clock pulses received when CSN is Low is (protocol error):

–

not zero

or less than 24

or more than 24 but not a multiple of 8

•

The microcontroller sends an SPI command to an unused address (protocol error).

A clock polarity error is detected (see Figure 45 Case 2 and Case 3): the incoming clock signal was High

during CSN rising or falling edges (protocol error).

•

No address byte or no last address byte are detected (protocol error).

In daisy chain: the microcontroller does not send in sequence the first address byte until the last address

byte (i.e. with gaps between two address bytes). In this case, the SDO signal is set to ‘0’ during the

remaining part of the SPI frame¹⁾, in order to prevent other devices from executing wrong commands

(protocol error).

•

A clear command to address 0x1F (Device ID register, Offset address = 0x1F).

The same half-bridge is allocated to several activated PWM channels.

Any write or clear command received in fail safe mode and not belonging to the exit sequence (refer to

Chapter 5.2.3).

Note:

SPI commands to activate a half-bridge mapped to several PWM channels are ignored.

In fail safe mode, the control registers may not be accessed, except for writing WDTRIG. An invalid write

command in this mode sets the SPIE bit.

For a correct SPI communication:

•

SCLK must be Low for a minimum t_BEFbefore CSN falling edge and t_leadafter CSN falling edge.

SCLK must be Low for a minimum t_lagbefore CSN rising edge and t_BEHafter CSN rising edge.

1) Provided that the SPI frame has a correct polarity

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

Case 1: Correct SCLK signal

Correct incoming clock signal

Correct clock during CSN rising edge

CSN

time

t_BEF

t_lead

t_lagt_BEH

SCLK

Case 2: Erroneous incoming clock signal

CSN

time

SCLK is High with CSN falling edge

SCLK

Case 3: Erroneous clock signal during CSN rising edge

CSN

time

Clock is High with CSN rising edge

SCLK

Figure 45 Clock polarity error

The reset condition of the SPIE bit depends on the cause of error:

•

In normal mode:

–

The microcontroller must clear HBVOUT_PWMERR if one half-bridge has been allocated to several

PWM channels.

–

The microcontroller must send a correct SPI frame for the other errors reported by SPIE.

•

If SPIE has been set in fail safe mode, the device must enter normal mode first.

8.5

Daisy chain

In daisy chain configuration the master output / slave input (noted MOSI) is connected to a slave SDI. The first

slave SDO is connected to the next slave SDI in the chain. The SDO of the final in the chain is connected to the

master input / slave output (noted MISO). In daisy chain configuration, the microcontroller MCSN is connected

to all the slave CSN inputs (Figure 46).

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

To support daisy chain configurations, the TLE92108-232QX accepts SPI frames with more than 24 bits,

provided that the number of bits is a multiple of 8, and the structure of the address byte is respected.

In daisy chain, the TLE92108-232QX works as follows:

1. The TLE92108-232QX operates as a 8-bit shift register until it receives the first address byte. This first

received address byte is considered by the device as its own address byte.

2. The TLE92108-232QX copies directly SDI to SDO until the last address byte is detected.

3. The TLE92108-232QX shifts out the response high byte and low byte corresponding to the address byte.

4. After the last address byte, the TLE92108-232QX operates as a 16-bit shift register until the end of the SPI

frame.

Microcontroller

TLE9210x_1

SPI

TLE9210x_2

SPI

TLE9210x_3

SPI

SDI1

SDO1 SDI2

SDO2 SDI3

SDO3

MOSI

MCSN

MCLK

MISO

Figure 46 Daisy chain configuration with three TLE9210x devices

In daisy chain configuration (Figure 46), the microcontroller must send the address and data bytes in the

following order (Figure 47):

1. The address bytes altogether are sent first:

•

Address byte 1 (for TLE9210x_1) is sent first, followed by address byte 2 (for TLE9210x_2), followed by

address byte 3 (for TLE9210x_3).

•

The LABT bit of the last address byte must be ‘1’, while the LABT bit of all the other address bytes must

be ‘0’.

2. The data bytes are sent altogether in reverse order once the address bytes are transmitted:

•

The data high byte for the TLE9210x_3 is sent first followed by the data low byte for the TLE9210x_3.

Then the data high byte for the TLE9210x_2 is sent followed by the data low byte for the TLE9210x_2.

Then the data high byte for the TLE9210x_1 is sent followed by the data low byte for the TLE9210x_1.

The Master Input / Slave Output (MISO), which is connected to SDO of the last device in the daisy chain,

receives:

1. A logic OR combination of all Global Error Flags (GEF) at the beginning of the SPI frame, between CSN

falling edge and the first SCLK rising edge.

2. The Global Status Byte of each TLE9210x in reverse order:

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

•

The Global Status Byte 3 (GSB3) corresponding to the TLE9210x_3 is received first, followed by GSB2

(corresponding to the TLE9210x_2), and finally the GSB1 (corresponding to the TLE9210x_1) is

received.

3. The response of each TLE9210x in reverse order:

•

The response high byte of the TLE9210x_3 is received first followed by the response low byte of the

TLE9210x_3.

Then the response high byte of the TLE9210x_2 is received followed by the response low byte of the

TLE9210x_2.

Then the response high byte of the TLE9210x_1 is received followed by the response low byte of the

TLE9210x_1.

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

Figure 47 SPI Frame in daisy chain configuration with three TLE9210x devices

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

8.6

SPI electrical characteristics: timings

Table 27

Electrical characteristics: SPI interface

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

4

SPI frequency

1)

Maximum SPI frequency

f_SPI,max

–

P_8.6.1

Delay from EN rising edge to first SPI frame

SPI interface setup time²⁾

t_{SET_SPI}

SPI interface, logic inputs SDI, SCLK, CSN

–

150

–

µs

P_8.6.32

High input voltage threshold V_IH

Low input voltage threshold V_IL

Hysteresis of input voltage V_IHY

0.7 x

V_DD

–

V

P_8.6.2

P_8.6.3

P_8.6.4

P_8.6.5

–

0.3 x

V_DD

1)

–

0.12 x

V_DD

–

Pull up resistor at pin CSN

R_{PU_CSN}

20

40

80

kΩ

V_CSN= 0.7 x V_DD

Pull down resistor at pin SDI, R_{PD_SDI,}

V_SDI, V_SCLK= 0.2 x P_8.6.6

SCLK

R_{PD_SCLK}

V_DD

Input capacitance at pin

CSN, SDI or SCLK

C_I

–

10

–

pF

¹⁾0 V < V_DD< 5.5 V P_8.6.7

Input interface, logic outputs SDO

H-output voltage level

L-output voltage level

Tri-state Leakage Current

V_SDOH

V_SDOL

I_SDOLK

0.8 x

V_DD

–

V

I_SDOH= -1.6 mA

P_8.6.8

P_8.6.9

P_8.6.10

P_8.6.11

–

0.2 x

V_DD

V

I_SDOL= 1.6 mA

1)

-10

–

10

µA

pF

V

= V_DD;

CSN

0 V < V_SDO< V_DD

1)

Tri-state input capacitance C_SDO

10

15

Data input timing. See Figure 41

1)

SCLK Period

t_pCLK

250

–

ns

P_8.6.12

P_8.6.13

SCLK High Time

t_SCLKH

0.45 x

0.55 x ns

t_pCLK

1)

SCLK Low Time

t_SCLKL

0.45 x

–

0.55 x ns

P_8.6.14

t_pCLK

1)

SCLK Low before CSN Low t_BEF

125

250

125

100

–

ns

P_8.6.15

P_8.6.16

P_8.6.17

P_8.6.18

P_8.6.19

CSN Setup Time

t_lead

SCLK Setup Time

SCLK Low after CSN High

SDI Setup Time

t_lag

t_BEH

t_{SDI_setup}

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Multiple MOSFET Driver IC

Serial Peripheral Interface - SPI

Table 27

Electrical characteristics: SPI interface (cont’d)

V_S= 6.0 V to 18 V if VSOVTH = 0, V_S= 6.0 V to 28 V if VSOVTH = 1; V_DD= 3.0 V to 5.5 V, T_j= -40°C to 150°C, all voltages

with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

50

Typ.

Max.

–

1)

SDI Hold Time

t_{SDI_hold}

–

ns

P_8.6.20

P_8.6.21

1)

Input Signal Rise Time at pin t_rIN

–

50

SDI, SCLK, CSN

1)

Input Signal Fall Time at pin t_fIN

SDI, SCLK, CSN

–

3

–

50

6

ns

µs

P_8.6.22

P_8.6.23

P_8.6.24

Delay time from EN falling

edge to standby mode

t_DMODE

Minimum CSN High Time

t_CSNH

–

Data output timing. See Figure 42.

1)

SDO Rise Time

SDO Fall Time

t_rSDO

t_fSDO

–

30

–

80

50

ns

C

= 100 pF

P_8.6.25

P_8.6.26

P_8.6.27

load

SDO Enable Time after CSN t_ENSDO

¹⁾Low

falling edge

Impedance

SDO Disable Time after CSN t_DISSDO

rising edge

–

50

55

50

ns

%

¹⁾High

Impedance

1)

P_8.6.28

P_8.6.29

Duty cycle of incoming clock duty_SCLK

at SCLK

45

–

1)

SDO Valid Time for V_DD= 5V t_VASDO5

ns

V

< 0.2 x V_DDP_8.6.31

SDO

V_SDO> 0.8 x V_DD

C_load= 100 pF

1) Not subject to production test, specified by design

2) Delay required between EN rising edge and the moment when the device can accept SPI commands

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Serial Peripheral Interface - SPI

t_lead

t_lag

t_CSNH

t_pCLK

0.8V_DD

0.2V_DD

CSN

t_SCLKH

t_SCLKL

0.8VDD

0.2V_DD

SCLK

t_{SDI_hold}

t_{SDI _s etup}

0.8V_DD

0.2V_DD

SDI

t_ENSDO

t_VASDO

t_DISSDO

0.8V_DD

0.2V_DD

SDO

Figure 48 SPI timing parameters

EN

t_SET

SPI

A) SPI message ignored

B) SPI message accepted

Figure 49 Setup time from EN rising edge to first SPI communication

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Register specification

9

Register specification

9.1

Control registers

Table 28 Register Overview

Register Short Name Register Long Name

Offset Address

Reset Value

GENCTRL1

GENCTRL2

VDS1

General control register 1

0x00 and REG_BANK = 0 or 1 0x0026

0x01 and REG_BANK = 0 or 1 0x4180

0x02 and REG_BANK = 0 or 1 0x0249

0x03 and REG_BANK = 0 or 1 0x0249

0x04 and REG_BANK = 0 or 1 0x0000

General control register 2

Drain-source monitoring HB1-4

Drain-source monitoring HB5-8

VDS2

CCP_BLK1

Cross current protection and

blank times setting 1

CCP_BLK2_ACT

CCP_BLK2_FW

Cross current protection and

blank times setting for active

MOSFETs¹⁾

0x05 and REG_BANK = 0

0x05 and REG_BANK = 1

0x4924

Cross current protection and

blank times setting for FW

MOSFETs¹⁾

HBMODE

PWMSET

TPRECHG

Half-bridge mode

0x06 and REG_BANK = 0 or 1 0x0000

0x07 and REG_BANK = 0 or 1 0x6C60

0x08 andREG_BANK = 0 or 1 0x0000

Setting of PWM channels

PWM pre-charge and pre-

discharge time

HBIDIAG

ST_ICHG

Half-bridge diagnostic current

control

0x09 and REG_BANK = 0 or 1 0xC000

Charge current for static half-

bridges

0x0A and REG_BANK = 0

0x0044

PWM_PCHG_INIT

PWM_ICHG_ACT

Precharge current initialization

0x0A and REG_BANK = 1

0x18C6

Charge current for half-bridges in 0x0B and REG_BANK = 0

PWM (active MOSFETs¹⁾)

PWM_ICHG_FW

Charge current for half-bridges in 0x0B and REG_BANK = 1

PWM (FW MOSFETs¹⁾)

0x18C6

0x1CE7

PWM_IDCHG_ACT

PWM_PDCHG_INIT

Discharge current of active

MOSFETs¹⁾in PWM operation

0x0C and REG_BANK = 0

Predischarge current initialization 0x0C and REG_BANK = 1

0x318C

0x4900

PWM_ICHGMAX_CCP_ Max. pre-charge / pre-discharge

BLK3_ACT

0x0D and REG_BANK =0

currents for half-bridges in PWM²⁾,

tCCP and tBLANK setting for

active MOSFETS¹⁾

PWM_ICHGMAX_CCP_ Max. pre-charge / pre-discharge

BLK3_FW

0x0D and REG_BANK =1

0x4900

currents for half-bridges in PWM²⁾,

tCCP and tBLANK setting for FW

MOSFETS¹⁾

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Multiple MOSFET Driver IC

Register specification

Table 28 Register Overview (cont’d)

Register Short Name Register Long Name

Offset Address

Reset Value

TDON_OFF1

TDON_OFF2

TDON_OFF3

Turn-on and turn-off delays for

PWM channel1

0x0E and REG_BANK = 0 or 1 0x0A0A

0x0F and REG_BANK = 0 or 1 0x0A0A

0x10 and REG_BANK = 0 or 1 0x0A0A

Turn-on and turn-off delays for

PWM channel2

Turn-on and turn-off delays for

PWM channel3

1) Refer to Chapter 6.3.1 for the definition of the active and the free-wheeling MOSFETs, depending on the setting of

AGC

2) ICHGMAX is also the current applied to the Active MOSFET during post-discharge.

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Register specification

9.1.1

General Control Registers and Protection Settings

General control register 1

GENCTRL1

General Control Register 1 (0 0000_B)Reset Value: 0000 0000 0010 0110_B

15

14

CSAG2

rw

13

12

11

CSAG1

rw

10

9

8

7

6

5

4

3

2

1

0

REG_ VSOV UNLO Reser FMOD Reser IPCHG

BANK TH

WDPE WDTR

R

CSD2

CSD1

OCEN

CK

ved

E

ved ADT

IG

rw

rw rw

rw

r

rw

r

rw

Field

CSD2

Bits

Type

Description

Direction of the current sense amplifier 2

15

rw

0_BThe current sense is unidirectional (default)

1_BThe current sense is bidirectional

CSAG2

14:13

rw

Gain of the current sense amplifier 2

00_B10 V/V (default)

01_B20 V/V

10_B40 V/V

11_B80 V/V

CSD1

12

rw

Direction of the current sense amplifier 1

0_BThe current sense is unidirectional (default)

1_BThe current sense is bidirectional

CSAG1

11:10

Gain of the current sense amplifier 1

00_B10 V/V (default)

01_B20 V/V

10_B40 V/V

11_B80 V/V

REG_BANK

9

rw

Register banking

0_B(Default) refer to CCP_BLK2_ACT,

PWM_ICHGMAX_CCP_BLK3_ACT, PWM_ICHG_ACT,

ST_ICHG, PWM_IDCHG_ACT

1_B

Refer to CCP_BLK2_FW, PWM_ICHGMAX_CCP_BLK3_FW,

PWM_ICHG_FW,PWM_PDCHG_INIT,PWM_PCHG_INIT

VSOVTH

UNLOCK

8

7

rw

VS Overvoltage threshold

0_BV_{SOV OFF}= V_{SOV OFF1}(min. 19 V, default)

1_BV_{SOV OFF}= V_{SOV OFF2}(min. 29V)

Unlock bit to disable the watchdog

0_BWDDIS cannot be reset (default)

1_BWDDIS (GENCTRL2) can be reset in the following SPI frame

Reserved

FMODE

6

5

r

Reserved. Always read as ‘0’

rw

Frequency modulation

0_BNo modulation

1_BModulation frequency 15.6 kHz (default)

Reserved

4

r

Reserved. Always read as ‘0’

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Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

IPCHGADT

3

rw

Adaptation of the pre-charge and pre-discharge current

0_B1 current step (default)

1_B2 current steps

OCEN

2

1

0

rw

Overcurrent shutdown Enable

0_BDisabled

1_BEnabled (default)

WDPER

WDTRIG

Watchdog period

0_B50 ms

1_B200 ms (default)

Watchdog trigger bit

This bit must be inverted within a watchdog period. After power on

reset, the default value is 0.

Attention: Any write access to this register must invert the WDTRIG bit. Otherwise, the device enters fail

safe mode. Refer to Chapter 5.2.3.

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Multiple MOSFET Driver IC

Register specification

General control register 2

GENCTRL2

General Control Register 2 (0 0001_B)Reset Value: 0100 0001 1000 0000_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POCH BD_P AGCFI

WDDI MSKT CPUV CPST

AGC

IHOLD

TFVDS

rw

OCTH2

rw

OCTH1

rw

GDIS ASS

LT

S

DREG TH

GA

rw

rw rw

rw

Field

Bits

Type

Description

Postcharge disable bit

POCHGDIS 15

rw

0_BThe postcharge phase is enabled during PWM (default)

1_BThe postcharge phase is disabled during PWM

BD_PASS

AGCFILT

14

13

rw

Bridge driver passive mode

0_BBridge driver is in active mode

1_BBridge driver is in passive mode (Default)

Filter for adaptive gate control

Note:

Refer to Adaptive control of pre-charge current and

Adaptive control of pre-discharge current

0_BNo filter applied (default)

1_BFilter applied

AGC

12:11

rw

Adaptive gate control

00_B(default) Adaptive gate control disabled, pre-charge and pre-

discharge disabled

01_BAdaptive gate control disabled, precharge is disabled,

predischarge is enabled with IPREDCHG = IPDCHGINIT (Refer

to PWM_PCHG_INIT)

10_BAdaptive gate control enabled, IPRECHG and IPREDCHG are

self adapted

11_BReserved. Adaptive gate control enabled, IPRECHG and

IPREDCHG are self adapted

IHOLD

WDDIS

10

9

rw

Gate driver hold current IHOLD

0_B(default) Charge: I_CHG8(12.5 mA typ.), discharge I_DCHG8(14.2

mA typ.)

1_B

Charge: I_CHG12(23.9 mA typ.), discharge: I_DCHG12(26.0 mA typ.)

Watchdog disable bit

0_Bthe watchdog is enabled (default)

1_Bthe watchdog is disabled if the previous SPI frame has set

UNLOCK bit (GENCTRL1)

Once the watchdog is disabled, it is directly re-enabled by resetting

WDDIS

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Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

MSKTDREG

8

rw

Masking of the turn-on/off delay error in the Global Error Flag

0_BTurn-on/off delay error is reported in the GEF

1_BTurn-on/off delay error is masked in the GEF (default)

CPUVTH

CPSTGA

7

6

rw

Charge pump undervoltage detection threshold

0_BV_CPUV(referred to VS) = 6.0V typ.

1_BV_CPUV(referred to VS)= 7.5 V typ. (default)

Automatic switch-over between dual and single charge pump

stage

0_BAutomatic switch over deactivated (default)

1_BAutomatic switch over activated

TFVDS

OCTH2

5:4

3:2

rw

Filter time of drain-source voltage monitoring

00_B0.5 µs (default)

01_B1 µs

10_B2 µs

11_B3 µs

Overcurrent detection threshold of CSO2 with CSD2 = 0

00_BV_CSO2> V_DD/2(default)

01_BV_CSO2> V_DD/2+ V_DD/10

10_BV_CSO2> V_DD/2+ 2 x V_DD/10

11_BV_CSO2> V_DD/2+ 3 x V_DD/10

Overcurrent detection threshold of CSO2 with CSD2 = 1

00_BV_CSO2> V_DD/2+ 2 x V_DD/20 or V_CSO2< V_DD/2- 2 x V_DD/20 (default)

01_BV_CSO2> V_DD/2+ 4 x V_DD/20 or V_CSO2< V_DD/2- 4 x V_DD/20

10_BV_CSO2> V_DD/2+ 5 x V_DD/20 or V_CSO2< V_DD/2- 5 xV_DD/20

11_BV_CSO2> V_DD/2+ 6 x V_DD/20 or V_CSO2< V_DD/2- 6 x V_DD/20

OCTH1

1:0

rw

Overcurrent detection threshold of CSO1 with CSD1 = 0

00_BV_CSO1> V_DD/2(default)

01_BV_CSO1> V_DD/2+ V_DD/10

10_BV_CSO1> V_DD/2+ 2 x V_DD/10

11_BV_CSO1> V_DD/2+ 3x V_DD/10

Overcurrent detection threshold of CSO1 with CSD1 = 1

00_BV_CSO1> V_DD/2+2 x V_DD/20 or V_CSOx< V_DD/2- 2x V_DD/20 (default)

01_BV_CSO1> V_DD/2+ 4x V_DD/20 or V_CSOx< V_DD/2- 4x V_DD/20

10_BV_CSO1> V_DD/2+ 5 x V_DD/20 or V_CSOx< V_DD/2- 5 xV_DD/20

11_BV_CSO1> V_DD/2+ 6x V_DD/20 or V_CSOx< V_DD/2- 6x V_DD/20

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Multiple MOSFET Driver IC

Register specification

Drain-source monitoring threshold HB1-4

VDS1

Drain-source monitoring threshold HB1-4(0 0010_B)Reset Value:0000 0010 0100 1001_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB4D HB3D HB2D HB1D

HB4VDSTH

HB3VDSTH

HB2VDSTH

HB1VDSTH

rw

Field

Bits

Type

Description

HS4 Drain-source monitoring¹⁾

HB4D

15

rw

0_BDrain-source monitoring: DH - VSH4 (default)

1_BDrain-source monitoring: CSIN1 - VSH4

HB3D

HB2D

HB1D

14

13

12

rw

HS3 Drain-source monitoring¹⁾

0_BDrain-source monitoring: DH - VSH3 (default)

1_BDrain-source monitoring: CSIN1 - VSH3

HS2 Drain-source monitoring¹⁾

0_BDrain-source monitoring: DH - VSH2 (default)

1_BDrain-source monitoring: CSIN1 - VSH2

HS1 Drain-source monitoring¹⁾

0_BDrain-source monitoring: DH - VSH1 (default)

1_BDrain-source monitoring: CSIN1 - VSH1

HB4VDSTH 11:9

HB4 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40 V

101_B0.50 V

110_B0.60 V

111_B2.0 V

HB3VDSTH 8:6

rw

HB3 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40V

101_B0.50 V

110_B0.60 V

111_B2.0 V

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB2VDSTH 5:3

rw

HB2 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40 V

101_B0.50 V

110_B0.60 V

111_B2.0 V

HB1VDSTH 2:0

rw

HB1 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40 V

101_B0.50 V

110_B0.60 V

111_B2.0 V

1) Applicable for HSx. The Drain-Source overvoltage for LSx is done by monitoring VSHx - VSL.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Drain-source monitoring threshold HB5-8

VDS2

Drain-source monitoring threshold HB5-8(0 0011_B)Reset Value: 0000 0010 0100 1001_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB8D HB7D HB6D HB5D

HB8VDSTH

HB7VDSTH

HB6VDSTH

HB5VDSTH

rw

Field

Bits

Type

Description

HS8 Drain-source monitoring¹⁾

HB8D

15

rw

0_BDrain-source monitoring: DH - VSH8 (default)

1_BDrain-source monitoring: CSIN1 - VSH8

HB7D

HB6D

HB5D

14

13

12

rw

HS7 Drain-source monitoring¹⁾

0_BDrain-source monitoring: DH - VSH7 (default)

1_BDrain-source monitoring: CSIN1 - VSH7

HS6 Drain-source monitoring¹⁾

0_BDrain-source monitoring: DH - VSH6 (default)

1_BDrain-source monitoring: CSIN1 - VSH6

HS5 Drain-source monitoring¹⁾

0_BDrain-source monitoring: DH - VSH5 (default)

1_BDrain-source monitoring: CSIN1 - VSH5

HB8VDSTH 11:9

HB8 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40 V

101_B0.50 V

110_B0.60 V

111_B2.0 V

HB7VDSTH 8:6

rw

HB7 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40 V

101_B0.50 V

110_B0.60 V

111_B2.0 V

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB6VDSTH 5:3

rw

HB6 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40 V

101_B0.50 V

110_B0.60 V

111_B2.0 V

HB5VDSTH 2:0

rw

HB5 drain-source overvoltage threshold

000_B0.15 V

001_B0.20 V (default)

010_B0.25 V

011_B0.30 V

100_B0.40 V

101_B0.50 V

110_B0.60 V

111_B2.0 V

1) Applicable for HSx. The Drain-Source overvoltage for LSx is done by monitoring VSHx - VSL.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Cross current protection and blank time setting 1

CCP_BLK1

CCP and Blank times setting 1(0 0100_B)Reset Value: 0000 0000 0000 0000_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB8CCPBLK HB7CCPBLK HB6CCPBLK HB5CCPBLK HB4CCPBLK HB3CCPBLK HB2CCPBLK HB1CCPBLK

rw

Field

Bits

Type

Description

HB8CCPBLK 15:14

HB7CCPBLK 13:12

HB6CCPBLK 11:10

HB5CCPBLK 9:8

HB4CCPBLK 7:6

HB3CCPBLK 5:4

HB2CCPBLK 3:2

rw

Cross-current protection and blank times applied to HB8

00_B(tHB8CCP, tHB8BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB8CCP, tHB8BLANK) = (tCCP2, tBLANK2)

10_B(tHB8CCP, tHB8BLANK) = (tCCP3, tBLANK3)

11_B(tHB8CCP, tHB8BLANK) = (tCCP4, tBLANK4)

Cross-current protection and blank times applied to HB7

00_B(tHB7CCP, tHB7BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB7CCP, tHB7BLANK) = (tCCP2, tBLANK2)

10_B(tHB7CCP, tHB7BLANK) = (tCCP3, tBLANK3)

11_B(tHB7CCP, tHB7BLANK) = (tCCP4, tBLANK4)

Cross-current protection and blank times applied to HB6

00_B(tHB6CCP, tHB6BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB6CCP, tHB6BLANK) = (tCCP2, tBLANK2)

10_B(tHB6CCP, tHB6BLANK) = (tCCP3, tBLANK3)

11_B(tHB6CCP, tHB6BLANK) = (tCCP4, tBLANK4)

Cross-current protection and blank times applied to HB5

00_B(tHB5CCP, tHB5BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB5CCP, tHB5BLANK) = (tCCP2, tBLANK2)

10_B(tHB5CCP, tHB5BLANK) = (tCCP3, tBLANK3)

11_B(tHB5CCP, tHB5BLANK) = (tCCP4, tBLANK4)

Cross-current protection and blank times applied to HB4

00_B(tHB4CCP, tHB4BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB4CCP, tHB4BLANK) = (tCCP2, tBLANK2)

10_B(tHB4CCP, tHB4BLANK) = (tCCP3, tBLANK3)

11_B(tHB4CCP, tHB4BLANK) = (tCCP4, tBLANK4)

Cross-current protection and blank times applied to HB3

00_B(tHB3CCP, tHB3BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB3CCP, tHB3BLANK) = (tCCP2, tBLANK2)

10_B(tHB3CCP, tHB3BLANK) = (tCCP3, tBLANK3)

11_B(tHB3CCP, tHB3BLANK) = (tCCP4, tBLANK4)

Cross-current protection and blank times applied to HB2

00_B(tHB2CCP, tHB2BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB2CCP, tHB2BLANK) = (tCCP2, tBLANK2)

10_B(tHB2CCP, tHB2BLANK) = (tCCP3, tBLANK3)

11_B(tHB2CCP, tHB2BLANK) = (tCCP4, tBLANK4)

Datasheet

110

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB1CCPBLK 1:0

rw

Cross-current protection and blank times applied to HB1

00_B(tHB1CCP, tHB1BLANK) = (tCCP1, tBLANK1) (default)

01_B(tHB1CCP, tHB1BLANK) = (tCCP2, tBLANK2)

10_B(tHB1CCP, tHB1BLANK) = (tCCP3, tBLANK3)

11_B(tHB1CCP, tHB1BLANK) = (tCCP4, tBLANK4)

Refer

to

CCP_BLK2_ACT,

PWM_ICHGMAX_CCP_BLK3_ACT,

CCP_BLK2_FW

and

PWM_ICHGMAX_CCP_BLK3_FW for the setting of (tCCPx, tBLANKx), x = 1 … 4.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Cross current protection and blank time setting 2 for active MOSFETs

Attention: This register is accessed with REG_BANK = 0 and the offset adress 0 0101_B. tCCP and tBLANK are

applicable to the active MOSFETs.

CCP_BLK2_ACT

Active CCP and Blank times setting 2(0 0101_B)Reset Value: 0100 1001 0010 0100_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

TCCP3_ACT

TBLANK2_ACT

TCCP2_ACT

TBLANK1_ACT

TCCP1_ACT

r

rw

Field

Bits

Type

r

Description

Reserved. Always read as ‘0’

Reserved

15

TCCP3_ACT 14:12

rw

Cross-current protection - tCCP3 Active

Refer to Table 29

Default: 100_B: typ. 2000 ns

TBLANK2_A 11:9

CT

rw

Blank time - tBLANK2 Active

Refer to Table 30

Default: 100_B: typ. 2000 ns

TCCP2_ACT 8:6

Cross-current protection - tCCP2 Active

Refer to Table 29

Default: 100_B: typ. 2000 ns

TBLANK1_A 5:3

CT

Blank time - tBLANK1 Active

Refer to Table 30

Default: 100_B: typ. 2000 ns

TCCP1_ACT 2:0

Cross-current protection - tCCP1 Active

Refer to Table 29

Default: 100_B: typ. 2000 ns

Table 29 Cross-current protection time for active MOSFETs

TCCPx_ACT[2:0], x = 1…4 Active cross-current protection HBx, x = 1…4 (typical)

000_B

001_B

010

011

100

101

110

111

375 ns

625 ns

1 µs

1.5 µs

2 µs (default)

3 µs

4 µs

16 µs¹⁾

1) When applying a cross-current protection time of 16 µs to a half-bridge, the max. drive current used for this half-

bridge must be set below 30 mA , to avoid an overheating of the gate driver. Refer to register ST_ICHG for static

controlled half-bridges and PWM_IDCHG_ACT for half-bridges controlled in PWM.

Datasheet

112

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Table 30 Drain-Source overvoltage blank time for active MOSFETs

TBLANKx_ACT[2:0], x =

1…4

Active drain-Source overvoltage blank time tBLANKx, x = 1…4 (typical)

000_B

001_B

010_B

011_B

100_B

101_B

110_B

111_B

625 ns

1 µs

1.25 µs

1.5 µs

2 µs (default)

3 µs

4 µs

16 µs¹⁾

1) When applying a drain-source overvoltage blank time of 16 µs to a half-bridge, the max. drive current used for this

half-bridge must be set below 30 mA , to avoid an overheating of the gate driver. Refer to register ST_ICHG for static

controlled half-bridges and PWM_ICHG_ACT for half-bridges controlled in PWM.

Refer to PWM_ICHGMAX_CCP_BLK3_ACT for the setting of tBLANK4, tCCP4 and tBLANK3 for the active

MOSFETs.

Refer to CCP_BLK1 for the mapping of (tCCPx,tBLANKx) to the half-bridges.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Cross current protection and blank time setting 2 for FW MOSFETs

Attention: This register is accessed with REG_BANK = 1 and the offset address 0 0101_B. tCCP and tBLANK

are applicable to the FW MOSFETs.

CCP_BLK2_FW

FW CCP and Blank times setting 2(0 0101_B)Reset Value: 0100 1001 0010 0100_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

TCCP3_FW

TBLANK2_FW

TCCP2_FW

TBLANK1_FW

TCCP1_FW

r

rw

Field

Bits

Type

r

Description

Reserved. Always read as ‘0’

Reserved

15

TCCP3_FW 14:12

rw

Cross-current protection - tCCP3 Freewheeling

Refer to Table 31

Default: 100_B: typ. 2000 ns

TBLANK2_F 11:9

W

rw

Blank time - tBLANK2 Freewheeling

Refer to Table 32

Default: 100_B: typ. 2000 ns

TCCP2_FW 8:6

Cross-current protection - tCCP2 Freewheeling

Refer to Table 31

Default: 100_B: typ. 2000 ns

TBLANK1_F 5:3

W

Blank time - tBLANK1 Freewheeling

Refer to Table 32

Default: 100_B: typ. 2000 ns

TCCP1_FW 2:0

Cross-current protection - tCCP1 Freewheeling

Refer to Table 31

Default: 100_B: typ. 2000 ns

Table 31 Cross-current protection time for FW MOSFETs

TCCPx_FW[2:0], x = 1…4

FW cross-current protection HBx, x = 1…4 (typical)

000_B

001_B

010

011

100

101

110

111

375 ns

625 ns

1 µs

1.5 µs

2 µs (default)

3 µs

4 µs

16 µs¹⁾

1) When applying a cross-current protection time of 16 µs to a half-bridge, the max. drive current used for this half-

bridge must be set below 30 mA , to avoid an overheating of the gate driver. Refer to register ST_ICHG for static

controlled half-bridges and PWM_ICHG_FW for half-bridges controlled in PWM.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Table 32 Drain-Source overvoltage blank time for FW MOSFETs

TBLANKx_FW[2:0], x = 1…4 FW Drain-Source overvoltage blank time tBLANKx, x = 1…4 (typical)

000_B

001_B

010_B

011_B

100_B

101_B

110_B

111_B

625 ns

1 µs

1.25 µs

1.5 µs

2 µs (default)

3 µs

4 µs

16 µs¹⁾

1) When applying a drain-source overvoltage blank time of 16 µs to a half-bridge, the max. drive current used for this

half-bridge must be set below 30 mA , to avoid an overheating of the gate driver. Refer to register ST_ICHG for static

controlled half-bridges and PWM_ICHG_FW for half-bridges controlled in PWM.

Refer to PWM_ICHGMAX_CCP_BLK3_FW for the setting of tBLANK4, tCCP4 and tBLANK3 for the FW MOSFETs.

Refer to CCP_BLK1 for the mapping of (tCCPx,tBLANKx) to the half-bridges.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

9.1.2

Half-bridge control

Half-bridge mode

HBMODE

Half-bridge mode

(0 0110_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB8MODE

HB7MODE

HB6MODE

HB5MODE

HB4MODE

HB3MODE

HB2MODE

HB1MODE

rw

Field

Bits

Type

Description

HB8MODE

HB7MODE

HB6MODE

HB5MODE

HB4MODE

HB3MODE

HB2MODE

15:14

13:12

11:10

9:8

rw

Half-bridge output 8 mode selection

00_BHB8 is in high impedance (default)

01_BLS8 is ON

10_BHS8 is ON

11_BReserved - HB8 is in high impedance

rw

Half-bridge output 7 mode selection

00_BHB7 is in high impedance (default)

01_BLS7 is ON

10_BHS7 is ON

11_BReserved - HB7 is in high impedance

Half-bridge output 6 mode selection

00_BHB6 is in high impedance (default)

01_BLS6 is ON

10_BHS6 is ON

11_BReserved - HB6 is in high impedance

Half-bridge output 5 mode selection

00_BHB5 is in high impedance (default)

01_BLS5 is ON

10_BHS5 is ON

11_BReserved - HB5 is in high impedance

7:6

Half-bridge output 4 mode selection

00_BHB4 is in high impedance (default)

01_BLS4 is ON

10_BHS4 is ON

11_BReserved - HB4 is in high impedance

5:4

Half-bridge output 3 mode selection

00_BHB3 is in high impedance (default)

01_BLS3 is ON

10_BHS3 is ON

11_BReserved - HB3 is in high impedance

3:2

Half-bridge output 2 mode selection

00_BHB2 is in high impedance (default)

01_BLS2 is ON

10_BHS2 is ON

11_BReserved - HB2 is in high impedance

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB1MODE

1:0

rw

Half-bridge output 1 mode selection

00_BHB1 is in high impedance (default)

01_BLS1 is ON

10_BHS1 is ON

11_BReserved - HB1 is in high impedance

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM channel settings

PWMSET

PWM channel settings

(0 0111_B)Reset Value: 0110 1100 0110 0000_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser PASS_

ved VDS

PWM3

_EN

PWM2

_EN

PWM1

_EN

PASS_MOD

PWM3_HB

PWM2_HB

PWM1_HB

r

rw

Field

Bits

Type

r

Description

Reserved. Always read as ‘0’

Reserved

15

PASS_VDS 14

rw

Drain-Source monitoring in bridge passive mode

0_BDS monitoring in bridge passive mode disabled

1_BDS monitoring in bridge passive mode enabled (Default)

PASS_MOD 13:12

rw

Settings for bridge driver passive mode

00_BLS1-4 are always off

Note: Changing PASS_MOD from 00_Bto any other value

requires to clear DSOV¹⁾first before writing PASS_MOD,

01_BLS1-4 are always on (static brake)

10_BLS1-4 are activated if passive VS OV is detected (overvoltage

brake) (Default)

11_BLS1-4 are activated if passive VS OV is detected and PWM1 =

High (overvoltage brake conditioned by PWM1)

PWM3_HB 11:9

rw

Allocation of the PWM channel 3

000_BHB1

001_BHB2

010_BHB3

011_BHB4

100_BHB5

101_BHB6

110_BHB7 (default)

111_BHB8

PWM3_EN

8

rw

PWM channel 3 enable

0_BPWM3 is disabled (default)

1_BPWM3 is enabled

PWM2_HB 7:5

Allocation of the PWM channel 2

000_BHB1

001_BHB2

010_BHB3

011_BHB4 (Default)

100_BHB5

101_BHB6

110_BHB7

111_BHB8

Datasheet

118

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

PWM2_EN

4

rw

PWM channel 2 enable

0_BPWM2 is disabled (default)

1_BPWM2 is enabled

PWM1_HB 3:1

rw

Allocation of the PWM channel 1

000_BHB1 (default)

001_BHB2

010_BHB3

011_BHB4

100_BHB5

101_BHB6

110_BHB7

111_BHB8

PWM1_EN

0

rw

PWM channel 1 enable

0_BPWM1 is disabled (default)

1_BPWM1 is enabled

1) If DSOV is not cleared first, the value of PASS_MOD stays at 00_B

If the same half-bridge is mapped to several activated PWM channels, then a SPI error is reported and the

impacted half-bridge is in high-impedance.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM pre-charge and pre-discharge time

TPRECHG

Charge and pre-charge time

(0 1000_B) Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EN_GE

N_CH TPDCHG3

ECK

Reser EN_DE Reser

ved EP_AD ved

TPCHG3

TPDCHG2

TPCHG2

TPDCHG1

TPCHG1

rw

Field

Bits

Type

Description

Reserved

15

rw

Reserved. To be programmed as ‘0’.

EN_DEEP_A 14

Deep adaptation enabled

D

0_BDeep adaptation disabled (default)

1_BDeep adaptation enabled. Refer to Chapter 6.3.3.6.

Reserved

13

rw

Reserved. This bits must be set to ‘0’

EN_GEN_CH 12

Enable generator check

ECK

0_BDetection of generator mode disabled (default)

1_BDetection of generator mode enabled.

TPDCHG3

TPCHG3

11:10

rw

Pre-discharge time of PWM channel 3

00_B125 ns (default)

01_B250 ns

10_B500 ns

11_B1000 ns

9:8

7:6

5:4

3:2

Pre-charge time of PWM channel 3

00_B125 ns (default)

01_B250 ns

10_B500 ns

11_B1000 ns

TPDCHG2

TPCHG2

Pre-discharge time of PWM channel 2

00_B125 ns (default)

01_B250 ns

10_B500 ns

11_B1000 ns

Pre-charge time of PWM channel 2

00_B125 ns (default)

01_B250 ns

10_B500 ns

11_B1000 ns

TPDCHG1

Pre-discharge time of PWM channel 1

00_B125 ns (default)

01_B250 ns

10_B500 ns

11_B1000 ns

Datasheet

120

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

TPCHG1

1:0

rw

Pre-charge time of PWM channel 1

00_B125 ns (default)

01_B250 ns

10_B500 ns

11_B1000 ns

Datasheet

121

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2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Half-bridge diagnostic current control

HBIDIAG

Half-bridge diagnostic current control(0 1001_B)Reset Value: 1100 0000 0000 0000_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CSA2_ CSA1_ HB8ID HB7ID HB6ID HB5ID HB4ID HB3ID HB2ID HB1ID

CSA2L CSA1L OC2FILT

OC1FILT

OFF OFF IAG

IAG

rw

rw rw rw

rw

Field

Bits

Type

Description

CSA2L

15

rw

Level of CSA2

0_BCSA2 is configured as low-side

1_BCSA2 is configured as high-side (default)

CSA1L

14

Level of CSA1

0_BCSA1 is configured as low-side

1_BCSA1 is configured as high-side (default)

OC2FILT

13:12

11:10

Overcurrent filter time for CSO2

00_B6 µs (default)

01_B10 µs

10_B50 µs

11_B100 µs

OC1FILT

rw

Overcurrent filter time for CSO1

00_B6 µs (default)

01_B10 µs

10_B50 µs

11_B100 µs

CSA2_OFF

CSA1_OFF

HB8IDIAG

HB7IDIAG

HB6IDIAG

HB5IDIAG

9

8

7

6

5

4

rw

Disable of CSA2

0_BCSA2 enabled(default)

1_BCSA2 disabled

Disable of CSA1

0_BCSA1 enabled (default)

1_BCSA1 disabled

Control of HB8 off-state current source and current sink

0_BPull-down deactivated (default)

1_BPull-down activated

Control of HB7 off-state current source and current sink

0_BPull-down deactivated (default)

1_BPull-down activated

Control of HB6 off-state current source and current sink

0_BPull-down deactivated (default)

1_BPull-down activated

Control of HB5 off-state current source and current sink

0_BPull-down deactivated (default)

1_BPull-down activated

Datasheet

122

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB4IDIAG

3

rw

Control of HB4 off-state current source and current sink

0_BPull-down deactivated (default)

1_BPull-down activated

HB3IDIAG

HB2IDIAG

HB1IDIAG

2

1

0

rw

Control of HB3 off-state current source and current sink

0_BPull-down deactivated (default)

1_BPull-down activated

Control of HB2 off-state current source and current sink

0_BPull-down deactivated (default)

1_BPull-down activated

Control of HB1 pull-down for off-state diagnostic

0_BPull-down deactivated (default)

1_BPull-down activated

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Static charge and discharge current selection

Attention: This register is accessed only if REG_BANK = 0 with the corresponding offset address.

ST_ICHG

Static charge and discharge current selection(0 1010_B)Reset Value: 0000 0000 0100 0100_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB8IC HB7IC HB6IC HB5IC HB4IC HB3IC HB2IC HB1IC

HGST HGST HGST HGST HGST HGST HGST HGST

ICHGST2

ICHGST1

rw

Field

Bits

Type

Description

HB8 Selection of charge and discharge currents

HB8ICHGST 15

HB7ICHGST 14

HB6ICHGST 13

HB5ICHGST 12

HB4ICHGST 11

HB3ICHGST 10

rw

0_BThe static charge/discharge current 1 is applied to the half-

bridge 8 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 8.

rw

HB7 Selection of charge and discharge currents

0_BThe static charge/discharge current 1 is applied to the half-

bridge 7 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 7.

HB6 Selection of charge and discharge currents

0_BThe static charge/discharge current 1 is applied to the half-

bridge 6 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 6.

HB5 Selection of charge and discharge currents

0_BThe static charge/discharge current 1 is applied to the half-

bridge 5 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 5.

HB4 Selection of charge and discharge currents

0_BThe static charge/discharge current 1 is applied to the half-

bridge 4 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 4.

HB3 Selection of charge and discharge currents

0_BThe static charge/discharge current 1 is applied to the half-

bridge 3 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 3.

Datasheet

124

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB2ICHGST

9

rw

HB2 Selection of charge and discharge currents

0_BThe static charge/discharge current 1 is applied to the half-

bridge 2 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 2.

HB1ICHGST

8

rw

HB1 Selection of charge and discharge currents

0_BThe static charge/discharge current 1 is applied to the half-

bridge 1 (default).

1_BThe static charge/discharge current 2 is applied to the half-

bridge 1.

ICHGST2

ICHGST1

7:4

3:0

rw

Static gate driver charge and discharge currents 2

Refer to Table 10

Default: 0100_B- Charge 12.5 mA typ., discharge 14.2 mA typ.

Static gate driver charge and discharge currents 1

Refer to Table 10

Default: 0100_B- charge 12.5 mA typ., discharge 14.2 mA typ.

Datasheet

125

Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM Active MOSFET precharge current initialization

Attention: This register is accessed only if REG_BANK = 1 with the corresponding offset address.

PWM_PCHG_INIT

Initial PWM precharge current selection(0 1010_B)Reset Value: 0001 1000 1100 0110_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

PCHGINIT3

PCHGINIT2

PCHGINIT1

r

rw

Field

Bits

Type

r

Description

Reserved. Always read as ‘0’

Reserved

15

PCHGINIT3 14:10

PCHGINIT2 9:5

PCHGINIT1 4:0

rw

Initial precharge current of PWM Channel 3

Refer to Table 13

Default: 00110_B: typ. 8.0 mA

rw

Initial precharge current of PWM Channel 2

Refer to Table 13

Default: 00110_B: typ. 8.0 mA

Initial precharge current of PWM Channel 1

Refer to Table 13

Default: 00110_B: typ. 8.0 mA

Datasheet

126

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM charge current of active MOSFETs

Attention: This register is accessed with REG_BANK = 0 and the offset address 0 1011_B. The charge currents

are applied to the active MOSFET (ICHG1-3).

PWM_ICHG_ACT

Active PWM charge current (0 1011_B)Reset Value:0001 1000 1100 0110_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

ICHG3

ICHG2

ICHG1

r

rw

Field

Bits

15

Type

r

Description

Reserved. Always read as ‘0’

Reserved

ICHG3

14:10

rw

Gate driver charge current of PWM Channel 3 (Active MOSFET)

Refer to Table 13

Default: 00110_B: typ. 8.0 mA

ICHG2

ICHG1

9:5

4:0

rw

Gate driver charge current of PWM Channel 2 (Active MOSFET)

Refer to Table 13

Default: 00110_B: typ. 8.0 mA

Gate driver charge current of PWM Channel 1 (Active MOSFET)

Refer to Table 13

Default: 00110_B: typ. 8.0 mA

Datasheet

127

Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM charge/discharge currents of FW MOSFETs

Attention: This register is accessed with REG_BANK = 1 and the offset address 0 1011_B. The charge and

discharge currents are applied to the freewheeling MOSFETs (ICHGFW1-3).

PWM_ICHG_FW

FW PWM charge/discharge currents (0 1011_B) Reset Value:0001 1000 1100 0110_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

ICHG3_FW

ICHG2_FW

ICHG1_FW

r

rw

Field

Bits

Type

r

Description

Reserved. Always read as ‘0’

Reserved

15

ICHG3_FW 14:10

ICHG2_FW 9:5

ICHG1_FW 4:0

rw

Gate driver charge and discharge currents of PWM Channel 3

(FW MOSFET)

Refer to Table 13, Table 14

Default: 00110_B. Typ. charge 8.0 mA, typ. discharge: 9.4 mA

rw

Gate driver charge and discharge currents of PWM Channel 2

(FW MOSFET)

Refer to Table 13, Table 14

Default: 00110_B. Typ. charge 8.0 mA, typ. discharge: 9.4 mA

Gate driver charge and discharge currents of PWM Channel 1

(FW MOSFET)

Refer to Table 13, Table 14

Default: 00110_B. Typ. charge 8.0 mA, typ. discharge: 9.4 mA

Note:

The selected currents are applied to the turn-on and the turn-off of the FW MOSFETs.

Datasheet

128

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2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM discharge current for active MOSFETs

Attention: This register is accessed only if REG_BANK = 0 with the corresponding offset address.

PWM_IDCHG_ACT

PWM discharge current

(0 1100_B)Reset Value: 0001 1100 1110 0111_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CCSO

IDCHG3

IDCHG2

IDCHG1

rw

Field

Bits

Type

Description

CCSO

15

rw

Capacitor connected to the current sense amplifier outputs

0_BCapacitor connected to CSO < 100 pF (default)

1_BCapacitor connected to CSO < 400 pF

IDCHG3

IDCHG2

IDCHG1

14:10

9:5

rw

Discharge current for PWM Channel 3 (Active MOSFET)

Refer to Table 14

Default: 00111_B: typ. 11.8 mA

Discharge current for PWM Channel 2 (Active MOSFET)

Refer to Table 14

Default: 00111_B: typ. 11.8 mA

4:0

Discharge current of PWM Channel 1 (Active MOSFET)

Refer to Table 14

Default: 00111_B: typ. 11.8 mA

Datasheet

129

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM Active MOSFET predischarge current initialization

Attention: This register is accessed only if REG_BANK = 1 with the corresponding offset address.

PWM_PDCHG_INIT

Initial PWM predischarge current selection(0 1100_B)Reset Value: 0011 0001 1000 1100_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CCSO

PDCHGINIT3

PDCHGINIT2

PDCHGINIT1

rw

Field

Bits

15

Type

Description

CCSO

rw

Capacitor connected to the current sense amplifier outputs

0_BCapacitor connected to CSO < 100 pF (default)

1_BCapacitor connected to CSO < 400 pF

PDCHGINIT 14:10

3

rw

Initial predischarge current of PWM Channel 3

Refer to Table 14

Default: 01100_B: typ. 26.0 mA

PDCHGINIT 9:5

2

Initial predischarge current of PWM Channel 2

Refer to Table 14

Default: 01100_B: typ. 26.0 mA

PDCHGINIT 4:0

1

Initial predischarge current of PWM Channel 1

Refer to Table 14

Default: 01100_B: typ. 26.0 mA

Datasheet

130

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM maximum drive current selection and active tCCP4, tBLANK 3/4

Attention: This register is accessed with REG_BANK = 0 and the offset address 0 1101_B. tCCP and tBLANK

are applicable to the active MOSFETs.

PWM_ICHGMAX_CCP_BLK3_ACT

PWM max. drive current

(0 1101_B)Reset Value: 0100 1001 0000 0000_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

TBLANK4_ACT

TCCP4_ACT

TBLANK3_ACT

ICHGMAX3

ICHGMAX2

ICHGMAX1

r

rw

Field

Bits

Type

r

Description

Reserved

15

Reserved. Always read as ‘0’

TBLANK4_A 14:12

CT

rw

Blank time ¹⁾- tBLANK4 Active

Refer to Table 30

Default: 100_B: typ. 2000 ns

TCCP4_ACT 11:9

rw

Cross-current protection¹⁾- tCCP4 Active

Refer to Table 29

Default: 100_B: typ. 2000 ns

Blank time¹⁾- tBLANK3 Active

Refer to Table 30

Default: 100_B: typ. 2000 ns

TBLANK3_A 8:6

CT

ICHGMAX3 5:4

ICHGMAX2 3:2

ICHGMAX1 1:0

Maximum drive current of half-bridge mapped to PWM channel

3 during the pre-charge phase and pre-discharge phases²⁾

00_B(default) charge: typ. 18.8 mA, discharge: typ. 19.7 mA

01_Bcharge: typ. 41mA, discharge: typ. 43 mA

10_Bcharge: typ. 77 mA, discharge: typ. 79 mA

11_Bcharge: typ. 100 mA, discharge: typ. 100 mA

rw

Maximum drive current of half-bridge mapped to PWM channel

2 during the pre-charge phase and pre-discharge phases²⁾

00_B(default) charge: typ. 18.8 mA, discharge: typ. 19.7 mA

01_Bcharge: typ. 41 mA, discharge: typ. 43 mA

10_Bcharge: typ. 77 mA, discharge: typ. 79 mA

11_Bcharge: typ. 100 mA, discharge: typ. 100 mA

Maximum drive current of half-bridge mapped to PWM channel

1 during the pre-charge and pre-discharge phases²⁾

00_B(default) charge: typ. 18.8 mA, discharge: typ. 19.7 mA

01_Bcharge: typ. 41 mA, discharge: typ. 43 mA

10_Bcharge: typ. 77 mA, discharge: typ. 79 mA

11_Bcharge: typ. 100 mA, discharge: typ. 100 mA

1) Refer to CCP_BLK1 for the mapping of (tCCPx,tBLANKx) to the half-bridges.

2) ICHGMAX is also the current applied during the post-charge of the PWM MOSFET Refer to Table 12.

Datasheet

131

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

PWM maximum drive current selection and FW tCCP4, tBLANK 3/4

Attention: This register is accessed with REG_BANK = 1 and the offset address 0 1101_B. tCCP and tBLANK

are applicable to the FW MOSFETs.

PWM_ICHGMAX_CCP_BLK3_FW

PWM max. drive current

(0 1101_B)Reset Value: 0100 1001 0000 0000_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

TBLANK4_FW

TCCP4_FW

TBLANK3_FW

ICHGMAX3

ICHGMAX2

ICHGMAX1

r

rw

Field

Bits

Type

r

Description

Reserved

15

Reserved. Always read as ‘0’

TBLANK4_F 14:12

W

rw

Blank time ¹⁾- tBLANK4 Freewheeling

Refer to Table 32

Default: 100_B: typ. 2000 ns

TCCP4_FW 11:9

rw

Cross-current protection¹⁾- tCCP4 Freewheeling

Refer to Table 31

Default: 100_B: typ. 2000 ns

Blank time¹⁾- tBLANK3 Freewheeling

Refer to Table 32

Default: 100_B: typ. 2000 ns

TBLANK3_F 8:6

W

ICHGMAX3 5:4

ICHGMAX2 3:2

ICHGMAX1 1:0

Maximum drive current of half-bridge mapped to PWM channel

3 during the pre-charge phase and pre-discharge phases²⁾

00_B(default) charge: typ. 19 mA, discharge: typ. 19 mA

01_Bcharge: typ. 41mA, discharge: typ. 43 mA

10_Bcharge: typ. 77 mA, discharge: typ. 79 mA

11_Bcharge: typ. 100 mA, discharge: typ. 100 mA

rw

Maximum drive current of half-bridge mapped to PWM channel

2 during the pre-charge phase and pre-discharge phases²⁾

00_B(default) charge: typ. 19 mA, discharge: typ. 19 mA

01_Bcharge: typ. 41mA, discharge: typ. 43 mA

10_Bcharge: typ. 77 mA, discharge: typ. 79 mA

11_Bcharge: typ. 100 mA, discharge: typ. 100 mA

Maximum drive current of half-bridge mapped to PWM channel

1 during the pre-charge and pre-discharge phases²⁾

00_B(default) charge: typ. 19 mA, discharge: typ. 19 mA

01_Bcharge: typ. 41mA, discharge: typ. 43 mA

10_Bcharge: typ. 77 mA, discharge: typ. 79 mA

11_Bcharge: typ. 100 mA, discharge: typ. 100 mA

1) Refer to CCP_BLK1 for the mapping of (tCCPx,tBLANKx) to the half-bridges.

2) ICHGMAX is also the current applied during the post-charge of the PWM MOSFET Refer to Table 12.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Selection MOSFET turn-on and turn-off delay for PWM channel 1

TDON_OFF1

MOSFET turn-on/off delay of PWM channel1 (0 1110_B)Reset Value:0000 1010 0000 1010_B

15

14

13

12

TDOFF1

rw

11

10

9

8

7

6

5

4

3

2

1

0

TDON1

rw

Field

Bits

Type

Description

TDOFF1

15:8

rw

Turn-off delay time of PWM Channel 1.

Typical TDOFF1 = 62.5 x TDOFF1[7:0]_Dns

Default: 0000 1010_B: 625 ns typ.

TDON1

7:0

rw

Turn-on delay time of PWM Channel 1.

Typical TDON1 = 62.5 x TDON1[7:0]_Dns

Default: 0000 1010_B: 625 ns typ.

Datasheet

133

Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Selection MOSFET turn-on and turn-off delay for PWM channel 2

TDON_OFF2

MOSFET turn-on/off delay of PWM channel2 (0 1111_B)Reset Value: 0000 1010 0000 1010_B

15

14

13

12

TDOFF2

rw

11

10

9

8

7

6

5

4

3

2

1

0

TDON2

rw

Field

Bits

Type

Description

TDOFF2

15:8

rw

Turn-off delay time of PWM Channel 2.

Typical TDOFF2 = 62.5 x TDOFF2[7:0]_Dns

Default: 0000 1010_B: 625 ns typ.

TDON2

7:0

rw

Turn-on delay time of PWM Channel 2.

Typical TDON2 = 62.5 x TDON2[7:0]_Dns

Default: 0000 1010_B: 625 ns typ.

Datasheet

134

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Selection MOSFET turn-on and turn-off delay for PWM channel 3

TDON_OFF3

MOSFET turn-on/off delay of PWM channel3 (1 0000_B)Reset Value: 0000 1010 0000 1010_B

15

14

13

12

TDOFF3

rw

11

10

9

8

7

6

5

4

3

2

1

0

TDON3

rw

Field

Bits

Type

Description

TDOFF3

15:8

rw

Turn-off delay time of PWM Channel 3.

Typical TDOFF3 = 62.5 x TDOFF3[7:0]_Dns

Default: 0000 1010_B: 625 ns typ.

TDON3

7:0

rw

Turn-on delay time of PWM Channel 3.

Typical TDON3 = 62.5 x TDON3[7:0]_Dns

Default: 0000 1010_B: 625 ns typ.

Datasheet

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Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

9.2

Status register

Table 33 Register Overview

Register Short Name Register Long Name

Offset Address Reset Value

GENSTAT

General status register

Drain-source overvoltage

Half-Bridge output voltage

11_H

12_H

13_H

0_H

DSOV

HBVOUT_PWMERR

EFF_TDON_OFF1

Effective MOSFET turn-on and turn-off delays for 14_H

PWM Channel 1

EFF_TDON_OFF2

EFF_TDON_OFF3

TRISE_FALL1

TRISE_FALL2

TRISE_FALL3

DEVID

Effective MOSFET turn-on and turn-off delays for 15_H

PWM Channel 2

0_H

01_H

Effective MOSFET turn-on and turn-off delays for 16_H

PWM Channel 3

Effective MOSFET rise and fall times for PWM

Channel 1

17_H

18_H

19_H

1F_H

Effective MOSFET rise and fall times for PWM

Channel 2

Effective MOSFET rise and fall times for PWM

Channel 3

Device identifier

Datasheet

136

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

9.2.1

General status register

GENSTAT

General Status Register

(1 0001_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PASS_

VDSO

V

PWM3 PWM2 PWM1 TDRE TDRE TDRE

WDMON

TSD

TW

OC2 OC1 VSOV VSUV CPUV

rc rc rc rc rc

STAT STAT STAT G3

G2

G1

r

rc

Field

Bits

Type

Description

DS overvoltage while the bridge driver is in passive mode

PASS_VDSO 15

r

V

0_BNo overvoltage on drain-source of any low-sides (default)

1_BOvervoltage on drain-source of one of the low-side is

detected.

WDMON

14:13

r

Watchdog Monitoring

00_BWD Timer is between [0%;25%[ of the WD period (default)

01_BWD Timer is between [25%;50%[ of the WD period

10_BWD Timer is between [50%;75%[ of the WD period

11_BWD Timer is between [75%;100 %[ of the WD period

PWM3STAT 12

PWM2STAT 11

PWM1STAT 10

r

Status of PWM3 input

0_BPWM3 is low (default)

1_BPWM3 is high

r

Status of PWM2 input

0_BPWM2 is low (default)

1_BPWM2 is high

r

Status of PWM1 input

0_BPWM1 is low (default)

1_BPWM1 is high

TDREG3

TDREG2

TDREG1

9

8

7

6

rc

PWM channel 3 - Regulation of turn-on and turn-off delays

0_Bthe turn-on delay or the turn-off delay are not in regulation

(default)

1_Bthe turn-on and turn-off delays are in regulation

rc

PWM channel 2 - Regulation of turn-on and turn-off delays

0_Bthe turn-on delay or the turn-off delay are not in regulation

(default)

1_Bthe turn-on and turn-off delays are in regulation

PWM channel 1 - Regulation of turn-on and turn-off delays

0_Bthe turn-on delay or the turn-off delay are not in regulation

(default)

1_Bthe turn-on and turn-off delays are in regulation

TSD

Thermal Shutdown

0_BNo thermal shutdown is detected (default)

1_BA thermal shutdown is detected ²⁾

Datasheet

137

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

TW

Bits

Type

Description

5

rc

Thermal Warning

0_BNo thermal warning is detected (default)

1_BA thermal warning is detected

OC2

4

3

2

1

0

rc

Overcurrent detection of CSO2

0_BNo overcurrent detection on CSO2 (default)

1_BOvercurrent detected on CSO2¹⁾

OC1

Overcurrent detection of CSO1

0_BNo overcurrent detection on CSO1 (default)

1_BOvercurrent detected on CSO1¹⁾

VSOV

VSUV

CPUV

VS Overvoltage

0_BNo overvoltage on V_Sdetected (default value)

1_BOvervoltage on V_Sdetected²⁾

VS Undervoltage

0_BNo undervoltage on V_Sdetected (default value)

1_BUndervoltage on V_Sdetected²⁾

Charge Pump Undervoltage

0_BNo charge pump undervoltage (default)

1_BA charge pump undervoltage is detected²⁾

1) The state of the external MOSFETs depends on the setting of OCEN bit (see GENCTRL1).

2) The error is latched and the external MOSFETs are turned off.

Datasheet

138

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Drain-Source Overvoltage 1

DSOV

Drain-Source Overvoltage

(1 0010_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LS8DS HS8D LS7DS HS7D LS6DS HS6D LS5DS HS5D LS4DS HS4D LS3DS HS3D LS2DS HS2D LS1DS HS1D

OV

SOV

OV

SOV

OV

SOV

OV

SOV

OV

SOV

OV

SOV

OV

SOV

OV

SOV

rc

Field

Bits

Type

Description

Drain-Source overvoltage on low-side 8

LS8DSOV

HS8DSOV

LS7DSOV

HS7DSOV

LS6DSOV

HS6DSOV

LS5DSOV

HS5DSOV

LS4DSOV

HS4DSOV

LS3DSOV

15

rc

0_BNo overvoltage on drain-source of low-side 8 (default)

1_BOvervoltage on drain-source of low-side 8 detected.

14

13

12

11

10

9

rc

Drain-Source overvoltage on high-side 8

0_BNo overvoltage on drain-source of high-side 8 (default)

1_BOvervoltage on drain-source of high-side 8 detected.

Drain-Source overvoltage on low-side 7

0_BNo overvoltage on drain-source of low-side 7(default)

1_BOvervoltage on drain-source of low-side 7detected.

Drain-Source overvoltage on high-side 7

0_BNo overvoltage on drain-source of high-side 7 (default)

1_BOvervoltage on drain-source of high-side 7 detected.

Drain-Source overvoltage on low-side 6

0_BNo overvoltage on drain-source of low-side 6 (default)

1_BOvervoltage on drain-source of low-side 6 detected.

Drain-Source overvoltage on high-side 6

0_BNo overvoltage on drain-source of high-side 6 (default)

1_BOvervoltage on drain-source of high-side 6 detected.

Drain-Source overvoltage on low-side 5

0_BNo overvoltage on drain-source of low-side 5 (default)

1_BOvervoltage on drain-source of low-side 5 detected.

8

Drain-Source overvoltage on high-side 5

0_BNo overvoltage on drain-source of high-side 5 (default)

1_BOvervoltage on drain-source of high-side 5 detected.

7

Drain-Source overvoltage on low-side 4

0_BNo overvoltage on drain-source of low-side 4 (default)

1_BOvervoltage on drain-source of low-side 4 detected.

6

Drain-Source overvoltage on high-side 4

0_BNo overvoltage on drain-source of high-side 4 (default)

1_BOvervoltage on drain-source of high-side 4 detected.

5

Drain-Source overvoltage on low-side 3

0_BNo overvoltage on drain-source of low-side 3 (default)

1_BOvervoltage on drain-source of low-side 3 detected.

Datasheet

139

Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HS3DSOV

4

rc

Drain-Source overvoltage on high-side 3

0_BNo overvoltage on drain-source of high-side 3 (default)

1_BOvervoltage on drain-source of high-side 3 detected.

LS2DSOV

HS2DSOV

LS1DSOV

HS1DSOV

3

2

1

0

rc

Drain-Source overvoltage on low-side 2

0_BNo overvoltage on drain-source of low-side 2 (default)

1_BOvervoltage on drain-source of low-side 2 detected.

Drain-Source overvoltage on high-side 2

0_BNo overvoltage on drain-source of high-side 2 (default)

1_BOvervoltage on drain-source of high-side 2 detected.

Drain-Source overvoltage on low-side 1

0_BNo overvoltage on drain-source of low-side 1 (default)

1_BOvervoltage on drain-source of low-side 1 detected.

Drain-Source overvoltage on high-side 1

0_BNo overvoltage on drain-source of high-side 1 (default)

1_BOvervoltage on drain-source of high-side 1 detected.

Note:

The impacted MOSFET is latched off if a Drain-Source overvoltage is detected.

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Half-bridge Output Voltage Status

HBVOUT_PWMERR

Half-bridge output voltage and PWM Error(1 0011_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB8P HB7P HB6P HB5P HB4P HB3P HB2P HB1P HB8V HB7V HB6V HB5V HB4V HB3V HB2V HB1V

WME WME WME WME WME WME WME WME OUT OUT OUT OUT OUT OUT OUT OUT

r

Field

Bits

Type

Description

PWM Error on HB8

HB8PWME 15

HB7PWME 14

HB6PWME 13

HB5PWME 12

HB4PWME 11

HB3PWME 10

r

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB8¹⁾

r

PWM Error on HB7

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB7¹⁾

PWM Error on HB6

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB6¹⁾

PWM Error on HB5

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB5¹⁾

PWM Error on HB4

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB4¹⁾

PWM Error on HB3

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB3¹⁾

HB2PWME

HB1PWME

HB8VOUT

9

8

7

PWM Error on HB2

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB2¹⁾

PWM Error on HB1

0_BNo PWM error (default)

1_BMore than one activated PWM channels is mapped to HB1¹⁾

Voltage level at SH8 when HB8MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH8| >V_VDSMONTHx²⁾if HB8D = 0

|VCSIN1 - VSH8| >V_VDSMONTHxif HB8D = 1

1_BHigh: |VDH - VSH8| <V_VDSMONTHxif HB8D = 0;

|VCSIN1 - VSH8| < V_VDSMONTHxif HB8D = 1

Note: HB8VOUT = 0 if HB8MODE[1:0]= (0,1) or (1,0)

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB7VOUT

6

r

Voltage level at SH7 when HB7MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH7| >V_VDSMONTHx²⁾if HB7D = 0

|VCSIN1 - VSH7| >V_VDSMONTHxif HB7D = 1

1_BHigh: |VDH - VSH7| <V_VDSMONTHxif HB7D = 0;

|VCSIN1 - VSH7| < V_VDSMONTHxif HB7D = 1

Note: HB7VOUT = 0 if HB7MODE[1:0]= (0,1) or (1,0)

HB6VOUT

HB5VOUT

HB4VOUT

HB3VOUT

HB2VOUT

5

4

3

2

1

r

Voltage level at SH6 when HB6MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH6| >V_VDSMONTHx²⁾if HB6D = 0

|VCSIN1 - VSH6| >V_VDSMONTHxif HB6D = 1

1_BHigh: |VDH - VSH6| <V_VDSMONTHxif HB6D = 0;

|VCSIN1 - VSH6| < V_VDSMONTHxif HB6D = 1

Note: HB6VOUT = 0 if HB6MODE[1:0]= (0,1) or (1,0)

Voltage level at SH5 when HB5MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH5| >V_VDSMONTHx²⁾if HB5D = 0

|VCSIN1 - VSH5| >V_VDSMONTHxif HB5D = 1

1_BHigh: |VDH - VSH5| <V_VDSMONTHxif HB5D = 0;

|VCSIN1 - VSH5| < V_VDSMONTHxif HB5D = 1

Note: HB5VOUT = 0 if HB5MODE[1:0]= (0,1) or (1,0)

Voltage level at SH4 when HB4MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH4| >V_VDSMONTHx²⁾if HB4D = 0

|VCSIN1 - VSH4| >V_VDSMONTHxif HB4D = 1

1_BHigh: |VDH - VSH4| <V_VDSMONTHxif HB4D = 0;

|VCSIN1 - VSH4| < V_VDSMONTHxif HB4D = 1

Note: HB4VOUT = 0 if HB4MODE[1:0]= (0,1) or (1,0)

Voltage level at SH3 when HB3MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH3| >V_VDSMONTHx²⁾if HB3D = 0

|VCSIN1 - VSH3| >V_VDSMONTHxif HB3D = 1

1_BHigh: |VDH - VSH3| <V_VDSMONTHxif HB3D = 0;

|VCSIN1 - VSH3| < V_VDSMONTHxif HB3D = 1

Note: HB3VOUT = 0 if HB3MODE[1:0]= (0,1) or (1,0)

Voltage level at SH2 when HB2MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH2| >V_VDSMONTHx²⁾if HB2D = 0

|VCSIN1 - VSH2| >V_VDSMONTHxif HB2D = 1

1_BHigh: |VDH - VSH2| <V_VDSMONTHxif HB2D = 0;

|VCSIN1 - VSH2| < V_VDSMONTHxif HB2D = 1

Note: HB2VOUT = 0 if HB2MODE[1:0]= (0,1) or (1,0)

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Field

Bits

Type

Description

HB1VOUT

0

r

Voltage level at SH1 when HB1MODE[1:0] = (0,0) or (1,1):

0_BLow: |VDH - VSH1| >V_VDSMONTHx²⁾if HB1D = 0;

|VCSIN1 - VSH1| >V_VDSMONTHxif HB1D = 1

1_BHigh: |VDH - VSH1| <V_VDSMONTHxif HB1D = 0;

|VCSIN1 - VSH1| < V_VDSMONTHxif HB1D = 1

Note: HB1VOUT = 0 if HB1MODE[1:0]= (0,1) or (1,0)

1) The bit is reset only if one PWM channel or no PWM channel is mapped to the half-bridge (refer to PWMSET).

2) V_VDSMONTHxis the drain-source monitoring threshold selected for the corresponding half-bridge.

Datasheet

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2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Effective MOSFET turn-on and turn-off delay of PWM1

EFF_TDON_OFF1

Effective MOSFET turn-on/off delay PWM1(1 0100_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TDOFF1EFF

TDON1EFF

r

Field

Bits

Type

Description

TDOFF1EFF 15:8

r

Effective MOSFET turn-off delay of PWM Channel 1

Effective turn-off delay = 62.5 x TDOFF1EFF[7:0]_Dns

Default: 0_B

TDON1EFF 7:0

r

Effective MOSFET turn-on delay of PWM Channel 1

Effective turn-on delay = 62.5 x TDON1EFF[7:0]_Dns

Default: 0_B

Datasheet

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Effective MOSFET turn-on and turn-off delay of PWM2

EFF_TDON_OFF2

Effective MOSFET turn-on/off delay PWM2(1 0101_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TDOFF2EFF

TDON2EFF

r

Field

Bits

Type

Description

TDOFF2EFF 15:8

r

Effective MOSFET turn-off delay of PWM Channel 2

Effective turn-off delay = 62.5 x TDOFF2EFF[7:0]_Dns

Default: 0_B

TDON2EFF 7:0

r

Effective MOSFET turn-on delay of PWM Channel 2

Effective turn-on delay = 62.5 x TDON2EFF[7:0]_Dns

Default: 0_B

Datasheet

145

Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Effective MOSFET turn-on and turn-off delay of PWM3

EFF_TDON_OFF3

Effective MOSFET turn-on/off delay PWM3(1 0110_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TDOFF3EFF

TDON3EFF

r

Field

Bits

Type

Description

TDOFF3EFF 15:8

r

Effective MOSFET turn-off delay of PWM Channel 3

Effective turn-off delay = 62.5 x TDOFF3EFF[7:0]_Dns

Default: 0_B

TDON3EFF 7:0

r

Effective MOSFET turn-on delay of PWM Channel 3

Effective turn-on delay = 62.5 x TDON3EFF[7:0]_Dns

Default: 0_B

Datasheet

146

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Effective MOSFET rise and fall times of PWM channel 1

TRISE_FALL1

Effective PWM MOSFET rise and fall times PWM1 (1 0111_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TFALL1

TRISE1

r

Field

Bits

Type

Description

MOSFET fall time of PWM Channel 1

TFALL1

15:8

r

MOSFET fall time = 62.5 x TFALL1[7:0]_Dns

Default: 0_B

TRISE1

7:0

r

MOSFET rise time of PWM Channel 1

MOSFET rise time = 62.5 x TRISE1[7:0]_Dns

Default: 0_B

Datasheet

147

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Effective MOSFET rise and fall times of PWM channel 2

TRISE_FALL2

Effective PWM MOSFET rise and fall times PWM2 (1 1000_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TFALL2

TRISE2

r

Field

Bits

Type

Description

MOSFET fall time of PWM Channel 2

TFALL2

15:8

r

MOSFET fall time = 62.5 x TFALL2[7:0]_Dns

Default: 0_B

TRISE2

7:0

r

MOSFET rise time of PWM Channel 2

MOSFET rise time = 62.5 x TRISE2[7:0]_Dns

Default: 0_B

Datasheet

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2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Effective MOSFET rise and fall times of PWM channel 3

TRISE_FALL3

Effective PWM MOSFET rise and fall times PWM3 (1 1001_B)Reset Value: 0_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TFALL3

TRISE3

r

Field

Bits

Type

Description

MOSFET fall time of PWM Channel 3

TFALL3

15:8

r

MOSFET fall time = 62.5 x TFALL3[7:0]_Dns

Default: 0_B

TRISE3

7:0

r

MOSFET rise time of PWM Channel 3

MOSFET rise time = 62.5 x TRISE3[7:0]_Dns

Default: 0_B

Datasheet

149

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Register specification

Device Identifier

DEVID

Device Identifier

(1 1111_B)Reset Value: 0000 0001_B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reser

ved

Reser

ved

Reserved

DEV_ID

r

Field

Bits

Type

Description

Reserved

DEV_ID

15

r

Reserved. Always read as ‘0’

Reserved. Always read as ‘0’.

Reserved.

14:8

7

6:5

4:3

2:0

Reserved.

Device derivative identifier

000_BReserved

001_BTLE92108-232

010_BReserved

011_BTLE92108-231

100_BReserved

101_BReserved

110_BReserved

111_BReserved

Datasheet

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Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Application information

10

Application information

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

EMC Filter

VBAT

Optional

Safe Switch

CSIP1

CSIN1

Temperature warning

and shutdown

CSIN1

Charge Pump

DH

GH1

SH1

VS

VCP

GH2

SH2

UV & OV

Detection

VDS

Monitoring

M

Voltage Regulator / System Basis

Chip

GL1

GH2

GL2

VCC1

SH2

GL2

CSIN1

EN

VDD

Internal Supply

GH3

SH3

GH4

SH4

Control Logic

M

SDI

SDO

SCLK

CSN

GL3

GH4

GL4

24-bit SPI

SH4

GL4

CSIP2

CSIN2

PWM1

PWMx

Mapping

PWM2

PWM3

GH5

SH5

GL5

GH6

DH

EN

Watchdog

GH6

SH6

GL6

MOSFET

Control

M

GH7

SH7

GL6

Microcontroller

Diagnostic

DH

GL7

GH8

SH8

Protections

GH8

SH8

GL8

CS Gain Config.

GL8

SL

Prog. Gain

Not required

CSIN1

RCSO1

CSO1

CSA1

CSIP1

CSIN2

CSIP2

CCSO1

RCSO2

Prog. Gain

Optional external

components

CSO2

CSA2

CCSO2

GND

Not required

Figure 50 Application diagram TLE92108-232QX

Note:

This is a simplified example of an application circuit. The function must be verified in the real

application.

The charge pump buffer capacitor between VS and CP must have a capacitance equal or higher than 470 nF

for a stable operation. A higher capacitance can be used to reduce the voltage ripples caused by the charge of

the gate of the external MOSFETs during PWM operation.

The flying capacitors between CPC1N/CPC1P and CPC2N/CPC2P must be as close as possible to the TLE92108-

232QX.

The decoupling capacitors between VS/GND and VDD/GND must be as close as possible to the TLE92108-

232QX and short PCB tracks to the GND plane.

A resistor (RCSOx) and a capacitor (CCSOx) can be placed (not mandatory) at the output of the current sense

amplifiers.

Datasheet

151

Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Application information

The device does not need any resistor at the output of the current sense amplifiers. However, if a resistor is

used by the application, RCSOx must be higher than 1 kΩ. This resistor causes additional current consumption

from VDD, which is not taken into account in the electrical characteristics of the datasheet.

CCSOx must be between 10 pF and 400 pF. For a fast reaction time of the CSA output, it is recommended to

keep CCSOx to 10 pF.

If a filter is used at the inputs of the current sense amplifier, the serial resistor may not exceed 5 Ω.

It is possible that the MOSFET gate voltage goes below the source voltage during the commutation of a half-

bridge. This depends on the stray inductances at the drain and the source of the MOSFET, the speed of the

commutation and the ratio between the MOSFET Gate-Source and Gate-Drain capacitances.

If V_GATE- V_SOURCE< -0.6 V, a series resistor (e.g. 4.7 Ω ) in series to GHx and GLx are recommended to limit current

delivered by the gate driver during the commutation.

Shunt resistor in the motor phase

When the shunt resistor is placed in the motor phase, it is highly recommended to apply the PWM to the half-

bridge which is not connected to the shunt resistor (Figure 51). This avoids a high common mode swing at the

inputs of the current sense amplifier.

The drain-source monitoring of the monitoring of the drain-source overvoltage of the high-side MOSFETs

must be set to DH - VSHx. Refer to VDS1, VDS2, HBxD bits.

VS

DH

ON

PWM

M

ON

PWM

CSIP1

CSIN1

CSIP1

CSIN1

Figure 51 PWM with Shunt resistance in the motor phase

For a proper off-state diagnostic for with the shunt resistor in the motor phase, the corresponding current

sense amplifier (CSA) must be deactivated. Otherwise, the activated CSA draws current from its inputs,

preventing the internal pull-up source to set the SHx pin to high.

Datasheet

152

Rev. 1.0

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TLE92108-232QX

Multiple MOSFET Driver IC

Package outlines

11

Package outlines

0ꢀ9 MAXꢀ

(0ꢀ65)

11 x 0ꢀ5 = 5ꢀ5

0ꢀ5

0ꢀ1

7

A

0ꢀ03

6ꢀ8

0ꢀ1

+0ꢀ03¹⁾

2)

37

B

36

25

24

48x

0ꢀ08

48

13

1

12

Index Marking

48x

0ꢀ1

0ꢀ4 x 45°

0ꢀ05

Index Marking

0ꢀ23

(0ꢀ35)

M

A B C

(0ꢀ2)

0ꢀ05 MAXꢀ

(5ꢀ2)

(6)

C

1) Vertical burr 0ꢀ03 maxꢀ, all sides

2) These four metal areas have exposed diepad potential

PG-VQFN-48-29, -31-PO V05

Figure 52 PG-VQFN-48¹⁾

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

1) Dimmensions in mm

Datasheet

153

Rev. 1.0

2019-08-29

TLE92108-232QX

Multiple MOSFET Driver IC

Revision History

12

Revision History

Revision Date

Changes

1.0

2019-08-29 First release

Datasheet

154

Rev. 1.0

2019-08-29

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2019-08-29

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

Document reference


型号：	TLE92108-232QX
厂家：	Infineon
描述：	Infineon’s MOTIX™ multiple MOSFET driver can drive up to 16 external n-channel MOSFETs and provides a unique Adaptive MOSFET Control concept to eliminate end-of-line calibration to MOSFET characteristic spreads and guarantees an optimized balancing between power dissipation and EMC behavior. Outstanding low sleep current, advanced protection and diagnostic makes the device to an optimal solution for automotive applications like seat and power lift gate control and various use cases in body control module (BCM) as centralized door lock or washer pumps. An integrated motor brake function is furthermore increasing the reliability and protection for the system. Last but not least, it can control half-bridges with dual supply.
文件：	总155页 (文件大小：4130K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLE92108-232QX [INFINEON]

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