TLE92464EDHP [INFINEON]
Compared to the existing TLE92464ED, the TLE92464EDHP offers higher accuracy performances, in particular:;
| 型号： | TLE92464EDHP |
| 厂家： | 
Infineon |
| 描述： | Compared to the existing TLE92464ED, the TLE92464EDHP offers higher accuracy performances, in particular: |
| 文件： | 总97页 (文件大小：4139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Quality Requirement Category: Automotive
Features
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High current control accuracy
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<±± ꢀm uꢁ to 1200 ꢀm initially (TJ = -40 - 150°C, VBmT = 9 - 16 V)
<±0ꢂ.8 uꢁ to 1200 ꢀm including aging (TJ = -40 - 150°C, VBmT = 9 - 16 V)
<±18 uꢁ to 1500 ꢀm including aging (TJ = -40 - 150°C, VBmT = 6 - 1. V)
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Four indeꢁendent low side channels with integrated MOSFETs (RDSon = 115 ꢀΩ)
Prograꢀꢀable setꢁoint froꢀ 0 ꢀm to 1ꢂ5 m
Load current including dither 1ꢂ. m
Current in ꢁarallel channel ꢀode 2ꢂ7 m
Integrated dither generator with ꢁrograꢀꢀable aꢀꢁlitude, frequency and waveforꢀ
15 bit current setꢁoint resolution
Integrated sense resistor RSHUNT = 140 ꢀΩ
Excellent iꢀꢀunity to large load suꢁꢁly voltage changes
Oꢁeration down to ±ꢂ5 V at VDD ꢁin
±2 bit SPI with . bit CRC and SPI watchdog
Soꢁhisticated ꢁrotection and diagnostic functions for each channel in on and off state
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Indeꢁendent therꢀal shutdown for each channel
Diagnostic Function (Oꢁen Load, Short Circuit Ground, Overcurrent)
Voltage ꢀonitoring
Overteꢀꢁerature ꢁrotection
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Two indeꢁendent current feedback ꢁaths
Integrated systeꢀ clock with clock watchdog
Teꢀꢁerature range -40°C to 175 °C
Sꢀall ꢁower ꢁackage PG-DSO-±6-72
Green Product (RoHS coꢀꢁliant)
Pb-free (RoHS coꢀꢁliant) ꢁackage
mEC-Q100 Grade 0 qualified
ISO 26262 Safety Eleꢀent out of Context for safety requireꢀents uꢁ to mSIL C
Potential applications
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Variable force solenoids (eꢂgꢂ autoꢀatic transꢀission and e-mxle)
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Other constant current solenoids
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Idle air control
Exhaust gas recirculation
Vaꢁor ꢀanageꢀent valve
Susꢁension control
Datasheet
wwwꢂinfineonꢂcoꢀ
Please read the sections "Iꢀꢁortant notice" and "Warnings" at the end of this docuꢀent
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Product validation
Product validation
Qualified for autoꢀotive aꢁꢁlications with higher teꢀꢁerature requireꢀentsꢂ Product validation according to
mEC-Q100, Grade 0ꢂ
Product type & package table
Product type
Package
Marking
TLE92464EDHP
PG-DSO-±6 Dual-Gauge (±00 ꢀil)
TLE92464EDHP
Description
The TLE92464EDHP is a flexible, ꢀonolithic solenoid driver IC designed for the control of linear solenoids in
autoꢀatic transꢀissions, electronic stability control, active susꢁension and e-mxle aꢁꢁlicationsꢂ
The TLE92464EDHP is a four channel low-side solenoid driver IC with high current accuracyꢂ The device
ꢁrovides an inital current accuracy of less than ±± ꢀm uꢁ to 1200 ꢀm current rangeꢂ Including life tiꢀe, the
current accuracy is less than ±0ꢂ.8 uꢁ to 1200 ꢀmꢂ Over the full teꢀꢁerature, battery and current range
(1500 ꢀm in single channel ꢀode, 2700 ꢀm in ꢁarallel channel ꢀode) the control error is less than ±18ꢂ
The device includes the drive transistors and the current sensing resistors to ꢀiniꢀize the nuꢀber of external
coꢀꢁonentsꢂ Target currents froꢀ 0 to 1500 ꢀm can be ꢁrograꢀꢀed with a resolution of 15 bitꢂ The device
suꢁꢁorts dither currents uꢁ to 1.00 ꢀmꢂ The dither generator suꢁeriꢀꢁoses a triangular or traꢁezoidal
waveforꢀ with ꢁrograꢀꢀable aꢀꢁlitude, frequency and shaꢁe on the ꢁrograꢀꢀed current setꢁointꢂ m ±2 bit
SPI interface is used to control the 4 channels and ꢀonitor the status of the diagnostic functionsꢂ The SPI
coꢀꢀunication is secured with an . bit CRC and a ꢁrograꢀꢀable tiꢀeout watchdogꢂ
mn active low reset inꢁut (RESN) is used to disable all channels and reset the internal registers to the default
valuesꢂ mn active high enable ꢁin (EN) enables or disables the outꢁut channels without disabling the SPI
interfaceꢂ m fault outꢁut ꢁin (FmULTN) signal can be used as external interruꢁt to the ꢀicrocontroller whenever a
fault is detectedꢂ
Datasheet
2
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Table of contents
Table of contents
Features ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ1
Potential applications ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 1
Product validation ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 2
Product type & package table ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 2
Description ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 2
Table of contents ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ±
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Block diagram ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 6
Pin configuration ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ7
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Electrial characteristics and parameters ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ9
mbsolute ꢀaxiꢀuꢀ ratings ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ9
mbsolute ꢀaxiꢀuꢀ voltage ratings ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ9
mbsolute ꢀaxiꢀuꢀ current ratings ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ10
mbsolute ꢀaxiꢀuꢀ teꢀꢁerature ratings ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 10
ESD Robustness ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 11
Functional range ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 11
Functional range ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 11
Paraꢀeter above 150°C ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 1±
Therꢀal resistance ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 1±
±ꢂ1ꢂ1
±ꢂ1ꢂ2
±ꢂ1ꢂ±
±ꢂ1ꢂ4
±ꢂ2
±ꢂ2ꢂ1
±ꢂ2ꢂ2
±ꢂ2ꢂ±
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4ꢂ1
Functional description ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 14
Power suꢁꢁly ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 14
TDS_Power Suꢁꢁly ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 14
TDS_Voltage ꢀonitoring ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 14
Electrical characteristics ꢁower suꢁꢁly ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 15
Inꢁut / Outꢁut ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 16
TDS_Clock ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ16
TDS_Clock Watchdog ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 17
TDS_I/O Pins ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ17
Electrical characteristics I/O ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 1.
IC Oꢁeration states ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 19
TDS_IC Oꢁeration states ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 19
Channel ꢀodes ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 21
TDS_Channel Modes ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ21
Channel Modes ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 21
TDS_Measureꢀent Mode - (4/6CHx) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 21
TDS_mdditional Inforꢀation Channel Modes ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 21
Power stages ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 21
TDS_Channel overview - (4CHx) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ21
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Datasheet
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Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Table of contents
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TDS_Parallel channel oꢁeration - (4CHx) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ22
Electrical characteristics ꢁower stages ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 2±
Current control ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 2±
Current accuracy overview ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 2±
Integrating Current Controller (ICC) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 24
Electrical characteristics current control ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 2.
Dither ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ29
TDS_Dither configuration ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 29
TDS_Dither ꢁaraꢀeter uꢁdate ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±0
TDS_Dither PWM synchronization ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±1
TDS_Only ICC ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±1
TDS_Dither setꢁoint synchronization ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ±1
TDS_Only ICC ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±2
TDS_Deeꢁ dither ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±2
TDS_ICC only ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±2
Direct Drive ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ±2
TDS_Direct Drive ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±2
Diagnostic functions ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±2
TDS_Overview ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±2
TDS_Oꢁen Load/Short to Ground (OLSG) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±4
TDS_OLSG Warning ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ±6
TDS_Oꢁen load (OL) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±7
TDS_Short circuit ground (SG) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±7
TDS_Overcurrent (OC) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±.
TDS_Register/OTP ECC ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ±9
TDS_Built in Self Test (BIST) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±9
Electrical characteristics diagnostic functions ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ±9
Current suꢁervision ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 40
TDS_Indeꢁendent current feedback ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ40
TDS_mverage feedback values ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 41
TDS_Uꢁdate/Freeze Mechanisꢀ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 42
TDS_Iavg16, ꢀiniꢀuꢀ/ꢀaxiꢀuꢀ current/PWM feedback ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 4±
Protection functions ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ44
TDS_Overteꢀꢁerature ꢁrotection ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ44
TDS_Overcurrent ꢁrotection ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ44
Electrical characteristics ꢁrotection functions ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 45
4ꢂ.ꢂ1
4ꢂ9
4ꢂ9ꢂ1
4ꢂ9ꢂ2
4ꢂ9ꢂ±
4ꢂ9ꢂ4
4ꢂ9ꢂ5
4ꢂ9ꢂ6
4ꢂ9ꢂ7
4ꢂ9ꢂ.
4ꢂ9ꢂ9
4ꢂ10
4ꢂ10ꢂ1
4ꢂ10ꢂ2
4ꢂ10ꢂ±
4ꢂ10ꢂ4
4ꢂ11
4ꢂ11ꢂ1
4ꢂ11ꢂ2
4ꢂ11ꢂ±
5
5ꢂ1
5ꢂ1ꢂ1
5ꢂ1ꢂ2
5ꢂ1ꢂ±
5ꢂ1ꢂ4
Serial peripheral interface (SPI) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ46
Descriꢁtion of interface ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 46
TDS_General inforꢀation ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 46
TDS_Cyclic redundancy check (CRC) ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 46
TDS_Tiꢀing Diagraꢀ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 47
Electrical characteristics SPI interface ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 47
Datasheet
4
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Table of contents
5ꢂ2
Descriꢁtion of ꢁrotocol ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 49
TDS_Data flow ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 49
TDS_SPI watchdog ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 49
SPI fraꢀe definition ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 49
Register descriꢁtion ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 5±
Overview of Register Tyꢁes ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 5±
Central registers ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 54
Channel registers ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ74
5ꢂ2ꢂ1
5ꢂ2ꢂ2
5ꢂ2ꢂ±
5ꢂ±
5ꢂ±ꢂ1
5ꢂ±ꢂ2
5ꢂ±ꢂ±
6
Application information ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 94
6ꢂ1
TDS_mꢁꢁlication inforꢀation ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 94
7
Package dimensions ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ95
7ꢂ1
TDS_Package diꢀensions ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ95
Revision history ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ96
Disclaimer ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ ꢂ 97
Datasheet
5
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Block diagram
1
Block diagram
Four Channel low-side
Solenoid Driver IC
Load
Diagnosis
LOAD0
FWD0
Channel
Logic,
Current
Control,
Dither
Current
Sense
shunt0
R
Overcurrent
Protection
Power Supply
VBAT
VDD
GND
Undervoltage/
Overvoltage
Detection
Low Side
Gate Control
DMOS0
Temperature Sense
GNDP0
LOAD1
Load
Diagnosis
PLL with
Watchdog
Channel
Logic,
Current
Sense
shunt1
R
CLK
RESN
Current
Control,
Dither
Overcurrent
Protection
FWD1
EN
Low Side
Gate Control
DMOS1
FAULTN
Temperature Sense
GNDP1
LOAD2
Central Logic
Load
Diagnosis
DRV0
DRV1
DRV2
DRV3
Channel
Logic,
Current
Control,
Dither
Current
Sense
shunt2
R
Overcurrent
Protection
FWD2
Low Side
Gate Control
DMOS2
Temperature Sense
GNDP2
LOAD3
Load
Diagnosis
SPI
Watchdog
VIO
SCK
CSN
SI
Channel
Logic,
Current
Control,
Dither
Current
Sense
shunt3
R
SPI
Overcurrent
Protection
FWD3
Low Side
Gate Control
DMOS3
SO
Temperature Sense
GNDP3
Figure 1
Block diagram
Datasheet
6
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Pin configuration
2
Pin configuration
LOAD0
FWD0
GNDP0
GND
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
LOAD3
FWD3
GNDP3
GND
VBAT
GND
GND
VDD
DRV3
DRV2
DRV1
DRV0
CLK
2
3
4
5
CSN
SCK
6
SI
7
VIO
SO
GND
RESN
GND
8
9
10
11
12
13
14
15
16
17
18
FAULTN
GND
EN
GND
GND
GNDP2
FWD2
LOAD2
GNDP1
FWD1
LOAD1
Figure 2
Pin assignment
Pin definitions and functions
Table 1
Pin definition and functions
Pin
1
Symbol
LOmD0
FWD0
GNDP0
GND
Function
Outꢁut; for channel 0ꢂ
2
Free wheeling diode; for channel 0ꢂ
±
Ground; for channel 0 ꢁower stageꢂ
Ground; connect to GNDꢂ
4
5
CSN
SPI chiꢁ select inꢁut; digital inꢁut: ±ꢂ± V or 5ꢂ0 V logic levelsꢂ
SPI clock inꢁut; digital inꢁut: ±ꢂ± V or 5ꢂ0 V logic levelsꢂ
SPI inꢁut; digital inꢁut: ±ꢂ± V or 5ꢂ0 V logic levelsꢂ
Suꢁꢁly SPI Slave Out (SO) ꢁin; connected to ±ꢂ± V or 5ꢂ0 V suꢁꢁlyꢂ
SPI outꢁut; ꢁush ꢁull outꢁut coꢀꢁatible to ±ꢂ± V or 5ꢂ0 V logic levelsꢂ
Ground; signal groundꢂ Internally connected to cooling tabꢂ
Control inꢁut; digital inꢁut: ±ꢂ± V or 5ꢂ0 V logic levelsꢂ mctive low reset inꢁutꢂ
Ground; signal groundꢂ Internally connected to cooling tabꢂ
Status outꢁut; oꢁen drain outꢁutꢂ In case not used, keeꢁ oꢁenꢂ
Ground; connect to GNDꢂ
6
SCK
7
SI
.
VIO
9
SO
10
11
12
1±
14
15
16
17
1.
19
GND
RESN
GND
FmULTN
GND
EN
Control inꢁut; digital inꢁut: ±ꢂ± V or 5ꢂ0 V logic levelsꢂ mctive high enable inꢁutꢂ
Ground; ground connection for channel 1 ꢁower stageꢂ
Free wheeling diode; for channel 1ꢂ
GNDP1
FWD1
LOmD1
LOmD2
Outꢁut; for channel 1ꢂ
Outꢁut; for channel 2ꢂ
(table continues...)
Datasheet
7
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Pin configuration
Table 1
(continued) Pin definition and functions
Pin
20
21
22
2±
24
25
26
27
2.
29
±0
±1
±2
Symbol
FWD2
GNDP2
GND
Function
Free wheeling diode; for channel 2ꢂ
Ground; ground connection for channel 2 ꢁower stageꢂ
Ground; connect to GNDꢂ
GND
Ground; signal groundꢂ Internally connected to cooling tabꢂ
Clock inꢁut; Main systeꢀ clockꢂ
CLK
DRV0
DRV1
DRV2
DRV±
VDD
Direct drive inꢁut for channel 0: ±ꢂ± V or 5ꢂ0 V logical levelsꢂ
Direct drive inꢁut for channel 1: ±ꢂ± V or 5ꢂ0 V logical levelsꢂ
Direct drive inꢁut for channel 2: ±ꢂ± V or 5ꢂ0 V logical levelsꢂ
Direct drive inꢁut for channel ±: ±ꢂ± V or 5ꢂ0 V logical levelsꢂ
Suꢁꢁly voltage; suꢁꢁlies digital circuitsꢂ Connected to 5ꢂ0 V suꢁꢁly voltageꢂ
Ground; signal groundꢂ Internally connected to cooling tabꢂ
Ground; connect to GND
GND
GND
VBmT
Suꢁꢁly voltage; connected to battery voltage with reverse ꢁrotection diode and
filter against EMCꢂ
±±
±4
±5
±6
±7
GND
Ground; connect to GNDꢂ
GNDP±
FWD±
LOmD±
Ground; for channel ± ꢁower stageꢂ
Free wheeling diode; for channel ±ꢂ
Outꢁut; for channel ±ꢂ
Cooling Taꢁ
Connect externally to GND and heat sink area
Datasheet
.
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Electrial characteristics and parameters
3
Electrial characteristics and parameters
3.1
Absolute maximum ratings
3.1.1
Absolute maximum voltage ratings
Table 2
Absolute maximum voltage ratings
TJ = -40°C to 150°C; all voltages with resꢁect to ground, ꢁositive current flowing into ꢁin (unless
otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Maxꢂ suꢁꢁly
VDD,ꢀax
VBmT,ꢀax
VVIO,ꢀax
-0ꢂ±
-0ꢂ±
-0ꢂ±
-0ꢂ±
–
–
–
–
19
40
19
19
V
V
V
V
voltage (VDD)
Maxꢂ suꢁꢁly
voltage (VBmT)
Maxꢂ suꢁꢁly
voltage (VIO)
Maxꢂ digital
inꢁut ꢁin
voltage (CLK,
RESN, EN,
DRVx, SCK,
CSN, SI)
VCLK,ꢀax
VRESN,ꢀax
VEN,ꢀax
VDRVx,ꢀax
VSCK,ꢀax
VCSN,ꢀax
VSI,ꢀax
Maxꢂ oꢁen
drain outꢁut
voltage
VFmULTN,ꢀax -0ꢂ±
–
19
V
(FmULTN)
Maxꢂ Push Pull VSO,ꢀax
-0ꢂ±
–
–
19
40
V
V
Ouꢁut (SO)
Maxꢂ LOmDx
voltage
VLOmDx,ꢀax
-0ꢂ±1)
1) During negative ꢁulses (VLOmDx < -0ꢂ±
V) the ꢀaxiꢀuꢀ energy of ELOmDx = |-
VLOmDx*(ILOmDx+IFWDx)*tꢁulse| <= 2 ꢀJ shall not be
violatedꢂ
Maxꢂ FWDx
voltage
VFWDx,ꢀax
-0ꢂ±1)
-0ꢂ±
–
–
40
V
V
1) During negative ꢁulses (VFWDx < -0ꢂ±
V) the ꢀaxiꢀuꢀ energy of EFWDx = |-
VFWDx*(ILOmDx+IFWDx)*tꢁulse| <= 2 ꢀJ shall not be
violatedꢂ
Maxꢂ GNDPx
voltage
VGNDPx,ꢀax
0ꢂ±
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Electrial characteristics and parameters
3.1.2
Absolute maximum current ratings
Table 3
Absolute maximum current ratings
TJ = -40°C to 150°C; all voltages with resꢁect to ground, ꢁositive current flowing into ꢁin (unless
otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Maxꢂ current
range
IFWDx,ꢀax
ILOmDx,ꢀax
-2
–
2
m
DC
In the case of an active overcurrent shutdown
the sꢁecification at the LOmDx ꢁin can be
exceededꢂ
Maxꢂ Outꢁut
Current
(FmULTN)
IFmULTN,ꢀax
-5
–
0
ꢀm
Maxꢂ outꢁut
current (SO)
ISO,ꢀax
-5
-5
-
5
5
ꢀm
ꢀm
DC
Maxꢂ inꢁut
current (CLK,
RESN, EN,
DRVx, SCK,
CSN, SI)
ICLK,ꢀax
IRESN,ꢀax
IEN,ꢀax
IDRVx,ꢀax
ISCK,ꢀax
ICSN,ꢀax
ISI,ꢀax
0
Maxiꢀuꢀ allowed forward and reverse current
through ESD structureꢂ
3.1.2.1
TDS_max_rating
Note:
Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Integrated protection
functions are designed to prevent IC destruction under fault conditions described in the data sheet.
Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
3.1.3
Absolute maximum temperature ratings
Table 4
Absolute maximum temperature ratings
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Junction
teꢀꢁerature
(TJ)
TJ
-40
–
150
°C
Extended
TJext
150
–
175
°C
ꢁaraꢀeter deviations are ꢁossible
junction
teꢀꢁerature
(TJ extended)
(table continues...)
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Electrial characteristics and parameters
Table 4
(continued) Absolute maximum temperature ratings
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Storage
teꢀꢁerature
(TSTG)
TSTG
-55
–
150
°C
3.1.4
ESD Robustness
Table 5
ESD Robustness
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note or condition
ESD
robustness
HBM (all ꢁins)
VHBMall
-2
–
2
kV
ESD robustness Huꢀan Body Model
(HBM) according to mNSI/ESDm/JEDEC JS-001ꢂ
ESD
VHBMglobal
-4
–
4
kV
VBmT, LOmDx vsꢂ all Grounds shorted
ESD robustness Huꢀan Body Model
(HBM) according to mNSI/ESDm/JEDEC JS-001ꢂ
robustness
HBM (VBmT,
LOmDx)
ESD
VCDMall
-500
-750
–
–
500
750
V
V
ESD robustness Charged Device Model (CDM)
according to JEDEC JESD22-C101
robustness
CDM (all ꢁins)
ESD
VCDMcorner
ESD robustness Charged Device Model (CDM)
according to JEDEC JESD22-C101
robustness
CDM (corner
ꢁins)
3.2
Functional range
3.2.1
Functional range
Table 6
Functional range
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note or condition
Functional
VDD
4ꢂ5
–
5ꢂ5
V
V
range (VDD)
Extended
Functional
range (VDD)
VDD,ext
±ꢂ5
–
19
Outside of the norꢀal Functional Range of VDD
:
•
VDD < VDD,UV,TH: SPI coꢀꢀunication
functional;Power-stage off
•
VDD > VDD,OV,TH: SPI coꢀꢀunication
functional; Power-stage off
Functional
range (VBmT)
VBmT
6
–
1.
V
(table continues...)
Datasheet
11
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Electrial characteristics and parameters
Table 6
(continued) Functional range
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Extended
functional
range (VBmT)
VBmT,ext
4
–
±.
V
Outside of the norꢀal functional VBmT range
ꢁaraꢀeter deviations are ꢁossible:
•
•
VBmTL 4 V…6 V: Paraꢀeter deviation ꢁossible
VBmTH 1. V…±. V: Paraꢀeter deviation
ꢁossible
Functional
range (VIO)
VIO
±ꢂ0
5ꢂ5
–
–
5ꢂ5
19
V
V
Extended
functional
range (VIO)
VIO,ext
Paraꢀeter deviation ꢁossible
Functional
VFWDx
VLOmDx
fCLK
-0ꢂ±1)
-0ꢂ±1)
1
–
–
–
40
40
.
V
1) During negative ꢁulses (VFWDx < -0ꢂ±
V) the ꢀaxiꢀuꢀ energy of EFWDx = |-
VFWDx*(ILOmDx+IFWDx)*tꢁulse| <= 2 ꢀJ shall not be
violatedꢂ
1) During negative ꢁulses (VLOmDx < -0ꢂ±
V) the ꢀaxiꢀuꢀ energy of ELOmDx = |-
VLOmDx*(ILOmDx+IFWDx)*tꢁulse| <= 2 ꢀJ shall not be
violatedꢂ
range (FWDx)
Functional
range (LOmDx)
V
Functional
range clock
frequency
(CLK)
MHz
Systeꢀ clock
frequency
fSYS
27ꢂ5 2.
2.ꢂ5 MHz
29 MHz
4000 Hz
For use of external clock, clock divider ꢀust be
set accordingly
Systeꢀ clock
watchdog
fSYS,WD
fPWM
TJ
27
–
-
Target PWM
frequency
110
-40
150
PWM frequency control configuration range
Junction
teꢀꢁerature
–
–
150
175
°C
°C
Extended
junction
teꢀꢁerature
TJ,ext
In the teꢀꢁerature range of 150 - 175°C
ꢁaraꢀeter deviations are ꢁossible
3.2.1.1
TDS_functional_range
Note:
Within the functional range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given by the related "electrical characteristics"
table.
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Electrial characteristics and parameters
3.2.2
Parameter above 150°C
Table 7
Parameter above 150°C
TJ = 150°C to 175°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground,
ꢁositive current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Shunt
Rshunt
-
-
190
ꢀΩ
resistance
ON resistance RDSON
-
-
215
6
ꢀΩ
mverage
current control
error, absolut
Ierr,absolut
-6
–
ꢀm
Iset = 10 - 500ꢀm
VBmT = 1±V
Single channel oꢁeration
mverage
Ierrꢂabsolut,ꢁar -12
-
12
ꢀm
Iset,ꢁar = 20 - 1000 ꢀm
VBmT = 1±V
Parallel channel oꢁeration
current control
error, absolut -
ꢁarallel
mverage
Ierrꢂrelative
-1ꢂ2
-
–
-
1ꢂ2
8
Iset > 500ꢀm; single channel oꢁeration
Iset,ꢁar > 1000ꢀm; ꢁarallel channel oꢁeration
VBmT = 1±V
current control
error, relative
Diagnosis
Current 0
IHS
ILS
1±0
µm
<I_DImG> = 00B
3.2.3
Thermal resistance
Table 8
Thermal resistance
Parameter
Symbol
RthJC
RthJm
Values
Min. Typ. Max.
Unit
Note or condition
Junction to
case
–
–
±
K/W
K/W
Junction to
aꢀbient
–
1.ꢂ5
–
Deꢁending on the ꢀounting conditionsꢂ
Sꢁecified RthJm value is according to JEDEC
JESD51 -5, -7 at natural convection on FR4
2s2ꢁ board; the ꢁroduct (chiꢁ and ꢁackage) was
siꢀulated on a 76ꢂ2 x 114ꢂ± x 1ꢂ5 ꢀꢀ board with
2 inner coꢁꢁer layers (2 x 70 μꢀ, 2 x ±5 μꢀ CU)ꢂ
Datasheet
1±
Revꢂ 1ꢂ0
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
4
Functional description
4.1
Power supply
4.1.1
TDS_Power Supply
VDD pin
The VDD ꢁin and GND ꢁin are the suꢁꢁly and ground ꢁins for the digital circuit blocksꢂ The current through
these ꢁins contain high frequency coꢀꢁonentsꢂ Decouꢁling with ceraꢀic caꢁacitors and careful PCB layout are
required to obtain good EMC ꢁerforꢀanceꢂ
VIO pin
The VIO ꢁin suꢁꢁlies the SPI outꢁut ꢁin (SO)ꢂ It should be connected to the I/O suꢁꢁly of the ꢀicrocontroller
(±ꢂ± V or 5ꢂ0 V)ꢂ The VIO voltage level can be configured by the <VIO_SEL> bit in the GLOBmL_CONFIG registerꢂ
VBAT pin
The VBmT ꢁin is an inꢁut ꢁin used to ꢀeasure and ꢀonitor the battery voltage and feed diagnosis current
sourceꢂ The ꢁin should be connected to the reverse ꢁrotected battery rail and decouꢁled with a ceraꢀic
caꢁacitorꢂ
GND/GNDP pin
GND ꢁins are the ground ꢁins for the logic while the GNDP ꢁins are the ꢁower ground ꢁins for the ꢁower stagesꢂ
It is recoꢀꢀended to connect all GNDP ꢁins to the GND net externallyꢂ
Power On Reset
mn internal ꢁower on reset (POR) circuit holds the device in a reset state if the internal logic is not
oꢁerational due to undervoltageꢂ The ꢁower on reset is released afte all suꢁꢁlies are within their functional
range and the Reset Duration Tiꢀe tPOR has elaꢁsedꢂ The SPI interface can be accessed afte the ꢁower on reset
tiꢀeꢂ mny ꢁower on reset will set the bit <POR_EVENT> in the GLOBmL_DImG0 register to 1ꢂ This can be used to
check whether a ꢁower on reset has haꢁꢁened since the bit was set to 0ꢂ
4.1.2
TDS_Voltage monitoring
The voltage levels of the suꢁꢁly ꢁins VBmT, VIO and VDD and all internal voltages (mDC reference voltages, internal
suꢁꢁly voltages) are ꢀonitoredꢂ m voltage fault is detected if a voltage exceeds the corresꢁonding overvoltage
(OV) threshold or falls below the resꢁective undervoltage (UV) thresholdꢂ mꢁart froꢀ a VBmT OV/UV, an under/
overvoltage fault disables the outꢁut stages by setting all <EN_CH> bits to "0"ꢂ mꢁart froꢀ a VBmT and internal
ꢁre-regulator (<VPRE_OV>) fault, an OV/UV fault condition causes the device to enter the Oꢁeration State Config
Modeꢂ
External suꢁꢁly voltage (VBmT, VIO, VDD) faults are indicated by setting the corresꢁonding indication bit in the
GLOBmL_DImG0 register to 1 while IC internal voltage faults are listed in the GLOBmL_DImG1 registerꢂ Voltage
fault indication bits are cleared on write onlyꢂ The bit <SUP_NOK_INT> and < SUP_NOK_EXT> in the FB_STmT
register ꢁrovide a suꢀꢀarized indication if any internal or external voltage fault has been detectedꢂ
The under and overvoltage thresholds of VBmT can be adaꢁted and be set in the VBmT_TH registerꢂ
VBAT, UV, TH = < VBAT_UV_TH > · 0 . 16208V
VBAT, OV, TH = < VBAT_OV_TH > · 0 . 16208V
Equation 1
The ꢀeasured voltages of VIO and VDD are ꢁrovided in the FB_VOLTmGE1 registerꢂ The VBmT voltage level can be
readout froꢀ the FB_VOLTmGE2 registerꢂ
The voltage ꢀonitoring ꢀechanisꢀ of external and internal voltages can be tested by setting the
<UV_OV_SWmP> bit in the GLOBmL_CONFIG register to "1"ꢂ If the test is successful, the OV/UV detection
bits <VDD_OV/UV>, <VIO_OV/UV>, <VBmT_OV/UV>, <VDD2V5_OV/UV>, <VR_IREF_OV/UV>, <VPRE_OV> and
Datasheet
14
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
<REF_OV/UV> are setꢂ The ꢁower on reset (POR) due to an under or overvoltage can be tested by setting
the bits <V1V5_OV_TEST> or <V1V5_UV_TEST> in the GLOBmL_CONFIG register to "1"ꢂ
4.1.3
Electrical characteristics power supply
Table 9
Electrical characteristics power supply
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground,
ꢁositive current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
VBmT current
consuꢀꢁtion
norꢀal ꢀode
IVBmT
–
–
1
ꢀm
VBmT = 1. V
Diagnosis off
VBmT current
consuꢀꢁtion
inactive ꢀode
IVBmT,inactive
–
–
10
µm
VBmT = 1. V
VDD = 0 V = VIO
VDD current
IVDD
IVIO
10
–
21
–
±0
1
ꢀm
ꢀm
VDD = 5ꢂ5 V
consuꢀꢁtion
VIO current
consuꢀꢁtion
VDD = 5ꢂ5 V
VCSN > VCSN,high
VBmT
VBmT,UV,TH
VBmT,OV,TH
VDD,UV,TH
VDD,OV,TH
(x*.-1 x *
(x*.+
V
x = <VBmT_UV_TH>
VBmT voltage is fallingꢂ
undervoltage
threshold
7)*0ꢂ0 0ꢂ162 17)*0ꢂ
1965 0.
020.7
VBmT
overvoltage
threshold
(x*.-1 x*0ꢂ1 (x*.+
7)*0ꢂ0 620. 17)*0ꢂ
V
x = <V_BmT_OV_TH>
VBmT voltage risingꢂ
1965
±ꢂ7
020.7
4ꢂ5
VDD
undervoltage
threshold
–
–
–
–
–
–
–
V
VDD falling
VDD
overvoltage
threshold
5ꢂ5
6ꢂ4
±
V
VDD rising
VIO
VIO,UV,±V±,TH 2ꢂ6
V
VIO falling
undervoltage
threshold ±ꢂ± V
VIO
VIO,OV,±V±,TH ±ꢂ6
4ꢂ1
4ꢂ5
6ꢂ4
0ꢂ1
V
VIO rising
overvoltage
threshold ±ꢂ± V
VIO
undervoltage
threshold 5 V
VIO,UV,5V,TH
±ꢂ7
5ꢂ5
–
V
VIO falling
VIO
overvoltage
threshold 5 V
VIO,OV,5V,TH
V
VIO rising
Power on reset tRESN
tiꢀe initialized
with RESN
ꢀs
Logic circuits are functional afte tRESN
(table continues...)
Datasheet
15
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Table 9
(continued) Electrical characteristics power supply
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground,
ꢁositive current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Power on reset tPOR
tiꢀe initialized
with
undervoltage
reset
–
–
10
ꢀs
Logic circuits are functional afte tPOR
4.2
Input / Output
TDS_Clock
4.2.1
The chiꢁ systeꢀ clock fSYS is generated by an integrated PLL (ꢁhase locked looꢁ) and is used to clock the
internal analog to digital converters and logicꢂ The PLL can be either sourced by an internal oscillator or
an external rectangular clock signal aꢁꢁlied on the CLK-ꢁinꢂ The PLL clock source fCLK can be selected by
ꢁrograꢀꢀing the <EXT_CLK> bit in the CLK_DIV registerꢂ Changing the clock source can only be done in
Oꢁeration State Config Modeꢂ During a change of the clock source, the clock watchdog is disabled and the
<INIT_DONE> bit is clearedꢂ Afte a successful transition of the clock source, the <INIT_DONE> bit in the
FB_STmT register is set to 1 and the clock watchdog is enabledꢂ
CLK
f
PLL
f
SYS
SYS
f
f
CLK
Clock
Watchdog
Control
Logic
MUX
1 / N
PLL
Internal
Oscillator
<EXT_CLK><PLL_REFDIV><PLL_FBDIV>
<CLK_WD_EN>
Figure 3
Clock Generation
The systeꢀ clock frequency fSYS is given by
< PLL_FBDIV >
fSYS = fCLK
·
2 · < PLL_REFDIV >
Equation 2
By selecting an external clock inꢁut, the PLL divider ꢀust be set to ꢀeet the systeꢀ clock frequency fSYS (see
table "Clock control register settings")ꢂ If the internal clock oscillator is used, the contents of the divider bit
fields are ignoredꢂ The values of PLL reference divider <PLL_REFDIV> and PLL feedback divider <PLL_FBDIV>
are located in the CLK_DIV registerꢂ
fCLK
< PLL_REFDIV > = round
1MHz
56MHz·< PLL_REFDIV >
< PLL_FBDIV > =
fCLK
Equation 3
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Table 10
Clock control register settings
fCLK
(MHz)
1
<PLL_REFDIV>
<PLL_FBDIV>
fSYS
(MHz)
Error
(%)
1
1
2
2
±
±
4
4
5
5
6
6
7
7
.
56
±7
56
45
56
4.
56
50
56
51
56
52
56
52
56
2.
27ꢂ75
2.
0ꢂ00
-0ꢂ.9
0ꢂ00
0ꢂ45
0ꢂ00
0ꢂ00
0ꢂ00
0ꢂ45
0ꢂ00
0ꢂ1.
0ꢂ00
0ꢂ60
0ꢂ00
-0ꢂ51
0ꢂ00
1ꢂ5
2
2ꢂ5
±
2.ꢂ1±
2.
±ꢂ5
4
2.
2.
4ꢂ5
5
2.ꢂ1±
2.
5ꢂ5
6
2.ꢂ05
2.
6ꢂ5
7
2.ꢂ17
2.
7ꢂ5
.
27ꢂ.6
2.
4.2.2
TDS_Clock Watchdog
The internal systeꢀ clock fSYS can be suꢁervised by a seꢁarate clock watchdogꢂ The clock watchdog can be
disabled by setting the <CLK_WD_EN> bit in the GLOBmL_CONFIG register to 0ꢂ m change of the clock watchdog
configuration is only ꢁossible in Config Mode and if the <INIT_DONE> bit in the FB_STmT register is 1ꢂ If the
systeꢀ clock fSYS is outside of the allowed frequency range fSYS,WD, a clock watchdog fault is indicated by
setting <CLK_NOK> in the GLOBmL_DImG0 register to 1, all ꢁower stages are disabled and device enters the
Config Modeꢂ In case the clock watchdog detects a too fast clock, the device iꢀꢀediately enters the Critical
Fault Stateꢂ
4.2.3
TDS_I/O Pins
RESN pin
The RESN ꢁin is an active low ꢁinꢂ If this ꢁin is low, all channels are off, the device is in Reset State and all
registers are set to their default valuesꢂ The bit <RES_EVENT> in the GLOBmL_DImG0 register indicates a reset
triggered via the RESN ꢁinꢂ The RESN inꢁut ꢁin is internally ꢁulled low (GND)ꢂ
EN pin
The EN ꢁin is an active high ꢁinꢂ When this ꢁin is low, all channels are turned off. The EN inꢁut ꢁin is internally
ꢁulled low (GND)ꢂ
FAULTN pin
The FmULTN ꢁin is an oꢁen drain outꢁutꢂ The FmULTN ꢁin is initally high, if no fault is ꢁresent afte ꢁower uꢁꢂ
The FmULTN ꢁin is ꢁulled low when the device transitions to the Critical Fault State, the RESN ꢁin is low or an
unꢀasked fault is detectedꢂ Fault inidication on the FmULTN ꢁin can be ꢀasked by setting the aꢁꢁroꢁriate ꢀask
bit in the FmULT_MmSK registersꢂ
•
Channel sꢁecific:
CHx ICC regulation warning
-
Datasheet
17
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
-
-
-
-
-
CHx PWM regulation warning
CHx overteꢀꢁerature warning
CHx oꢁen load
CHx short circuit battery
CHx short circuit ground
•
•
•
•
•
•
•
Central overteꢀꢁerature warning
Central overteꢀꢁerature error
SPI watchdog error
Clock too slow error
Data error
EN ꢁin status indication
Internal/External suꢁꢁly fault
CLK pin
m digital inꢁut clock signal fCLK ꢀust be aꢁꢁlied on the CLK ꢁin if an external clock inꢁut is usedꢂ Using the
internal clock, the ꢁin should be connected to GNDꢂ The CLK inꢁut ꢁin is internally ꢁulled low (GND)ꢂ
DRV pins
The DRV ꢁins enable a direct control of the outꢁut stages, if the channel is configured to Direct Drive Mode via
DRV ꢁinꢂ The DRV inꢁut ꢁins are internally ꢁulled low (GND)ꢂ Unused DRV ꢁins should be connected to GNDꢂ
SI, SO, CSN, SCK pin
The SI, SO, CSN, and SCK ꢁins coꢀꢁrise the SPI interfaceꢂ See SPI chaꢁter for detailsꢂ
4.2.4
Electrical characteristics I/O
4.2.4.1
Control inputs EN, RESN, CLK, DRVx
Table 11
Control inputs EN, RESN, CLK, DRVx
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Digital high
threshold
voltage (EN,
RESN, CLK,
DRVx)
VEN,high
2
–
-
V
VRESN,high
VCLK,high
VDRVx,high
Digital low
threshold
voltage (EN,
RESN, CLK,
DRVx)
VEN,low
-
–
0ꢂ.
-
V
VRESN,low
VCLK,low
VDRVx,low
Digital inꢁut
hysteresis (EN,
RESN, CLK,
DRVx)
VIN_HYS,EN
-
50
ꢀV
VIN_HYS,RESN
VIN_HYS,CLK
VIN_HYS,DRVx
(table continues...)
Datasheet
1.
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Table 11
(continued) Control inputs EN, RESN, CLK, DRVx
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Pull down
current (EN,
RESN, CLK,
DRVx)
IPD,EN
10
–
50
µm
VIN = 0ꢂ. V
IPD,RESN
IPD,CLK
IPD,DRVx
4.2.4.2
FAULTN
Table 12
FAULTN
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground,
ꢁositive current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Outꢁut low
threshold
voltage
VFmULTN,LOW
0
–
0ꢂ4
V
IFmULTN = 2 ꢀm
(FmULTN)
Outꢁut leakage IFmULTN,LGK
current
(FmULTN)
-100
–
100
µm
No fault ꢁresent
0 V < VFmULTN < VIO
4.3
IC Operation states
TDS_IC Operation states
4.3.1
Reset state:
•
The answer to an SPI coꢀꢀand is the 16 bit reꢁly fraꢀeꢂ
•
mll SPI register values are being reset to default when the ꢁroduct leaves the Reset Stateꢂ
Config Mode:
•
•
•
mll channels are disabledꢂ <EN_CH> bits are 0 and cannot be setꢂ
Channel diagnostic is disabled (HS and LS current source are disabled)ꢂ
The Channel Mode, the global configuration, the ꢁarallel channel oꢁeration and the PLL divider can only be
configured in Config Modeꢂ
Mission Mode:
•
The channels and their resꢁective diagnosis are only functional in Mission Modeꢂ
Critical Fault state:
•
The IC will reꢁly all SPI interactions with the Critical Fault fraꢀeꢂ
•
The FmULTN ꢁin is ꢁulled lowꢂ
The following State Diagraꢀ gives an overview on the transition conditionsꢂ
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
1)POR
OR
RESN pin = low
0
RESET
state
OR-Condition
1)POR
RESN pin = low
OR-Condition
1)POR
RESN pin = low
AND-Condition
No clock too fast fault
Supply ok
RESN pin = high
clock too fast fault
clock too fast fault
3
1
Critical Fault
State
Config
Mode
OR-Condition
1)POR
RESN pin = low
AND-Condition
FB_STAT register:
INIT_DONE=1
OR-Condition
GLOBAL_DIAG0:
SPI_WD_ERR = 1
2)CLK_NOK = 1
<VIO_UV/OV> = 1
<VDD_UV/OV> = 1
GLOBAL_DIAG1:
GLOBAL_DIAG0:
SPI_WD_ERR = 0
CLK_NOK = 0
<VIO_UV/OV> = 0
<VDD_UV/OV> = 0
<VBAT_UV/OV> = 0
<COTW/Ex> = 0
<VDD2V5_UV/OV> = 1
<REF_UV/OV> = 1
<VR_IREF_UV/OV> = 1
<REG_ECC_ERR> = 1
CH_CTRL:
GLOBAL_DIAG1:
<VDD2V5_UV/OV> = 0
<REF_UV/OV> = 0
<VR_IREF_UV/OV> = 0
<REG_ECC_ERR> = 0
DIAG_ERR_CHGR0/1:
<OTW/Ex> = 0
clock too fast fault
OP_MODE = 0
CH_CTRL:
OP_MODE = 1
2
Mission
Mode
1): POR: power on reset
2): Clock too slow fault detected
Figure 4
Operation States and Transitions
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
4.4
Channel modes
4.4.1
TDS_Channel Modes
The IC offtes difftetnꢀ ꢀodes to control the outꢁut stage of a channelꢂ The channel ꢀode can be selected
by ꢁrograꢀꢀing the MODE registerꢂ m change of the channel ꢀode is only ꢁossible in Config Modeꢂ The
ꢀeasurꢀent ꢁeriod Tꢀeas for averaged feedback values deꢁends on the selected channel ꢀode (see chaꢁter
"current suꢁervision")ꢂ
4.4.2
Channel Modes
Channel Mode
Channel off
Measurement Period Tmeas for Feedback Values
No ꢀeasureꢀent active
Current Control ICC
Dither Period TDither
Direct Drive via on-tiꢀe (TON register)
Direct Drive via DRV ꢁin
Dither Period TDither
•
•
If configured Dither Period TDither, else
Tiꢀe between two rising edges at DRV ꢁin
Measureꢀent Mode*
Dither Period TDither
4.4.3
TDS_Measurement Mode - (4/6CHx)
Note:
The current measurement over the shunt can be used for high-precision current measurement
applications. In measurement mode the internal low-side switch is non-conductive.
4.4.4
TDS_Additional Information Channel Modes
Note:
For more details on the "Current Control" and "Direct Drive" Mode please refer to the respective
chapters.
4.5
Power stages
4.5.1
TDS_Channel overview - (4CHx)
There are four indeꢁendent outꢁut channels iꢀꢁleꢀented in this deviceꢂ The outꢁut ꢁowerstage of each
channel consists of a low side n-channel DMOS transistor and a current sensing resistorꢂ The switch and shunt
resistor are ꢁrotected froꢀ external failures by built in overcurrent and overteꢀꢁerature detection circuitsꢂ m
high-side load can be connected to the LOmDx ꢁinꢂ For inductive loads a diode ꢀust be aꢁꢁlied at the FWDx
ꢁin for external freewheelingꢂ The outꢁut voltage slew rate of the ꢁower stages can be ꢁrograꢀꢀed in the
CH_CONFIG registerꢂ
Datasheet
21
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Output-Stage
LOADx
FWDx
ΔΣ - A/D
RShunt
-
setpoint
Current
Controller
PWM
Driver Block
DMOS
+
GNDPx
Dither
Channel x
Figure 5
Channel Block Diagram
4.5.2
TDS_Parallel channel operation - (4CHx)
The IC features a ꢁarallel ꢀode of outꢁut stages to increase the ꢀaxiꢀuꢀ current caꢁability of the deviceꢂ
The channels 0 and ± and the channels 1 and 2 can be connected in ꢁarallelꢂ Channel 0 and 1 are the ꢀaster
channels and channel 2 and ± are the slave channelsꢂ Only the ꢀaster channels can be configured via SPIꢂ The
ꢁarallel channel ꢀode can be enabled or disabled in the CH_CTRL register when the device is in Config Modeꢂ
VBAT
Lload
LOAD
<y>
D
RShunt
<y>
ΔΣ - A/D
<y>
FWD
<y>
Iloadx,y,par
LOAD
<x>
RShunt
<x>
ΔΣ - A/D
<x>
+
FWD
<x>
DMOS
<x>
DMOS
<y>
-
Current
Controller
<x>
PWM
Driver Block
<x>
setpoint
+
GNDP
<y>
Dither
<x>
PWM
Driver Block
<y>
GNDP
<x>
Parallel Channel
Figure 6
Parallel Channel Configuration
Slave channel
The current controller and the OFF-state diagnosis of the slave channel are disabledꢂ m write access to the
MODE register of the slave channel is ignored and reads back zeroꢂ The slave channel´s SETPOINT register
cannot be set and is read back as zeroꢂ mll feedback registers of the slave channel have to be disregardedꢂ m
write to a slave <EN_CH> bit is ignored and 0 is read backꢂ Afte disabling the ꢁarallel channel ꢀode the slave
channel ꢀust be re-configured to the desired channel behaviourꢂ
Setpoint
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
In ꢁarallel channel ꢀode, the ꢁrograꢀꢀed setꢁoint of the ꢀaster channel is usedꢂ Hence the LSB (least
significant bit) of the setꢁoint is doubledꢂ
Diagnostic functions
The LSB of the fixed OLSG (oꢁen load/short to GND) threshold is scaled by a factor of twoꢂ The OC (overcurrent)
ꢁrotection feature is active on the ꢀaster as well as on the slave channelꢂ If either the ꢀaster or the slave
channel detects an OC fault, both channels are disabledꢂ
Feedback functions
The current feedback in the FB_I_mVG register reꢁresent the suꢀꢀed uꢁ current over the shunt resistors of the
ꢀaster and slave channelꢂ The duty cycle feedback can be read froꢀ the ꢀaster channelꢂ
4.5.3
Electrical characteristics power stages
Table 13
Electrical characteristics power stages
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Shunt
Rshunt
–
140
1.5
ꢀΩ
resistance
ON resistance RDSON
-
115
–
2001) ꢀΩ
1) TJ = 150°C, ILOmDx = 2ꢂ0 m
Leakage
ILOmDx,LKG
IFWDx,LKG
-100
100
2
µm
VBmT = 1. V; Setꢁoint = 0 ꢀm; Diagnosis off
current
(LOmDx, FWDx)
Slew rate 0
Slew rate 1
Slew rate 2
Slew rate ±
SR0
0ꢂ5
1
V/µs
VBmT=14V; RLOmD=10Ω
208 to .08 of aꢁꢁlied load voltage
<SLEWR> = 00B
SR1
SR2
SR±
1ꢂ25 2ꢂ5
5
V/µs
V/µs
V/µs
VBmT=14V; RLOmD=10Ω
208 to .08 of aꢁꢁlied load voltage
<SLEWR> = 01B
2ꢂ5
5
5
10
20
VBmT=14V; RLOmD=10Ω
208 to .08 of aꢁꢁlied load voltage
<SLEWR> = 10B
10
VBmT=14V; RLOmD=10Ω
208 to .08 of aꢁꢁlied load voltage
<SLEWR> = 11B
4.6
Current control
Current accuracy overview
4.6.1
The average current setꢁoint is deterꢀined by the content of <TmRGET> in the SETPOINT registerꢂ The accuracy
band of the current regulation is illustrated in the figure belowꢂ The current accuracy includes the junction
teꢀꢁerature range TJ, battery voltage range VBmT and device aging (mEC-Q100 HTOL, TC)ꢂ The device suꢁꢁorts a
high ꢁrecision current accuracy within a reduced battery rangeꢂ For ꢀore details refer to Table 14ꢂ
Datasheet
2±
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
current
error
1 %
6V ≤ VBAT ≤ 18V
9V ≤ VBAT ≤ 16V
9V ≤ VBAT ≤ 16V, inital
0.8 %
5 mA – parallel Channel mode
2.5 mA
3 mA initial
3 mA
setpoint [mA]
10 20
500
250 300
375
1200
1500
-3 mA
-2.5 mA
-3 mA initial
-5 mA – parallel Channel mode
-0.8 %
-1 %
Figure 7
Current accuracy specification overview
4.6.2
Integrating Current Controller (ICC)
4.6.2.1
TDS_Integrating Current Controller (ICC)
The current controller regulates the load current autoꢀatically to a user defined setꢁoint by turning on and
off the internal transistorꢂ If the internal transistor is switched on, the current through the inductive load will
increaseꢂ If the internal transistor is turned off, the current will continue to flow through the recirculation diode
gradually decayꢂ
The Integrating Current Controller (ICC) is based on the requireꢀent that the integrated current error over
one PWM cycle is zeroꢂ This ꢀeans that the average current afte one PWM cycle exactly equals the targeted
currentꢂ The controller integrates the current deviation (difftetnct between load current and the setꢁoint)
and switches the outꢁut stage accordingly: While the integrated current deviation is below a configurable
integrator threshold, the ꢁower stage is turned onꢂ In this ꢁhase the load current will increaseꢂ When the
integrated current error exceeds the deterꢀined integrator threshold the ꢁower stage is turned off and the
current recirculates through the freewheeling diodeꢂ The average current is reached when the integrated
current deviation crosses zero which deterꢀines the start of a new PWM cycleꢂ The ICC switching characteristic
ꢁrovides the ꢁhysically fastest current resꢁonse which ꢀakes it very robust against load voltage diꢁsꢂ
Datasheet
24
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Outꢁut Stage
State
“on tiꢀe”
“off tiꢀe”
Load
Current
Isetpoint
Error
Integrator
threshold
Figure 8
Current Control Waveform
4.6.2.2
TDS_Integrator Limits
The ICC integrator can be saturated in order to avoid an integrator winduꢁꢂ The integrator liꢀits are
configurable via +/-<LIM_VmLUE_mBS> in the INTEGRmTOR_LIMIT registerꢂ
In order to avoid current overshoots afte setꢁoint changes the mutoliꢀit feature is introducedꢂ The device
liꢀits the integrator value to +/-<mUTO_LIM_VmLUE_mBS> (INTEGRmTOR_LIMIT register) for a ꢀaxiꢀuꢀ of two
PWM cycles afte a setꢁoint changeꢂ Afte the coꢀꢁletion of mutoliꢀit, the ICC autoꢀatically revert back to
the norꢀal integrator liꢀit values +/-<LIM_VmLUE_mBS>ꢂ The mutoliꢀit feature is disabled by writing a 1 to the
<mUTO_LIMIT_DIS> bit in the SETPOINT registerꢂ
Datasheet
25
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
i(t)
setpoint
t
t
ò (i(t)-iset)dt
+ <AUTO_LIM_VALUE_ABS>
- <AUTO_LIM_VALUE_ABS>
Autolimit
Figure 9
Autolimit feature
4.6.2.3
TDS_PWM Frequency Control
The load characteristic and load suꢁꢁly voltage afftcꢀing the PWM outꢁut frequency of the ICC controllerꢂ The
on-tiꢀe of the LS-FET and therefore the PWM cycle can be adjusted by ꢀodifying the integrator threshold
valueꢂ m greater integrator threshold ends uꢁ in a longer on-tiꢀeꢂ mlthough the configured integrator threshold
value is ꢁositive, the actual threshold can get negative since it is referenced to the lowest current deviation
integral value caꢁtured during the on-ꢁhaseꢂ This ꢀeans very short on-tiꢀe configurations are ꢁossibleꢂ
The shortest on-tiꢀe is deterꢀined by liꢀiting the integrator threshold to a ꢀiniꢀuꢀ value configurable
via <MIN_INT_THRESH> in the CTRL registerꢂ
There are two oꢁtions to set the integrator threshold to adjust the PWM frequencyꢂ
Manual setting of On-time
The driver on-tiꢀe and therefore a target PWM ꢁeriod can be set ꢀanually by ꢁrograꢀꢀing a fixed integrator
threshold <INT_THRESH> in the CTRL_INT_THRESH registerꢂ The PWM frequency controller has to be disabled
by setting <PERIOD_MmNT> in the PERIOD register to 0ꢂ
Automatic PWM control
The PWM frequency controller regulates the PWM frequency using an “Integral” control looꢁ with a
ꢁrograꢀꢀable gain, KIꢂ This control looꢁ ꢀonitors the actual PWM ꢁeriod and coꢀꢁares substracts it froꢀ
the PWM ꢁeriod target setting in the PWM ꢁeriod registerꢂ The error in the PWM ꢁeriod is ꢀultiꢁlied by the gain
KI and then integrated at each PWM cycleꢂ The outꢁut of the controller adjusts the on-tiꢀe of the PWM signal
until the actual PWM ꢁeriod ꢀatches the ꢁrograꢀꢀed PWM ꢁeriodꢂ The internal PWM frequency controller can
be activated by setting a target PWM ꢁeriod Tꢁeriod in the PERIOD registerꢂ
< PERIOD_MANT > · 2< PERIOD_EXP >
Tperiod
=
fSYS
Equation 4
By setting the bit <LOW_FREQ_RmNGE_EN> the range of the configurable target PWM frequency is lower and
can be calculated as followꢂ
< PERIOD_MANT > · 8 · 2< PERIOD_EXP >
Tperiod
=
fSYS
Equation 5
Datasheet
26
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
The bitfield <INT_THRESH> in the CTRL_INT_THRESH register deterꢀines the integrator threshold used afte
setꢁoint changes or activation of the PWM controllerꢂ The <INT_THRESH> value ꢀust be configured before
aꢁꢁlying the new setꢁointꢂ The resulting threshold calculated by the PWM frequency controller can be retrieved
froꢀ the FB_INT_THRESH registerꢂ The threshold calculated by the PWM frequency controller can be read back
froꢀ the FB_INT_THRESH registerꢂ The threshold value can be used to ꢁrograꢀ <INT_THRESH> to reduce the
settling tiꢀe of the PWM frequency controller eꢂgꢂ afte a setꢁoint changeꢂ
Note: The Autolimit threshold must be greater than the lower threshold limit configuration for a correct ICC
functioning (<AUTO_LIM_VALUE_ABS> > <MIN_INT_THRESH>+0x3).
The PWM frequency control ꢁaraꢀeter KI can be set by <PWM_CTRL_PmRmM> in the PERIOD registerꢂ The
integrator ꢁaraꢀeter KI deterꢀines the gain and therefore the sꢁeed of the PWM frequency control looꢁꢂ m KI
value of 0 results in a slower but ꢀore stable PWM controlꢂ
During steeꢁ dither settings, long off-ꢀimts can aꢁꢁear which end uꢁ in high frequencies in the next
rising dither sloꢁeꢂ The frequency controller does not consider falling dither sloꢁes by setting the
<PWM_PERIOD_CmLC_MODE> in the CTRL registerꢂ
4.6.2.4
TDS_PWM regulation warning
mn ICC PWM regulation warning is issued if the ICC integrator value droꢁs below the ꢀiniꢀuꢀ integral value,
which was caꢁtured during the on-ꢁhaseꢂ This can haꢁꢁen iꢂeꢂ if a negative absolute integrator threshold is
calculated froꢀ the PWM control and the inertia of the load is too largeꢂ This ꢀeans the integrated current
deviation could not exceed the zero level and therefore the ꢁower stage would not switch on anyꢀoreꢂ
m negative integrator threshold can be avoided by ꢁrograꢀꢀing <MIN_INT_THRESH> in the CTRL register to a
value greater than 1ꢂ m recovery ꢁrocess ꢀaintains the current regulation by triggering the mutoliꢀit featureꢂ
Afte finishing mutoliꢀit, the integrator threshold configured in <INT_THRESH> bitfield is usedꢂ The PWM
regulation warning is signaled by asserting the <PWM_REG_WmRN> bit in the DImG_WmRN_CHGR registerꢂ
i(t)
t
ò (i(t)-iset)dt
<AUTO_LIM_VALUE_ABS>
<int_thresh>
t
minimum
- <AUTO_LIM_VALUE_ABS>
Autolimit active
Integrator threshold
of PWM control
PWM regulation warning
Figure 10
ICC PWM regulation warning
4.6.2.5
TDS_Current regulation warning
mn ICC current regulation warning occurs if the ICC integrator value reaches the absolute integrator liꢀit
<LIM_VmLUE_mBS> located in the INTEGRmTOR_LIMIT registerꢂ This can haꢁꢁen for exaꢀꢁle during a voltage
suꢁꢁly diꢁꢂ m recovery ꢁrocess ꢀaintains the current regulation by triggering the mutoliꢀit featureꢂ The
integrator threshold will be reset to <INT_THRESH> located in the CTRL_INT_THRESH registerꢂ The warning
is signaled by asserting the resꢁective <I_REG_WmRN> bit in the DImG_WmRN_CHGR registerꢂ
Datasheet
27
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
i(t)
low solenoid supply
t
ò (i(t)-iset)dt
<AUTO_LIM_VALUE_ABS>
t
- <AUTO_LIM_VALUE_ABS>
Autolimit active
- <LIM_VALUE_ABS>
current regulation warning
Figure 11
4.6.3
ICC current regulation warning
Electrical characteristics current control
Table 14
Electrical characteristics current control
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
mverage
current control
error, absolute
Ierr,abs,1
-2ꢂ5
–
2ꢂ5
ꢀm
Iset = 10 - 250 ꢀm
includes aging
single channel oꢁeration
mverage
Ierr,abs,1,ꢁar
-5
–
5
ꢀm
8
Iset = 20 - 500 ꢀm
includes aging
ꢁarallel channel oꢁeration
current control
error, absolute
- ꢁarallel
mverage
current control
error, relative
Ierr,rel,1
-1
-±
–
–
1
±
250 ꢀm < Iset ≤ 1500 ꢀm; single channel
oꢁeration
500 ꢀm < Iset ≤ 2700 ꢀm; ꢁarallel channel
oꢁeration
includes aging
mverage
Ierr,abs,2
ꢀm
±00 ꢀm < Iset ≤ ±75 ꢀm
9ꢂ0 V ≤ VBmT ≤ 16 V
includes aging
current control
error, absolute
- reduced
single channel oꢁeration
battery
(table continues...)
Datasheet
2.
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Table 14
(continued) Electrical characteristics current control
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Initial average Ierrꢂabs,2,init
current control
error, absolute
- reduced
-±
-
±
ꢀm
±75 ꢀm < Iset ≤ 1200 ꢀm
9ꢂ0 V ≤ VBmT ≤ 16 V
single channel oꢁeration
battery
mverage
Ierr,rel,2
-0ꢂ.
–
0ꢂ.
8
±75 ꢀm < Iset ≤ 1200 ꢀm
9ꢂ0 V ≤ VBmT ≤ 16 V
includes aging
current control
error, relative -
reduced
single channel oꢁeration
battery
Load current
Iset
0
0
–
–
1500 ꢀm
1.00 ꢀm
DC setꢁoint current
Single channel oꢁeration
Dither current Iset+ IDither
DC setꢁoint current inclꢂ dither current
aꢀꢁlitude
Single channel oꢁeration
Measureꢀent ILOmDx
0
0
–
-
2000 ꢀm
2700 ꢀm
DC setꢁoint inclꢂ dither current aꢀꢁlitude and
overshoot
Single channel oꢁeration
The user ꢀust take care that the ꢀaxiꢀuꢀ
value is not exceeded
current
Measureꢀent ILOmDx,y,ꢁar
current -
ꢁarallel
DC setꢁoint current inclꢂ dither current
aꢀꢁlitude and overshoot
Parallel channel oꢁeration
Single channel ꢀeasureꢀent range ILOmDx of
each Channel shall not be violated
4.7
Dither
TDS_Dither configuration
4.7.1
m configurable dither waveforꢀ can be added to the average current setꢁoint in order to reduce the hysteresis
of a driven solenoid valveꢂ The dither oꢁeration is an overlay of a triangular or traꢁezoidal waveforꢀ over the
current setꢁointꢂ The dither waveforꢀ is generated by ꢁerꢀanently changing the setꢁoint according to the
ꢁrograꢀꢀed shaꢁeꢂ
The dither shaꢁe can be configured by setting the <STEPS>, <STEP_SIZE> and <FLmT> values in the
DITHER_STEP and DITHER_CTRL registerꢂ The <STEP_SIZE> value scales the height of each dither steꢁ where
the LSB is equal to <TmRGET> in the setꢁoint registerꢂ The value of <STEPS> deterꢀines the nuꢀber of steꢁs
for the rising and falling edge of each half cycle of the dither waveforꢀꢂ The value of <FLmT> deterꢀines the
nuꢀber of flat steꢁs at the ꢀiniꢀuꢀ and ꢀaxiꢀuꢀ ꢁlateau of the dither waveforꢀꢂ
The aꢀꢁlitude of the dither waveforꢀ overlay IDither can be calculated as followsꢂ
Datasheet
29
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
2A
IDitℎer = < STEPS > · < STEP_SIZE > ·
215 − 1
Equation 6
Care should be taken that no negative dither aꢀꢁlitude (Iset - IDither > 0) is configured and ꢁossible overshoots
are not violating the sꢁecified ꢀeasureꢀent current range ILOmDx or ILOmDx,ꢁar (ꢁarallel channel oꢁeration)ꢂ The
dither overlay IDither is deactivated if the target setꢁoint is set to 0ꢂ
The Dither ꢁeriod TDither is a ꢀuliꢁle of the Dither reference clock deterꢀined by the values of <MmNT>, <EXP>
of the DITHER_CLK_DIV registerꢂ The dither ꢁeriod TDither and dither reference clock tref_clk can be calculated as
followsꢂ
TDitℎer = 4 · < STEPS > + 2 · < FLAT > · tref_clk
Equation 7
< MANT > · 2< EXP >
tref_clk
=
fSYS
Equation 8
tflat = < FLAT > · tref_clk
Equation 9
Note: If <STEPS> = 0 and <FLAT> = 0, the dither period TDither = tref_clk
dither ꢁeriod TDither
<STEPS> = 4
<FLmT> = ±
dither aꢀꢁlitude IDither
<STEP_SIZE>
setꢁoint Iset
Figure 12
Dither Waveform Configuration
4.7.2
TDS_Dither parameter update
mll dither ꢁaraꢀeters located in registers DITHER_STEP and DITHER_CTRL becoꢀe active at the start of
the next dither ꢁeriod afte writing to the DITHER_CTRL registerꢂ Afte triggering an uꢁdate event (write
to DITHER_CTRL) within the active dither ꢁeriod, the dither configuration ( DITHER_STEP/ DITHER_CTRL)
that was transꢀitted last within the active dither ꢁeriod is taken overꢂ mn uꢁdate of the reference clock
tref_clk controlled by the DITHER_CLK_DIV register takes iꢀꢀediate tfftcꢀ. If the dither aꢀꢁlitude is disabled by
clearing <STEP_SIZE>, the active dither ꢁeriod will be coꢀꢁletedꢂ The configured dither ꢁeriod and overlay is
iꢀꢀediately (re)-started if the <EN_CH> bit transitions to 1ꢂ
Datasheet
±0
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
4.7.3
TDS_Dither PWM synchronization
The dither-PWM synchronization starts a new dither ꢁeriod synchron with the start of the next PWM cycle to
enable the saꢀe starting conditions for each dither ꢁeriodꢂ The start of a PWM cycle ꢁeriod is defined as a turn
on of the outꢁut stageꢂ The start of a dither ꢁeriod is defined to be when the dither increases one steꢁ above
zero on this rising sloꢁe of the dither waveforꢀꢂ The dither-PWM synchronization can be enabled by setting the
<DITHER_PWM_SYNC_EN> bit in the DITHER_CLK_DIV registerꢂ When the <DITHER_PWM_SYNC_EN> bit is set to
0, the dither waveforꢀ is free-running and asynchronous to the PWM frequencyꢂ
SYNC occurs
Load Current without SYNC
Setꢁoint + Dither shaꢁe without SYNC
Load Current with SYNC
Setꢁoint + Dither shaꢁe with SYNC
SYNC = 0 : Dither ꢁeriod is indeꢁendent of switching cycle ꢁeriod
SYNC = 1 : Start of dither ꢁeriod is delayed until start of next switching cycle ꢁeriod
Current_Control_Dither_Sync.vsdx
Figure 13
4.7.4
Note:
Dither sync
TDS_Only ICC
This feature is only available in ICC Channel Mode.
4.7.5
TDS_Dither setpoint synchronization
The dither-setꢁoint synchronization feature uꢁdates the averaged feedback values of a channel (FB_DC,
FB_I_mVG, FB_VBmT) afte a change in setꢁoint in the shortest ꢁossible tiꢀeꢂ The dither-setꢁoint
synchronization restarts the dither ꢁeriod when the newly aꢁꢁlied setꢁoint has been reachedꢂ Therefore, the
ꢀeasureꢀent ꢁeriod Tꢀeas (dither ꢁeriod) for the feedback values is always in locksteꢁ with a setꢁoint change
and no latency of the averaged feedback values (FB_DC, FB_I_mVG, FB_VBmT) is ꢁresentꢂ The synchronization
of the dither ꢁeriod to a setꢁoint change can be enabled by ꢁrograꢀꢀing the <DITHER_SETPOINT_SYNC_EN>
bit in the DITHER_CLK_DIV registerꢂ mn enabled setꢁoint synchronization freezes the average feedback registers
(FB_DC, FB_I_mVG, FB_VBmT) with the last valid ꢀeasureꢀent result if the channel is disabled with setꢁoint "0"ꢂ
Datasheet
±1
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
4.7.6
TDS_Only ICC
Note:
This feature is only available in ICC Channel Mode.
4.7.7
TDS_Deep dither
m steeꢁ and deeꢁ dither coꢀꢀand is coꢀꢁarable to great changes of setꢁointꢂ The deeꢁ dither function
reduces the over- and undershoot of very steeꢁ dither overlays by ꢁerꢀanently enabling the mutoliꢀit
featureꢂ The deeꢁ dither feature can be enabled by setting the <DEEP_DITHER> bit in DITHER_CTRL registerꢂ
4.7.8
TDS_ICC only
Note:
This feature is only available in ICC Channel Mode.
4.8
Direct Drive
4.8.1
TDS_Direct Drive
In Direct Drive, the channel's outꢁut stage is controlled directly by the userꢂ To enable a outꢁut stage switching,
the resꢁective channel ꢀust be activated by setting <EN_CH> bit to 1 and a target current setꢁoint value
difftetnꢀ to zeroꢂ The Direct Drive ꢀode ꢀust be selected by ꢁrograꢀꢀing the MODE registerꢂ
Direct Drive mode via DRV pin
In Direct Drive ꢀode via DRV ꢁin the channel’s outꢁut stage is switched according to the logic level at the
corresꢁonding DRV ꢁinꢂ The channel is turned on if the DRV ꢁin is high and is switched off if the DRV ꢁin is lowꢂ
Direct Drive mode via SPI on-Time
In Direct Drive ꢀode via SPI on-Tiꢀe, the channel’s outꢁut stage is switched according to a configurable ꢁeriodꢂ
The ꢁeriod Tꢁeriod is set in the DITHER_CLK_DIV register by the bit fields <MmNT> and <EXP>ꢂ The on-tiꢀe ton
during a ꢁeriod can be configured with the <TON_MmNT> bit field in the TON registerꢂ
< MANT > · 2< EXP >
Tperiod
=
fSYS
< TON_MANT > · 2< EXP >
ton
=
fSYS
Equation 10
4.9
Diagnostic functions
4.9.1
TDS_Overview
Each IC channel has an indeꢁendend oꢁen load (OL), overcurrent (OC) and short circuit to ground (SG)
diagnosisꢂ
The following ꢁoints should be considered:
•
•
•
mll failure ꢀodes are only considered to occur on the off board routed LOmD-ꢁinꢂ
The diagnosis indication bits are clear on writeꢂ
The diagnosis is only enabled if the device is in Mission Mode
The diagnosis consists of an ON-state diagnosis and an OFF-state diagnosisꢂ Both diagnosis states shall be used
to enable a full fault analysis coverageꢂ
ON-state diagnosis
Datasheet
±2
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
m channel is in ON-state if the <EN_CH> bit is set and the setꢁoint value is difftetnꢀ to 0 ꢀmꢂ mll diagnostic
functions in ON-state rely on ꢀeasuring the current through the shunt resistorꢂ The ON-state diagnosis cannot
distinguish between a short circuit to ground (SG) and an oꢁen load (OL) faultꢂ Those faults are suꢀꢀarized to
an Oꢁen Load/Short to Ground fault (OLSG) in the ON-stateꢂ m distinction whether an OL or SG is ꢁresent needs
to be done by the OFF-state diagnosisꢂ
OFF-state diagnosis
m channel is in OFF-state if
1.
the setꢁoint is 0 and the <EN_CH> bit is set to 1 (EN-ꢁin ꢀust be high for use of OFF-state diagnosis state
ꢀachine)
2.
the setꢁoint is non-zero and the <EN_CH> bit is set to 0ꢂ
The first condition can be used to initially test the aꢁꢁlication circuitꢂ The second condition is ꢁresent afte the
ON-state diagnosis has detected a fault ꢂ
In OFF-state, the internal high and low side current sources IHS and ILS at the LOmDx ꢁin are activeꢂ The
switching configuration and current strength of IHS and ILS can configured in the CH_CONFIG registerꢂ
VBAT
VBAT
HS
I
Load
D
HS_enable
LS_enable
I
LOADx
FWDx
OFF-state
Diagnosis
C
I
Shunt
R
LS
I
DMOS
GNDPx
Figure 14
OFF-state diagnosis circuit
Setting <OFF_DImG_CH> bit in the CH_CONFIG register to "0", activates the OFF-state diagnosisꢂ The OFF-state
diagnosis detects and indicates oꢁen load (OL) or short circuit to ground (SG) faults by ꢁerforꢀing following
LOmD ꢁin voltage checksꢂ
1.
The low side diagnostic current ILS is enabled and the high side diagnostic current IHS is disabledꢂ
•
•
If VLOmD > VTH_BmT/2 no fault is detectedꢂ
If VLOmD < VTH_BmT/2 the sequence continuesꢂ
2.
The high side diagnostic current IHS is enabled and the low side diagnostic current ILS is disabledꢂ
•
•
If VLOmD > VTH_BmT/2 an OL is detected and indicated in the DImG_ERR_CHGR registerꢂ
If VLOmD < VTH_BmT/2 a SG is detected and indicated in the DImG_ERR_CHGR registerꢂ
The OFF-state diagnosis handles all channels sequentiallyꢂ The OFF-state diagnosis sequence takes Toff,stqutnct
ꢂ
Datasheet
±±
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
CHx in OFF-state
wait for CHx
handling
activate ILS
settling time
No
Fault.
keep ILS
enabled
VLOAD < VTH_BAT/2
YES
activate IHS
settling time
set
SGx
fault bit
set
OLx
fault bit
YES
VLOAD < VTH_BAT/2
NO
Figure 15
OFF-state diagnosis sequence
4.9.2
TDS_Open Load/Short to Ground (OLSG)
mn oꢁen load (OL) and a short circuit to ground (SG) are both reducing the current flowing through the shunt
resistorꢂ Therefore the faults cannot be distinguished in ON-state and are suꢀꢀarized as OLSG faultꢂ mn OLSG
is detected if the cuꢀulated driver on-tiꢀe equals TOLSGON and the load current ILOmD is below the oꢁen load
threshold IOLTH
ꢂ
Datasheet
±4
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Open Load or Short to
Ground happened
OLSG detected
OLSGON = ton1 + ton2
T
No
OLSG
IOLTH
ton1
ton2
t
Figure 16
Simplified OLSG detection mechanism
mn OLSG fault switches off the resꢁective ꢁower stage and is indicated by setting the resꢁective OLSG bit in the
DImG_ERR_CHGR registerꢂ The device keeꢁs the channel disabled until the fault is reꢀoved, the diagnosis bit is
cleared and the <EN_CH> bit is set to “1” againꢂ
ROLꢀin is the ꢀiniꢀuꢀ iꢀꢁedance to detect an OL in ON-state via an OLSG faultꢂ
VBAT
ROLmin
=
− RLOAD + Rsℎunt + RDSon
IOLTH
Equation 11
RSGꢀax is the ꢀaxiꢀuꢀ iꢀꢁedance to detect an SG in ON-state via an OLSG faultꢂ
RLOAD · Rsℎunt + RDSon
RSGmax
=
ROLmin
Equation 12
4.9.2.1
TDS_OL-Threshold configuration
The oꢁen load threshold IOLTH can be set to a fixed threshold and/or a threshold relative to the setꢁoint via the
CH_CONFIG registerꢂ The OLSG diagnosis is disabled by setting both OL-thresholds to 0ꢂ
Fixed OL-Threshold
m fixed oꢁen load threshold is ꢁrograꢀꢀable via bitfield <OL_TH_FIXED>ꢂ
Datasheet
±5
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
< OL_TH_FIXED > · 128 · 2000mA
215 − 1
IOLTH
=
< OL_TH_FIXED > · 128 · 4000mA
215 − 1
IOLTH, parallel
=
Equation 13
Note: The OL detection in direct drive mode is only possible with the fixed threshold configuration.
Relative OL-Threshold
The relative threshold refers to the actual setꢁoint Iset including the dither aꢀꢁlitude IDitherꢂ m relative oꢁen load
threshold is adjustable in bitfield <OL_TH>ꢂ The relative oꢁen load threshold is disabled by setting <OL_TH> to
0ꢂ
< OL_TH >
IOLTH = Iset + IDitℎer
·
8
Equation 14
Note: The relative threshold is only available in a current control mode.
Transition phase
During a transition ꢁhase, the fixed OL-threshold is always usedꢂ m transition ꢁhase takes ꢁlace afte a channel
activation or setꢁoint changeꢂ m transition ꢁhase lasts for one PWM cycle or ꢀaxiꢀuꢀ for a driver on-tiꢀe
of TOLSGON (PWM cycle > TOLSGON)ꢂ The transition ꢁhase tiꢀe out can be extended or shortened by configuring
tOLSG_TIMEOUT in the TON registerꢂ Afte the transition ꢁhase has been finished, the OLSG detection swaꢁs froꢀ
fixed to relative OL-thresholdꢂ If the <OL_TH_FIXED> bitfield is set to 0, no OLSG will be detected during
a transition ꢁhaseꢂ
< OLSG_TIMEOUT > · 256 + 255 · 64
tOLSG_TIMEOUT
=
fSYS
Equation 15
4.9.3
TDS_OLSG Warning
mn additional OLSG-Warning checks if the voltage at the LOmD ꢁin is greater than VTH_BmT/2 at the end of the
freewheeling ꢁhaseꢂ The blanking tiꢀe tOLwindow is triggered every tiꢀe the outꢁutstage is switched off. If
the outꢁut stage is switched on within tOLwindow, no voltage check is ꢁossibleꢂ This is indicated by setting
<OLSG_WmRN_CHK_NOK> in the DImG_WmRN_CHGR register to 1ꢂ The <OLSG_WmRN_CHK_NOK> bit is cleared
by readingꢂ
If the check was successful, a detected OLSG-warning is indicated by setting <OLSG_WmRN> in the
DImG_WmRN_CHGR register to 1ꢂ The OLSG-warning is initially enabled and can be disabled by clearing the
bit <OLSG_WmRN_EN> in the CTRL registerꢂ The OLSG-warning check bit <OLSG_WmRN_CHK_NOK> is set to 1
afte clearing <OLSG_WmRN> in the DImG_WmRN_CHGR registerꢂ
tOLwindow can be configured in the CTRL registerꢂ
< OLSG_W ARN_WINDOW > + 1 · 64
tOLwindow =
fSYS
Equation 16
Datasheet
±6
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
OLSG Warning check
<OLSG_WARN_EN> = 1
DMOS
tOLwindow
on
off
t
t
VLOADx
VTH_BAT/2
<OLSGW_CHK_NOK> = 1
<OLSG_WARN> = 1
ok
Figure 17
OLSG-Warning and OLSG warning check overview
4.9.4
TDS_Open load (OL)
In ON-state, an oꢁen load is indicated via the <OLSG> bit in the DImG_ERR_CHGR registerꢂ The final fault
discriꢀination to identify an oꢁen load is done by the OFF-state diagnosticꢂ The device indicates the fault by
setting the resꢁective <OL> bit in the DImG_ERR_CHGR registerꢂ The device keeꢁs the channel disabled until the
fault is reꢀoved, the diagnosis bit is cleared and the <EN_CH> bit is set to “1” againꢂ
VBAT
VBAT
HS
I
D
Load
HS_enable
LS_enable
I
LOADx
FWDx
OFF-state
Diagnosis
I
C
Shunt
R
LS
I
DMOS
GNDPx
Figure 18
Open load
4.9.5
TDS_Short circuit ground (SG)
In the ON-state, a short circuit to ground is detected via the <OLSG> bit in the DImG_ERR_CHGR registerꢂ The
final fault discriꢀination to identify a short circuit to ground is done by the OFF-state diagnosticꢂ The device
indicates the fault by setting the resꢁective <SG> bit in the DImG_ERR_CHGR registerꢂ The device keeꢁs the
channel disabled until the fault is reꢀoved, the diagnosis bit is cleared and the <EN_CH> bit is set to “1” againꢂ
Datasheet
±7
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
VBAT
Load
VBAT
HS
I
D
HS_enable
I
LOADx
FWDx
OFF-state
Diagnosis
C
LS_enable
I
Shunt
R
LS
I
RSG
DMOS
GNDPx
Figure 19
Short to Ground
4.9.6
TDS_Overcurrent (OC)
mn overcurrent fault (OC) is an unintended low iꢀꢁedance connection between the LOmD terꢀinal and the
battery rail, therefore byꢁassing the load iꢀꢁedanceꢂ
mn overcurrent is detected if a current flow through the ꢁower stage exceeds IOCꢂ Therefore the ꢁower stage
ꢀust be turned on for a short ꢁeriod of tiꢀe tOCon to detect an OC in OFF-stateꢂ The driver on-tiꢀe tOCon can
be triggered by setting the <OC_DImG_EN> bit in the CH_CONFIG register and the resꢁective <EN_CH> bit in the
CH_CTRL register to 1ꢂ The driver on-tiꢀe tOCon ꢀust be configured before executing the OC detectionꢂ
< TON_MANT > + 1 · 2< EXP >
tOCon
=
fSYS
Equation 17
The ꢀantissa <TON_MmNT> is located in the TON register and the exꢁonent <EXP> is located in
DITHER_CLK_DIVꢂ mn enabled OFF-state diagnosis is keꢁt active during tOCon
ꢂ
<OC_DImG_EN> is reset afte tOCon has exꢁiredꢂ If an overcurrent is ꢁresent, the <EN_CH> bit is cleared and
the indication bit <OC> in the DImG_ERR_CHGR register is set to 1ꢂ The device keeꢁs the channel disabled until
the fault is reꢀoved, the diagnosis bits are cleared by two clear coꢀꢀands and the <EN_CH> bit is set to “1”
againꢂ
Datasheet
±.
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
VBAT
VBAT
HS
I
ROC
Load
D
HS_enable
I
LOADx
FWDx
OFF-state
Diagnosis
LS_enable
I
C
Shunt
R
LS
I
DMOS
GNDPx
Figure 20
Overcurrent
4.9.7
TDS_Register/OTP ECC
m register/OTP (one tiꢀe ꢁrograꢀꢀable ꢀeꢀory) error will be detected by a continuous error checking and
correction (ECC) ꢀechanisꢀꢂ If a correction is not ꢁossible, a register/OTP ECC error is ꢁresent and the
<REG_ECC_ERR>/<OTP_ECC_ERR> bit in the GLOBmL_DImG2 register will be setꢂ The <OTP_ECC_ERR> can
only be cleared by sending two clear coꢀꢀandsꢂ m register ECC error disables all ꢁower stages and the
ꢁroduct enters the Oꢁeration State "Config Mode"ꢂ The <OTP_VIRGIN> bit in the GLOBmL_DImG2 indicates a non
ꢁrograꢀꢀed OTP-ꢀeꢀoryꢂ This bit ꢀust always be 0ꢂ
4.9.8
TDS_Built in Self Test (BIST)
The device ꢁrovides a self-test in order to check the built in error detection and correction feature for safety
critical registersꢂ The BIST tests the ability to detect correctable and uncorrectable errorsꢂ The BIST can
only be triggered in Config Mode by writing a '1' to the <SMU_SLF_TST_EN> bit in the SFF_BIST registerꢂ
Afte the safety fliꢁ-floꢁ BIST sequence is coꢀꢁleted, the bits <SMU_SLF_TST_DONE>, <SMU_SLF_TST_UERR>
and <SMU_SLF_TST_CERR> are set to indicate a finished test sequenceꢂ
The safety fliꢁ-floꢁ BIST result is stored in the <SMU_SLF_TST_FmIL> bit in SFF_BIST registerꢂ mll result and
status bits in the SFF_BIST register are cleared on writing 0ꢂ m successfully tested safety fliꢁ-floꢁ error
(uncorrectable fault) sets the resꢁective error bits <REG_ECC_ERR> in the GLOBmL_DImG2 registerꢂ
4.9.9
Electrical characteristics diagnostic functions
Table 15
Electrical characteristics diagnostic functions
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
OLSG
threshold
single
IOLTH
0
–
492
ꢀm
fixed OLSG threshold in single channel ꢀode
(table continues...)
Datasheet
±9
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Table 15
(continued) Electrical characteristics diagnostic functions
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
OLSG
threshold
ꢁarallel
IOLTH,ꢁarallel
0
-
9.4
ꢀm
fixed OLSG threshold in ꢁarallel ꢀode
OLSG filter
detection tiꢀe
TOLSGON
-
215
-
cycles fSYS cycles
OFF-state
LOmDx
threshold
voltage
VTH_BmT/2
–
VBmT
2
/
–
V
OFF-state
sequence tiꢀe
Toff,stqutnct 1ꢂ2
–
4ꢂ.
ꢀs
Diagnosis
Current 0
IHS
ILS
±0
.0
120
µm
µm
µm
<I_DImG> = 00B
Diagnosis
Current 1
IHS
ILS
105
510
910
190
720
275
910
<I_DImG> = 01B
<I_DImG> = 10B
<I_DImG> = 11B
Diagnosis
Current 2
IHS
ILS
Diagnosis
Current ±
IHS
ILS
1250 1520 µm
4.10
Current supervision
TDS_Independent current feedback
4.10.1
The device ꢁrovides indeꢁendent current feedback ꢁaths to the ꢀicrocontroller for ꢁlausibility checks on
the load currentꢂ The average load current ꢀeasured via the internal shunt can be read back directlyꢂ The
indeꢁendently ꢀeasured duty cycle and battery voltage can be used to calculate the average load current using
a load ꢀodelꢂ
Datasheet
40
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
VBAT
Load
VBAT
D
Solenoid
Driver IC
Average
LOAD
FWD
Imeas
RShunt
ΔΣ - A/D
DMOS
Current
PWM
Driver Block
Dither
Control +
-
GNDP
PWM
Feedback
Average
Average
Battery Voltage
Duty Cycle
<FB_DC_CHx>
Average Current
<FB_I_AVG_CHx>
<FB_VBAT_CHx>
<setpoint>
Solenoid
Model or
LUT
-
calculated Iaverage
-
µC
error1
error2
Figure 21
Current supervision
4.10.2
TDS_Average feedback values
The feedback values are ꢁrovided in the registers FB_DC, FB_VBmT, FB_I_mVGꢂ The feedback values averaged
over the configured ꢀeasureꢀent ꢁeriod Tꢀeas (see "Channel ꢀodes")ꢂ The register contents are uꢁdated afte
each ꢀeasureꢀent ꢁeriod Tꢀeas
ꢂ
The feedback values can be calculated as follows:
•
•
•
Measureꢀent ꢁeriod:
< TP_MANT > · 2< EXP >
Tmeas
=
fSYS
Equation 18
PWM on tiꢀe:
< TO_MANT > · 2< EXP >
ton
=
fSYS
Equation 19
Duty cycle:
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
< TO_MANT >
< TP_MANT >
DC
=
Equation 20
Battery voltage:
•
•
< VBAT_AVG_MANT >
< TP_MANT >
VBAT = 41 . 47V ·
Equation 21
mverage load current (signed):
< I_AVG_MANT >
Iavg = 4A ·
< TP_MANT >
Equation 22
The bitfields <TP_MmNT> and <TO_MmNT> are located in the FB_DC registerꢂ The bitfields <VBmT_mVG_MmNT>
and <EXP> are loacated the FB_VBmT registerꢂ The bitfield <I_mVG_MmNT> is located in the FB_I_mVG registerꢂ
The bitfield <I_mVG_MmNT> reꢁresents a signed current value (two's coꢀꢁleꢀent)ꢂ
4.10.3
TDS_Update/Freeze Mechanism
The Uꢁdate/Freeze ꢀechanisꢀ should be aꢁꢁlied for a correct readout of each ꢀeasureꢀent saꢀꢁle setꢂ The
IC indicates new feedback data by setting the resꢁective <CH> bit in the FB_UPD register to 1ꢂ Setting <CH>
bit in the FB_FRZ register to 1, stoꢁs the uꢁdating and freezes the latest ꢀeasureꢀent results of the feedback
registers FB_DC, FB_VBmT, FB_I_mVG, FB_PERIOD_MIN_MmX, FB_IMIN_IMmXꢂ Setting the <CH> bit in the FB_FRZ
register to 0, also clears the resꢁective <CH> bit in the FB_UPD register and enables the uꢁdate of the feedback
valuesꢂ Following state diagraꢀ shows a recoꢀꢀendation for the readout of the feedback valuesꢂ
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
Start
all FB_FRZ.CHx flag
cleared
Poll FB_UPD
register
no
<FB_UPD.CHx>
is set ?
yes
set FB_FRZ.CHx
flag
read
FB_DC_CHx,
FB_I_AVG_CHx,
FB_I_VBAT_CHx
Select
next
Channel
clear
FB_FRZ.CHx flag
no
all results read of
flagged channels ?
yes
Figure 22
Readout proposal for feedback values
4.10.4
TDS_Iavg16, minimum/maximum current/PWM feedback
The IC ꢁrovides the average load current Iavg16 over a free running ꢁeriod of 216 systeꢀ clocks, as a signed 16 bit
value in the FB_I_mVG_s16 registerꢂ This value is not intended to be used while in closed looꢁ oꢁeration or for
current suꢁervisionꢂ The value is ꢁrovided as additional inforꢀation and can be used for calibration ꢁurꢁosesꢂ
< I_AVG_s16 >
216 − 1
Iavg16 = 4A·
Equation 23
The IC ꢁrovides ꢀeasureꢀents of the ꢀiniꢀuꢀ (ꢀin) and ꢀaxiꢀuꢀ (ꢀax) current and PWM ꢁeriodꢂ
The ꢀin/ꢀax values reꢁresent the highes/lowest current and shortest/longest PWM ꢁeriod caꢁtured
during a ꢀeasureꢀent ꢁeriod Tꢀeasꢂ If no ꢀeasureꢀent ꢁeriod Tꢀeas is defined, the ꢀin/ꢀax registers are
Datasheet
4±
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
ꢁerꢀanently uꢁdated when a new ꢀiniꢀuꢀ or ꢀaxiꢀuꢀ current/PWM has been ꢀeasuredꢂ The current values
are held in the FB_IMIN_IMmX register and the PWM values can be read out froꢀ the FB_PERIOD_MIN_MmX
registerꢂ The current values in the FB_IMIN_IMmX register are reꢁresented as a signed 9 bit value (two´s
coꢀꢁleꢀent)ꢂ
< IMIN >
Imin = 4A·
29 − 1
< IMAX >
Imax = 4A·
29 − 1
Equation 24
256
TPWM_min = < PMIN > ·
fSYS
256
TPWM_max = < PMAX > ·
fSYS
Equation 25
4.11
Protection functions
4.11.1
TDS_Overtemperature protection
The device ꢁrovides ꢁrotection against overteꢀꢁerature by ꢀeasuring the central IC teꢀꢁerature and every
ꢁower stage teꢀꢁeratureꢂ If an overteꢀꢁerature TJ,ot is ꢀeasured, the resꢁective ꢁower stage is switched off
and the resꢁective <OT> bit in the DImG_ERR_CHGRx register is setꢂ m central overteꢀꢁerature of the IC disables
all ꢁower stages and sets the <COTERR> bit in the GLOBmL_DImG0 registerꢂ
If the resꢁective ꢁower stage has cooled down to TJ,ot -TH, the ꢁower stage can be re-enabledꢂ m ꢁre-warning bit
in the diagnostic register is set, if the ꢁower stage teꢀꢁerature exceeds the ꢁre-warning threshold Tꢁꢂ
The overteꢀꢁerature detection can be tested by setting the <OT_TEST> bit in the GLOBmL_CONFIG register
to "1"ꢂ This test sets the overteꢀꢁerature threshold to the lowest ꢁossible value and the according
overteꢀꢁerature indication bits should be assertedꢂ
The device ꢁrovides a teꢀꢁerature feedback TFB which can be read out froꢀ the bitfield <TEMP_VmLUE> in the
FB_VOLTmGE2 registerꢂ The teꢀꢁerature feedback TFB is given by
< TEMP_V ALUE > · 0 . 000593 − 0 . 819*
−0 . 0016*
TFB
=
°C
Equation 26
If a higher accuracy of the teꢀꢁerature feedback TFB is required, a calibration of the ꢁaraꢀeters *) have to be
done on systeꢀ levelꢂ
4.11.2
TDS_Overcurrent protection
The ꢀaxiꢀuꢀ current through every ꢁower stage of the device is liꢀitedꢂ mn overcurrent condition is
detected if the load current exceeds IOCꢂ The detection of an overcurrent takes ꢀaxiꢀuꢀ tOC,DETECTꢂ mn
overcurrent causes the channel to be switched off and is indicated by setting the resꢁective <OC> bit in the
DImG_ERR_CHGR register to 1ꢂ The <OC> bit ꢀust be cleared by two SPI write coꢀꢀandsꢂ
Datasheet
44
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Functional description
4.11.3
Electrical characteristics protection functions
4.11.3.1
Overtemperature protection
Table 16
Overtemperature protection
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Overteꢀꢁeratu TP
re ꢁre-warning
threshold
150
-
175
°C
Overteꢀꢁeratu TJ,OT
175
10
-
200
15
°C
°C
°C
re threshold
Therꢀal
hysteresis
TH
–
–
Teꢀꢁerature
feedback
accuracy
TFB
-20
20
4.11.3.2
Overcurrent protection
Table 17
Overcurrent protection
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Overcurrent
ꢁrotection
threshold
IOC
2ꢂ05
–
6
m
Overcurrent
ꢁrotection
filter tiꢀe
tOC,DETECT
–
–
1ꢂ5
µs
fSYS = 2. MHz
Datasheet
45
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5
Serial peripheral interface (SPI)
5.1
Description of interface
TDS_General information
5.1.1
The coꢀꢀunication interface is based on a standard serial ꢁeriꢁheral interface (SPI)ꢂ The SPI is a full duꢁlex
synchronous serial slave interface which uses four signal lines: SO, SI, SCK, and CSNꢂ Data is transferred by the
lines SI and SO at the data rate given by SCKꢂ The falling edge of CSN indicates the beginning of a data accessꢂ
Data is saꢀꢁled in on line SI at the falling edge of SCK and shiftd out on line SO at the rising edge of SCKꢂ Each
access ꢀust be terꢀinated by a rising edge of CSNꢂ m counter ensures that data is taken only when ±2 bits have
been transferredꢂ If the nuꢀber of bits transferred is not ±2, the data fraꢀe is ignoredꢂ
...
...
30
30
29
29
28
28
27
27
26
26
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
SO
SI
MSB
MSB
LSB
LSB
CSN
SCK
...
...
t
Figure 23
SPI signal overview
5.1.2
TDS_Cyclic redundancy check (CRC)
mn .-bits cyclic redundancy code (CRC-8 SAE-J1850) is added to all SPI coꢀꢀunication fraꢀes to detect corruꢁt
data and to avoid wrong configuration of the ICꢂ The CRC-. SmE-J1.50 ꢁolynoꢀial is used for the calculation:
x. + x4 + x± + x2 + 1 or 0x1D
Note: CRC is supported by the flexible CRC engine (FCE) of Aurix TC26x, TC27x and TC29x.
The initial value of the CRC-byte is 0xFFꢂ The CRC result is XOR oꢁerated with 0xFFꢂ The CRC-byte is located in
the ꢀost significant byte of the SPI fraꢀeꢂ The byte-sequence for the CRC calculation is as follows:
1st byte: SPI fraꢀe[7:0]
2nd byte: SPI fraꢀe[15:.]
±
rd byte: SPI fraꢀe[2±:16]
Difftetnꢀ generator ꢁolynoꢀials are suꢁꢁorted by the fraꢀe encoder/decoder entity definition, but the sꢁecific
iꢀꢁleꢀentation is not ꢁart of the reuse ꢀoduleꢂ The ꢁroduct designer has to ꢀodify the fraꢀe encoder/
decoder source code within the ꢁroject design environꢀent accordinglyꢂ
The CRC byte is located in the ꢀost significant fraꢀe byte [±1:24]ꢂ Whenever a SPI fraꢀe CRC error is detected,
a SPI 16 bit reꢁly fraꢀe indicating the SPI CRC error status is send in the subsequent SPI transactionꢂ
The CRC check can be disabled by setting the <CRC_EN> bit in the GLOBmL_CONFIG register to "0"ꢂ
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.1.3
TDS_Timing Diagram
tCSN_LEAD
tCSN_LAG
tCSN_TD
tSCK
VCSN,high
VCSN,low
CSN
SCK
SI
. . .
tSCKH
tSCKL
VSCK,high
VSCK,low
...
tSI_SU
tSI_H
...
...
VSI,high
VSI,low
tSO_EN
tSO_V
tSO_DIS
...
...
VSO,high
VSO,low
SO
Figure 24
5.1.4
SPI Signal Timing Diagram
Electrical characteristics SPI interface
Table 18
Electrical characteristics SPI interface
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Serial clock
high tiꢀe
tSCKH
50
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
Serial clock
low tiꢀe
tSCKL
50
Enable lead
tiꢀe
tCSN_LEmD
tCSN_LmG
250
250
600
20
falling CSN to rising SCK
falling SCK to rising CSN
rising CSN to falling CSN
required tiꢀe SI to falling SCK
required tiꢀe falling SCK to SI
Enable lag
tiꢀe
Transfer delay tCSN_TD
tiꢀe
Data setuꢁ
tiꢀe
tSI_SU
Data hold tiꢀe tSI_H
20
–
–
–
–
ns
ns
Outꢁut disable tSO_DIS
tiꢀe
200
rising CSN to SO tri-state
CL = 150 ꢁF
Outꢁut enable tSO_EN
–
–
–
–
200
100
ns
ns
falling CSN to SO valid
CL = 150 ꢁF
tiꢀe
Outꢁut data
valid tiꢀe
tSO_V
CL = 150 ꢁF
(table continues...)
Datasheet
47
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
Table 18
(continued) Electrical characteristics SPI interface
TJ = -40°C to 150°C; VDD = 4ꢂ5 - 5ꢂ5 V; VIO = ±ꢂ0 - 5ꢂ5 V; VBmT = 6 - 1. V; all voltages with resꢁect to ground, ꢁositive
current flowing into ꢁin (unless otherwise sꢁecified)ꢂ
Parameter
Symbol
Values
Unit
Note or condition
Min. Typ. Max.
Functional
range SPI clock
frequency
(SCK)
fSCK
–
–
.
MHz
SPI watchdog fSPI,WD
decreꢀent
–
–
fSYS
/
–
MHz
ꢁF
fSYS = 2. MHz
214
frequency
Inꢁut ꢁin
caꢁacitance
(CSN, SCK, SI,
CLK)
CIN
–
10
Vbias = 2 V; Vtest = 20 ꢀVꢁꢁ; f =1 MHz
Outꢁut ꢁin
caꢁacitance
(SO)
CSO_HIZ
–
-
–
-
15
2
ꢁF
V
Tri-state Outꢁut Vbias = 2 V; Vtest = 20 ꢀVꢁꢁ; f = 1
MHz
SPI High
VSI,high
VSCK,high
VCSN,high
Threshold
Voltage (SI,
SCK, CSN)
SPI Low
VSI,low
VSCK,low
VCSN,low
0ꢂ.
-
-
-
V
Threshold
Voltage (SI,
SCK, CSN)
SPI Inꢁut
hysteresis (SI,
SCK, CSN)
VIN,HYS,SI
VIN,HYS,SCK
VIN,HYS,CSN
50
–
-
ꢀV
V
SPI outꢁut
high voltage
(SO)
VSO,high
VIO
0ꢂ5
-
VIO
ꢁull down current ISO = -0ꢂ5 ꢀm/ ±ꢂ0 V < VIO < 5ꢂ5
V
SPI outꢁut low VSO,low
0
–
–
0ꢂ5
10
V
ꢁull uꢁ current ISO = 0ꢂ5 ꢀm
voltage (SO)
SPI outꢁut
leakage
ISO,OFF
-10
µm
VCSN > VCSN,high
0 V < VSO < VIO
current (SO)
Pull down
current (SI,
SCK)
IPD,SI
IPD,SCK
10
–
–
50
µm
µm
VIN = 2 V
Pull uꢁ current IPU,CSN
(CSN)
-50
-10
VCSN = 0ꢂ. V
Datasheet
4.
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.2
Description of protocol
TDS_Data flow
5.2.1
The ꢀessage froꢀ the ꢀicrocontroller ꢀust be sent MSB firstꢂ The data froꢀ the SO ꢁin is sent MSB firstꢂ For
each coꢀꢀand received at the SI ꢁin of the SPI interface, a serial data streaꢀ is returned at the saꢀe tiꢀe on
the SO ꢁinꢂ The content of the SO data fraꢀe is deꢁendent on the coꢀꢀand which was received on the SI ꢁin
during the ꢁrevious fraꢀeꢂ m REmD coꢀꢀand (R/W = 0) returns the contents of the addressed register one SPI
fraꢀe laterꢂ The data bits in the REmD coꢀꢀand are ignoredꢂ
m WRITE coꢀꢀand (R/W = 1) will write the data bits in the SPI word to the addressed registerꢂ The actual
contents of addressed register will be returned to the SPI ꢀaster (ꢀicrocontroller) during the next SPI fraꢀeꢂ
CSN
SI
R
Message #1
W
Message #2
R
Message #±
SO
Resꢁonse #1
Resꢁonse #2
SPI_protocol.vsdx
Figure 25
SPI protocol
5.2.2
TDS_SPI watchdog
mn SPI watchdog checks the coꢀꢀunication on the SPI busꢂ The SPI watchdog can be enabled by setting
<SPI_WD_EN> in the GLOBmL_CONFIG registerꢂ
If the SPI watchdog is enabled, the <WD_TIME> value in the WD_RELOmD register is constantly decreꢀented
with fSPI,WDꢂ In order to avoid a SPI watchdog error, the WD_RELOmD register ꢀust be ꢁerꢀanently uꢁdatedꢂ
If the <WD_TIME> value of the WD_RELOmD register transitions froꢀ 1 to 0, the <SPI_WD_ERR> bit in the
GLOBmL_DImG0 register is asserted and the IC transits to Config Modeꢂ
ms long as a SPI watchdog fault is ꢁresent the device cannot enter Mission Modeꢂ The SPI error indication bit
<SPI_WD_ERR> is set to 0 if the WD_RELOmD register contains a non-zero valueꢂ
The SPI watchdog tiꢀeout tSPI,WD is given by:
< WD_TIME >
tSPI, WD
=
fSPI, WD
Equation 27
5.2.3
SPI frame definition
5.2.3.1
TDS_MOSI - Write frame
MOSI SPI write fraꢀe
Data in fraꢀe of slave device
±1
±0
29
2.
27
26
25
24
2±
22
21
20
19
1.
17
16
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
CRC
mddress
4
R/W
0
15
14
1±
12
11
10
9
.
7
6
5
±
2
1
Data
Field
CRC
Bits
Description
±1:24
2±:17
16
CRC check (SmE CRC. J1.50)
mddress field
mddress
R/W
MOSI Read/Write Indicator
0B: Read oꢁeration
1B: Write oꢁeration
Data
15:0
Data bits are defined in register descriꢁtion
5.2.3.2
TDS_MOSI - Read frame
MOSI SPI read fraꢀe
Data in fraꢀe of slave device
±1
15
±0
14
29
1±
2.
CRC
12
27
11
26
10
25
9
24
.
2±
7
22
6
21
5
20
-
19
±
1.
2
17
1
16
R/W
0
4
mddress
Field
CRC
-
Bits
Description
±1:24
2±:17
16
CRC check (SmE CRC. J1.50)
Don´t care
R/W
MOSI Read/Write Indicator
0B: Read oꢁeration
1B: Write oꢁeration
mddress
15:0
Read mddress
5.2.3.3
TDS_MISO - 16 bit reply frame
MISO SPI 16 bit reꢁly fraꢀe
16 bit data out fraꢀe of slave device
±1
15
±0
14
29
1±
2.
CRC
12
27
11
26
10
25
9
24
.
2±
22
21
5
20
4
19
Status
±
1.
2
17
1
16
R/W
0
Reꢁly Mode
7
6
Data
Field
Bits
±1:24
Description
CRC
CRC check (SmE CRC. J1.50)
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
Field
Bits
Description
Reꢁly Mode
2±:22
Indicates tyꢁe of reꢁly fraꢀe:
00B: 16 bit Reꢁly Fraꢀe
01B: 22 bit Reꢁly Fraꢀe
10B: Critical Fault Fraꢀe
Status
21:17
Status indication of the current Fraꢀe:
00B: no error
01B: SPI fraꢀe error
10B: Parity/CRC error
11B: Write to read only register
100B/101B/110B: Internal bus fault
NOTE: The highest priority has the lowest encoding
R/W
16
Indicator ꢀirrored froꢀ ꢁrevious MOSI fraꢀe
0B: Read indicator
1B: Write indicator
Data
15:0
Data bits are defined in register descriꢁtion
5.2.3.4
TDS_MISO - 22 bit reply frame
MISO SPI 22 bit reꢁly fraꢀe
22 bit data out fraꢀe of slave device
±1
15
±0
14
29
1±
2.
CRC
12
27
11
26
10
25
9
24
.
2±
0
22
1
21
5
20
4
19
±
1.
2
17
1
16
0
Data
7
6
Data (cont'd)
Field
Bits
Description
CRC
±1:24
2±:22
CRC check (SmE CRC. J1.50)
Reꢁly Mode
Indicates tyꢁe of reꢁly fraꢀe:
00B: 16 bit Reꢁly Fraꢀe
01B: 22 bit Reꢁly Fraꢀe
10B: Critical Fault Fraꢀe
Data
21:0
22 data bits used for feedback registers defined in register descriꢁtion
5.2.3.5
TDS_MISO - Critical fault reply frame
MISO SPI critical fault reꢁly fraꢀe
Critical fault fraꢀe of slave device
±1
±0
29
2.
27
26
25
24
2±
1
22
0
21
20
19
19
17
16
Don't care
Don't care
Datasheet
51
Revꢂ 1ꢂ0
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
Don't care (cont'd)
1V5 2V5
BG CLK_ CLK_ DIG_ DIG_ WD_
TOO TOO CLK_ CLK_ REF_
_SLO _FmS TOO TOO CLK
W
T
_SLO _FmS
W
T
Field
Bits
Description
Don´t care
Reꢁly Mode
±1:24
2±:22
-
Indicates tyꢁe of reꢁly fraꢀe:
00B: 16 bit Reꢁly Fraꢀe
01B: 22 bit Reꢁly Fraꢀe
10B: Critical Fault Fraꢀe
Don´t care
1V5
21:.
7
-
0B: 1V5 suꢁꢁly not ok
1B: 1V5 suꢁꢁly ok
2V5
6
5
4
±
0B: 2V5 suꢁꢁly not ok
1B: 2V5 suꢁꢁly ok
BG
0B: mDC Bandgaꢁ not ok
1B: mDC Bandgaꢁ ok
CLK_TOO_SLOW
CLK_TOO_FmST
0B: No clock fault detected
1B: Clock is too slow for IC oꢁeration
0B: No clock fault detected
1B: Clock is too fast for IC oꢁeration
DIG_CLK_TOO_SLOW
DIG_CLK_TOO_FmST
WD_REF_CLK
2
1
0
0B: No clock fault detected
1B: Digital Clock is too slow
Note: clock watchdog must be enabled.
0B: No clock fault detected
1B: Digital Clock is too fast
Note: clock watchdog must be enabled.
0B: Clock watchdog reference clock is ok
1B: Clock watchdog reference clock is ꢀissing
Datasheet
52
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3
Register description
5.3.1
Overview of Register Types
Bit type short name
Bit type description
Note
r
Bits are readable (read)
bitfields "RES" do not care
bitfields "RES" do not care
rh
Bits are readable (read) and
ꢀodifiable by the IC (hardware)
rw
Bits are read- and writeable (read- bitfields "RES" do not care, write "0"
write)
rwh
Bits are read- and writeable (read- bitfields "RES" do not care, write "0"
write) and ꢀodifiable by the IC
(hardware)
Datasheet
5±
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.2
Central registers
5.3.2.1
Register overview - centralRegs (ascending offset address)
Table 19
Register overview - centralRegs (ascending offset address)
Short name
Long name
Offset
Page
address
number
CH_CTRL
Channel Control Register
Global Configuration Register
Global Diagnosis Register 0
Global Diagnosis Register 1
Global Diagnosis Register 2
VBmT Threshold Register
Feedback Freeze Register
Feedback Uꢁdate Register
SPI Watchdog Register
0000H
0002H
000±H
0004H
0005H
0006H
0007H
000.H
0009H
000mH
000BH
0010H
0011H
0016H
0017H
001.H
0019H
00±FH
0200H
0201H
0202H
020±H
0204H
55
55
56
57
5.
59
59
60
61
61
62
6±
64
66
66
67
6.
6.
69
70
70
72
7±
GLOBmL_CONFIG
GLOBmL_DImG0
GLOBmL_DImG1
GLOBmL_DImG2
VBmT_TH
FB_FRZ
FB_UPD
WD_RELOmD
DImG_ERR_CHGR0
DImG_ERR_CHGR1
Diagnosis Error Register 0
Diagnosis Error Register 1
DImG_WmRN_CHGR0 Diagnosis Warning Register 0
DImG_WmRN_CHGR1 Diagnosis Warning Register 1
FmULT_MmSK0
FmULT_MmSK1
FmULT_MmSK2
CLK_DIV
Fault Mask Register 0
Fault Mask Register 1
Fault Mask Register 2
Clock Control Register
BIST Register
SFF_BIST
ICVID
Version Register
PIN_STmT
Pin Status Register
FB_STmT
Feedback Status Register
Feedback Voltage Register 1
Feedback Voltage Register 2
FB_VOLTmGE1
FB_VOLTmGE2
5.3.2.2
Register address space - centralRegs
Table 20
Registers address space - centralRegs
Module
Base address End address
00000000H 0000FFFEH
Note
aꢁb
Datasheet
54
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.2.3
Channel Control Register
The channel enable bits EN_CHx can only be set in Mission ꢀodeꢂ The ꢁarallel ꢀode configuration bits
CH_PmR_x can only be set in Config ꢀodeꢂ
CH_CTRL
Channel Control Register
Offstꢀ address:
0000H
0000H
value:
15
14
1±
12
11
10
9
.
Res
r
7
6
5
4
±
2
1
0
CH_ CH_
PAR_ PAR_
1_2 0_3
OP_M
ODE
EN_C EN_C EN_C EN_C
H3
H2
H1
H0
undef
undef
undef
undef
undef
undef
undef
Field
Bits
Type
Description
EN_CH0
0
undef
Enable Channel 0
0B Disabled
1B Enabled
EN_CH1
EN_CH2
EN_CH±
1
2
±
undef
undef
undef
undef
undef
undef
Enable Channel 1
0B Disabled
1B Enabled
Enable Channel 2
0B Disabled
1B Enabled
Enable Channel 3
0B Disabled
1B Enabled
CH_PmR_0_± 1±
CH_PmR_1_2 14
Parallel Operation Channel 0/3
0B Disabled
1B Enabled
Parallel Operation Channel 1/2
0B Disabled
1B Enabled
OP_MODE
15
Chip Operation Mode
0B Config Mode
1B Mission Mode
5.3.2.4
Global Configuration Register
Global Configuration Register: write access only ꢁossible in Config Mode
GLOBAL_CONFIG
Global Configuration Register
Offstꢀ address:
0002H
4005H
value:
Datasheet
55
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
Res
r
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
UV_
OV_S
WAP
V1V5 V1V5
SPI_ CLK_
WD_ WD_
VIO_
SEL
OT_T
EST
CRC_
EN
Res
_OV_ _UV_ Res
TEST TEST
EN
undef
EN
undef
undef
undef
undef
r
undef
undef
r
undef
Field
Bits
Type
Description
CLK_WD_EN
SPI_WD_EN
CRC_EN
0
undef
Clock Watchdog
0B Disabled
1B Enabled
1
undef
undef
undef
undef
undef
undef
SPI Watchdog
0B Disabled
1B Enabled
2
SPI CRC Check
0B Disabled
1B Enabled
V1V5_UV_TES
T
4
Test Internal Supply Undervoltage Detection
0B Disabled
1B Enabled
V1V5_OV_TES
T
5
Test Internal Supply Overvoltage Detection
0B Disabled
1B Enabled
OT_TEST
12
Test Overtemperature Detection
0B Disabled
1B Enabled
UV_OV_SWmP 1±
Test Undervoltage/Overvoltage Detection
0B Disabled
1B Enabled
VIO_SEL
14
undef
VIO voltage selection
0B ±ꢂ± V
1B 5ꢂ0 V
5.3.2.5
Global Diagnosis Register 0
Global Diagnosis Register 0
GLOBAL_DIAG0
Global Diagnosis Register 0
Offstꢀ address:
000±H
0600H
value:
15
14
1±
12
Res
r
11
10
9
.
7
6
5
4
±
2
1
0
SPI_
POR RES_ COT
_EVE EVEN WAR
COTE CLK_ VDD_ VDD_ VIO_ VIO_ VBAT VBAT
Res WD_
ERR
RR NOK OV
UV
OV
UV _OV _UV
NT
undef
T
undef
N
undef
r
undef
undef
undef
undef
undef
undef
undef
undef
undef
Datasheet
56
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
Field
Bits
Type
Description
VBmT_UV
0
undef
VBAT Undervoltage Detection
0B No Fault Detected
1B Fault Detected
VBmT_OV
VIO_UV
1
2
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
VBAT Overvoltage Detection
0B No Fault Detected
1B Fault Detected
VIO Undervoltage Detection
0B No Fault Detected
1B Fault Detected
VIO_OV
±
VIO Overvoltage Detection
0B No Fault Detected
1B Fault Detected
VDD_UV
4
VDD Undervoltage Detection
0B No Fault Detected
1B Fault Detected
VDD_OV
5
VDD Overvoltage Detection
0B No Fault Detected
1B Fault Detected
CLK_NOK
COTERR
6
Clock Fault Detection
0B No Fault Detected
1B Fault Detected
7
Central Overtemperature Error
0B No Fault Detected
1B Fault Detected
COTWmRN
RES_EVENT
POR_EVENT
.
Central Overtemperature Warning
0B No Fault Detected
1B Fault Detected
9
Reset occurred due to RESN-pin low
0B No Event Occurred
1B Event Occurred
10
Event Occurred
0B No Event Occurred
1B m Power On Reset Event occurred since ꢁrevious read out
SPI_WD_ERR 14
SPI Watchdog Fault Detection
0B No Fault Detected
1B Fault Detected
5.3.2.6
Global Diagnosis Register 1
Global Diagnosis Register 1
GLOBAL_DIAG1
Offstꢀ address:
0004H
Datasheet
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TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
Global Diagnosis Register 1
value:
0000H
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
HVAD
C_ER
R
VDD VDD VR_I VR_I
2V5_ 2V5_ REF_ REF_
VPRE REF_ REF_
Res
_OV OV
UV
OV
UV
OV
UV
undef
r
undef
undef
undef
undef
undef
undef
undef
Field
Bits
Type
Description
VR_IREF_UV
VR_IREF_OV
VDD2V5_UV
VDD2V5_OV
REF_UV
0
undef
Internal Bias Current too Low Detection
0B No Fault Detected
1B Fault Detected
1
undef
undef
undef
undef
undef
undef
undef
Internal Bias Current too High Detection
0B No Fault Detected
1B Fault Detected
2
Internal 2V5 Supply Undervoltage Detection
0B No Fault Detected
1B Fault Detected
±
Internal 2V5 Supply Overvoltage Detection
0B No Fault Detected
1B Fault Detected
4
Internal Reference Undervoltage Detection
0B No Fault Detected
1B Fault Detected
REF_OV
5
Internal Reference Overvoltage Detection
0B No Fault Detected
1B Fault Detected
VPRE_OV
6
Internal Pre-Regulator Overvoltage Detection
0B No Fault Detected
1B Fault Detected
HVmDC_ERR
15
Internal Monitoring ADC Error Detection
0B No Fault Detected
1B Fault Detected
5.3.2.7
Global Diagnosis Register 2
Global Diagnosis Register 2
GLOBAL_DIAG2
Global Diagnosis Register 2
Offstꢀ address:
0005H
0000H
value:
Datasheet
5.
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
14
1±
12
11
10
Res
r
9
.
7
6
5
4
±
2
1
0
OTP_ OTP_
REG_
VIRG ECC_ Res ECC_ Res
IN
undef
ERR
undef
ERR
undef
r
r
Field
Bits
Type
Description
REG_ECC_ERR 1
undef
Register ECC Error
0B No Error
1B Multi Bit Fliꢁ Detected
OTP_ECC_ERR ±
undef
undef
OTP ECC Error
0B No Error
1B None Reꢁairable Multi Bit Fliꢁ Detected
OTP_VIRGIN
4
OTP Memory Configured Complete
0B OTP coꢀꢁletely configured
1B Virgin OTP mddress Detected
5.3.2.8
VBAT Threshold Register
VBmT Over and Under Voltage Threshold Register
VBAT_TH
VBmT Threshold Register
Offstꢀ address:
0006H
FF19H
value:
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
VBAT_OV_TH
VBAT_UV_TH
undef
undef
Field
Bits
Type
Description
VBmT_UV_TH 7:0
undef
VBAT Undervoltage Threshold
V BmT_UV = <VBmT_UV_TH> * 0ꢂ1620. V
VBmT_OV_TH 15:.
undef
VBAT Overvoltage Threshold
V BmT_OV = <VBmT_OV_TH> * 0ꢂ1620. V
5.3.2.9
Feedback Freeze Register
Feedback Freeze Register
Feedback Values are ꢁrovided in the registers FB_DC, FB_VBmT, FB_I_mVG
FB_FRZ
Feedback Freeze Register
Offstꢀ address:
0007H
0000H
value:
Datasheet
59
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
FR_C FR_C FR_C FR_C
Res
H3
H2
H1
H0
r
rw
rw
rw
rw
Field
Bits
Type
Description
FR_CH0
0
rw
Freeze of CH0 Feedback Values
0B Disabled
1B Enabled
FR_CH1
FR_CH2
FR_CH±
1
2
±
rw
rw
rw
Freeze of CH1 Feedback Values
0B Disabled
1B Enabled
Freeze of CH2 Feedback Values
0B Disabled
1B Enabled
Freeze of CH3 Feedback Values
0B Disabled
1B Enabled
5.3.2.10
Feedback Update Register
Feedback Uꢁdate Register
Feedback Values are ꢁrovided in the registers FB_DC, FB_VBmT, FB_I_mVG
FB_UPD
Feedback Uꢁdate Register
Offstꢀ address:
000.H
0000H
value:
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
UD_ UD_ UD_ UD_
CH3 CH2 CH1 CH0
Res
r
undef
undef
undef
undef
Field
Bits
Type
Description
UD_CH0
0
undef
Indication of CH0 Feedback Values Update
0B No new Feedback Values available
1B New Feedback Values available
UD_CH1
UD_CH2
1
2
undef
undef
Indication of CH1 Feedback Values Update
0B No new Feedback Values available
1B New Feedback Values available
Indication of CH2 Feedback Values Update
0B No new Feedback Values available
1B New Feedback Values available
(table continues...)
Datasheet
60
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
(continued)
Field
Bits
Type
Description
UD_CH±
±
undef
Indication of CH3 Feedback Values Update
0B No new Feedback Values available
1B New Feedback Values available
5.3.2.11
SPI Watchdog Register
SPI Watchdog Counter Reload Register
WD_RELOAD
SPI Watchdog Register
Offstꢀ address:
0009H
0001H
value:
15
14
1±
Res
r
12
11
10
9
.
7
6
5
4
±
2
1
0
WD_TIME
undef
Field
Bits
10:0
Type
Description
WD_TIME
undef
Reload value of SPI watchdog timout t_SPI_WD
<WD_TIME> = rounddown( t SPI_WD * f SYS/ 2^14 )
5.3.2.12
Diagnosis Error Register 0
Diagnosis Error Register Channel Grouꢁ 0
DIAG_ERR_CHGR0
Diagnosis Error Register 0
Offstꢀ address:
000mH
0000H
value:
15
14
Res
r
1±
12
11
10
9
.
7
6
Res
r
5
4
±
2
1
0
OLS
G1
OLS
G0
OTE1 SG1 OC1 OL1
OTE0 SG0 OC0 OL0
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
Field
Bits
Type
Description
OLSG0
0
undef
Open Load or Short to Ground Detection CH0
0B No Fault Detected
1B Fault Detected
OL0
OC0
1
2
undef
undef
Open Load Detection CH0
0B No Fault Detected
1B Fault Detected
Overcurrent Detection CH0
0B No Fault Detected
1B Fault Detected
(table continues...)
Datasheet
61
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
(continued)
Field
Bits
Type
Description
SG0
±
undef
Short to Ground Detection CH0
0B No Fault Detected
1B Fault Detected
OTE0
OLSG1
OL1
4
undef
undef
undef
undef
undef
undef
Overtemperature Error Detection CH0
0B No Fault Detected
1B Fault Detected
.
Open Load or Short to Ground Detection CH1
0B No Fault Detected
1B Fault Detected
9
Open Load Detection CH1
0B No Fault Detected
1B Fault Detected
OC1
10
11
12
Overcurrent Detection CH1
0B No Fault Detected
1B Fault Detected
SG1
Short to Ground Detection CH1
0B No Fault Detected
1B Fault Detected
OTE1
Overtemperature Error Detection CH1
0B No Fault Detected
1B Fault Detected
5.3.2.13
Diagnosis Error Register 1
Diagnosis Error Register Channel Grouꢁ 1
DIAG_ERR_CHGR1
Diagnosis Error Register 1
Offstꢀ address:
000BH
0000H
value:
15
14
Res
r
1±
12
11
10
9
.
7
6
Res
r
5
4
±
2
1
0
OLS
G3
OLS
G2
OTE3 SG3 OC3 OL3
OTE2 SG2 OC2 OL2
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
Field
Bits
Type
Description
OLSG2
0
undef
Open Load or Short to Ground Detection CH2
0B No Fault Detected
1B Fault Detected
OL2
1
undef
Open Load Detection CH2
0B No Fault Detected
1B Fault Detected
(table continues...)
Datasheet
62
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
(continued)
Field
Bits
Type
Description
OC2
2
undef
Overcurrent Detection CH2
0B No Fault Detected
1B Fault Detected
SG2
±
undef
undef
undef
undef
undef
undef
undef
Short to Ground Detection CH2
0B No Fault Detected
1B Fault Detected
OTE2
OLSG±
OL±
4
Overtemperature Error Detection CH2
0B No Fault Detected
1B Fault Detected
.
Open Load or Short to Ground Detection CH3
0B No Fault Detected
1B Fault Detected
9
Open Load Detection CH3
0B No Fault Detected
1B Fault Detected
OC±
10
11
12
Overcurrent Detection CH3
0B No Fault Detected
1B Fault Detected
SG±
Short to Ground Detection CH3
0B No Fault Detected
1B Fault Detected
OTE±
Overtemperature Error Detection CH3
0B No Fault Detected
1B Fault Detected
5.3.2.14
Diagnosis Warning Register 0
Diagnosis Warning Register Channel Grouꢁ 0
DIAG_WARN_CHGR0
Diagnosis Warning Register 0
Offstꢀ address:
0010H
1010H
value:
15
14
Res
r
1±
12
11
10
9
.
7
6
Res
r
5
4
±
2
1
0
OLS
OLS
G_W OLS
I_RE PWM
G_W OLS
I_RE PWM
ARN G_W OTW G_W _REG
ARN G_W OTW G_W _REG
1_CH ARN
1
ARN _WA
0_CH ARN
0
ARN _WA
K_N
OK
1
1
RN1
K_N
OK
0
0
RN0
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
Datasheet
6±
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
Field
Bits
Type
Description
PWM_REG_Wm 0
RN0
undef
ICC PWM Regulation Warning Detection CH0
0B No Warning Detected
1B Warning Detected
I_REG_WmRN0
OTW0
1
2
±
4
undef
undef
undef
undef
undef
undef
undef
undef
undef
ICC Current Regulation Warning CH0
0B No Warning Detected
1B Warning Detected
Overtemperature Warning Detection CH0
0B No Warning Detected
1B Warning Detected
OLSG_WmRN0
Open Load or Short to Ground Warning Detection CH0
0B No Warning Detected
1B Warning Detected
OLSG_WmRN0
_CHK_NOK
Open Load or Short to Ground Warning Detection performed CH0
0B OLSG Warning Detection ꢁerforꢀed
1B OLSG Warning Detection not ꢁossible
PWM_REG_Wm .
RN1
ICC PWM Regulation Warning Detection CH1
0B No Warning Detected
1B Warning Detected
I_REG_WmRN1
OTW1
9
ICC Current Regulation Warning CH1
0B No Warning Detected
1B Warning Detected
10
Overtemperature Warning Detection CH1
0B No Warning Detected
1B Warning Detected
OLSG_WmRN1 11
Open Load or Short to Ground Warning Detection CH1
0B No Warning Detected
1B Warning Detected
OLSG_WmRN1 12
_CHK_NOK
Open Load or Short to Ground Warning Detection performed CH1
0B OLSG Warning Detection ꢁerforꢀed
1B OLSG Warning Detection not ꢁossible
5.3.2.15
Diagnosis Warning Register 1
Diagnosis Warning Register Channel Grouꢁ 1
DIAG_WARN_CHGR1
Diagnosis Warning Register 1
Offstꢀ address:
0011H
1010H
value:
Datasheet
64
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
14
Res
r
1±
12
11
10
9
.
7
6
Res
r
5
4
±
2
1
0
OLS
OLS
G_W OLS
I_RE PWM
G_W OLS
I_RE PWM
ARN G_W OTW G_W _REG
ARN G_W OTW G_W _REG
3_CH ARN
3
ARN _WA
2_CH ARN
2
ARN _WA
K_N
OK
3
3
RN3
K_N
OK
2
2
RN2
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
Field
Bits
Type
Description
PWM_REG_Wm 0
RN2
undef
ICC PWM Regulation Warning Detection CH2
0B No Warning Detected
1B Warning Detected
I_REG_WmRN2
OTW2
1
2
±
4
undef
undef
undef
undef
undef
undef
undef
undef
undef
ICC Current Regulation Warning CH2
0B No Warning Detected
1B Warning Detected
Overtemperature Warning Detection CH2
0B No Warning Detected
1B Warning Detected
OLSG_WmRN2
Open Load or Short to Ground Warning Detection CH2
0B No Warning Detected
1B Warning Detected
OLSG_WmRN2
_CHK_NOK
Open Load or Short to Ground Warning Detection performed CH2
0B OLSG Warning Detection ꢁerforꢀed
1B Warning Detected
PWM_REG_Wm .
RN±
ICC PWM Regulation Warning Detection CH3
0B No Warning Detected
1B Warning Detected
I_REG_WmRN±
OTW±
9
ICC Current Regulation Warning CH3
0B No Warning Detected
1B Warning Detected
10
Overtemperature Warning Detection CH3
0B No Warning Detected
1B Warning Detected
OLSG_WmRN± 11
Open Load or Short to Ground Warning Detection CH3
0B No Warning Detected
1B Warning Detected
OLSG_WmRN± 12
_CHK_NOK
Open Load or Short to Ground Warning Detection performed CH3
0B OLSG Warning Detection ꢁerforꢀed
1B OLSG Warning Detection not ꢁossible
Datasheet
65
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.2.16
Fault Mask Register 0
FmULTN-ꢁin Mask 0 Register
FAULT_MASK0
Fault Mask Register 0
Offstꢀ address:
0016H
C00FH
value:
15
14
1±
12
11
10
9
.
Res
r
7
6
5
4
±
2
1
0
SUP
SUP_
NOK_
EXT_
CH3_ CH2_ CH1_ CH0_
ERR_ ERR_ ERR_ ERR_
MAS MAS MAS MAS
_NO EN_P
K_IN IN_M
T_M ASK
ASK
MASK
K
K
K
K
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
CH0_ERR_MmS 0
K
rw
OC0, SG0, OL0, OTE0, OLSG0 FAULTN-pin Indication
0B Disabled
1B Enabled
CH1_ERR_MmS 1
K
rw
rw
rw
rw
rw
rw
OC1, SG1, OL1, OTE1, OLSG1 FAULTN-pin Indication
0B Disabled
1B Enabled
CH2_ERR_MmS 2
K
OC2, SG2, OL2, OTE2, OLSG2 FAULTN-pin Indication
0B Disabled
1B Enabled
CH±_ERR_MmS ±
K
OC3, SG3, OL3, OTE3, OLSG3 FAULTN-pin Indication
0B Disabled
1B Enabled
EN_PIN_MmSK 1±
EN-pin Status at FAULTN-pin Indication
0B Disabled
1B Enabled
SUP_NOK_INT 14
_MmSK
Internal Supply UV/OV at FAULTN-pin Indication (SUP_NOK_INT)
0B Disabled
1B Enabled
SUP_NOK_EXT 15
_MmSK
External Supply UV/OV at FAULTN-pin Indication (SUP_NOK_EXT)
0B Disabled
1B Enabled
5.3.2.17
Fault Mask Register 1
FmULTN-ꢁin Mask 1 Register
FAULT_MASK1
Fault Mask Register 1
Offstꢀ address:
0017H
700FH
value:
Datasheet
66
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
Res
r
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
CLK_ COTE COT
LOW RR_ WAR
_MA MAS N_M
CH3_ CH2_ CH1_ CH0_
WAR WAR WAR WAR
N_M N_M N_M N_M
ASK ASK ASK ASK
Res
SK
rw
K
rw
ASK
rw
r
rw
rw
rw
rw
Field
Bits
Type
Description
CH0_WmRN_M
mSK
0
rw
CH0 Warning at FAULTN-pin Indication (OTW, I_REG_WARN,
PWM_REG_WARN, OLSG_WARN)
0B Disabled
1B Enabled
CH1_WmRN_M
mSK
1
2
±
rw
rw
rw
rw
CH1 Warning at FAULTN-pin Indication (OTW, I_REG_WARN,
PWM_REG_WARN, OLSG_WARN)
0B Disabled
1B Enabled
CH2_WmRN_M
mSK
CH2 Warning at FAULTN-pin Indication (OTW, I_REG_WARN,
PWM_REG_WARN, OLSG_WARN)
0B Disabled
1B Enabled
CH±_WmRN_M
mSK
CH3 Warning at FAULTN-pin Indication (OTW, I_REG_WARN,
PWM_REG_WARN, OLSG_WARN)
0B Disabled
1B Enabled
COTWmRN_Mm 12
SK
Central Overtemperature Warning at FAULTN-pin Indication
(COTWRN)
0B Disabled
1B Enabled
COTERR_MmS 1±
K
rw
rw
Central Overtemperature Error at FAULTN-pin Indication (COTERR)
0B Disabled
1B Enabled
CLK_LOW_Mm 14
SK
Clock too Slow at FAULTN-pin Indication (DIG_CLK_TOO_SLOW,
CLK_TOO_SLOW)
0B Disabled
1B Enabled
5.3.2.18
Fault Mask Register 2
FmULTN-ꢁin Mask 2 Register
FAULT_MASK2
Fault Mask Register 2
Offstꢀ address:
001.H
C000H
value:
Datasheet
67
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
DATA
_ERR
_MA
SK
SPI_
WD_
Res
MASK
rw
rw
r
Field
Bits
Type
Description
DmTm_ERR_Mm 14
SK
rw
Data Error at FAULTN-pin Indication (DATA_ERR)
0B Disabled
1B Enabled
SPI_WD_MmSK 15
rw
SPI Watchdog Fault at FAULTN-pin Indication (SPI_WD_ERR)
0B Disabled
1B Enabled
5.3.2.19
Clock Control Register
Clock Control Register: write access only ꢁossible in Config Mode
CLK_DIV
Clock Control Register
Offstꢀ address:
0019H
04±.H
value:
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
EXT_
CLK
PLL_REFDIV
PLL_FBDIV
undef
undef
undef
Field
Bits
Type
Description
PLL_FBDIV
PLL_REFDIV
EXT_CLK
.:0
undef
PLL feedback divider
<PLL_FBDIV> = 56 MHz * <PLL_REFDIV> / f CLK
14:9
15
undef
undef
PLL reference divider
<PLL_REFDIV> = round( f CLK / 1 MHz )
Clock Source Selection
0B Internal Clock
1B External clock (CLK-ꢁin)
5.3.2.20
BIST Register
Built In Self Test (BIST) register: write access only ꢁossible in Config Mode
SFF_BIST
BIST Register
Offstꢀ address:
00±FH
0000H
value:
Datasheet
6.
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
15
14
1±
12
11
10
Res
r
9
.
7
6
5
4
±
2
1
0
SMU SMU SMU SMU
_SLF _SLF _SLF _SLF
_TST _TST _TST _TST
_CER _UE _FAI _DO
SMU
_SLF
_TST
_EN
R
undef
RR
undef
L
undef
NE
undef
undef
Field
Bits
Type
Description
BIST Enable
0B BIST not triggered
1B BIST triggered
SMU_SLF_TST
_EN
0
undef
SMU_SLF_TST
_DONE
1
2
±
4
undef
undef
undef
undef
BIST Done
0B BIST not done
1B BIST done
SMU_SLF_TST
_FmIL
BIST Sequence
0B Passed
1B Failed
SMU_SLF_TST
_UERR
BIST Uncorrectable Errors
0B Not Tested
1B Tested
SMU_SLF_TST
_CERR
BIST Correctable Errors
0B Not Tested
1B Tested
5.3.2.21
IC version and ID
Version Register
ICVID
Version Register
Offstꢀ address:
0200H
C1XXH
value:
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
MANUFACTURER
VERSION
undef
undef
Field
Bits
Type
Description
VERSION
7:0
undef
Chip Version
FCH B11 Design Steꢁ
FDH B12 Design Steꢁ
FEH B1± Design Steꢁ
FFH B15 Design Steꢁ
MmNUFmCTUR 15:.
ER
undef
Manufacturer ID
Datasheet
69
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.2.22
Pin Status Register
Pin Status Feedback Register
PIN_STAT
Pin Status Register
Offstꢀ address:
0201H
0000H
value:
15
14
1±
12
11
Res
r
10
9
.
7
6
5
4
±
2
1
0
FAUL
TN_F
B
FAUL
TN
EN DRV3 DRV2 DRV1 DRV0
undef
undef
undef
undef
undef
undef
undef
Field
Bits
Type
Description
DRV0
0
undef
Logic Level of DRV0-pin
0B Low
1B High
DRV1
DRV2
DRV±
EN
1
2
±
4
5
undef
undef
undef
undef
undef
Logic Level of DRV1-pin
0B Low
1B High
Logic Level of DRV2-pin
0B Low
1B High
Logic Level of DRV3-pin
0B Low
1B High
Logic Level of EN-pin
0B Low
1B High
FmULTN
Internal Status of FAULTN-pin according to Fault Mask
Configuration
0B Fault detected
1B No Fault detected
FmULTN_FB
6
undef
Logic Level of FAULTN-pin
0B Low
1B High
5.3.2.23
Feedback Status Register
General status register
FB_STAT
Offstꢀ address:
0202H
Feedback Status Register
Reset values see:
Table 21
Datasheet
70
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
21
20
19
1.
17
16
INIT_ SPI_
DON WD_
Res
E
ERR
undef
undef
r
15
14
1±
12
11
10
9
.
7
6
5
Res
r
4
±
2
1
0
OLS OLS
G_W G_W
ARN ARN
_CH _CH
K_N K_N
OK_ OK_
CHG CHG
DIAG DIAG
_WA _WA
SUP SUP
ERR_ ERR_
CHGR CHG
POR RES_ COT
_eve even WAR
_NO _NO DATA
K_IN K_EX _err
COTE CLK_
RR NOK
Res RN_ RN_
CHG CHG
1
R0
nt
t
N
T
T
R1
R0
R1
undef
R0
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
r
undef
undef
Field
Bits
Type
Description
DImG_WmRN_C 0
HGR0
undef
Current status of DIAG_WARN_CHGR0 register (excluding
<OLSG_WARNx_CHK_NOK>)
0B No Warning detected
1B Warning detected
DImG_WmRN_C 1
HGR1
undef
undef
undef
Current status of DIAG_WARN_CHGR1 register (excluding
<OLSG_WARNx_CHK_NOK>)
0B No Warning detected
1B Warning detected
OLSG_WmRN_
CHK_NOK_CH
GR0
±
4
Current status of <OLSG_WARNx_CHK_NOK> bit in the
DIAG_WARN_CHGR0 register
0B No Warning detected
1B Warning detected
OLSG_WmRN_
CHK_NOK_CH
GR1
Current status of <OLSG_WARNx_CHK_NOK> bit in the
DIAG_WARN_CHGR1 register
0B No Warning detected
1B Warning detected
CLK_NOK
COTERR
6
7
.
9
undef
undef
undef
undef
Current status of CLK_NOK in GLOBAL_DIAG0 register
0B No Fault detected
1B Fault detected
Current status of COTERR in GLOBAL DIAG0 register
0B No Fault detected
1B Fault detected
COTWmRN
RES_event
Current status of COTWARN in GLOBAL DIAG0 register
0B No Warning detected
1B Warning detected
Current status of RES_event in GLOBAL DIAG0 register
0B No Reset Event
1B Reset occurred
(table continues...)
Datasheet
71
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
(continued)
Field
Bits
Type
Description
POR_event
10
undef
Current status of POR_event in GLOBAL DIAG0 register
0B No ꢁower on Reset
1B Power on Reset occurred
DmTm_err
11
undef
undef
undef
Current status of <OTP_ECC_ERR>, <OTP_VIRGIN>, <HV_ADC_ERR>
0B No Fault detected
1B Fault detected
SUP_NOK_EXT 12
SUP_NOK_INT 1±
Current status of <VIO_UV/OV>, <VDD_UV/OV>, <VBAT_UV/OV>
0B No Fault detected
1B Fault detected
Current status of <VDD2V5_UV/OV>, <REF_UV/OV>, <VR_IREF_UV/
OV>, <VPRE_OV>
0B No Fault detected
1B Fault detected
ERR_CHGR0
ERR_CHGR1
14
15
undef
undef
undef
undef
Current status of DIAG_ERR_CHGR1 register
0B No Fault detected
1B Fault detected
Current status of DIAG_ERR_CHGR2 register
0B No Fault detected
1B Fault detected
SPI_WD_ERR 20
Current status of <SPI_WD_ERR>
0B No Fault detected
1B Fault detected
INIT_DONE
21
Chip Initialization
0B Not Done
1B Done
Table 21
Reset values of FB_STmT
Reset type
Reset value
Note
10 0000 0000
0110 0001
1000B
5.3.2.24
Feedback Voltage Register 1
Suꢁꢁly Voltage Feedback Register 1
FB_VOLTAGE1
Offstꢀ address:
020±H
Feedback Voltage Register 1
value:
XX XXXXH
Datasheet
72
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
21
20
19
1.
17
16
VDD
undef
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
VDD
undef
VIO
undef
Field
Bits
Type
Description
VIO Voltage
VIO
10:0
undef
V IO = 0ꢂ00±45±4 V * <VIO>
VDD
21:11
undef
VDD Voltage
V DD = 0ꢂ00±45±4 V * <VDD>
5.3.2.25
Feedback Voltage Register 2
Suꢁꢁly Voltage Feedback Register 2
FB_VOLTAGE2
Offstꢀ address:
0204H
Feedback Voltage Register 2
value:
XX XXXXH
21
20
19
1.
17
16
VBAT
undef
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
VBAT
undef
TEMP_VALUE
undef
Field
Bits
Type
Description
TEMP_VmLUE 10:0
undef
Temperature Feedback
T FB =(<TEMP_VmLUE>*0ꢂ00059± - 0ꢂ.19 )/(-0ꢂ0016 ) [Celsius]
VBmT
21:11
undef
VBAT Voltage
V BmT = 41ꢂ47 V * <VBmT>/(2^11-1)
Datasheet
7±
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3
Channel registers
5.3.3.1
Register Overview - channelRegs (ascending Offset Address)
Table 22
Register Overview - channelRegs (ascending Offset Address)
Short Name
Long Name
Offset
Page
Address
Number
SETPOINT
CTRL
Setꢁoint Register
0000H
0001H
0002H
000±H
0004H
0005H
0006H
0007H
000CH
000DH
000EH
0200H
0201H
0202H
020±H
0204H
0205H
0206H
75
76
77
7.
79
.0
.1
.2
.4
.5
.6
.7
..
.9
90
91
92
9±
Control Register
PERIOD
ICC PWM Frequency Controller Register
INTEGRmTOR_LIMIT ICC Integrator Liꢀitation Register
DITHER_CLK_DIV
DITHER_STEP
DITHER_CTRL
CH_CONFIG
MODE
Dither Clock Register
Dither Steꢁ Register
Dither Control Register
Channel Configuration Register
Channel Mode Register
On-Tiꢀe Register
TON
CTRL_INT_THRESH ICC Integrator Threshold Control Register
FB_DC
Feedback Duty Cycle Register
Feedback mverage VBmT
FB_VBmT
FB_I_mVG
Feedback mverage Current
Feedback Min/Max Current
Feedback signed Current
FB_IMIN_IMmX
FB_I_mVG_s16
FB_INT_THRESH
Feedback ICC Integrator Threshold
FB_PERIOD_MIN_Mm Feedback Min/Max PWM Period
X
5.3.3.2
Register Address Space - channelRegs
Table 23
Registers Address Space - channelRegs
Base Address End Address Note
Module
CH0
00000040H
00000050H
00000060H
00000070H
000100±EH
0001004EH
0001005EH
0001006EH
CH1
CH2
CH±
Datasheet
74
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.3
Setpoint Register
Current Setꢁoint Register
SETPOINT
Setꢁoint Register
Offstꢀ address:
0000H
0000H
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
AUTO
_LIMI
T_DIS
TARGET
rwh
rwh
Field
Bits
Type
Description
TmRGET
14:0
rwh
Current Setpoint Target
I set = 2m * <TmRGET> / ( 2^15 - 1)
I set,ꢁar = 4m * <TmRGET> / ( 2^15 - 1)
NOTE: Values higher than 0x6000 are saturated
mUTO_LIMIT_D 15
IS
rwh
Autolimit Feature
0B Enabled
1B Disabled
Datasheet
75
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.4
Control Register
Channel Control Register
CTRL
Control Register
Offstꢀ address:
0001H
4600H
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
PWM
_PER
IOD_
CALC
_MO
DE
OLS
G_W
ARN
_EN
Res
OLSG_WARN_WINDOW
MIN_INT_THRESH
r
rw
rw
rw
rw
Field
Bits
Type
Description
MIN_INT_THR 7:0
ESH
rw
Minimum limit for ICC integrator threshold
The value is signed: -12. to 127
PWM_PERIOD
_CmLC_MODE
.
rw
ICC PWM controller does not consider falling Dither Slope
0B No disabling of threshold calculation
1B Skiꢁ threshold calculation on falling dither
OLSG_WmRN_ 1±:9
WINDOW
rw
rw
OLSG Warning Detection Blanking Time
t OLwindow= (<OLSG_WmRN_WINDOW>+1) * 64 * 1/ fsys
OLSG_WmRN_ 14
EN
OLSG Warning Detection
0B Disable warning
1B Enable warning
Datasheet
76
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.5
ICC PWM Frequency Controller Register
ICC PWM Frequency Controller Register
PERIOD
Offstꢀ address:
0002H
0000H
ICC PWM Frequency Controller Register
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
LOW
_FRE
Q_R
PWM_CTRL_PARAM
PERIOD_EXP
PERIOD_MANT
ANG
E_EN
rw
rw
rw
rw
Field
Bits
Type
Description
PERIOD_MmNT 7:0
rw
Mantissa of PWM Target Frequency
t PWM = <PERIOD_MmNT> * 2^<PERIOD_EXP> * 1/f sys
<PERIOD_MmNT> = 0 disables the ICC PWM Frequency Controller
PERIOD_EXP 10:.
rw
rw
Exponent of PWM Target Frequency
t PWM = <PERIOD_MmNT> * 2^<PERIOD_EXP> * 1/f sys
LOW_FREQ_R 11
mNGE_EN
Low PWM Frequency Range
t PWM = <PERID_MmNT> * . * 2^<PERIOD_EXP> * 1/f sys
0B Disabled
1B Enabled
PWM_CTRL_P 15:12
mRmM
rw
Control parameter ki of PWM Frequency Controller
Datasheet
77
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2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.6
ICC Integrator Limitation Register
ICC Integrator Liꢀitation Register
INTEGRATOR_LIMIT
ICC Integrator Liꢀitation Register
Offstꢀ address:
000±H
4±FFH
Value
15
Res
r
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
AUTO_LIM_VALUE_ABS
LIM_VALUE_ABS
rw
rw
Field
Bits
Type
Description
LIM_VmLUE_m 9:0
BS
rw
Absolut Integrator Limit of ICC
mUTO_LIM_Vm 14:10
LUE_mBS
rw
Integrator Limit of ICC afeꢀ a setpoint update (Autolimit)
Datasheet
7.
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.7
Dither Clock Register
Dither Period Configuration
DITHER_CLK_DIV
Dither Clock Register
Offstꢀ address:
0004H
0000H
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
DITH
ER_S
ETPO
INT_S
YNC_
EN
DITH
ER_P
WM_
SYNC
_EN
EXP
MANT
rw
rw
rw
rw
Field
Bits
Type
Description
MmNT
9:0
rw
Mantissa of Dither Reference Clock
t ref_clk = (<MmNT> * 2 <EXP>) * 1/f sys
EXP
1±:10
rw
rw
Exponent of Dither Reference Clock
t ref_clk = (<MmNT> * 2 <EXP>) * 1/f sys
DITHER_PWM 14
_SYNC_EN
Synchronization of Dither Period with PWM Period
0B Disabled
1B Enabled
DITHER_SETP 15
OINT_SYNC_E
N
rw
Synchronization of the Dither Period to a setpoint change
0B Disabled
1B Enabled
Datasheet
79
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.8
Dither Step Register
Dither mꢀꢁlitude Configuration
DITHER_STEP
Dither Steꢁ Register
Offstꢀ address:
0005H
0000H
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
STEPS
FLAT
rw
rw
Field
Bits
Type
Description
FLmT
7:0
rw
Number of flat Dither Reference Clocks tref_clk on top and bottom
of the Dither waveform
t flat= <FLmT> * t ref_clk
STEPS
15:.
rw
Number of Dither steps within a quarter Dither Period
T Dither = [4* (<STEPS>) + 2 * <FLmT> ] * t ref_clk
I Dither =<STEPS>*<STEP_SIZE> * 2 m / (215-1)
NOTE: If <STEP_SIZE> = 0, the dither overlay I Dither is disabledꢂ
NOTE: If <STEPS> = 0, the dither overlay I Dither is disabled and the
dither ꢁeriod T Dither is deterꢀined by <FLmT>
NOTE: If <STEPS> = 0 and <FLmT> = 0, the dither ꢁeriod T Dither=t ref_clk
Datasheet
.0
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.9
Dither Control Register
Dither Control Register
DITHER_CTRL
Dither Control Register
Offstꢀ address:
0006H
0000H
Value
15
14
1±
12
Res
r
11
10
9
.
7
6
5
4
±
2
1
0
DEE
P_DI
THE
R
Res
STEP_SIZE
r
rw
rw
Field
STEP_SIZE
Bits
Type
Description
11:0
rw
Size of Dither Steps resulting in a Dither Amplitude IDither
I Dither =<STEPS>*<STEP_SIZE> * 2 m / (215-1)
DEEP_DITHER 1±
rw
Deep Dither Feature
0B Disabled
1B Enabled
Datasheet
.1
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.10
Channel Configuration Register
Channel Configuration Register
CH_CONFIG
Channel Configuration Register
Offstꢀ address:
0007H
000±H
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
OC_
DIAG
_EN
OFF_DIAG_C
H
OL_TH_FIXED
OL_TH
rw
I_DIAG
SLEWR
rwh
rwh
rw
rw
rw
Field
Bits
Type
Description
SLEWR
1:0
rw
Channel Slew Rate
00B 1ꢂ0 V/us
01B 2ꢂ5 V/us
10B 5ꢂ0 V/us
11B 10ꢂ0 V/us
I_DImG
OL_TH
±:2
6:4
rw
rw
OFF-state Diagosis Current Strength
00B .0 um
01B 190 um
10B 720 um
11B 1250 um
Open Load Threshold relative to Setpoint
000B Disabled
001B 1/. of Current Setꢁoint
010B 2/. of Current Setꢁoint
011B ±/. of Current Setꢁoint
100B 4/. of Current Setꢁoint
101B 5/. of Current Setꢁoint
110B 6/. of Current Setꢁoint
111B 7/. of Current Setꢁoint
OL_TH_FIXED 12:7
OC_DImG_EN 1±
rw
Fixed Open Load Threshold
I OLTH = <OL_TH_FIXED> * 12. * 2000ꢀm / (2^15 - 1)
I OLTH,ꢁarallel = <OL_TH_FIXED> * 12. * 4000ꢀm / (2^15 - 1)
rwh
OC Diagnosis in OFF-state
0B Disabled
1B Enable Outꢁut Stage for t_OCon
tOCon = [(<TON_MmNT>+1)*2^<EXP>)] * 1/fSYS
NOTE: <TON_MmNT> is located in the TON registerꢂ
NOTE: <EXP> is located in the DITHER_CLK_DIV registerꢂ
(table continues...)
Datasheet
.2
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
(continued)
Field
Bits
Type
Description
OFF_DImG_CH 15:14
rwh
OFF-state Diagnosis Current Sources Control
00B OFF-state Diagnosis Enabled
01B Low Side Current Source Enabled
10B High Side Current Source Enabled
11B OFF-state Diagnosis Disabled
Datasheet
.±
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.11
Channel Mode Register
Channel Mode Register: write access only ꢁossible in Config Mode
MODE
Channel Mode Register
Offstꢀ address:
000CH
0000H
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
Res
CH_MODE
r
rw
Field
Bits
Type
Description
CH_MODE
±:0
rw
Channel Operation Mode
0H Off
1H ICC Current Control
2H Direct Drive Mode via SPI on-tiꢀe setting (TON register)
Direct Drive Mode via DRVx-ꢁin
±
H
CH Free running Measureꢀent (2^16 saꢀꢁles)
Datasheet
.4
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.12
On-Time Register
Driver On-Tiꢀe Configuration Register
TON
On-Tiꢀe Register
Offstꢀ address:
000DH
0000H
Value
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
OLSG_TIMEOUT
TON_MANT
rw
rw
Field
Bits
Type
Description
TON_MmNT
9:0
rw
On-Time of Output stage (SPI Direct Drive Mode/OC-Detection)
t OCon = [(<TON_MmNT>+1)*2^<EXP>)] * 1/f sys
NOTE: For OC detection in OFF-state the ꢀaxiꢀuꢀ t on ꢁeriod is ±00ꢀs
and <TON_MmNT> ꢀust be difftetnꢀ to 0ꢂ
t on = (<TON_MmNT> * 2^<EXP>) * 1/f sys
NOTE: The Period is derived froꢀ the Dither Period (DITHER_CLK_DIV)
NOTE: <EXP> is located in the DITHER_CLK_DIV register
OLSG_TIMEOU 15:10
T
rw
Time out period for OLSG detection
t OLSG_TIMEOUT = (<OLSG_TIMEOUT> *256 +255) *64 * 1/f sys
Datasheet
.5
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.13
ICC Integrator Threshold Control Register
ICC Integrator Threshold Control Register
CTRL_INT_THRESH
ICC Integrator Threshold Control Register
Offstꢀ address:
000EH
000±H
Value
15
14
1±
12
Res
r
11
10
9
.
7
6
5
4
±
2
1
0
INT_THRESH
rw
Field
Bits
Type
Description
INT_THRESH .:0
rw
ICC Integrator Threshold which determines the on-time of the PWM
period
NOTE: <INT_THRESH> is used as inital threshold value for the ICC PWM
Frequency Controllerꢂ
Datasheet
.6
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.14
Feedback Duty Cycle Register
Duty Cycle Feedback Value
Read Only Register
FB_DC
Offstꢀ address:
0200H
Feedback Duty Cycle Register
Value
00 0000H
21
20
19
1.
17
16
TO_MANT
rh
15
14
1±
TO_MANT
rh
12
11
10
9
.
7
6
5
TP_MANT
rh
4
±
2
1
0
Field
Bits
Type
Description
TP_MmNT
10:0
rh
Period Mantissa
T ꢀeas = <TP_MmNT> * 2^<EXP> * 1/f sys
NOTE: <EXP> is located in the FB_VBmT or FB_I_mVG registerꢂ
TO_MmNT
21:11
rh
On-time Mantissa
t ON = <TO_MmNT>*2^<EXP> * 1/f sys
DC = <TO_MmNT>/<TP_MmNT>
NOTE: <EXP> is located in the FB_VBmT or FB_I_mVG registerꢂ
Datasheet
.7
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.15
Feedback Average VBAT
mverage Battery Voltage (VBmT) Feedback Register
Read Only Register
FB_VBAT
Offstꢀ address:
0201H
Feedback mverage VBmT
Value
00 0000H
21
20
19
1.
17
16
Res
r
15
14
1±
12
11
Res
r
10
9
.
7
6
5
4
±
2
1
0
EXP
rh
VBAT_AVG_MANT
rh
Field
Bits
Type
Description
VBmT_mVG_Mm 10:0
NT
rh
Average Battery Voltage Mantissa
V BmT = 41ꢂ47V * <VBmT_mVG_MmNT>/<TP_MmNT>
NOTE: <TP_MmNT> is located in the FB_DC register
EXP
15:12
rh
Measurement Exponent
Datasheet
..
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.16
Feedback Average Current
mverage Current Feedback Value
Read Only Register
FB_I_AVG
Offstꢀ address:
0202H
Feedback mverage Current
Value
00 0000H
21
20
19
1.
17
16
Res
r
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
EXP
I_AVG_MANT
rh
rh
Field
Bits
Type
Description
I_mVG_MmNT 11:0
rh
Signed Mantissa of Average Current Feedback (two's complement)
I avg = 4m * <I_mVG_MmNT> / <TP_MmNT>
NOTE: <TP_MmNT> is located in the FB_DC register
EXP
15:12
rh
Measurement Exponent
Datasheet
.9
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.17
Feedback Min/Max Current
Miniꢀuꢀ/Maxiꢀuꢀ Current Feedback Register
Read Only Register
FB_IMIN_IMAX
Offstꢀ address:
020±H
Feedback Min/Max Current
Value
00 0000H
21
20
19
1.
17
16
Res
IMAX
r
rh
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
IMAX
IMIN
rh
rh
Field
Bits
Type
Description
IMIN
9:0
rh
Signed Minimum Current of last measurement period (two's
complement)
I ꢀin = <IMIN>*4m / (2^9-1)
IMmX
19:10
rh
Signed Maximum Current of last measurement period (two's
complement)
I ꢀax = <IMmX>*4m / (2^9-1)
Datasheet
90
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.18
Feedback signed Current
Signed mverage Current Measureꢀent over free running ꢁeriod (2^16 fsys cycles)
Read Only Register
FB_I_AVG_s16
Offstꢀ address:
0204H
Feedback signed Current
Value
00 0000H
21
20
19
1.
17
16
I_AV
G_s1
6
TIME_STAM
P
Res
rh
r
rh
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
I_AVG_s16
rh
Field
Bits
Type
Description
I_mVG_s16
16:0
rh
Average Current Measurement over free running period (2^16 fsys
cycles) - two's complement
I avg16 = 4m* <I_mVG_s16>/(2^16-1)
TIME_STmMP 21:20
rh
Time Stamp for signed Average Current Measurement over free
running period
Datasheet
91
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.19
Feedback ICC Integrator Threshold
ICC PWM Frequency Controller Integrator Thershold Feedback
Read Only Register
FB_INT_THRESH
Offstꢀ address:
0205H
Feedback ICC Integrator Threshold
Value
00 01.0H
21
20
19
1.
17
16
Res
r
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
INT_THRESH_VAL
rh
Field
Bits
Type
Description
INT_THRESH_ 15:0
VmL
rh
ICC PWM Frequency Controller Calculated Integrator Threshold
Value
Datasheet
92
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Serial peripheral interface (SPI)
5.3.3.20
Feedback Min/Max PWM Period
Miniꢀuꢀ and Maxiꢀuꢀ PWM Frequency Feedback of last Measureꢀent ꢁeriod
Read Only Register
FB_PERIOD_MIN_MAX
Offstꢀ address:
0206H
Feedback Min/Max PWM Period
Value
00 0000H
21
20
19
1.
17
16
Res
PMAX
r
rh
15
14
1±
12
11
10
9
.
7
6
5
4
±
2
1
0
PMAX
PMIN
rh
rh
Field
Bits
Type
Description
PMIN
9:0
rh
Minimum PWM period of last Measurement period
f PWM_ꢀin = f sys / (<PMIN> * 256)
PMmX
19:10
rh
Maximum PWM period of last Measurement period
f PWM_ꢀax = f sys / (<PMmX> * 256)
Datasheet
9±
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Application information
6
Application information
6.1
TDS_Application information
The following aꢁꢁlication diagraꢀ shows how the IC is used in its environꢀentꢂ
VBAT
Vsup
C1
Reverse polarity
SSxSense
SSxD
Protection
and
Filter
Power-supply incl. High-side Driver
e.g. TLE9243QK
Safety Switch
Circuitry
SSxG
SSxS
GND
VDD
C3
Low-side Solenoid Driver IC
C5
Power Supply,
Battery sense
and
Under/Over
Voltage Detection
GND
GND
GND
VBAT
C2
PLL
Clock Watchdog
Lx
Dx
Channel x
Micro-Controller
e.g. TC27x
EN
LOADy
C
RESN
Load
LOADx
Diagnostics
CLK
LOADx
C
R
Channel Logic,
Current Control,
Dither
FAULTN
DRVx
Current
Sense
Central Logic
FWDx
FWDx
C
Temperature
Sense
Low-side
Gate Control
Overcurrent
Protection
GNDPx
VIO
GND
SPI
C4
GND
Watchdog
SCK
CSN
SI
SPI
SO
GND
R = 10kΩ
C1 = 100µF
C2 = C3 = C4 = C5 = 100nF
LOADx
C
= 4.7nF…10nF
LOADy
LOADx
= 4.7nF…10nF; C
LOADy
FWDx
/10; C = 4.7nF…10nF
recommended: C
= C
Note: This is a simplified example of an application circuit with focus on the Low-side Solenoid Driver IC. The function must be verified in the real application.
Figure 26
Simplified Application Circuit
Datasheet
94
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Package dimensions
7
Package dimensions
7.1
TDS_Package dimensions
Figure 27
Package outlines
Green Product
To ꢀeet the world-wide custoꢀer requireꢀents for environꢀentally friendly ꢁroducts and to be coꢀꢁliant with
the governꢀent regulations the device is available as a Green Productꢂ Green Products are RoHS coꢀꢁliant
(Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020)ꢂ
Datasheet
95
Revꢂ 1ꢂ0
2021-12-15
TLE92464EDHP
High accuracy four channel low-side solenoid driver IC
Revision history
Revision history
Revision
Date
Changes
Datasheet v1ꢂ0
2021-12-15 Initial release
Datasheet
96
Revꢂ 1ꢂ0
2021-12-15
Trademarks
mll referenced ꢁroduct or service naꢀes and tradeꢀarks are the ꢁroꢁerty of their resꢁective ownersꢂ
Edition 2021-12-15
Published by
Infineon Technologies AG
81726 Munich, Germany
IMPORTANT NOTICE
WARNINGS
The inforꢀation given in this docuꢀent shall in no
event be regarded as a guarantee of conditions or
characteristics (“Btschafftnhtiꢀsgaeanꢀit”).
With resꢁect to any exaꢀꢁles, hints or any tyꢁical
values stated herein and/or any inforꢀation regarding
the aꢁꢁlication of the ꢁroduct, Infineon Technologies
hereby disclaiꢀs any and all warranties and liabilities
of any kind, including without liꢀitation warranties of
non-infringeꢀent of intellectual ꢁroꢁerty rights of any
third ꢁartyꢂ
In addition, any inforꢀation given in this docuꢀent is
subject to custoꢀer’s coꢀꢁliance with its obligations
stated in this docuꢀent and any aꢁꢁlicable legal
requireꢀents, norꢀs and standards concerning
custoꢀer’s ꢁroducts and any use of the ꢁroduct of
Infineon Technologies in custoꢀer’s aꢁꢁlicationsꢂ
Due to technical requireꢀents ꢁroducts ꢀay contain
dangerous substancesꢂ For inforꢀation on the tyꢁes
in question ꢁlease contact your nearest Infineon
Technologies offict.
Exceꢁt as otherwise exꢁlicitly aꢁꢁroved by Infineon
Technologies in
authorized reꢁresentatives of Infineon Technologies,
Infineon Technologies’ ꢁroducts ꢀay not be used in
any aꢁꢁlications where a failure of the ꢁroduct or
any consequences of the use thereof can reasonably
be exꢁected to result in ꢁersonal injuryꢂ
a written docuꢀent signed by
©
2021 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
IFX-ntz1491827137291
The data contained in this docuꢀent is exclusively
intended for technically trained sꢀaff. It is the
resꢁonsibility of custoꢀer’s technical deꢁartꢀents to
evaluate the suitability of the ꢁroduct for the intended
aꢁꢁlication and the coꢀꢁleteness of the ꢁroduct
inforꢀation given in this docuꢀent with resꢁect to such
aꢁꢁlicationꢂ
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