TLE9853QX_技术文档

TLE9853QX

Arm® Cortex®-M0 Microcontroller with LIN and H-Bridge NFET

Driver for Automotive Applications

AD-Step

1

Overview

Features

•

32-bit Arm® Cortex®*-M0 Core

–

up to 40 MHz clock frequency

one clock per machine cycle architecture

single cycle multiplier

•

On-chip memory

–

48 KB Flash (including EEPROM)

4 KB EEPROM (emulated in Flash)

512 bytes 100 Time Programmable Memory (100TP)

4 KB RAM

Boot ROM for startup firmware and Flash routines

•

Math Co-Processor Unit with Divider Unit for signed and unsigned 32-bit division operations

On-chip OSC and PLL for clock generation

–

PLL loss-of-lock detection

•

MOSFET Driver including charge pump for H-Bridge motor applications

Current Sense Amplifier

High-Side Switch with cyclic sense option and PWM functionality, e.g. for supplying LEDs or switch panels

(min. 150 mA)

•

4 High Voltage Monitor Input pins for wake-up and with cyclic sense with analog measurement option

10 General-purpose I/O Ports (GPIO)

5 Analog input Ports

10-Bit A/D Converter with 5 analog inputs + VBAT_SENSE + VS + 4 high voltage monitoring inputs

8-Bit A/D Converter with 9 inputs for voltage and temperature supervision

Measurement unit with 12 channels together with the onboard 10-Bit A/D converter and data post

processing

•

16-Bit timers - GPT12, Timer 2 and Timer 21

*

Arm and Cortex are registered trademarks of Arm Limited, UK

Datasheet

www.infineon.com

1

Rev. 1.0

2019-07-26

TLE9853QX

Overview

•

Capture/compare unit for PWM signal generation (CCU6)

2 full duplex serial interfaces (UART1, UART2), UART1 with LIN support

2 synchronous serial channels (SSC1, SSC2)

On-chip debug support via 2-wire SWD

1 LIN 2.2 transceiver

Single power supply V_S= 5.5 V to 28 V

Extended supply voltage range V_S= 3 V to 28 V

Low-dropout voltage regulators (LDO)

5 V voltage supply VDDEXT for external loads (e.g. Hall-sensor)

Core logic supply at 1.5 V

Programmable window watchdog (WDT1) with independent on-chip clock source

Power saving modes:

–

Micro Controller Unit slow-down mode

Sleep Mode with cyclic sense option

Cyclic wake-up during Sleep Mode

Stop Mode with cyclic sense option

•

Power-on and undervoltage/brownout reset generator

Overtemperature protection incl. shutdown

Short circuit protection for all voltage regulators and actuators (High Side Switch)

Loss of clock detection with fail safe mode for power switches

Temperature Range T_j= -40°C to +150°C

Package VQFN-48-31 with LTI feature

Green package (RoHS compliant)

AEC Qualified

Potential applications

•

Window lift

Sunroof

Single-phase DC pumps and fans, e.g. HVAC blower

Single-phase BLDC pumps and fans, e.g. single-phase water pump

... and other LIN addressed motor control applications

Product validation

Qualified for Automotive Applications. Product Validation according to AEC-Q100/101

Description

TLE985x devices integrate an Arm® Cortex®-M0 processor and peripherals for motor control, power supply and

communication. Two integrated measurement units (analog-to-digital converters) for monitoring

temperature, battery voltage and four monitoring inputs help to save pins. These inputs can be operated

directly with battery voltage, which saves costs on additional components such as external voltage dividers or

Datasheet

2

Rev. 1.0

2019-07-26

TLE9853QX

Overview

shutdown transistors. Furthermore, the chips are equipped with two full duplex serial interfaces (UART) with

LIN support.

A new feature in the TLE985x family is its adaptive MOSFET driver. The control algorithm is able to compensate

MOSFET parameter spread in the system by automatically adjusting the gate current according to required

switching times. This allows an optimization of the system concerning EME (electro-magnetic emissions, slow

slew rates) as well as power dissipation (short dead times) simultaneously.

The product family includes several devices with different flash sizes (48 - 96KB) and temperature ranges (T_j

up to 175°C). In addition, different numbers of half-bridge drivers for uni- or bidirectional DC motor

applications are offered.

All TLE985x products are based on the same hardware and software platform as Infineon's other Embedded

Power products (TLE984x, TLE986x and TLE987x), thus enabling design synergies and allowing customers to

reuse parts of the software. The devices come in a leadless VQFN package with a footprint of 7x7 mm.

Type

Package

Marking

TLE9853QX

VQFN-48-31

TLE9853QX

Datasheet

3

Rev. 1.0

2019-07-26

TLE9853QX

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2

3

3.1

3.2

General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4

Modes of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5

5.1

5.2

5.2.1

5.2.2

5.3

5.3.1

5.3.2

5.3.3

5.3.4

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PMU Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power Supply Generation (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power-on Reset Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6

6.1

6.2

6.2.1

6.3

6.3.1

6.3.2

6.3.2.1

6.3.2.2

6.3.3

System Control Unit - Digital Modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

External Input Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

External Crystal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Clock Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7

System Control Unit - Power Modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1

7.2

7.2.1

8

Arm® Cortex®-M0 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1

8.2

8.2.1

9

Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10

Datasheet

4

Rev. 1.0

2019-07-26

TLE9853QX

10.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.2

10.2.1

10.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

NVM Module (Flash Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11

Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11.1

11.2

11.2.1

12

Math Divider Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12.1

12.2

12.3

13

13.1

13.2

Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

14

14.1

14.2

14.2.1

14.2.2

14.3

14.3.1

14.3.1.1

14.3.1.2

14.3.1.3

GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

15

15.1

General Purpose Timer Units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Features Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Features Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Block Diagram GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Block Diagram GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

15.1.1

15.1.2

15.2

15.2.1

15.2.2

16

Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Timer2 and Timer21 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

16.1

16.2

16.2.1

17

Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

17.1

17.2

17.2.1

18

UART1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

18.1

18.2

18.2.1

18.3

Datasheet

5

Rev. 1.0

2019-07-26

TLE9853QX

19

LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

19.1

19.2

19.2.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

20

High-Speed Synchronous Serial Interface SSC1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

20.1

20.2

20.2.1

21

Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

21.1

21.2

21.2.1

22

Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

22.1

22.2

22.2.1

23

Analog Digital Converter ADC10B (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

23.1

23.2

23.2.1

24

High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

24.1

24.2

24.2.1

25

High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

25.1

25.2

25.2.1

25.2.2

26

26.1

26.2

Bridge Driver (incl. Charge Pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Flexible Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Current-Driven Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Switch-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Switch-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Adjustable Cross-Conduction Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

High-Current Discharge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Passive Pull-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Brake Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Hold Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

26.2.1

26.2.2

26.2.3

26.2.3.1

26.2.3.2

26.2.3.3

26.2.3.4

26.2.4

26.2.5

26.2.6

26.2.7

26.2.8

26.2.9

Datasheet

6

Rev. 1.0

2019-07-26

TLE9853QX

26.2.10

26.2.11

26.2.12

26.2.13

26.2.14

26.2.15

Adaptive Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Integrated 2-Stage Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Adjustable Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Adjustable Short Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Open-Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

27

Current Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

27.1

27.2

27.2.1

28

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Window-Lift Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Connection of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Connection of P0.2 for SWD debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Connection of TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

28.1

28.2

28.3

28.4

28.5

29

29.1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PMU Input Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PMU I/O Supply Parameters VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PMU Core Supply Parameters VDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

VDDEXT Voltage Regulator 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

VPRE Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Load Sharing Scenario of VPRE Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Power Down Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Electrical Characteristics Oscillators and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

External Clock Parameters XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Description of Keep and Force Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

DC Parameters Port 0, Port 1, TMS, Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

DC Parameters Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

SSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

29.1.1

29.1.2

29.1.3

29.1.4

29.1.5

29.2

29.2.1

29.2.2

29.2.3

29.2.4

29.2.5

29.2.5.1

29.2.6

29.3

29.3.1

29.3.2

29.4

29.4.1

29.5

29.5.1

29.5.2

29.5.3

29.6

29.6.1

29.7

29.7.1

29.8

29.8.1

Datasheet

7

Rev. 1.0

2019-07-26

TLE9853QX

29.8.2

29.8.2.1

29.9

29.9.1

29.10

29.10.1

29.11

29.11.1

29.12

Central Temperature Sensor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Electrical Characteristics ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

High-Voltage Monitoring Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

High Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

29.12.1

29.13

29.13.1

30

31

32

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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TLE9853QX

Block Diagram

2

Block Diagram

TMS

P0.0

DEBUG

INTERFACE

Arm^(R)

FLASH

SRAM

slave

ROM

slave

Cortex^(R)-M0

systembus

slave

Multilayer AHB Matrix

slave

PBA0

slave

PBA1

* P2.0, ...P2.7

(AN0, … AN7)

VS

MON 1...4

ADC10B

DPP1

VBAT_SENSE

P0.0 – P0.x

P1.0 – P1.x

P2.0 – P2.x

UART1

GPIO

UART2

GPT12

LIN

GNDLIN

LIN-

Transceiver

OP1

OP2

SSC1

SSC2

CSA

ADC8B

DPP2

T2

MEASUNIT

HS

High Side

T21

PMU

Power

Control

&

System

Functions

VS

VSD

RESET

VDDEXT

VDDP

VDDC

OSC+PLL

CP1L

CP1H

CP2L

CP2H

VCP

WDT

SCU_DM

Charge

Pump

CCU6

1- 4 MON

MON 1...4

WDT1

SCU_PM

MON 1...4

VDH

GH2

SH2

GH1

SH1

GL2

GL1

FET Driver

SL

* P2.0, P2.1, P2.2, P2.3, P2.7

(AN0, AN1, AN2, AN3, AN7)

Figure 1

Block Diagram TLE9853QX

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TLE9853QX

General Device Information

3

General Device Information

3.1

Pin Configurations

24 P0.0

P2.7 37

P2.3 38

23 TMS/DAP1

22 P0.1

EP

P2.1 39

21 GNDP

20 MON4

19 MON3

18 MON2

17 MON1

16 VDH

P2.2 / XTAL2 40

P2.0 / XTAL1 41

VDDC 42

TLE 985x

GNDA 43

VDDP 44

VDDEXT 45

VS 46

15 VSD

14 CP1H

13 CP1L

VBAT_SENSE 47

LIN 48

TLE985x V.02

Low Voltage Pin

High Voltage Pin

Figure 2

Pin Configuration VQFN-48, TLE9853QX

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TLE9853QX

General Device Information

3.2

Pin Definitions and Functions

After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings:

•

Pull-up enabled only (PU)

Pull-down enabled only (PD)

Input with both pull-up and pull-down disabled (I)

Output with output stage deactivated = high impedance state (Hi-Z)

The functions and default states of the TLE9853QX external pins are provided in the following table.

Type: indicates the pin type.

•

I/O: Input or output

I: Input only

O: Output only

P: Power supply

Not all alternate functions listed, see Chapter 14.

Table 1

Symbol

Pin Definitions and Functions

Type Reset Function

Number

State

P0

Port 0

Port 0 is a 6-Bit bidirectional general purpose I/O port.

Alternate functions can be assigned and are listed in the Port

description. Main function is listed below.

P0.0

24

I/O

I/PU

SWD_CLK

GPIO

Serial Wire Debug Clock

General Purpose IO

Alternate function mapping see Table 7

P0.1

P0.2

P0.3

P0.4

P0.5

P1

22

26

27

28

29

I/O

I/PU

I/PD

I/PU

GPIO

Port 1

General Purpose IO

Alternate function mapping see Table 7

General Purpose IO

Alternate function mapping see Table 7

General Purpose IO

Alternate function mapping see Table 7

General Purpose IO

Alternate function mapping see Table 7

General Purpose IO

Alternate function mapping see Table 7

Port 1 is a 4-Bit bidirectional general purpose I/O port.

Alternate functions can be assigned and are listed in the Port

description. Main function is listed below.

P1.0

P1.1

P1.2

31

32

33

I/O

I

GPIO

General Purpose IO

Alternate function mapping see Table 8

General Purpose IO

Alternate function mapping see Table 8

General Purpose IO

Alternate function mapping see Table 8

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General Device Information

Table 1

Symbol

Pin Definitions and Functions (cont’d)

Type Reset Function

State

Number

P1.4

34

I/O

I

GPIO

General Purpose IO

Alternate function mapping see Table 8

P2

Port 2

Port 2 is a 5-Bit general purpose input-only port.

Alternate functions can be assigned and are listed in the Port

description. Main function is listed below.

P2.0

41

I

AN0

ADC1 analog input channel 6

External oscillator input

Alternate function mapping see Table 9

XTAL1¹⁾

P2.1

P2.2

39

40

AN1

ADC1 analog input channel 7

Alternate function mapping see Table 9

I

O

I

AN2

ADC1 analog input channel 8

External oscillator output

Hi-Z

XTAL2¹⁾

Alternate function mapping see Table 9

P2.3

P2.7

38

37

I

AN3

AN7

ADC1 analog input channel 9

Alternate function mapping see Table 9

ADC1 analog input channel 12

Alternate function mapping see Table 9

Power Supply

VS

46

44

P

–

Battery supply input

VDDP

I/O port supply (5.0 V). Do not connect external loads. For

buffer and bypass capacitors.

VDDC

42

P

–

Core supply (1.5 V during Active Mode,

0.9 V during Stop Mode). Do not connect external loads. For

buffer/bypass capacitor.

VDDEXT

GNDP

45

P

–

External voltage supply output (5.0 V, 40 mA)

Core supply ground

21, 30

43

GNDA

Analog supply ground

GNDLIN

Monitor Inputs

MON1

1

LIN ground

17

18

19

20

I

High Voltage Monitor Input 1

High Voltage Monitor Input 2

High Voltage Monitor Input 3

High Voltage Monitor Input 4

MON2

MON3

MON4

High Side Switch Outputs

HS

2

O

Hi-Z

PU

–

High Side Switch output

LIN Interface

LIN

48

14

I/O

P

LIN bus interface input/output

Charge Pump

CP1H

Charge Pump Capacity 1 High, connect external C

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TLE9853QX

General Device Information

Table 1

Symbol

Pin Definitions and Functions (cont’d)

Type Reset Function

State

Number

CP1L

CP2H

CP2L

VCP

13

11

10

12

15

P

–

Charge Pump Capacity 1 Low, connect external C

Charge Pump Capacity 2 High, connect external C

Charge Pump Capacity 2 Low, connect external C

Charge Pump Capacity

VSD

Battery supply input for Charge Pump

MOSFET Driver

VDH

16

3

P

–

Voltage Drain High Side MOSFET Driver

Gate High Side FET 1

GH1

GH2

9

Gate High Side FET 2

SH1

4

Source High Side FET 1

Source High Side FET 2

Gate Low Side FET 1

SH2

8

GL1

5

GL2

7

Gate Low Side FET 2

SL

6

Source Low Side FETs

Others

TMS

23

25

I

I/PD

TMS

DAP1

test mode select input

RESET

I/O

I/O/PU Bidirectional reset input/output, not available during Sleep

Mode

VBAT_SENSE 47

I

Battery supply voltage sense input

Negative current sense amplifier input

Positive current sense amplifier input

Exposed Pad, connect to GND

OP1

OP2

EP

35

36

–

I

–

I

–

1) configurable by user

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TLE9853QX

Modes of Operations

4

Modes of Operations

This highly integrated circuit contains analog and digital functional blocks. For system and interface control

an embedded 32-Bit Arm® Cortex®-M0 microcontroller is included. For internal and external power supply

purposes, on-chip low drop-out regulators are existent. An internal oscillator (no external components

necessary) provides a cost effective and suitable clock in particular for LIN slave nodes. As communication

interface, a LIN transceiver and several High Voltage Monitor Inputs with adjustable threshold and filters are

available. Furthermore one High-Side Switch (e.g. for driving LEDs or powering of switches), a driver for 4 n-

channel MOSFETs including a two-stage charge pump and several general purpose input/outputs (GPIO) with

pulse-width modulation (PWM) capabilities are available.

The Micro Controller Unit supervision and system protection including reset feature is controlled by a

programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated

temperature sensors are available on-chip.

All relevant modules offer power saving modes in order to support terminal 30 connected automotive

applications. A wake-up from the power saving mode is possible via a LIN bus message, via the monitoring

inputs or repetitive with a programmable time period (cyclic wake-up).

The integrated circuit is available in a VQFN-48-31 package with 0.5 mm pitch and is designed to withstand the

challenging conditions of automotive applications.

The TLE9853QX has several operational modes mainly to support low power consumption requirements. The

low power modes and state transitions are depicted in Figure 3 below.

Reset

Transition by software Transition by external event

Safety Fallback Transition by internal event

Active Mode

Stop Mode

Sleep Mode

PMU_System_Modes.vsd

Figure 3

Power Control State Diagram

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TLE9853QX

Modes of Operations

Reset Mode

The Reset Mode is a transition mode e.g. during power-up of the device after a power-on reset. In this mode

the on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is

stable, the Active Mode is entered . In case the watchdog timer WDT1 fails for more than four times, a fail-safe

transition to the Sleep Mode is done.

Active Mode

In Active Mode all modules are activated and the TLE9853QX is fully operational.

Stop Mode

The Stop Mode is one out of two major low power modes. The transition to the low power modes is done by

setting the respective Bits in the mode control register. In Stop Mode the embedded microcontroller is still

powered allowing faster wake-up reaction times, but not clocked. A wake-up from this mode is possible by LIN

bus activity, the High Voltage Monitor Input pins or the respective 5V GPIOs.

Sleep Mode

The Sleep Mode is a major low-power mode. The transition to the low-power modes is done by setting the

respective Bits in the Micro Controller Unit mode control register. The sleep time is configurable. In Sleep

Mode the embedded microcontroller power supply is deactivated, allowing the lowest system power

consumption, but the wake-up time is longer compared to the Stop Mode. In this mode a 64 bit wide buffer for

data storage is available. A wake-up from this mode is possible by LIN bus activity or the High Voltage Monitor

Input pins and cyclic wake. A wake-up from Sleep Mode behaves similar to a power-on reset. While changing

into Sleep Mode, no incoming wake-requests are lost (i.e. no dead-time). It is possible to enter sleep-mode

even with LIN dominant.

Cyclic Wake-up Mode

The cyclic wake-up mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to

the cyclic wake-up mode is done by first setting the respective Bits in the mode control register followed by

the SLEEP or STOP command. Additional to the cyclic wake-up behavior (wake-up after a programmable time

period), the wake-up sources of the normal Stop Mode and Sleep Mode are available.

Cyclic Sense Mode

The cyclic sense mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the

cyclic sense mode is done by first setting the respective Bits in the mode control register followed by the STOP

or SLEEP command. In cyclic sense mode the High Side Switch can be switched on periodically for biasing

some switches for example. The wake-up condition is configurable, when the sense result of defined monitor

inputs at a window of interest changed compared to the previous wake-up period or reached a defined state

respectively. In this case the Active Mode is entered immediately.

The following table shows the possible power mode configurations of each major module or function

respectively.

Table 2

Power Mode Configurations

Module/function

VPRE, VDDP, VDDC

VDDEXT

Active Mode Sleep Mode

Stop Mode

ON

Comment

ON

OFF

–

ON/OFF

OFF

cyclic ON/OFF

–

HS

cyclic ON/OFF

cyclic sense

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TLE9853QX

Modes of Operations

Table 2

Power Mode Configurations (cont’d)

Module/function

Bridge Driver

LIN TRx

Active Mode Sleep Mode

Stop Mode

OFF¹⁾

Comment

ON/OFF

OFF¹⁾

–

wake-up only / OFF wake-up only/

OFF

MONx (wake-up)

MONx (measurement)

VS sense

n.a.

disabled/static/

cyclic

disabled/static/ cyclic: combined with

cyclic

HS=on

ON/OFF

OFF

available on all

channels

ON/OFF

brownout

detection

brownout detection brownout

detection

brownout det. done

in PCU

VBAT_SENSE

GPIO 5V

ON/OFF

ON

OFF

ON

–

WDT1

ON

OFF

CYCLIC WAKE

n.a.

cyclic wake-up/

cyclic sense/OFF

cyclic wake-up/ cyclic sense with HS;

cyclic sense/OFF wake-up needs MC

for enter Sleep Mode

again

Measurement

ON²⁾

OFF

–

Micro Controller Unit

ON/slow-

down/STOP

CLOCK GEN (MC)

ON

OFF

ON

OFF

ON

–

LP_CLK (f_{LP_CLK}

)

WDT1

LP_CLK2 (f_{LP_CLK2}

)

for cyclic wake-up

1) Bridge Driver “Hold Mode” is available in sleep mode and stop mode.

2) May not be switched off due to safety reasons

Wake-up Source Prioritization

All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up

sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are

latched in order to provide all wake-up events to the application software. The software can clear the wake-

up source flags. It is ensured, that no wake-up event is lost.

As default wake-up sources, MON inputs and cyclic wake are activated after power-on reset, LIN is disabled as

wake-up source by default.

Wake-up Levels and Transitions

The wake-up can be triggered by rising, falling or both signal edges for each monitor input individually.

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TLE9853QX

Power Management Unit (PMU)

5

Power Management Unit (PMU)

5.1

Features

•

System modes control (startup, sleep, stop and active)

Power management (cyclic wake, cyclic sense)

Control of system voltage regulators with diagnosis (overload, short, overvoltage)

Fail safe mode detection and operation in case of system errors

Wake-up sources configuration and management (LIN, MON, GPIOs)

System error logging

5.2

Introduction

The purpose of the power management unit is to ensure the fail safe behavior of the system IC. Therefore the

power management unit controls all system modes including the corresponding transitions. The power

management unit is responsible for generating all needed voltage supplies for the embedded MCU (VDDC,

VDDP) and the external supply (VDDEXT). Additionally, the PMU provides well defined sequences for the

system mode transitions and generates hierarchical reset priorities. The reset priorities control the reset

behavior of all system functionalities especially the reset behavior of the embedded MCU. All these functions

are controlled by finite state machines. The system master functionality of the PMU requires the generation of

an independent logic supply and system clock. Therefore the PMU has a module internal logic supply and

system clock which works independently of the MCU clock.

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TLE9853QX

Power Management Unit (PMU)

5.2.1

Block Diagram

The following figure shows the structure of the Power Management Unit. Table 3 describes the submodules

more detailed.

VS

Power Down Supply

VDDP

VDDC

Power Supply Generation Unit

(PGU)

I

N

T

E

R

N

A

L

e.g. for WDT 1

LP_CLK

Peripherals

LDO for External Supply

VDDEXT

e.g. for cyclic

wake and sense

LP_CLK2

B

U

S

PMU-PCU

PMU-SFR

MON1...4

LIN

P0. 0... P0.4

P1. 0... P1.4

PMU-CMU

PMU-RMU

PMU-WMU

RESET

PMU-Control

Power Management Unit

Power_Management_985x.vsd

Figure 4

Table 3

Power Management Unit Block Diagram

Description of PMU Submodules

Mod.

Modules

Functions

Name

Power Down Independent Supply Voltage

This supply is dedicated to the PMU to ensure an

independent operation from generated power supplies

(VDDP, VDDC).

Supply

Generation for PMU

LP_CLK

(= f_{LP_CLK}

- Clock Source for all PMU

submodules

This ultra low power oscillator generates the clock for

the PMU.

)

- Backup Clock Source for System This clock is also used as backup clock for the system in

(can be selected as fsys clock

source through

case of PLL Clock failure and as independent clock

source for WDT1.

SCU_APCLK.SYSCLKSEL)

- Clock Source for WDT1

LP_CLK2

(= f_{LP_CLK2}

Clock Source for PMU

This ultra low power oscillator generates the clock for

the PMU in Stop Mode and in the cyclic modes.

)

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Power Management Unit (PMU)

Table 3

Description of PMU Submodules (cont’d)

Mod.

Modules

Functions

Name

Peripherals

Peripheral Blocks of PMU

These blocks include the analog peripherals to ensure a

stable and fail safe PMU startup and operation

(bandgap, bias).

Power Supply Voltage regulators for VDDP and

This block includes the voltage regulators for the pad

supply (VDDP) and the core supply (VDDC).

Generation

Unit (PGU)

VDDC

VDDEXT

Voltage regulator for VDDEXT to

supply external modules (e.g.

Sensors)

This voltage regulator is a dedicated supply for external

modules.

PMU-SFR

PMU-PCU

All PMU relevant Extended Special This module contains all PMU relevant registers, which

Function Registers

are needed to control and monitor the PMU.

Power Control Unit of the PMU

This block is responsible for controlling all power

related actions within the PGU Module.It also contains

all regulator related diagnosis like under- and

overvoltage detection, overcurrent and short circuit

diagnoses.

PMU-WMU

PMU-CMU

PMU-RMU

Wake-up Management Unit of the This block is responsible for controlling all Wake-up

PMU

related actions within the PMU Module.

Cyclic Management Unit of the

PMU

This block is responsible for controlling all actions

within cyclic mode.

Reset Management Unit of the PMU This block generates resets triggered by the PMU like

undervoltage or short circuit reset, and passes all resets

to the relevant modules and their register. A reset status

register with every reset source is available.

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Power Management Unit (PMU)

5.2.2

PMU Modes Overview

The following state diagram shows the available modes of the device.

V_S> 4V and V_Sramp up

or

VS

< 3V and V

S

ramp down

LIN-wake or

MON-wake or

cyclic -wake

start-up

VDDC =stable and

error_supp<5

VDDC / VDDP = fail

(short circuit )

à error_supp ++

error_supp = 5

sleep

active

Sleep command (from MCU ) or

WDT1_SEQ_FAIL = 1 (à error_wdt = 5) or

VDDC / VDDP = overload

LIN-wake or

MON-wake or

GPIO-wake or

cyclic_wake or

PMU_PIN = 1 or

SUP_TMOUT = 1

PMU_PIN = 1 or

PMU_SOFT = 1 or

(PMU_Ext_WDT = 1 and

WDT1_SEQ_FAIL = 0

à error_wdt ++)

cyclic sense

Stop

command

(from MCU)

stop

cyclic sense

Figure 5

Power Management Unit System Modes

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TLE9853QX

Power Management Unit (PMU)

5.3

Power Supply Generation (PGU)

5.3.1

Voltage Regulator 5.0V (VDDP)

This module represents the 5 V voltage regulator, which provides the pad supply for the parallel port pins and

other 5 V analog functions (e.g. LIN Transceiver).

Features

•

5 V low-drop voltage regulator

Overcurrent Monitoring and Shutdown with MCU signalling (Interrupt)

Overvoltage monitoring with MCU signalling (Interrupt)

Undervoltage monitoring with MCU signalling (Interrupt)

Undervoltage monitoring with Reset (UnderVoltage Reset, V_DDPUV

Overtemperature Shutdown with MCU signalling (Interrupt)

Pre-Regulator for VDDC Regulator

)

GPIO Supply

Pull Down Current Source at the output for Sleep Mode only

The output capacitor C_VDDPis mandatory to ensure a proper regulator functionality.

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Power Management Unit (PMU)

VDDP Regulator

VS

VDDP

VPRE

A

CVDDP

V

GND

I

5V LDO

LDO Supervision

LDO_block_external .vsd

Figure 6

Module Block Diagram of VDDP Voltage Regulator

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Power Management Unit (PMU)

5.3.2

Voltage Regulator 1.5V (VDDC)

This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core,

digital peripherals and other chip internal analog 1.5 V functions (e.g. ADC).

Features

•

1.5 V low-drop voltage regulator

Overcurrent monitoring and Shutdown with MCU signalling (Interrupt)

Overvoltage monitoring with MCU signalling (Interrupt)

Undervoltage monitoring with MCU signalling (interrupt)

Undervoltage monitoring with reset

Overtemperature Shutdown with MCU signalling (Interrupt)

Pull Down Current Source at the output for Sleep Mode only

The output capacitor C_VDDCis mandatory to ensure a proper regulator functionality.

VDDC Regulator

VDDP (5V)

VDDC (1.5V)

A

V

C_VDDP

C_VDDC

I

1.5V LDO

LDO Supervision

1.5VLDOblockexternal.vsd

Figure 7

Module Block Diagram of VDDC Voltage Regulator

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TLE9853QX

Power Management Unit (PMU)

5.3.3

External Voltage Regulator 5.0V (VDDEXT)

This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used

e.g. to supply an external sensor, LEDs or potentiometers.

Features

•

Switchable (by software) 5 V low-drop voltage regulator

Switch-on undervoltage blanking time in order to drive small capacitive loads

Intrinsic current limitation

Undervoltage monitoring and shutdown with MCU signalling (Interrupt)

Overtemperature Shutdown with MCU signalling (Interrupt)

Resistive discharge path at the output if the regulator is off

Cyclic sense option together with GPIOs

Low current mode available to ensure reduced stop mode current consumption. In this mode current

capability is reduced to I_{VDDEXT_LCM}

The output capacitor C_VDDEXTis mandatory to ensure a proper regulator functionality.

VDDEXTRegulator

VS

VDDEXT (5V)

C_VDDEXT

V

C_VS

V

VDDEXTLDO

Supervision

HALL_LDOblockexternal.vsd

Figure 8

Module Block Diagram

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Power Management Unit (PMU)

5.3.4

Power-on Reset Concept

Vs

ca. 4V

1.5V

Power Down RESET_N

LP_Clk

VDDP

5V

ca. 3.5V

3V

VDDC

1.5V

fail

stable

ok

SUPPLY_STATUS

RESET_PIN

PMU_RESET_STS

xxh

80h

Down

Start-up

Active

SYSTEM_STATE

Figure 9

Power-on Reset Concept

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TLE9853QX

System Control Unit - Digital Modules (SCU-DM)

6

System Control Unit - Digital Modules (SCU-DM)

6.1

Features

•

Flexible clock configuration features

Reset management of all system resets

System modes control for all power modes (active, power down, sleep)

Interrupt enabling for many system peripherals

General purpose input output control

Debug mode control of system peripherals

6.2

Introduction

The System Control Unit (SCU) supports all central control tasks in the TLE9853QX. The SCU is made up of the

following sub-modules:

•

Clock System and Control (CGU)

Reset Control (RCU)

Power Management (PCU)

Interrupt Management (ICU)

General Port Control

Flexible Peripheral Management

Module Suspend Control

Watchdog Timer (WDT)

Error Detection and Correction in Data Memory

Miscellaneous Control

Register Mapping

Datasheet

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System Control Unit - Digital Modules (SCU-DM)

6.2.1

Block Diagram

on signalsto digital

peripherals;

statussignalsfrom

digital peripherals

AHB

PMCU

WDT

ICU

f_PCLK

I

N

T

E

R

N

A

L

XTAL1

CGU

f_OSC

OSC_HP

PLL

XTAL2

LP_CLK

NMI

f_SYS

f_PLL

f_PCLK

MI_CLK

INTISR <23:0>

CG

f

f_{TFILT _CLK}

B

U

S

PMU_1V5DidPOR

PMU_PIN

PMU_ExtWDT

PMU_IntWDT

PMU_SOFT

RCU

MISC Control

MODPISELx

PMU_Wake

RESET_TYPE_3

RESET_TYPE_4

P0_POCONy.PDMx

P1_POCONy.PDMx

PortControl

System Control Unit -Digital Modules

SCU_DM_Block_Diagram_Cust.vsd

Figure 10 System Control Unit - Digital Modules Block Diagram

IO description of SCU_DM:

•

CGU:

–

f

_sys; system clock

LP_CLK; low-power backup clock

•

RCU:

–

1V5DidPOR; Undervoltage reset of power down supply

PMU_PIN; Reset generated by reset pin

PMU_ExtWDT; WDT1 reset

PMU_IntWDT; WDT (SCU) reset

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System Control Unit - Digital Modules (SCU-DM)

–

PMU_SOFT; Software reset

PMU_Wake; Stop Mode exit with reset

Reset_Type_3; Peripheral reset (contains all resets)

Reset_Type_4; Peripheral reset (without SOFT and WDT reset)

•

Port Control:

–

P0_POCONy.PDMx; driver strength control

P1_POCONy.PDMx; driver strength control

•

MISC:

–

MODPISELx; Mode selection registers for UART (source selection) and Timer (trigger or count selection)

WDT (Watchdog Timer in SCU-DM): f_SYS; System clock

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System Control Unit - Digital Modules (SCU-DM)

6.3

Clock Generation Unit

The Clock Generation Unit (CGU) provides a flexible clock generation for TLE9853QX. During user program

execution the frequency can be programmed for an optimal ratio between performance and power

consumption. Therefore the power consumption can be adapted to the actual application state.

The CGU in the TLE9853QX consists of one oscillator circuit (OSC_HP), a Phase-Locked Loop (PLL) module

including an internal oscillator (OSC_PLL) and a Clock Control Unit (CCU). The CGU can convert a low-

frequency input/external clock signal to a high-frequency internal clock.

The system clock f_SYSis generated out of the following selectable clocks:

•

PLL clock output f_PLL

Direct clock from oscillator OSC_HP f_OSC

Direct output of internal Oscillator f_INTOSC

Low precision clock f_{LP_CLK}(HW-enabled for startup after reset and during power-down wake-up sequence)

The following sections describe the different parts of the CGU.

6.3.1

Low Precision Clock

The clock source LP_CLK is a low-precision RC oscillator (LP-OSC, see f_{LP_CLK}) that is enabled by hardware as

an independent clock source for the TLE9853QX startup after reset and during the power-down wake-up

sequence. There is no user configuration possible on f_{LP_CLK}

.

6.3.2

High Precision Oscillator Circuit (OSC_HP)

The high precision oscillator circuit, designed to work with both an external crystal oscillator or an external

stable clock source, consists of an inverting amplifier with XTAL1 as input, and XTAL2 as output.

Figure 11 shows the recommended external circuitries for both operating modes, External Crystal Mode and

External Input Clock Mode.

6.3.2.1 External Input Clock Mode

When supplying the clock signal directly, not using an external crystal and bypassing the oscillator, the input

frequency needs to be equal to or greater than 4 MHz if the PLL VCO part is used.

When using an external clock signal it must be connected to XTAL1. XTAL2 is left open (unconnected).

6.3.2.2 External Crystal Mode

When using an external crystal, its frequency can be within the range of 4 MHz to 16 MHz. An external oscillator

load circuitry must be used, connected to both pins, XTAL1 and XTAL2. It consists normally of the two load

capacitances C1 and C2, for some crystals a series damping resistor might be necessary. The exact values and

related operating range are dependent on the crystal and have to be determined and optimized together with

the crystal vendor using the negative resistance method. As starting point for the evaluation, the following

load cap values may be used:

Table 4

External CAP Capacitors

Fundamental Mode Crystal Frequency (approx., MHz) Load Caps C₁, C₂(pF)

4

33

18

12

10

8

12

16

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System Control Unit - Digital Modules (SCU-DM)

V

DDP

External Clock

Signal

XTAL1

OSC_HP

f

XTAL1

OSC_HP

f

OSC

4 - 16

MHz

XTAL2

C₁

C₂

Fundamental

Mode Crystal

V

SS

External Input Clock Mode

External Crystal Mode

V_SS= GND = PIN 43

Figure 11 TLE9853QX External Circuitry for the OSC_HP

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System Control Unit - Digital Modules (SCU-DM)

6.3.3

Clock Control Unit

The Clock Control Unit (CCU) receives the clock from the PLL f_PLL, the external input clock f_OSC, the internal

input clock f_INTOSC, or the low-precision input clock f_{LP_CLK}. The system frequency is derived from one of these

clock sources.

CCU

SYSCON0.SYSCLKSEL

f_PLL

f_OSC

M

U

f_SYS

f

X

INTOSC

f_{LP_CLK}

CCU_block

Figure 12 Clock Inputs to Clock Control Unit

The CCU generates all necessary clock signals within the microcontroller from the system clock. It consists of:

•

Clock slow down circuitry

Centralized enable/disable circuit for clock control

In normal running mode, the main module frequencies (synchronous unless otherwise stated) are as follows:

•

System frequency, f_SYS= up to 40 MHz (measurement interface clock MI_CLK is derived from this clock)

CPU clock (CCLK, SCLK) = up to 40 MHz (divide-down of NVM access clock)

NVM access clock (NVMACCCLK) = up to 40 MHz

Peripheral clock (PCLK, PCLK2, NVMCLK) = up to 40 MHz (equals CPU clock; must be same or higher)

Some peripherals are clocked by PCLK, others clocked by PCLK2 and the NVM is clocked by both NVMCLK and

NVMACCCLK. During normal running mode, PCLK = PCLK2 = NVMCLK = CCLK. On wake-up from power-down

mode, PCLK2 is restored similarly like NVMCLK, whereas PCLK is restored only after PLL is locked.

For optimized NVM access (read/write) with reduced wait state(s) and with respect to system requirements on

CPU operational frequency, bit field NVMCLKFAC is provided for setting the frequency factor between the NVM

access clock NVMACCCLK and the CPU clock CCLK.

For the slow down mode, the operating frequency is reduced using the slow down circuitry with clock divider

setting at the bit field CLKREL. Bit field CLKREL is only effective when slow down mode is enabled via SFR bit

PMCON0.SD bit. Note that the slow down setting of bit field CLKREL correspondingly reduces the NVMACCCLK

clock. Slow down setting does not influence the erase and write cycles for the NVM.

Peripherals UART1, UART2, T2 and T21 are not influenced by CLKREL and either not by NVMCLKFAC, to

allow functional LIN communication in slow down mode.

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System Control Unit - Digital Modules (SCU-DM)

Analog Subsystem/

PBA0 / PBA1

UART 1/2,

Timer 2/21,

Baudgen 1/2

f_SYS

ADC1_CLK

PCLK2

ADC1_CLK_DIV

DPP1_CLK_DIV

DPP1_CLK

DPP1

SFR

BRDRV_TFILT_DIV

BRDRV_TFILT_CLK

BRDRV_CLK_DIV

APCLK2FAC

Bridge Driver

BRDRV_CLK

PCLK2

Clock

Control Unit

SFR

TFILT_CLK

Analog

Peripherals

MI_CLK

PCLK2

APCLK1FAC

SFR

MI_CLK

Measurement

Interface

MI_CLK

PCLK2

PCLK

Peripherals

CLKREL

NVMCLKFAC

f_PLL

SCLK

CCLK

f_OSC

f

CORE

M

U

X

SYS

CCLK

f_INTOSC

f

LP_CLK

NVMCLK

NVM

NVMACCCLK

PBA0CLKREL

Peripherals

CORDIC

Peripherals

COREL

TLEN

Toggle

Latch

CLKOUT

LP-OSC

Watchdog

Timer

COUTS1

Figure 13 Clock Generation from f_sys; CLKOUT Generation

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System Control Unit - Power Modules (SCU-PM)

7

System Control Unit - Power Modules (SCU-PM)

7.1

Features

•

Clock Watchdog Unit (CWU): supervision of all power modules relevant clocks with NMI signalling.

Interrupt Control Unit (ICU): all system relevant interrupt flags and status flags.

Power Control Unit (PCU): takes over control when device enters and exits Sleep and Stop Mode.

External Watchdog (WDT1): independent system watchdog to monitor system activity

7.2

Introduction

7.2.1

Block Diagram

The System Control Unit of the power modules consists of the sub-modules in the figure shown below:

on signals to analog

peripherals;

status signals from

analog peripherals

AMBA AHB

I

N

T

PCU

WDT1

LP_CLK

E

R

N

A

L

fsys

MI_CLK

PREWARN_SUP_NMI

PREWARN_SUP_INT

INT<n:0>

B

U

S

CWU

ICU

TFILT_CLK

System ControlUnit -Power Modules

SCU_PM_Block_Diagram_Cust.vsd

Figure 14 Block diagram of System Control Unit - Power Modules

IO description of SCU_PM:

•

CWU:

–

check of f_sys= system frequency: output of PLL

check of MI_CLK = measurement interface clock (analog clock): derived out of f_sysby division factors

1/2/3/4

–

check of TFILT_CLK = clock used for digital filters: derived out of f_sysby configurable division factors

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System Control Unit - Power Modules (SCU-PM)

•

ICU:

–

PREWARN_SUP_NMI = generation of Prewarn-Supply NMI

PREWARN_CLK_INT = generation of Prewarn-Clock Watchdog NMI

INT = generation of MISC interrupts

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Arm® Cortex®-M0 Core

8

Arm® Cortex®-M0 Core

8.1

Features

The key features of the Arm® Cortex®-M0 implemented are listed below.

Processor Core. A low gate count core, with low latency interrupt processing:

•

Thumb^®+ Thumb-2^®Instruction Set

Banked stack pointer (SP) only

Handler and thread modes

Thumb and debug states

Interruptible-continued instructions LDM/STM, Push/Pop for low interrupt latency

Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and

exit

•

Arm® architecture v6-M Style

Arm®v6 unaligned accesses

Systick (typ. 1ms)

Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low

latency interrupt processing:

•

External interrupts, configurable from 1 to 24

7 interrupt priority registers for levels from 0 up to 192 in steps of 64

Dynamic repriorization of interrupts

Priority grouping. This enables selection of pre-empting interrupt levels and non pre-empting interrupt

levels

•

Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing

without the overhead of state saving and restoration between interrupts.

Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction

overhead

Bus interfaces

Advanced High-performance Bus-Lite (AHB-Lite) interfaces

•

8.2

Introduction

The Arm® Cortex®-M0 processor is a leading 32-bit processor and provides a high-performance and cost-

optimized platform for a broad range of applications including microcontrollers, automotive body systems

and industrial control systems. Like the other Arm® Cortex® family processors, the Arm® Cortex®-M0 processor

implements the Thumb^®-2 instruction set architecture. With the optimized feature set the Arm® Cortex®-M0

delivers 32-bit performance in an application space that is usually associated with 8- and 16-bit

microcontrollers.

8.2.1

Block Diagram

Figure 15 shows the functional blocks of the Arm® Cortex®-M0.

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Arm® Cortex®-M0 Core

Arm^(R)Cortex^(R)-M0 Processor

Nested Vectored

Interrupt

Breakpoint

Arm^(R)Cortex^(R)-M0

Interrupt and

Power Control

and

watchpoint

unit

processor

core

Controller

(NVIC)

Serial-Wire

Debug Access Port

(SW-DP)

Bus matrix

Debugger interface

AHB-Lite interface

Serial-Wire Debug

Interface

Figure 15 Arm® Cortex®-M0 Block Diagram

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Address Space Organization

9

Address Space Organization

The TLE9853QX manipulates operands in the following memory spaces:

•

48 KB of Flash memory in code space

24 KB Boot ROM memory in code space (used for boot code and IP storage)

4 KB RAM memory in Arm® Cortex®-M0 code region (RAM can be fetched, read/written as program memory)

Special function registers (SFRs) in peripheral linear address space

The on-chip memory modules available in the TLE9853QX are:

00000000_H/ 00005FFF_H

BROM, 24K

reserved

11000000_H/ 1100BFFF_H

1100C000_H/ 17FFFFFF_H

Flash, 48K

reserved

18000000_H/ 18000FFF_H

18001000_H/ 3FFFFFFF_H

SRAM, 4K

reserved

PBA0

40000000_H/ 47FFFFFF_H

48000000_H/ 5FFFFFFF_H

PBA1

60000000_H/ DFFFFFFF_H

E0000000_H/ E00FFFFF_H

E01FFFFF_H/ FFFFFFFF_H

reserved

Private Peripheral Bus

reserved

Figure 16 TLE9853QX Memory Map

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Memory Control Unit

10

Memory Control Unit

10.1

Features

•

Provides Memory access to ROM, RAM, NVM, Config Sector through AHB-Lite Interface

MBIST for RAM

MBIST for ROM

NVM Configuration with Special Function Registers through AHB-Lite Interface

Hardware Memory Protection Logic

Stack overflow detection

10.2

Introduction

10.2.1

Block Diagram

The Memory Control Unit (MCU) is divided in the following sub-modules:

•

NVM Memory module (embedded Flash Memory)

RAM memory module

BootROM memory module

Memory protection Unit (MPU) module

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Memory Control Unit

NVM

S0

RAM

S1

ROM

S2

PBA0

S3

Memory Protection

Unit

Sx: BusSlave

Mx: Bus Master

M0

M1

M2

M3

Bus Matrix

MCU_Block_Diagram_overview.vsd

Figure 17 Memory Control Unit Block View

Functional Features for RAM

•

4 KB RAM

Error correction code (ECC) for detection of single bit and double bit errors and dynamic correction of

single bit errors

•

Single byte access

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Memory Control Unit

10.3

NVM Module (Flash Memory)

The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and

reliable storage of user code and data.

Features

•

In-System Programming via LIN (Flash mode) and SWD

Error Correction Code (ECC) for detection of single Bit and double Bit errors and dynamic correction of

single Bit errors on Data Block (Double words, 64 bits).

•

Interrupt and signaling of double bit error by NMI, address of double bit error readable by FW API user

routine

•

Possibility of checking single bit error occurrence by ROM routines

Program width of 128 Byte (page)

Minimum erase width of 128 Byte (page)

Integrated hardware support for EEPROM emulation

8 Byte read access

Physical read access time: max. 75 ns

Code read access acceleration integrated (read buffer)

Page program time: typ. 3 ms

Page erase (128 bytes) and sector erase (4K bytes) time: typ. 4 ms

4 individual protection passwords for NVM customer BSL region, code region, data linear region, and data

mapped region

•

Security option to protect read out via debug interface in application run mode

Write/erase access to 100TP (e.g. option bytes) is possible via the debug interface

Note:

The user has to ensure that no flash operations which change the content of the flash get interrupted

at any time.

The clock for the NVM is supplied with the system frequency f_sys. Integrated firmware routines are provided to

ease NVM, and other operations including EEPROM emulation.

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Interrupt System

11

Interrupt System

11.1

Features

•

23 interrupt nodes for on-chip peripherals

8 NMI nodes for critical system events

Maximum flexibility (resp. priority and node grouping) for all interrupt nodes

11.2

Introduction

11.2.1

Overview

The TLE9853QX supports 24 interrupt vectors with 4 priority levels. 21 of these interrupt vectors are assigned

to the on-chip peripherals: GPT12, SSC1, SSC2, CCU6, High-Side Switch, WAKEUP, Bridge Driver, Charge Pump,

Differential Unit, Math Divider, GPIOs, MONs, CSA and A/D Converter are each assigned to one dedicated

interrupt vector; while UART1 and Timer2 or UART2, External Interrupt 2 and Timer21 share interrupt vectors.

Two vectors are dedicated for External Interrupt 0 and 1.

Table 5

Interrupt Vector Table

Service Request

GPT1

Node ID

Description

0

GPTimer 1 Interrupt

GPT2

1

GPTimer 2 Interrupt

MU

2

MU interrupt / ADC2, VBG interrupt

ADC10 Bit interrupt

ADC1

3

CCU0

4

CCU6 node 0 interrupt

CCU1

5

CCU6 node 1 interrupt

CCU2

6

CCU6 node 2 interrupt

CCU3

7

CCU6 node 3 interrupt

SSC1

8

SSC1 interrupt (receive, transmit, error)

SSC2 interrupt (receive, transmit, error)

UART1 interrupt (receive, transmit), Timer2, LIN sync, LIN

SSC2

9

UART1

UART2

10

11

UART2 interrupt (receive, transmit), Timer21, External Interrupt

(EINT2)

EXINT0

EXINT1

WAKEUP

Math Div

rfu

12

13

14

15

16

17

18

External interrupt (EINT0), wake-up

External interrupt (EINT1)

Wake-up interrupt (generated by a wake-up event)

Hardware Divider Unit Interrupt

Reserved for future use

CP

Charge Pump

BDRV

Bridge Driver

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Interrupt System

Table 5

Interrupt Vector Table (cont’d)

Service Request

Node ID

Description

HS

19

20

21

22

23

High Side Interrupt

CSA

Current Sense Amplifier Overcurrent Measurement

Differential Unit - DPP1

MONx Interrupt

DU

MONx

Port 2.x

Port 2.x - DPP1

Table 6

NMI Interrupt Table

Service Request

Node

NMI

Description

Watchdog Timer NMI

Watchdog Timer overflow

MI_CLK Watchdog Timer Overflow

MI_CLK Watchdog

Timer NMI

NMI

PLL NMI

NMI

PLL Loss-of-Lock

Overtemperature NMI NMI

System Overtemperature

Oscillator Watchdog

NMI

NVM Map Error NMI

ECC Error NMI

NMI

NVM Map Error

RAM / NVM Uncorrectable ECC Error

Supply Prewarning

Supply Prewarning NMI NMI

Stack overflow

NMI

Stack Overflow

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Math Divider Module

12

Math Divider Module

12.1

Features

The MATH Coprocessor includes the following features:

•

Divide function with operand pre-processing and result post-processing

AHB-Interface supports Byte/half word/ word Register access

Supports fast execution kernel clock faster than interface clock

12.2

Introduction

The MATH Coprocessor (MATH) module supports the CPU in math-intensive computations with a Divider Unit

(DIV) for signed and unsigned 32-bit division operations.

12.3

Block Diagram

Figure 18 shows a block diagram of the MATH Coprocessor.

MATH Coprocessor

PCLK

MCLK

System

Clock

Control

DIV

Kernel

Interface Block

DIV Registers

Address

Decoder

Global Registers

Interrupt

Control

Figure 18 MATH Coprocessor Block Diagram

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Watchdog Timer (WDT1)

13

Watchdog Timer (WDT1)

13.1

Features

In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way

to recover from software or hardware failures.

The WDT1 is always enabled in Active Mode. In Sleep Mode, Stop Mode and Debug Mode the WDT1 is disabled.

Functional Features

•

Watchdog Timer is operating with a from the system clock (f_SYS) independent clock source (f_{LP_CLK})

Windowed Watchdog Timer with programmable timing (16, 32, 48, …, 1008ms period) in Active Mode

Long open window (200 ms) after power-up, reset, wake-up

Short open window (30 ms) to facilitate Flash programming

System safety shutdown to Sleep Mode after 5 missed WDT1 services

Watchdog is disabled in Debug Mode

Watchdog cannot be deactivated in Normal Mode

Watchdog reset is stored in reset status register

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Watchdog Timer (WDT1)

13.2

Introduction

The behavior of the Watchdog Timer in Active Mode is depicted in Figure 19.

Power-up

Reset

RESET

always

Timeout

RESET

Trigger SOW

Maximum number

of count_SOW

Timeout

or

Trigger in closed window

RESET

Long

Open Window

Trigger&

count_SOW = 0

Trigger SOW&

count_SOW++

Normal

„windowed“

operation

Short

open window

& SOW

Trigger &

count_SOW = 0

Trigger SOW &

count_SOW++

Trigger&

count_SOW = 0

Figure 19 Watchdog Timer Behavior

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GPIO Ports and Peripheral I/O

14

GPIO Ports and Peripheral I/O

The TLE9853QX has 15 port pins organized into three parallel ports: Port 0 (P0), Port 1 (P1) and Port 2 (P2). Each

port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. P0

and P1 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate

input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can

be selected. On Port 2 (P2) analog inputs are shared with general purpose input.

14.1

Features

•

10 GPIOs and 5 analog inputs.

Strong pull-up at Reset-pin and Hall-inputs (except P2.x)

Bidirectional Port Features (P0, P1)

•

Configurable pin direction

Configurable pull-up/pull-down devices

Configurable open drain mode

Configurable drive strength

Transfer of data through digital inputs and outputs (general purpose I/O)

Possible readback of pin status when GPIO is configured as output (short detection)

Alternate input/output for on-chip peripherals

Analog Port Features (P2)

•

Configurable pull-up/pull-down devices

Transfer of data through digital inputs

Alternate inputs for on-chip peripherals

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GPIO Ports and Peripheral I/O

14.2

Introduction

14.2.1

Port 0 and Port 1

Figure 20 shows the block diagram of an TLE9853QX bidirectional port pin. Each port pin is equipped with a

number of control and data bits, thus enabling very flexible usage of the pin.

PUDSEL

Pull-up / Pull-down

Select Register

Pull-up / Pull-down

Control Logic

PUDEN

Pull-up / Pull-down

Enable Register

TCCR

Temperature Compensation

Control Register

Px_POCONy

Port Output

Driver Control Registers

I

N

OD

T

E

R

N

A

L

Open Drain

Control Register

DIR

Direction Register

ALTSEL0

Alternate Select

Register 0

B

U

S

ALTSEL1

Alternate Select

Register 1

Pull Device

AltDataOut 3

AltDataOut 2

AltDataOut 1

11

10

Output

Driver

01

00

Out

In

Data

Data Register

Input

Driver

AltDataIn

AnalogIn

Schmitt

Trigger

Pad

Port_Block_Diagram.vsd

Figure 20 General Structure of Bidirectional Port

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GPIO Ports and Peripheral I/O

14.2.2

Port 2

Figure 21 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register

P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage

level present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the

register P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device.

Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated while register P2_PUDEN

enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt-

Trigger device for direct feed-through to the ADC input channel.

PUDSEL

Pull-up / Pull-down

SelectRegister

Pull-up / Pull-down

Control Logic

I

N

T

E

R

N

A

L

PUDEN

Pull-up / Pull-down

Enable Register

Pull Device

B

U

S

Input

Driver

In

Data

Data Register

Schmitt

Trigger

Pad

AltDataIn

AnalogIn

Port_Input_Diagram.vsd

Figure 21 General Structure of Input Port

14.3

Functional Description

An overview of the available alternate functions of the GPIOs is provided in Chapter 14.3.1.

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GPIO Ports and Peripheral I/O

14.3.1

Alternate Functions

The following chapters describe the Portx.y mapping to their alternate functions.

14.3.1.1 Port 0 Functions

Port 0 alternate function mapping according Table 7

Table 7

Port Pin

P0.0

Port 0 Input/Output Functions

Input/Output

Select

GPI

Connected Signal(s)

P0_DATA.P0

T12HR_0

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

GPO

ALT1

ALT2

ALT3

GPI

CCU6

GPT12

Timer 2

SWD

T4INA

T2_0

SWD_CLK

EXINT2_3

P0_DATA.P0

T3OUT_0

EXF21_0

SCU

Output

Input

GPT12

Timer 21

UART2

UART2_RXDO

P0_DATA.P1

T13HR_0

P0.1

INP1

INP2

INP3

INP4

INP5

INP6

INP7

INP8

INP9

GPO

ALT1

ALT2

ALT3

CCU6

UART1_RXD

T2EX_1

UART1

Timer 2

Timer 21

SCU

T21_0

EXINT0_3

T4INC

GPT12

SSC1/2

CCU6

CAPINA

SSC12_S_SCK_0

CC62_0

Output

P0_DATA.P1

T6OUT_0

CC62_0

GPT12

CCU6

SSC12_M_SCK

SSC1/2

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GPIO Ports and Peripheral I/O

Table 7

Port Pin

P0.2

Port 0 Input/Output Functions (cont’d)

Input/Output

Select

GPI

Connected Signal(s)

P0_DATA.P2

T2EUDA

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

GPO

ALT1

ALT2

ALT3

GPI

GPT12

CCU6

CTRAP_0

SSC12_M_MRST_0

T21EX_0

SSC1/2

Timer 21

SCU

EXINT1_3

Output

Input

P0_DATA.P2

SSC12_S_MRST

UART1_TXD

EXF2_0

SSC1/2

UART1

Timer 2

P0.3

P0_DATA.P3

SSC1_S_SCK

T4EUDA

INP1

INP2

INP3

INP4

INP5

INP6

GPO

ALT1

ALT2

ALT3

GPI

SSC1

GPT12

SCU

CAPINB

EXINT1_2

T3EUDD

GPT12

CCU6

CCPOS0_1

P0_DATA.P3

SSC1_M_SCK

T6OFL

Output

Input

SSC1

GPT12

T6OUT_1

P0.4

P0_DATA.P4

SSC1_S_MTSR

CC60_0

INP1

INP2

INP3

INP4

INP5

INP6

GPO

ALT1

ALT2

ALT3

SSC1

CCU6

Timer 21

SCU

T21_2

EXINT2_2

T3EUDA

GPT12

CCU6

CCPOS1_1

P0_DATA.P4

SSC1_M_MTSR

CC60_0

Output

SSC1

CCU6

SCU

CLKOUT_0

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GPIO Ports and Peripheral I/O

Table 7

Port Pin

P0.5

Port 0 Input/Output Functions (cont’d)

Input/Output

Select

GPI

Connected Signal(s)

P0_DATA.P5

SSC1_M_MRST

EXINT0_0

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

GPO

ALT1

ALT2

ALT3

SSC1

SCU

T21EX_2

Timer 21

GPT12

CCU6

T5INA

CCPOS2_1

Output

P0_DATA.P5

SSC1_S_MRST

COUT60_0

SSC1

CCU6

LIN

LIN_RXD

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GPIO Ports and Peripheral I/O

14.3.1.2 Port 1 Functions

Port 1 alternate function mapping according Table 8

Table 8

Port Pin

P1.0

Port 1 Input / Output Functions

Input/Output

Select

GPI

Connected Signal(s)

P1_DATA.P0

T3INC

From/to Module

Input

INP1

INP2

INP3

INP4

GPO

ALT1

ALT2

ALT3

GPI

GPT12

CCU6

SSC2

CC61_0

SSC2_S_SCK

T4EUDB

GPT12

Output

Input

P1_DATA.P0

SSC2_M_SCK

CC61_0

SSC2

CCU6

UART2

UART2_TXD

P1_DATA.P1

T6EUDA

P1.1

INP1

INP2

INP3

INP4

INP5

INP6

GPO

ALT1

ALT2

ALT3

GPI

GPT12

SSC2

T5INB

T3EUDC

SSC2_S_MTSR

T21EX_3

Timer 21

UART2

UART2_RXD

P1_DATA.P1

SSC2_M_MTSR

COUT61_0

EXF21_1

Output

Input

SSC2

CCU6

Timer 21

P1.2

P1_DATA.P2

EXINT0_1

INP1

INP2

INP3

INP4

INP5

GPO

ALT1

ALT2

ALT3

SCU

T21_1

Timer 21

GPT12

SSC2

T2INA

SSC2_M_MRST

CCPOS2_2

P1_DATA.P2

SSC2_S_MRST

COUT63_0

T3OUT_1

CCU6

Output

SSC2

CCU6

GPT12

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GPIO Ports and Peripheral I/O

Table 8

Port Pin

P1.4

Port 1 Input / Output Functions (cont’d)

Input/Output

Select

GPI

Connected Signal(s)

P1_DATA.P4

EXINT2_1

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

INP6

GPO

ALT1

ALT2

ALT3

SCU

T21EX_1

Timer 21

GPT12

SSC1/2

CCU6

T2INB

T5EUDA

SSC12_S_MTSR_0

CCPOS1_2

Output

P1_DATA.P4

CLKOUT_1

SCU

COUT62_0

CCU6

SSC1/2

SSC12_M_MTSR

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GPIO Ports and Peripheral I/O

14.3.1.3 Port 2 Functions

Port 2 alternate function mapping according Table 9

Table 9

Port Pin

P2.0

Port 2 Input Functions

Input/Output

Select

Connected Signal(s)

P2_DATA.P0

EXINT1_1

CCPOS0_2

T5EUDB

From/to Module

Input

GPI

INP1

INP2

INP3

INP4

ANALOG

IN

SCU

CCU6

GPT12

CCU6

ADC

T13HR_2

AN0

XTAL (in)¹⁾

P2_DATA.P1

CCPOS0_0

EXINT1_0

T12HR_1

CC61_1

XTAL

P2.1

Input

GPI

INP1

INP2

INP3

INP4

INP5

INP6

INP7

INP8

ANALOG

GPI

CCU6

SCU

CCU6

GPT12

Timer2

LIN

T4EUDD

T2EX_3

LIN_TXD

SSC12_S_SCK_1

AN1

SSC1/2

ADC

P2.2

Input / Output

P2_DATA.P2

T6EUDB

INP1

INP2

INP3

INP4

ANALOG

OUT

GPT12

Timer 2

CCU6

ADC

T2EX_0

T12HR_2

CTRAP_2

AN2

XTAL (out)¹⁾

XTAL

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GPIO Ports and Peripheral I/O

Table 9

Port Pin

P2.3

Port 2 Input Functions (cont’d)

Input/Output

Select

GPI

Connected Signal(s)

P2_DATA.P3

CCPOS1_0

EXINT0_2

CTRAP_1

T3IND

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

INP6

INP7

INP8

INP9

ANALOG

GPI

CCU6

SCU

CCU6

GPT12

CCU6

GPT12

Timer2

SSC1/2

ADC

CC60_1

T2EUDB

T2_2

T2EX_2

SSC12_S_MTSR_1

AN3

P2.7

Input

P2_DATA.P7

CCPOS2_0

EXINT2_0

T13HR_1

CC62_1

INP1

INP2

INP3

INP4

INP5

INP6

INP7

INP8

ANALOG

CCU6

SCU

CCU6

GPT12

Timer2

SSC1/2

ADC

T3EUDB

T4EUDC

T2_1

SSC12_M_MRST_1

AN7

1) configurable by user

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General Purpose Timer Units (GPT12)

15

General Purpose Timer Units (GPT12)

15.1

Features

15.1.1

Features Block GPT1

The following list summarizes the supported features:

•

f_GPT/4 maximum resolution

3 independent timers/counters

Timers/counters can be concatenated

4 operating modes:

–

Timer Mode

Gated Timer Mode

Counter Mode

Incremental Interface Mode

•

Reload and Capture functionality

Shared interrupt: Node 0

15.1.2

Features Block GPT2

The following list summarizes the supported features:

•

f_GPT/2 maximum resolution

2 independent timers/counters

Timers/counters can be concatenated

3 operating modes:

–

Timer Mode

Gated Timer Mode

Counter Mode

•

Extended capture/reload functions via 16-bit capture/reload register CAPREL

Shared interrupt: Node 1

15.2

Introduction

The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures

which may be used for timing, event counting, pulse width measurement, pulse generation, frequency

multiplication, and other purposes.

They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in

each block may operate independently in a number of different modes such as Gated timer or Counter Mode,

or may be concatenated with another timer of the same block.

Each block has alternate input/output functions and specific interrupts associated with it. Input signals can

be selected from several sources by register PISEL.

The GPT module is clocked with clock f_GPT. f_GPTis a clock derived from f_SYS

.

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General Purpose Timer Units (GPT12)

15.2.1

Block Diagram GPT1

Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The

maximum resolution is f_GPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture

registers for the core timer.

T3CON.BPS1

2ⁿ: 1

Basic clock

f_GPT

InterruptRequest

(T2IRQ)

Aux. Timer T2

Core Timer T3

Aux. Timer T4

U/D

T2IN

T2

Mode

Control

Capture

Reload

T2EUD

Toggle Latch

T3

Mode

Control

T3IN

T3OTL

T3OUT

U/D

T3EUD

InterruptRequest

(T3IRQ)

Capture

Reload

T4IN

T4

Mode

Control

T4EUD

InterruptRequest

(T4IRQ)

U/D

MC _GPT0101_bldiax1.vsd

Figure 22 GPT1 Block Diagram (n = 2 … 5)

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General Purpose Timer Units (GPT12)

15.2.2

Block Diagram GPT2

Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum

resolution is f_GPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation

with extended functionality.

T6CON.BPS2

f_GPT

2ⁿ: 1

Basic clock

Toggle FF

T5

Mode

Control

U/D

Interrupt Request

(T5IR)

T5IN

GPT2 Timer T5

Clear

T5EUD

Capture

CAPIN

CAPREL

Mode

Control

GPT2 CAPREL

T3IN/

T3EUD

Interrupt Request

(CRIR)

Reload

Interrupt Request

(T6IR)

Clear

U/D

T6

Mode

Control

GPT2 Timer T6

T6OTL

T6OUT

T6OUF

T6IN

T6EUD

MC_GPT0108_bldiax4.vsd

Figure 23 GPT2 Block Diagram

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Timer2 and Timer21

16

Timer2 and Timer21

16.1

Features

•

16-bit auto-reload mode

selectable up or down counting

–

•

One channel 16-bit capture mode

Baud-rate generator for U(S)ART

16.2

Introduction

Two functionally identical timers are implemented: Timer 2 and 21. The description refers to Timer 2 only, but

applies to Timer 21 as well.

The timer modules are general purpose 16-bit timer. Timer 2 can function as a timer or counter in each of its

modes. As a timer, it counts with an input clock of f_sys/12 (if prescaler is disabled). As a counter, Timer 2 counts

1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is f_sys/24 (if prescaler

is disabled).

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Timer2 and Timer21

16.2.1

Timer2 and Timer21 Modes Overview

Table 10

Mode

Port Registers

Description

Up/Down Count Disabled

Auto-reload

•

Count up only

Start counting from 16-Bit reload value, overflow at FFFF_H

Reload event configurable for trigger by overflow condition only, or by

negative/positive edge at input pin T2EX as well

•

Programmable reload value in register RC2

Interrupt is generated with reload events.

Auto-reload

Up/Down Count Enabled

•

Count up or down, direction determined by level at input pin T2EX

No interrupt is generated

Count up

–

Start counting from 16-Bit reload value, overflow at FFFF_H

Reload event triggered by overflow condition

Programmable reload value in register RC2

•

Count down

–

Start counting from FFFF_H, underflow at value defined in register RC2

Reload event triggered by underflow condition

Reload value fixed at FFFF_H

•

Count up only

Channel capture

Start counting from 0000_H, overflow at FFFF_H

Reload event triggered by overflow condition

Reload value fixed at 0000_H

Capture event triggered by falling/rising edge at pin T2EX

Captured timer value stored in register RC2

Interrupt is generated with reload or capture event

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Capture/Compare Unit 6 (CCU6)

17

Capture/Compare Unit 6 (CCU6)

17.1

Feature Set Overview

This section gives an overview over the different building blocks and their main features.

Timer 12 Block Features

•

Three capture/compare channels, each channel can be used either as capture or as compare channel

Generation of a three-phase PWM supported (six outputs, individual signals for High Side and low-side

switches)

•

16-bit resolution, maximum count frequency = peripheral clock

Dead-time control for each channel to avoid short-circuits in the power stage

Concurrent update of T12 registers

Center-aligned and edge-aligned PWM can be generated

Single-shot mode supported

Start can be controlled by external events

Capability of counting external events

Multiple interrupt request sources

Hysteresis-like control mode

Timer 13 Block Features

•

One independent compare channel with one output

16-bit resolution, maximum count frequency = peripheral clock

Concurrent update of T13 registers

Can be synchronized to T12

Interrupt generation at period-match and compare-match

Single-shot mode supported

Start can be controlled by external events

Capability of counting external events

Additional Specific Functions

•

Block commutation for Brushless DC-drives implemented

Position detection via Hall-sensor pattern

Noise filter supported for position input signals

Automatic rotational speed measurement and commutation control for block commutation

Integrated error handling

Fast emergency stop without CPU load via external signal (CTRAP)

Control modes for multi-channel AC-drives

Output levels can be selected and adapted to the power stage

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Capture/Compare Unit 6 (CCU6)

17.2

Introduction

The CCU6 unit is made up of a Timer T12 Block with three capture/compare channels and a Timer T13 Block

with one compare channel. The T12 channels can independently generate PWM signals or accept capture

triggers, or they can jointly generate control signal patterns to drive AC-motors or inverters.

A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible

generation of interrupt request signals provide means for efficient software-control.

Note:

The capture/compare module itself is named CCU6 (capture/compare unit 6). A capture/compare

channel inside this module is named CC6x.

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Capture/Compare Unit 6 (CCU6)

17.2.1

Block Diagram

The Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be

combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). The

Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns which

can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal

modulation.

CCU6 Module Kernel

Compare

CC60

CC61

CC62

1

T12SUSP

T13SUSP

Dead-

Time

Control

Multi-

channel

Control

Debug

Suspend

Trap

Control

T12

T13

f_{CC 6}

Clock

Control

CC63

1

3

2

3

1

SR[3:0]

Interrupt

Control

Input / Output Control

Port Control

CCU6_MCB05506.vsd

P0.x

P1.x

P2.x

Figure 24 CCU6 Block Diagram

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UART1/2

18

UART1/2

18.1

Features

•

Full-duplex asynchronous modes

–

8-Bit or 9-Bit data frames, LSB first

fixed or variable baud rate

•

Receive buffered (1 Byte)

Multiprocessor communication

Interrupt generation on the completion of a data transmission or reception

Baud-rate generator with fractional divider for generating a wide range of baud rates, e.g. 9.6kBaud,

19.2kBaud, 115.2kBaud, 125kBaud, 250kBaud, 500kBaud

•

Hardware logic for break and sync byte detection

for UART1: LIN support: connected to timer channel for synchronization to LIN baud rate

In all modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is

initiated in the modes by the incoming start bit if REN = 1.

The serial interface also provides interrupt requests when transmission or reception of the frames has been

completed. The corresponding interrupt request flags are TI or RI, respectively. If the serial interrupt is not

used (i.e., serial interrupt not enabled), TI and RI can also be used for polling the serial interface.

18.2

Introduction

The UART1/2 provide a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive

simultaneously. They are also receive-buffered, i.e., they can commence reception of a second byte before a

previously received byte has been read from the receive register. However, if the first byte still has not been

read by the time reception of the second byte is complete, the previous byte will be lost. The serial port receive

and transmit registers are both accessed at Special Function Register (SFR) SBUF. Writing to SBUF loads the

transmit register, and reading SBUF accesses a physically separate receive register.

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UART1/2

18.2.1

Block Diagram

UART disreq from SCU_DM

RI

TXD

RXD

TXD

SCU_D

M

Interrupt

Control

RXD_0

RXD_1

TI

URIOS

SCU_DM

P0.x

P1.x

P2.x

UART

Module

(Kernel)

PortControl

f_UART2

Clock

Control

Baud Rate

Generator

f

BR

Address

Decoder

RXDO _2

SCU_DM

AHB Interface

SSC Module

GPIOs

Figure 25 UART Block Diagram

18.3

UART Modes

The UART1/2 can be used in four different modes. In mode 0, it operates as an 8-Bit shift register. In mode 1, it

operates as an 8-Bit serial port. In modes 2 and 3, it operates as a 9-Bit serial port. The only difference between

mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is

set by the underflow rate on the dedicated baud-rate generator.

The different modes are selected by setting bits SM0 and SM1 to their corresponding values, as shown in

Table 11.

Mode 1 example: 8 data bits, 1 start bit, 1 stop bit, no parity selection, 16 times oversampled, receive &

transmit register double buffered, Tx/Rx IRQ(s).

Table 11

UART Modes

SM1

SM0

Operating Mode

Mode 0: 8-Bit shift register

Baud Rate

0

1

0

1

0

1

f

_sys/2

Variable

_sys/64 or f_sys/32

Variable

Mode 1: 8-Bit shift UART

Mode 2: 9-Bit shift UART

Mode 3: 9-Bit shift UART

f

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LIN Transceiver

19

LIN Transceiver

19.1

Features

General Functional Features

•

Compliant to LIN2.2 Standard, backward compatible to LIN1.3, LIN2.0 and LIN 2.1

Compliant to SAE J2602 (Slew Rate, Receiver hysteresis)

Special Features

•

Measurement of LIN Master baudrate via Timer 2

LIN can be used as Input/Output with SFR bits.

TxD Timeout Feature (optional, on by default)

Overcurrent limitation and overtemperature protection

LIN module fully resettable via global enable bit

Operation Modes Features

•

LIN Sleep Mode (LSLM)

LIN Receive-Only Mode (LROM)

LIN Normal Mode (LNM)

High Voltage Input / Output Mode (LHVIO)

Slope Modes Features

•

Normal Slope Mode (20 kbit/s)

Low Slope Mode (10.4 kbit/s)

Fast Slope Mode (62.5 kbit/s)

Flash Mode (115 kbit/s, 250 kbit/s)

Wake-Up Features

LIN Bus wake-up

•

19.2

Introduction

The LIN Module is a transceiver for the Local Interconnect Network (LIN) compliant to the LIN2.2 Standard,

backward compatible to LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller

and the physical network. The LIN bus is a single wire, bi-directional bus typically used for in-vehicle networks,

using baud rates between 2.4 kBaud and 20 kBaud. Additionally baud rates up to 62.5 kBaud are

implemented.

The LIN Module offers several different operation modes, including a LIN Sleep Mode and the LIN Normal

Mode. The integrated slope control allows to use several data transmission rates with optimized EMC

performance. For data transfer at the end of line, a Flash Mode up to 115 kBaud is implemented. This Flash

Mode can be used for data transfer under special conditions for up to 250 kbit/s (in production environment,

point-to-point communication with reduced wire length and limited supply voltage).

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LIN Transceiver

19.2.1

Block Diagram

VS

LIN Transceiver

30 k

LIN_CTRL_STS

LIN-FSM

LIN

CTRL

Driver +

Curr. Limit. +

TSD

TxD_1

from UART

STATUS

GND_LIN

Transmitter

PMU_LIN_WAKE_EN.LIN_EN

Filter

RxD_1

to UART

Filter

Receiver

LIN_Wake

Sleep Comparator

LIN_Block_Diagram_Customer.vsd

GND_LIN

Figure 26 LIN Transceiver Block Diagram

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High-Speed Synchronous Serial Interface SSC1/2

20

High-Speed Synchronous Serial Interface SSC1/2

Features

20.1

•

Master and Slave Mode operation

–

Full-duplex or half-duplex operation

•

Transmit and receive double buffered

Flexible data format

–

Programmable number of data bits: 2 to 16 bits

Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit (MSB) shift first

Programmable clock polarity: idle low or high state for the shift clock

Programmable clock/data phase: data shift with leading or trailing edge of the shift clock

•

Variable baud rate, e.g. 250kBaud - 8MBaud

Compatible with Serial Peripheral Interface (SPI)

Interrupt generation

–

On a transmitter empty condition

On a receiver full condition

On an error condition (receive, phase, baud rate, transmit error)

On a transfer complete condition

•

Port direction selection, see Chapter 14

20.2

Introduction

The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial

synchronous communication. The serial clock signal can be generated by the SSC internally (master mode),

using its own 16-Bit baud-rate generator, or can be received from an external master (slave mode). Data width,

shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible

devices or devices using other synchronous serial interfaces.

Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR

(MasterTransmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line

MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally

connected to the pin SCLK. Transmission and reception of data are double-buffered.

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High-Speed Synchronous Serial Interface SSC1/2

20.2.1

Block Diagram

Figure 27 shows all functional relevant interfaces associated with the SSC Kernel.

MRSTA

MRSTB

EIR

MTSR

SCU_DM

Interrupt

Control

RIR

TIR

MTSRA

MTSRB

P0.x

P1.x

P2.x

SSC

Port

Control

Module

(Kernel)

MRST

f_{hw_clk}

Clock

Control

SCLKA

SCLKB

Address

Decoder

SCLK

AHB Interface

Module

ProductInterface

SSC_interface_overview.vsd

Figure 27 SSC Interface Diagram

Datasheet

69

Rev. 1.0

2019-07-26

TLE9853QX

Measurement Unit

21

Measurement Unit

21.1

Features

•

1 x 10-bit ADC with 12 inputs

Supply Voltage Attenuators with attenuation of VBAT_SENSE, VS, MONx, P2.x, CSA.

1 x 8-bit ADC with 9 inputs

Supply Voltage Attenuators with attenuation of VS, VDDEXT, VSD, VCP, VDDP, VBG, VDDC, T_SENSE1

(Central Temperature Sensor), T_SENSE2 (Bridge Driver Charge Pump Temperature Sensor).

•

Monitoring of PMU bandgap by 8-bit ADC to support functional safety requirements.

Temperature Sensor to monitor the chip temperature and Bridge Driver Charge Pump temperature.

Supplement Block with Reference Voltage Generation, Bias Current Generation, Voltage Buffer for NVM

Reference Voltage, Voltage Buffer for Analog Module Reference Voltage and Test Interface.

21.2

Introduction

The measurement unit is a functional unit that comprises the following associated sub-modules:

Table 12

Measurement functions and associated modules

Module

Name

Modules

Functions

CentralFunctions Bandgap reference circuit +

Unit current reference circuit

The bandgap-reference sub-module provides two

reference voltages

1. an accurate reference voltage for the 10-bit and 8-

bit ADCs. A local dedicated bandgap circuit is

implemented to avoid deterioration of the reference

voltage caused e.g. by crosstalk or ground voltage

shift.

2. the reference voltage for the NVM module

10-bit ADC (ADC1) 10-bit ADC module with 12

multiplexed analog inputs

VBAT_SENSE, VS and MONx measurement.

Five (5V) analog inputs from Port 2.x

8-bit ADC (ADC2) 8-bit ADC module with 9

multiplexed inputs

VS/VDDEXT/VSD/VCP/VDDP/VBG/VDDC/BDrv CP

Temperature Sensor and Central Temperature

Sensor measurement.

Temperature

Sensor

Temperature sensor readout

amplifier with two multiplexed

ΔV_be-sensing elements

Generates output voltage which is a linear function of

the local chip (Tj) temperature.

Measurement

Core Module

Digital signal processing and ADC 1. Generates the control signal for the 8-bit ADC 2 and

control unit

the synchronous clock for the switched capacitor

circuits (temperature sensor)

2. Performs digital signal processing functions and

provides status outputs for interrupt generation.

Datasheet

70

Rev. 1.0

2019-07-26

TLE9853QX

Measurement Unit

21.2.1

Block Diagram

The Structure of the Measurement Functions Module is shown in the following figure.

VS

VDDC

ATT

ATT_{VBAT_SENSE}

ATT_VS

VBAT_SENSE

CH0

CH1

ATT_VMONx

CH2

CH3

CH4

CH5

CH6

MON1

MON2

MON3

MON4

P2.0

ATT_VMONx

ATT_2.x

V_BG

DPP1

VREF

ADC 1

MUX

P2.1

P2.2

P2.3

ATT_2.x

CH7

CH8

CH9

10

/

SFR

A

D

ATT_2.x

CH10

CH11

CH12

CH13

rfu

ATT_2.x

P2.7

OP1

OP2

OPA

ATT_OPA

10 Bit ADC + DPP

ATT

ATT_{VS_ADC2}

CH0

CH1

V_BG

ATT_{VSD_ADC2}

ATT_{VCP_ADC2}

ATT_VDDEXT

ATT_VDDP

VSD

VCP

CH2

CH3

CH4

CH5

CH6

CH7

CH8

DPP2

VDDEXT

VDDP

8

/

MUX

SFR

A

D

PMU VBG

ATT_PMUVBG

ATT_VDDC

ATT_VTEMP

VDDC

ADC 2

BDrv CP TS

Central TS

8 Bit ADC + DPP

Measurement-Unit – TLE985x

Measurement_Unit_Overview_Cus_TLE985x_2.vsd

Figure 28

Measurement Unit-Overview

Datasheet

71

Rev. 1.0

2019-07-26

TLE9853QX

Measurement Core Module (incl. ADC2)

22

Measurement Core Module (incl. ADC2)

22.1

Features

•

9 individually programmable channels split into two groups of user configurable and non user

configurable

•

Individually programmable channel prioritization scheme for measurement unit

Two independent filter stages with programmable low-pass and time filter characteristics for each

channel

•

Two channel configurations:

–

Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis

Two individually programmable trigger thresholds with limit hysteresis settings

•

Status for all channel thresholds

Operation down to reset threshold of entire system

22.2

Introduction

The basic function of this block is the digital postprocessing of several analog digitized measurement signals

by means of filtering, level comparison and interrupt generation. The measurement postprocessing block is

built of nine identical channel units attached to the outputs of the 9-channels 8-bit ADC (ADC2). It processes

nine channels, where the channel sequence and prioritization is programmable within a wide range.

Datasheet

72

Rev. 1.0

2019-07-26

TLE9853QX

Measurement Core Module (incl. ADC2)

22.2.1

Block Diagram

4

/

MUX_SEL<3:0>

Channel Controller

(Sequencer)

ADC2 - SFR

CH0

VSD

CH1

1st Order IIR

1

/

VCP

VDDEXT

CH2

+

-

8 Bit ADC

VREF

UP_X_STS

+ / -

THy_z_UPPER.

CHx

Calibration Unit:

y= a + (1+b)*x

CH3

8

/

10

/

8

/

VDDP

CH4 MUX

CH5

A

D

1

/

THy_z_LOWER.

CHx

PMU-VBG

-

LOW_X_STS

+

VDDC

CH6

BDrv CP Temp. Sens.

Central Temp. Sens.

CH7

Digital Signal Processing

CH8

TSENSE

Measurement Core Module

Figure 29 Module Block Diagram

Datasheet

73

Rev. 1.0

2019-07-26

TLE9853QX

Analog Digital Converter ADC10B (ADC1)

23

Analog Digital Converter ADC10B (ADC1)

23.1

Features

The basic function of this block is the digital postprocessing of several analog digitized measurement signals

by means of filtering, level comparison and interrupt generation. The measurement postprocessing block is

built of the same number of identical channel units attached to the outputs of the 10-bit ADC. It processes

allchannels, where the channel sequence and prioritization is programmable within a wide range.

Functional Features

•

10 Bit SAR ADC with conversion time of 17 clock cycles

programmable clock divider for sequencer and ADC

12 individually programmable channels:

–

6 HV Channels: VS, VBAT_SENSE, MON1...MON4

5 LV Channels: P2.0, P2.1, P2.2, P2.3, P2.7

1 Current-Sense Amplifier Channel

•

all channels are fully calibrated; calibration can be enabled/disabled by user

individually programmable channel prioritization scheme for digital postprocessing (dpp)

two independent filter stages with programmable low-pass and time filter characteristics for each channel

two channel configurations:

–

programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis

two individually programmable trigger thresholds with limit hysteresis settings

•

individually programmable upper threshold and lower threshold interrupts and status for all channel

thresholds

•

one additional differential channel (MON1-MON2) with postprocessing and interrupt generation

ADC voltage reference completely integrated

Note:

In case the MONx should be evaluated by the ADC1, it is recommended to add 6.8nF capacitors close

to the MONx pin of the device, in order to build an external RC filter to limit the bandwidth of the input

signal.

Datasheet

74

Rev. 1.0

2019-07-26

TLE9853QX

Analog Digital Converter ADC10B (ADC1)

23.2

Introduction

23.2.1

Block Diagram

5

/

MUX_SEL<4:0>

Channel Controller

(Sequencer)

SOS à EOC

ADC - SFR

ADC1_PP_MAPxxx

ADC1_THxxx

ADC1_CNTxxx

ADC1_CTRL_STS

ADC1_CTRL2

ADC1_CTRL5

VBAT_SENSE

CH 0

CH 1

CH 2

CH 3

VS

MON1

MON2

MON3

MON4

P2.0

P2.1

P2.2

P2.3

rfu

12

/

FILT_OUT_CHx

1st Order IIR

PP_CHx_UP

CH 4

CH 5

1

/

+

-

10 Bit ADC

VREF

PP_CHx_UP_STS

PP_CHx_LO_STS

+ / -

CH 6

Calibration Unit:

MUX

10

/

12

/

CH 7

A

D

/

8

y= a + (1+b)*x

MUX

CH 8

1

/

-

CH 9

+

CH 10

CH 11

CH 12

CH 13

rfu

PP_CHx_LOW

Digital Signal Processing

P2.7

OPA

Figure 30 Module Block Diagram

Datasheet

75

Rev. 1.0

2019-07-26

TLE9853QX

High-Voltage Monitor Input

24

High-Voltage Monitor Input

24.1

Features

•

Four High-voltage inputs with VS/2 threshold voltage

Wake capability for system stop mode and system sleep mode

Edge sensitive wake-up feature configurable for transitions from low to high, high to low or both directions

MON inputs can also be evaluated with ADC in Active Mode, using adjustable threshold values

Selectable pull-up and pull-down current sources available

24.2

Introduction

This module is dedicated to monitor external voltage levels above or below a specified threshold. Each MONx

pin can further be used to detect a wake-up event by detecting a level change by crossing the selected

threshold. This applies to any power mode. Further more each MONx pin can be sampled by the ADC as analog

input.

24.2.1

Block Diagram

VS

MON

+

-

Filter

to internal

circuitry

MON

Logic

SFR

MONx_Input_Circuit_ext.vsd

Figure 31 Monitoring Input Block Diagram

Datasheet

76

Rev. 1.0

2019-07-26

TLE9853QX

High-Side Switch

25

High-Side Switch

25.1

Features

The high-side switch is optimized for driving resistive loads. Only small line inductances are allowed. Typical

applications are single or multiple LEDs of a dashboard, switch illumination or other loads that require a high-

side switch.

A cyclic switch activation during Sleep Mode or Stop Mode of the system is also available.

Functional Features

•

Multi purpose high-side switch for resistive load connections (only small line inductances are allowed)

Overcurrent limitation

Selectable current capability (25 mA/50 mA/100 mA/150 mA) by adjustable overcurrent detection with

automatic shutdown

•

Overtemperature detection and automatic shutdown

Open load detection in on mode with open load current of typ. 1.4 mA

Interrupt signalling of overcurrent, overtemperature and open load condition

Cyclic switch activation in Sleep Mode and Stop Mode with cyclic sense support and reduced driver

capability: max. 40 mA

•

PWM capability up to 25 kHz

Internal connection to System-PWM Generator (CCU6)

Slew rate control for low EMI characteristic

Applications hints

•

The voltage at HSx must not exceed the supply voltage by more than 0.3V to prevent a reverse current from

HSx to VS.

Datasheet

77

Rev. 1.0

2019-07-26

TLE9853QX

High-Side Switch

25.2

Introduction

25.2.1

Block Diagram

VS

25 mA

50 mA

100 mA

150 mA

OC_SEL

OC-Detection

Cyclic-

Driver

SFR

ON

Driver

HS

OL-Detection

High Side

Figure 32 High-Side Module Block Diagram (incl. subblocks)

25.2.2

General

The high-side switch can generally be controlled in three different ways:

•

In normal mode the output stage is fully controllable through the SFR Registers HSx_CTRL. Protection

functions as overcurrent, overtemperature and open load detection are available.

•

The PWM Mode can also be enabled by a HSx_CTRL - SFR bit. The PWM configuration has to be done in the

corresponding PWM Module. All protection functions are also available in this mode. The maximum PWM

frequency must not exceed 25 kHz (disabled slew rate control only).

•

The high-side switch provides also the possibility of cyclic switch activation in all low power modes (Sleep

Mode and Stop Mode). In this configuration it has limited functionality with limited current capability.

Diagnostic functions are not available in this mode.

Datasheet

78

Rev. 1.0

2019-07-26

TLE9853QX

Bridge Driver (incl. Charge Pump)

26

Bridge Driver (incl. Charge Pump)

26.1

Features

The Bridge Driver is intended to drive external normal-level MOSFETs in bridge configuration and provides

many diagnostic possibilities to detect faults.

Functional Features

•

Flexible control by SFRs of Bridge Driver module or PWM output signals of CCU6 module

Current-driven output stages to control external n-channel MOSFET gates with flexibly programmable

gate current profile

•

Adjustable cross-conduction protection

High-current discharge mode to reduce dead times and to keep external MOSFETs off during fast

transients

•

Passive pull-down mode to keep external MOSFETs off if the Bridge Driver is disabled

Brake mode with reduced current consumption to statically switch on external MOSFETs

Hold mode with low current consumption to switch on external low-side MOSFETs if the Bridge Driver is

disabled

•

Timing measurements of on/off delays and on/off slope durations

Adaptive control mode with automatic adjustment of gate current values

Integrated 2-stage charge pump for low-voltage operation and statical MOSFET gate control

Adjustable voltage monitoring of Bridge Driver supply voltage (VSD) and charge pump output voltage

(VCP)

•

Adjustable short-circuit detection in on and off state

Open-load detection in off state

Overtemperature detection and shutdown

Datasheet

79

Rev. 1.0

2019-07-26

TLE9853QX

Bridge Driver (incl. Charge Pump)

26.2

Introduction

26.2.1

Block Diagram

VDH VCP

CP1H CP1L CP2H CP2L

PWM-Unit

CCU6

(not part of the module)

2-Stage

Charge Pump

VSD

Pre-Driver

BDRV_TRIM_DRVx.

HSDRV_DS_TFILT_SEL LS_HS_BT_TFILT_SEL

BDRV_TRIM_DRVx.

BDRV_CTRL3.

DSMONVTH

+

Spike

Filter

Blank

Filter

VDS

High Side

Driver

-

GHx

1

0

R_{GG ND}

V_{DSMO NVTH}

BDRV_CTRL1.HSx_PWM

SFR

SHx

GLx

1

0

Low Side

Driver

BDRV_CTRL1.LSx_PWM

+

Spike

Filter

Blank

Filter

VDS

R_{GG ND}

-

V_{DSMO NVTH}

BDRV_TRIM_DRVx.

LSDRV_DS_TFILT_SEL LS_HS_BT_TFILT_SEL

BDRV_TRIM_DRVx.

BDRV_CTRL3.

DSMONVTH

SL

Figure 33 Driver Module Block Diagram (incl. System Connections)

26.2.2

Flexible Control

Each gate driver of the Bridge Driver module can be switched on and off in two different ways:

•

Static Mode: The gate drivers are statically switched on or off by the Bridge Driver module SFRs.

PWM Mode: The gate drivers are PWM-controlled by the System PWM Module (CCU6). The interconnection

from the CCU6 output channels to the gate drivers is set up by the Bridge Driver module SFRs.

In both modes all diagnostic and protection functions (short-circuit, open-load, and overtemperature

detection) are available.

Datasheet

80

Rev. 1.0

2019-07-26

TLE9853QX

Bridge Driver (incl. Charge Pump)

26.2.3

Current-Driven Output Stages

The Bridge Driver output stages generate source and sink currents to charge and discharge the gates of the

external n-channel MOSFETs. The gate current values are programmable to vary the slew rate at the bridge

output.

26.2.3.1 Overview

Figure 34 shows an overview of one switching cylce of an external MOSFET.

Control

Signal

OFF

ON

OFF

ON

I

Gate

Current

*)

I_gate

t

V_DS

V

External

MOSFET

Voltages

V_GS

t

Pre-Charge

Post-Charge

Pre-Discharge

Post-Discharge

On Slope

Off Slope

Off

On

Off

^*)positive current flowing out of Gx pin

Figure 34 Switching cycle

The control input signal sets the gate driver either in charge or discharge mode, i.e. it generates a source

current flowing out of the driver to charge the gate of an external MOSFET or a sink current flowing into the

driver to discharge the gate of an external MOSFET.

Based on the changes on the drain-to-source voltage of the external MOSFET the charging and discharging

phases can each be divided into three subphases.

Subphases of the charging phase:

•

pre-charge subphase: the gate of the external MOSFET is pre-charged without change on V_DS; the external

MOSFET is still off

•

on slope subphase: the gate of the external MOSFET is further charged while the external MOSFET turns on

and generates the on slope at V_DS

Datasheet

81

Rev. 1.0

2019-07-26

TLE9853QX

Bridge Driver (incl. Charge Pump)

•

post-charge subphase: the gate of the external MOSFET is post-charged until the maximum V_GSthe gate

driver is able to provide; the external MOSFET is on and its R_DS(on)decreases to its minimum value

Subphases of the discharging phase:

•

pre-discharge subphase: the gate of the external MOSFET is pre-discharged without significant change on

_DS; the external MOSFET is still on, but its R_DS(on)increases

V

off slope subphase: the gate of the external MOSFET is further discharged while the external MOSFET turns

off and generates the off slope at V_DS

post-discharge subphase: the gate of the external MOSFET is post-charged until V_GSis equal to 0V; the

external MOSFET is off and is kept off

26.2.3.2 Switch-On

Figure 35 shows the detailed behavior of the gate driver output stage in the switch-on phase and the

corresponding electrical characteristic parameters.

Control

Signal

OFF

ON

SR_{on_SHx}= 0

SR_{on_SHx}≠ 0, V_GS<V_GS(on)

t_dly(on)

I_chgx

t_rise(on)

I

max.

typ.

Gate

Charge

Current

ΔI_{chg_avg_%}

*)

min.

I_gate

20%

t

V

V_DS

max.

V_Gxxy

min.

V_GS=V_GS(on)

External

MOSFET

Voltages

t_sat(on)

V_GS

t

Pre-Charge

Post-Charge

On Slope

Off

On

^*)positive current flowing out of Gx pin

Figure 35 Detailed behavior of the gate driver output stage in the switch-on phase

After an initial turn-on delay time t_dly(on)the gate charge current I_gaterises and after additional t_rise(on)reaches

its specified minimum limit I_chgx,minand stays stable until the gate-to-source voltage of the external MOSFET

reaches V_GS= V_GS(on). During the slope at the corresponding SHx pin (i.e. SR_{on_SHx}≠ 0) the average gate current

deviates less than ΔI_{chg_avg_%}from the original set point I_chgx. The gate of the external MOSFET is further

charged to the high-level output voltage of the gate driver V_Gxxy. The time from exceeding V_GS= V_GS(on)and

reaching V_Gxxy,minis defined by t_sat(on)

.

Datasheet

82

Rev. 1.0

2019-07-26

TLE9853QX

Bridge Driver (incl. Charge Pump)

26.2.3.3 Switch-Off

Figure 36 shows the detailed behavior of the gate driver output stage in the switch-off phase and the

corresponding electrical characteristic parameters.

Control

Signal

ON

OFF

SR_{off_SHx}= 0

SR_{off_SHx}≠ 0, V_GS>V_GS(off)

t_dly(off)

I_dischgx

t_rise(off)

I

Gate

Discharge

Current

max.

typ.

ΔI_{dischg_avg_%}

*)

min.

I_gate

20%

t

V

External

MOSFET

Voltages

V_DS

V_GS

V_GS=V_GS(off)

t

Pre-Discharge

Post-Discharge

Off Slope

On

Off

^*)positive current flowing into Gx pin

Figure 36 Detailed behavior of the gate driver output stage in the switch-off phase

After an initial turn-off delay time t_dly(off)the gate discharge current I_gaterises and reaches its specified

minimum limit I_dischgx,minafter t_rise(off)and stays stable until the gate-to-source voltage of the external MOSFET

reaches V_GS= V_GS(off). During the slope at the corresponding SHx pin (i.e. SR_{off_SHx}≠ 0) the average gate discharge

current deviates less than ΔI_{dischg_avg_%}from the original set point I_dischgx

.

26.2.3.4 Control Modes

There are two basic modes to program the gate current set point values of the output stages: constant mode

and sequencer mode.

•

In constant mode a simple gate current profile is defined by SFRs where the gate charging phase and the

gate discharging phase each have two current set point values and one duration value. The second current

set point value remains valid until the driver changes from charge mode to discharge mode or vice versa

and is intended to statically keep on or off the external MOSFET at a reduced gate current level to be robust

against external shorts at the gate pin.

Datasheet

83

Rev. 1.0

2019-07-26

TLE9853QX

Bridge Driver (incl. Charge Pump)

•

In sequencer mode an advanced gate current profile is defined by SFRs where the gate charging phase and

the gate discharging phase each are split into consecutive sub phases with individual current set point

values and duration values (see Figure 37):

–

For the gate charging phase 5 current set point values (i_x(on)) and 4 duration values (t_x(on)) are defined by

SFRs.

–

The fifth current setpoint value I_5(on)remains valid until the driver changes to discharge mode. This

charge current is intended to statically keep on the external MOSFET (e.g. driving an external R_GS) at a

reduced gate current level to be robust against external gate-to-source shorts.

–

For the gate discharging phase 5 current set point values (i_x(off)) and 4 duration values (t_x(off)) are defined

by SFRs.

The fifth current setpoint value I_5(off)remains valid until the driver changes to charge mode. This

discharge current is intended to statically keep off the external MOSFET (e.g. during fast voltage

transients or EMI) at a reduced gate current level to be robust against external gate-to-drain shorts.

–

At the transition between two gate current set points the actual gate driver output current settles

within t_set(seq)to the new gate current set point (see Figure 38).

Control

Signal

OFF

ON

OFF

ON

t_1(on)

t_2(on)

t_3(on)

i_4(on)

t_4(on)

I

i_1(on)

Gate

Current

*)

i_3(on)

i_2(on)

i_5(on)

i_5(off)

t

i_3(off)

i_2(off)

i_1(off)

i_4(off)

t_(3)off

t_(1)off

t_(2)off

t_(4)off

V_DS

V

External

MOSFET

Voltages

V_GS

t

Pre-Charge Slope

Post-Charge

Pre-Discharge

Slope Post-Discharge

^*)positive current flowing out of Gx pin

Figure 37 Gate current set point values generated by the sequencer

Datasheet

84

Rev. 1.0

2019-07-26

TLE9853QX

Bridge Driver (incl. Charge Pump)

Gate Current

i_n-1

i_n

i_n+1

Set Point

t_n-1

t_n

t_n+1

Gate Current

Duration

t_set(seq)

I

max.

i_n

typ.

Gate Current

min.

Profile

I_gate

max.

i_n-1

typ.

min.

max.

typ.

i_n+1

t_set(seq)

min.

t

Figure 38 Gate current settling time

26.2.4

Adjustable Cross-Conduction Protection

The Bridge Driver protects half bridges of external MOSFETs against cross conduction. After switching off one

of the MOSFETs of a half bridge the complementary MOSFET cannot be switched on for an optionally

programmable time defined by SFRs.

26.2.5

High-Current Discharge Mode

The high-current discharge mode provides a low-ohmic path between the Gx and Sx pins to do a fast discharge

of the external MOSFET gate and keep the external MOSFET off during fast voltage transients at its drain or

source terminals.

The high-current discharge mode is activated in the following situations:

•

in the case of an emergency shutdown after detection of an error condition,

if the complementary external MOSFET is switched on to avoid cross conduction in the external half bridge.

If the adjustable cross-conduction protection feature is enabled the high-current discharge mode is delayed

and activated at the same time than the switch-on control signal of the complementary MOSFET.

26.2.6

Passive Pull-Down Mode

If the Bridge Driver module is disabled the passive pull-down mode activates resistors R_GGNDbetween the Gx

pins and ground to passively keep discharged the gates of the external MOSFETs. During normal operation

these pull-down resistors are switched off.

Datasheet

85

Rev. 1.0

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TLE9853QX

Bridge Driver (incl. Charge Pump)

26.2.7

Brake Mode

In Brake Mode either both external high-side MOSFETs or both external low-side MOSFETs are statically

switched on to short circuit the motor coil to brake the motor or keep it actively blocked during standstill.

Since in brake mode no PWM capability is needed the charge pump is set into low-power mode to reduce the

current consumption I_{VSD_BK}from the VSD pin.

26.2.8

Hold Mode

In Hold Mode the external low-side MOSFETs can be switched to an auxiliary gate voltage V_{Gxx_HM}to terminate

the motor pins in all cases where the Bridge Driver and its charge pump is disabled (including stop mode and

sleep mode where the Bridge Driver is disabled by default). This leads to low current consumption I_{VSD_SMHM}

and I_{VSD_STPMHM}from the VSD pin. The Hold Mode is configured by SFRs in the Power Management Unit where

the behavior during stop or sleep mode is defined. The configuration includes the channel-individual

selection between static and cyclic activation of the Hold mode and programmable timing.

Note:

In Hold Mode the monitoring and protection of the Bridge Driver is not available.

26.2.9

Timing Measurements

The Bridge Driver provides fast comparators with low propagation delay t_cdlyat the SHx pins to measure on

and off delays t_sdly(on)and t_sdly(off)between changes on the control signals and the corresponding slopes at the

SHx pins. Additionally, these comparators are able to measure the on and off slope durations t_sdur(on)and

t_sdur(off)at the SHx pins. The measured values are stored in SFRs for further evaluation by software or by the

adaptive control mode (see Chapter 26.2.10).

Figure 39 shows the thresholds V_SH(high)and V_SH(low)and propagation delay t_cdlyof the fast comparators and the

measured slope timing parameters t_sdly(on), t_sdur(on), t_sdly(off), and t_sdur(off)during PWM actuation of the external

low-side MOSFET.

Low-Side

Control

Signal

OFF

ON

OFF

ON

V

V_VDH

V_SH(high)

Half-Bridge

Voltages

V_SHx

V_SH(low)

t

t_cdly

SH_high

SH_low

Comparator

Output

Signals

t_cdly

t_sdur(on)

t_cdly

t_sdly(off)

t_sdly(on)

t_sdur(off)

Figure 39 Comparator thresholds and timing parameters during low-side PWM

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Bridge Driver (incl. Charge Pump)

Figure 40 shows the thresholds V_SH(high)and V_SH(low)and propagation delay t_cdlyof the fast comparators and the

measured slope timing parameters t_sdly(on), t_sdur(on), t_sdly(off), and t_sdur(off)during PWM actuation of the external

high-side MOSFET.

High-Side

Control

Signal

OFF

ON

OFF

ON

V

V_VDH

V_SH(high)

Half-Bridge

Voltages

V_SHx

V_SH(low)

t

t_cdly

SH_high

SH_low

Comparator

Output

Signals

t_cdly

t_sdly(on)

t_cdly

t_sdly(off)

t_sdur(on)

t_sdur(off)

Figure 40 Comparator thresholds and timing parameters during high-side PWM

For plausibility checks of the fast comparators and the assigned timing measurement counters there is an

additional channel on/off delay measurement counter which can be switched to each channel’s control

signals and the corresponding drain-to-source voltage monitoring comparator outputs.

26.2.10 Adaptive Control Mode

The Bridge Driver provides an optional adaptive control mode if the output stages are controlled by the

sequencer mode. The target values for on and off delays are defined by SFRs. In order to reach these target

values, the adaptive control algorithm reads the results from the timing measurement and adjusts the current

set point of the first gate charging sub phase i_1(on)and the first gate discharging sub phase i_1(off)accordingly.

26.2.11 Integrated 2-Stage Charge Pump

The Bridge Driver is supplied by an integrated 2-stage charge pump which provides a stable voltage V_CPabove

the battery voltage. This enables the Bridge Driver to operate down to low battery voltage values and to

statically switch on the external MOSFETs.

The charge pump output voltage is programmable by SFRs. The charge pump frequency is continously varied

between two boundary frequencies defined by SFRs.

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Bridge Driver (incl. Charge Pump)

26.2.12 Adjustable Voltage Monitoring

The supply voltages of the Bridge Driver (VSD and VCP) are monitored by the Measurement Unit. The Bridge

Driver including the charge pump can be optionally disabled at undervoltage or overvoltage of the monitored

signals.

26.2.13 Adjustable Short Circuit Detection

For short circuit detection the drain-to-source comparators of the Bridge Driver are used to compare the

voltage drops across the external MOSFETs to the programmable threshold voltage V_DSMONVTH. During

transitions from off to on and vice versa the comparator output signals are ignored for a programmable blank

time defined by SFRs.

In on state the external MOSFETs are switched off automatically if a stable short-circuit condition is detected

for a SFR programmable filter time and an interrupt is generated. It can be selected by SFR if all MOSFETs are

switched off or only the one where the short-circuit condition was detected.

In off state the motor phases can be pulled up or pulled down by the diagnostic currents I_PUDiagand I_PDDiag. The

drain-to-source comparator output signals can be read by SFRs to check if the motor phase voltages change

according to the activated diagnostic currents.

26.2.14 Open-Load Detection

For open-load detection in off state the pull-up diagnostic current I_PUDiagof one half bridge and the pull-down

diagnostic current I_PDDiagof the other half bridge are activated. The pull-down diagnostic current I_PDDiagis able

to overdrive the pull-up diagnostic current I_PUDiag(by I_{PDDiag_OD}). Therefore, in the case of a connected motor,

both motor phase voltages are pulled-down. In the case of an disconnected motor, one motor phase voltage

is pulled down while the other is pulled up according to the diagnostic current settings. The reaction of the

motor phase voltages can be checked by the drain-to-source comparators of the Bridge Driver and their

corresponding SFR status bits.

26.2.15 Overtemperature

The temperature of the Bridge Driver Charge Pump is monitored by a dedicated temperature sensor of the

Measurement Unit for temperature warning signalling and overtemperature shutdown of the Bridge Driver.

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TLE9853QX

Current Sense Amplifier

27

Current Sense Amplifier

27.1

Features

Main Features

•

Programmable gain settings: G = 10, 20, 40, 60

Differential input voltage: ± 1.5V / G

Wide common mode input range ± 2 V

Low settling time < 1.4 µs

27.2

Introduction

The current sense amplifier in Figure 41 can be used to measure near ground differential voltages via the 10-

bit ADC. Its gain is digitally programmable through internal control registers.

Linear calibration has to be applied to achieve high gain accuracy, e.g. end-of-line calibration including the

shunt resistor.

Figure 41 shows how the current sense amplifier can be used as a low-side current sense amplifier where the

motor current is converted to a voltage by means of a shunt resistor R_SH. A differential amplifier input is used

in order to eliminate measurement errors due to voltage drop across the stray resistance R_Strayand differences

between the external and internal ground. If the voltage at one or both inputs is out of the operating range it

has to be taken into account that the input circuit is overloaded and needs a certain specified recovery time.

In general, the external low pass filter should provide suppression of EMI.

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Current Sense Amplifier

27.2.1

Block Diagram

V_BAT

M

V

_ZERO– Generation:

_BG* 1.652

V

_BG=1,211V

V_{ZE RO}= V

Motor

Current

Amplifier

configurable

LP Filter

R_OPAFILT

OP2

OP1

Gain: 10, 20, 40, 60

VP

V_zero+ (V_OP2-V_OP1) * G

10

/

* 0,273 10-bit ADC

ADC1_OUT_CH13

C_OPAFILT

R_OPAFILT

R_SH

VN

CSA_CTRL

R_Stray

Ext. GND

Current_Sense_Amplifier.vsd

Figure 41 Simplified Application Diagram

V_BAT

M

V

_ZERO– Generation:

V_ZERO

V_ZERO= V_BG* 1.652

V_BG= 1.211V

Amplifier

configurable

PP_CHx_UP

Motor

Current

LP Filter

R_OPAFILT

Gain: 10, 20, 40, 60

1

OP2

OP1

+

UP_X_STS

+ / -

/

VP

-

10

/

8

/

V_zero+ (V_OP2-V_OP1) * G

* 0,273

C_OPAFILT

R_OPAFILT

10-bit ADC

R_SH

ADC1_OUT_CH13

1

/

-

+ / -

LOW_X_STS

VN

+

CSA_CTRL

R_Stray

2 bit Gain

Control

PP_CHx_LOW

ADC1

DPP1

Ext. GND

CSA_OC_Det_Int.vsd

Figure 42 Simplified Application Diagram for Softshort Detection

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TLE9853QX

Application Information

28

Application Information

Note:

28.1

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Window-Lift Application Diagram

Rev. Polarity Protection

L_PF

ILT

VBAT

C_PF

ILT

C_VDDP2

C_VDDP1

C_VDDC1

C_VDDC2

EMC Filter

R_SWITCH1

R_{SWI TCH2}

D_VS

VDDP VDDC

VS

CP1H

CP1L

CP2H

C_CPS1

C_{VS 2}

C_{VS 1}

Switch3

Switch4

C_CPS2

CP2L

VCP

R_{VB AT _SE NSE}

VBAT_SENSE

R_{VS D}

C_VCP

C_{VB AT _SE NSE}

VSD

C_{VS D}

R_VDH

VDH

LIN

C_VDH

C_LIN

GND_LIN

D

S

D

S

VDDEXT

R_GATE

G

C_VDDEXT2

C_VDDEXT1

GH1

T_H1

C_{PH 1}

T_H2

C_{PH 2}

Speed

Direction

R_GS

C_GS

R_GS

C_GS

Double Hall

Sensor

e.g. TLE4966

P0.4 (CC60)

P1.0 (CC61)

R_GATE

GH2

SH2

R_MON1

MON1

C_SH

C_MON1

C_MON2

C_MON3

C_MON4

M

R_MON2

R_MON3

R_MON4

SH1

GL1

TLE985x

C_SH

MON2

MON3

MON4

D

S

D

S

R_GATE

G

T_L1

T_L2

R_GS

R_GATE

C_GS

R_GS

C_GS

GL2

SL

R_HS

HS

R_{SWI TCH3}

R_{SWI TCH4}

D_HS

C_HS

R_OPAFIL

T

Switch1

Switch2

R_GATE

OP2

OP1

R_Shunt

C_OPAFIL

T

Temp Sensor

P2.2

R_GATE

R_OPAFIL

T

TMS

P0.0

DebugConnector

P0.x

P2.x

P1.x

GND

R_TM

S

GND

Figure 43 Simplified Application Diagram Example

Note:

This is a very simplified example of an application circuit and bill of material. The function must be

verified in the actual application.

Table 13

Symbol

C_VS1

External Component (BOM)

Function

Component

22 µF¹⁾

100 nF²⁾³⁾

Capacitor 1 at VS pin

Capacitor 2 at VS pin

Reverse-polarity protection diode

C_VS2

D_VS

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Application Information

Table 13

Symbol

C_VDDEXT1

C_VDDEXT2

C_VDDC1

C_VDDC2

C_VDDP1

C_VDDP2

R_MONx

External Component (BOM) (cont’d)

Function

Component

470 nF³⁾

470 nF

100 nF³⁾

330nF

470 nF³⁾

470 nF

1 kΩ

Capacitor 1 at VDDEXT pin

Capacitor 2 at VDDEXT pin

Capacitor 1 at VDDC pin

Capacitor 2 at VDDC pin

Capacitor 1 at VDDP pin

Capacitor 2 at VDDP pin

Resistor at MONx pin

Capacitor at MONx pin

Resistor at VBAT_SENSE pin

Capacitor at VBAT_SENSE pin

Capacitor at LIN pin

C_MONx

10 nF

R_{VBAT_SENSE}

C_{VBAT_SENSE}

C_LIN

1 kΩ

10 nF

220 pF

160 Ω⁴⁾

R_HS

Resistor at HS pin

C_HS

Capacitor at HS pin

6.8 nF or 33 nF (dependant on ESD GUN

requirements)

D_HS

LED

R_VSD

Limitation of reverse currents due 2 Ω

to transients (-2V, 8ms)

C_VSD

Filter C for charge pump and driver 1 µF

C_CPS1

C_CPS2

C_VCP

Charge pump flying capacitor 1

Charge pump flying capacitor 2

Charge pump storage capacitor

Resistor

220 nF

470 nF

R_VDH

1 kΩ

C_VDH

Capacitor

1 nF

C_PH1

DC-link buffer capacitor phase 1

DC-link buffer capacitor phase 2

Shunt resistor

220 µF

C_PH2

220 µF

R_Shunt

R_OPAFILT

C_OPAFILT

C_SH

5 mΩ

Resistor

12 Ω

Capacitor

100 nF

Capacitor

1 nF

R_GATE

R_GS

Resistor

optional

Resistor

100 kΩ

C_GS

Capacitor

4.7 nF (depends on MOSFET C_GS)

L_PFILT

C_PFILT

R_SWITCHx

R_TMS

PI filter inductor

PI filter capacitor

Resistor

10 µF

Resistor

1) to be dimensioned according to application requirements

2) to reduce the effect of fast voltage transients of Vs, these capacitors should be placed close to the device pin

3) ceramic capacitor

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TLE9853QX

Application Information

4) calculated for 24V (jump start)

28.2

Connection of unused pins

Table 14 shows recommendations how to connect pins, in case they are not needed by the application.

Table 14

type

Recommendation for connecting unused pins

pin number

recommendation 1

(if unused)

recommendation 2

(if unused)

LIN

48

open

VS

HS

2

open

MON

GPIO

17, 18, 19, 20

GND

open + configure internal PU/PD

22, 24, 26, 27, 28, 29, 31, GND

32, 33, 34, 37, 38, 39, 40,

41

external PU/PD

or

open + configure internal PU/PD

TMS

23

25

40

41

45

47

GND

open

GND

open

VS

RESET

P2/XTAL out

P2/XTAL in

VDDEXT

VBAT_SENSE

28.3

Connection of P0.2 for SWD debug mode

To enter the SWD debug mode, P0.2 needs to be 0 at the rising edge of the reset signal.

P0.2 has an internal pulldown, so it just needs to be ensured that there is no external 1 at P0.2 when the debug

mode is entered.

28.4

Connection of TMS

For the debug mode, the TMS pin needs to be 1 at the rising edge of the reset signal. This is controlled by the

debugger. The TMS pin has an internal PD.

To avoid the device entering the debug mode unintendedly in the final application, adding an external pull-

down additionally is recommended.

28.5

ESD Tests

Note:

Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) were performed. The

results and test condition will be available in a test report. The target values for the test are listed in

Table 15 below.

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TLE9853QX

Application Information

Table 15

ESD “Gun Test”

Performed Test

Result

>6

Unit

kV

Remarks

ESD at pin LIN, versus GND

¹⁾positive pulse

¹⁾negative pulse

¹⁾²⁾positive pulse

< -6

kV

ESD at pin VS, VBAT_SENSE, MONx, >6

HS, versus GND

kV

ESD at pin VS, VBAT_SENSE, MONx, < -6

HS, versus GND

kV

¹⁾²⁾negative pulse

1) ESD susceptibility “ESD GUN”, tested by external test house (IBEE Zwickau, EMC Test report Nr. 07-01-19), according

to “LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008” and “Hardware Requirements for

LIN, CAN and FlexRay Interfaces in Automotive Application - AUDI, BMW, Daimler, Porsche, Volkswagen - Revision 1.3

/ 2012”

2) With external circuit as shown in Figure 43.

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TLE9853QX

Electrical Characteristics

29

Electrical Characteristics

This chapter includes all relevant Electrical Characteristics of the product TLE9853QX.

29.1

General Characteristics

29.1.1

Absolute Maximum Ratings

Table 16

Voltages Supply Pins

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

VS voltage

VSD voltage

V_S,max

-0.3

-

40

48

V

¹⁾Load dump

P_1.1.1

1)

V_SD,max

P_1.1.34

P_1.1.35

V_{SD,max_ext}-2.8

^{2) 1)}Series resistor; R_VSD=2.2Ω;

t=8ms

ended

1)

VDDP voltage

V_DDP,max

-0.3

-

5.5

V

P_1.1.2

P_1.1.3

1)

VDDEXT voltage

V_DDEXT,max-0.3

V_S+

0.3

1)

VDDC voltage

V_DDC,max

-0.3

-

1.6

V

P_1.1.4

1) Not subject to production test, specified by design

2) Conditions and min. value is derived from application condition for reverse-polarity event.

Table 17

Voltages High Voltage Pins

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1) 2)

Voltage at VBAT_SENSE V_{BAT_SENSE,}-28

-

40

V

P_1.1.5

P_1.1.6

max

2)

Voltage at HS pin

V_HS,max

-0.3

-28

-

V_S

+0.3

V

2)

Voltage at LIN pin

Voltage at MONx pins

Voltage at VDH pin

Voltage at GHx pins

V_LIN,max

-

40

48

14

V

P_1.1.7

P_1.1.8

P_1.1.36

P_1.1.37

P_1.1.38

1) 2)

V_MON,max-28

V

3) 2)

V_VDH,max

V_GH

-2.8

-8

V

4) 2)

V

2)

Voltage at GHx vs. SHx V_GHvsSH

-

V

pins

2)

Voltage at SHx pins

Voltage at GLx pins

V_SH

V_GL

-8

-

48

V

P_1.1.39

P_1.1.40

5) 2)

V

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TLE9853QX

Electrical Characteristics

Table 17

Voltages High Voltage Pins (cont’d)

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

2)

Voltage at GLx vs. SL

pins

V_GLvsSL

V_SL

-

14

V

P_1.1.41

2)

Voltage at SL pin

-8

-

48

V

P_1.1.49

P_1.1.42

6) 2)

Voltage at charge pump V_CPx

pins CP1H, CP1L, CP2H,

CP2L, VCP

-0.3

V

1) For -28V, external 1 kΩ resistor is required to limit output current.

2) Not subject to production test, specified by design

3) For -2.8V, external 1 kΩ resistor is required to limit output current.

4) To achieve max. ratings on this pin, Parameter P_1.1.38 has to be taken into account resulting in the following

dependency: V_GH< V_SH+ V_{GHvsSH_max}and additionally V_SH< V_GH+ 0.3 V

5) To achieve max. ratings on this pin, Parameter P_1.1.41 has to be taken into account resulting in the following

dependency: V_GL< V_SL+ V_{GLvsSL_max}and additionally V_SL< V_GL+ 0.3 V

6) These limits can be kept if max current drawn out of pin does not exceed limit of 200 μA

Table 18

Voltages GPIOs

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Voltage on port pin P0.x, V_IO,max

P1.x, P2.x, TMS and

RESET

-0.3

-

V_DDP+ V

0.3

¹⁾in consideration of V_IO,max

V_DDP@MAX

<

P_1.1.10

1) Not subject to production test, specified by design

Table 19

Voltages at Current Sense Amplifier Inputs

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Input voltage OP1, OP2 V_OAI

-7

-

7

V

P_1.1.43

1) Not subject to production test, specified by design

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TLE9853QX

Electrical Characteristics

Table 20

Currents

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Injection current in

Sleep Mode on P0.x,

P1.x, P2.x, TMS and

RESET

I_xx

-

5

mA ¹⁾maximum allowed injection P_1.1.11

current on single pin or sum of

pins in Sleep Mode and

unpowered device

Injection current on HS I_HS

-

150

-

mA ¹⁾current flowing into HS pin

(back supply in case of short to

battery)

P_1.1.12

P_1.1.44

1)

Max. current at VCP pin I_VCP

-15

mA

1) Not subject to production test, specified by design

Table 21

Temperatures

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Junction Temperature T_j

Storage Temperature T_stg

-40

-55

-

150

°C

P_1.1.14

P_1.1.15

1)

°C

1) Not subject to production test, specified by design

Table 22

ESD Susceptibility

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

ESD Susceptibility HBM V_ESD1

all pins

-2

-

2

kV

V

^{1) 2)}JEDEC HBM

P_1.1.16

P_1.1.17

P_1.1.18

P_1.1.48

ESD Susceptibility HBM V_ESD3

pins LIN vs. LINGND

-6

-

6

ESD Susceptibility CDM V_{ESD_CDM}-500 -

500

750

²⁾Charged device model, acc.

JEDEC JESD22-C101

²⁾Charged device model, acc.

JEDEC JESD22-C101

ESD Susceptibility CDM V_{ESD_CDM_C}-750 -

V

corner pins: 1, 12, 13, 24,

orner

25, 36, 37, 48

1) ESD susceptibility, ″JEDEC HBM″ according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF).

2) Not subject to production test, specified by design

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Electrical Characteristics

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

29.1.2

Functional Range

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

Table 23

Functional Range

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Supply voltage in Active V_{S_AM}

5.5

-

28

V

P_1.2.1

Mode

Extended Supply

voltage in Active Mode-

range 1

V_{S_AM_exten}28

-

40

V

¹⁾Functional with parameter

deviation

P_1.2.24

d_1

Extended Supply

voltage in Active Mode

V_{S_AM_exten}3.0

-

28

29

V

²⁾Functional with parameter

deviation

P_1.2.2

d_2

Supply voltage in Active V_{SD_AM}

Mode for MOSFET Driver

Supply

5.4

P_1.2.12

Extended maxiumum

supply voltage in Active

Mode for MOSFET Driver

Supply

V_{SD_AM_max}29

-

32

V

¹⁾Functional with parameter

deviation

P_1.2.13

_extended

Supply voltage for LIN V_{S_AM_LIN}5.5

Transceiver

-

18

28

V

Parameter Specification

P_1.2.3

P_1.2.4

Extended Supply

voltage for LIN

Transceiver and

Monitoring Inputs

(MONx) for all device

modes

V_{S_AM_LIN_e}4.0

Functional with parameter

deviation

xtend

Supply voltage in Stop V_{S_Stopmin}3.0

Mode

-

V

P_1.2.5

P_1.2.6

Min. Supply voltage in V_{S_Sleepmin}3.0

Sleep Mode

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Electrical Characteristics

Table 23

Functional Range (cont’d)

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

3)

Supply Voltage

transients slew rate

dV_S/dt

-5

-

5

V/µs

P_1.2.7

P_1.2.8

P_1.2.9

P_1.2.11

3)

Output current on any I_OH, I_OL

GPIO

-5

5

mA

3)

Output sum current for I_GPIO,sum

all GPIO pins

-50

50

mA

Junction Temperature T_j

-40

150

°C

1) This operation voltage range is only allowed for a short duration: t_max< 400 ms

2) Hall-Supply, ADC, SPI, UART, NVM, RAM, CPU fully functional and in spec down to V_s= 3 V. Actuators (High-Side Switch,

MOSFET Driver) in V_srange from 3 V < V_s< 5.5 V (High-Side Switch) or 3 V < V_s< 4.4 V (MOSFET Driver) functional but

some parameters can be out of spec

3) Not subject to production test, specified by design

29.1.3

Current Consumption

Table 24

Current Consumption

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Current Consumption in I_{Vs_40M}

Active Mode at pin VS

-

30

mA all digital modules enabled and P_1.3.18

functional, ADCs converting in

sequencer mode, PLL running,

no loads on GPIOs, VDDEXT off,

LIN in recessive state (no

communication), HSx enabled

but off, Charge Pump on,

MOSFET Driver enabled and on

(PWM running at 25kHz with a

capacitive load of C_Load= 10 nF),

CSA enabled.; 3V≤V_s≤28V;

f_sys=40MHz

Current consumption in I_VSD

Active Mode at pin VSD

-

50

25

mA Charge Pump on, MOSFET

Driver enabled and on (PWM

running at 25kHz with a

P_1.3.8

capacitive load of C_Load= 10 nF).

Current consumption in I_{VSD_BK}

Active Mode at pin VSD -

Brake Mode

mA Charge Pump on and in single- P_1.3.33

stage mode, MOSFET Driver

enabled and 2 Low-Side Drivers

on, but not switching;

I_CHARGE=15_D

Datasheet

99

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 24

Current Consumption (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Current consumption in I_{VSD_SMHM}

Sleep Mode at pin VSD -

Hold Mode

-

16

19

16

19

25

µA Device in Sleep mode, but Low P_1.3.34

Side Gates are charged

statically to keep low side

MOSFETs on. Current does not

include static Gate to Source

current caused by external Gate

to Source resistor.;

-40°C≤T_j≤85°C

Current consumption in I_{VSD_SMHM(}

µA Device in Sleep mode, but Low P_1.3.35

Side Gates are charged

Sleep Mode at pin VSD -

T_extend)

Hold Mode (extended

Temperature Range)

statically to keep low side

MOSFETs on. Current does not

include static Gate to Source

current caused by external Gate

to Source resistor.;

85°C<T_j≤150°C

Current consumption in I_{VSD_STPMH}

µA Device in Stop mode, but Low P_1.3.37

Side Gates are charged

Stop Mode at pin VSD -

M

Hold Mode

statically to keep low side

MOSFETs on. Current does not

include static Gate to Source

current caused by external Gate

to Source resistor.;

-40°C≤T_j≤85°C

Current consumption in I_{VSD_STPMH}

µA Device in Stop mode, but Low P_1.3.38

Side Gates are charged

Stop Mode at pin VSD -

M(T_extend)

Hold Mode (extended

Temperature Range)

statically to keep low side

MOSFETs on. Current does not

include static Gate to Source

current caused by external Gate

to Source resistor.;

85°C<T_j≤150°C

Current consumption in I_Sleep

Sleep Mode at pin VS

µA System in Sleep Mode,

microcontroller not powered,

Wake capable via LIN and MON;

GPIOs open (no loads) or

connected to GND;

P_1.3.2

-40°C≤T_j≤25°C

Datasheet

100

Rev. 1.0

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TLE9853QX

Electrical Characteristics

Table 24

Current Consumption (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Current consumption in I_{Sleep(T_exte}

-

35

µA ¹⁾System in Sleep Mode,

microcontroller not powered,

Wake capable via LIN and MON;

GPIOs open (no loads) or

connected to GND;

P_1.3.3

Sleep Mode at pin VS

nd)

(extended Temperature

Range)

25°C<T_j≤85°C; 3V≤V_s≤18V

Current consumption in I_{Sleep(V_T_e}

40

µA ¹⁾System in Sleep Mode,

microcontroller not powered,

Wake capable via LIN and MON;

GPIOs open (no loads) or

connected to GND;

P_1.3.4

Sleep Mode at pin VS

xtend)

(extended Voltage and

Temperature Range)

25°C<T_j≤85°C; 3V≤V_s≤28V

Current consumption in I_Cyclic

Sleep Mode at pin VS

with cyclic wake

-

30

40

µA during sleep period;

P_1.3.5

P_1.3.6

-40°C≤T_j≤25°C; 3V≤V_s≤28V

Current consumption in I_{Cyclic(T_exte}

µA ¹⁾during sleep period;

Sleep Mode at pin VS

25°C<T_j≤85°C; 3V≤V_s≤28V

nd)

with cyclic wake

(extended Temperature

Range)

Current consumption in I_Stop

Stop Mode at pin VS

-

60

µA System in Stop Mode,

microcontroller not clocked,

Wake capable via LIN and MON;

GPIOs open (no loads) or

connected to GND;

P_1.3.22

P_1.3.19

-40°C≤T_j≤25°C; 5.5V≤V_s≤18V

Current consumption in I_{Stop(T_exte}

90

110

µA ¹⁾System in Stop Mode,

microcontroller not clocked,

Wake capable via LIN and MON;

GPIOs open (no loads) or

connected to GND;

Stop Mode at pin VS

nd)

(extended Temperature

Range)

25°C<T_j≤85°C

Datasheet

101

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 24

Current Consumption (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Current consumption in I_{Stop_V_exte}

-

4.0

mA System in Stop Mode,

microcontroller not clocked,

Wake capable via LIN and MON;

GPIOs open (no loads) or

connected to GND;

-40°C≤T_j≤85°C; 3V≤V_s<5.5V

µA ¹⁾System in Stop Mode (during P_1.3.20

stop period), microcontroller

P_1.3.21

Stop Mode at pin VS

nd

Current consumption in I_{Stop_CS}

Stop Mode at pin VS

95

115

with cyclic sense

not clocked, Wake capable via

LIN and MON; VDDEXT off; High

Side off; GPIOs open (no loads)

or connected to GND or VDDP;

-40°C≤T_j≤85°C; 5.5V≤V_s≤18V

1) Not subject to production test, specified by design

29.1.4

Thermal Resistance

Table 25

Thermal Resistance

Symbol

Parameter

Values

Min. Typ. Max.

Unit Note or Test Condition

Number

Junction to Case

R_th(JC)

R_th(JA)

-

6

-

K/W ¹⁾measured to Exposed Pad

P_1.4.1

P_1.4.2

2)

Junction to Ambient

-

33

K/W

1) Not subject to production test, specified by design

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board . Board: 76.2x114.3x1.5mm³with 2 inner

copper layers (35μm thick), with thermal via array under the exposed pad contacting the first inner copper layer and

300mm²cooling area on the bottom layer (70μm).

29.1.5

Timing Characteristics

The transition times between the system modes are specified here. Generally the timings are defined from the

time when the corresponding bits in register PMCON0 are set until the sequence is terminated.

Datasheet

102

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 26

System Timing

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Wake-up over battery

Sleep-Exit

t_start

-

2.5

ms ¹⁾Battery ramp-up till MCU

software is running.

P_1.5.1

P_1.5.2

t_{sleep - exit}

-

2.5

ms ¹⁾rising/falling edge of any

wake-up signal (LIN, MON) till

MCU software running.

2) 1)

Sleep-Entry

t_{sleep - entry}

-

330

µs

P_1.5.3

1) Not subject to production test, specified by design

2) Wake events during Sleep-Entry are stored and lead to wake-up after Sleep Mode is reached.

Datasheet

103

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.2

Power Management Unit (PMU)

This chapter includes all electrical characteristics of the Power Management Unit.

29.2.1

PMU Input Voltage VS

Table 27

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Required decoupling

capacitance

C_VS1

C_VS2

0.1

-

µF ESR<1Ω

P_2.1.12

P_2.1.13

1)

Required buffer

10

-

µF

capacitance for stability

(load jumps)

1) Not subject to production test, specified by design

29.2.2

PMU I/O Supply Parameters VDDP

Table 28

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Specified Output

Current

I_VDDP

0

-

50

mA

P_2.1.1

P_2.1.2

P_2.1.3

Required decoupling

capacitance

C_VDDP1

C_VDDP2

0.47 -

-

µF ^{2) 3)}ESR<1Ω

3) 4)

Total required buffer

capacitance for stability

(load jumps, line steps)

2.2

µF

5)

Output Voltage

including line and load

regulation @ Active

Mode

V_DDPOUT

4.9 5.0

5.1

V

I

<90mA; V_s≥5.5V

P_2.1.4

P_2.1.5

load

5)

Output Voltage

V_DDPOUTST4.5 5.0

5.25

=I_{load_internal}+I_{load_external};

load

including line and load

regulation @ Stop Mode

I

_{load_external}=5mA;

OP

I

_{load_internal}=2mA; V_s≥5.5V

6)

Output Drop

V_{sV DDPout}

-

50

-

+400 mV

I

=50mA; V_s=3V

P_2.1.6

P_2.1.7

VDDP

Load Regulation

V_VDDPLOR-50

50

mV 2mA≤I_load≤90mA; T_j≤150°C;

C=C_VDDP1+C_VDDP2

Line Regulation

V_VDDPLIR

-50

-

50

mV 5.5V≤V_s≤28V

P_2.1.8

P_2.1.9

Overvoltage detection V_DDPOV

5.14 -

5.4

V

Overvoltage leads to

SUPPLY_NMI; V_s≥5.5V

Datasheet

104

Rev. 1.0

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TLE9853QX

Electrical Characteristics

Table 28

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Under Voltage Reset

V_DDPUV

2.55 2.7

2.8

V

P_2.1.10

P_2.1.15

4)

Voltagestabledetection ΔV_DDPSTB-220 -

+220 mV

range ⁷⁾

Over Current Diagnostic I_VDDPOC

90

-

220

mA current including VDDC current P_2.1.11

consumption

4)

Short-Circuit Diagnostic I_VDDPSC

270

-

600

8.9

mA

P_2.1.31

P_2.1.29

Pull Down Strength in I_VDDPPDSLP5.1

mA V_DDP=5V

Sleep Mode

1) Specified output current for port supply and additional other external loads connected to VDDP, excluding on-chip

current consumption.

2) only min. value is tested

3) The total capacitance on pin VDDP is specified by C_VDDP2including C_VDDP1

4) Not subject to production test, specified by design

5) Load current includes internal supply.

.

6) Output drop for I_VDDPplus internal supply

7) The absolute voltage value is the sum of parameters V_VDDP= V_VDDP+ ΔV_VDDPSTB

Table 29

Timing Parameters

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1) 2)

Overvoltage detection t_{FILT_VDDPO}465 665

865

µs

P_2.1.16

P_2.1.17

P_2.1.18

P_2.1.34

P_2.1.35

filter time

V

1) 2)

Overcurrent diagnostic t_{FILT_VDDPO}21 30

filter time

39

µs

C

1) 2)

Overcurrent diagnostic t_{FILT_VDDPO}615 920

shutdown time

1250 µs

C_SD

1) 2)

Short-circuit diagnostic t_{FILT_VDDPS}

filter time

5

10

13

µs

C

Short-circuit diagnostic t_{FILT_VDDPS}50 75

105

shutdown time

C_SD

1) This filter time and its variation is derived from the time base t_{LP_CK}= 1 / f_{LP_CLK}

2) Not subject to production test, specified by design

Datasheet

105

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.2.3

PMU Core Supply Parameters VDDC

Table 30

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Required decoupling

capacitance

C_VDDC1

C_VDDC2

0.1

-

1

µF ¹⁾ESR<1Ω

P_2.2.1

P_2.2.2

2)

Required buffer

0.33 -

1

µF

capacitance for stability

(load jumps)

Output Voltage

including line

regulation @ Active

Mode

V_DDCOUT

1.44 1.5

1.56

V

I_load<40mA

P_2.2.3

Output Voltage

including line

regulation @ Stop Mode

V_{DDCOUT_St}1.44 1.5

1.56

1.3

V

with setting of VDDC output

voltage to 1.5V in Stop Mode;

I_{load_internal}<2mA

P_2.2.26

P_2.2.25

op1

Output Voltage

including line

V_{DDCOUT_St}0.8

-

with setting of VDDC output

voltage to 0.9V in Stop Mode;

op2

regulation @ Stop Mode

- Reduced Core Supply

Voltage

I_{load_internal}<2mA

Load Regulation

V_DDCLOR

V_DDCLIR

-50

-25

-

50

mV 2mA≤I_load≤40mA;

C=C_VDDC1+C_VDDC2

P_2.2.4

Line Regulation

25

-

mV 5.5V≤V_s≤28V

P_2.2.5

P_2.2.6

Over Voltage Detection V_DDCOV

1.58 -

V

Overvoltage leads to

SUPPLY_NMI

Under Voltage Reset V_DDVUV

1.10 -

1.19

80

V

P_2.2.7

P_2.2.8

P_2.2.28

P_2.2.27

Over Current Diagnostic I_VDDCOC

Short-Circuit Diagnostic I_VDDCSC

40

-

mA

2)

120

240

2.7

Pulldown Strength in

Sleep Mode

I_VDDCPDSLP0.75 1.5

mA V_DDC=1.5V

1) only min. value is tested

2) Not subject to production test, specified by design

Datasheet

106

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 31

Timing Parameters

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1) 2)

Overvoltage detection t_{FILT_VDDCO}465 665

865

µs

P_2.2.11

P_2.2.12

P_2.2.13

P_2.2.29

P_2.2.30

filter time

V

1) 2)

Overcurrent diagnostic t_{FILT_VDDCO}21 30

filter time

39

µs

C

1) 2)

Overcurrent diagnostic t_{FILT_VDDCO}615 920

shutdown time

1250 µs

C_SD

1) 2)

Short-circuit diagnostic t_{FILT_VDDCS}

filter time

5

10

13

µs

C

Short-circuit diagnostic t_{FILT_VDDCS}50 75

105

shutdown time

C_SD

1) This filter time and its variation is derived from the time base t_{LP_CLK}= 1 / f_{LP_CLK}

.

2) Not subject to production test, specified by design

Datasheet

107

Rev. 1.0

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TLE9853QX

Electrical Characteristics

29.2.4

VDDEXT Voltage Regulator 5.0V

Table 32

VDDEXT Regulator Active Mode

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Specified Output

Current

I_VDDEXT

0

-

40

mA

P_2.3.1

P_2.3.2

P_2.3.3

Required decoupling

capacitance

C_VDDEXT1330

C_VDDEXT2100

1000 nF

ESR<1Ω

1)

Required buffer

capacitance for stability

(load jumps)

Output voltage

including line and load

regulation - Load 1

V_{DDEXT_LD1}4.9 5.0

5.1

V

I_load≤20mA; V_s≥5.5V

P_2.3.4

Output voltage

including line and load

regulation - Load 2

V_{DDEXT_LD2}4.9 5.0

I_load≤40mA; -40°C≤T_j≤150°C;

V_s≥5.5V

P_2.3.45

Output Drop - Load 1

Output Drop - Load 2

Load Regulation

V_s-

-

50

-

+300 mV ²⁾0mA≤I_load≤20mA; 3V≤V_s≤5V;

C=C_VDDEXT1+C_VDDEXT2

P_2.3.5

P_2.3.17

P_2.3.6

VDDEXT_L1

V_s-

+600 mV 20mA<I_load≤40mA; 3V≤V_s≤5V;

C=C_VDDEXT1+C_VDDEXT2

VDDEXT_L2

V_DDEXTLOR-100 -

10

mV ²⁾0mA≤I_load≤40mA; V_s≥5.5V;

C=C_VDDEXT1+C_VDDEXT2

Line Regulation - Load 1 V_VDDEXTLIR-50

Line Regulation - Load 2 V_VDDEXTLIR-60

Power Supply Rejection PSRR_VDDEX50

-

50

60

-

mV ²⁾0mA≤I_load≤20mA; 5.5V≤V_s≤28V P_2.3.7

mV 20mA<I_load≤40mA; 5.5V≤V_s≤28V P_2.3.50

dB ¹⁾0mA≤I_load≤20mA; V_r=2Vpp ;

V_s=13.5V; 0kHz<f≤1kHz

P_2.3.8

P_2.3.9

Ratio

T1

3)

Under Voltage

Shutdown

V_VDDEXTUV1.55 1.9

2.1

V

1)

Over Current Limitation I_VDDEXTOC100 250

380

24

mA

P_2.3.10

P_2.3.11

VDDEXT output

R_{VDDEXT_DI}16 20

kOh

m

discharge resistance

SCHG

1) Not subject to production test, specified by design

2) Tested with 10 uA.

3) When condition is met, the bit VDDEXT_CTRL.VDDEXT_UV_IS will be set.

Datasheet

108

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 33

Thermal Shutdown (Junction Temperature)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Thermal shutdown

temp.

T_jSD

180 200

215

°C

P_2.3.48

P_2.3.49

1)

Thermalshutdownhyst. ΔT

5

10

15

K

1) Not subject to production test, specified by design

Table 34

VDDEXT Regulator Low Current Mode

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Specified Output

Current

I_{VDDEXT_LCM}

0

-

5

mA

P_2.3.28

P_2.3.29

Output Voltage

including line and load

regulation

V_{DDEXT_LCM}4.6 5.0

5.1

V

I_load≤5mA; V_s≥5.5V

Output Drop

V_s-

-

50

+300 mV I_load≤5mA; 3V≤V_s≤5V;

C=C_VDDEXT1+C_VDDEXT2

P_2.3.30

P_2.3.31

VDDEXT_LCM

Load Regulation

Line Regulation

V_{DDEXTLOR_}-250 -

250

300

-

mV ¹⁾0mA≤I_load≤5mA; V_s≥5.5V;

C=C_VDDEXT1+C_VDDEXT2

mV ¹⁾0mA≤I_load≤5mA; 5.5V≤V_s≤28V P_2.3.32

LCM

V_{VDDEXTLIR_}-300 -

LCM

Power Supply Rejection PSRR_VDDEX50

Ratio

-

dB ²⁾0mA≤I_load≤5mA; V_r=2Vpp ;

V_s=13.5V; 0kHz<f≤1kHz

P_2.3.33

T_LCM1

1) Tested with 10 uA.

2) Not subject to production test, specified by design

Datasheet

109

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.2.5

VPRE Voltage Regulator (PMU Subblock) Parameters

Table 35

Functional Range

Symbol

Parameter

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Specified Output

Current

I_VPRE

0

-

90

mA

P_2.4.1

1) Not subject to production test, specified by design

29.2.5.1 Load Sharing Scenario of VPRE Regulator

The figure below shows the possible load sharing scenario of VPRE regulator.

VS

VPRE

max. 90 mA

VDDP - 5V

1: max. 50 mA

2: max. 70 mA

VDDP

C_VDDP

GND (Pin 43)

VDDC

VDDC - 1.5V

max. 20 mA

C_VDDC

GND (Pin 43)

Load Sharing VPRE – Scenarios 1 & 2

Load_Sharing_VPRE.vsd

Figure 44 Load Sharing Scenario of VPRE and VDDP Regulator

Datasheet

110

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.2.6

Power Down Voltage Regulator (PMU Subblock) Parameters

The PMU Power Down voltage regulator consists of two subblocks:

•

Power Down Pre regulator: VDD5VPD

Power Down Core regulator: VDD1V5_PD (Supply used for GPUDATAxy registers)

Both regulators are used as purely internal supplies. The following table contains all relevant parameter:

Table 36

Functional Range

Symbol

Parameter

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Power-On Reset

Threshold

V_{DD1V5_PD_}1.2

-

1.5

V

I

=internal load connected P_2.5.1

load

to VDD1V5_PD

RSTTH

1) Not subject to production test, specified by design

Datasheet

111

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.3

System Clocks

29.3.1

Electrical Characteristics Oscillators and PLL

Table 37

PMU Oscillators (Power Management Unit)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Frequency of LP_CLK

f_{LP_CLK}

17 20

23

MHz this clock is used at startup and P_3.1.1

can be used in case the PLL fails

Frequency of LP_CLK2 f_{LP_CLK2}

Table 38

70 100

130

kHz this clock is used for cyclic wake P_3.1.2

CGU Oscillator (Clock Generation Unit Microcontroller)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Short term frequency

deviation

f_TRIMST

-0.4

%

-

+0.4 MHz within any 100 ms, e.g. after

synchronization to a LIN frame

+1.49 MHz Including temperature and

P_3.1.3

P_3.1.4

%

Absolute accuracy

f_TRIMABSA

-

1.49

%

lifetime drift and supply

variation; T_j≤150°C

¹⁾startup time OSC from Sleep P_3.1.5

Mode, power supply stable

CGU-OSC Start-up time t_OSC

-

10

µs

1) Not subject to production test, specified by design

Table 39

PLL (Clock Generation Unit Microcontroller)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1) 2)

VCO reference

frequency range

f_REF

0.8

1

1.27 MHz

P_3.1.25

P_3.1.21

2)

VCO frequency (tuning) f_VCO

48

-

160

MHz

range

Input frequency range f_OSC

XTAL1 input freq. range f_OSCHP

4

5

-

40

16

40

MHz ^{3) 4) 2)}External input clock mode P_3.1.6

MHz ^{3) 2)}External crystal mode

P_3.1.23

P_3.1.7

3) 2)

Output freq. range

f_PLL

MHz

2)

Free-running frequency f_VCOfree

21.5 38

MHz

P_3.1.24

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Electrical Characteristics

Table 39

PLL (Clock Generation Unit Microcontroller) (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

2)

Input clock high/low

time

t_high/low

10

-

ns

P_3.1.8

Accumulated jitter with jacc_ext

-

8

ns

²⁾for K2=2; this parameter value P_3.1.10

external oscillator

is only valid with the

combination of an external

quartz oscillator (e.g. 5 MHz)

Lock-in time

t_L

-

260

µs

²⁾this parameter represents the P_3.1.11

duration from module power-

on to assertion of lock signal

1) oscillator or clock inaccuracy needs to be taken into accout, do not select a nominal frequency and PDIV in a

combination that fREF has exactly min or max value

2) Not subject to production test, specified by design

3) specified limits for fVCO and fREF need to be fulfilled, restrictions to PDIV, NDIV, K2DIV settings apply

4) Above 24MHz the hysteresis of the OSC_HP module needs to be switched off (see register SCU_XTAL_CTRL).

29.3.2

External Clock Parameters XTAL1, XTAL2

Table 40

Functional Range

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1) 2)

Input voltage range

limits for signal on

XTAL1

V_{IX1_SR}

-1.7

+

-

1.7

V

P_3.2.1

V_DDC

Input voltage

V_{AX1_SR}

0.3x -

-

V

^{3) 4)}Peak-to-peak voltage

P_3.2.2

(amplitude) on XTAL1

V_DDC

XTAL1 input current

I_IL

-20

4

-

20

16

µA 0V<V_IN<V_DDC

P_3.2.3

P_3.2.4

5) 6)

Oscillator frequency -

External input clock

mode

f_{OSC_EXT}

MHz

4)

Oscillator frequency -

External crystal (or

resonator) mode

f_{OSC_XTAL}

4

-

16

MHz

P_3.2.5

5) 7) 4) 2)

High time

Low time

Rise time

Fall time

High time

t_H

6

-

ns

P_3.2.6

P_3.2.7

P_3.2.8

P_3.2.9

P_3.2.10

5) 7) 4) 2)

t_L

-

ns

5) 7) 4) 2)

t_R

8

-

8

-

ns

5) 7) 4) 2)

t_F

-

ns

5) 8) 4) 2)

t_{H_PLLNM}

12

ns

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Electrical Characteristics

Table 40

Functional Range (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

5) 8) 4) 2)

Low time

Rise time

Fall time

t_{L_PLLNM}

t_{R_PLLNM}

t_{F_PLLNM}

12

-

ns

P_3.2.11

P_3.2.12

P_3.2.13

5) 8) 4) 2)

7

ns

5) 8) 4) 2)

-

7

ns

1) Overload conditions must not occur on pin XTAL1. This Parameter is not valid for stop mode.

2) Not subject to production test, specified by design

3) The amplitude voltage V_AX1refers to the offset voltage V_OFF. This offset voltage must be stable during the operation

and the resulting voltage peaks must remain within the limits defined by V_IX1

.

4) Default hysteresis settings (SCU_XTAL_CTRL.XTALHYSEN = 1_B, SCU_XTAL_CTRL.XTALHYSCTRL = 11_B)

5) Valid for rectangular full-swing input signals.

6) Hysteresis disabled (SCU_XTAL_CTRL.XTALHYSEN=0_B)

7) This performance is only valid for Prescaler Mode (VCO Bypass mode).

8) This performance is only valid for PLL Normal Mode.

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Electrical Characteristics

29.4

Flash Parameters

This chapter includes the parameters for the 48 KB embedded flash module (incl. config sector).

29.4.1

Flash Characteristics

Table 41

Flash Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

ns

¹⁾3V<V_s<28V

Number

Min. Typ. Max.

Read time

t_{read_ac}

-

75

P_4.1.22

P_4.1.1

Programming time per t_PR

3

3.5

ms ¹⁾3V<V_s<28V

128 Byte page

Programming time per t_{PR_FW}

128 Byte page incl.

Firmware routine

-

4

ms ¹⁾3V<V_s<28V

P_4.1.20

runtime for program

operation

Erase time per

sector/page

t_ER

-

4

-

4.5

5

ms ¹⁾3V<V_s<28V

P_4.1.2

Erase time per

sector/page incl.

Firmware routine

runtime for erase

operation

t_{ER_FW}

P_4.1.21

Data retention time

t_RET

20

50

30

10

32

-

year ¹⁾1,000 erase / program cycles P_4.1.3

s

Data retention time

year ^{2) 1)}1,000 erase / program

cycles; T_j=30°C

P_4.1.4

s

Flash erase endurance N_ER

for user sectors

kcyc ¹⁾Data retention time 5 years

les

P_4.1.5

Flash erase endurance N_SEC

for security pages

cycl ¹⁾Data retention time 20 years; P_4.1.6

es

T_j=25°C

3) 1)

Drain disturb limit

N_DD

kcyc

les

P_4.1.7

1) Not subject to production test, specified by design

2) Derived by extrapolation of lifetime tests.

3) This parameter limits the number of subsequent programming operations within a physical sector without a given

page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly.

For normal sector erase/program cycles this limit will not be violated. For data sectors the integrated EEPROM

emulation firmware routines handle this limit automatically, for wordline erases in code sectors (without EEPROM

emulation) it is recommended to execute a software based refresh, which may make use of the integrated random

number generator NVMBRNG to statistically start a refresh.

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Electrical Characteristics

29.5

Parallel Ports (GPIO)

29.5.1

Description of Keep and Force Current

V_DDP

keeper

current

PU Device

PUDSEL

P2.x

P1.x

P0.x

\PUDSEL

keeper

current

PD Device

V_SS

Figure 45 Pull-Up/Down Device

U

GPIO

Logical „1"

undefined

Logical „0"

7.5 KOhm (equivalent)

(1.5V / 200uA) ^*)

V_IH

V_IL

2.33 KOhm (equivalent)

(3.5V / 1.5mA) ^*)

I

I_PUK

I_PUF

^*)value for port 0 and 1, as example

Figure 46 Pull-Up Keep and Forced Current

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Electrical Characteristics

U

GPIO

Logical „1"

undefined

Logical „0"

2.33 KOhm (equivalent)

(3.5V / 1.5mA) ^*)

V_IH

V_IL

7.5 KOhm (equivalent)

(1.5V / 200uA) ^*)

I

I_PDK

I_PDF

^*)value for port 0 and 1, as example

Figure 47 Pull-Down Keep and Force Current

29.5.2

DC Parameters Port 0, Port 1, TMS, Reset

Note:

Operating Conditions apply.

Keeping signal levels within the limits specified in this table ensures operation without overload

conditions. For signal levels outside these specifications, also refer to the specification of the

overload current I_OV

.

Table 42

DC Characteristics Port0, Port1, TMS, Reset

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input low voltage

Input high voltage

Input Hysteresis

V_IL

-0.3

-

0.3 x

V_DDP

V

2.55V≤V_DDP<5.5V

P_5.2.1

P_5.2.2

P_5.2.3

V_IH

0.7x -

V_DDP

V_DDP+ V

0.3

HYS

0.11 -

x

V_DDP

-

V

¹⁾4.5V≤V_DDP≤5.5V; Series

Resistance=0Ω

Input Hysteresis

HYSexten 0.04 -

d

-

¹⁾2.55V≤V_DDP<4.5V; Series

Resistance=0Ω

P_5.2.16

x

V_DDP

2) 3)

Output low voltage

Output high voltage

V_OL

V_OH

-

1.0

0.4

-

V

I ≤I_OLmax; 2.55V≤V_DDP<5.5V P_5.2.4

OL

2) 3)

I ≤I_OLnom; 2.55V≤V_DDP<5.5V P_5.2.5

OL

V_DDP

I ≥I_OHmax; 2.55V≤V_DDP<5.5V P_5.2.6

OH

- 1.0

2) 3)

Output high voltage

V_OH

I_OZ2

V_DDP

-

V

I ≥I_OHnom; 2.55V≤V_DDP<5.5V P_5.2.7

OH

- 0.4

Input leakage current

-5

-

+5

µA ⁴⁾T_j≤85°C; 0V<V_IN<V_DDP

µA ⁴⁾T_j≤150°C; 0V<V_IN<V_DDP

P_5.2.8

P_5.2.9

I_{OZ2_T_exten}-15

+15

d

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Electrical Characteristics

Table 42

DC Characteristics Port0, Port1, TMS, Reset (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

5)

Pull-up level keep

current

I_PUK

I_PUF

I_PDK

I_PDF

-

-200 µA

V

≥V_IH

≤V_IL

≥V_IH

P_5.2.10

P_5.2.11

P_5.2.26

P_5.2.27

5)

Pull-up level force

current

-1.5

200

-

mA

µA

Pull-down level keep

current

-

Pull-down level force

current

1.5

mA

1)

6)

Pin capacitance

C_IO

-

10

6

pF

µs

P_5.2.12

P_5.2.13

Reset Pin Input Filter

Time

T_{filt_RESET}

3

4.5

1) Not subject to production test, specified by design

2) The values for I_OLnom, I_OLmax, I_OHnom, I_OHmaxdepend on the driver strength settings (see register bit fields

SCU_Px_POCON0.Px_PDMy) and are defined by P_5.2.20 ... P_5.2.25

3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for

pin groups must be respected (see P_1.2.9).

4) The given values are worst-case values. In production test, this leakage current is only tested at 150ºC; other values

are ensured by correlation. For derating, please refer to the following descriptions:

Leakage derating depending on temperature (T_J= junction temperature [ºC]):I_OZ= 0.05 x e^{(1.5 + 0.028xTJ)}[μA]. For

example, at a temperature of 95ºC the resulting leakage current is 3.2μA.

Leakage derating depending on voltage level (DV = V_DDP- V_PIN[V]):I_OZ= I_OZtempmax- (1.6 x DV) [μA]

This voltage derating formula is an approximation which applies for maximum temperature.

5) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the

default pin level: V_PIN≥ V_IHfor a pull-up; V_PIN≤ V_ILfor a pull-down.

Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the

enabled pull device: V_PIN≤ V_ILfor a pull-up; V_PIN≥ V_IHfor a pull-down.

These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general

purpose IO pins.

6) This filter time and its variation is derived from the time base t_{LP_CLK}= 1 / f_{LP_CLK}

.

Table 43

Current Limits for Port Output Drivers

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Output Current, Strong I_OLs5

Driver

-

1.6

5

mA

V

≥4.5V

P_5.2.20

P_5.2.21

P_5.2.22

DDP

1)

Output Current,

Medium Driver

I_OLm5

1.0

3

Output Current, Weak I_OLw5

0.25 0.5

Driver

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Electrical Characteristics

Table 43

Current Limits for Port Output Drivers (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Output Current, Strong I_OLs3

Driver

-

1.0

3

mA ¹⁾2.55V<V_DDP<4.5V

P_5.2.23

P_5.2.24

P_5.2.25

Output Current,

Medium Driver

I_OLm3

0.8

1.8

Output Current, Weak I_OLw3

0.15 0.3

Driver

1) These values apply for P_5.2.4 ... P_5.2.7: typ. values represent the "Nominal Output Current" (I_OLnom, - I_OHnom), max.

values represent the "Maximum Output Current" (I_OLmax, - I_OHmax

)

29.5.3

DC Parameters Port 2

Note:

Operating Conditions apply.

Keeping signal levels within the limits specified in this table ensures operation without overload

conditions. For signal levels outside these specifications, also refer to the specification of the

overload current I_OV

.

Table 44

DC Characteristics Port 2

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input low voltage

Input high voltage

Input Hysteresis

V_{IL_P2}

V_{IH_P2}

HYS_P2

-0.3

-

0.3 x

V_DDP

V

2.55V≤V_DDP<5.5V

P_5.3.1

P_5.3.2

P_5.3.3

0.7x -

V_DDP

V_DDP+ V

0.3

0.11 -

x

V_DDP

-

V

¹⁾4.5V≤V_DDP≤5.5V; Series

Resistance=0Ω

Input Hysteresis

HYS_{P2_exte}0.04 -

-

¹⁾2.55V≤V_DDP<4.5V; Series

Resistance=0Ω

P_5.3.10

x

nd

V_DDP

Input leakage current

I_{OZ1_P2}

-400 -

+400 nA ; T_j≤85°C; 0V<V_IN<V_DDP

P_5.3.4

Input leakage current

(extended temperature

range)

I_{OZ1_P2_T_}-1

-

+1

µA ; T_j≤150 °C ; 0V<V_IN<V_DDP

P_5.3.11

extend

2)

Pull-up level keep

current

I_{PUK_P2}

-

-30

µA

V

≥V_IH

P_5.3.5

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Electrical Characteristics

Table 44

DC Characteristics Port 2 (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

2)

Pull-up level force

current

I_{PUF_P2}

I_{PDK_P2}

I_{PDF_P2}

-750 -

-

µA

pF

V

≤V_IL

≥V_IH

P_5.3.6

P_5.3.12

P_5.3.13

P_5.3.7

2)

1)

Pull-down level keep

current

30

-

Pull-down level force

current

750

10

Pin capacitance (digital C_{IO_P2}

-

inputs/outputs)

1) Not subject to production test, specified by design

2) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the

default pin level: V_PIN≥ V_IHfor a pull-up; V_PIN≤ V_ILfor a pull-down.

Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the

enabled pull device: V_PIN≤ V_ILfor a pull-up; V_PIN≥ V_IHfor a pull-down.

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Electrical Characteristics

29.6

LIN Transceiver

29.6.1

Electrical Characteristics

Table 45

Bus Receiver Interface

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Receiver threshold

voltage, recessive to

dominant edge

V_{th_dom}

0.4x 0.45 x 0.53 x

V

SAE J2602

P_6.1.1

V_S

Receiver dominant

state

V_BUSdom

V_{th_rec}

-27

-

0.4 x

V_S

V

LIN Spec 2.2 (Par. 17)

SAE J2602

P_6.1.2

P_6.1.3

Receiver threshold

voltage, dominant to

recessive edge

0.47 0.55 x 0.6 x

x V_SV_S

V_S

Receiver recessive state V_BUSrec

0.6x -

V_S

1.15 x

V_S

V

¹⁾LIN Spec 2.2 (Par. 18)

²⁾LIN Spec 2.2 (Par. 19)

P_6.1.4

P_6.1.5

Receiver center voltage V_{BUS_CNT}0.47 0.5 x 0.525

5 x V_S

x V_S

V_S

Receiver hysteresis

V_HYS

0.07 0.12 x 0.175

V_SV_Sx V_S

0.4x 0.5 x 0.6 x

V

³⁾LIN Spec 2.2 (Par. 20)

P_6.1.6

P_6.1.7

Wake-up threshold

voltage

V_BUS,wk

V

V_S

Dominant analog filter t_{WK_ana,bus}

time for bus wake-up

3

-

15

µs

analog filtertime of transceiver P_6.1.88

Dominant time for bus t_WK,bus

wake-up

30

-

150

including analog and digital

filter time. Digital filter time can

be adjusted by

P_6.1.8

PMU.CNF_WAKE_FILTER

1) Maximum limit specified by design.

2) V_{BUS_CNT}= (V_{th_dom}+V_{th rec})/2

3) V_HYS= V_BUSrec- V_BUSdom

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Electrical Characteristics

Table 46

Bus Transmitter Interface

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

V_TxD=high Level

Number

Min. Typ. Max.

Bus recessive output

voltage

V_BUS,ro

0.8x -

V_S

V

P_6.1.9

V_S

Bus short circuit current I_BUS,sc

40 100

150

mA Current Limitation for driver

dominant state driver on

P_6.1.10

V_BUS=18V; LIN Spec 2.2 (Par. 12)

Leakage current

I_{BUS_NO_GN}

-

-450

0

µA LIN Spec 2.2 (Par. 15); V_BUS=-12V; P_6.1.11

V_s=0V

100

0

D

Leakage current

I_{BUS_NO_BA}

-

10

-

20

-

µA LIN Spec 2.2 (Par. 16); V_BUS=18V; P_6.1.12

V_s=0V

T

I_{BUS_PAS_do}-1

mA LIN Spec 2.2 (Par. 13); V_BUS=0V; P_6.1.13

V_s=18V

m

I_{BUS_PAS_re}

-

20

µA LIN Spec 2.2 (Par. 14); V_BUS=18V; P_6.1.14

V_s=8V

c

Bus pull-up resistance R_BUS

20 30

47

kOh Normal mode LIN Spec 2.2 (Par. P_6.1.15

m

26), also present in Sleep mode

Table 47

AC Characteristics - Transceiver Normal Slope Mode

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Propagation delay bus t_d(L),R

dominant to RxD LOW

0.1

-2

1

-

6

2

-

µs

LIN Spec 2.2 (Param. 31)

LIN Spec 2.2 (Par. 32);

P_6.1.16

P_6.1.17

P_6.1.18

Propagation delay bus t_d(H),R

recessive to RxD HIGH

Receiver delay

symmetry

t_sym,R

t_duty1

t_sym,R=t_d(L),R- t_d(H),R

Duty cycle D1 Normal

Slope Mode(for worst

case at 20 kbit/s)

0.39 -

6

¹⁾duty cycle 1, LIN Spec 2.2 (Par. P_6.1.19

27); D1=t_{bus_rec(min)}/2 t_bit

TH_Dom(max)=0.581xV_S;

TH_Rec(max)=0.744xV_S;

5.5V≤V_s≤18V; t_bit=50µs

;

Duty cycle D2 Normal

Slope Mode(for worst

case at 20 kbit/s)

t_duty2

-

0.581

¹⁾duty cycle 2, LIN Spec 2.2 (Par. P_6.1.20

28); D2=t_{bus_rec(max)}/2 t_bit

TH_Dom(max)=0.284xV_S;

TH_Rec(max)=0.422xV_S;

5.5V≤V_s≤18V; t_bit=50µs

;

Datasheet

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TLE9853QX

Electrical Characteristics

1) Bus load concerning LIN Spec. 2.2: Load 1 = 1 nF / 1 kΩ = C_BUS/ R_BUS, Load 2 = 6.8 nF / 660 Ω = C_BUS/ R_BUS, Load 3 = 10

nF / 500 Ω = C_BUS/ R_BUS

Table 48

AC Characteristics - Transceiver Low Slope Mode

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Propagation delay bus t_{d(L),R_LSM}0.1

dominant to RxD LOW

1

-

6

2

-

µs

LIN Spec 2.2 (Param. 31)

P_6.1.21

P_6.1.22

P_6.1.23

Propagation delay bus t_{d(H),R_LSM}0.1

recessive to RxD HIGH

Receiver delay

symmetry

t_{sym,R_LSM}-2

LIN Spec 2.2 (Par. 32);

t_sym,R=t_d(L),R- t_d(H),R

¹⁾duty cycle 3 LIN Spec 2.2 (Par. P_6.1.24

Duty cycle D3(for worst t_{duty1_LSM}0.41 -

case at 10.4 kbit/s)

7

29); D3=t_{bus_rec(min)}/2 t_bit

TH_Dom(max)=0.616xV_S;

TH_Rec(max)=0.778xV_S;

5.5V≤V_s≤18V; t_bit=96µs

;

Duty cycle D4(for worst t_{duty2_LSM}

-

0.590

¹⁾duty cycle 4 LIN Spec 2.2 (Par. P_6.1.25

case at 10.4 kbit/s)

30); D4=t_{bus_rec(max)}/2 t_bit

TH_Dom(max)=0.251xV_S;

TH_Rec(max)=0.389xV_S;

5.5V≤V_s≤18V; t_bit=96µs

;

1) Bus load concerning LIN Spec. 2.2: Load 1 = 1 nF / 1 kΩ = C_BUS/ R_BUS, Load 2 = 6.8 nF / 660 Ω = C_BUS/ R_BUS, Load 3 = 10

nF / 500 Ω = C_BUS/ R_BUS

Table 49

AC Characteristics - Transceiver Fast Slope Mode

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Propagation delay bus t_{d(L),R_FSM}0.1

dominant to RxD LOW

1

-

6

µs

P_6.1.26

P_6.1.27

P_6.1.28

Propagation delay bus t_{d(H),R_FSM}0.1

recessive to RxD HIGH

6

Receiver delay

symmetry (LIN Spec

V1.3 supply voltage

range)

t_{sym,R_VS_S}-1.5

1.5

µs

7V≤V_s≤18V; t_sym,R=t_d(L),R- t_d(H),R

pecV1.3

Receiver delay

symmetry

t_{sym,R_FSM}-2.0

-

2.0

µs

t_sym,R=t_d(L),R- t_d(H),R

P_6.1.42

Datasheet

123

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TLE9853QX

Electrical Characteristics

Table 49

AC Characteristics - Transceiver Fast Slope Mode (cont’d)

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Duty cycle D5(used for t_{duty1_FSM}0.39 -

-

¹⁾duty cycle 5; D1=t_{bus_rec(min)}/2 P_6.1.29

_bit; TH_Dom(max)=0.581xV_S;

62.5 kbit/s)

5

t

TH_Rec(max)=0.744xV_S;

5.5V≤V_s≤18V; t_bit=25µs

Duty cycle D6(used for t_{duty2_FSM}

62.5 kbit/s)

-

0.581

¹⁾duty cycle 6; D2=t_{bus_rec(max)}/2 P_6.1.30

t_bit; TH_Dom(max)=0.284xV_S;

TH_Rec(max)=0.422xV_S; t_bit=25µs

1) Bus load concerning LIN Spec. 2.2: Load 1 = 1 nF / 1 kΩ = C_BUS/ R_BUS, Load 2 = 6.8 nF / 660 Ω = C_BUS/ R_BUS, Load 3 = 10

nF / 500 Ω = C_BUS/ R_BUS

Table 50

AC Characteristics - Flash Mode

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Propagation delay bus t_{d(L),R_FM}0.1 0.5

dominant to RxD LOW

6

µs

P_6.1.31

P_6.1.32

P_6.1.33

Propagation delay bus t_{d(H),R_FM}0.1 0.5

recessive to RxD HIGH

6

Receiver delay

symmetry (LIN Spec

V1.3 supply voltage

range)

t_{sym,R_VS_S}-1.0

-

1.5

µs

7V≤V_s≤18V; t_sym,R=t_d(L),R- t_d(H),R

pecV1_3

Receiver delay

symmetry

t_{sym,R_FM}-2.0

-

2.0

-

µs

t_sym,R=t_d(L),R- t_d(H),R

P_6.1.86

P_6.1.34

Duty cycle D7(for worst t_{duty1_FM}0.39 -

¹⁾duty cycle D7;

case at 115 kbit/s)for +1

us Receiver delay

symmetry (used for 250

kbit/s programming)

5

D7=t_{bus_rec(min)}/(2 x t_bit) ;

TH_Dom(max)=0.581xV_S;

TH_Rec(max)=0.744xV_S; t_bit=8.7µs

Duty cycle D8(for worst t_{duty2_FM}

case at 115 kbit/s)for +1

us Receiver delay

symmetry (used for 250

kbit/s programming)

-

0.578

30

¹⁾duty cycle 8; D8=t_{bus_rec(max)}/(2 P_6.1.35

x t_bit) ; TH_Dom(max)=0.284xV_S;

TH_Rec(max)=0.422xV_S; t_bit=8.7µs

2)

LIN input capacity

C_{LIN_IN}

-

15

pF

P_6.1.36

1) Bus load: Load 1 = 1 nF / 500 Ω = C_BUS/ R_BUS

2) Not subject to production test, specified by design

Datasheet

124

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TLE9853QX

Electrical Characteristics

Table 51

AC Characteristics - Other Timings

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

TxD dominant time out t_timeout

Table 52

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

6

12

20

ms V_TxD=0V

P_6.1.37

Thermal Shutdown (Junction Temperature)

V_S= 5.5 V to 18 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Thermal shutdown

temp.

T_jSD

180 200

215

°C

P_6.1.38

P_6.1.39

1)

Thermalshutdownhyst. ΔT

-

10

-

K

1) Not subject to production test, specified by design

Datasheet

125

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TLE9853QX

Electrical Characteristics

29.7

High-Speed Synchronous Serial Interface

29.7.1

SSC Timing

The table below provides the SSC timing in the TLE9853QX:

Table 53 SSC Master Mode Timing (Operating Conditions apply, CL = 50 pF)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1) 2)

SCLK clock period

t₀

2 x

-

V

>2.7V

P_7.1.1

DDP

T_SSC

2)

MTSR delay from SCLK t₁

10

15

-

ns

V

>2.7V

P_7.1.2

P_7.1.3

P_7.1.4

DDP

MRST setup to SCLK

t₂

t₃

>2.7V

MRST hold from SCLK

1) T_SSCmin= T_CPU= 1/f_CPU

.

If f_CPU= 20 MHz, t₀= 100 ns. T_CPUis the CPU clock period.

2) Not subject to production test, specified by design

t₀

SCLK¹⁾

t₁

1)

MTSR

t₂

t₃

Data

valid

MRST¹⁾

t₁

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_Tmg1

Figure 48 SSC Master Mode Timing

Datasheet

126

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TLE9853QX

Electrical Characteristics

29.8

Measurement Unit

29.8.1

Electrical Characteristics

Table 54

ADC1 - Battery / Supply Voltage Measurement V_{BAT_SENSE}, V_S

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_{VBAT_SE}

-

0.047

-

P_8.1.10

attenuation:

_{BAT_SENSE}/V_S

_NSE, ATT_VS

V

Nominal operating

input voltage range

V_{BAT_SENSE}/V_S

V_{BAT_SENSE,}

_range, V_S,

0

-

25.77

200

300

V

¹⁾Max. value corresponds to typ. P_8.1.11

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_{VBAT_SENSE}

range

AccuracyofV_{BAT_SENSE}/V_SΔV_{BAT_SEN}-200 -

after calibration - with

IIR filter

mV -40°C≤T_j≤150°C; 5.5V≤V_s≤28V;

ADC1_FILTCOEFF0_13.CHx=11_B

; f_ADCI=f_{sys_max}

P_8.1.12

P_8.1.49

,

SE_IIR

ΔV_{S_IIR}

AccuracyofV_{BAT_SENSE}/V_SΔV_{BAT_SEN}-300 -

after calibration _SE, ΔV_S

mV -40°C≤T_j≤150°C; 5.5V≤V_s≤28V;

f_ADCI=f_{sys_max}

1) Not subject to production test, specified by design

Table 55

ADC1 - Monitoring Input Voltage Measurement V_MONx

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_VMONx

-

0.039

-

P_8.1.13

attenuation: VMONx

Nominal operating

input voltage range

VMONx

V_MONx,range

0

-

31.05

V

¹⁾Max. value corresponds to typ. P_8.1.14

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_VMONx

1) Not subject to production test, specified by design

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127

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TLE9853QX

Electrical Characteristics

Table 56

ADC1 - Port 2.x Voltage Measurement V_2.x

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_2.x

-

0.227

-

P_8.1.15

attenuation: VPort2.x

Nominal operating

input voltage range

VPort2.x

V_Port2.x,rang

0

-

V_DDPOU

V

¹⁾Max. value corresponds to typ. P_8.1.16

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_2.x

e

T

1) Not subject to production test, specified by design

Table 57

ADC1 - OPA Voltage Measurement V_OPA

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_OPA

attenuation: V_OPA

-

0.265

-

P_8.1.36

Nominal operating

V_OPA,range

0

-

4.57

V

¹⁾Max. value corresponds to typ. P_8.1.37

input voltage range V_OPA

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_OPA

Accuracy of V_OPAsense ΔV_{OPA_IIR}- 75

after calibration - with

IIR filter ²⁾

-

75

95

mV V_OP1=0V; V_OP2=0V; 5.5V≤V_s≤28V; P_8.1.38

ADC1_FILTCOEFF0_13.CHx=11_B

; CSA gain=40 ; f_ADCI=f_{sys_max}

Accuracy of V_OPAsense ΔV_OPA

-95

mV V_OP1=0V; V_OP2=0V; 5.5V≤V_s≤28V; P_8.1.52

CSA gain=40 ; f_ADCI=f_{sys_max}

after calibration ²⁾

1) Not subject to production test, specified by design

2) CSA + ADC1 (i.e. P_8.1.38 includes P_13.1.5 and P_13.1.7)

Table 58

ADC2 - Supply Voltage Measurement V_S

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_{VS_ADC}

-

0.039

-

P_8.1.1

attenuation: V_S

2

Nominal operating

V_S,ADC2

3

-

31.05

V

¹⁾Max. value corresponds to typ. P_8.1.2

input voltage range V_S

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_{VS_ADC2}

Accuracy of V_Safter

ΔV_S,ADC2-320 -

320

mV -40°C≤T_j≤150°C; 5.5V≤V_s≤28V

P_8.1.3

calibration

1) Not subject to production test, specified by design

Datasheet

128

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TLE9853QX

Electrical Characteristics

Table 59

ADC2 - Supply Voltage Measurement V_SD

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_{VSD_AD}

-

0.039

-

P_8.1.44

attenuation: V_SD

C2

Nominal operating

V_SD,ADC2

3

-

31.05

V

¹⁾Max. value corresponds to typ. P_8.1.39

input voltage range V_SD

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_{VSD_ADC2}

Accuracy of V_SDafter

ΔV_SD,ADC2-320 -

320

mV -40°C≤T_j≤150°C; 5.5V≤V_s≤28V

P_8.1.40

calibration

1) Not subject to production test, specified by design

Table 60

ADC2 - Supply Voltage Measurement V_CP

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_{VCP_AD}

-

0.023

-

P_8.1.41

attenuation: V_CP

C2

Nominal operating

V_CP,ADC2

3

-

52.65

V

^{1) 2)}Max. value corresponds to P_8.1.42

input voltage range V_CP

typ. ADC full scale input;

calculated: typ. V_BG/ typ.

ATT_{VCP_ADC2}

Accuracy of V_CPafter

ΔV_CP,ADC2-650 -

650

mV -40°C≤T_j≤150°C; 5.5V≤V_s≤28V

P_8.1.43

calibration

1) This is the theoretical nominal full-scale input range of the measurement chain. The allowed input voltage range at

the pin is given in the "Absolute Maximum Ratings" section.

2) Not subject to production test, specified by design

Table 61

ADC2 - VDDEXT Voltage Measurement V_DDEXT

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input to output voltage ATT_VDDEXT

-

0.195

-

P_8.1.17

attenuation: VDDEXT

Nominal operating

input voltage range

VDDEXT

V_DDEXT,rang

0

-

5.97

V

¹⁾Max. value corresponds to typ. P_8.1.18

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_{VCP_VDDEXT}

e

1) Not subject to production test, specified by design

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129

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TLE9853QX

Electrical Characteristics

Table 62

ADC2 - Pad Supply Voltage Measurement V_VDDP

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input-to-output voltage ATT_VDDP

-

0.195

-

P_8.1.4

attenuation: VDDP

Nominal operating

input voltage range

VDDP

V_DDP,range

0

-

V_DDPOU

_T+ 0.3

V

¹⁾Max. value corresponds to typ. P_8.1.5

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_VDDP

1) Not subject to production test, specified by design

Table 63

ADC2 - Reference Voltage Measurement V_PMUBG

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Input-to-output voltage ATT_PMUVBG

-

0.75

-

P_8.1.6

attenuation: VBG

Nominal operating

input voltage range VBG

V_PMUBG,ran0.8

-

V_DDC

0.1

-

V

¹⁾Max. value corresponds to typ. P_8.1.7

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_VBG

ge

Value of ADC2-V_PMUBG

measurement after

calibration

V_PMUBG

0.9 1.0

1.1

P_8.1.45

1) Not subject to production test, specified by design

Table 64

ADC2 - Core supply Voltage Measurement V_DDC

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input-to-output voltage ATT_VDDC

-

0.75

-

P_8.1.8

attenuation: VDDC

Nominal operating

input voltage range

VDDC

V_DDC,range0.6

-

V_DDC+ V

0.1

¹⁾Max. value corresponds to typ. P_8.1.9

ADC full scale input; calculated:

typ. V_BG/ typ. ATT_VDDC

1) Not subject to production test, specified by design

Datasheet

130

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TLE9853QX

Electrical Characteristics

29.8.2

Central Temperature Sensor Module

29.8.2.1 Electrical Characteristics

Table 65

Temperature Sensor Specifications

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Output voltage V_TEMPat

T₀=0ºC (273 K)

a

-

0.628

-

V

¹⁾T₀=0°C

P_8.2.1

P_8.2.2

1)

Temperature sensitivity b

b

-

2.31

-

mV/

K

Accuracy_1

Accuracy_2

Accuracy_3

Acc_1

-10

-5

-

10

5

°C

²⁾-40°C<T_j<85°C

¹⁾125°C<T_j<150 °C

85°C<T_j<125°C

P_8.2.3

P_8.2.4

P_8.2.5

Acc_2

Acc_3

1) Not subject to production test, specified by design

2) Accuracy with reference to on-chip temperature calibration measurement, valid for Mode1

Datasheet

131

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TLE9853QX

Electrical Characteristics

29.9

ADC1 (10-Bit)

29.9.1

Electrical Characteristics ADC1 (10-Bit)

These parameters describe the conditions for optimum ADC performance.

Note:

Operating Conditions apply.

Table 66

Timing and AC Specification

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

1)

Analog clock frequency f_ADCI

5

-

MHz

P_9.2.1

1) The limit values for f_ADCImust not be exceeded when selecting the peripheral frequency and the prescaler setting.

Table 67

DC Specification

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

DNL error

INL error

Gain error

EA_DNL

EA_INL

-2

-

2

LSB

P_9.2.8

P_9.2.9

P_9.2.10

-2

2

LSB T_j≤150°C

% of ^{1) 2)}Already calibrated by

EA_GAIN

-1.2

1.2

FSR implemented calibration unit

Offset error

EA_OFF

-2.5

-10

-2

-

2.5

10

2

LSB ²⁾already calibrated

P_9.2.11

P_9.2.33

P_9.2.12

Total unadjusted error EA_TUE

2)

Cross-coupling

Attenuation between LV

Channels

EA_CCOUP

LSB

2)

Input capacitance of a C_{AINT_HVI}

HV analog input

-

200

fF

P_9.2.13

P_9.2.19

2)

Input capacitance of a C_{AINT_LVI}

fF

LV analog input

1) This Gain error is calibrated by IFX end of line

2) Not subject to production test, specified by design

Datasheet

132

Rev. 1.0

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TLE9853QX

Electrical Characteristics

29.10

High-Voltage Monitoring Input

29.10.1 Electrical Characteristics

Table 68

Electrical Characteristics Monitoring Input

V_S= 5.5 V to 28 V; T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Wake-up/monitoring

threshold voltage

V_MONth

0.4x 0.5 x 0.6 x

V

without external serial resistor P_10.1.1

R_s(with R_s:dV = I_PD/PU* R_s);

V_S

Threshold hysteresis

V_MONth,hys0.02 0.06 x 0.12 x

in all modes; without external P_10.1.2

x V_SV_S

V_S

serial resistor R_s(with R_s:dV =

I_PD/PU* R_s);

Pull-up current

I_{PU, MON}

I_{PD, MON}

I_LK,MON

t_FT,MON

-20 -10

-5

20

2

µA V_{MON_IN}=0.6*V_s

P_10.1.3

P_10.1.4

P_10.1.5

P_10.1.6

Pull-down current

Input leakage current

Wake-up filter time

5

-2

-

10

-

µA V_{MON_IN}=0.4*V_s

µA ¹⁾T_j<150°C; 0V<V_{MON_IN}<28V

2)

20

-

µs

1) Valid for enabled module. Pull-up and pull down current functionality disabled; ADC1 off.

2) With pull-up, pull down current disabled.

Datasheet

133

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.11

High Side Switch

29.11.1 Electrical Characteristics

Table 69

Operating areas

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

PWM frequency of HS

with Slew Rate Control

f_{PWM_W_SR}

0

-

10

kHz ¹⁾Frequency must be

configured in the PWM

Generator

P_11.1.1

PWM frequency of HS

without Slew Rate

Control

f_{PWM_W/O_S}

0

-

25

kHz ^{2) 1)}Frequency must be

configured in the PWM

Generator (minimum ON / OFF

time 5 us)

P_11.1.2

R

1) Not subject to production test, specified by design

2) Referring to a 47Ohm series resistor to charge an external power mos gate.

Table 70

Output HS

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

ON-State Resistance

R_ON

3.5 10

15

Oh V_s=13.5V; Ids=100mA

P_11.1.3

m

Output leakage Current I_leakage

-1.5

-

µA Output OFF; -0.3V<V_HS<V_S

P_11.1.4

P_11.1.5

Output Slew Rate

(rising) with slow Slew

Rate setting (Slew Rate

1)

SR_{raise_SR1}1.5

SR_{fall_SR1}-7

SR_{raise_SR2}21

SR_{fall_SR2}-30

7

V/µs 20% to 80% of V_S; C_L=1nF;

R_L=300Ω

Output Slew Rate

(falling) with slow Slew

Rate setting (Slew Rate

1)

-

-1.5

80

V/µs 80% to 20% of V_S; C_L=1nF;

R_L=300Ω

P_11.1.6

P_11.1.7

P_11.1.8

Output Slew Rate

(rising) with fast Slew

Rate setting (Slew Rate

2)

V/µs 20% to 80% of V_S; C_L=1nF;

R_L=300Ω

Output Slew Rate

(falling) with fast Slew

Rate setting (Slew Rate

2)

-3

V/µs 80% to 20% of V_S; C_L=1nF;

R_L=300Ω

Datasheet

134

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 70

Output HS (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Output Slew Rate

(rising) with Slew Rate

setting for low Emission

(Slew Rate 3)

SR_{raise_SR3}0.3

-

1.8

V/µs 20% to 80% of V_S; C_L=1nF;

R_L=300Ω

P_11.1.59

Output Slew Rate

SR_{fall_SR3}-1.8

-

-0.3

V/µs 80% to 20% of V_S; C_L=1nF;

R_L=300Ω

P_11.1.60

(falling) with Slew Rate

setting for low Emission

(Slew Rate 3)

Turn ON Delay time

(Slew Rate 1)

t_{IN-HS_SR1}1.1 2.2

3.6

8.8

16

µs

ON=1 to 20% of V_S; C_L=1nF;

R_L=300Ω

P_11.1.9

Turn ON time (Slew Rate t_{ON_SR1}

1)

2.1

5

-

HS_ON=1 to 80% of V_S; C_L=1nF; P_11.1.10

R_L=300Ω

Turn OFF time (Slew

Rate 1)

t_{OFF_SR1}

HS_ON=0 to 20% of V_S; C_L=1nF; P_11.1.11

R_L=300Ω

Turn ON Delay time

(Slew Rate 2)

t_{IN-HS_SR2}0.08 0.22 0.38 µs

ON=1 to 20% of V_S; C_L=1nF;

R_L=300Ω

P_11.1.55

Turn ON time (Slew Rate t_{ON_SR2}

2)

0.2

1.1

-

1.2

2.7

µs

HS_ON=1 to 80% of V_S; C_L=1nF; P_11.1.56

R_L=300Ω

Turn OFF time (Slew

Rate 2)

t_{OFF_SR2}

HS_ON=0 to 20% of V_S; C_L=1nF; P_11.1.57

R_L=300Ω

Turn ON Delay time

(Slew Rate 3)

t_{IN-HS_SR3}3.5 8.2

13.5 µs

ON=1 to 20% of V_S; C_L=1nF;

R_L=300Ω

P_11.1.61

Turn ON time (Slew Rate t_{ON_SR3}

3)

7.8

18

-

36

64

µs

HS_ON=1 to 80% of V_S; C_L=1nF; P_11.1.62

R_L=300Ω

Turn OFF time (Slew

Rate 3)

t_{OFF_SR3}

HS_ON=0 to 20% of V_S; C_L=1nF; P_11.1.63

R_L=300Ω

Table 71

Overcurrent detection

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

26 40.5 56

Overcurrent threshold I_octh0

0,trimmed

mA V_s=13.5V; HSx_OC_SEL=00

mA ¹⁾HSx_OC_SEL=00

P_11.1.12

P_11.1.13

P_11.1.14

Overcurrent threshold 0 I_octh0,hyst2.5

5

12

86

hysteresis

Overcurrent threshold I_octh1

51 65

mA V_s=13.5V; HSx_OC_SEL=01

1,trimmed

Datasheet

135

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 71

Overcurrent detection (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Overcurrent threshold 1 I_octh1,hyst

hysteresis

4

8

17

mA ¹⁾HSx_OC_SEL=01

P_11.1.15

P_11.1.16

P_11.1.17

P_11.1.18

P_11.1.19

Overcurrent threshold I_octh2

2,trimmed

101 134

180

33

mA V_s=13.5V; HSx_OC_SEL=10

mA ¹⁾HSx_OC_SEL=10

Overcurrent threshold 2 I_octh2,hyst11 17

hysteresis

Overcurrent threshold I_octh3

3,trimmed

151 201

270

67

mA V_s=13.5V; HSx_OC_SEL=11

mA ¹⁾HSx_OC_SEL=11

Overcurrent threshold 3 I_octh3,hyst22 35

hysteresis

Overcurrent shutdown t_ocft

8

-

80

µs

¹⁾HS_ON to OC_SD (including P_11.1.20

response time

switch-on time); R_L=100Ω;

V_s=13.5V

1) Not subject to production test, specified by design

Table 72

ON-state open load detection

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Open load threshold

Hysteresis

I_OLONth

0.35 -

2.15 mA

P_11.1.21

P_11.1.22

I_OLONhys

0.01 -

5

0.3

mA

Table 73

Cyclic sense mode

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Current capability

I_{HS max}

40

-

mA Sleep Mode / Stop Mode Cyclic P_11.1.23

Operation

sleep_pd

ON-State Resistance

R_ON,static

-

105

18

-2.5

Oh Ids=40mA

m

P_11.1.24

P_11.1.25

P_11.1.26

Output Slew Rate

(rising)

SR_{rise_cyc}0.9

SR_{fal_cycl}-34

V/µs 20% to 80% of V_S; R_L=300Ω;

V_s≤18V

Output Slew Rate

(falling)

V/µs 80% to 20% of V_S; R_L=300Ω;

V_s≤18V

Datasheet

136

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 73

Cyclic sense mode (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Delay Time CYCLIC_ON- t_{IN_cyc}

HS

0.2

-

5.6

µs

ON=1 to 20% of V_S; R_L=300Ω;

V_s≤18V

P_11.1.27

Turn-ON time

Turn-OFF time

t_{ON_cyc}

t_{OFF_cyc}

1.5

0.8

-

15

µs

ON=1 to 80%; R_L=300Ω; V_s≤18V P_11.1.28

3.4

ON=0 to 20% of V_S; R_L=300Ω;

V_s≤18V

P_11.1.29

Datasheet

137

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.12

MOSFET Driver

29.12.1 Electrical Characteristics

Table 74

MOSFET Driver Output

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Gate charge current

I_chg0

3

7

12

mA ¹⁾C_L=10nF; I_CHARGE=0_D;

P_12.1.80

P_12.1.81

P_12.1.82

P_12.1.83

P_12.1.84

P_12.1.44

P_12.1.85

V

_GSx≤V_GS(on); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_CHARGE=3_D;

_GSx≤V_GS(on); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_CHARGE=7_D;

_GSx≤V_GS(on); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_CHARGE=15_D;

_GSx≤V_GS(on); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_CHARGE=31_D;

_GSx≤V_GS(on); V_SD≥7.4V

mA C_L=10nF; I_CHARGE=63_D;

_GSx≤V_GS(on); V_SD≥7.4V

I_chg3

8

15

23

V

I_chg7

16 26

38 53

96 125

260 320

36

V

I_chg15

I_chg31

I_chg63

68

V

154

380

+25 %

V

Gate charge current

dynamic average

deviation

Δ I

-25

%

-

¹⁾Reference: typ. I_chgx; C_L=10,

33nF; SR_{on_SHx}=165V/µs;

V_GSx≤V_GS(on)

chg_avg_%

Gate discharge current I_dischg0

Gate discharge current I_dischg3

Gate discharge current I_dischg7

Gate discharge current I_dischg15

Gate discharge current I_dischg31

Gate discharge current I_dischg63

Gate discharge current Δ I

3

8

7

12

mA ¹⁾C_L=10nF; I_DISCHARGE=0_D;

V_GSx≥V_GS(off); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_DISCHARGE=3_D;

V_GSx≥V_GS(off); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_DISCHARGE=7_D;

V_GSx≥V_GS(off); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_DISCHARGE=15_D;

P_12.1.86

P_12.1.87

P_12.1.88

P_12.1.89

P_12.1.90

P_12.1.45

15

23

16 26

38 53

96 125

260 320

36

68

V

_GSx≥V_GS(off); V_SD≥7.4V

mA ¹⁾C_L=10nF; I_DISCHARGE=31_D;

_GSx≥V_GS(off); V_SD≥7.4V

mA C_L=10nF; I_DISCHARGE=63_D;

_GSx≥V_GS(off); V_SD≥7.4V

154

380

+28 %

V

-28

%

-

¹⁾Reference: typ. I_dischgx; C_L=10, P_12.1.91

33nF; SR_{off_SHx}=165V/µs;

dynamic average

dischg_avg_

deviation

V_GSx≥V_GS(off); V_SD≥7.4V

%

High level output

voltage Gxx vs. Sxx

V_Gxx1

10

12

V

²⁾all other Drivers enabled but P_12.1.3

not ON; C_L=10nF; I_CP=6mA;

V_SD≥7.4V

Datasheet

138

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 74

MOSFET Driver Output (cont’d)

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

High level output

V_Gxx2

8

7

8

7

-

V

^{2) 1)}all other Drivers enabled but P_12.1.4

not ON; C_L=10nF; I_CP=6mA;

V_SD=6.4V

²⁾all other Drivers enabled but P_12.1.5

not ON; C_L=10nF; I_CHARGE≤31_D;

voltage GHx vs. SHx

High level output

V_Gxx3

voltage GHx vs. SHx

I_CP=6mA; V_SD=5.4V

High level output

V_Gxx6

^{2) 1)}all other Drivers enabled but P_12.1.6

voltage GLx vs. GND

not ON; C_L=10nF; I_CP=6mA;

V_SD=6.4V

High level output

V_Gxx7

²⁾all other Drivers enabled but P_12.1.7

not ON; C_L=10nF; I_CP=6mA;

V_SD=5.4V

voltage GLx vs. GND

High level output

voltage GLx vs. GND /

GHx vs. SHx - Brake

Mode

V_{Gxx_BM}

all other Drivers enabled but

P_12.1.66

not ON; C_L=10nF; R_GS=100kΩ;

V_SD=5.4V

High level output

voltage GLx vs. GND -

Hold Mode

V_{Gxx_HM}

2.5

4.2

-

7.1

7.4

V

; C_L=10nF; R_GS=100kΩ; V_SD≥5.4V P_12.1.67

¹⁾; C_L=10nF; R_GS=100kΩ;

P_12.1.102

V_SD≥7.4V

1)

External MOSFET gate- V_GS(on)

to-source voltage -

MOSFET on

5

7

-

V

=5.4V

=7.4V

P_12.1.103

P_12.1.95

SD

1)

SD

1)

External MOSFET gate- V_GS(off)

to-source voltage -

MOSFET off

-

2

V

I

<31_D

≥31_D

P_12.1.104

P_12.1.96

DISCHARGE

3.5

I

DISCHARGE

Rise time

Fall time

Rise time

Fall time

t_{rise3_3nf}

t_{fall3_3nf}

t_risemax

t_fallmax

65 100

100 250

130

450

ns

¹⁾25-75% of V_Gxx1; C_L=3.3nF;

I_CHARGE=max ; I_DISCHARGE=max ;

V_SD≥7.4V

P_12.1.8

P_12.1.9

P_12.1.57

P_12.1.58

¹⁾75-25% of V_Gxx1; C_L=3.3nF;

I_CHARGE=max ; I_DISCHARGE=max ;

V_SD≥7.4V

25-75% of V_Gxx1; C_L=10nF;

I_CHARGE=max ; I_DISCHARGE=max ;

V_SD≥7.4V

75-25% of V_Gxx1; C_L=10nF;

I_CHARGE=max ; I_DISCHARGE=max ;

V_SD≥7.4V

Datasheet

139

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 74

MOSFET Driver Output (cont’d)

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Rise time

t_risemin

4

-

15

µs

ns

¹⁾25-75% of V_Gxx1; C_L=10nF;

_CHARGE=min ; I_DISCHARGE=min ;

V_SD≥7.4V

¹⁾75-25% of V_Gxx1; C_L=10nF;

I_CHARGE=min ; I_DISCHARGE=min ;

V_SD≥7.4V

P_12.1.14

I

Fall time

t_fallmin

3.5

12

P_12.1.15

P_12.1.35

P_12.1.36

Absolute rise - fall time t_{r_f(diff)LSx}

difference for all LSx

-

100

25-75% of V_Gxx1; C_L=10nF;

I_CHARGE=max ; I_DISCHARGE=max ;

V_SD≥7.4V

Absolute rise - fall time t_{r_f(diff)HSx}

25-75% of V_Gxx1; C_L=10nF;

difference for all HSx

I_CHARGE=max ; I_DISCHARGE=max ;

V_SD≥7.4V

Resistor between

GHx/GLx and GND

R_GGND

R_SHGN

30 40

50

kOh

m

P_12.1.11

P_12.1.10

Resistor between SHx

and GND

kOh ³⁾This resistance is the

m

resistance between GHx and

GND connected through a diode

to SHx. As a consequence the

voltage at SHx can rise up to

0,6V typ. before it gets

discharged through the resistor.

Effective

R_ONCCP

-

9

12

Oh 50mA forced into Gx, Sx

P_12.1.50

dischargeRDSON

m

grounded; I_DISCHARGE=63_D;

V_VCP=V_VSD+14.0V; V_VSD=13.5V

Input propagation time t_P(ILN)min

(LS on)

-

3

8

µs

ns

¹⁾"ON"=1 to 25% of V_Gxx1

C_L=10nF; I_CHARGE=min

¹⁾"ON"=0 to 75% of V_Gxx1

C_L=10nF; I_DISCHARGE=min

¹⁾"ON"=1 to 25% of V_Gxx1

C_L=10nF; I_CHARGE=min

¹⁾"ON"=0 to 75% of V_Gxx1

C_L=10nF; I_DISCHARGE=min

;

P_12.1.37

P_12.1.38

P_12.1.39

P_12.1.40

Input propagation time t_P(ILF)min

(LS off)

3

8

Input propagation time t_P(IHN)min

(HS on)

3

8

Input propagation time t_P(IHF)min

(HS off)

3

8

Input propagation time t_P(ILN)max

(LS on)

200

350

300

350

"ON"=1 to 25% of V_Gxx1; C_L=10nF; P_12.1.26

_CHARGE=max

"ON"=0 to 75% of V_Gxx1; C_L=10nF; P_12.1.27

_DISCHARGE=max

"ON"=1 to 25% of V_Gxx1; C_L=10nF; P_12.1.28

_CHARGE=max

I

Input propagation time t_P(ILF)max

(LS off)

I

Input propagation time t_P(IHN)max

(HS on)

I

Datasheet

140

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 74

MOSFET Driver Output (cont’d)

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Input propagation time t_P(IHF)max

(HS off)

-

200

300

ns

"ON"=0 to 75% of V_Gxx1; C_L=10nF; P_12.1.29

_DISCHARGE=max

"ON"=1 to 25% of V_Gxx1; C_L=10nF; P_12.1.30

_CHARGE=max

I

Absolute input

t_Pon(diff)LSx

t_{Poff(diff)LSx}

t_Pon(diff)HSx

t_{Poff(diff)HSx}

-

100

propagation time

difference between

propagation times for

all LSx (LSx on)

I

Absolute input

-

100

ns

"ON"=0 to 75% of V_Gxx1; C_L=10nF; P_12.1.41

I_CHARGE=max

propagation time

difference between

propagation times for

all LSx (LSx off)

Absolute input

"ON"=1 to 25% of V_Gxx1; C_L=10nF; P_12.1.42

I_CHARGE=max

propagation time

difference between

propagation times for

all HSx (HSx on)

Absolute input

"ON"=0 to 75% of V_Gxx1; C_L=10nF; P_12.1.43

I_CHARGE=max

propagation time

difference between

propagation times for

all HSx (HSx off)

1) Not subject to production test, specified by design

2) The condition I_CP= 6 mA emulates H-Bridge Drive with 2 MOSFET switching at 25 kHz and C_L= 10 nF.

3) This resistance is connected through a diode between SHx and GHx to ground.

Table 75

Charge-Discharge Current Timing Characteristics

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Charge current delay

time

t_dly(on)

-

35

50

90

ns

¹⁾from ″ON″=1 to 20% of I_chgx

(x=0...63); C_L=10nF

¹⁾from 20% of I_chgxto I_chgx,min

(x=0...63); C_L=10nF

P_12.1.63

P_12.1.64

P_12.1.68

Charge current rise time t_rise(on)

70

Gate Source Voltage

Saturation Time

t_sat(on)

100

¹⁾from V_GS=V_GS(on)to V_Gxxy,min

C_L=10nF; I_CHARGE=63

;

Datasheet

141

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 75

Charge-Discharge Current Timing Characteristics (cont’d)

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Charge current settling t_{set_chg(seq)}

time - sequencer mode

-

150

ns

^{2) 1)}from any I_CHARGE(n)to

I_CHARGE(n+1)= 0_Dor 63_D; C_L=10nF

^{3) 1)}from any I_DISCHARGE(n)to

I_{DISCHARGE(n+1)}= 0_Dor 63_D;

C_L=10nF

P_12.1.69

P_12.1.70

Discharge current

settling time -

t_{set_dischg(s}

-

75

eq)

sequencer mode

Discharge current delay t_dly(off)

time

-

25

80

50

ns

¹⁾from "ON"=0 to 20% of I_dischgxP_12.1.71

(x=0...63); C_L=10nF

¹⁾from 20% of I_dischgxto I_dischgx,minP_12.1.72

(x=0...63); C_L=10nF

Discharge current rise t_rise(off)

time

1) Not subject to production test, specified by design

2) I_CHARGE(n)and I_CHARGE(n+1)are consecutive gate charge current set points in sequencer mode.

3) I_DISCHARGE(n)and I_{DISCHARGE(n+1)}are consecutive gate discharge current set points in sequencer mode.

Table 76

Timing Measurement Comparators

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Low-side timing

measurement

V_SH(low)

2

-

2.5

V

P_12.1.73

comparator threshold

High-side timing

measurement

comparator threshold

V_SH(high)

V_SD- -

2.5V

V_SD

2V

-

V

P_12.1.74

P_12.1.75

P_12.1.76

Delay of low-side timing t_cdly(low)

measurement

comparator

5

-

20

25

ns

Delay of high-side

timing measurement

comparator

t_cdly(high)

Datasheet

142

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 77

Drain source monitoring

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Drain source

monitoring threshold

V_DSMONVTH0.11 0.145 0.178

V

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.46

=000_B

2

0.22 0.27 0.311

9

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.105

=001_B

0.42 0.5

5

0.575

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.106

=010_B

0.63 0.75 0.863

7

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.107

=011_B

0.85 1.00 1.15

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.108

=100_B

1.06 1.25 1.44

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.109

=101_B

1.27 1.5

1.73

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.110

=110_B

1.48 1.75 2.02

BDRV_CTRL3.DSMONVTH<2:0> P_12.1.111

=111_B

Table 78

Open load diagnosis currents

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Pull-Up diagnosis

current

I_PUDiag

I_PDDiag

I_{PDDiag_OD}200

-700 -

-300 µA I_DISCHARGE=0 ; V_SD≥6.4V; V_SHx=5V; P_12.1.47

V_s≥5.4V

Pull-Down diagnosis

current

800

-

1450 µA I_DISCHARGE=0 ; V_SD≥6.4V; V_SHx=5V; P_12.1.48

V_s≥5.4V

Effective Pull-Down

diagnosis current

overdrive

-

µA I_DISCHARGE=0 ; V_SD≥6.4V; V_SHx=5V; P_12.1.100

V_s≥5.4V

Datasheet

143

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 79

Charge pump

V_S= 4.4 V to 28 V, V_SD= 5.4 V to 29 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current

flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Output voltage VCP vs. V_CPmin1

7.7

-

10.1

V

¹⁾Bridge Driver enabled but not P_12.1.53

VSD

ON; C_CP1=220nF; C_CP2=220nF;

100µA≤I_CP≤6mA; V_VSD=5.4V;

f_CP=250kHz

Single-Stage Mode

Output voltage VCP vs.

VSD

V_CPsingle

10.5 -

12.5

V

¹⁾Bridge Driver enabled but not P_12.1.101

ON, Charge Pump in single-

stage mode; C_CP1=220nF;

C_CP2=220nF; 100µA≤I_CP≤6mA;

V

_VSD=13.5V; f_CP=250kHz

Regulated output

voltage VCP vs. VSD

V_CP

11.8 14.8 16.8

V

¹⁾Bridge Driver enabled but not P_12.1.49

ON; C_CP1=220nF; C_CP2=220nF;

I_CP=6mA; V_SD≥7.4V; f_CP=250kHz

Regulated output

voltage VCP vs. VSD

V_{CP_9V}

7.4 9.4

11.4

90

¹⁾Bridge Driver enabled but not P_12.1.98

ON; C_CP1=220nF; C_CP2=220nF;

I_CP=6mA; V_SD≥7.4V; f_CP=250kHz;

VCP9V_SET=1

^{2) 1) 3)}from CPCLK_EN='1' to 25% P_12.1.59

of V_CP; C_CP1=220nF; C_CP2=220nF;

Turn ON Time

Rise time

t_{ON_VCP}

27

55

-

µs

C_VCP=470nF; V_SD≥7.4V;

f_CP=250kHz

t_{rise_VCP}

130

^{2) 1) 3)}from 25% to 75% of V_CP

C_CP1=220nF; C_CP2=220nF;

;

P_12.1.60

C_VCP=470nF; V_SD≥7.4V;

f_CP=250kHz

1) Ichgx = 63d, Idischgx = 63d, BDRV_CTRL3.DSMONVTH<2:0>=111B

2) This time applies when bit DRV_CP_CLK_CTRL.CPCLK_EN is set

3) Not subject to production test, specified by design

Datasheet

144

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

29.13

Operational Amplifier

29.13.1 Electrical Characteristics

Table 80

Electrical Characteristics Operational Amplifier

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Differential gain

(uncalibrated)

G

9.5 10

19 20

10.5

21

CSA_CTRL.CSA_GAIN<1:0>=00_BP_13.1.6

1)

P_13.1.28

CSA_CTRL.CSA_GAIN<1:0>=01_B

1)

38 40

57 60

42

P_13.1.29

CSA_CTRL.CSA_GAIN<1:0>=10_B

1)

63

P_13.1.30

CSA_CTRL.CSA_GAIN<1:0>=11_B

Differential input

operating voltage range

OP2 - OP1

V_IX

-1.5

/ G

-

1.5 / G V

P_13.1.1

Operating. common

mode input voltage

range (referred to GND

(OP2 - GND) or (OP1 -

GND)

V_CM

-2.0

2.0

7.0

V

P_13.1.2

Max. input voltage

range (referred to GND)

(OP2 - GND) or (OP1 -

GND)

V_{IX_max}

-7.0

-

max. rating of operational

amplifier inputs, where

measurement is not done

P_13.1.3

P_13.1.4

2) 1)

Single ended output

voltage range (linear

range)

V_OUT

V_zero

- 1.5

-

V_zero+ V

1.5

Linearity error

E_LIN

-15

15

mV maximum deviation from best P_13.1.5

fit straight line divided by max.

value of differential output

voltage range (0.5V - 3.5V); this

parameter is determined at G =

40.

Gain drift

ΔG

-1

-

1

-

%

Gain drift after calibration at G = P_13.1.7

40.

DC input voltage

common mode

rejection ratio

DC-CMRR 58 80

dB CMRR (in dB)=-20*log

(differential mode gain/

P_13.1.8

common mode gain); -

2V≤V_CMI≤2V; V_OP2-V_OP1=0V; G=40

Datasheet

145

Rev. 1.0

2019-07-26

TLE9853QX

Electrical Characteristics

Table 80

Electrical Characteristics Operational Amplifier (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Settling time to 98%

T_SET

-

800

1400 ns

¹⁾derived from 80 - 20 % rise fall P_13.1.9

times for ±2V overload

condition (3 Tau value of

settling time constant)

1)

Current Sense Amplifier R_{in_OP1_OP}

1

1.25 1.5

kOh

m

P_13.1.25

InputResistance@ OP1,

2

OP2

1) Not subject to production test, specified by design

2) Nominal V_zero= 2 V (derived from the bandgap voltage: V_zero= 1.652 * V_BG

)

Datasheet

146

Rev. 1.0

2019-07-26

TLE9853QX

Package Outlines

30

Package Outlines

0ꢀ9 MAXꢀ

(0ꢀ65)

11 x 0ꢀ5 = 5ꢀ5

0ꢀ5

0ꢀ1

7

A

0ꢀ03

6ꢀ8

0ꢀ1

+0ꢀ03¹⁾

2)

37

B

36

25

24

48x

0ꢀ08

48

13

1

12

Index Marking

48x

0ꢀ1

0ꢀ4 x 45°

0ꢀ05

Index Marking

0ꢀ23

(0ꢀ35)

M

A B C

(0ꢀ2)

0ꢀ05 MAXꢀ

(5ꢀ2)

(6)

C

1) Vertical burr 0ꢀ03 maxꢀ, all sides

2) These four metal areas have exposed diepad potential

PG-VQFN-48-29, -31-PO V05

Figure 49 VQFN-48-31 (with LTI)

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Datasheet

147

Rev. 1.0

2019-07-26

TLE9853QX

Abbreviations

31

Abbreviations

The following acronyms and terms are used within this document. List see in Table 81.

Table 81

Acronyms

AHB

CCU6

CGU

CLKMU

CMU

CSA

Acronyms

Name

Arm® Advanced High-Performance Bus

Capture Compare Unit 6

Clock Generation Unit

Clock Management Unit

Cyclic Management Unit

Current Sense Amplifier

Data Post Processing

DPP

ECC

Error Correction Code

EEPROM

GPIO

HV

Electrically Erasable Programmable Read Only Memory

General Purpose Input Output

High Voltage

ICU

Interrupt Control Unit

LDO

LIN

Low DropOut voltage regulator

Local Interconnect Network

Least Significant Bit

LSB

LTI

Lead Tip Inspection

LV

Low Voltage

MCU

MF

Memory Control Unit

Measurement Functions

Memory Protection Unit

Master Receive / Slave Transmit, corresponds to MISO in SPI

Most Significant Bit

MPU

MRST

MSB

MTSR

MU

Master Transmit / Slave Receive, corresponds to MOSI in SPI

Measurement Unit

NMI

Non Maskable Interrupt

Nested Vector Interrupt Controller

Oscillator

NVIC

OSC

OTP

PBA

One Time Programmable

Peripheral Bridge

PC

Program Counter

PCU

PD

Power Control Unit

Pull Down

PGU

PLL

Power supply Generation Unit

Phase Locked Loop

Datasheet

148

Rev. 1.0

2019-07-26

TLE9853QX

Abbreviations

Table 81

Acronyms

PMU

PPB

Acronyms

Name

Power Management Unit

Private Peripheral Bus

PSW

PU

Program Status Word

Pull Up

PWM

RAM

Pulse Width Modulation

Random Access Memory

RCU

Reset Control Unit

rfu

reserved for future use

RMU

ROM

SCU

Reset Management Unit

Read Only Memory

System Control Unit

SOW

SPI

Short Open Window (for WDT1)

Serial Peripheral Interface

Synchronous Serial Channel

Arm® Serial Wire Debug

SSC

SWD

TCCR

TMS

Temperature Compensation Control Register

Test Mode Select

TSD

Thermal Shut Down

UART

VBG

Universal Asynchronous Receiver Transmitter

Voltage reference Band Gap

Voltage Controlled Oscillator

Watchdog timer in SCU-DM (System Control Unit - Digital Modules)

Watchdog timer in SCU-PM (System Control Unit - Power Modules)

Wake-up Management Unit

100 Times Programmable

VCO

WDT

WDT1

WMU

100TP

Datasheet

149

Rev. 1.0

2019-07-26

TLE9853QX

Revision History

32

Revision History

Revision Date

Changes

1.0

2019-07-26 Initial version for AD-Step

Datasheet

150

Rev. 1.0

2019-07-26

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2019-07-26

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

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Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

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Document reference

Z8F65189481


型号：	TLE9853QX
厂家：	Infineon
描述：	TLE9853QX is part of the MOTIX™ TLE985x Infineon
文件：	总151页 (文件大小：3881K)
中文：	中文翻译
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