TLF11251LD [INFINEON]
OPTIREG™ PMIC (Automotive);
| 型号： | TLF11251LD |
| 厂家： | 
Infineon |
| 描述： | OPTIREG™ PMIC (Automotive) 集成电源管理电路 |
| 文件： | 总25页 (文件大小：1084K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
Features
•
Integrated PMOS and NMOS complementary output bridge with 2.5 A
current capability
•
•
Integrated gate drivers
Single control input with an integrated dead time logic for optimized
control and high efficiency
•
•
•
•
•
•
Output current sensing
Output current limitation
Overtemperature protection
Low quiescent current
No external dead time adjustment required
Green Product (RoHS compliant)
Potential applications
Companion for the OPTIREG™ PMIC TLF3558xxxx for core voltage regulation of AURIX™ TC3xx microcontroller in:
•
•
•
•
•
Electric power steering
Battery management
Inverter applications
Engine management
Domain control
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
The OPTIREG™ PMIC TLF11251LD is a 2.5 A half bridge with integrated driver and level shifeꢀ. It also contains
a high side P-channel MOSFET and a low side N-channel MOSFET in a single package. The integrated level
shifinꢁ stage allows for conversion of the input logic signals to the supply voltage level of the gate drivers. The
input signal levels are CMOS compatible. The level shifeꢀ and the gate driver provide a dead time generation
to simplify the interface with the embedded core voltage regulator of the AURIX™ TC3xx microcontroller. The
low propagation delay allows for use in closed loop control applications with limited requirements for timing.
The output stage allows for a high switching frequency. The TLF11251LD integrates protection features against
overcurrent at the high side MOSFET and at the low side MOSFET as well as against overtemperature events.
Internal power-on reset releases the digital logic and ensures its operation for the supply voltage within the
specified range.
Datasheet
Please read the sections "Important notice" and "Warnings" at the end of this document
Rev. 1.03
2022-11-25
www.infineon.com/OPTIREG-PMIC
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
Description
Type
Package
Marking
TLF11251LD
PG-TSON-10
11251
Datasheet
2
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
2.1
2.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
4
4.1
4.2
Block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Logical inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional description control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Electrical characteristics control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional description output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical characteristics output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical performance characteristics output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical characteristics undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional description overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical characteristics overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Functional description overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical characteristics overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.2
4.4.2.1
4.4.2.2
4.4.3
4.4.3.1
4.4.3.2
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Datasheet
3
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
Table of contents
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Datasheet
4
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
1 Block diagram
1
Block diagram
Figure 1
Block diagram
Datasheet
5
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
2 Pin configuration
2
Pin configuration
2.1
Pin assignment
SW
SW
10
9
VS
VS
1
2
PGND
VCC
PGND
GND
8
Heat sink
3
4
5
7
LSCON
PWM
6
Figure 2
Pin configuration
Datasheet
6
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
2 Pin configuration
2.2
Pin definitions and functions
Pin
Symbol
Function
1, 2
SW
Switch node:
Half bridge drains; typically connected to the input of the LC filter in buck circuits
3, 8
4
PGND
GND
Power ground:
Half bridge low side source
Ground;
Logical ground
5
LSCON
Bridge control scheme:
Defines the low side state during PWM input "high".
Switch to "high" enables synchronous control of high side and low side, based on PWM
input state.
Switch to "low" disables low side control.
6
7
PWM
Control input:
Input for the logical signal that controls the state of the half bridge transistors. Switch to
"high" opens the high side switch and closes the low side switch. Switch to "low" closes
the high side switch and opens the low side switch.
VCC
VS
Supply voltage input:
Supply voltage for the PWM and LSCON inputs; typically the same as the supply of
microcontroller output pins.
9, 10
–
Supply voltage input:
Supply to gate drivers, connected to half bridge high side source.
Heat sink Connect to heat sink area.
Connect to GND and to PGND.
Datasheet
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Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
3 General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 1
Absolute maximum ratings1)
Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise
specified).
Parameter
Symbol
Values
Unit Note or condition
Number
Min. Typ. Max.
Voltages
Supply voltage VS
Supply voltage VCC
Switch node SW
Input PWM
VS
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
7.0
7.0
7.0
7.0
7.0
V
V
V
V
V
–
–
–
–
–
P_3.1.1
P_3.1.2
P_3.1.3
P_3.1.4
P_3.1.5
Vcc
VSW
VPWM
VLSCON
Input LSCON
Currents
Continuous drain current high
side
IDHS
IDLS
IDHS
IDLS
-2.5
–
–
–
–
–
–
A
A
A
A
PWM = off
P_3.1.6
P_3.1.7
P_3.1.8
P_3.1.9
Continuous drain current low
side
2.5
–
PWM = on
Pulsed drain current high side
-4.4
–
Valid during active
overcurrent protection
Pulsed drain current low side
4.4
Valid during active
overcurrent protection
Temperatures
Junction temperature
Storage temperature
ESD susceptibility
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_3.1.10
P_3.1.11
Tstg
ESD susceptibility all pins
ESD susceptibility all pins
VESD
VESD
-2
–
–
–
2
kV
V
2) HBM
3) CDM
3) CDM
P_3.1.12
P_3.1.13
P_3.1.14
-500
-750
500
750
ESD susceptibility (corner pins) VESD
V
1)
2)
3)
Not subject to production test, specified by design.
Human body model (HBM) robustness according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).
Charged device model (CDM) robustness according to JEDEC JESD22-C101.
Notes:
1.
Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods of time may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the datasheet. Fault conditions are considered as outside the normal operating range. Protection functions
are not designed for continuous repetitive operation.
2.
Datasheet
8
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
3 General product characteristics
3.2
Functional range
Table 2
Functional range
Symbol
Parameter
Values
Typ.
Unit Note or condition Number
Min.
3.5
VCC,nom 2.35
Max.
7.0
Supply voltage range VS
Supply voltage range VCC
VS,nom
–
–
–
V
–
P_3.2.1
P_3.2.2
P_3.2.3
7.0
V
–
1)
Supply voltage VS transient dVS/dt -120
120
V/ms
slew rate
1)
Supply voltage VCC
transient slew rate
dVCC/dt -120
–
120
V/ms
P_3.2.4
Junction temperature
Tj
-40
–
–
–
150
35
°C
–
P_3.2.5
P_3.2.9
Supply current total,
normal operation
IC,norm
mA
PWM input @
1.8 MHz
Supply current total, no
switching
IC,ns
–
200
–
µA
VS < 5.8 V;
Vcc < 5.1 V;
Tj < 85°C
P_3.2.10
1)
Not subject to production test, specified by design.
Note:
Within the functional range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the electrical characteristics table.
Datasheet
9
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
3 General product characteristics
3.3
Thermal resistance
Table 3
Thermal resistance1)
Parameter
Symbol
Values
Typ.
Unit Note or
condition
Number
Min.
RthJCT(HS) 51.6
Max.
57.0
Junction to case top, high side
Junction to case top, low side
–
K/W
K/W
K/W
–
–
–
P_3.3.1
P_3.3.2
P_3.3.3
RthJCT(LS) 64.5
RthJCB(HS) 6.3
–
–
71.2
6.9
Junction to case bottom, high
side
Junction to case bottom, low side RthJCB(LS) 9.4
Junction to ambient RthJA
–
10.4
–
K/W
K/W
–
2)
P_3.3.4
P_3.3.5
–
54.5
1)
2)
Not subject to production test, specified by design.
Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip and
package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with two inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where
applicable, a thermal via array next to the package contacted the first inner copper layer.
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more information
visit www.jedec.org.
Datasheet
10
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4
Block description and electrical characteristics
The device simplifies the interface of microcontroller control outputs to the half bridge.
4.1
Logical inputs
A single PWM input controls the state of the half bridge MOSFETs. The inverted logical scheme translates the
PWM input state to the gate signal shifeꢂ to the output supply level, thus the device switches the high side
MOSFET off during PWM logical on-state, and it switches them on during PWM logical off state. The built-in
dead time control circuitry prevents a shoot-through condition over the MOSFET bridge and improves system
efficiency while used in buck power conversion circuits. No external dead time adjustment is required.
In addition to the PWM input, the LSCON input determines the low side MOSFET control scheme and allows
for both synchronous as well as asynchronous operation in buck converter applications. Logical off state at the
LSCON input switches off the low side MOSFET independently of the PWM input signal, so that the device only
controls the high side MOSFET.
A permanent logical on state at the LSCON input allows both high side and low side operation according to
PWM input state with the internal dead time generation. If such operation is required, then the LSCON input can
be pulled-up or connected directly to the VCC supply rail.
The device interprets a toggling input signal at LSCON as a control request for synchronous low side and
high side MOSFET switching. In this case the device generates dead time internally in accordance with
the PWM input timing. Frequency detection at LSCON inputs detect toggling input signals within the
acceptable range referred to as tdet
.
Table 4
Switching states
LSCON
On
PWM
1) On
2) Off
On
High side MOSFET
Low side MOSFET
Off
On
Off
On
Off
On
Off
On
On
Off
Off
Off
On
Off
On
Off
On
Off
Off
Off
Toggling between on and off3) On
Off
Toggling between on and off On
stopped4)
Off
(< tfil)
Toggling between on and off On
Off
On
Off
On
On
Off
Off
Off
stopped
(> tfil); LSCON: on
Toggling between on and off Off
stopped
(> tfil); LSCON: on
Toggling between on and off On
stopped
(> tfil); LSCON: off
Toggling between on and off Off
stopped
(> tfil); LSCON: off
(table continues...)
Datasheet
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Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
Table 4
LSCON
(continued) Switching states
PWM
High side MOSFET
Low side MOSFET
1)
2)
3)
On: "high"
Off: "low"
Toggling between on and off: The device detects switching on and off at a frequency corresponding to the detection range tdet at
the LSCON input.
Toggling between on and off stopped: Afeꢀ the toggling between on and off, the device detects a permanent on or off state.
4)
The switching states in Table 4 are only valid for device input supplies within the operational range and if no
protection feature is active.
If the PWM pin is not connected, then the integrated weak pull-up ensures a defined level.
If an AURIX™ TC3xx microcontroller controls the device, then place an additional pull-down resistor at the
LSCON input to keep the low side MOSFET switched off during power-down, see Application information.
Datasheet
12
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.2
Control parameters
4.2.1
Functional description control parameters
The device provides a high frequency switching capability with a low propagation delay. The input stage and
the drivers can react to fast changing PWM signals and provide a tres resolution to the on-time of the input
signal with a pulse duration longer than tpulse. The "low" state pulse duration is limited to tpulse, min
.
The total propagation time tprop is the time from the "low" to "high" edge transition or from the "high"
to "low" edge transition at the PWM input to the SW output level transitions to 10% or 90% of VS supply
level accordingly. The internal dead time generation provides optimal efficiency during switching phases and
performs the state change of the switching node SW within the specified propagation delay.
The device is optimized for a switching frequency in a buck converter application from 0.3 MHz to 2 MHz.
PWM Input
Test circuit
Vs
VIH
tpulse
Min accepted pulse:
tpulse,min=65ns
VIL
15..25 Ohm
15..25 Ohm
PWM
SW
DUT
SW output
GND
PGND
tprop,fe
0.9*Vs
tpulse ± |tres|
tprop,re
0.1*Vs
Figure 3
Control timing diagram
Datasheet
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Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.2.2
Electrical characteristics control parameters
Table 5
Electrical characteristics control parameters
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Typ.
–
Unit Note or condition
Number
Min.
Max.
60
Propagation time, PWM
falling edge
tprop,fe
–
ns
ns
ns
High side drain
connected to
resistive load;
VCC > 3.0 V;
VS > 4.5 V
P_4.2.1
Propagation time, PWM
rising edge
tprop,re
–
–
–
60
–
Low side drain
connected to
resistive load;
VCC > 3.0 V;
VS > 4.5 V
1)
P_4.2.2
P_4.2.3
Minimum pulse width input tpulse,
65
min
1)
1)
1)
Pulse resolution time
tres
–
–
–
–
3
–
–
–
ns
ns
ns
P_4.2.4
P_4.2.5
P_4.2.6
P_4.2.7
Dead time "high" to "low"
Dead time "low" to "high"
tdead,hl
tdead,lh
15
18
–
LSCON frequency detector
frequency range
fdet,lscon 0.72
MHz –
1)
LSCON frequency detector
filter time
tfil,lscon
3
–
–
µs
P_4.2.8
Logic inputs
Input voltage "high"
Input voltage "low"
Input voltage hysteresis
Input capacitance
VIH
0.67 × Vcc
–
–
V
CMOS function
P_4.2.9
VIL
–
–
0.33 × Vcc
V
CMOS function
P_4.2.10
P_4.2.11
P_4.2.12
VIHYS
CIN
0.05
–
–
–
–
V
–
1)
10
pF
1)
Not subject to production test, specified by design.
Datasheet
14
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.3
Output stage
4.3.1
Functional description output stage
The P-N-channel output half bridge of the device can operate at a switching frequency up to 2 MHz nominal
range, providing very low power dissipation in synchronous buck converter topology. The P-channel MOSFET
used as high side switch eliminates the need for a charge pump circuitry and improves the EMI performance.
The output stage delivers a minimum output current of 2.5 A within the specified voltage and temperature
range.
4.3.2
Electrical characteristics output stage
Table 6
Electrical characteristics output stage
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or
condition
Number
Min.
Max.
100
On-state resistance high side RONHS
–
–
–
–
–
mΩ
mΩ
mΩ
mΩ
Tj ≤ 150°C;
Id = -2 A;
Vs = 5.8 V
1) Tj ≤ 85°C;
Id = -2 A;
Vs = 5.8 V
P_4.3.1
–
–
–
70
P_4.3.2
P_4.3.3
P_4.3.4
On-state resistance low side RONLS
105
75
Tj ≤ 150°C;
Id = 2 A;
Vs = 5.8 V
1) Tj ≤ 85°C;
Id = 2 A;
Vs = 5.8 V
Body diode forward voltage VDFHS
–
–
0.67
0.72
0.95
0.91
V
V
Ifw = 2 A
P_4.3.5
P_4.3.6
high side
Body diode forward voltage VDFLS
low side
Ifw = 2 A
1)
Not subject to production test, specified by design.
Datasheet
15
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.3.3
Typical performance characteristics output stage
Maximum on-state resistance high side RONHS
(PWM = "low") versus Tj = -40°C, 25°C, 150°C
Maximum on-state resistance low side RONLS
(PWM = "high") versus Tj = -40°C, 25°C, 150°C
Datasheet
16
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.4
Protection functions
The following integrated protection functions prevent the device and the output circuitry from destruction as
well as from operation under unspecified conditions:
•
•
•
High side and low side overcurrent detection and limitation
Undervoltage shutdown
Overtemperature protection
The device reacts within the time specified for each protection feature. This is related to the state change of the
half bridge MOSFETs independent from the PWM input signal. The device performs the input logic reset release
at VS voltage exceeding the minimum functional limit of 3.5 V, where protection functions are also operational.
For the VCC voltage below VCCUV, the output half bridge MOSFETs remain in the off-state and the output switch
node SW is floating.
4.4.1
Undervoltage shutdown
4.4.1.1
Functional description undervoltage shutdown
The device monitors the input supply VCC for undervoltage conditions. If the output voltage drops below the
Vccuv limit, then the device switches off the high side MOSFET and the low side MOSFET, so that the device is
only operational within the specified supply limits. The voltage hysteresis circuitry Vccuvh protects from noise
conditions.
4.4.1.2
Electrical characteristics undervoltage shutdown
Table 7
Electrical characteristics undervoltage shutdown
VS = 3.5 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless
otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or
condition
Number
Min.
1.95
Max.
2.28
Undervoltage limit at VCC
supply
Vccuv
Vccuvh
Vuvr
–
V
VCC falling
P_4.4.2.1
P_4.4.2.2
P_4.4.2.3
Undervoltage detector
hysteresis
0.05
–
–
–
0.1
3
V
–
1)
Undervoltage detector
reaction time
µs
1)
Not subject to production test, specified by design.
Datasheet
17
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.4.2
Overcurrent protection
4.4.2.1
Functional description overcurrent protection
The overcurrent protection works in a cycle-by-cycle limitation mode. If the sensed input drain current exceeds
the peak current limit Ioc, lim during a switching cycle, then the device switches off the high side MOSFET and
the switch node SW current decreases. If the overcurrent protection circuitry is active, then the device limits the
PWM input duty cycle for each cycle.
During startup or with VCC supply power cycle afeꢀ the logic reset is released, the overcurrent protection
remains inactive for the number of PWM pulses npwm,st to avoid accidental activation due to startup current
overshoot.
Figure 4
Overcurrent protection example
Datasheet
18
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.4.2.2
Electrical characteristics overcurrent protection
Table 8
Electrical characteristics overcurrent protection
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or
condition
Number
Min.
-4.4
Max.
-2.6
5500
Overcurrent sensing limit
Ioc, lim
–
A
–
–
P_4.4.3.1
Startup protection inactive, npwm,st
number of PWM pulses
–
–
VCC rising above P_4.4.3.2
VCC,min
Datasheet
19
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
4 Block description and electrical characteristics
4.4.3
Overtemperature protection
4.4.3.1
Functional description overtemperature protection
If an overtemperature condition TjOT occurs, then the integrated temperature sensor disables the device by
switching off the high side and low side MOSFETs. Only if both the temperature decreases by the hysteresis
temperature dTj and the temperature falls below TjSO, then the MOSFETs resume operation.
4.4.3.2
Electrical characteristics overtemperature protection
Table 9
Electrical characteristics overtemperature protection1)
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or
condition
Number
Min.
175
Max.
200
Overtemperature shutdown TjOT
Switch-on temperature TjSO
–
°C
°C
°C
–
–
–
P_4.4.4.1
P_4.4.4.2
P_4.4.4.3
–
–
–
165
–
Overtemperature switch-on dTj
hysteresis
15
1)
Not subject to production test, specified by design.
Datasheet
20
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
5 Application information
5
Application information
Note:
The following information is given as an example for the implementation of the device only and shall
not be regarded as a description or warranty of a certain functionality, condition or quality of the
device.
5.1
Application diagram
In the target application scenario the device is the counterpart for an AURIX™ TC3xx microcontroller for core
voltage generation with the system power supply TLF35584. The device configuration allows connectivity with
the half bridge control output of the microcontroller’s embedded voltage regulator core (EVRC) converter,
which generates the core voltage Vdd. The device only supports power supply topologies that use ꢂiffeꢀent
sources for the microcontroller supply domain Vext and the EVRC input VS, expecting ꢂiffeꢀent voltage levels. VS
must exceed VCC during startup, in normal operation and during power-down.
Figure 5
Application diagram
Note:
This figure is a simplified example of an application circuit. The function must be verified in the
application.
As soon as VS voltage reaches 3.5 V during power-up, the device releases the internal logic reset. During this
phase the central function logic is operational. Only if VCC is within the specified range, then the device reacts
to the input signals LSCON and PWM as specified. However, the operational VCC voltage minimum is specified at
2.35 V, which allows for early device readiness, even if the microcontroller is not yet operational.
The VGATEP output of the microcontroller controls the PWM signal, while the VGATEN output is connected
to LSCON. The microcontroller typically starts in an open loop mode, controlling only VGATEP and allowing
for fast Vdd voltage ramp-up and startup. Afeꢀ ramp-up time, the EVRC starts to control the high side and
low side MOSFETs of the half bridge. The LSCON input detects this phase with the frequency detector. If the
microcontroller is switched into power-down mode and if the high side and low side control signals are off,
Datasheet
21
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
5 Application information
then the frequency detector recognizes it as a request to set the SW output floating. Therefore add a pull-down
resistor for the LSCON signal in order to limit its possible variation during the power-down phase afeꢀ the
supply voltage reaches the hard reset limit of the microcontroller.
Figure 6
Start-up and ramp-down example
Table 10 shows the required nominal values of the discrete components for proper operation.
Table 10
Nominal values of discrete components
Component name
Nominal value
10 µF
Acceptable variation
Note
CVS
30%
Input capacitor
Output capacitor
Output inductor
LSCON input pull-down
CVDD
LVDD
RLSCON
22 µF
30%
3.3 µH
30% (@ 1.8 MHz)
20%
6.2 kΩ
Datasheet
22
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
6 Package information
6
Package information
0.36±0.1
1±0.1
2.58±0.1
3.3±0.1
0.05
0.5
INDEX MARKING
0.53±0.1
INDEX MARKING
0.07 MIN.
0.25±0.1
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 7
PG-TSON-10
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a Green Product. Green Products are RoHS compliant
(Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Information on alternative packages
Please visit www.infineon.com/packages.
Datasheet
23
Rev. 1.03
2022-11-25
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifte
Revision history
Revision history
Revision Date
Changes
1.03
2022-11-25
Editorial changes
1.02
1.01
1.0
2021-02-05
2021-01-14
2020-01-23
Editorial changes
Editorial changes
Datasheet created
Datasheet
24
Rev. 1.03
2022-11-25
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2022-11-25
Published by
Infineon Technologies AG
81726 Munich, Germany
Important notice
Warnings
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsꢁaꢀantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer’s compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer’s products and any use of the product of
Infineon Technologies in customer’s applications.
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dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or
any consequences of the use thereof can reasonably
be expected to result in personal injury.
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2022 Infineon Technologies AG
All Rights Reserved.
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Email: erratum@infineon.com
Document reference
IFX-Z8F80033844
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments to
evaluate the suitability of the product for the intended
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application.
相关型号：
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current sensing, current & temperture reporting, over-current protection & flag, over-temperature protection & shutdown, high-side short detection & flag, bootstrap under-voltage protection, VDRV under-voltage lockout, 3.3V tri-state PWM-input, auto-sleep- & deep-sleep-mode
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