TLF35584QKVS2 [INFINEON]
如需数据表和进一步帮助，请联系您的销售代表或技术援助中心 (TAC) 前/后稳压器概念：升压和降压/ LDO和跟踪器 功能安全集成 (功能支持 ASIL-D) 动力系统 xEV 底盘/安全 Access to complete OPTIREG™ PMIC technical documentation including data sheets, app notes, etc.: 1. To get access to the full technical documentation you need access to the MyInfineon Collaboration Portal 2. Please register* under myinfineon.com with your company e-mail address and with this, request access to the MyInfineon Collaboration Portal. (*If you are already registered at myinfineon.com, follow the guideline from page 6.) Click here to see the step-by-step instructions to get registered. 3. In case you need further assistance, please fill in the form to our Technical Assistance Center or contact support@infineon.com ;
| 型号： | TLF35584QKVS2 |
| 厂家： | 
Infineon |
| 描述： | 如需数据表和进一步帮助，请联系您的销售代表或技术援助中心 (TAC) 前/后稳压器概念：升压和降压/ LDO和跟踪器 功能安全集成 (功能支持 ASIL-D) 动力系统 xEV 底盘/安全 Access to complete OPTIREG™ PMIC technical documentation including data sheets, app notes, etc.: 1. To get access to the full technical documentation you need access to the MyInfineon Collaboration Portal 2. Please register* under myinfineon.com with your company e-mail address and with this, request access to the MyInfineon Collaboration Portal. (*If you are already registered at myinfineon.com, follow the guideline from page 6.) Click here to see the step-by-step instructions to get registered. 3. In case you need further assistance, please fill in the form to our Technical Assistance Center or contact support@infineon.com 集成电源管理电路 稳压器 |
| 文件： | 总7页 (文件大小：690K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
OPTIREG PMIC TLF35584
Functional Safety PMIC
Features
•
•
High efficient power management integrated circuit (PMIC)
Serial step up and step down pre regulator for wide input voltage range
from 3.0 to 40 V with full performance and low over all power loss
•
•
Low drop post regulator 5.0 V/200 mA for communication supply (QCO)
Low drop post regulator 5.0 V/600 mA (TLF35584QxVS1) or 3.3 V/600 mA
(TLF35584QxVS2) for µC supply (QUC)
•
•
Voltage reference 5.0 V ±1% for ADC supply, 150 mA current capability (QVR)
Two trackers for sensor supply following voltage reference 150 mA current
capability each (QT1 and QT2)
•
•
Standby regulator 5.0 V/10 mA (TLF35584QxVS1) or 3.3 V/10 mA
(TLF35584QxVS2) (QST)
Provides enable, sync out signal and voltage monitoring for an optional
external post regulator for core supply
•
•
•
•
•
Independent voltage monitoring block and error pin monitoring
Configurable window and functional watchdog
Safe State Control with two safe state signals with programmable delay
16-bit SPI, interrupt and reset function
PRO-SIL™ Features:
-
-
ISO 26262 compliant supporting up to ASIL-D
Safety Documentation (Safety Manual & Safety Analysis Summary
Report)
•
Green Product (RoHS compliant)
Potential applications
•
•
•
•
•
•
Electric Power Steering
Battery Management
Inverter
Transmission
Engine Management
Domain Control
Product validation
Qualified for Automotive Applications.
Product validation according to AEC-Q100/101.
Device Overview
Please read the Important Notice and Warnings at the end of this document
Rev 1.0
www.infineon.com/OPTIREG-PMIC
2019-03-25
™
OPTIREG PMIC TLF35584
Functional Safety PMIC
Description
Description
The OPTIREG™ PMIC TLF35584 is a high efficient Functional Safety PMIC (Power Management Integrated Circuit).
Type
Package
TLF35584QVVS1 (5.0 V Variant)
TLF35584QVVS2 (3.3 V Variant)
TLF35584QKVS1 (5.0 V Variant)
TLF35584QKVS2 (3.3 V Variant)
PG-VQFN-48
PG-VQFN-48
PG-LQFP-64
PG-LQFP-64
Application Example
LDO_Stby
3.3V (5.0V)
(as LDO_µC)
VST
QST
3.3V/5.0V
V_STBY
WakeUp Timer
ENA
FRE
STU
Set fSTEPDOWN high/low by FRE: open/GND
Set STEPUP usage yes/no by STU: open/GND
ENABLE (KL 15)
WAKE/INH
ENABLE
Logic
WAK
Comparator
(PG-LQFP-64 only)
VS2
VS1
V_Bat (KL30)
Internal Supply
and Clock
Feedback
DRG
RSH
SW1
Step down-
Regulator
Step Up-
Regulator
V_PREREG
BSG
RSL
SW2
(PG-LQFP-64 only)
PG1
PG2
Feedback
Bandgap 1 for
Regulators
External
switchmode
post
regulator
(optional)
FB1
V_Core
For µC
core supply
FB2
V_LDO_µC
FB3 (PG-LQFP-64 only)
FB4 (PG-LQFP-64 only)
Bandgap 2
for Voltage Mon.
SYN
EVC
Sync_Out
Enable ext.Core sup
Sync
Feedback
Enable
Voltage
Monitoring/
Reset Function
Reset Output
ROT
SEC
VCI
Set ext SMPR yes/no by
SEC: open/GND
Reset Control
QUC
3.3V/5.0V
V_LDO_µC
For µC supply
INTERRUPT
INT
SCS
INTERRUPT
Generator
LDO_µC
3.3V (5.0V)
SQUC (PG-LQFP-64 only)
QCO
CHIP SELECT
CLOCK
5.0V
5.0V
LDO_Com
5.0V
V_LDO_Com
For communication supply (CAN/FlexRay)
SCL
SDI
SPI
DATA_IN
SPI
QT1
V_TR1
For sensor supply
DATA_OUT
SDO
Tracker 1
5.0V
µC
SQT1 (PG-LQFP-64 only)
QT2
5.0V
5.0V
V_TR2
For sensor supply
Tracker 2
5.0V
Trigger
Window
-
Watchdog
Functional
-
Watchdog
WDI
SQT2 (PG-LQFP-64 only)
QVR
Series
Protection
resistors
Volt_Ref.
5.0V
V_Volt_Ref
Safe State
Control
/ErrorPin
ERR
Error
Monitoring
SMU
MPS
SS1
SS2
Driver
Driver
Safe State 1
TLF35584
AG4
(PG-LQFP-64
only)
Safe State 2
(signal delayed)
3.3V
(5V)
e.g. 1.3V
V_LDO_µC
V_Core
Note:
The following information is given as an example for the implementation of the device only and shall
not be regarded as a description or warranty of a certain functionality, condition or quality of the
device.
•
•
Please contact us for additional supportive documentation.
For further information you may contact http://www.infineon.com/OPTIREG-PMIC
Note:
This figure is a very simplyfied example on an application circuit. The function must be verified in the
real application.
Device Overview
2
Rev 1.0
2019-03-25
™
OPTIREG PMIC TLF35584
Functional Safety PMIC
1 Absolute maximum ratings
1
Absolute maximum ratings
Table 1
Absolute maximum ratings2)
Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Typ.
Unit
Note or condition
Min.
Max.
Voltages
Boost driver ground
Input standby LDO
VBSG
VVST
-0.3
–
0.3
V
V
V
V
V
V
–
3)4)
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
40
40
40
40
40
Input voltage pin 1 (pre regulator) VVS1
Input voltage pin 2 (pre regulator) VVS2
External step up power stage, gate VDRG
–
PG-LQFP-64 only
–
–
External power stage, sense
resistor high
VRSH
External power stage, sense
resistor low
VRSL
-0.3
–
6.0
V
–
Enable input
VENA
IENA
-0.3
-5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
V
–
5)
Enable input
–
mA
V
Wake input
VWAK
IWAK
VROT
VSCS
VSCL
VSDI
-0.3
-5
40
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Wake input
–
mA
V
Reset output
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-1.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
40
SPI chip select input
SPI clock input
V
V
SPI data in (MOSI) input
SPI data out (MISO output)
Interrupt output
V
VSDO
VINT
VWDI
VERR
VSS1
VSS2
VQVR
VQT2
V
V
Window watchdog trigger input
Error pin input
V
V
Safe state 1 output
Safe state 2 output
Output voltage reference LDO
Output tracker 2
V
V
V
V
2
Not subject to production test, specified by design.
Maximum rating is 60 V, if rise time from 0 to 60 V is longer than 10 ms
Maximum rating is 49 V, for an overall time of 10 s (in the range of 40 V to 49 V) during the lifetime of the
product independent from the rise time.
3
4
5
Consider external series resistor for negative voltages < -0.3 V to ensure maximum rating of current
Device Overview
3
Rev 1.0
2019-03-25
™
OPTIREG PMIC TLF35584
Functional Safety PMIC
1 Absolute maximum ratings
Table 1
Absolute maximum ratings2) (continued)
Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Typ.
Unit
Note or condition
Min.
-0.3
Max.
40
Sense Pin for tracker 2
Output tracker 1
VSQT2
VQT1
–
V
V
V
V
V
V
V
PG-LQFP-64 only
-1.0
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
–
40
–
Sense Pin for tracker 1
Output communication LDO
Output microcontroller LDO
VSQT1
VQCO
VQUC
40
PG-LQFP-64 only
6.0
6.0
6.0
6.0
–
–
Sense Pin for microcontroller LDO VSQUC
PG-LQFP-64 only
–
External core voltage monitor
input
VVCI
VSEC
VSYN
HW config: ext. core voltage
monitor
-0.3
–
6.0
V
–
Synchronization output
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6.0
6.0
7.0
7.0
7.0
7.0
0.3
0.3
40
V
V
V
V
V
V
V
V
V
V
V
V
V
V
–
Enable output for ext. core supply VEVC
–
Step down feedback input 4
Step down feedback input 3
Step down feedback input 2
Step down feedback input 1
Step down power ground 2
Step down power ground 1
Step down switching node 2
Step down switching node 1
HW config: step up pre regulator
HW config: step down frequency
Output standby LDO
VFB4
VFB3
VFB2
VFB1
VPG2
VPG1
VSW2
VSW1
VSTU
VFRE
VQST
VMPS
PG-LQFP-64 only
PG-LQFP-64 only
–
–
–
–
PG-LQFP-64 only
40
–
–
–
–
–
6.0
6.0
6.0
6.0
Input MPS
Temperatures
Junction temperature
Tj
-40
-55
–
–
150
150
°C
°C
–
–
Storage temperature
Tstg
ESD susceptibility
ESD susceptibility to GND
VESD
-2
–
2
kV
HBM6)
2
Not subject to production test, specified by design.
ESD susceptibility, HBM according to JEDEC HBM Human Body Model ANSI/ESDA/JEDEC JS001 (1.5 kΩ,
100 pF)
6
Device Overview
4
Rev 1.0
2019-03-25
™
OPTIREG PMIC TLF35584
Functional Safety PMIC
1 Absolute maximum ratings
Table 1
Absolute maximum ratings2) (continued)
Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Typ.
Unit
Note or condition
Min.
-500
-750
Max.
500
750
ESD susceptibility to GND
VESD
–
V
V
CDM7)
CDM
ESD susceptibility (corner pins) to VESD,Corner
–
GND
2
Not subject to production test, specified by design.
ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
7
Device Overview
5
Rev 1.0
2019-03-25
™
OPTIREG PMIC TLF35584
Functional Safety PMIC
2 Package information 8)
8
Dimensions in mm
2
Package information 8)
C
0.08
48x
7±0.1
(6.8)
SEATING COPLANARITY
A
PLANE
B
0.5±0.07
0.1±0.05
2)
1)
36
25
37
24
48
13
INDEX MARKING
1
12
INDEX MARKING
0.1±0.03
48x
0.5
0.4 x 45°
0.9 MAX.
0.23±0.05
0.1
A B C
3)
5.2±0.1
1) VERTICAL BURR 0.03 MAX. AT ALL SIDES
2) THESE FOUR METAL AREAS HAVE EXPOSED DIEPAD POTENTIAL
3) EXCLUDE MOLD RESIDUES
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 1
PG-VQFN-48 package outline
Z VIEW
H
Z
C
0.6±0.15
12
SEATING
1)
0.2 A-B D 64x
0.2 A-B H 4x
PLANE
0.08 C 64x
COPLANARITY
BOTTOM VIEW
10
D
EXPOSED
DIEPAD
D
A
B
64
64
1
1
Ax
0.2+-00..0037
0.5
INDEX
MARKING
Ex
0.08
A-B D C
64x
AVAIL. EXPOSED
DIEPAD SIZE
Ex Ey
By
Ax
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.25 MAX. PER SIDE
6.3 6.3 5.3 5.3
6.0 6.0 5.0 5.0
4.5 4.5 3.5 3.5
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 2
PG-LQFP-64 package outline
8
Dimensions in mm
Device Overview
6
Rev 1.0
2019-03-25
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-03-25
Published by
IMPORTANT NOTICE
WARNINGS
The information contained in this application note is
given as a hint for the implementation of the product
only and shall in no event be regarded as a description
or warranty of a certain functionality, condition or
quality of the product. Before implementation of the
product, the recipient of this application note must
verify any function and other technical information
given herein in the real application. Infineon
Technologies hereby disclaims any and all warranties
and liabilities of any kind (including without limitation
warranties of non-infringement of intellectual property
rights of any third party) with respect to any and all
information given in this application note.
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or
any consequences of the use thereof can reasonably
be expected to result in personal injury
Infineon Technologies AG
81726 Munich, Germany
©
2019 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to such
application.
Document reference
IFX-jmv1546509847065
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如需数据表和进一步帮助，请联系您的销售代表或技术援助中心 (TAC) Access to complete OPTIREG™ PMIC technical documentation including data sheets, app notes, etc.: 1. To get access to the full technical documentation you need access to the MyInfineon Collaboration Portal 2. Please register* under myinfineon.com with your company e-mail address and with this, request access to the MyInfineon Collaboration Portal. (*If you are already registered at myinfineon.com, follow the guideline from page 6.) Click here to see the step-by-step instructions to get registered. 3. In case you need further assistance, please fill in the form to our Technical Assistance Center or contact support@infineon.com
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如需数据表和进一步帮助，请联系您的销售代表或技术援助中心 (TAC) Access to complete OPTIREG™ PMIC technical documentation including data sheets, app notes, etc.: 1. To get access to the full technical documentation you need access to the MyInfineon Collaboration Portal 2. Please register* under myinfineon.com with your company e-mail address and with this, request access to the MyInfineon Collaboration Portal. (*If you are already registered at myinfineon.com, follow the guideline from page 6.) Click here to see the step-by-step instructions to get registered. 3. In case you need further assistance, please fill in the form to our Technical Assistance Center or contact support@infineon.com
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