TLS203B0EJ V50_技术文档

TLS203B0 V50

Linear Voltage Post Regulator

Low Dropout, Low Noise, 5V, 300mA

TLS203B0EJV50

TLS203B0LDV50

Data Sheet

Rev. 1.1, 2015-01-15

Automotive Power

Linear Voltage Post Regulator

Low Dropout, Low Noise, 5V, 300mA

TLS203B0EJV50

TLS203B0LDV50

1

Overview

Features

•

Low Noise down to 42 µV_RMS(BW = 10 Hz to 100 kHz)

300 mA Current Capability

Low Quiescent Current: 30 µA

Wide Input Voltage Range up to 20 V

Internal circuitry working down to 2.3 V

2.5% Output Voltage Accuracy (over full temperature and load range)

Low Dropout Voltage: 290 mV

Very low Shutdown Current: < 1 µA

No Protection Diodes needed

Fixed Output Voltage: 5.0 V

PG-DSO-8 Exposed Pad

Stable with ≥ 3.3 µF Output Capacitor

Stable with Aluminium, Tantalum or Ceramic Output Capacitors

Reverse Polarity Protection

No Reverse Current

Overcurrent and Overtemperature Protected

PG-DSO-8 Exposed Pad and PG-TSON-10 Exposed Pad Package

Suitable for use in Automotive Electronics as Post Regulator

Green Product (RoHS compliant)

PG-TSON-10

AEC Qualified

The TLS203B0 V50 is a micropower, low noise, low dropout voltage 5 V regulator. The device is capable of

supplying an output current of 300 mA with a dropout voltage of 290 mV. Designed for use in battery-powered

systems, the low quiescent current of 30 µA makes it an ideal choice.

A key feature of the TLS203B0 V50 is its low output noise. By adding an external 10 nF bypass capacitor output

noise values down to 42 µV_RMSover a 10 Hz to 100 kHz bandwidth can be reached. The TLS203B0 V50 voltage

regulator is stable with output capacitors as small as 3.3 µF. Small ceramic capacitors can be used without the

series resistance required by many other linear voltage regulators.

Internal protection circuitry includes reverse battery protection, current limiting and reverse current protection. The

TLS203B0 V50 comes as 5.0 V fixed output voltage variant and is available in a PG-DSO-8 Exposed Pad as well

as in a PG-TSON-10 Exposed Pad package.

Type

Package

Marking

203B0V50

203B0V5

TLS203B0EJV50

TLS203B0LDV50

PG-DSO-8 Exposed Pad

PG-TSON-10

Data Sheet

2

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Block Diagram

2

Block Diagram

Note: Pin numbers in block diagrams refer to the PG-DSO-8 Exposed Pad package type.

Saturation

Control

TLS203B0

I

8

5

1

Q

Over Current

Protection

Temperature

Protection

EN

Bias

Voltage

reference

4

BYP

Error

Amplifier

2

SENSE

6

GND

Figure 1

Block Diagram TLS203B0 V50

Data Sheet

3

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

1

2

8

7

Q

I

SENSE

NC

3

4

6

5

GND

EN

9

BYP

TLS203B0EJV50

Figure 2

Pin Configuration of TLS203B0EJV50 in PG-DSO-8 Exposed Pad

Q

1

2

3

4

5

10

9

I

NC

8

NC

EN

GND

SENSE

BYP

7

11

6

TLS203B0LDV50

Figure 3

Pin Configuration of TLS203B0LDV50 in PG-TSON-10

Data Sheet

4

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Pin Configuration

3.2

Pin Definitions and Functions

Symbol

Function

1 (DSO-8 EP)

1,2 (TSON-10)

Q

Output. Supplies power to the load. For this pin a minimum output capacitor of

3.3 µF is required to prevent oscillations. Larger output capacitors may be

required for applications with large transient loads in order to limit peak voltage

transients or when the regulator is applied in conjunction with a bypass capacitor.

For more details please refer to “Application Information” on Page 19.

2 (DSO-8 EP)

4 (TSON-10)

SENSE

Output Sense. The SENSE pin is the input to the error amplifier. This allows to

achieve an optimized regulation performance in case of small voltage drops R_p

that occur between regulator and load. In applications where such drops are

relevant they can be eliminated by connecting the SENSE pin directly at the load.

In standard configuration the SENSE pin can be directly connected to Q. For

further details please refer to the section “Kelvin Sense Connection” on

Page 19.

3, 7 (DSO-8 EP) NC

3, 8 (TSON-10)

No Connect. The NC Pins have no connection to any internal circuitry. Connect

either to GND or leave open.

4 (DSO-8 EP)

5 (TSON-10)

BYP

Bypass. The BYP pin is used to bypass the reference of the TLS203B0 V50 to

achieve low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e.

one V_BE). A small capacitor from the output Q to the BYP pin will bypass the

reference to lower the output voltage noise ¹⁾. If not used this pin must be left

unconnected.

5 (DSO-8 EP)

7 (TSON-10)

EN

Enable. With the EN pin the TLS203B0 V50 can be put into a low power shutdown

state. The output will be off when the EN is pulled low. The EN pin can be driven

either by 3.3 V or 5 V logic or as well by open-collector logic with pull-up resistor.

The pull-up resistor is required to supply the pull-up current of the open-collector

gate ²⁾and the EN pin current ³⁾. Please note that if the EN pin is not used it must

be connected to V_I. It must not be left floating.

6 (DSO-8 EP)

6 (TSON-10)

GND

I

Ground.

8 (DSO-8 EP)

Input. The device is supplied by the input pin I. A capacitor at the input pin is

required if the device is more than 6 inches away from the main input filter

capacitor or if a non-negligible inductance is present at the input I ⁴⁾. The

TLS203B0 V50 is designed to withstand reverse voltages on the input pin I with

respect to GND and output Q. In the case of reverse input (e.g. due to a wrongly

attached battery) the device will act as if there is a diode in series with its input. In

this way there will be no reverse current flowing into the regulator and no reverse

voltage will appear at the load. Hence, the device will protect both - the device

itself and the load.

9, 10 (TSON-10)

9 (DSO-8 EP)

11 (TSON-10)

Tab

Exposed Pad. To ensure proper thermal performance, solder Pin 11 of TSON-10

to the PCB ground and tie directly to Pin 6. In the case of DSO-8 EP as well solder

Pin 9 (exposed pad) to the PCB ground and tie directly to Pin 6 (GND).

1) A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz.

2) Normally several microamperes.

3) Typical value is 1 µA.

4) In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-

powered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient.

Data Sheet

5

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings ¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise

specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Input Voltage

Voltage

V_I

-20

–

20

V

–

P_4.1.1

Output Voltage

Voltage

V_Q

-20

–

20

V

–

P_4.1.2

P_4.1.3

Input to Output Differential Voltage V_I- V_Q

Sense Pin

Voltage

V_SENSE

V_BYP

V_EN

-20

-0.6

-20

–

20

0.6

20

V

–

P_4.1.4

P_4.1.5

P_4.1.6

BYP Pin

Voltage

Enable Pin

Voltage

–

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

All Pins

T_j

-40

-55

–

150

°C

–

P_4.1.7

P_4.1.8

T_stg

V_ESD

-2

-1

–

2

1

kV

HBM ²⁾

CDM ³⁾

P_4.1.9

All Pins

P_4.1.10

1) Not subject to production testing, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Data Sheet

6

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

Parameter

Symbol

Values

Unit Note / Test Condition Number

Min.

5.5

Typ.

Max.

20

Input Voltage Range

V_I

–

V

–

P_4.2.1

P_4.2.2

OutputCapacitor’sRequirements C_Q

3.3

–

µF

C

_BYP= 0 nF ¹⁾

for Stability

OutputCapacitor’sRequirements C_Q

6.8

–

µF

0 nF < C_BYP≤ 10 nF ¹⁾P_4.2.3

for Stability

2)

1)

ESR

–

3

Ω

–

P_4.2.4

P_4.2.5

Operating Junction Temperature T_j

1) for further details see corresponding graph.

-40

125

°C

2) C_BYP= 0 nF, C_Q≥ 3.3 µF; please note that for cases where a bypass capacitor at BYP is used – depending on the actual

applied capacitance of C_Qand C_BYPa minimum requirement for ESR of C_Qmay apply.

Note:Within the functional or operating range, the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the Electrical Characteristics table.

4.3

Thermal Resistance

Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance ¹⁾

Symbol

Parameter

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

Max.

TLS203B0EJV50 (PG-DSO-8 Exposed Pad)

Junction to Case

R_thJC

R_thJA

–

7.0

39

–

K/W

–

P_4.3.1

P_4.3.2

P_4.3.3

2)

Junction to Ambient

–

155

66

Footprint only ³⁾

300 mm²heatsink P_4.3.4

area on PCB ³⁾

Junction to Ambient

R_thJA

–

52

–

K/W

600 mm²heatsink P_4.3.5

area on PCB ³⁾

TLS203B0LDV50 (PG-TSON-10)

Junction to Case

R_thJC

R_thJA

–

6.4

53

–

K/W

–

P_4.3.6

P_4.3.7

P_4.3.8

2)

Junction to Ambient

183

69

Footprint only ³⁾

300 mm²heatsink P_4.3.9

area on PCB ³⁾

Junction to Ambient

R_thJA

–

57

7

–

K/W

600 mm²heatsink P_4.3.10

area on PCB ³⁾

1) Not subject to production test, specified by design.

Data Sheet

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

General Product Characteristics

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70 µm Cu).

Data Sheet

8

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

5

Electrical Characteristics

Table 4

Electrical Characteristics

-40 °C < T_j< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless

otherwise specified.

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Number

Min.

Max.

2.3

Minimum Operating Voltage ¹⁾

Minimum Operating Voltage

Output Voltage ²⁾

V_I,min

V_Q

–

1.8

V

I_Q= 300 mA

P_5.0.1

P_5.0.2

Output Voltage

4.875 5.00

5.125

1mA < I_Q< 300 mA ;

6 V < V_I< 20 V

Line Regulation

∆V_Q

–

1

25

mV

ꢀV_I= 5.5 V to 20 V ;

I_Q= 1 mA

P_5.0.3

Load Regulation

∆V_Q

–

8

–

22

43

mV

T_J= 25 °C ; V_I= 6.0 V ;

∆I_Q= 1 to 300 mA

P_5.0.4

P_5.0.5

Load Regulation

V_I= 6.0 V ;

∆I_Q= 1 to 300 mA

Dropout Voltage ³⁾

Dropout Voltage

V_DR

–

130

190

mV

I_Q= 10 mA ; V_I= V_Q,nom

T_J= 25 °C

;

P_5.0.6

Dropout Voltage

V_DR

–

250

220

mV

I_Q= 10 mA ; V_I= V_Q,nom

P_5.0.7

P_5.0.8

170

I_Q= 50 mA ; V_I= V_Q,nom

T_J= 25 °C

Dropout Voltage

V_DR

–

320

240

mV

I_Q= 50 mA ; V_I= V_Q,nom

P_5.0.9

200

I_Q= 100 mA ;

P_5.0.10

V_I= V_Q,nom; T_J= 25 °C

Dropout Voltage

V_DR

–

340

320

mV

I_Q= 100 mA ; V_I= V_Q,nomP_5.0.11

290

I_Q= 300 mA ;

P_5.0.12

V_I= V_Q,nom; T_J= 25 °C

Dropout Voltage

V_DR

–

410

mV

I_Q= 300 mA ; V_I= V_Q,nomP_5.0.13

Quiescent Current

(Active-Mode, EN-pin high)

I_q

–

30

60

1

µA

V_I= V_Q,nom

I_Q= 0 mA

;

P_5.0.14

P_5.0.15

Quiescent Current

(Off-Mode, EN-pin low)

0.1

V_I= 6 V ; V_EN= 0 V ;

T_J= 25 °C

GND Pin Current ⁴⁾

GND Pin Current

I_GND

–

50

100

850

µA

V_I= V_Q,nom

I_Q= 1 mA

;

P_5.0.16

P_5.0.17

GND Pin Current

Data Sheet

300

V_I= V_Q,nom;

I_Q= 50 mA

9

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

Table 4

Electrical Characteristics (cont’d)

-40 °C < T_j< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless

otherwise specified.

Parameter

Symbol

Values

Typ.

0.7

Unit

Note / Test Condition

Number

Min.

Max.

GND Pin Current

I_GND

–

2.2

mA

V_I= V_Q,nom

I_Q= 100 mA

V_I= V_Q,nom

;

P_5.0.18

P_5.0.19

–

4

12

;

I_Q= 300 mA

Enable

Enable Threshold High

Enable Threshold Low

EN Pin Current ⁵⁾

V_th,EN

V_tl,EN

I_EN

–

0.8

0.65

0.01

1

2.0

–

V

V_Q= Off to On

V_Q= On to Off

P_5.0.20

P_5.0.21

P_5.0.22

P_5.0.23

0.25

–

V

–

µA

V

_EN= 0 V ; T_J= 25 °C

_EN= 20V ; T_J= 25 °C

EN Pin Current ⁵⁾

I_EN

–

Output Voltage Noise ⁶⁾

Output Voltage Noise

e_no

–

55

–

µV_RMSC_Q= 10 µF ;

_BYP= 10 nF ;

P_5.0.24

C

I_Q= 300 mA ;

BW = 10 Hz to 100 kHz

Output Voltage Noise

e_no

44

µV_RMSC_Q= 10 µF

+250mΩ resistorinseries;

_BYP= 10 nF ;

P_5.0.25

C

I_Q= 300 mA ;

BW = 10 Hz to 100 kHz

Output Voltage Noise

e_no

–

42

–

µV_RMSC_Q= 22 µF

_BYP= 10 nF ;

P_5.0.26

P_5.0.27

C

I_Q= 300 mA ;

BW = 10 Hz to 100 kHz

e_no

µV_RMSC_Q= 22 µF

+250mΩ resistorinseries;

_BYP= 10 nF ;

C

I_Q= 300 mA ;

BW = 10 Hz to 100 kHz

Power Supply Ripple Rejection ⁶⁾

Power Supply Ripple Rejection PSRR

–

65

–

dB

V_I- V_Q= 1.5 V (avg) ;

P_5.0.28

V

_RIPPLE= 0.5 Vpp ;

f_r= 120 Hz ; I_Q= 300 mA

Output Current Limitation

Output Current Limit

I_Q,limit

320

–

mA

V_I= 7 V ; V_Q= 0 V

P_5.0.29

P_5.0.30

V_I= V_Q,nom+ 1 V

∆V_Q= -0.1 V

Input Reverse Leakage Current

Input Reverse Leakage

Reverse Output Current ⁷⁾

Reverse Output Current

I_leak,rev

–

1

mA

µA

V_I= -20 V ; V_Q= 0 V

P_5.0.31

I_Reverse

10

20

V_Q= V_Q,nom; V_I< V_Q,nom; P_5.0.32

T_J= 25 °C

Data Sheet

10

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

1) This parameter defines the minimum input voltage for which the device is powered up and provides the maximum nominal

output current of 300 mA. Under this minimum input voltage condition the TLS203B0 V50 starts to be in tracking mode and

the output voltage will typically be in the range of around 1 V while providing the 300 mA.

2) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will

only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all

possible combinations of input voltage and output current. When operating at maximum input voltage, the output current

must be limited for thermal reasons. The same holds true when operating at maximum output current where the input

voltage range must be limited for thermal reasons.

3) The dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output

current. In dropout, the output voltage will be equal to V_I- V_DR

4) GND-pin current is tested with V_I= V_Q,nomand a current source load. This means that this parameter is tested while being

in the dropout region. The GND pin current will in most cases decrease slightly at higher input voltages - please also refer

to the corresponding typical performance graphs.

5) The EN pin current flows into EN pin.

6) Not subject to production test, specified by design.

7) Reverse output current is tested with the I pin grounded and the Q pin forced to the rated output voltage. This current flows

into the Q pin and out of the GND pin.

Note:The listed characteristics are ensured over the operating range of the integrated circuit. Typical

characteristics specified mean values expected over the production spread. If not otherwise specified,

typical characteristics apply at T_A= 25 °C and the given supply voltage.

Data Sheet

11

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

5.1

Typical Performance Characteristics

Dropout Voltage V_DRversus

Output Current I_Q

Guaranteed Dropout Voltage V_DRversus

Output Current I_Q

500

450

400

350

300

250

200

150

100

50

500

Δ = Guaranteed Limits

450

400

350

300

250

200

150

100

50

T_j= −40 °C

T_j= 25 °C

T_j= 125 °C

T_j≤ 25 °C

T_j≤ 125 °C

0

50

100

150

200

250

300

0

50

100

150

200

250

300

I_Q[A]

Dropout Voltage V_DRversus

Junction Temperature T_j

Quiescent Current versus

Junction Temperature T_j

500

50

45

40

35

30

25

20

15

10

5

I_Q= 10 mA

450

I_Q= 50 mA

I_Q= 100 mA

400

I_Q= 300 mA

350

300

250

200

150

100

50

V_I= 6 V

I_Q= 0 mA .

V_EN= V

I

0

−50

0

50

T_j[°C]

100

−50

0

50

T_j[°C]

100

Data Sheet

12

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

Output Voltage V_Qversus

Junction Temperature T_J

Quiescent Current I_qversus

Input Voltage V_I

800

700

600

500

400

300

200

100

0

5.08

5.06

5.04

5.02

5

4.98

4.96

4.94

V_Q,nom= 5.0 V

I_Q,nom= 0 mA

V_EN= V

I

T_j= 25 °C

4.92

I_Q= 1 mA

4.9

−50

0

50

T_j[°C]

100

0

2

4

6

8

10

V_I[V]

GND Pin Current I_GNDversus

Input Voltage V_I

GND Pin Current I_GNDversus

Input Voltage V_I

1600

8

R_Load= 5.0 kΩ / I_Q= 1 mA*

R_Load= 100 Ω / I_Q= 50 mA*

R_Load= 50.0 Ω / I_Q= 100 mA*

R_Load= 16.7 Ω / I_Q= 300 mA*

1400

1200

1000

800

600

400

200

0

7

6

5

4

3

2

1

0

[* for V_Q= 5.0 V]

T_j= 25°C

[* for V_Q= 5.0 V]

T_j= 25°C

0

2

4

6

8

10

0

2

4

6

8

10

V_I[V]

Data Sheet

13

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

GND Pin Current I_GNDversus

Output Current I_Q

EN Pin Threshold (On-to-Off) versus

Junction Temperature T_J

1.2

1

5

1 mA

300 mA

V_I= 6 V

T_j= 25 ° C

4.5

4

3.5

3

0.8

0.6

0.4

0.2

0

2.5

2

1.5

1

0.5

0

−50

0

50

T_j[°C]

100

0

50

100

150

200

250

300

I_Q[mA]

EN Pin Threshold (Off-to-On) versus

EN Pin Input Current versus

Junction Temperature T_J

EN Pin Voltage V_EN

1.2

1

1.4

1.2

1

T_j= 25 °C

V_I= 20 V

1 mA

300 mA

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

−50

0

50

T_j[°C]

100

0

5

10

V_EN[V]

15

20

Data Sheet

14

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

EN Pin Current versus

Current Limit versus

Junction Temperature T_J

Input Voltage V_I

1.6

1.4

1.2

1

V_Q= 0 V

V_EN= 20 V

T = 25 ° C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

j

0.8

0.6

0.4

0.2

0

−50

0

50

T_j[°C]

100

0

1

2

3

4

5

6

7

V_I[V]

Current Limit versus

Reverse Output Current versus

Junction Temperature T_J

Output Voltage V_Q

1.2

1

90

V_Q.nom= 5.0 V (V50)

V_I= 7 V

V_Q= 0 V

80

70

V_I= 0 V

T_j= 25 °C

0.8

0.6

0.4

0.2

0

60

50

40

30

20

10

0

−50

0

50

T_j[°C]

100

0

2

4

6

8

10

V_Q[V]

Data Sheet

15

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

Reverse Output Current versus

Minimum Input Voltage ¹⁾versus

Junction Temperature T_J

22

2.5

V_Q.nom= 5.0 V (V50)

20

18

2

1.5

1

V_I= 0 V

16

14

12

10

8

6

0.5

0

4

I_Q= 1 mA

2

I_Q= 300 mA

0

−50

0

50

T_j[°C]

100

−50

0

50

T_j[°C]

100

Load Regulation versus

Junction Temperature T_J

5

V50: V = 6.0 V; V_Q.nom= 5.0 V

I

0

−5

−10

−15

−20

−25

ΔI_Load= 1 mA to 300 mA

−50

0

50

T_j[°C]

100

1) V_I,minis referred here as the minimum input voltage for which the requested current is provided and V_Qreaches 1 V.

Data Sheet

16

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

ESR Stability versus

ESR(C_Q) with C_BYP= 10 nF versus

Output Current I_Q(for C_Q= 3.3 µF)

Output Capacitance C_Q

3

2.5

2

10¹

C_Byp= 10 nF

measurement limit

ESR_maxC_Byp= 0 nF

10⁰

stable region above blue line

ESR_minC_Byp= 0 nF

ESR_maxC_Byp= 10 nF

ESR_minC_Byp= 10 nF

1.5

1

C_Q= 3.3 µF

(0.06 Ω is measurement limit)

0.5

0

10⁻¹

0

50

100

150

200

250

300

2

3

4

5

6

7

I_Q[mA]

C_Q[µF]

Input Ripple Rejection PSRR versus

Frequency f

Junction Temperature T_J

100

72

70

68

66

64

62

V_I= V_Qnom+ 1.5 V

V_ripple= 0.5 V_pp

C_Q= 10 µF

90

80

70

60

50

40

30

20

10

0

60

V_I= V_Qnom+ 1.5 V

V_ripple= 0.5 V_pp

f_ripple= 120 Hz

C_Q= 10 µF

58

56

54

52

I_Q=300mA C_BYP=0 nF

I_Q=300mA C_BYP=10nF

I_Q=50mA C_BYP=0 nF

I_Q=50mA C_BYP=10nF

I_Q= 300mA; C_BYP= 0 nF

I_Q= 300mA; C_BYP= 10nF

50

T_j[°C]

10

100

1k

10k

100k

−50

0

100

f [Hz]

Data Sheet

17

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Electrical Characteristics

Output Noise Spectral Density versus

Frequency f (C_Q= 10 µF, I_Q= 50 mA)

Frequency f (C_Q= 22 µF, I_Q= 50 mA)

10¹

C_Q= 10 µF

I_Q= 50 mA

C_Q= 22 µF

I_Q= 50 mA

10⁰

10⁻¹

C_Byp= 0 nF; ESR(C_Q)=0

C_Byp= 10 nF; ESR(C_Q)=0

C_Byp= 0 nF; ESR(C_Q)=0

C_Byp= 10 nF; ESR(C_Q)=0

C_Byp= 10 nF; ESR(C_Q)=250mΩ

10⁻²

10¹

10⁻²

10¹

10²

10³

f [Hz]

10⁴

10⁵

10²

10³

f [Hz]

10⁴

10⁵

Transient Response C_BYP= 0 nF

Transient Response C_BYP= 10 nF

0,3

0,15

C_Q= 10 µF

C_BYP

V_I

=

0 nF

6V

C_BYP= 10 nF

0,2

0,1

0

0,1

V_I

=

6V

0,05

0

-0,1

-0,2

-0,3

-0,05

-0,1

-0,15

0

100

200

300

400

500

Time (μs)

600

700

800

900

1000

0

20

40

60

80

100

Time / [μs]

120

140

160

180

200

400

350

300

250

200

150

100

50

400

350

300

250

200

150

100

50

I_Q: 100 to 300mA

0

100

200

300

400

500

Time (μs)

600

700

800

900

1000

0

20

40

60

80

100

Time / [μs]

120

140

160

180

200

Data Sheet

18

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Application Information

6

Application Information

Note:The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

TLS203B0

V_I

V_Q

I

Q

C_I

SENSE

R_Load

C_Q

C_BYP

1µF

10nF

10µF

EN

BYP

GND

Typical Application Circuit TLS203B0 V50

Figure 4

Note:This is a very simplified example of an application circuit. The function must be verified in the real

application. ^{1) 2)}

The TLS203B0 V50 is a 300 mA low dropout regulator with very low quiescent current and Enable-functionality.

The device is capable of supplying 300 mA at a dropout voltage of 290 mV. Output voltage noise numbers down

to 42 µV_RMScan be achieved over a 10 Hz to 100 kHz bandwidth with the addition of a 10 nF reference bypass

capacitor. The usage of a reference bypass capacitor will additionally improve transient response of the regulator,

lowering the settling time for transient load conditions. The device has a low operating quiescent current of typical

30 µA that drops to less than 1 µA in shutdown (EN-pin pulled to low level). The device also incorporates several

protection features which makes it ideal for battery-powered systems. It is protected against both reverse input

and reverse output voltages.

6.1

Kelvin Sense Connection

The SENSE pin of the TLS203B0 V50 is the input to the error amplifier. An optimum regulation will be obtained at

the point where the SENSE pin is connected to the output pin Q of the regulator. In critical applications however

small voltage drops may be caused by the resistance R_pof the PC-traces and thus may lower the resulting voltage

at the load. This effect may be eliminated by connecting the SENSE pin to the output as close as possible at the

load (see Figure 5). Please note that the voltage drop across the external PC trace will add up to the dropout

voltage of the regulator.

1) Please note that in case a non-negligible inductance at the input pin I is present, e.g. due to long cables, traces, parasitics,

etc, a bigger input capacitor C_Imay be required to filter its influence. As a rule of thumb if the I pin is more than six inches

away from the main input filter capacitor an input capacitor value of C_I= 10 µF is recommended.

2) For specific needs a small optional resistor may be placed in series to very low ESR output capacitors C_Qfor enhanced

noise performance (for details please see “Bypass Capacitance and Low Noise Performance” on Page 20).

Data Sheet

19

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Application Information

TLS203B0

R_P

I

Q

V_I

C_I

SENSE

R_Load

C_Q

EN

BYP

GND

R_P

Figure 5

Kelvin Sense Connection

6.2

Bypass Capacitance and Low Noise Performance

The TLS203B0 V50 regulator may be used in combination with a bypass capacitor connecting the output pin Q to

the BYP pin in order to minimize output voltage noise¹⁾. This capacitor will bypass the reference of the regulator,

providing a low frequency noise pole. The noise pole provided by such a bypass capacitor will lower the output

voltage noise in the considered bandwidth. Actual numbers of the output voltage noise of the TLS203B0 V50 will

- next to the bypass capacitor itself - be dependent on the capacitance of the applied output capacitor C_Qand its

ESR: In case of applying a bypass capacitor of 10 nF in combination with a (low ESR) ceramic C_Qof 10 µF output

voltage noise numbers will be in the range of typical 55 µV_RMS. This output noise level can be reduced to typical

44 µV_RMSunder the same conditions by adding a small resistor of ~250 mΩ in series to the 10 µF ceramic output

capacitor acting as additional ESR. A reduction of the output voltage noise can also be achieved by increasing

capacitance of the output capacitor. For C_Q= 22 µF (ceramic low ESR) the output voltage noise will be typically

around 42 µV_RMS. For output capacitor values of 22 µF or bigger adding resistance in series to C_Qdoes not further

lower output noise numbers significantly anymore. For further details please also see “Output Voltage Noise”

on Page 10,, of the Electrical Characteristics. Please note that next to reducing the output voltage noise level the

usage of a bypass capacitor has the additional benefit of improving transient response which will be also explained

in the next chapter. However one needs to take into consideration that on the other hand the regulator start-up

time is proportional to the size of the bypass capacitor and slows down to values around 15 ms when using a 10 nF

bypass capacitor in combination with a 10 µF C_Qoutput capacitor.

6.3

Output Capacitance and Transient Response

The TLS203B0 V50 is designed to be stable with a wide range of output capacitors. The ESR of the output

capacitor is an essential parameter with regard to stability, most notably with small capacitors. A minimum output

capacitor of 3.3 µF with an ESR of 3 Ω or less is recommended to prevent oscillations. Like in general for LDO’s

the output transient response of the TLS203B0 V50 will be a function of the output capacitance. Larger values of

output capacitance decrease peak deviations and thus improve transient response for larger load current

changes. Bypass capacitors, used to decouple individual components powered by the TLS203B0 V50 will

increase the effective output capacitor value. Please note that with the usage of bypass capacitors for low noise

operation either larger values of output capacitors may be needed or a minimum ESR requirement of C_Qmay have

to be considered (see also typical performance graph “ESR(C_Q) with C_BYP= 10 nF versus Output Capacitance

1) a good quality low leakage capacitor is recommended.

Data Sheet

20

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Application Information

C_Q” on Page 17 as example). In conjunction with the usage of a 10 nF bypass capacitor an output capacitor C_Q≥

6.8 µF is recommended. The benefit of a bypass capacitor to the transient response performance is impressive

and illustrated as one example in Figure 6 where the transient response of the TLS203B0 V50 to one and the

same load step from 100 mA to 300 mA is shown with and without a 10 nF bypass capacitor: for the given

configuration of C_Q= 10 µF with no bypass capacitor the load step will settle in the range of less than 200 µs while

for C_Q= 10 µF in conjunction with a 10 nF bypass capacitor the same load step will settle in the range of 20 µs.

Due to the shorter reaction time of the regulator by adding the bypass capacitor not only the settling time improves

but also output voltage deviations due to load steps are sharply reduced.

0,3

C_BYP = 0nF

C_BYP = 10nF

C_Q= 10 µF

_BYP= 0 vs 10nF

V_I= 6 V

C

0,2

0,1

0

-0,1

-0,2

-0,3

0

100

200

300

400

500

Time (μs)

600

700

800

900

1000

Figure 6

Influence of C_BYP: example of transient response to one and the same load step with and

without C_BYPof 10 nF (I_Q: 100 mA to 300 mA)

6.4

Protection Features

The TLS203B0 V50 regulators incorporate several protection features which make them ideal for use in battery-

powered circuits. In addition to normal protection features associated with monolithic regulators like current limiting

and thermal limiting the device is protected against reverse input voltage, reverse output voltage and reverse

voltages from output to input.

Current limit protection and thermal overload protection are intended to protect the device against current overload

conditions at the output of the device. For normal operation the junction temperature must not exceed 125 °C.

The input of the device will withstand reverse voltages of 20 V. Current flowing into the device will be limited to

less than 1 mA (typically less than 100 µA) and no negative voltage will appear at the output. The device will

protect both itself and the load. This provides protection against batteries being plugged backwards.

The output of the TLS203B0 V50 can be pulled below ground without damaging the device. If the input is left open-

circuit or grounded, the output can be pulled below ground by 20 V. Under such conditions the output of the device

by itself behaves like an open circuit with practically no current flowing out of the pin ¹⁾. In more application relevant

cases however where the output is connected to the SENSE pin there will be a small current of typically less than

100 µA present from this origin. If the input is powered by a voltage source the output will source the short circuit

current of the device and will protect itself by thermal limiting. In this case grounding the EN pin will turn off the

device and stop the output from sourcing the short-circuit current.

In circuits where a backup battery is required, several different input/output conditions can occur. The output

voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left

open-circuit. Current flow back into the output will follow the curve as shown in Figure 7 below.

1) typically < 1 µA for the mentioned conditions, V_Qbeing pulled below ground with other pins either grounded or open.

Data Sheet

21

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Application Information

90

80

70

60

50

40

30

20

10

0

V_Q.nom= 5.0 V (V50)

V_I= 0 V

T_j= 25 °C

0

2

4

6

8

10

V_Q[V]

Figure 7

Reverse Output Current

Data Sheet

22

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Package Outlines

7

Package Outlines

0.35 x 45˚

1)

±0.1

3.9

0.1 C D 2x

+0.06

9

0.1

0.08

Seating Plane

C

0.64_±0.25

±0.2

0.2

1.27

2)

M

±0.09

0.41

D 8x

6

M

0.2

C A-B D 8x

D

Bottom View

±0.2

3

A

1

4

8

5

1

4

8

5

B

0.1 C A-B 2x

1)

±0.1

4.9

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width

3) JEDEC reference MS-012 variation BA

PG-DSO-8-27-PO V01

Figure 8

PG-DSO-8 Exposed Pad package outlines

±0.1

2.58

±0.1

0.1

±0.1

3.3

0.36

0.53

0.05

Z

Pin 1 Marking

±0.1

0.5

Pin 1 Marking

±0.1

0.25

PG-TSON-10-2-PO V02

Z (4:1)

0.07 MIN.

Figure 9

PG-TSON-10 Package Outlines

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e

Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

23

Rev. 1.1, 2015-01-15

TLS203B0EJV50

TLS203B0LDV50

Revision History

8

Revision History

Revision

Date

Changes

Data Sheet - Revision 1.1:

1.1

2015-01-15

•

PG-TSON-10 package variant added: Product Overview, Pin Configuration,

Thermal Resistance, etc - wording and description added / updated

accordingly.

•

Editorial changes.

1.0

2014-06-30

Data Sheet - Initial Release

Data Sheet

24

Rev. 1.1, 2015-01-15

Edition 2015-01-15

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.


型号：	TLS203B0EJ V50
厂家：	Infineon
描述：	TLS203B0EJV50 是一款微功耗、低噪声、低压差的调节器。该器件能够实现 300 mA 的输出电流，290 mV 的压差。专为电池供电系统设计，30 μA 的低静态电流使其成为理想的选择。TLS203B0EJV50 的一个关键特性是其输出噪声较低。通过添加一个外部 10 nF 的旁路电容，可以在 10 Hz 至 100 kHz 的带宽内将输出噪音值下降至 42 μVRMS。TLS203B0EJV50 电压调节器在输入电容小至 3.3 μF 时也能保持其稳定性。可以使用小型陶瓷电容，不需要其他许多调节器所需的串联电阻。内部保护电路包括反向电池保护、电流限制和反向电流保护。TLS203B0EJV50 是5.0 V 固定输出电压的型号，采用 PG-DSO-8 散热焊盘封装。电池调节器
文件：	总25页 (文件大小：2346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLS203B0EJ V50 [INFINEON]

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