TLS4125D0EPV_技术文档

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Features

•

2.5 A step down regulator

Input voltage from 3.7 V to 35 V

Adjustable output voltage 3.0 V to 10.0 V

±1.5% feedback voltage accuracy in PWM mode

Ultra low current consumption 31 µA

Integrated high side and low side power MOSFETs

Peak current mode PWM regulation

Light load PFM mode with improved eﬀiciency

Switching frequency range: 320 kHz to 560 kHz or 1.6 MHz to 2.8 MHz

100% duty cycle operation

Synchronization input

Spread spectrum frequency modulation for improved EMI performance

Soꢀ-start function

Integrated compensation network

Output discharge function in disabled state

Ultra low current consumption in disabled state (typically 1 µA)

Undervoltage monitoring

Overvoltage monitoring

Overcurrent protection and overload protection

Input undervoltage shutdown

Wide temperature range T_j= -40°C to 150°C

Green Product (RoHS compliant)

Potential applications

•

Body

ADAS

Infotainment, telematics

Navigation

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100.

Datasheet

Please read the Important Notice and Warnings at the end of this document

Rev. 1.02

www.infineon.com/OPTIREG-switcher

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Description

The OPTIREG^™switcher TLS4125D0EPV is a 2.8 MHz synchronous step down regulator especially designed

for automotive applications. The device has a current capability of 2.5 A, adjustable output voltage and

a feedback voltage accuracy of ±1.5% in PWM mode. The integrated power stages, soꢀ-start feature and

integrated compensation network reduce the required amount of external components and thus system costs

and board space. The wide input voltage range and a 100% duty cycle operation mode make the device

suitable for battery cranking scenarios in automotive applications. The wide switching frequency range allows

the selection of appropriate coils and capacitors. The switching frequency can be synchronized to an external

clock signal. Spread spectrum frequency modulation can be activated to improve the EMI performance in PWM

operation. The device oﬀers low current consumption in PFM mode at light loads to optimize eﬀiciency. The

TLS4125D0EPV can detect undervoltage and overvoltage conditions of the output voltage and indicates this

with the reset output signal. Overcurrent and overload protections avoid excessive current to protect the device

during short circuit conditions at the buck converter output. The integrated thermal shutdown feature protects

the device from overheating. The enhanced PG-TSDSO-14 exposed pad package oﬀers advantageous thermal

performance in the application.

Type

Package

Marking

TLS4125D0EPV

PG-TSDSO-14

4125D0V

Datasheet

2

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Table of contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1

2

2.1

2.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

3.2

3.3

4

4.1

Buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional description buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Regulation loop and operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PWM (Pulse Width Modulation) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PFM (Pulse Frequency Modulation) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Continuous conduction mode and discontinuous conduction mode . . . . . . . . . . . . . . . . . . . . .12

High duty cycle operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-up and power-down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Startup procedure with soꢀ-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Active output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Overcurrent protection and overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Input undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Electrical characteristics buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typical performance characteristics buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.1

4.1.1.1

4.1.1.2

4.1.1.3

4.1.1.4

4.1.2

4.1.2.1

4.1.2.2

4.1.3

4.1.3.1

4.1.3.2

4.1.3.3

4.2

4.3

5

5.1

5.1.1

5.1.2

5.2

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Functional description oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Electrical characteristics oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Typical performance characteristics oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.3

6

Current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Datasheet

3

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Table of contents

6.1

6.2

6.3

Functional description current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Electrical characteristics current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Typical performance characteristics current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . 32

7

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Functional description reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electrical characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical performance characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

7.2

7.3

8

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Feedforward capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

8.1

8.2

8.3

8.4

9

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Datasheet

4

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Block diagram

1

Block diagram

VS

EN

Enable

UVLO

Internal

supply

Over-

temperature

shutdown

Bandgap

reference

FREQ

SW

Control loop

+ driver

Oscillator

SYNC

SSON

PGND

FB

Spread

spectrum

Soft-start

ramp

generator

RO

RT

Reset

AGND

Figure 1

Block diagram

Datasheet

5

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Pin configuration

2

Pin configuration

2.1

Pin assignment

TSDSO-14

FB

FREQ

SYNC

RO

AGND

EN

1

2

3

4

5

6

7

14

13

12

11

10

9

RT

SSON

SW

PGND

VS

8

Figure 2

Pin configuration

2.2

Pin definitions and functions

Symbol Function

1

FREQ

Frequency selection input:

Connect this pin to GND via resistor for frequency selection.

Leave this pin open to set the default high switching frequency.

Connect this pin to GND to set the default low switching frequency.

2

3

SYNC

RO

Synchronization input:

Connect this pin to external clock to synchronize the switching frequency.

If this pin is not used, then connect it to GND.

Reset output:

Open drain reset output. Provides the reset output signal.

If the reset feature is used, then connect this pin via external resistor to V_CCor to an external

pull-up voltage.

If the reset feature is not used, then leave this pin open.

4

5

AGND

EN

Analog ground:

Connect this pin to GND using a low inductive, broad PCB trace.

Enable input:

This pin has an integrated pull-down resistor.

"High" enables the device.

"Low" disables the device.

6, 7

8, 9

VS

Supply voltage input:

Connect this pin to supply voltage.

Short pins 6 and 7 at the PCB.

PGND

Power ground:

Connect this pin directly to GND using a low inductive, broad PCB trace.

Short pins 8 and 9 at the PCB.

10, 11 SW

Regulator switch node:

Datasheet

6

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Pin configuration

Symbol Function

Connect this pin to the buck converter power inductor.

Short pins 10 and 11 at the PCB.

12

SSON

Spread spectrum enable input:

This pin has an integrated pull-down resistor.

"High" enables spread spectrum.

"Low" disables spread spectrum.

13

RT

Reset configuration input:

Connect this pin via a resistor to GND to adjust the reset delay time and the reset

undervoltage threshold.

Connect this pin to GND, if the reset function is not needed or to configure the default reset

delay time and default undervoltage reset threshold.

14

–

FB

Feedback input:

Feedback input to the regulator. Connect this pin to the feedback resistor divider tap (see

Output voltage adjustment).

Exposed Connect the exposed pad to a heatsink area and to GND with low inductive and broad PCB

pad trace.

Datasheet

7

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

Table 1

Absolute maximum ratings¹⁾

T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Min. Typ.

Unit Note or

condition

Number

Max.

Voltages

Enable input

V_EN

-20

–

35

42

V

–

P_3.1.1

P_3.1.2

V_EN,dyn

²⁾Transients

present on this

Synchronization input

Spread spectrum enable input

Frequency selection

Reset output

V_SYNC

V_SSON

V_FREQ

V_RO

-0.3

–

6

V

–

P_3.1.3

P_3.1.4

P_3.1.5

P_3.1.6

P_3.1.7

P_3.1.8

P_3.1.9

Reset configuration

Feedback input

V_RT

V_FB

1.5

Buck switch output

V_SW

V_VS+ 0.3

Minimum -2.0 V

in transient

condition (single

event < 15 ns)

Supply voltage input

V_VS

-0.3

–

35

42

V

–

P_3.1.10

P_3.1.11

V_VS,dyn

²⁾Transients

present on this

Power GND

V_PGND

V_AGND

-0.3

–

0.3

V

–

P_3.1.12

P_3.1.13

Analog GND

Temperatures

Junction temperature

Storage temperature

ESD susceptibility

ESD susceptibility to GND

T_j

-40

-55

–

150

°C

–

P_3.1.14

P_3.1.15

T_stg

V_ESD,HBM-2

–

2

kV

V

³⁾HBM

⁴⁾CDM

P_3.1.16

P_3.1.17

V_ESD,CDM-500

500

1

Not subject to production test, specified by design.

Transients between 35 V and 42 V can be tolerated for a total lifetime duration shorter than 48 s.

ESD susceptibility, Human Body Model (HBM) according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).

ESD susceptibility, Charged Device Model (CDM) according to JEDEC JESD22-C101.

2

3

4

Datasheet

8

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

General product characteristics

Table 1

Absolute maximum ratings¹⁾(continued)

T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Min. Typ.

Unit Note or

condition

Number

Max.

750

ESD susceptibility corner pins 1, 7, 8, V_ESD,CDM,C-750

–

V

⁴⁾CDM

P_3.1.18

14 to GND

Notes:

1.

Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods of time may aﬀect device reliability.

Integrated protection functions are designed to prevent IC destruction under fault conditions described in

the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions

are not designed for continuous repetitive operation.

2.

3.2

Functional range

Table 2

Functional range

T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Min. Typ.

Unit Note or condition

Number

Max.

Supply voltage decreasing

V_VS,dec

3.7

–

35

V

⁵⁾Minimum value

represents low

battery voltage

P_3.2.1

condition (cranking)

Supply voltage increasing

V_VS,inc

6.0

–

35

Minimum value

represents startup

condition

P_3.2.2

Enable input

V_EN

V_CC

0

–

35

10

V

–

P_3.2.3

P_3.2.6

P_3.2.9

P_3.2.12

P_3.2.13

P_3.2.15

Output voltage adjust range

SYNC input voltage

Reset output voltage

Output current

3.0

0

V

V_SYNC

V_RO,hi

I_CC

5.2

2.5

150

V

–

6)

0

V

0

A

°C

–

Junction temperature

T_j

-40

1

Not subject to production test, specified by design.

ESD susceptibility, Charged Device Model (CDM) according to JEDEC JESD22-C101.

With 3.7 V < V_VS< 6 V, a reduced performance of parameter settings applies to feedback voltage accuracy,

synchronization and the reset function.

4

5

6

Allowed pull-up voltage applied via pull-up resistance to pin RO.

Datasheet

9

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

General product characteristics

Note:

Within the functional or operating range, the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the electrical characteristics

table.

3.3

Thermal resistance

Table 3

Thermal resistance⁷⁾

Parameter

Symbol

Values

Unit Note or condition Number

Min.

Typ. Max.

Junction to case

R_thJC

–

8.6

34

–

K/W

K/W ⁸⁾2s2p

K/W ⁹⁾1s0p + 600 mm² P_3.3.3

K/W ⁹⁾1s0p + 300 mm² P_3.3.4

K/W ⁹⁾1s0p footprint

–

P_3.3.1

P_3.3.2

Junction to ambient

R_thJA,1

R_thJA,2

R_thJA,3

R_thJA,4

45

54

116

P_3.3.5

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information

visit www.jedec.org.

7

Not subject to production test, specified by design.

8

Specified R_thJAvalue is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the

product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with two inner copper layers

(2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable, a thermal via array next to the package contacted the first

inner copper layer.

Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; the

product (IC and package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 × 70 µm

Cu).

9

Datasheet

10

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

4

Buck regulator

4.1

Functional description buck regulator

The TLS4125D0EPV is a synchronous current mode step down (buck) regulator with selectable switching

frequency f_OSC. The device regulates the output voltage in pulse width modulation (PWM) or in pulse frequency

modulation (PFM) mode and automatically moves between both modes on load change or input voltage

change. At low input voltage conditions, for example during battery cranking, the device can operate at a duty

cycle of 100%.

4.1.1

Regulation loop and operation modes

Figure 3 shows the regulation loop. An external resistor divider is connected between V_CCand AGND. The

intermediate point V_FBis connected to pin FB. The error amplifier processes the diﬀerence between scaled

output feedback voltage and internal reference voltage to provide a reference current to the PWM comparator.

The PWM comparator compares that reference current to a scaled version of the inductor current to determine

the PWM duty cycle that is required for stable output voltage regulation. In PFM mode the error amplifier output

signal also serves to modulate the switching frequency.

The control logic supervises the handover between operation modes and triggers the drivers of high side PMOS

power stage and the low side NMOS power stage accordingly. For the modes of PWM, PFM and 100% duty cycle

operation see PWM (Pulse Width Modulation) mode, PFM (Pulse Frequency Modulation) mode, Continuous

conduction mode and discontinuous conduction mode and High duty cycle operation respectively.

VS

V_CC

Current

sense

Internal

comp.

R1

R2

FB

Error

amp.

L_OUT

V_CC

Control

logic

SW

PWM

comp.

Soft-

start

Voltage

reference

GND

C_OUT

Slope

compensation

Oscillator

Clock

PGND

Clock

manager

GND

SYNC

AGND

Figure 3

Functional block diagram buck regulator

4.1.1.1

PWM (Pulse Width Modulation) mode

At high load the TLS4125D0EPV operates with the configured switching frequency f_OSCin PWM mode. In PWM

mode the device modulates the duty cycle to achieve a regulated output voltage. The nominal switching

frequency can be set using one of the following methods, see Oscillator:

•

by an external resistor connected at pin FREQ

from a synchronization signal applied at the SYNC pin

The pulse width modulation is based on peak current mode detection to achieve a fast reaction time and

an optimized feedback accuracy. The PWM comparator processes the current signal detected at the high

Datasheet

11

Rev. 1.02

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

side power stage as well as the current signals of the slope compensation and the error amplifier to adjust

the switching duty cycle to regulate the output voltage accordingly. With a duty cycle above 50% the slope

compensation ensures system stability. This is achieved by avoidance of subharmonic oscillations of the output

inductor current.

Due to a current sense signal inaccuracy at the beginning of each high side switch conduction phase, a short

blanking time is required to mask the output of the current sense before processing it. The blanking time

defines the minimum allowed on-time t_on,minof the high side PMOS power stage and therefore the point of

transition from PWM to PFM operation.

4.1.1.2

PFM (Pulse Frequency Modulation) mode

The device can operate at constant on-time t_on,minof the high side PMOS power stage to achieve a stable output

voltage at light load or high input voltage conditions. In PFM mode the device operates at a constant on-time

and modulates the switching frequency to regulate the output voltage. The switching frequency is lower than

in PWM mode. For further information about the PFM boundary condition and the frequency modulation

depending on load and on input voltage, see Typical performance characteristics buck regulator.

In PFM mode with light load the device oﬀers optimized eﬀiciency with reduced current consumption.

4.1.1.3

Continuous conduction mode and discontinuous conduction mode

Continuous conduction mode (CCM)

The device operates at a continuously rising or falling triangular positive inductor current. The on-time and the

switching duty cycle mainly depend on the ratio of output voltage to input voltage.

Boundary condition for CCM → DCM transition

With a decrease of the load current during continuous conduction mode, the minimum valley inductor current

can obtain approximately zero, which is the boundary condition for the discontinuous conduction mode.

Further reduction of the load current leads to discontinuous conduction mode.

Discontinuous conduction mode (DCM)

The device turns oﬀ the low side power stage to avoid a negative inductor current. Further reduction of the load

current reduces the on-time and leads to transition from PWM into PFM when obtaining the minimum on-time.

I_L

High load

PWM-CCM

t

I_L

CCM-DCM

boundary

t

I_L

Medium-low load

PWM-DCM

t

I_L

Low load

PFM-DCM

t

Figure 4

Typical example inductor current waveforms for CCM and DCM

Datasheet

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Rev. 1.02

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

4.1.1.4

High duty cycle operation

In 100% duty cycle mode the high side PMOS power stage constantly conducts current. If the input voltage is

close to the nominal output voltage or lower, then the device enters this operation mode, see Figure 5.

If the input voltage is decreased (for example during a battery cranking scenario) and the device moves from

regulation to the 100% duty cycle mode, then the output voltage tracks the input voltage as accurate as

possible down to an input voltage V_VSof 3.7 V. During steady state operation, the diﬀerence of the output

voltage and the tracked input voltage as well as the entry point into 100% duty cycle mainly depend on the

voltage drop at the resistance R_on,hsof the high side PMOS power stage, which in turn depends on the load

current I_CC. Parasitic elements of external application circuitry and components, such as the output inductor

series resistance, increase the voltage drop.

At high duty cycles close to 100%, the loop might not propagate very short oﬀ-times and compensates this by

skipping switching cycles to ensure a smooth transition to 100% duty cycle with a stable output voltage.

Commonly, regulators with adjustable output voltage are more sensitive towards noise injected into the

feedback path due to the external resistor divider. The current sense signal processing for accurate peak current

detection may reach its resolution limit at high duty cycles close to 100% due to low peak to peak inductor

currents. Therefore an optimized PCB layout and suitable external components are crucial to avoid irregular

cycles of the switching frequency and to maintain a stable output voltage.

V_VS

V_CC

V_CC= V_CC,nom

Voltage

t

100%

Duty-

cycle

Regulation

Tracking

Regulation

Figure 5

Typical 100% duty cycle mode tracking behavior

Datasheet

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Rev. 1.02

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

4.1.2

Power-up and power-down control

The following features of the device control power up and power down, see Table 4 for electrical characteristics:

•

Startup with soꢀ-start

Active output discharge

4.1.2.1

Startup procedure with soꢀ-start

The soꢀ-start function of the TLS4125D0EPV controls the ramp-up of the output voltage with defined timing

t_startduring startup, see Figure 6. If V_VS> V_VS,on, then a "high" signal V_EN,hiat pin EN triggers the startup

procedure. During startup the internal supply establishes a stable state and the device initializes the switching

frequency and the reset function according to the configuration. The regulator then increases the output

voltage V_ccby ramping up the internal voltage reference connected to the error amplifier.

V_VS

V_VS> V_VS,on

0 V

t

V_EN

V_EN,hi

0 V

t

V_CC

Initialization

Soft-start

V_CC,nom

95% of V_CC,nom

5% of V_CC,nom

0 V

t_init

t_start

t

Figure 6

Typical startup procedure

4.1.2.2

Active output discharge

The active output discharge function of the TLS4125D0EPV controls the ramp-down of the output voltage

during power down, see Figure 7. If the device detects a "low" signal V_EN,loat the EN pin, then it switches on the

integrated discharge transistor connected to the SW pin in order to discharge the output capacitor C_OUTvia the

output inductor L_OUT. The typical on-resistance R_dcof the discharge transistor is 55 Ω.

VS

L_OUT

V_CC

SW

Discharge

Internal

supply

current

C_OUT

Discharge

transistor

EN

Discharge

control

GND

Figure 7

Active output discharge block diagram

Datasheet

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Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

4.1.3

Protection features

The device oﬀers features that are designed to protect it from fault events such as overcurrent, overload, input

undervoltage and overtemperature, see Table 4.

4.1.3.1

Overcurrent protection and overload protection

If the sensed current through the high side PMOS power stage exceeds the buck peak overcurrent limit I_BUOC

aꢀer the blanking time of the current sense, then the device switches oﬀ the high side power stage for the

remaining time of the current cycle. Active current limitation can decrease the output voltage level.

If the sensed freewheeling current through the low side NMOS power stage exceeds the overload limit I_BUOL

,

then the device prevents the high side PMOS power stage from switching on in the subsequent clock cycles to

avoid overheating. The overload threshold level is set to a higher value than the overcurrent threshold level.

If an overload condition and an undervoltage condition occur for longer than 3 ms typically, then the device

detects a short circuit at the output voltage node and shuts down. Aꢀer a waiting time of typically 1 s, the

device restarts with a soꢀ-start.

4.1.3.2

Input undervoltage shutdown

The device incorporates an undervoltage shutdown function. If the input voltage V_VSdrops below the input

undervoltage shutdown threshold V_VS,oﬀ, then the device shuts down.

4.1.3.3

Overtemperature protection

The integrated overtemperature protection turns oﬀ the device in case of a too high junction temperature. The

typical junction thermal shutdown temperature is 175°C. Aꢀer the device has cooled down by the amount of the

typical junction temperature hysteresis 10 K and a subsequent waiting time of typically 1 s, the device restarts

with a soꢀ-start to resume normal operation. The thermal shutdown is an integrated protection function to

prevent the immediate destruction of the device during fault conditions. However, a junction temperature

above 150°C is outside of the maximum ratings and reduces the lifetime of the device.

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

4.2

Electrical characteristics buck regulator

Table 4

Electrical characteristics buck regulator

V_VS= 6 V to 35 V; T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or condition

Number

Min. Typ. Max.

Feedback voltage accuracy

V_FB,PWM-1.5

V_FB,PFM,1-2

–

+1.5

+3.5

–

%

V

6 V ≤ V_VS≤ 35 V;

PWM mode

P_4.2.1

P_4.2.2

P_4.2.5

Feedback voltage accuracy

–

6 V ≤ V_VS≤ 35 V;

PFM mode

Feedback voltage V_FB

V_FB

–

0.8

–

MOSFETs

High side MOSFET on-

resistance

R_on,hs

R_on,ls

–

120

70

240

150

mΩ I_CC= 100 mA

P_4.2.7

P_4.2.9

Low side MOSFET on-

resistance

Regulation loop

10)

Maximum duty cycle

D_max

–

100

–

%

P_4.2.11

P_4.2.12

11)

Minimum on-time,

high frequency

t_on,min,hf

78

ns

I

= 1.5 A;

CC

valid for high frequency

operation range

11)

Minimum on-time,

low frequency

t_on,min,lf

–

308

–

ns

I

= 1.5 A;

P_4.2.13

CC

valid for low frequency

operation range

Startup and active discharge¹²⁾

Soꢀ-start time

t_start

0.8

–

1

–

1.2

2.6

6.0

ms V_CCrising from 5% to 95% of P_4.2.14

nominal V_CClevel

Startup initialization time

t_init

ms time from rising edge of V_ENP_4.2.15

(0 V to V_EN,hi) until soꢀ-start

Input voltage startup

threshold

V_VS,on

2.6

V

V_VSincreasing;

V_EN≥ 2 V

P_4.2.16

Output discharge resistance

R_dc

–

55

–

Ω

V_EN= 0 V;

P_4.2.17

V_VS= 13.5 V;

V_SW= 100 mV

Current limitation

Buck peak overcurrent limit

I_BUOC

3.3

3.9

4.5

A

–

P_4.2.19

10

See Functional range and High duty cycle operation.

Specified by design, not subject to production test.

See Power-up and power-down control

11

12

Datasheet

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Rev. 1.02

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

Table 4

Electrical characteristics buck regulator (continued)

V_VS= 6 V to 35 V; T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or condition

Number

Min. Typ. Max.

Overload current limit

I_BUOL

3.9

4.4

5.1

–

A

–

P_4.2.21

P_4.2.22

Overload overcurrent gap

I_BUOL,gap0.05 0.5

Overload current limit is

typically 0.5 A above buck

peak overcurrent limit

Undervoltage shutdown

Input undervoltage shutdown V_VS,oﬀ

threshold

3.3

–

3.55

420

V

V_VSdecreasing

P_4.2.23

P_4.2.24

Input undervoltage shutdown V_VS,hys

180

280

mV

–

hysteresis

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

4.3

Typical performance characteristics buck regulator

FREQ: 2.2 MHz; V_VS= 13.5 V; T_j= 25°C (if not otherwise specified). The shown performance characteristics was

measured on a 4 layer FR4 printed circuit board with external components as recommended in Application

information.

Eﬀiciency

FREQ: 440 kHz; T_j= 25°C; V_CC= 5 V

Eﬀiciency

FREQ: 2.2 MHz; T_j= 25°C; V_CC= 5 V

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

Eﬀiciency

FREQ: 440 kHz; T_j= 25°C; V_CC= 3.3 V

Eﬀiciency

FREQ: 2.2 MHz; T_j= 25°C; V_CC= 3.3 V

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

Line regulation

Load regulation

I_CC= 1 A; V_CC= 5 V

V_VS= 13.5 V; V_CC= 5 V

Line regulation

Load regulation

I_CC= 1 A; V_CC= 3.3 V

V_VS= 13.5 V; V_CC= 3.3 V

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

Output voltage precision

I_CC= 200 mA; V_CC= 5 V

I_CC= 200 mA; V_CC= 3.3 V

Line regulation (low load)

I_CC= 100 µA; V_CC= 5 V

I_CC= 100 µA; V_CC= 3.3 V

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

High side MOSFET on-resistance

Low side MOSFET on-resistance

I_CC= 100 mA

Output discharge resistance

Input undervoltage shutdown threshold

V_EN= 0 V; V_SW= 100 mV

V_VSdecreasing

Datasheet

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Rev. 1.02

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

PFM frequency modulation (CCM)

FREQ: 440 kHz; I_CC= 1.5 A; V_CC= 5 V

FREQ: 2.2 MHz; I_CC= 1.5 A; V_CC= 5 V

PFM frequency modulation (DCM)

FREQ: 440 kHz; T_j= 25°C; V_CC= 5 V

FREQ: 2.2 MHz; T_j= 25°C; V_CC= 5 V

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

PFM frequency modulation (CCM)

FREQ: 440 kHz; I_CC= 1.5 A; V_CC= 3.3 V

FREQ: 2.2 MHz; I_CC= 1.5 A; V_CC= 3.3 V

PFM frequency modulation (DCM)

FREQ: 440 kHz; T_j= 25°C; V_CC= 3.3 V

FREQ: 2.2 MHz; T_j= 25°C; V_CC= 3.3 V

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

PFM boundary

T_j= 25°C; V_CC= 3.3 V

T_j= 25°C; V_CC= 5 V

Buck peak overcurrent limit

Overload current limit

V_VS= 13.5 V

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Buck regulator

Load step response

I_CC: 0.6 A to 2 A to 0.6 A; V_CC= 5 V

I_CC: 0.6 A to 2 A to 0.6 A; V_CC= 3.3 V

V_CC[100 mV/div]

I_CC[2 A/div]

V_CC[100 mV/div]

I_CC[2 A/div]

3.3

V

5 V

0.6 A

-0.5

0

0.5

1

1.5

-0.5

0

0.5

1

1.5

t [ms]

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Oscillator

5

Oscillator

5.1

Functional description oscillator

The integrated clock provides a constant frequency to the regulation loop. In PWM mode the device switches on

and oﬀ the high side and low side power stages at the oscillator frequency f_OSC

.

The oscillator frequency can be set by connecting a resistor R_FREQbetween the FREQ pin and ground, see Table

5, Table 6 and Table 7. The device sets the selected switching frequency during startup.

Table 5

FREQ configuration for typical oscillator frequencies in the low frequency range

R_FREQ[kΩ]¹³⁾

f_OSC[kHz]

320

2.2

3.3

4.7

360

400

≤ 1.0 (or connect FREQ pin directly to GND)

440¹⁴⁾

6.8

10

15

480

520

560

Table 6

FREQ configuration for typical oscillator frequencies in the high frequency range

R_FREQ[kΩ]¹⁵⁾

f_OSC[MHz]

22

33

47

1.6

1.8

2.0

≥ 200 (or leave FREQ pin open)

2.2¹⁶⁾

68

2.4

100

150

2.6

2.8

5.1.1

Synchronization input

In PWM mode the device can synchronize the switching frequency to an external oscillator connected to the

SYNC pin. The internal clock manager triggers at the falling edge of the external signal. The phase shiꢀ towards

the switching frequency can be adjusted with the duty cycle of the external oscillator. 50% duty cycle of the

external oscillator corresponds to a phase shiꢀ of approximately zero. A suitable setting of R_FREQis required

so that the internal operation frequency is equal to the corresponding external synchronization frequency or

above it. This is a prerequisite for the automatic transitions between PWM mode and PFM mode.

As soon as the startup is completed and the device accepts the external signal at the SYNC pin, the

synchronization turns active.

13

Resistor tolerance ≤ 5%.

Default oscillator low frequency.

Resistor tolerance ≤ 5%.

Default oscillator high frequency.

14

15

16

Datasheet

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Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Oscillator

5.1.2

Spread spectrum

In PWM mode, when used without an external clock at the SYNC pin, the TLS4125D0EPV can apply spread

spectrum to optimize EMI performance. The device modulates the switching frequency up and down by a

triangle waveform with a typical frequency of 8.3 kHz within a range of typically ±7.5% of the selected oscillator

frequency. The logical signal on the SSON pin switches spread spectrum on or oﬀ.

5.2

Electrical characteristics oscillator

Table 7

Electrical characteristics oscillator

V_VS= 6 V to 35 V; T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or condition Number

Min.

Typ. Max.

Frequency setting

Default oscillator low frequency

f_osc,1

396

440

2.2

484

kHz

R_FREQ≤ 1.0 kΩ or

connect FREQ pin

directly to GND

P_5.2.1

Default oscillator high frequency

f_osc,2

1.98

2.42

MHz R_FREQ≥ 200 kΩ or P_5.2.2

leave FREQ pin

open

Oscillator frequency

Synchronization input

f_osc,3

f_osc,4

f_osc,5

f_osc,6

f_osc,7

f_osc,8

f_osc,9

f_osc,10

f_osc,11

f_osc,12

f_osc,13

f_osc,14

288

324

360

432

468

504

1.44

1.62

1.8

320

360

400

480

520

560

1.6

1.8

2.0

2.4

2.6

2.8

352

396

440

528

572

616

1.76

1.98

2.2

kHz

R_FREQ= 2.2 kΩ

R_FREQ= 3.3 kΩ

R_FREQ= 4.7 kΩ

R_FREQ= 6.8 kΩ

R_FREQ= 10 kΩ

R_FREQ= 15 kΩ

P_5.2.3

P_5.2.4

P_5.2.5

P_5.2.6

P_5.2.7

P_5.2.8

P_5.2.9

P_5.2.10

P_5.2.11

P_5.2.12

P_5.2.13

P_5.2.14

MHz R_FREQ= 22 kΩ

MHz R_FREQ= 33 kΩ

MHz R_FREQ= 47 kΩ

MHz R_FREQ= 68 kΩ

MHz R_FREQ= 100 kΩ

MHz R_FREQ= 150 kΩ

2.16

2.34

2.52

2.64

2.86

3.08

Synchronization low frequency

capture range

f_sync,lf

320

1.6

3.0

–

560

2.8

–

kHz

¹⁷⁾valid for

oscillator low

frequency range

P_5.2.15

P_5.2.16

Synchronization high frequency

capture range

f_sync,hf

MHz ¹⁷⁾valid for

oscillator high

frequency range

¹⁷⁾5.5V ≤ V_VS≤ 35 V P_5.2.17

SYNC "high" signal

V_SYNC,hi

V

17

Synchronization of PWM to the falling edge.

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Oscillator

Table 7

Electrical characteristics oscillator (continued)

V_VS= 6 V to 35 V; T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or condition Number

Min.

Typ. Max.

17)

SYNC "low" signal

V_SYNC,lo

–

0.8

600

1

V

P_5.2.21

P_5.2.22

P_5.2.25

P_5.2.26

P_5.2.28

17)

SYNC signal hysteresis

SYNC "high" input current

SYNC "low" input current

SYNC signal duty cycle

Spread spectrum

V_SYNC,hys45

255

0.1

–

mV

µA

%

I_SYNC,hi

I_SYNC,lo

D_SYNC

–

V_SYNC= 5 V

V_SYNC= 0 V

–

1

10

90

Spread spectrum "high" signal

V_SSON,hi2.0

V_SSON,lo

–

V

Enables spread

spectrum

P_5.2.29

P_5.2.30

Spread spectrum "low" signal

–

0.8

Disables spread

spectrum

Spread spectrum enable hysteresis V_SSON,hys100

250

1

1000

1.25

mV

µA

–

P_5.2.31

P_5.2.32

Spread spectrum enable "high"

input current

I_SSON,hi

f_SS,mod

f_SS,range

0.7

7.5

–

V_SSON= 5.0 V

Spread spectrum modulation

frequency

8.3

9.3

–

kHz

%

Spread spectrum P_5.2.33

enabled

Spread spectrum modulation

range

±7.5

Spread spectrum P_5.2.34

enabled

17

Synchronization of PWM to the falling edge.

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Oscillator

5.3

Typical performance characteristics oscillator

Oscillator (low frequency)

Oscillator (high frequency)

V_VS= 13.5 V; FREQ: 440 kHz

V_VS= 13.5 V; FREQ: 2.2 MHz

Datasheet

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OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Current consumption and enable

6

Current consumption and enable

6.1

Functional description current consumption and enable

A "high" signal V_EN,hiat the EN pin switches on the regulator. In on-state the device can operate at very low

current consumption I_VS,onto improve the eﬀiciency with low load in PFM mode.

A "low" signal V_EN,loat the EN pin switches the regulator oﬀ. In turned oﬀ-state, the current consumption I_VS,oﬀ

of the device is 1 µA typically. If the EN pin is leꢀ open, then an internal pull-down resistor R_EN,intensures that

the device remains switched oﬀ.

6.2

Electrical characteristics current consumption and enable

Table 8

Electrical characteristics current consumption and enable

V_VS= 6 V to 35 V; T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or condition

Number

Min.

Max.

Current consumption

Current consumption in oﬀ- I_VS,oﬀ

state

–

1

2

µA

V_EN= 0 V;

V_VS= 13.5 V;

T_j< 85°C

P_6.2.1

P_6.2.2

Current consumption in on- I_VS,on

31

65

V_EN= 5.0 V;

state

V_VS= 13.5 V;

T_j< 85°C;

not switching¹⁸⁾

Enable

Enable "high" signal

Enable "low" signal

Enable hysteresis

V_EN,hi

V_EN,lo

V_EN,hys

2.0

–

V

–

P_6.2.3

P_6.2.4

P_6.2.5

P_6.2.6

P_6.2.7

P_6.2.8

–

0.8

1000

1

V

–

100

–

400

0.6

2.5

8

mV

µA

MΩ

–

Enable "high" input current I_EN,hi,1

Enable "high" input current I_EN,hi,2

V_EN= 5.0 V

V_EN= 13.5 V

V_EN= 2.0 V

–

3.5

10.4

Enable, internal resistor to R_EN,int

5.6

GND

18

The current consumption is tested while the output voltage is forced to a slightly higher value than the

nominal output voltage to prevent switching activities of the regulator.

Datasheet

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2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Current consumption and enable

6.3

Typical performance characteristics current consumption and

enable

Current consumption in oﬀ-state

V_VS= 13.5 V; V_EN= 0 V

Current consumption in on-state

V_VS= 13.5 V; V_EN= 5 V; no switching

Enable "high" input current

V_VS= 13.5 V

Datasheet

32

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Reset

7

Reset

7.1

Functional description reset

The reset function supervises the regulator output voltage V_CCby monitoring the feedback voltage V_FB. The

device indicates the reset status at the RO pin. RO "high" indicates, that the output voltage is within the desired

reset thresholds. RO "low" indicates that the output voltage is outside the desired reset thresholds. As long as

the device operates within the specified range, the reset function is active, see Table 10 and Functional range.

Reset output RO

The reset output pin RO is an open drain structure and needs to be pulled up to V_CCor to a voltage rail via an

external pull-up resistor R_RO, which must be chosen according to the maximum pull-up current I_RO,lo. During

battery cranking conditions of the input voltage V_VS, the reset feature is active down to an input voltage V_VSof

2.8 V.

Power-on reset delay time

Power-on reset delay time t_RD,PWR-onis the time period from completion of the soꢀ-start until the device

releases the reset by switching the reset output RO from "low" to "high", see Figure 8. An external resistor R_RT

connected to the RT pin determines the value of power-on reset delay time t_RD,PWR-on, see Table 9.

Reset undervoltage, overvoltage and delay time

In contrast to the power-on reset delay time t_RD,PWR-on, the reset delay time t_RDrefers to an output undervoltage

or output overvoltage event during operation, see Figure 8. If V_FBdrops below the undervoltage reset threshold

V_RT,UV,th, then the device sets the reset signal at the RO to "low". When the output voltage recovers and V_FB

exceeds the undervoltage reset threshold plus the hysteresis (V_RT,UV,th+ V_RT,UV,hys), then the device sets the

RO pin to "high" aꢀer the reset delay time t_RD. In accordance with the undervoltage reset delay time, the

overvoltage reset delay time t_RDconsiders an output overvoltage event. If case V_FBexceeds the overvoltage

reset threshold V_RT,OV,th, then the device sets the RO pin to "low". When the output voltage recovers and V_FB

drops below the overvoltage reset threshold minus the hysteresis (V_RT,OV,th- V_RT,OV,hys), then the device sets the

RO pin to "high" aꢀer the reset delay time t_RD. An external resistor R_RTconnected to the RT pin determines the

value of the reset delay time t_RDalong with the reset undervoltage threshold V_RT,UV,th, see Table 9. The device

sets the selected reset delay time and reset threshold during initialization phase. The value of the overvoltage

reset threshold V_RT,OV,this fixed.

Reset reaction time

If the output voltage of the regulator drops below the output undervoltage reset threshold V_RT,UV,thor rises

above the output overvoltage reset threshold V_RT,OV,th, then this triggers the internal output voltage monitoring

circuit. If that condition lasts longer than the blanking time t_r,blank(see Table 10), then the device sets the reset

signal at the RO pin to "low". If the output overvoltage or undervoltage condition lasts shorter than t_r,blank, then

the device keeps the reset signal "high". This prevents a microcontroller reset due to very short distortions of

the output voltage, see Figure 8.

Datasheet

33

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Reset

Table 9

RT configuration for typical values of power-on, undervoltage, overvoltage reset delay

time and undervoltage reset threshold

R_RT[kΩ]¹⁹⁾

t_RD,PWR-on[ms]

t_RD[ms]

V_RT,UV,th[% of V_FB]

20)

≤ 1.0 (or connect to GND)

0.06

1.9

0.03

1.3

-8

2.2

-14

-25

-40

-8

3.3

4.7

6.8

10

1.9

1.3

-14

-25

-40

-14

-25

-40

-8

15

1.9

1.3

22

1.9

1.3

33

7.7

5.1

47

7.7

5.1

68

7.7

5.1

100

15.4

7.7

10.2

5.1

150

-14

-8

≥ 200 (or leave open)

V

EN

V

EN,hi

EN,lo

Soft-

start

Undervoltage

Short undervoltage

Undervoltage

Overvoltage

t

VCC

t < t^r,blank

V

RT,OV,th

RT,UV,th

t

VRO

t

RD,PWR-on

t

r,blank

t

RD

t

r,blank

t

RD

t

r,blank

t

RD

VPU

V

RO,lo

t

Figure 8

Reset timing diagram²¹⁾

19

Resistor tolerance ≤ 5%.

In relation to the typical feedback voltage level 0.8 V.

The diagram neglects the reset undervoltage hysteresis and reset overvoltage hysteresis to improve the

20

21

overview. V_ROis connected to an external pull-up voltage V_PUvia an external pull-up resistor. The input

voltage V_VSis set to a level higher than V_VS,on

.

Datasheet

34

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Reset

7.2

Electrical characteristics reset

Table 10

Electrical characteristics reset

V_VS= 6 V to 35 V; T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or condition

Number

Min. Typ. Max.

Reset output RO

Reset output "low" voltage V_RO,lo

–

0.4

1.5

1

V

V_EN≥ 2 V;

I_RO≤ 1.5 mA

P_7.2.1

P_7.2.2

P_7.2.3

Reset output "low" pull-up I_RO,lo

current

mA

µA

V_EN≥ 2 V;

V_RO= 0.4 V

Reset output "high"

leakage current

I_RO,hi

V_RO= 5 V

Output overvoltage reset threshold

Output overvoltage reset

threshold increasing

V_RT,OV,th

5

–

7

1

9

2

%

percentage of V_FB

P_7.2.4

P_7.2.5

Output overvoltage reset

hysteresis

V_RT,OV,hys

Output undervoltage reset threshold²²⁾

Output undervoltage reset V_RT,UV,th,1

threshold decreasing -8%

-10

-16

-27

-42

–

-8

-6

%

percentage of V_FB

P_7.2.6

P_7.2.7

P_7.2.8

P_7.2.9

P_7.2.10

Output undervoltage reset V_RT,UV,th,2

threshold decreasing -14%

-14

-25

-40

1

-12

-23

-38

2

Output undervoltage reset V_RT,UV,th,3

threshold decreasing -25%

Output undervoltage reset V_RT,UV,th,4

threshold decreasing -40%

Output undervoltage reset V_RT,UV,hys

hysteresis

Reset delay timing²²⁾

Power-on reset delay time t_RD,PWR-on,115

60 µs

60

90

µs

–

P_7.2.11

P_7.2.12

P_7.2.13

P_7.2.14

P_7.2.15

Power-on reset delay time t_RD,PWR-on,21.7

1.9 ms

1.9

7.7

2.2

8.6

17.1

95

ms

µs

Power-on reset delay time t_RD,PWR-on,36.9

7.7 ms

Power-on reset delay time t_RD,PWR-on,413.9 15.4

15.4 ms

Reset delay time 30 µs

t_RD,1

15

30

22

For RT configuration see Table 9

Datasheet

35

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Reset

Table 10

Electrical characteristics reset (continued)

V_VS= 6 V to 35 V; T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or condition

Number

Min. Typ. Max.

Reset delay time 1.3 ms

Reset delay time 5.1 ms

Reset delay time 10.2 ms

Reset blanking time

t_RD,2

1.1

4.6

9.3

2

1.3

5.1

10.2

5

1.5

5.7

11.4

10

ms

µs

–

P_7.2.16

P_7.2.17

P_7.2.18

P_7.2.19

t_RD,3

t_RD,4

t_r,blank

Datasheet

36

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Reset

7.3

Typical performance characteristics reset

Output undervoltage reset threshold

Output overvoltage reset threshold

V_VS= 13.5 V

Datasheet

37

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Application information

8

Application information

Note:

The following information is given as an example for the implementation of the device only and shall

not be regarded as a description or warranty of a certain functionality, condition or quality of the

device.

D_IN*)

L_IN**)

V_BAT

C_IN3**)

C_IN2

C_IN1

VS

EN

Enable signal (e.g. from IGN)

Enable

UVLO

Internal

supply

Over

temperature

shutdown

Bandgap

reference

R_FREQ*)

FREQ

L_OUT

SW

Control loop

+ driver

V_CC

C_FF

R₁

R₂

Oscillator

Synchronisation signal (e.g. from µC)

SYNC

SSON

PGND

FB

C_OUT

High signal

(e.g. V^CC)

Spread

spectrum

ON/OFF control for

spread spectrum

V_PU

pull-up voltage

Soft-start

ramp

generator

R_RO

RO

RT

Reset

Reset signal

(e.g. indicate output voltage status to µC)

R_RT*)

AGND

*) optional

**) optional for improved EMI performance

Figure 9

Application diagram

Note:

This figure is a simplified example of an application circuit. The function must be verified in the

application.

Datasheet

38

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Application information

Table 11

Name

Recommended values for components in the application diagram

Value²³⁾

Switching

frequency range range

Output voltage

Component type

C_IN1

C_IN2

L_OUT

100 nF

10 µF

22 µH

–

Ceramic X7R capacitor; 50 V

320 kHz to

560 kHz

Shielded power inductor; I_SAT> I_BUOC

DCR < 70 mΩ

C_OUT

L_OUT

C_OUT

L_OUT

88 µF²⁴⁾

2.2 µH

320 kHz to

560 kHz

–

22 µF (x4) ceramic X7R capacitor; 16 V

1.6 MHz to

2.8 MHz

3 V ≤ V_CC≤ 5 V

Shielded power inductor; I_SAT> I_BUOC

DCR < 70 mΩ

44 µF²⁴⁾

4.7 µH

1.6 MHz to

2.8 MHz

3 V ≤ V_CC≤ 5 V

5 V < V_CC≤ 10 V

22 µF (x2) ceramic X7R capacitor; 16 V

1.6 MHz to

2.8 MHz

Shielded power inductor; I_SAT> I_BUOC

DCR < 70 mΩ

C_OUT

22 µF²⁴⁾

1.6 MHz to

2.8 MHz

5 V < V_CC≤ 10 V

22 µF ceramic X7R capacitor; 25 V

8.1

Output voltage adjustment

The output voltage of the TLS4125D0EPV can be adjusted with an external voltage divider connected to the FB

pin. To achieve a high output voltage accuracy, a resistor R₂< 160 kΩ is recommended. By neglecting the current

flowing into the FB pin, the desired resistance R₁can be calculated depending on the required nominal output

voltage V_CC

:

V

CC

FB

R = R

− 1

1

2

V

Equation 1

8.2

Feedforward capacitor

An additional feedforward capacitor C_FFbetween the output voltage node V_CCand the feedback pin FB might be

required for stable operation (see Figure 9). A good starting value is a feedforward capacitor of 10 pF, but the

best value may be higher due to additional parasitic capacitance at the FB pin to GND resulting from the PCB

layout. The capacitance must match the conditions of the application.

23

Typical condition

24

For maintenance of loop stability it is recommended to use capacitors with a limited voltage derating at

the typical output voltage level. A capacitor in parallel can be added to match the recommended typical

capacitance value as close as possible.

Datasheet

39

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Application information

8.3

Layout recommendations

Introduction

A switch mode power supply is a potential source of electromagnetic disturbance, which may aﬀect the

application environment as well as the device itself. This can lead to sporadic malfunction including regulator

instability or irreversible damage depending on the amount of generated disturbance.

Main types of electromagnetic disturbance:

•

Radiated emission

Conducted emission

Radiated emission

Radiated emission is caused by circulating currents and voltage oscillations. Alternating currents appear in so

called current windows, which are defined by the area of the circulating current within the corresponding filter

stage at the input or the output of the regulator. Voltage oscillations are mainly caused by resonant circuits

induced by parasitic inductance and capacitance of the PCB layout.

The following PCB layout design recommendations help to minimize radiated emission:

•

Place external components close to the device to reduce parasitic elements of the PCB layout and to

keep the area of circulating currents small. At the same time some distance should be kept between the

components to avoid coupling.

Reduce the switching area at pin SW to minimize the inductance and especially the parasitic capacitance.

The parasitic capacitance can be further reduced by removing inner GND layers below the switching area.

Routing of other signal traces below the switching area should be avoided generally.

Use GND layers to shield areas with alternating currents or voltage oscillations.

Conducted emission

Conducted emission consists of voltage oscillations, which occur permanently or by occasion at the regulator

input or output connection. Their frequency range can exceed 100 MHz and they are superimposed to the input

voltage V_VSand to the output voltage V_CC. This might disturb other components of the application.

Countermeasures against conducted disturbances are the same as against radiated emission. The following

recommendations can further reduce the conducted emission:

•

Reduce high frequency conducted emission by placing well connected small ceramic filter capacitors (1 nF

to 220 nF) with low ESR and low ESL in parallel to the input capacitors as close as possible to the input pin

VS and in parallel to the output capacitor C_OUTclose to the output inductor L_OUT

.

•

Reduce noise injected into the battery supply line by using a π-filter, for example consisting of C_IN1, C_IN2

,

C_IN3and L_IN. This requires additional capacitors and an inductor. The filter must be designed according to

the requirements of the application.

8.4

Additional information

Please contact Infineon:

•

for information regarding the pin behavioral assessment

for application notes with more detailed information about this device

for any further information visit https://www.infineon.com/

Datasheet

40

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Package information

9

Package information

1)

4.9±0.1

1)

3.9±0.1

0.1

2x

0.67±0.25

C

0.08 C

Coplanarity

Seating

Plane

6±0.2

0.2 D

14x

2)

0.25±0.05

0.25

A-B C

14x

Bottom View

A

14

8

14

1

7

1

0.15

D

Index

Marking

B

0.65

4±0.1

A-B

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width.

All dimensions are in units mm

The drawing is in compliance with ISO 128-30, Projection Method 1 [

]

Figure 10

PG-TSDSO-14

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a Green Product. Green Products are RoHS compliant (Pb-free

finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Information on alternative packages

Please visit www.infineon.com/packages.

Datasheet

41

Rev. 1.02

2021-02-05

OPTIREG^™switcher TLS4125D0EPV

2.8 MHz synchronous step down regulator

Revision history

Version Date

Changes

Rev. 1.02 2021-02-05 Editorial changes

Rev. 1.01 2020-10-15 Editorial changes

Rev. 1.0 2020-03-20 Initial datasheet

Datasheet

42

Rev. 1.02

2021-02-05

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

Edition 2021-02-05

Published by

IMPORTANT NOTICE

WARNINGS

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaﬀenheitsgarantie”).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer’s compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer’s products and any use of the product of

Infineon Technologies in customer’s applications.

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies oﬀice.

Except as otherwise explicitly approved by Infineon

Technologies in

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or

any consequences of the use thereof can reasonably

be expected to result in personal injury.

Infineon Technologies AG

81726 Munich, Germany

a written document signed by

©

2021 Infineon Technologies AG

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Document reference

IFX-Z8F64777586

The data contained in this document is exclusively

intended for technically trained staﬀ. It is the

responsibility of customer’s technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to such

application.


型号：	TLS4125D0EPV
厂家：	Infineon
描述：	OPTIREG™开关TLS4125D0EPV是一款同步降压型DC-DC转换器，专为汽车应用而设计。该器件的电流能力为2.5 A，输出电压可调, PWM模式下的反馈电压精度为+/- 1.5%。器件集成功率级、软启动和补偿功能，从而减少所需的外部组件数量，进而降低了系统成本并节省板空间。宽输入电压范围(3.7 V – 35V)和100%占空比运行模式使该器件适用汽车应用的电池启动场景。器件的宽开关频率范围使得可以选用适当的电感和电容。开关频率可以与外部时钟信号同步。在PWM模式下，可以启动扩频调频功能来改善电磁干扰。在轻负载时，器件在PFM模式下工作，电流消耗低，从而提高了效率。在停用模式下, 电流消耗降低到典型值1μA。TLS4125D0EPV能够检测输出电压的欠压或过压，并通过复位输出信号来反映。过流和过载保护可以避免出现过电流，从而在降压转换器输出端发生短路时保护器件。此外，集成的热关断功能还可以防止器件过热。增强裸露焊盘的PG-TSDSO-14封装能够提升器件热性能。时钟电池开关 DC-DC转换器软启动过载保护
文件：	总43页 (文件大小：6078K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLS4125D0EPV [INFINEON]

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