TLS850D0TE V50 [INFINEON]
TLS850D0TEV50 是一款高性能的极低压差线性稳压器,采用 PGTO252-5 封装,适用于 5V 电源。这些稳压器的输入电压范围为 3 V 至 40 V,静态电流极低(仅 40μA),非常适合汽车或永久连接电池的任何其他电源系统。TLS850D0TAV50 的输出电压精度为 2%,最大输出电流高达 500 mA。新的回路概念结合了快速调节和非常好的稳定性,输出端只需要一个 1μF 的小型陶瓷电容即可。在低于 100 mA 的电流下,该设备的典型压差非常低,仅 70 mV。工作范围从仅 3 V 的输入电压开始(扩展工作范围)。因此,TLS850D0TAV50 也适用于需要在启动条件下运行的汽车系统。;型号: | TLS850D0TE V50 |
厂家: | Infineon |
描述: | TLS850D0TEV50 是一款高性能的极低压差线性稳压器,采用 PGTO252-5 封装,适用于 5V 电源。这些稳压器的输入电压范围为 3 V 至 40 V,静态电流极低(仅 40μA),非常适合汽车或永久连接电池的任何其他电源系统。TLS850D0TAV50 的输出电压精度为 2%,最大输出电流高达 500 mA。新的回路概念结合了快速调节和非常好的稳定性,输出端只需要一个 1μF 的小型陶瓷电容即可。在低于 100 mA 的电流下,该设备的典型压差非常低,仅 70 mV。工作范围从仅 3 V 的输入电压开始(扩展工作范围)。因此,TLS850D0TAV50 也适用于需要在启动条件下运行的汽车系统。 电池 稳压器 |
文件: | 总29页 (文件大小:1154K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Low Dropout Linear Voltage Regulator
TLS850D0TE
TLS850D0TEV50
TLS850D0TEV33
Linear Voltage Regulator
Data Sheet
Rev. 1.0, 2016-10-07
Automotive Power
TLS850D0TE
Table of Contents
Table of Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment TLS850D0TEV50 and TLS850D0TEV33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions TLS850D0TEV50 and TLS850D0TEV33 . . . . . . . . . . . . . . . . . . . . . . . 6
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
4.2
4.3
5
Block Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance Characteristics Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical Performance Characteristics Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical Performance Characteristics Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical Performance Characteristics Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
6
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Selection of External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.5
7
8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Data Sheet
2
Rev. 1.0, 2016-10-07
Low Dropout Linear Voltage Regulator
TLS850D0TE
1
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Input Voltage Range from 3.0 V to 40 V
Fixed Output Voltage 5 V or 3.3 V
Output Voltage Precision ≤ ±2 %
Output Current Capability up to 500 mA
Ultra Low Current Consumption typ. 40 µA
Very Low Dropout Voltage typ. 70 mV @100 mA
Stable with Ceramic Output Capacitor of 1 µF
Delayed Reset at Power-On: 16.5 ms
Enable, Undervoltage Reset, Overtemperature Shutdown
Output Current Limitation
Figure 1
PG-TO252-5
Wide Temperature Range
Green Product (RoHS compliant)
AEC Qualified
Data Sheet
3
Rev. 1.0, 2016-10-07
TLS850D0TE
Overview
Functional Description
The TLS850D0TE is a high performance very low dropout linear voltage regulator for 5 V (TLS850D0V50) or 3.3 V
(TLS850D0V33) supply in a PG-TO252-5 package.
With an input voltage range of 3 V to 40 V and very low quiescent of only 40 µA, these regulators are perfectly
suitable for automotive or any other supply systems connected to the battery permanently. The TLS850D0TE
provides an output voltage accuracy of 2 % and a maximum output current up to 500 mA.
The new loop concept combines fast regulation and very good stability while requiring only one small ceramic
capacitor of 1 µF at the output. At currents below 100 mA the device will have a very low typical dropout voltage
of only 70 mV (for 5 V device) and 80 mV (for 3.3 V device). The operating range starts already at input voltages
of only 3 V (extended operating range). This makes the TLS850D0TE also suitable to supply automotive systems
that need to operate during cranking condition.
The device can be switched on and off by the Enable feature as described in Chapter 5.5.
The output voltage is supervised by the Reset feature, including Undervoltage Reset and delayed Reset at Power-
On, more details can be found in Chapter 5.7.
Internal protection features like output current limitation and overtemperature shutdown are implemented to
protect the device against immediate damage due to failures like output short circuit to GND, over-current and
over-temperatures.
Choosing External Components
An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for
the stability of the regulating circuit. TLS850D0TE is designed to be also stable with low ESR ceramic capacitors.
Type
Package
Marking
TLS850D0TEV50
TLS850D0TEV33
PG-TO252-5
PG-TO252-5
850D0V50
850D0V33
Data Sheet
4
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Diagram
2
Block Diagram
I
Q
Current
Limitation
RO
Reset
EN
Enable
Bandgap
Reference
Temperature
Shutdown
GND
Figure 2
Block Diagram TLS850D0TEV50 and TLS850D0TEV33
Data Sheet
5
Rev. 1.0, 2016-10-07
TLS850D0TE
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment TLS850D0TEV50 and TLS850D0TEV33
GND
1
5
Figure 3
Pin Configuration
3.2
Pin Definitions and Functions TLS850D0TEV50 and TLS850D0TEV33
Pin
Symbol
Function
1
I
Input
It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close
to the IC terminals, in order to compensate line influences. See also Chapter 6.2.1
2
EN
Enable (integrated pull-down resistor)
Enable the IC with high level input signal;
Disable the IC with low level input signal;
3
4
GND
RO
Ground
Reset Output (intergrated pull-up resistor to Q)
Open collector output;
Leave open if the reset function is not needed
5
Q
Output Voltage
Connect output capacitor CQ to GND close to the IC’s terminals, respecting the
values specified for its capacitance and ESR in “Functional Range” on Page 8
Heat
Slug
GND
Heat Slug
Connect to GND
Connect to heatsink area;
Data Sheet
6
Rev. 1.0, 2016-10-07
TLS850D0TE
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min. Typ. Max.
Input I, Enable EN
Voltage
VI, VEN
-0.3
-0.3
–
–
45
7
V
V
–
P_4.1.1
P_4.1.3
Output Q, Reset Output RO
Voltage
VQ, VRO
–
Temperatures
Junction Temperature
Storage Temperature
ESD Absorption
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_4.1.7
P_4.1.8
Tstg
ESD Susceptibility to GND
ESD Susceptibility to GND
VESD
VESD
-2
–
–
–
2
kV
V
2) HBM
3) CDM
3) CDM
P_4.1.9
-500
-750
500
750
P_4.1.10
P_4.1.13
ESD Susceptibility Pin 1, 5 (corner pins) VESD1,5
to GND
V
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Note:
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
7
Rev. 1.0, 2016-10-07
TLS850D0TE
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Number
Min.
V
Max.
40
1)
Input Voltage Range
VI
Q,nom + Vdr
–
–
–
–
V
–
–
P_4.2.1
P_4.2.3
P_4.2.5
P_4.2.6
2)
Extended Input Voltage Range
Enable Voltage Range
VI,ext
VEN
CQ
3.0
0
40
V
40
V
–
3)4)
Output Capacitor’s
1
–
µF
–
Requirements for Stability
3)
ESR
ESR(CQ) –
Tj -40
–
–
100
150
Ω
–
P_4.2.7
P_4.2.9
Junction Temperature
°C
–
1) Output current is limited internaly and depends on the input voltage, see Electrical Characteristics for more details.
2) When VI is between VI,ext,min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V.
3) Not subject to production test, specified by design.
4) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
Note:Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
Data Sheet
8
Rev. 1.0, 2016-10-07
TLS850D0TE
General Product Characteristics
4.3
Thermal Resistance
Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3
Thermal Resistance
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Number
Min.
Max.
Package Version PG-TO252-5
Junction to Case
1)
RthJC
RthJA
RthJA
–
–
–
3
–
–
–
K/W
K/W
K/W
–
P_4.3.11
P_4.3.12
P_4.3.13
Junction to Ambient
26
109
1)2) 2s2p board
1)3) 1s0p board,
Junction to Ambient
footprint only
Junction to Ambient
Junction to Ambient
RthJA
–
–
51
40
–
–
K/W
K/W
1)3) 1s0p board,
300 mm2 heatsink
area on PCB
1)3) 1s0p board,
600 mm2 heatsink
area on PCB
P_4.3.14
P_4.3.15
RthJA
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
9
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5
Block Description and Electrical Characteristics
5.1
Voltage Regulation
The output voltage VQ is divided by a resistor network. This fractional voltage is compared to an internal voltage
reference and the pass transistor is driven accordingly.
The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the
internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent series
resistor (ESR) requirements given in “Functional Range” on Page 8 have to be maintained. For details, also see
the typical performance graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on
Page 15. As the output capacitor also has to buffer load steps, it should be sized according to the application’s
needs.
An input capacitor CI is recommended to compensate line influences. In order to block influences like pulses and
HF distortion at input side, an additional reverse polarity protection diode and a combination of several capacitors
for filtering should be used. Connect the capacitors close to the component’s terminals.
In order to prevent overshoots during start-up, a smooth ramp up function is implemented. This ensures almost
no output voltage overshoots during start-up, mostly independent from load and output capacitance.
Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited
and the output voltage decreases.
The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g.
output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed. However, junction
temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.
Regulated
Output Voltage
Supply
IQ
II
I
Q
Current
Limitation
RO
Reset
EN
Enable
C
CI
VI
VQ
Bandgap
Reference
LOAD
ESR
Temperature
Shutdown
CQ
GND
Figure 4
Voltage Regulation
V
VI
Vdr
VQ,nom
VI,ext,min
VQ
t
Figure 5
Output Voltage vs. Input Voltage
Data Sheet
10
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
Table 4
Electrical Characteristics Voltage Regulator 5 V version
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Output Voltage Precision
Output Voltage Precision
VQ
VQ
4.9
5.0
5.0
7.5
5.1
5.1
18
V
V
0.05 mA < IQ < 500 mA
5.95 V < VI < 28 V
P_5.1.3
P_5.1.4
P_5.1.7
4.9
0.05 mA < IQ < 200 mA
5.44 V < VI < 40 V
Output Voltage Start-up
slew rate
dVQ/dt 3.0
V/ms VI > 18 V/ms
CQ = 1 µF
0.5 V < VQ < 4.5 V
650 1100 mA 0 V < VQ < 4.8 V
Output Current Limitation
IQ,max
501
P_5.1.9
Load Regulation
steady-state
∆VQ,load -20
-1.5
5
mV
IQ = 0.05 mA to 500 mA
VI = 6 V
P_5.1.11
Line Regulation
steady-state
∆VQ,line -20
0
20
mV
VI = 8 V to 32 V
IQ = 5 mA
P_5.1.13
P_5.1.16
P_5.1.17
P_5.1.18
P_5.1.19
P_5.1.20
Dropout Voltage
Vdr = VI - VQ
Vdr
–
175 425 mV 1) IQ = 250 mA
Dropout Voltage
Vdr = VI - VQ
Vdr
–
70
59
–
170 mV 1) IQ = 100 mA
Power Supply Ripple Rejection
PSRR
Tj,sd
Tj,sdh
–
–
dB
2) fripple = 100 Hz
ripple = 0.5 Vpp
V
Overtemperature Shutdown
Threshold
151
–
200 °C
2) Tj increasing
Overtemperature Shutdown
Threshold Hysteresis
15
–
K
2) Tj decreasing
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V
2) Not subject to production test, specified by design
Data Sheet
11
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
Table 5
Electrical Characteristics Voltage Regulator 3.3 V version
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Output Voltage Precision
Output Voltage Precision
VQ
VQ
3.23 3.3
3.37
3.37
18
V
V
0.05 mA < IQ < 500 mA
4.23 V < VI < 28 V
P_5.1.23
P_5.1.24
P_5.1.27
3.23 3.3
0.05 mA < IQ < 200 mA
3.72 V < VI < 40 V
Output Voltage Start-up
slew rate
dVQ/dt 3.0
7.5
V/ms VI > 18 V/ms
CQ = 1 µF
0.33 V < VQ < 2.97 V
650 1100 mA 0 V < VQ < 3.1 V
Output Current Limitation
IQ,max
501
P_5.1.29
P_5.1.31
Load Regulation
steady-state
∆VQ,load -20
-1.5
5
mV
IQ = 0.05 mA to 500 mA
VI = 6 V
Line Regulation
steady-state
∆VQ,line -15
0
15
mV
VI = 8 V to 32 V
IQ = 5 mA
P_5.1.33
P_5.1.36
P_5.1.37
P_5.1.38
P_5.1.39
P_5.1.40
Dropout Voltage
Vdr = VI - VQ
Vdr
–
200 430 mV 1) IQ = 250 mA
Dropout Voltage
Vdr = VI - VQ
Vdr
–
80
63
–
175 mV 1) IQ = 100 mA
Power Supply Ripple Rejection
PSRR
Tj,sd
Tj,sdh
–
–
dB
2) fripple = 100 Hz
ripple = 0.5 Vpp
V
Overtemperature Shutdown
Threshold
151
–
200 °C
2) Tj increasing
Overtemperature Shutdown
Threshold Hysteresis
15
–
K
2) Tj decreasing
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V
2) Not subject to production test, specified by design
Data Sheet
12
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5.2
Typical Performance Characteristics Voltage Regulator
Typical Performance Characteristics
Output Voltage VQ versus
Output Voltage VQ versus
Junction Temperature Tj (3.3 V version)
Junction Temperature Tj (5 V version)
3.5
IQ = 100mA
IQ = 100mA
3.45
3.4
5.15
5.1
5.05
5
3.35
3.3
3.25
3.2
4.95
4.9
3.15
3.1
4.85
4.8
0
50
100
150
0
50
100
150
Tj [°C]
Tj [°C]
Dropout Voltage Vdr versus
Dropout Voltage Vdr versus
Junction Temperature Tj (3.3 V version)
Junction Temperature Tj (5 V version)
350
350
IQ = 100 mA
IQ = 100 mA
IQ = 250 mA
300
IQ = 250 mA
300
VQ = 3.3 V
250
200
150
100
50
250
200
150
100
50
0
0
−40
0
50
Tj [°C]
100
150
−40
0
50
Tj [°C]
100
150
Data Sheet
13
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
Load Regulation ∆VQ,load versus
Output Current Change IQ
Line Regulation ∆VQ,line versus
Input Voltage VI
8
0
−2
IQ = 5 mA
Tj = −40 o
Tj = 25 o
Tj = 150 oC
C
C
6
4
−4
−6
2
−8
−10
−12
0
−2
−4
−6
−8
−14
VI = 6 V
−16
Tj = −40 o
C
Tj = 25 o
Tj = 150 oC
100 200
C
−18
−20
0
300
IQ [mA]
400
500
10
15
20
25
30
VI [V]
Output Voltage VQ versus
Output Voltage VQ versus
Input Voltage VI (3.3 V version)
Input Voltage VI (5 V version)
4
6
Tj = −40 °C
Tj = −40 °C
Tj = 25 °C
Tj = 25 °C
3.5
5
Tj = 150 °C
Tj = 150 °C
IQ = 100 mA
3
IQ = 100 mA
4
2.5
2
3
2
1
0
1.5
1
0.5
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VI [V]
VI [V]
Data Sheet
14
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
Power Supply Ripple Rejection PSRR versus
ripple frequency f
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
80
103
VQ = 3.3 V
VQ = 5 V
70
Unstable Region
102
60
50
40
30
101
Stable Region
100
20
10−1
IQ = 10 mA
C
Q = 1 μF
ripple = 0.5 Vpp
T = 25 o
CQ = 1 μF
10
V
C
Tj = 25 o
C
j
0
10−2
0.05
10−2
10−1
100
101
102
103
1
10
IQ [mA]
100
500
f [kHz]
Maximum Output Current IQ versus
Input Voltage VI
Dropout Voltage Vdr versus
Output Current IQ
1200
1000
800
500
VQ = 3.3 V
450
VQ = 5 V
Tj = 25 o
C
400
350
300
250
200
150
100
50
600
400
VQ = 0 V
Tj = −40 oC
Tj = 25 oC
Tj = 150 oC
30
200
0
0
0
100
200
300
400
500
0
10
20
40
IQ [mA]
VI [V]
Data Sheet
15
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5.3
Current Consumption
Table 6
Electrical Characteristics Current Consumption
Tj = -40 °C to +150 °C, VI = 13.5 V (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Current Consumption
Iq = II
Iq,off
Iq,off
Iq
–
–
–
–
–
1.3
5
µA
µA
µA
µA
µA
V
V
EN = 0 V; Tj < 105 °C
EN = 0.4 V; Tj < 125 °C
P_5.3.1
P_5.3.3
P_5.3.4
P_5.3.7
P_5.3.11
Current Consumption
Iq = II
–
8
Current Consumption
Iq = II - IQ
40
62
62
52
77
82
IQ = 0.05 mA
Tj = 25 °C
Current Consumption
Iq = II - IQ
Iq
IQ = 0.05 mA
Tj < 125 °C
1) IQ = 500 mA
Tj < 125 °C
Current Consumption
Iq = II - IQ
Iq
1) Not subject to production test, specified by design
Data Sheet
16
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5.4
Typical Performance Characteristics Current Consumption
Typical Performance Characteristics
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Input Voltage VI
200
100
Tj = 25 o
C
Tj = −40 °C
180
90
80
70
60
50
40
30
20
10
0
Tj = 25 °C
Tj = 150 °C
160
VEN = 5 V
IQ = 50 uA
140
120
100
80
60
40
20
0
0
100
200
300
400
500
5
10
15
20
VI [V]
25
30
35
40
IQ [mA]
Data Sheet
17
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5.5
Enable
The TLS850D0TE can be switched on and off by the Enable feature: Connect a HIGH level as specified below
(e.g. the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to
shut it down. The enable has a built in hysteresis to avoid toggling between ON/OFF state, if signals with slow
slopes are applied to the EN input.
Table 7
Electrical Characteristics Enable
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min. Typ. Max.
High Level Input Voltage
Low Level Input Voltage
Enable Threshold Hysteresis
High Level Input Current
High Level Input Current
VEN,H
VEN,L
VEN,Hy
IEN,H
2
–
–
–
–
–
–
V
VQ settled
VQ ≤ 0.1 V
–
P_5.5.1
P_5.5.2
P_5.5.3
P_5.5.4
P_5.5.6
P_5.5.7
–
0.8
–
V
100
–
mV
µA
µA
MΩ
3.5
22
2.6
V
V
–
EN = 3.3 V
IEN,H
–
EN ≤ 18 V
Enable internal pull-down resistor REN
0.95 1.5
Data Sheet
18
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5.6
Typical Performance Characteristics Enable
Typical Performance Characteristics
Input Current IIN versus
Input Voltage VIN (condition: VEN = 0 V)
Enabled Input Current IEN versus
Enabled Input Voltage VEN
30
50
Tj = −40 °C
Tj = −40 °C
45
Tj = 25 °C
Tj = 25 °C
25
Tj = 150 °C
Tj = 150 °C
40
35
30
25
20
15
10
5
VEN = 0V
20
15
10
5
0
0
0
10
20
30
40
0
10
20
30
40
VIN [V]
VEN [V]
Output Voltage VQ versus
Output Voltage VQ versus
time (EN switched ON, 5 V version)
time (EN switched ON, 3.3 V version)
6
6
5
4
3
2
5
4
3
2
IQ = 100 mA
Tj = −40 °C
IQ = 100 mA
Tj = −40 °C
Tj = 25 °C
Tj = 150 °C
VEN
Tj = 25 °C
Tj = 150 °C
VEN
1
0
1
0
0
500
1000
t [us]
1500
2000
0
500
1000
t [us]
1500
2000
Data Sheet
19
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5.7
Reset
The TLS850D0TE’s output voltage is supervised by the Reset feature, including Undervoltage Reset and delayed
Reset at Power-On.
The Undervoltage Reset function sets the pin RO to LOW, in case VQ is falling for any reason below the Reset
Threshold VRT,low
.
When the regulator is powered on, the pin RO is held at LOW for the duration of the Power-On Reset Delay Time
trd.
Supply
I
Q
VDD
RRO,int
CQ
Control
RO
Reset
S
R
IRO
Reference
Q
OR
Micro-
Controller
Timer
GND
GND
Figure 6
Block Diagram Reset Circuit
Reset Delay Time
The Reset Delay Time trd is fix defined according to Table 8.
Table 8
Reset DelayTime
Reset delay timing
trd
fix
16.5 ms
Power-On Reset Delay Time
The power-on reset delay time is defined by the parameter trd and allows a microcontroller and oscillator to start
up. This delay time is the time period from exceeding the upper reset switching threshold VRT,high until the reset is
released by switching the reset output “RO” from “LOW” to “HIGH”.
Undervoltage Reset Delay Time
Unlike the power-on reset delay time, the undervoltage reset delay time is defined by the parameter trd and
considers an output undervoltage event where the output voltage VQ trigger the VRT,low threshold.
Reset Blanking Time
The reset blanking time trr,blank avoids that short undervoltage spikes trigger an unwanted reset “low” signal.
Data Sheet
20
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
Reset Reaction Time
In case the output voltage of the regulator drops below the output undervoltage lower reset threshold VRT,low, the
reset output “RO” is set to low, after the delay of the internal reset reaction time trr,int. The reset blanking time trr,blank
is part of the reset reaction time trr,int
.
Reset Output “RO”
The reset output “RO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic “RO”
signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the maximum “RO” sink
current is limited, the minimum value of the optional external resistor “RRO,ext” is given in Table “Reset Output
RO” on Page 22.
Reset Output “RO” Low for VQ ≥ 1 V
In case of an undervoltage reset condition reset output “RO” is held “low” for VQ ≥ 1 V, even if the input “I” is not
supplied and the voltage VI drops below 1 V. This is achieved by supplying the reset circuit from the output
capacitor.
VI
t
t < trr,blank
VQ
VRH
VRT,high
VRT,low
1 V
t
trd
trr,int
trd
trr,int
trd
trr,int
VRO
trd
1V
VRO,low
t
Thermal
Shutdown
Input
Voltage Dip
Under-
voltage
Spike at Over-
output load
Figure 7
Typical Timing Diagram Reset
Data Sheet
21
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
Table 9
Electrical Characteristics Reset
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Output Undervoltage Reset 5V Version only
Output Undervoltage Reset Upper VRT,high
Switching Threshold
4.6
4.5
60
4.7
4.6
100
4.8
4.7
–
V
VQ increasing
P_5.7.1
P_5.7.2
P_5.7.3
P_5.7.4
Output Undervoltage Reset Lower VRT,low
Switching Threshold - Default
V
VQ decreasing
Output Undervoltage Reset
Switching Hysteresis
VRT,hy
VRH
mV
mV
–
–
Output Undervoltage Reset
200 400
–
Headroom VQ - VRT
Output Undervoltage Reset 3V3 Version only
Output Undervoltage Reset Upper VRT,high
Switching Threshold
3.08 3.15 3.22
V
VQ increasing
P_5.7.5
P_5.7.6
P_5.7.7
P_5.7.8
Output Undervoltage Reset Lower VRT,low
Switching Threshold - Default
3.0
60
3.05 3.13
V
VQ decreasing
Output Undervoltage Reset
Switching Hysteresis
VRT,hy
VRH
100
–
–
mV
mV
–
–
Output Undervoltage Reset
100 250
Headroom VQ - VRT
Reset Output RO
Reset Output Low Voltage
VRO,low
–
0.2
0.4
V
1 V ≤ VQ ≤ VRT;
P_5.7.40
R
RO ≥ 5.1 kΩ
Reset Output
Internal Pull-Up Resistor
RRO,int
RRO,ext
13
20
–
36
–
kΩ
kΩ
internally connected to Q P_5.7.41
Reset Output External
Pull-up Resistor to VQ
5.1
1 V ≤ VQ ≤ VRT
RO ≤ 0.4 V
;
P_5.7.42
V
Reset Delay Timing
Reset Delay Time
trd
13.2 16.5 19.8 ms
Fixed Timing
P_5.7.44
P_5.7.22
P_5.7.46
P_5.7.23
P_5.7.36
Reset blanking time
trr,blank
trr,blank
trr,int
–
–
–
–
6
–
µs
µs
µs
µs
1) for VQ,nom = 3.3 V
2) for VQ,nom = 5 V
for VQ,nom = 3.3 V
for VQ,nom = 5 V
Reset blanking time
7
–
Internal Reset Reaction Time
Internal Reset Reaction Time
7
20
33
trr,int
10
1) Not subject to production test, specified by design.
2) Not subject to production test, specified by design.
Data Sheet
22
Rev. 1.0, 2016-10-07
TLS850D0TE
Block Description and Electrical Characteristics
5.8
Typical Performance Characteristics Reset
Typical Performance Characteristics
Undervoltage Reset Threshold VRT versus
Junction Temperature Tj (3.3 V version)
Undervoltage Reset Threshold VRT versus
Junction Temperature Tj (5 V version)
3.5
3.4
3.3
3.2
3.1
3
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
2.9
2.8
IQ = 1 mA
IQ = 1 mA
2.7
4.2
V
Q = 3.3 V
VRT, high
VRT, low
V
Q = 5 V
VRT, high
VRT, low
2.6
2.5
4.1
4
0
50
100
150
0
50
100
150
Tj [°C]
Tj [°C]
Power On Reset Delay Time trd versus
Junction Temperature Tj
Internal Reset Reaction Time trr,int versus
Junction Temperature Tj
20
25
20
15
10
5
VQ = 3.3 V
VQ = 5 V
18
16
14
12
10
8
6
4
2
0
−40
0
50
100
150
0
50
Tj [°C]
100
150
Tj [°C]
Data Sheet
23
Rev. 1.0, 2016-10-07
TLS850D0TE
Application Information
6
Application Information
6.1
Application Diagram
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Supply
Regulated Output Voltage
I
Q
Load
e. g.
Micro
Controller
XC22xx
DI1
Current
Limitation
RO
Reset
EN
DI2
CI2
CI1
CQ
1µF
100nF
<45V
47µF
Enable
Bandgap
Reference
Temperature
Shutdown
GND
GND
e.g. Ignition
Figure 8
Application Diagram
Note:This is a very simplified example of an application circuit. The function must be verified in the real application.
6.2
Selection of External Components
6.2.1
Input Pin
The typical input circuitry for a linear voltage regulator is shown in the application diagram above.
A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency
disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin
of the linear voltage regulator on the PCB.
An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth
out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear
voltage regulator on the PCB.
An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating
of the linear voltage regulator and protect the device against any damage due to over-voltage.
The external components at the input are not mandatory for the operation of the voltage regulator, but they are
recommended in case of possible external disturbances.
6.2.2
Output Pin
An output capacitor is mandatory for the stability of linear voltage regulators.
The requirement to the output capacitor is given in “Functional Range” on Page 8. The graph “Output
Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15 shows the stable operation range
of the device.
Data Sheet
24
Rev. 1.0, 2016-10-07
TLS850D0TE
Application Information
TLS850D0TE is designed to be also stable with low ESR capacitors. According to the automotive requirements,
ceramic capacitors with X5R or X7R dielectrics are recommended.
The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the
same side of the PCB as the regulator itself.
In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance
and verified in the real application that the output stability requirements are fulfilled.
6.3
Thermal Considerations
Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation
can be calculated:
PD = (VI - VQ) × IQ + VI × Iq
(1)
with
•
•
•
•
•
PD: continuous power dissipation
VI : input voltage
VQ: output voltage
IQ: output current
Iq: quiescent current
The maximum acceptable thermal resistance RthJA can then be calculated:
RthJA,max = ( Tj,max - Ta ) / PD
(2)
with
•
•
T
j,max: maximum allowed junction temperature
Ta: ambient temperature
Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with
reference to the specification in “Thermal Resistance” on Page 9.
Example
Application conditions:
VI = 13.5 V
VQ = 5 V
IQ = 175 mA
Ta = 85 °C
Calculation of RthJA,max
:
PD = (VI – VQ) × IQ + VI × Iq
= (13.5 V – 5 V) × 175 mA
= 1.487 W
(VI × Iq can be neglected because of very low Iq)
RthJA,max = (Tj,max – Ta) / PD
= (150 °C – 85 °C) / 1.487 W = 43.71 K/W
Data Sheet
25
Rev. 1.0, 2016-10-07
TLS850D0TE
Application Information
As a result, the PCB design must ensure a thermal resistance RthJA lower than 43.71 K/W. According to “Thermal
Resistance” on Page 9, at least 600 mm2 heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board
can be used to ensure a proper cooling for the TLS850D0TE in package.
6.4
Reverse Polarity Protection
TLS850D0TE is not self protected against reverse polarity faults and must be protected by external components
against negative supply voltage. An external reverse polarity diode is needed. The absolute maximum ratings of
the device as specified in “Absolute Maximum Ratings” on Page 7 must be kept.
6.5
Further Application Information
•
For further information you may contact http://www.infineon.com/
Data Sheet
26
Rev. 1.0, 2016-10-07
TLS850D0TE
Package Outlines
7
Package Outlines
+0.15
-0.05
6.5
A
+0.05
-0.10
5.7 MAX.1)
2.3
+0.08
-0.04
B
(5)
0.5
+0.20
-0.01
0.9
0...0.15
0.15 MAX.
per side
+0.08
±0.1
5 x 0.6
1.14
0.5
-0.04
0.1 B
4.56
M
0.25
A B
1) Includes mold flashes on each side.
All metal surfaces tin plated, except area of cut.
Figure 9
PG-TO252-5
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Data Sheet
27
Rev. 1.0, 2016-10-07
TLS850D0TE
Revision History
8
Revision History
Revision
Date
Changes
Data Sheet - Initial version
1.0
2016-10-07
Data Sheet
28
Rev. 1.0, 2016-10-07
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, LITIX™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,
UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of
Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay
Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association
Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave
Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of
Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
www.infineon.com
Edition 2016-10-07
Published by
Infineon Technologies AG
81726 Munich, Germany
Legal Disclaimer
The information given in this document shall in
no event be regarded as
Warnings
Due to technical requirements, components
may contain dangerous substances. For
information on the types in question, please
contact the nearest Infineon Technologies
Office. Infineon Technologies components may
be used in life-support devices or systems only
with the express written approval of Infineon
Technologies, if a failure of such components
can reasonably be expected to cause the failure
of that life-support device or system or to affect
the safety or effectiveness of that device or
system. Life support devices or systems are
intended to be implanted in the human body or
to support and/or maintain and sustain and/or
protect human life. If they fail, it is reasonable to
assume that the health of the user or other
persons may be endangered.
a guarantee of
conditions or characteristics. With respect to any
examples or hints given herein, any typical
values stated herein and/or any information
regarding the application of the device, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation, warranties of non-
infringement of intellectual property rights of
any third party.
© 2016 Infineon Technologies AG.
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For further information on technology, delivery
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相关型号:
TLS850F0TA V33
TLS850F0TAV33 是一款高性能的极低压差线性稳压器,采用 PGTO263-7 封装,适用于 3.3 V 电源。这些稳压器的输入电压范围为 3 V 至 40 V,静态电流极低(仅 40μA),非常适合汽车或永久连接电池的任何其他电源系统。TLS850F0TAV33 的输出电压精度为 2%,最大输出电流高达 500 mA。新的回路概念结合了快速调节和非常好的稳定性,输出端只需要一个 1μF 的小型陶瓷电容即可。在低于 100 mA 的电流下,该设备的典型压差非常低,仅 80 mV。工作范围从仅 3 V 的输入电压开始(扩展工作范围)。因此,TLS850F0TAV33 也适用于需要在启动条件下运行的汽车系统。
INFINEON
TLS850F0TAV33
Fixed Positive LDO Regulator, 3.3V, 0.43V Dropout, PSSO7, GREEN, PLASTIC, TO-263, 7 PIN
INFINEON
TLS850F0TAV33ATMA1
Fixed Positive LDO Regulator, 3.3V, 0.43V Dropout, PSSO7, GREEN, PLASTIC, TO-263, 7 PIN
INFINEON
TLS850F0TAV50
Fixed Positive LDO Regulator, 5V, 0.425V Dropout, PSSO7, GREEN, PLASTIC, TO-263, 7 PIN
INFINEON
TLS850F0TAV50ATMA1
Fixed Positive LDO Regulator, 5V, 0.425V Dropout, PSSO7, GREEN, PLASTIC, TO-263, 7 PIN
INFINEON
TLS857J008C1F
CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 8V, 850uF, THROUGH HOLE MOUNT, AXIAL LEADED
VISHAY
TLS857M008C1F
CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 8V, 850uF, THROUGH HOLE MOUNT, AXIAL LEADED
VISHAY
TLS866J100C1F
CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 100V, 86uF, THROUGH HOLE MOUNT, AXIAL LEADED
VISHAY
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